2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005 Broadcom Corporation.
10 * Copyright (C) 2000-2003 Broadcom Corporation.
13 #include <linux/config.h>
15 #include <linux/module.h>
16 #include <linux/moduleparam.h>
17 #include <linux/kernel.h>
18 #include <linux/types.h>
19 #include <linux/compiler.h>
20 #include <linux/slab.h>
21 #include <linux/delay.h>
22 #include <linux/init.h>
23 #include <linux/ioport.h>
24 #include <linux/pci.h>
25 #include <linux/netdevice.h>
26 #include <linux/etherdevice.h>
27 #include <linux/skbuff.h>
28 #include <linux/ethtool.h>
29 #include <linux/mii.h>
30 #include <linux/if_vlan.h>
32 #include <linux/tcp.h>
33 #include <linux/workqueue.h>
35 #include <net/checksum.h>
37 #include <asm/system.h>
39 #include <asm/byteorder.h>
40 #include <asm/uaccess.h>
43 #include <asm/idprom.h>
44 #include <asm/oplib.h>
48 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
49 #define TG3_VLAN_TAG_USED 1
51 #define TG3_VLAN_TAG_USED 0
55 #define TG3_TSO_SUPPORT 1
57 #define TG3_TSO_SUPPORT 0
62 #define DRV_MODULE_NAME "tg3"
63 #define PFX DRV_MODULE_NAME ": "
64 #define DRV_MODULE_VERSION "3.27"
65 #define DRV_MODULE_RELDATE "May 5, 2005"
67 #define TG3_DEF_MAC_MODE 0
68 #define TG3_DEF_RX_MODE 0
69 #define TG3_DEF_TX_MODE 0
70 #define TG3_DEF_MSG_ENABLE \
80 /* length of time before we decide the hardware is borked,
81 * and dev->tx_timeout() should be called to fix the problem
83 #define TG3_TX_TIMEOUT (5 * HZ)
85 /* hardware minimum and maximum for a single frame's data payload */
86 #define TG3_MIN_MTU 60
87 #define TG3_MAX_MTU(tp) \
88 (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 9000 : 1500)
90 /* These numbers seem to be hard coded in the NIC firmware somehow.
91 * You can't change the ring sizes, but you can change where you place
92 * them in the NIC onboard memory.
94 #define TG3_RX_RING_SIZE 512
95 #define TG3_DEF_RX_RING_PENDING 200
96 #define TG3_RX_JUMBO_RING_SIZE 256
97 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
99 /* Do not place this n-ring entries value into the tp struct itself,
100 * we really want to expose these constants to GCC so that modulo et
101 * al. operations are done with shifts and masks instead of with
102 * hw multiply/modulo instructions. Another solution would be to
103 * replace things like '% foo' with '& (foo - 1)'.
105 #define TG3_RX_RCB_RING_SIZE(tp) \
106 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
108 #define TG3_TX_RING_SIZE 512
109 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
111 #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
113 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
114 TG3_RX_JUMBO_RING_SIZE)
115 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
116 TG3_RX_RCB_RING_SIZE(tp))
117 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
119 #define TX_RING_GAP(TP) \
120 (TG3_TX_RING_SIZE - (TP)->tx_pending)
121 #define TX_BUFFS_AVAIL(TP) \
122 (((TP)->tx_cons <= (TP)->tx_prod) ? \
123 (TP)->tx_cons + (TP)->tx_pending - (TP)->tx_prod : \
124 (TP)->tx_cons - (TP)->tx_prod - TX_RING_GAP(TP))
125 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
127 #define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
128 #define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
130 /* minimum number of free TX descriptors required to wake up TX process */
131 #define TG3_TX_WAKEUP_THRESH (TG3_TX_RING_SIZE / 4)
133 /* number of ETHTOOL_GSTATS u64's */
134 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
136 static char version
[] __devinitdata
=
137 DRV_MODULE_NAME
".c:v" DRV_MODULE_VERSION
" (" DRV_MODULE_RELDATE
")\n";
139 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
140 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
141 MODULE_LICENSE("GPL");
142 MODULE_VERSION(DRV_MODULE_VERSION
);
144 static int tg3_debug
= -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
145 module_param(tg3_debug
, int, 0);
146 MODULE_PARM_DESC(tg3_debug
, "Tigon3 bitmapped debugging message enable value");
148 static struct pci_device_id tg3_pci_tbl
[] = {
149 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5700
,
150 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
151 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5701
,
152 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
153 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702
,
154 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
155 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5703
,
156 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
157 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5704
,
158 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
159 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702FE
,
160 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
161 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705
,
162 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
163 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705_2
,
164 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
165 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705M
,
166 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
167 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705M_2
,
168 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
169 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702X
,
170 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
171 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5703X
,
172 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
173 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5704S
,
174 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
175 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702A3
,
176 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
177 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5703A3
,
178 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
179 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5782
,
180 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
181 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5788
,
182 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
183 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5789
,
184 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
185 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5901
,
186 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
187 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5901_2
,
188 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
189 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5704S_2
,
190 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
191 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705F
,
192 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
193 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5720
,
194 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
195 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5721
,
196 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
197 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5750
,
198 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
199 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5751
,
200 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
201 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5750M
,
202 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
203 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5751M
,
204 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
205 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5751F
,
206 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
207 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5752
,
208 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
209 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5753
,
210 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
211 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5753M
,
212 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
213 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5753F
,
214 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
215 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5781
,
216 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
217 { PCI_VENDOR_ID_SYSKONNECT
, PCI_DEVICE_ID_SYSKONNECT_9DXX
,
218 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
219 { PCI_VENDOR_ID_SYSKONNECT
, PCI_DEVICE_ID_SYSKONNECT_9MXX
,
220 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
221 { PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC1000
,
222 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
223 { PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC1001
,
224 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
225 { PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC1003
,
226 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
227 { PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC9100
,
228 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
229 { PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_TIGON3
,
230 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
234 MODULE_DEVICE_TABLE(pci
, tg3_pci_tbl
);
237 const char string
[ETH_GSTRING_LEN
];
238 } ethtool_stats_keys
[TG3_NUM_STATS
] = {
241 { "rx_ucast_packets" },
242 { "rx_mcast_packets" },
243 { "rx_bcast_packets" },
245 { "rx_align_errors" },
246 { "rx_xon_pause_rcvd" },
247 { "rx_xoff_pause_rcvd" },
248 { "rx_mac_ctrl_rcvd" },
249 { "rx_xoff_entered" },
250 { "rx_frame_too_long_errors" },
252 { "rx_undersize_packets" },
253 { "rx_in_length_errors" },
254 { "rx_out_length_errors" },
255 { "rx_64_or_less_octet_packets" },
256 { "rx_65_to_127_octet_packets" },
257 { "rx_128_to_255_octet_packets" },
258 { "rx_256_to_511_octet_packets" },
259 { "rx_512_to_1023_octet_packets" },
260 { "rx_1024_to_1522_octet_packets" },
261 { "rx_1523_to_2047_octet_packets" },
262 { "rx_2048_to_4095_octet_packets" },
263 { "rx_4096_to_8191_octet_packets" },
264 { "rx_8192_to_9022_octet_packets" },
271 { "tx_flow_control" },
273 { "tx_single_collisions" },
274 { "tx_mult_collisions" },
276 { "tx_excessive_collisions" },
277 { "tx_late_collisions" },
278 { "tx_collide_2times" },
279 { "tx_collide_3times" },
280 { "tx_collide_4times" },
281 { "tx_collide_5times" },
282 { "tx_collide_6times" },
283 { "tx_collide_7times" },
284 { "tx_collide_8times" },
285 { "tx_collide_9times" },
286 { "tx_collide_10times" },
287 { "tx_collide_11times" },
288 { "tx_collide_12times" },
289 { "tx_collide_13times" },
290 { "tx_collide_14times" },
291 { "tx_collide_15times" },
292 { "tx_ucast_packets" },
293 { "tx_mcast_packets" },
294 { "tx_bcast_packets" },
295 { "tx_carrier_sense_errors" },
299 { "dma_writeq_full" },
300 { "dma_write_prioq_full" },
304 { "rx_threshold_hit" },
306 { "dma_readq_full" },
307 { "dma_read_prioq_full" },
308 { "tx_comp_queue_full" },
310 { "ring_set_send_prod_index" },
311 { "ring_status_update" },
313 { "nic_avoided_irqs" },
314 { "nic_tx_threshold_hit" }
317 static void tg3_write_indirect_reg32(struct tg3
*tp
, u32 off
, u32 val
)
319 if ((tp
->tg3_flags
& TG3_FLAG_PCIX_TARGET_HWBUG
) != 0) {
322 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
323 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
);
324 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, val
);
325 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
327 writel(val
, tp
->regs
+ off
);
328 if ((tp
->tg3_flags
& TG3_FLAG_5701_REG_WRITE_BUG
) != 0)
329 readl(tp
->regs
+ off
);
333 static void _tw32_flush(struct tg3
*tp
, u32 off
, u32 val
)
335 if ((tp
->tg3_flags
& TG3_FLAG_PCIX_TARGET_HWBUG
) != 0) {
338 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
339 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
);
340 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, val
);
341 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
343 void __iomem
*dest
= tp
->regs
+ off
;
345 readl(dest
); /* always flush PCI write */
349 static inline void _tw32_rx_mbox(struct tg3
*tp
, u32 off
, u32 val
)
351 void __iomem
*mbox
= tp
->regs
+ off
;
353 if (tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
)
357 static inline void _tw32_tx_mbox(struct tg3
*tp
, u32 off
, u32 val
)
359 void __iomem
*mbox
= tp
->regs
+ off
;
361 if (tp
->tg3_flags
& TG3_FLAG_TXD_MBOX_HWBUG
)
363 if (tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
)
367 #define tw32_mailbox(reg, val) writel(((val) & 0xffffffff), tp->regs + (reg))
368 #define tw32_rx_mbox(reg, val) _tw32_rx_mbox(tp, reg, val)
369 #define tw32_tx_mbox(reg, val) _tw32_tx_mbox(tp, reg, val)
371 #define tw32(reg,val) tg3_write_indirect_reg32(tp,(reg),(val))
372 #define tw32_f(reg,val) _tw32_flush(tp,(reg),(val))
373 #define tw16(reg,val) writew(((val) & 0xffff), tp->regs + (reg))
374 #define tw8(reg,val) writeb(((val) & 0xff), tp->regs + (reg))
375 #define tr32(reg) readl(tp->regs + (reg))
376 #define tr16(reg) readw(tp->regs + (reg))
377 #define tr8(reg) readb(tp->regs + (reg))
379 static void tg3_write_mem(struct tg3
*tp
, u32 off
, u32 val
)
383 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
384 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, off
);
385 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_DATA
, val
);
387 /* Always leave this as zero. */
388 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, 0);
389 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
392 static void tg3_read_mem(struct tg3
*tp
, u32 off
, u32
*val
)
396 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
397 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, off
);
398 pci_read_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_DATA
, val
);
400 /* Always leave this as zero. */
401 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, 0);
402 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
405 static void tg3_disable_ints(struct tg3
*tp
)
407 tw32(TG3PCI_MISC_HOST_CTRL
,
408 (tp
->misc_host_ctrl
| MISC_HOST_CTRL_MASK_PCI_INT
));
409 tw32_mailbox(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0x00000001);
410 tr32(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
);
413 static inline void tg3_cond_int(struct tg3
*tp
)
415 if (tp
->hw_status
->status
& SD_STATUS_UPDATED
)
416 tw32(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
| GRC_LCLCTRL_SETINT
);
419 static void tg3_enable_ints(struct tg3
*tp
)
421 tw32(TG3PCI_MISC_HOST_CTRL
,
422 (tp
->misc_host_ctrl
& ~MISC_HOST_CTRL_MASK_PCI_INT
));
423 tw32_mailbox(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
,
424 (tp
->last_tag
<< 24));
425 tr32(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
);
430 static inline unsigned int tg3_has_work(struct tg3
*tp
)
432 struct tg3_hw_status
*sblk
= tp
->hw_status
;
433 unsigned int work_exists
= 0;
435 /* check for phy events */
436 if (!(tp
->tg3_flags
&
437 (TG3_FLAG_USE_LINKCHG_REG
|
438 TG3_FLAG_POLL_SERDES
))) {
439 if (sblk
->status
& SD_STATUS_LINK_CHG
)
442 /* check for RX/TX work to do */
443 if (sblk
->idx
[0].tx_consumer
!= tp
->tx_cons
||
444 sblk
->idx
[0].rx_producer
!= tp
->rx_rcb_ptr
)
451 * similar to tg3_enable_ints, but it accurately determines whether there
452 * is new work pending and can return without flushing the PIO write
453 * which reenables interrupts
455 static void tg3_restart_ints(struct tg3
*tp
)
457 tw32(TG3PCI_MISC_HOST_CTRL
,
458 (tp
->misc_host_ctrl
& ~MISC_HOST_CTRL_MASK_PCI_INT
));
459 tw32_mailbox(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
,
463 /* When doing tagged status, this work check is unnecessary.
464 * The last_tag we write above tells the chip which piece of
465 * work we've completed.
467 if (!(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) &&
469 tw32(HOSTCC_MODE
, tp
->coalesce_mode
|
470 (HOSTCC_MODE_ENABLE
| HOSTCC_MODE_NOW
));
473 static inline void tg3_netif_stop(struct tg3
*tp
)
475 netif_poll_disable(tp
->dev
);
476 netif_tx_disable(tp
->dev
);
479 static inline void tg3_netif_start(struct tg3
*tp
)
481 netif_wake_queue(tp
->dev
);
482 /* NOTE: unconditional netif_wake_queue is only appropriate
483 * so long as all callers are assured to have free tx slots
484 * (such as after tg3_init_hw)
486 netif_poll_enable(tp
->dev
);
490 static void tg3_switch_clocks(struct tg3
*tp
)
492 u32 clock_ctrl
= tr32(TG3PCI_CLOCK_CTRL
);
495 orig_clock_ctrl
= clock_ctrl
;
496 clock_ctrl
&= (CLOCK_CTRL_FORCE_CLKRUN
|
497 CLOCK_CTRL_CLKRUN_OENABLE
|
499 tp
->pci_clock_ctrl
= clock_ctrl
;
501 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
502 if (orig_clock_ctrl
& CLOCK_CTRL_625_CORE
) {
503 tw32_f(TG3PCI_CLOCK_CTRL
,
504 clock_ctrl
| CLOCK_CTRL_625_CORE
);
507 } else if ((orig_clock_ctrl
& CLOCK_CTRL_44MHZ_CORE
) != 0) {
508 tw32_f(TG3PCI_CLOCK_CTRL
,
510 (CLOCK_CTRL_44MHZ_CORE
| CLOCK_CTRL_ALTCLK
));
512 tw32_f(TG3PCI_CLOCK_CTRL
,
513 clock_ctrl
| (CLOCK_CTRL_ALTCLK
));
516 tw32_f(TG3PCI_CLOCK_CTRL
, clock_ctrl
);
520 #define PHY_BUSY_LOOPS 5000
522 static int tg3_readphy(struct tg3
*tp
, int reg
, u32
*val
)
528 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
530 (tp
->mi_mode
& ~MAC_MI_MODE_AUTO_POLL
));
536 frame_val
= ((PHY_ADDR
<< MI_COM_PHY_ADDR_SHIFT
) &
537 MI_COM_PHY_ADDR_MASK
);
538 frame_val
|= ((reg
<< MI_COM_REG_ADDR_SHIFT
) &
539 MI_COM_REG_ADDR_MASK
);
540 frame_val
|= (MI_COM_CMD_READ
| MI_COM_START
);
542 tw32_f(MAC_MI_COM
, frame_val
);
544 loops
= PHY_BUSY_LOOPS
;
547 frame_val
= tr32(MAC_MI_COM
);
549 if ((frame_val
& MI_COM_BUSY
) == 0) {
551 frame_val
= tr32(MAC_MI_COM
);
559 *val
= frame_val
& MI_COM_DATA_MASK
;
563 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
564 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
571 static int tg3_writephy(struct tg3
*tp
, int reg
, u32 val
)
577 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
579 (tp
->mi_mode
& ~MAC_MI_MODE_AUTO_POLL
));
583 frame_val
= ((PHY_ADDR
<< MI_COM_PHY_ADDR_SHIFT
) &
584 MI_COM_PHY_ADDR_MASK
);
585 frame_val
|= ((reg
<< MI_COM_REG_ADDR_SHIFT
) &
586 MI_COM_REG_ADDR_MASK
);
587 frame_val
|= (val
& MI_COM_DATA_MASK
);
588 frame_val
|= (MI_COM_CMD_WRITE
| MI_COM_START
);
590 tw32_f(MAC_MI_COM
, frame_val
);
592 loops
= PHY_BUSY_LOOPS
;
595 frame_val
= tr32(MAC_MI_COM
);
596 if ((frame_val
& MI_COM_BUSY
) == 0) {
598 frame_val
= tr32(MAC_MI_COM
);
608 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
609 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
616 static void tg3_phy_set_wirespeed(struct tg3
*tp
)
620 if (tp
->tg3_flags2
& TG3_FLG2_NO_ETH_WIRE_SPEED
)
623 if (!tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x7007) &&
624 !tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &val
))
625 tg3_writephy(tp
, MII_TG3_AUX_CTRL
,
626 (val
| (1 << 15) | (1 << 4)));
629 static int tg3_bmcr_reset(struct tg3
*tp
)
634 /* OK, reset it, and poll the BMCR_RESET bit until it
635 * clears or we time out.
637 phy_control
= BMCR_RESET
;
638 err
= tg3_writephy(tp
, MII_BMCR
, phy_control
);
644 err
= tg3_readphy(tp
, MII_BMCR
, &phy_control
);
648 if ((phy_control
& BMCR_RESET
) == 0) {
660 static int tg3_wait_macro_done(struct tg3
*tp
)
667 if (!tg3_readphy(tp
, 0x16, &tmp32
)) {
668 if ((tmp32
& 0x1000) == 0)
678 static int tg3_phy_write_and_check_testpat(struct tg3
*tp
, int *resetp
)
680 static const u32 test_pat
[4][6] = {
681 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
682 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
683 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
684 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
688 for (chan
= 0; chan
< 4; chan
++) {
691 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
692 (chan
* 0x2000) | 0x0200);
693 tg3_writephy(tp
, 0x16, 0x0002);
695 for (i
= 0; i
< 6; i
++)
696 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
,
699 tg3_writephy(tp
, 0x16, 0x0202);
700 if (tg3_wait_macro_done(tp
)) {
705 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
706 (chan
* 0x2000) | 0x0200);
707 tg3_writephy(tp
, 0x16, 0x0082);
708 if (tg3_wait_macro_done(tp
)) {
713 tg3_writephy(tp
, 0x16, 0x0802);
714 if (tg3_wait_macro_done(tp
)) {
719 for (i
= 0; i
< 6; i
+= 2) {
722 if (tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &low
) ||
723 tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &high
) ||
724 tg3_wait_macro_done(tp
)) {
730 if (low
!= test_pat
[chan
][i
] ||
731 high
!= test_pat
[chan
][i
+1]) {
732 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x000b);
733 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x4001);
734 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x4005);
744 static int tg3_phy_reset_chanpat(struct tg3
*tp
)
748 for (chan
= 0; chan
< 4; chan
++) {
751 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
752 (chan
* 0x2000) | 0x0200);
753 tg3_writephy(tp
, 0x16, 0x0002);
754 for (i
= 0; i
< 6; i
++)
755 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x000);
756 tg3_writephy(tp
, 0x16, 0x0202);
757 if (tg3_wait_macro_done(tp
))
764 static int tg3_phy_reset_5703_4_5(struct tg3
*tp
)
766 u32 reg32
, phy9_orig
;
767 int retries
, do_phy_reset
, err
;
773 err
= tg3_bmcr_reset(tp
);
779 /* Disable transmitter and interrupt. */
780 if (tg3_readphy(tp
, MII_TG3_EXT_CTRL
, ®32
))
784 tg3_writephy(tp
, MII_TG3_EXT_CTRL
, reg32
);
786 /* Set full-duplex, 1000 mbps. */
787 tg3_writephy(tp
, MII_BMCR
,
788 BMCR_FULLDPLX
| TG3_BMCR_SPEED1000
);
790 /* Set to master mode. */
791 if (tg3_readphy(tp
, MII_TG3_CTRL
, &phy9_orig
))
794 tg3_writephy(tp
, MII_TG3_CTRL
,
795 (MII_TG3_CTRL_AS_MASTER
|
796 MII_TG3_CTRL_ENABLE_AS_MASTER
));
798 /* Enable SM_DSP_CLOCK and 6dB. */
799 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
801 /* Block the PHY control access. */
802 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8005);
803 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0800);
805 err
= tg3_phy_write_and_check_testpat(tp
, &do_phy_reset
);
810 err
= tg3_phy_reset_chanpat(tp
);
814 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8005);
815 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0000);
817 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8200);
818 tg3_writephy(tp
, 0x16, 0x0000);
820 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
821 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
822 /* Set Extended packet length bit for jumbo frames */
823 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4400);
826 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
829 tg3_writephy(tp
, MII_TG3_CTRL
, phy9_orig
);
831 if (!tg3_readphy(tp
, MII_TG3_EXT_CTRL
, ®32
)) {
833 tg3_writephy(tp
, MII_TG3_EXT_CTRL
, reg32
);
840 /* This will reset the tigon3 PHY if there is no valid
841 * link unless the FORCE argument is non-zero.
843 static int tg3_phy_reset(struct tg3
*tp
)
848 err
= tg3_readphy(tp
, MII_BMSR
, &phy_status
);
849 err
|= tg3_readphy(tp
, MII_BMSR
, &phy_status
);
853 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
854 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
855 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
856 err
= tg3_phy_reset_5703_4_5(tp
);
862 err
= tg3_bmcr_reset(tp
);
867 if (tp
->tg3_flags2
& TG3_FLG2_PHY_ADC_BUG
) {
868 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
869 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x201f);
870 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x2aaa);
871 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x000a);
872 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0323);
873 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
875 if (tp
->tg3_flags2
& TG3_FLG2_PHY_5704_A0_BUG
) {
876 tg3_writephy(tp
, 0x1c, 0x8d68);
877 tg3_writephy(tp
, 0x1c, 0x8d68);
879 if (tp
->tg3_flags2
& TG3_FLG2_PHY_BER_BUG
) {
880 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
881 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x000a);
882 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x310b);
883 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x201f);
884 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x9506);
885 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x401f);
886 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x14e2);
887 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
889 /* Set Extended packet length bit (bit 14) on all chips that */
890 /* support jumbo frames */
891 if ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5401
) {
892 /* Cannot do read-modify-write on 5401 */
893 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4c20);
894 } else if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
897 /* Set bit 14 with read-modify-write to preserve other bits */
898 if (!tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0007) &&
899 !tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &phy_reg
))
900 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy_reg
| 0x4000);
903 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
904 * jumbo frames transmission.
906 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
909 if (!tg3_readphy(tp
, MII_TG3_EXT_CTRL
, &phy_reg
))
910 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
911 phy_reg
| MII_TG3_EXT_CTRL_FIFO_ELASTIC
);
914 tg3_phy_set_wirespeed(tp
);
918 static void tg3_frob_aux_power(struct tg3
*tp
)
920 struct tg3
*tp_peer
= tp
;
922 if ((tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
) != 0)
925 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
926 tp_peer
= pci_get_drvdata(tp
->pdev_peer
);
932 if ((tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
) != 0 ||
933 (tp_peer
->tg3_flags
& TG3_FLAG_WOL_ENABLE
) != 0) {
934 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
935 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
936 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
937 (GRC_LCLCTRL_GPIO_OE0
|
938 GRC_LCLCTRL_GPIO_OE1
|
939 GRC_LCLCTRL_GPIO_OE2
|
940 GRC_LCLCTRL_GPIO_OUTPUT0
|
941 GRC_LCLCTRL_GPIO_OUTPUT1
));
948 (tp_peer
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
) != 0)
951 /* On 5753 and variants, GPIO2 cannot be used. */
952 no_gpio2
= tp
->nic_sram_data_cfg
&
953 NIC_SRAM_DATA_CFG_NO_GPIO2
;
955 grc_local_ctrl
= GRC_LCLCTRL_GPIO_OE0
|
956 GRC_LCLCTRL_GPIO_OE1
|
957 GRC_LCLCTRL_GPIO_OE2
|
958 GRC_LCLCTRL_GPIO_OUTPUT1
|
959 GRC_LCLCTRL_GPIO_OUTPUT2
;
961 grc_local_ctrl
&= ~(GRC_LCLCTRL_GPIO_OE2
|
962 GRC_LCLCTRL_GPIO_OUTPUT2
);
964 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
968 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OUTPUT0
;
970 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
975 grc_local_ctrl
&= ~GRC_LCLCTRL_GPIO_OUTPUT2
;
976 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
982 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
983 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
) {
985 (tp_peer
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
) != 0)
988 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
989 (GRC_LCLCTRL_GPIO_OE1
|
990 GRC_LCLCTRL_GPIO_OUTPUT1
));
993 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
994 (GRC_LCLCTRL_GPIO_OE1
));
997 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
998 (GRC_LCLCTRL_GPIO_OE1
|
999 GRC_LCLCTRL_GPIO_OUTPUT1
));
1005 static int tg3_setup_phy(struct tg3
*, int);
1007 #define RESET_KIND_SHUTDOWN 0
1008 #define RESET_KIND_INIT 1
1009 #define RESET_KIND_SUSPEND 2
1011 static void tg3_write_sig_post_reset(struct tg3
*, int);
1012 static int tg3_halt_cpu(struct tg3
*, u32
);
1014 static int tg3_set_power_state(struct tg3
*tp
, int state
)
1017 u16 power_control
, power_caps
;
1018 int pm
= tp
->pm_cap
;
1020 /* Make sure register accesses (indirect or otherwise)
1021 * will function correctly.
1023 pci_write_config_dword(tp
->pdev
,
1024 TG3PCI_MISC_HOST_CTRL
,
1025 tp
->misc_host_ctrl
);
1027 pci_read_config_word(tp
->pdev
,
1030 power_control
|= PCI_PM_CTRL_PME_STATUS
;
1031 power_control
&= ~(PCI_PM_CTRL_STATE_MASK
);
1035 pci_write_config_word(tp
->pdev
,
1038 udelay(100); /* Delay after power state change */
1040 /* Switch out of Vaux if it is not a LOM */
1041 if (!(tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
)) {
1042 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
);
1061 printk(KERN_WARNING PFX
"%s: Invalid power state (%d) "
1063 tp
->dev
->name
, state
);
1067 power_control
|= PCI_PM_CTRL_PME_ENABLE
;
1069 misc_host_ctrl
= tr32(TG3PCI_MISC_HOST_CTRL
);
1070 tw32(TG3PCI_MISC_HOST_CTRL
,
1071 misc_host_ctrl
| MISC_HOST_CTRL_MASK_PCI_INT
);
1073 if (tp
->link_config
.phy_is_low_power
== 0) {
1074 tp
->link_config
.phy_is_low_power
= 1;
1075 tp
->link_config
.orig_speed
= tp
->link_config
.speed
;
1076 tp
->link_config
.orig_duplex
= tp
->link_config
.duplex
;
1077 tp
->link_config
.orig_autoneg
= tp
->link_config
.autoneg
;
1080 if (!(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)) {
1081 tp
->link_config
.speed
= SPEED_10
;
1082 tp
->link_config
.duplex
= DUPLEX_HALF
;
1083 tp
->link_config
.autoneg
= AUTONEG_ENABLE
;
1084 tg3_setup_phy(tp
, 0);
1087 pci_read_config_word(tp
->pdev
, pm
+ PCI_PM_PMC
, &power_caps
);
1089 if (tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
) {
1092 if (!(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)) {
1093 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x5a);
1096 mac_mode
= MAC_MODE_PORT_MODE_MII
;
1098 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
||
1099 !(tp
->tg3_flags
& TG3_FLAG_WOL_SPEED_100MB
))
1100 mac_mode
|= MAC_MODE_LINK_POLARITY
;
1102 mac_mode
= MAC_MODE_PORT_MODE_TBI
;
1105 if (!(tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
))
1106 tw32(MAC_LED_CTRL
, tp
->led_ctrl
);
1108 if (((power_caps
& PCI_PM_CAP_PME_D3cold
) &&
1109 (tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
)))
1110 mac_mode
|= MAC_MODE_MAGIC_PKT_ENABLE
;
1112 tw32_f(MAC_MODE
, mac_mode
);
1115 tw32_f(MAC_RX_MODE
, RX_MODE_ENABLE
);
1119 if (!(tp
->tg3_flags
& TG3_FLAG_WOL_SPEED_100MB
) &&
1120 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
1121 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)) {
1124 base_val
= tp
->pci_clock_ctrl
;
1125 base_val
|= (CLOCK_CTRL_RXCLK_DISABLE
|
1126 CLOCK_CTRL_TXCLK_DISABLE
);
1128 tw32_f(TG3PCI_CLOCK_CTRL
, base_val
|
1130 CLOCK_CTRL_PWRDOWN_PLL133
);
1132 } else if (!((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
1133 (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))) {
1134 u32 newbits1
, newbits2
;
1136 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
1137 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
1138 newbits1
= (CLOCK_CTRL_RXCLK_DISABLE
|
1139 CLOCK_CTRL_TXCLK_DISABLE
|
1141 newbits2
= newbits1
| CLOCK_CTRL_44MHZ_CORE
;
1142 } else if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
1143 newbits1
= CLOCK_CTRL_625_CORE
;
1144 newbits2
= newbits1
| CLOCK_CTRL_ALTCLK
;
1146 newbits1
= CLOCK_CTRL_ALTCLK
;
1147 newbits2
= newbits1
| CLOCK_CTRL_44MHZ_CORE
;
1150 tw32_f(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
| newbits1
);
1153 tw32_f(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
| newbits2
);
1156 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
1159 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
1160 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
1161 newbits3
= (CLOCK_CTRL_RXCLK_DISABLE
|
1162 CLOCK_CTRL_TXCLK_DISABLE
|
1163 CLOCK_CTRL_44MHZ_CORE
);
1165 newbits3
= CLOCK_CTRL_44MHZ_CORE
;
1168 tw32_f(TG3PCI_CLOCK_CTRL
,
1169 tp
->pci_clock_ctrl
| newbits3
);
1174 tg3_frob_aux_power(tp
);
1176 /* Workaround for unstable PLL clock */
1177 if ((GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_AX
) ||
1178 (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_BX
)) {
1179 u32 val
= tr32(0x7d00);
1181 val
&= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1183 if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
1184 tg3_halt_cpu(tp
, RX_CPU_BASE
);
1187 /* Finally, set the new power state. */
1188 pci_write_config_word(tp
->pdev
, pm
+ PCI_PM_CTRL
, power_control
);
1189 udelay(100); /* Delay after power state change */
1191 tg3_write_sig_post_reset(tp
, RESET_KIND_SHUTDOWN
);
1196 static void tg3_link_report(struct tg3
*tp
)
1198 if (!netif_carrier_ok(tp
->dev
)) {
1199 printk(KERN_INFO PFX
"%s: Link is down.\n", tp
->dev
->name
);
1201 printk(KERN_INFO PFX
"%s: Link is up at %d Mbps, %s duplex.\n",
1203 (tp
->link_config
.active_speed
== SPEED_1000
?
1205 (tp
->link_config
.active_speed
== SPEED_100
?
1207 (tp
->link_config
.active_duplex
== DUPLEX_FULL
?
1210 printk(KERN_INFO PFX
"%s: Flow control is %s for TX and "
1213 (tp
->tg3_flags
& TG3_FLAG_TX_PAUSE
) ? "on" : "off",
1214 (tp
->tg3_flags
& TG3_FLAG_RX_PAUSE
) ? "on" : "off");
1218 static void tg3_setup_flow_control(struct tg3
*tp
, u32 local_adv
, u32 remote_adv
)
1220 u32 new_tg3_flags
= 0;
1221 u32 old_rx_mode
= tp
->rx_mode
;
1222 u32 old_tx_mode
= tp
->tx_mode
;
1224 if (tp
->tg3_flags
& TG3_FLAG_PAUSE_AUTONEG
) {
1225 if (local_adv
& ADVERTISE_PAUSE_CAP
) {
1226 if (local_adv
& ADVERTISE_PAUSE_ASYM
) {
1227 if (remote_adv
& LPA_PAUSE_CAP
)
1229 (TG3_FLAG_RX_PAUSE
|
1231 else if (remote_adv
& LPA_PAUSE_ASYM
)
1233 (TG3_FLAG_RX_PAUSE
);
1235 if (remote_adv
& LPA_PAUSE_CAP
)
1237 (TG3_FLAG_RX_PAUSE
|
1240 } else if (local_adv
& ADVERTISE_PAUSE_ASYM
) {
1241 if ((remote_adv
& LPA_PAUSE_CAP
) &&
1242 (remote_adv
& LPA_PAUSE_ASYM
))
1243 new_tg3_flags
|= TG3_FLAG_TX_PAUSE
;
1246 tp
->tg3_flags
&= ~(TG3_FLAG_RX_PAUSE
| TG3_FLAG_TX_PAUSE
);
1247 tp
->tg3_flags
|= new_tg3_flags
;
1249 new_tg3_flags
= tp
->tg3_flags
;
1252 if (new_tg3_flags
& TG3_FLAG_RX_PAUSE
)
1253 tp
->rx_mode
|= RX_MODE_FLOW_CTRL_ENABLE
;
1255 tp
->rx_mode
&= ~RX_MODE_FLOW_CTRL_ENABLE
;
1257 if (old_rx_mode
!= tp
->rx_mode
) {
1258 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
1261 if (new_tg3_flags
& TG3_FLAG_TX_PAUSE
)
1262 tp
->tx_mode
|= TX_MODE_FLOW_CTRL_ENABLE
;
1264 tp
->tx_mode
&= ~TX_MODE_FLOW_CTRL_ENABLE
;
1266 if (old_tx_mode
!= tp
->tx_mode
) {
1267 tw32_f(MAC_TX_MODE
, tp
->tx_mode
);
1271 static void tg3_aux_stat_to_speed_duplex(struct tg3
*tp
, u32 val
, u16
*speed
, u8
*duplex
)
1273 switch (val
& MII_TG3_AUX_STAT_SPDMASK
) {
1274 case MII_TG3_AUX_STAT_10HALF
:
1276 *duplex
= DUPLEX_HALF
;
1279 case MII_TG3_AUX_STAT_10FULL
:
1281 *duplex
= DUPLEX_FULL
;
1284 case MII_TG3_AUX_STAT_100HALF
:
1286 *duplex
= DUPLEX_HALF
;
1289 case MII_TG3_AUX_STAT_100FULL
:
1291 *duplex
= DUPLEX_FULL
;
1294 case MII_TG3_AUX_STAT_1000HALF
:
1295 *speed
= SPEED_1000
;
1296 *duplex
= DUPLEX_HALF
;
1299 case MII_TG3_AUX_STAT_1000FULL
:
1300 *speed
= SPEED_1000
;
1301 *duplex
= DUPLEX_FULL
;
1305 *speed
= SPEED_INVALID
;
1306 *duplex
= DUPLEX_INVALID
;
1311 static void tg3_phy_copper_begin(struct tg3
*tp
)
1316 if (tp
->link_config
.phy_is_low_power
) {
1317 /* Entering low power mode. Disable gigabit and
1318 * 100baseT advertisements.
1320 tg3_writephy(tp
, MII_TG3_CTRL
, 0);
1322 new_adv
= (ADVERTISE_10HALF
| ADVERTISE_10FULL
|
1323 ADVERTISE_CSMA
| ADVERTISE_PAUSE_CAP
);
1324 if (tp
->tg3_flags
& TG3_FLAG_WOL_SPEED_100MB
)
1325 new_adv
|= (ADVERTISE_100HALF
| ADVERTISE_100FULL
);
1327 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
1328 } else if (tp
->link_config
.speed
== SPEED_INVALID
) {
1329 tp
->link_config
.advertising
=
1330 (ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
1331 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
|
1332 ADVERTISED_1000baseT_Half
| ADVERTISED_1000baseT_Full
|
1333 ADVERTISED_Autoneg
| ADVERTISED_MII
);
1335 if (tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)
1336 tp
->link_config
.advertising
&=
1337 ~(ADVERTISED_1000baseT_Half
|
1338 ADVERTISED_1000baseT_Full
);
1340 new_adv
= (ADVERTISE_CSMA
| ADVERTISE_PAUSE_CAP
);
1341 if (tp
->link_config
.advertising
& ADVERTISED_10baseT_Half
)
1342 new_adv
|= ADVERTISE_10HALF
;
1343 if (tp
->link_config
.advertising
& ADVERTISED_10baseT_Full
)
1344 new_adv
|= ADVERTISE_10FULL
;
1345 if (tp
->link_config
.advertising
& ADVERTISED_100baseT_Half
)
1346 new_adv
|= ADVERTISE_100HALF
;
1347 if (tp
->link_config
.advertising
& ADVERTISED_100baseT_Full
)
1348 new_adv
|= ADVERTISE_100FULL
;
1349 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
1351 if (tp
->link_config
.advertising
&
1352 (ADVERTISED_1000baseT_Half
| ADVERTISED_1000baseT_Full
)) {
1354 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Half
)
1355 new_adv
|= MII_TG3_CTRL_ADV_1000_HALF
;
1356 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Full
)
1357 new_adv
|= MII_TG3_CTRL_ADV_1000_FULL
;
1358 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
) &&
1359 (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
1360 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
))
1361 new_adv
|= (MII_TG3_CTRL_AS_MASTER
|
1362 MII_TG3_CTRL_ENABLE_AS_MASTER
);
1363 tg3_writephy(tp
, MII_TG3_CTRL
, new_adv
);
1365 tg3_writephy(tp
, MII_TG3_CTRL
, 0);
1368 /* Asking for a specific link mode. */
1369 if (tp
->link_config
.speed
== SPEED_1000
) {
1370 new_adv
= ADVERTISE_CSMA
| ADVERTISE_PAUSE_CAP
;
1371 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
1373 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
1374 new_adv
= MII_TG3_CTRL_ADV_1000_FULL
;
1376 new_adv
= MII_TG3_CTRL_ADV_1000_HALF
;
1377 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
1378 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
)
1379 new_adv
|= (MII_TG3_CTRL_AS_MASTER
|
1380 MII_TG3_CTRL_ENABLE_AS_MASTER
);
1381 tg3_writephy(tp
, MII_TG3_CTRL
, new_adv
);
1383 tg3_writephy(tp
, MII_TG3_CTRL
, 0);
1385 new_adv
= ADVERTISE_CSMA
| ADVERTISE_PAUSE_CAP
;
1386 if (tp
->link_config
.speed
== SPEED_100
) {
1387 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
1388 new_adv
|= ADVERTISE_100FULL
;
1390 new_adv
|= ADVERTISE_100HALF
;
1392 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
1393 new_adv
|= ADVERTISE_10FULL
;
1395 new_adv
|= ADVERTISE_10HALF
;
1397 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
1401 if (tp
->link_config
.autoneg
== AUTONEG_DISABLE
&&
1402 tp
->link_config
.speed
!= SPEED_INVALID
) {
1403 u32 bmcr
, orig_bmcr
;
1405 tp
->link_config
.active_speed
= tp
->link_config
.speed
;
1406 tp
->link_config
.active_duplex
= tp
->link_config
.duplex
;
1409 switch (tp
->link_config
.speed
) {
1415 bmcr
|= BMCR_SPEED100
;
1419 bmcr
|= TG3_BMCR_SPEED1000
;
1423 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
1424 bmcr
|= BMCR_FULLDPLX
;
1426 if (!tg3_readphy(tp
, MII_BMCR
, &orig_bmcr
) &&
1427 (bmcr
!= orig_bmcr
)) {
1428 tg3_writephy(tp
, MII_BMCR
, BMCR_LOOPBACK
);
1429 for (i
= 0; i
< 1500; i
++) {
1433 if (tg3_readphy(tp
, MII_BMSR
, &tmp
) ||
1434 tg3_readphy(tp
, MII_BMSR
, &tmp
))
1436 if (!(tmp
& BMSR_LSTATUS
)) {
1441 tg3_writephy(tp
, MII_BMCR
, bmcr
);
1445 tg3_writephy(tp
, MII_BMCR
,
1446 BMCR_ANENABLE
| BMCR_ANRESTART
);
1450 static int tg3_init_5401phy_dsp(struct tg3
*tp
)
1454 /* Turn off tap power management. */
1455 /* Set Extended packet length bit */
1456 err
= tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4c20);
1458 err
|= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x0012);
1459 err
|= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x1804);
1461 err
|= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x0013);
1462 err
|= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x1204);
1464 err
|= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8006);
1465 err
|= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0132);
1467 err
|= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8006);
1468 err
|= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0232);
1470 err
|= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x201f);
1471 err
|= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0a20);
1478 static int tg3_copper_is_advertising_all(struct tg3
*tp
)
1480 u32 adv_reg
, all_mask
;
1482 if (tg3_readphy(tp
, MII_ADVERTISE
, &adv_reg
))
1485 all_mask
= (ADVERTISE_10HALF
| ADVERTISE_10FULL
|
1486 ADVERTISE_100HALF
| ADVERTISE_100FULL
);
1487 if ((adv_reg
& all_mask
) != all_mask
)
1489 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)) {
1492 if (tg3_readphy(tp
, MII_TG3_CTRL
, &tg3_ctrl
))
1495 all_mask
= (MII_TG3_CTRL_ADV_1000_HALF
|
1496 MII_TG3_CTRL_ADV_1000_FULL
);
1497 if ((tg3_ctrl
& all_mask
) != all_mask
)
1503 static int tg3_setup_copper_phy(struct tg3
*tp
, int force_reset
)
1505 int current_link_up
;
1514 (MAC_STATUS_SYNC_CHANGED
|
1515 MAC_STATUS_CFG_CHANGED
|
1516 MAC_STATUS_MI_COMPLETION
|
1517 MAC_STATUS_LNKSTATE_CHANGED
));
1520 tp
->mi_mode
= MAC_MI_MODE_BASE
;
1521 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
1524 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x02);
1526 /* Some third-party PHYs need to be reset on link going
1529 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
1530 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
1531 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) &&
1532 netif_carrier_ok(tp
->dev
)) {
1533 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
1534 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
1535 !(bmsr
& BMSR_LSTATUS
))
1541 if ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5401
) {
1542 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
1543 if (tg3_readphy(tp
, MII_BMSR
, &bmsr
) ||
1544 !(tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
))
1547 if (!(bmsr
& BMSR_LSTATUS
)) {
1548 err
= tg3_init_5401phy_dsp(tp
);
1552 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
1553 for (i
= 0; i
< 1000; i
++) {
1555 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
1556 (bmsr
& BMSR_LSTATUS
)) {
1562 if ((tp
->phy_id
& PHY_ID_REV_MASK
) == PHY_REV_BCM5401_B0
&&
1563 !(bmsr
& BMSR_LSTATUS
) &&
1564 tp
->link_config
.active_speed
== SPEED_1000
) {
1565 err
= tg3_phy_reset(tp
);
1567 err
= tg3_init_5401phy_dsp(tp
);
1572 } else if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
1573 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
) {
1574 /* 5701 {A0,B0} CRC bug workaround */
1575 tg3_writephy(tp
, 0x15, 0x0a75);
1576 tg3_writephy(tp
, 0x1c, 0x8c68);
1577 tg3_writephy(tp
, 0x1c, 0x8d68);
1578 tg3_writephy(tp
, 0x1c, 0x8c68);
1581 /* Clear pending interrupts... */
1582 tg3_readphy(tp
, MII_TG3_ISTAT
, &dummy
);
1583 tg3_readphy(tp
, MII_TG3_ISTAT
, &dummy
);
1585 if (tp
->tg3_flags
& TG3_FLAG_USE_MI_INTERRUPT
)
1586 tg3_writephy(tp
, MII_TG3_IMASK
, ~MII_TG3_INT_LINKCHG
);
1588 tg3_writephy(tp
, MII_TG3_IMASK
, ~0);
1590 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
1591 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
1592 if (tp
->led_ctrl
== LED_CTRL_MODE_PHY_1
)
1593 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
1594 MII_TG3_EXT_CTRL_LNK3_LED_MODE
);
1596 tg3_writephy(tp
, MII_TG3_EXT_CTRL
, 0);
1599 current_link_up
= 0;
1600 current_speed
= SPEED_INVALID
;
1601 current_duplex
= DUPLEX_INVALID
;
1603 if (tp
->tg3_flags2
& TG3_FLG2_CAPACITIVE_COUPLING
) {
1606 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4007);
1607 tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &val
);
1608 if (!(val
& (1 << 10))) {
1610 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, val
);
1616 for (i
= 0; i
< 100; i
++) {
1617 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
1618 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
1619 (bmsr
& BMSR_LSTATUS
))
1624 if (bmsr
& BMSR_LSTATUS
) {
1627 tg3_readphy(tp
, MII_TG3_AUX_STAT
, &aux_stat
);
1628 for (i
= 0; i
< 2000; i
++) {
1630 if (!tg3_readphy(tp
, MII_TG3_AUX_STAT
, &aux_stat
) &&
1635 tg3_aux_stat_to_speed_duplex(tp
, aux_stat
,
1640 for (i
= 0; i
< 200; i
++) {
1641 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
1642 if (tg3_readphy(tp
, MII_BMCR
, &bmcr
))
1644 if (bmcr
&& bmcr
!= 0x7fff)
1649 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) {
1650 if (bmcr
& BMCR_ANENABLE
) {
1651 current_link_up
= 1;
1653 /* Force autoneg restart if we are exiting
1656 if (!tg3_copper_is_advertising_all(tp
))
1657 current_link_up
= 0;
1659 current_link_up
= 0;
1662 if (!(bmcr
& BMCR_ANENABLE
) &&
1663 tp
->link_config
.speed
== current_speed
&&
1664 tp
->link_config
.duplex
== current_duplex
) {
1665 current_link_up
= 1;
1667 current_link_up
= 0;
1671 tp
->link_config
.active_speed
= current_speed
;
1672 tp
->link_config
.active_duplex
= current_duplex
;
1675 if (current_link_up
== 1 &&
1676 (tp
->link_config
.active_duplex
== DUPLEX_FULL
) &&
1677 (tp
->link_config
.autoneg
== AUTONEG_ENABLE
)) {
1678 u32 local_adv
, remote_adv
;
1680 if (tg3_readphy(tp
, MII_ADVERTISE
, &local_adv
))
1682 local_adv
&= (ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
1684 if (tg3_readphy(tp
, MII_LPA
, &remote_adv
))
1687 remote_adv
&= (LPA_PAUSE_CAP
| LPA_PAUSE_ASYM
);
1689 /* If we are not advertising full pause capability,
1690 * something is wrong. Bring the link down and reconfigure.
1692 if (local_adv
!= ADVERTISE_PAUSE_CAP
) {
1693 current_link_up
= 0;
1695 tg3_setup_flow_control(tp
, local_adv
, remote_adv
);
1699 if (current_link_up
== 0) {
1702 tg3_phy_copper_begin(tp
);
1704 tg3_readphy(tp
, MII_BMSR
, &tmp
);
1705 if (!tg3_readphy(tp
, MII_BMSR
, &tmp
) &&
1706 (tmp
& BMSR_LSTATUS
))
1707 current_link_up
= 1;
1710 tp
->mac_mode
&= ~MAC_MODE_PORT_MODE_MASK
;
1711 if (current_link_up
== 1) {
1712 if (tp
->link_config
.active_speed
== SPEED_100
||
1713 tp
->link_config
.active_speed
== SPEED_10
)
1714 tp
->mac_mode
|= MAC_MODE_PORT_MODE_MII
;
1716 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
1718 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
1720 tp
->mac_mode
&= ~MAC_MODE_HALF_DUPLEX
;
1721 if (tp
->link_config
.active_duplex
== DUPLEX_HALF
)
1722 tp
->mac_mode
|= MAC_MODE_HALF_DUPLEX
;
1724 tp
->mac_mode
&= ~MAC_MODE_LINK_POLARITY
;
1725 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) {
1726 if ((tp
->led_ctrl
== LED_CTRL_MODE_PHY_2
) ||
1727 (current_link_up
== 1 &&
1728 tp
->link_config
.active_speed
== SPEED_10
))
1729 tp
->mac_mode
|= MAC_MODE_LINK_POLARITY
;
1731 if (current_link_up
== 1)
1732 tp
->mac_mode
|= MAC_MODE_LINK_POLARITY
;
1735 /* ??? Without this setting Netgear GA302T PHY does not
1736 * ??? send/receive packets...
1738 if ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5411
&&
1739 tp
->pci_chip_rev_id
== CHIPREV_ID_5700_ALTIMA
) {
1740 tp
->mi_mode
|= MAC_MI_MODE_AUTO_POLL
;
1741 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
1745 tw32_f(MAC_MODE
, tp
->mac_mode
);
1748 if (tp
->tg3_flags
& TG3_FLAG_USE_LINKCHG_REG
) {
1749 /* Polled via timer. */
1750 tw32_f(MAC_EVENT
, 0);
1752 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
1756 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
&&
1757 current_link_up
== 1 &&
1758 tp
->link_config
.active_speed
== SPEED_1000
&&
1759 ((tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) ||
1760 (tp
->tg3_flags
& TG3_FLAG_PCI_HIGH_SPEED
))) {
1763 (MAC_STATUS_SYNC_CHANGED
|
1764 MAC_STATUS_CFG_CHANGED
));
1767 NIC_SRAM_FIRMWARE_MBOX
,
1768 NIC_SRAM_FIRMWARE_MBOX_MAGIC2
);
1771 if (current_link_up
!= netif_carrier_ok(tp
->dev
)) {
1772 if (current_link_up
)
1773 netif_carrier_on(tp
->dev
);
1775 netif_carrier_off(tp
->dev
);
1776 tg3_link_report(tp
);
1782 struct tg3_fiber_aneginfo
{
1784 #define ANEG_STATE_UNKNOWN 0
1785 #define ANEG_STATE_AN_ENABLE 1
1786 #define ANEG_STATE_RESTART_INIT 2
1787 #define ANEG_STATE_RESTART 3
1788 #define ANEG_STATE_DISABLE_LINK_OK 4
1789 #define ANEG_STATE_ABILITY_DETECT_INIT 5
1790 #define ANEG_STATE_ABILITY_DETECT 6
1791 #define ANEG_STATE_ACK_DETECT_INIT 7
1792 #define ANEG_STATE_ACK_DETECT 8
1793 #define ANEG_STATE_COMPLETE_ACK_INIT 9
1794 #define ANEG_STATE_COMPLETE_ACK 10
1795 #define ANEG_STATE_IDLE_DETECT_INIT 11
1796 #define ANEG_STATE_IDLE_DETECT 12
1797 #define ANEG_STATE_LINK_OK 13
1798 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
1799 #define ANEG_STATE_NEXT_PAGE_WAIT 15
1802 #define MR_AN_ENABLE 0x00000001
1803 #define MR_RESTART_AN 0x00000002
1804 #define MR_AN_COMPLETE 0x00000004
1805 #define MR_PAGE_RX 0x00000008
1806 #define MR_NP_LOADED 0x00000010
1807 #define MR_TOGGLE_TX 0x00000020
1808 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
1809 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
1810 #define MR_LP_ADV_SYM_PAUSE 0x00000100
1811 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
1812 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
1813 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
1814 #define MR_LP_ADV_NEXT_PAGE 0x00001000
1815 #define MR_TOGGLE_RX 0x00002000
1816 #define MR_NP_RX 0x00004000
1818 #define MR_LINK_OK 0x80000000
1820 unsigned long link_time
, cur_time
;
1822 u32 ability_match_cfg
;
1823 int ability_match_count
;
1825 char ability_match
, idle_match
, ack_match
;
1827 u32 txconfig
, rxconfig
;
1828 #define ANEG_CFG_NP 0x00000080
1829 #define ANEG_CFG_ACK 0x00000040
1830 #define ANEG_CFG_RF2 0x00000020
1831 #define ANEG_CFG_RF1 0x00000010
1832 #define ANEG_CFG_PS2 0x00000001
1833 #define ANEG_CFG_PS1 0x00008000
1834 #define ANEG_CFG_HD 0x00004000
1835 #define ANEG_CFG_FD 0x00002000
1836 #define ANEG_CFG_INVAL 0x00001f06
1841 #define ANEG_TIMER_ENAB 2
1842 #define ANEG_FAILED -1
1844 #define ANEG_STATE_SETTLE_TIME 10000
1846 static int tg3_fiber_aneg_smachine(struct tg3
*tp
,
1847 struct tg3_fiber_aneginfo
*ap
)
1849 unsigned long delta
;
1853 if (ap
->state
== ANEG_STATE_UNKNOWN
) {
1857 ap
->ability_match_cfg
= 0;
1858 ap
->ability_match_count
= 0;
1859 ap
->ability_match
= 0;
1865 if (tr32(MAC_STATUS
) & MAC_STATUS_RCVD_CFG
) {
1866 rx_cfg_reg
= tr32(MAC_RX_AUTO_NEG
);
1868 if (rx_cfg_reg
!= ap
->ability_match_cfg
) {
1869 ap
->ability_match_cfg
= rx_cfg_reg
;
1870 ap
->ability_match
= 0;
1871 ap
->ability_match_count
= 0;
1873 if (++ap
->ability_match_count
> 1) {
1874 ap
->ability_match
= 1;
1875 ap
->ability_match_cfg
= rx_cfg_reg
;
1878 if (rx_cfg_reg
& ANEG_CFG_ACK
)
1886 ap
->ability_match_cfg
= 0;
1887 ap
->ability_match_count
= 0;
1888 ap
->ability_match
= 0;
1894 ap
->rxconfig
= rx_cfg_reg
;
1898 case ANEG_STATE_UNKNOWN
:
1899 if (ap
->flags
& (MR_AN_ENABLE
| MR_RESTART_AN
))
1900 ap
->state
= ANEG_STATE_AN_ENABLE
;
1903 case ANEG_STATE_AN_ENABLE
:
1904 ap
->flags
&= ~(MR_AN_COMPLETE
| MR_PAGE_RX
);
1905 if (ap
->flags
& MR_AN_ENABLE
) {
1908 ap
->ability_match_cfg
= 0;
1909 ap
->ability_match_count
= 0;
1910 ap
->ability_match
= 0;
1914 ap
->state
= ANEG_STATE_RESTART_INIT
;
1916 ap
->state
= ANEG_STATE_DISABLE_LINK_OK
;
1920 case ANEG_STATE_RESTART_INIT
:
1921 ap
->link_time
= ap
->cur_time
;
1922 ap
->flags
&= ~(MR_NP_LOADED
);
1924 tw32(MAC_TX_AUTO_NEG
, 0);
1925 tp
->mac_mode
|= MAC_MODE_SEND_CONFIGS
;
1926 tw32_f(MAC_MODE
, tp
->mac_mode
);
1929 ret
= ANEG_TIMER_ENAB
;
1930 ap
->state
= ANEG_STATE_RESTART
;
1933 case ANEG_STATE_RESTART
:
1934 delta
= ap
->cur_time
- ap
->link_time
;
1935 if (delta
> ANEG_STATE_SETTLE_TIME
) {
1936 ap
->state
= ANEG_STATE_ABILITY_DETECT_INIT
;
1938 ret
= ANEG_TIMER_ENAB
;
1942 case ANEG_STATE_DISABLE_LINK_OK
:
1946 case ANEG_STATE_ABILITY_DETECT_INIT
:
1947 ap
->flags
&= ~(MR_TOGGLE_TX
);
1948 ap
->txconfig
= (ANEG_CFG_FD
| ANEG_CFG_PS1
);
1949 tw32(MAC_TX_AUTO_NEG
, ap
->txconfig
);
1950 tp
->mac_mode
|= MAC_MODE_SEND_CONFIGS
;
1951 tw32_f(MAC_MODE
, tp
->mac_mode
);
1954 ap
->state
= ANEG_STATE_ABILITY_DETECT
;
1957 case ANEG_STATE_ABILITY_DETECT
:
1958 if (ap
->ability_match
!= 0 && ap
->rxconfig
!= 0) {
1959 ap
->state
= ANEG_STATE_ACK_DETECT_INIT
;
1963 case ANEG_STATE_ACK_DETECT_INIT
:
1964 ap
->txconfig
|= ANEG_CFG_ACK
;
1965 tw32(MAC_TX_AUTO_NEG
, ap
->txconfig
);
1966 tp
->mac_mode
|= MAC_MODE_SEND_CONFIGS
;
1967 tw32_f(MAC_MODE
, tp
->mac_mode
);
1970 ap
->state
= ANEG_STATE_ACK_DETECT
;
1973 case ANEG_STATE_ACK_DETECT
:
1974 if (ap
->ack_match
!= 0) {
1975 if ((ap
->rxconfig
& ~ANEG_CFG_ACK
) ==
1976 (ap
->ability_match_cfg
& ~ANEG_CFG_ACK
)) {
1977 ap
->state
= ANEG_STATE_COMPLETE_ACK_INIT
;
1979 ap
->state
= ANEG_STATE_AN_ENABLE
;
1981 } else if (ap
->ability_match
!= 0 &&
1982 ap
->rxconfig
== 0) {
1983 ap
->state
= ANEG_STATE_AN_ENABLE
;
1987 case ANEG_STATE_COMPLETE_ACK_INIT
:
1988 if (ap
->rxconfig
& ANEG_CFG_INVAL
) {
1992 ap
->flags
&= ~(MR_LP_ADV_FULL_DUPLEX
|
1993 MR_LP_ADV_HALF_DUPLEX
|
1994 MR_LP_ADV_SYM_PAUSE
|
1995 MR_LP_ADV_ASYM_PAUSE
|
1996 MR_LP_ADV_REMOTE_FAULT1
|
1997 MR_LP_ADV_REMOTE_FAULT2
|
1998 MR_LP_ADV_NEXT_PAGE
|
2001 if (ap
->rxconfig
& ANEG_CFG_FD
)
2002 ap
->flags
|= MR_LP_ADV_FULL_DUPLEX
;
2003 if (ap
->rxconfig
& ANEG_CFG_HD
)
2004 ap
->flags
|= MR_LP_ADV_HALF_DUPLEX
;
2005 if (ap
->rxconfig
& ANEG_CFG_PS1
)
2006 ap
->flags
|= MR_LP_ADV_SYM_PAUSE
;
2007 if (ap
->rxconfig
& ANEG_CFG_PS2
)
2008 ap
->flags
|= MR_LP_ADV_ASYM_PAUSE
;
2009 if (ap
->rxconfig
& ANEG_CFG_RF1
)
2010 ap
->flags
|= MR_LP_ADV_REMOTE_FAULT1
;
2011 if (ap
->rxconfig
& ANEG_CFG_RF2
)
2012 ap
->flags
|= MR_LP_ADV_REMOTE_FAULT2
;
2013 if (ap
->rxconfig
& ANEG_CFG_NP
)
2014 ap
->flags
|= MR_LP_ADV_NEXT_PAGE
;
2016 ap
->link_time
= ap
->cur_time
;
2018 ap
->flags
^= (MR_TOGGLE_TX
);
2019 if (ap
->rxconfig
& 0x0008)
2020 ap
->flags
|= MR_TOGGLE_RX
;
2021 if (ap
->rxconfig
& ANEG_CFG_NP
)
2022 ap
->flags
|= MR_NP_RX
;
2023 ap
->flags
|= MR_PAGE_RX
;
2025 ap
->state
= ANEG_STATE_COMPLETE_ACK
;
2026 ret
= ANEG_TIMER_ENAB
;
2029 case ANEG_STATE_COMPLETE_ACK
:
2030 if (ap
->ability_match
!= 0 &&
2031 ap
->rxconfig
== 0) {
2032 ap
->state
= ANEG_STATE_AN_ENABLE
;
2035 delta
= ap
->cur_time
- ap
->link_time
;
2036 if (delta
> ANEG_STATE_SETTLE_TIME
) {
2037 if (!(ap
->flags
& (MR_LP_ADV_NEXT_PAGE
))) {
2038 ap
->state
= ANEG_STATE_IDLE_DETECT_INIT
;
2040 if ((ap
->txconfig
& ANEG_CFG_NP
) == 0 &&
2041 !(ap
->flags
& MR_NP_RX
)) {
2042 ap
->state
= ANEG_STATE_IDLE_DETECT_INIT
;
2050 case ANEG_STATE_IDLE_DETECT_INIT
:
2051 ap
->link_time
= ap
->cur_time
;
2052 tp
->mac_mode
&= ~MAC_MODE_SEND_CONFIGS
;
2053 tw32_f(MAC_MODE
, tp
->mac_mode
);
2056 ap
->state
= ANEG_STATE_IDLE_DETECT
;
2057 ret
= ANEG_TIMER_ENAB
;
2060 case ANEG_STATE_IDLE_DETECT
:
2061 if (ap
->ability_match
!= 0 &&
2062 ap
->rxconfig
== 0) {
2063 ap
->state
= ANEG_STATE_AN_ENABLE
;
2066 delta
= ap
->cur_time
- ap
->link_time
;
2067 if (delta
> ANEG_STATE_SETTLE_TIME
) {
2068 /* XXX another gem from the Broadcom driver :( */
2069 ap
->state
= ANEG_STATE_LINK_OK
;
2073 case ANEG_STATE_LINK_OK
:
2074 ap
->flags
|= (MR_AN_COMPLETE
| MR_LINK_OK
);
2078 case ANEG_STATE_NEXT_PAGE_WAIT_INIT
:
2079 /* ??? unimplemented */
2082 case ANEG_STATE_NEXT_PAGE_WAIT
:
2083 /* ??? unimplemented */
2094 static int fiber_autoneg(struct tg3
*tp
, u32
*flags
)
2097 struct tg3_fiber_aneginfo aninfo
;
2098 int status
= ANEG_FAILED
;
2102 tw32_f(MAC_TX_AUTO_NEG
, 0);
2104 tmp
= tp
->mac_mode
& ~MAC_MODE_PORT_MODE_MASK
;
2105 tw32_f(MAC_MODE
, tmp
| MAC_MODE_PORT_MODE_GMII
);
2108 tw32_f(MAC_MODE
, tp
->mac_mode
| MAC_MODE_SEND_CONFIGS
);
2111 memset(&aninfo
, 0, sizeof(aninfo
));
2112 aninfo
.flags
|= MR_AN_ENABLE
;
2113 aninfo
.state
= ANEG_STATE_UNKNOWN
;
2114 aninfo
.cur_time
= 0;
2116 while (++tick
< 195000) {
2117 status
= tg3_fiber_aneg_smachine(tp
, &aninfo
);
2118 if (status
== ANEG_DONE
|| status
== ANEG_FAILED
)
2124 tp
->mac_mode
&= ~MAC_MODE_SEND_CONFIGS
;
2125 tw32_f(MAC_MODE
, tp
->mac_mode
);
2128 *flags
= aninfo
.flags
;
2130 if (status
== ANEG_DONE
&&
2131 (aninfo
.flags
& (MR_AN_COMPLETE
| MR_LINK_OK
|
2132 MR_LP_ADV_FULL_DUPLEX
)))
2138 static void tg3_init_bcm8002(struct tg3
*tp
)
2140 u32 mac_status
= tr32(MAC_STATUS
);
2143 /* Reset when initting first time or we have a link. */
2144 if ((tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
) &&
2145 !(mac_status
& MAC_STATUS_PCS_SYNCED
))
2148 /* Set PLL lock range. */
2149 tg3_writephy(tp
, 0x16, 0x8007);
2152 tg3_writephy(tp
, MII_BMCR
, BMCR_RESET
);
2154 /* Wait for reset to complete. */
2155 /* XXX schedule_timeout() ... */
2156 for (i
= 0; i
< 500; i
++)
2159 /* Config mode; select PMA/Ch 1 regs. */
2160 tg3_writephy(tp
, 0x10, 0x8411);
2162 /* Enable auto-lock and comdet, select txclk for tx. */
2163 tg3_writephy(tp
, 0x11, 0x0a10);
2165 tg3_writephy(tp
, 0x18, 0x00a0);
2166 tg3_writephy(tp
, 0x16, 0x41ff);
2168 /* Assert and deassert POR. */
2169 tg3_writephy(tp
, 0x13, 0x0400);
2171 tg3_writephy(tp
, 0x13, 0x0000);
2173 tg3_writephy(tp
, 0x11, 0x0a50);
2175 tg3_writephy(tp
, 0x11, 0x0a10);
2177 /* Wait for signal to stabilize */
2178 /* XXX schedule_timeout() ... */
2179 for (i
= 0; i
< 15000; i
++)
2182 /* Deselect the channel register so we can read the PHYID
2185 tg3_writephy(tp
, 0x10, 0x8011);
2188 static int tg3_setup_fiber_hw_autoneg(struct tg3
*tp
, u32 mac_status
)
2190 u32 sg_dig_ctrl
, sg_dig_status
;
2191 u32 serdes_cfg
, expected_sg_dig_ctrl
;
2192 int workaround
, port_a
;
2193 int current_link_up
;
2196 expected_sg_dig_ctrl
= 0;
2199 current_link_up
= 0;
2201 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5704_A0
&&
2202 tp
->pci_chip_rev_id
!= CHIPREV_ID_5704_A1
) {
2204 if (tr32(TG3PCI_DUAL_MAC_CTRL
) & DUAL_MAC_CTRL_ID
)
2207 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2208 /* preserve bits 20-23 for voltage regulator */
2209 serdes_cfg
= tr32(MAC_SERDES_CFG
) & 0x00f06fff;
2212 sg_dig_ctrl
= tr32(SG_DIG_CTRL
);
2214 if (tp
->link_config
.autoneg
!= AUTONEG_ENABLE
) {
2215 if (sg_dig_ctrl
& (1 << 31)) {
2217 u32 val
= serdes_cfg
;
2223 tw32_f(MAC_SERDES_CFG
, val
);
2225 tw32_f(SG_DIG_CTRL
, 0x01388400);
2227 if (mac_status
& MAC_STATUS_PCS_SYNCED
) {
2228 tg3_setup_flow_control(tp
, 0, 0);
2229 current_link_up
= 1;
2234 /* Want auto-negotiation. */
2235 expected_sg_dig_ctrl
= 0x81388400;
2237 /* Pause capability */
2238 expected_sg_dig_ctrl
|= (1 << 11);
2240 /* Asymettric pause */
2241 expected_sg_dig_ctrl
|= (1 << 12);
2243 if (sg_dig_ctrl
!= expected_sg_dig_ctrl
) {
2245 tw32_f(MAC_SERDES_CFG
, serdes_cfg
| 0xc011000);
2246 tw32_f(SG_DIG_CTRL
, expected_sg_dig_ctrl
| (1 << 30));
2248 tw32_f(SG_DIG_CTRL
, expected_sg_dig_ctrl
);
2250 tp
->tg3_flags2
|= TG3_FLG2_PHY_JUST_INITTED
;
2251 } else if (mac_status
& (MAC_STATUS_PCS_SYNCED
|
2252 MAC_STATUS_SIGNAL_DET
)) {
2255 /* Giver time to negotiate (~200ms) */
2256 for (i
= 0; i
< 40000; i
++) {
2257 sg_dig_status
= tr32(SG_DIG_STATUS
);
2258 if (sg_dig_status
& (0x3))
2262 mac_status
= tr32(MAC_STATUS
);
2264 if ((sg_dig_status
& (1 << 1)) &&
2265 (mac_status
& MAC_STATUS_PCS_SYNCED
)) {
2266 u32 local_adv
, remote_adv
;
2268 local_adv
= ADVERTISE_PAUSE_CAP
;
2270 if (sg_dig_status
& (1 << 19))
2271 remote_adv
|= LPA_PAUSE_CAP
;
2272 if (sg_dig_status
& (1 << 20))
2273 remote_adv
|= LPA_PAUSE_ASYM
;
2275 tg3_setup_flow_control(tp
, local_adv
, remote_adv
);
2276 current_link_up
= 1;
2277 tp
->tg3_flags2
&= ~TG3_FLG2_PHY_JUST_INITTED
;
2278 } else if (!(sg_dig_status
& (1 << 1))) {
2279 if (tp
->tg3_flags2
& TG3_FLG2_PHY_JUST_INITTED
)
2280 tp
->tg3_flags2
&= ~TG3_FLG2_PHY_JUST_INITTED
;
2283 u32 val
= serdes_cfg
;
2290 tw32_f(MAC_SERDES_CFG
, val
);
2293 tw32_f(SG_DIG_CTRL
, 0x01388400);
2296 /* Link parallel detection - link is up */
2297 /* only if we have PCS_SYNC and not */
2298 /* receiving config code words */
2299 mac_status
= tr32(MAC_STATUS
);
2300 if ((mac_status
& MAC_STATUS_PCS_SYNCED
) &&
2301 !(mac_status
& MAC_STATUS_RCVD_CFG
)) {
2302 tg3_setup_flow_control(tp
, 0, 0);
2303 current_link_up
= 1;
2310 return current_link_up
;
2313 static int tg3_setup_fiber_by_hand(struct tg3
*tp
, u32 mac_status
)
2315 int current_link_up
= 0;
2317 if (!(mac_status
& MAC_STATUS_PCS_SYNCED
)) {
2318 tp
->tg3_flags
&= ~TG3_FLAG_GOT_SERDES_FLOWCTL
;
2322 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) {
2326 if (fiber_autoneg(tp
, &flags
)) {
2327 u32 local_adv
, remote_adv
;
2329 local_adv
= ADVERTISE_PAUSE_CAP
;
2331 if (flags
& MR_LP_ADV_SYM_PAUSE
)
2332 remote_adv
|= LPA_PAUSE_CAP
;
2333 if (flags
& MR_LP_ADV_ASYM_PAUSE
)
2334 remote_adv
|= LPA_PAUSE_ASYM
;
2336 tg3_setup_flow_control(tp
, local_adv
, remote_adv
);
2338 tp
->tg3_flags
|= TG3_FLAG_GOT_SERDES_FLOWCTL
;
2339 current_link_up
= 1;
2341 for (i
= 0; i
< 30; i
++) {
2344 (MAC_STATUS_SYNC_CHANGED
|
2345 MAC_STATUS_CFG_CHANGED
));
2347 if ((tr32(MAC_STATUS
) &
2348 (MAC_STATUS_SYNC_CHANGED
|
2349 MAC_STATUS_CFG_CHANGED
)) == 0)
2353 mac_status
= tr32(MAC_STATUS
);
2354 if (current_link_up
== 0 &&
2355 (mac_status
& MAC_STATUS_PCS_SYNCED
) &&
2356 !(mac_status
& MAC_STATUS_RCVD_CFG
))
2357 current_link_up
= 1;
2359 /* Forcing 1000FD link up. */
2360 current_link_up
= 1;
2361 tp
->tg3_flags
|= TG3_FLAG_GOT_SERDES_FLOWCTL
;
2363 tw32_f(MAC_MODE
, (tp
->mac_mode
| MAC_MODE_SEND_CONFIGS
));
2368 return current_link_up
;
2371 static int tg3_setup_fiber_phy(struct tg3
*tp
, int force_reset
)
2374 u16 orig_active_speed
;
2375 u8 orig_active_duplex
;
2377 int current_link_up
;
2381 (tp
->tg3_flags
& (TG3_FLAG_RX_PAUSE
|
2382 TG3_FLAG_TX_PAUSE
));
2383 orig_active_speed
= tp
->link_config
.active_speed
;
2384 orig_active_duplex
= tp
->link_config
.active_duplex
;
2386 if (!(tp
->tg3_flags2
& TG3_FLG2_HW_AUTONEG
) &&
2387 netif_carrier_ok(tp
->dev
) &&
2388 (tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
)) {
2389 mac_status
= tr32(MAC_STATUS
);
2390 mac_status
&= (MAC_STATUS_PCS_SYNCED
|
2391 MAC_STATUS_SIGNAL_DET
|
2392 MAC_STATUS_CFG_CHANGED
|
2393 MAC_STATUS_RCVD_CFG
);
2394 if (mac_status
== (MAC_STATUS_PCS_SYNCED
|
2395 MAC_STATUS_SIGNAL_DET
)) {
2396 tw32_f(MAC_STATUS
, (MAC_STATUS_SYNC_CHANGED
|
2397 MAC_STATUS_CFG_CHANGED
));
2402 tw32_f(MAC_TX_AUTO_NEG
, 0);
2404 tp
->mac_mode
&= ~(MAC_MODE_PORT_MODE_MASK
| MAC_MODE_HALF_DUPLEX
);
2405 tp
->mac_mode
|= MAC_MODE_PORT_MODE_TBI
;
2406 tw32_f(MAC_MODE
, tp
->mac_mode
);
2409 if (tp
->phy_id
== PHY_ID_BCM8002
)
2410 tg3_init_bcm8002(tp
);
2412 /* Enable link change event even when serdes polling. */
2413 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
2416 current_link_up
= 0;
2417 mac_status
= tr32(MAC_STATUS
);
2419 if (tp
->tg3_flags2
& TG3_FLG2_HW_AUTONEG
)
2420 current_link_up
= tg3_setup_fiber_hw_autoneg(tp
, mac_status
);
2422 current_link_up
= tg3_setup_fiber_by_hand(tp
, mac_status
);
2424 tp
->mac_mode
&= ~MAC_MODE_LINK_POLARITY
;
2425 tw32_f(MAC_MODE
, tp
->mac_mode
);
2428 tp
->hw_status
->status
=
2429 (SD_STATUS_UPDATED
|
2430 (tp
->hw_status
->status
& ~SD_STATUS_LINK_CHG
));
2432 for (i
= 0; i
< 100; i
++) {
2433 tw32_f(MAC_STATUS
, (MAC_STATUS_SYNC_CHANGED
|
2434 MAC_STATUS_CFG_CHANGED
));
2436 if ((tr32(MAC_STATUS
) & (MAC_STATUS_SYNC_CHANGED
|
2437 MAC_STATUS_CFG_CHANGED
)) == 0)
2441 mac_status
= tr32(MAC_STATUS
);
2442 if ((mac_status
& MAC_STATUS_PCS_SYNCED
) == 0) {
2443 current_link_up
= 0;
2444 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) {
2445 tw32_f(MAC_MODE
, (tp
->mac_mode
|
2446 MAC_MODE_SEND_CONFIGS
));
2448 tw32_f(MAC_MODE
, tp
->mac_mode
);
2452 if (current_link_up
== 1) {
2453 tp
->link_config
.active_speed
= SPEED_1000
;
2454 tp
->link_config
.active_duplex
= DUPLEX_FULL
;
2455 tw32(MAC_LED_CTRL
, (tp
->led_ctrl
|
2456 LED_CTRL_LNKLED_OVERRIDE
|
2457 LED_CTRL_1000MBPS_ON
));
2459 tp
->link_config
.active_speed
= SPEED_INVALID
;
2460 tp
->link_config
.active_duplex
= DUPLEX_INVALID
;
2461 tw32(MAC_LED_CTRL
, (tp
->led_ctrl
|
2462 LED_CTRL_LNKLED_OVERRIDE
|
2463 LED_CTRL_TRAFFIC_OVERRIDE
));
2466 if (current_link_up
!= netif_carrier_ok(tp
->dev
)) {
2467 if (current_link_up
)
2468 netif_carrier_on(tp
->dev
);
2470 netif_carrier_off(tp
->dev
);
2471 tg3_link_report(tp
);
2474 tp
->tg3_flags
& (TG3_FLAG_RX_PAUSE
|
2476 if (orig_pause_cfg
!= now_pause_cfg
||
2477 orig_active_speed
!= tp
->link_config
.active_speed
||
2478 orig_active_duplex
!= tp
->link_config
.active_duplex
)
2479 tg3_link_report(tp
);
2485 static int tg3_setup_phy(struct tg3
*tp
, int force_reset
)
2489 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
2490 err
= tg3_setup_fiber_phy(tp
, force_reset
);
2492 err
= tg3_setup_copper_phy(tp
, force_reset
);
2495 if (tp
->link_config
.active_speed
== SPEED_1000
&&
2496 tp
->link_config
.active_duplex
== DUPLEX_HALF
)
2497 tw32(MAC_TX_LENGTHS
,
2498 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
2499 (6 << TX_LENGTHS_IPG_SHIFT
) |
2500 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT
)));
2502 tw32(MAC_TX_LENGTHS
,
2503 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
2504 (6 << TX_LENGTHS_IPG_SHIFT
) |
2505 (32 << TX_LENGTHS_SLOT_TIME_SHIFT
)));
2507 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
2508 if (netif_carrier_ok(tp
->dev
)) {
2509 tw32(HOSTCC_STAT_COAL_TICKS
,
2510 DEFAULT_STAT_COAL_TICKS
);
2512 tw32(HOSTCC_STAT_COAL_TICKS
, 0);
2519 /* Tigon3 never reports partial packet sends. So we do not
2520 * need special logic to handle SKBs that have not had all
2521 * of their frags sent yet, like SunGEM does.
2523 static void tg3_tx(struct tg3
*tp
)
2525 u32 hw_idx
= tp
->hw_status
->idx
[0].tx_consumer
;
2526 u32 sw_idx
= tp
->tx_cons
;
2528 while (sw_idx
!= hw_idx
) {
2529 struct tx_ring_info
*ri
= &tp
->tx_buffers
[sw_idx
];
2530 struct sk_buff
*skb
= ri
->skb
;
2533 if (unlikely(skb
== NULL
))
2536 pci_unmap_single(tp
->pdev
,
2537 pci_unmap_addr(ri
, mapping
),
2543 sw_idx
= NEXT_TX(sw_idx
);
2545 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
2546 if (unlikely(sw_idx
== hw_idx
))
2549 ri
= &tp
->tx_buffers
[sw_idx
];
2550 if (unlikely(ri
->skb
!= NULL
))
2553 pci_unmap_page(tp
->pdev
,
2554 pci_unmap_addr(ri
, mapping
),
2555 skb_shinfo(skb
)->frags
[i
].size
,
2558 sw_idx
= NEXT_TX(sw_idx
);
2561 dev_kfree_skb_irq(skb
);
2564 tp
->tx_cons
= sw_idx
;
2566 if (netif_queue_stopped(tp
->dev
) &&
2567 (TX_BUFFS_AVAIL(tp
) > TG3_TX_WAKEUP_THRESH
))
2568 netif_wake_queue(tp
->dev
);
2571 /* Returns size of skb allocated or < 0 on error.
2573 * We only need to fill in the address because the other members
2574 * of the RX descriptor are invariant, see tg3_init_rings.
2576 * Note the purposeful assymetry of cpu vs. chip accesses. For
2577 * posting buffers we only dirty the first cache line of the RX
2578 * descriptor (containing the address). Whereas for the RX status
2579 * buffers the cpu only reads the last cacheline of the RX descriptor
2580 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
2582 static int tg3_alloc_rx_skb(struct tg3
*tp
, u32 opaque_key
,
2583 int src_idx
, u32 dest_idx_unmasked
)
2585 struct tg3_rx_buffer_desc
*desc
;
2586 struct ring_info
*map
, *src_map
;
2587 struct sk_buff
*skb
;
2589 int skb_size
, dest_idx
;
2592 switch (opaque_key
) {
2593 case RXD_OPAQUE_RING_STD
:
2594 dest_idx
= dest_idx_unmasked
% TG3_RX_RING_SIZE
;
2595 desc
= &tp
->rx_std
[dest_idx
];
2596 map
= &tp
->rx_std_buffers
[dest_idx
];
2598 src_map
= &tp
->rx_std_buffers
[src_idx
];
2599 skb_size
= RX_PKT_BUF_SZ
;
2602 case RXD_OPAQUE_RING_JUMBO
:
2603 dest_idx
= dest_idx_unmasked
% TG3_RX_JUMBO_RING_SIZE
;
2604 desc
= &tp
->rx_jumbo
[dest_idx
];
2605 map
= &tp
->rx_jumbo_buffers
[dest_idx
];
2607 src_map
= &tp
->rx_jumbo_buffers
[src_idx
];
2608 skb_size
= RX_JUMBO_PKT_BUF_SZ
;
2615 /* Do not overwrite any of the map or rp information
2616 * until we are sure we can commit to a new buffer.
2618 * Callers depend upon this behavior and assume that
2619 * we leave everything unchanged if we fail.
2621 skb
= dev_alloc_skb(skb_size
);
2626 skb_reserve(skb
, tp
->rx_offset
);
2628 mapping
= pci_map_single(tp
->pdev
, skb
->data
,
2629 skb_size
- tp
->rx_offset
,
2630 PCI_DMA_FROMDEVICE
);
2633 pci_unmap_addr_set(map
, mapping
, mapping
);
2635 if (src_map
!= NULL
)
2636 src_map
->skb
= NULL
;
2638 desc
->addr_hi
= ((u64
)mapping
>> 32);
2639 desc
->addr_lo
= ((u64
)mapping
& 0xffffffff);
2644 /* We only need to move over in the address because the other
2645 * members of the RX descriptor are invariant. See notes above
2646 * tg3_alloc_rx_skb for full details.
2648 static void tg3_recycle_rx(struct tg3
*tp
, u32 opaque_key
,
2649 int src_idx
, u32 dest_idx_unmasked
)
2651 struct tg3_rx_buffer_desc
*src_desc
, *dest_desc
;
2652 struct ring_info
*src_map
, *dest_map
;
2655 switch (opaque_key
) {
2656 case RXD_OPAQUE_RING_STD
:
2657 dest_idx
= dest_idx_unmasked
% TG3_RX_RING_SIZE
;
2658 dest_desc
= &tp
->rx_std
[dest_idx
];
2659 dest_map
= &tp
->rx_std_buffers
[dest_idx
];
2660 src_desc
= &tp
->rx_std
[src_idx
];
2661 src_map
= &tp
->rx_std_buffers
[src_idx
];
2664 case RXD_OPAQUE_RING_JUMBO
:
2665 dest_idx
= dest_idx_unmasked
% TG3_RX_JUMBO_RING_SIZE
;
2666 dest_desc
= &tp
->rx_jumbo
[dest_idx
];
2667 dest_map
= &tp
->rx_jumbo_buffers
[dest_idx
];
2668 src_desc
= &tp
->rx_jumbo
[src_idx
];
2669 src_map
= &tp
->rx_jumbo_buffers
[src_idx
];
2676 dest_map
->skb
= src_map
->skb
;
2677 pci_unmap_addr_set(dest_map
, mapping
,
2678 pci_unmap_addr(src_map
, mapping
));
2679 dest_desc
->addr_hi
= src_desc
->addr_hi
;
2680 dest_desc
->addr_lo
= src_desc
->addr_lo
;
2682 src_map
->skb
= NULL
;
2685 #if TG3_VLAN_TAG_USED
2686 static int tg3_vlan_rx(struct tg3
*tp
, struct sk_buff
*skb
, u16 vlan_tag
)
2688 return vlan_hwaccel_receive_skb(skb
, tp
->vlgrp
, vlan_tag
);
2692 /* The RX ring scheme is composed of multiple rings which post fresh
2693 * buffers to the chip, and one special ring the chip uses to report
2694 * status back to the host.
2696 * The special ring reports the status of received packets to the
2697 * host. The chip does not write into the original descriptor the
2698 * RX buffer was obtained from. The chip simply takes the original
2699 * descriptor as provided by the host, updates the status and length
2700 * field, then writes this into the next status ring entry.
2702 * Each ring the host uses to post buffers to the chip is described
2703 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
2704 * it is first placed into the on-chip ram. When the packet's length
2705 * is known, it walks down the TG3_BDINFO entries to select the ring.
2706 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
2707 * which is within the range of the new packet's length is chosen.
2709 * The "separate ring for rx status" scheme may sound queer, but it makes
2710 * sense from a cache coherency perspective. If only the host writes
2711 * to the buffer post rings, and only the chip writes to the rx status
2712 * rings, then cache lines never move beyond shared-modified state.
2713 * If both the host and chip were to write into the same ring, cache line
2714 * eviction could occur since both entities want it in an exclusive state.
2716 static int tg3_rx(struct tg3
*tp
, int budget
)
2719 u32 sw_idx
= tp
->rx_rcb_ptr
;
2723 hw_idx
= tp
->hw_status
->idx
[0].rx_producer
;
2725 * We need to order the read of hw_idx and the read of
2726 * the opaque cookie.
2731 while (sw_idx
!= hw_idx
&& budget
> 0) {
2732 struct tg3_rx_buffer_desc
*desc
= &tp
->rx_rcb
[sw_idx
];
2734 struct sk_buff
*skb
;
2735 dma_addr_t dma_addr
;
2736 u32 opaque_key
, desc_idx
, *post_ptr
;
2738 desc_idx
= desc
->opaque
& RXD_OPAQUE_INDEX_MASK
;
2739 opaque_key
= desc
->opaque
& RXD_OPAQUE_RING_MASK
;
2740 if (opaque_key
== RXD_OPAQUE_RING_STD
) {
2741 dma_addr
= pci_unmap_addr(&tp
->rx_std_buffers
[desc_idx
],
2743 skb
= tp
->rx_std_buffers
[desc_idx
].skb
;
2744 post_ptr
= &tp
->rx_std_ptr
;
2745 } else if (opaque_key
== RXD_OPAQUE_RING_JUMBO
) {
2746 dma_addr
= pci_unmap_addr(&tp
->rx_jumbo_buffers
[desc_idx
],
2748 skb
= tp
->rx_jumbo_buffers
[desc_idx
].skb
;
2749 post_ptr
= &tp
->rx_jumbo_ptr
;
2752 goto next_pkt_nopost
;
2755 work_mask
|= opaque_key
;
2757 if ((desc
->err_vlan
& RXD_ERR_MASK
) != 0 &&
2758 (desc
->err_vlan
!= RXD_ERR_ODD_NIBBLE_RCVD_MII
)) {
2760 tg3_recycle_rx(tp
, opaque_key
,
2761 desc_idx
, *post_ptr
);
2763 /* Other statistics kept track of by card. */
2764 tp
->net_stats
.rx_dropped
++;
2768 len
= ((desc
->idx_len
& RXD_LEN_MASK
) >> RXD_LEN_SHIFT
) - 4; /* omit crc */
2770 if (len
> RX_COPY_THRESHOLD
2771 && tp
->rx_offset
== 2
2772 /* rx_offset != 2 iff this is a 5701 card running
2773 * in PCI-X mode [see tg3_get_invariants()] */
2777 skb_size
= tg3_alloc_rx_skb(tp
, opaque_key
,
2778 desc_idx
, *post_ptr
);
2782 pci_unmap_single(tp
->pdev
, dma_addr
,
2783 skb_size
- tp
->rx_offset
,
2784 PCI_DMA_FROMDEVICE
);
2788 struct sk_buff
*copy_skb
;
2790 tg3_recycle_rx(tp
, opaque_key
,
2791 desc_idx
, *post_ptr
);
2793 copy_skb
= dev_alloc_skb(len
+ 2);
2794 if (copy_skb
== NULL
)
2795 goto drop_it_no_recycle
;
2797 copy_skb
->dev
= tp
->dev
;
2798 skb_reserve(copy_skb
, 2);
2799 skb_put(copy_skb
, len
);
2800 pci_dma_sync_single_for_cpu(tp
->pdev
, dma_addr
, len
, PCI_DMA_FROMDEVICE
);
2801 memcpy(copy_skb
->data
, skb
->data
, len
);
2802 pci_dma_sync_single_for_device(tp
->pdev
, dma_addr
, len
, PCI_DMA_FROMDEVICE
);
2804 /* We'll reuse the original ring buffer. */
2808 if ((tp
->tg3_flags
& TG3_FLAG_RX_CHECKSUMS
) &&
2809 (desc
->type_flags
& RXD_FLAG_TCPUDP_CSUM
) &&
2810 (((desc
->ip_tcp_csum
& RXD_TCPCSUM_MASK
)
2811 >> RXD_TCPCSUM_SHIFT
) == 0xffff))
2812 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
2814 skb
->ip_summed
= CHECKSUM_NONE
;
2816 skb
->protocol
= eth_type_trans(skb
, tp
->dev
);
2817 #if TG3_VLAN_TAG_USED
2818 if (tp
->vlgrp
!= NULL
&&
2819 desc
->type_flags
& RXD_FLAG_VLAN
) {
2820 tg3_vlan_rx(tp
, skb
,
2821 desc
->err_vlan
& RXD_VLAN_MASK
);
2824 netif_receive_skb(skb
);
2826 tp
->dev
->last_rx
= jiffies
;
2834 sw_idx
%= TG3_RX_RCB_RING_SIZE(tp
);
2836 /* Refresh hw_idx to see if there is new work */
2837 if (sw_idx
== hw_idx
) {
2838 hw_idx
= tp
->hw_status
->idx
[0].rx_producer
;
2843 /* ACK the status ring. */
2844 tp
->rx_rcb_ptr
= sw_idx
;
2845 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0
+ TG3_64BIT_REG_LOW
, sw_idx
);
2847 /* Refill RX ring(s). */
2848 if (work_mask
& RXD_OPAQUE_RING_STD
) {
2849 sw_idx
= tp
->rx_std_ptr
% TG3_RX_RING_SIZE
;
2850 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX
+ TG3_64BIT_REG_LOW
,
2853 if (work_mask
& RXD_OPAQUE_RING_JUMBO
) {
2854 sw_idx
= tp
->rx_jumbo_ptr
% TG3_RX_JUMBO_RING_SIZE
;
2855 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX
+ TG3_64BIT_REG_LOW
,
2863 static int tg3_poll(struct net_device
*netdev
, int *budget
)
2865 struct tg3
*tp
= netdev_priv(netdev
);
2866 struct tg3_hw_status
*sblk
= tp
->hw_status
;
2867 unsigned long flags
;
2870 spin_lock_irqsave(&tp
->lock
, flags
);
2872 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)
2873 tp
->last_tag
= sblk
->status_tag
;
2875 /* handle link change and other phy events */
2876 if (!(tp
->tg3_flags
&
2877 (TG3_FLAG_USE_LINKCHG_REG
|
2878 TG3_FLAG_POLL_SERDES
))) {
2879 if (sblk
->status
& SD_STATUS_LINK_CHG
) {
2880 sblk
->status
= SD_STATUS_UPDATED
|
2881 (sblk
->status
& ~SD_STATUS_LINK_CHG
);
2882 tg3_setup_phy(tp
, 0);
2886 /* run TX completion thread */
2887 if (sblk
->idx
[0].tx_consumer
!= tp
->tx_cons
) {
2888 spin_lock(&tp
->tx_lock
);
2890 spin_unlock(&tp
->tx_lock
);
2893 spin_unlock_irqrestore(&tp
->lock
, flags
);
2895 /* run RX thread, within the bounds set by NAPI.
2896 * All RX "locking" is done by ensuring outside
2897 * code synchronizes with dev->poll()
2900 if (sblk
->idx
[0].rx_producer
!= tp
->rx_rcb_ptr
) {
2901 int orig_budget
= *budget
;
2904 if (orig_budget
> netdev
->quota
)
2905 orig_budget
= netdev
->quota
;
2907 work_done
= tg3_rx(tp
, orig_budget
);
2909 *budget
-= work_done
;
2910 netdev
->quota
-= work_done
;
2912 if (work_done
>= orig_budget
)
2916 /* if no more work, tell net stack and NIC we're done */
2918 spin_lock_irqsave(&tp
->lock
, flags
);
2919 __netif_rx_complete(netdev
);
2920 tg3_restart_ints(tp
);
2921 spin_unlock_irqrestore(&tp
->lock
, flags
);
2924 return (done
? 0 : 1);
2927 /* MSI ISR - No need to check for interrupt sharing and no need to
2928 * flush status block and interrupt mailbox. PCI ordering rules
2929 * guarantee that MSI will arrive after the status block.
2931 static irqreturn_t
tg3_msi(int irq
, void *dev_id
, struct pt_regs
*regs
)
2933 struct net_device
*dev
= dev_id
;
2934 struct tg3
*tp
= netdev_priv(dev
);
2935 struct tg3_hw_status
*sblk
= tp
->hw_status
;
2936 unsigned long flags
;
2938 spin_lock_irqsave(&tp
->lock
, flags
);
2941 * Writing any value to intr-mbox-0 clears PCI INTA# and
2942 * chip-internal interrupt pending events.
2943 * Writing non-zero to intr-mbox-0 additional tells the
2944 * NIC to stop sending us irqs, engaging "in-intr-handler"
2947 tw32_mailbox(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0x00000001);
2948 tp
->last_tag
= sblk
->status_tag
;
2949 sblk
->status
&= ~SD_STATUS_UPDATED
;
2950 if (likely(tg3_has_work(tp
)))
2951 netif_rx_schedule(dev
); /* schedule NAPI poll */
2953 /* No work, re-enable interrupts. */
2954 tw32_mailbox(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
,
2955 tp
->last_tag
<< 24);
2958 spin_unlock_irqrestore(&tp
->lock
, flags
);
2960 return IRQ_RETVAL(1);
2963 static irqreturn_t
tg3_interrupt(int irq
, void *dev_id
, struct pt_regs
*regs
)
2965 struct net_device
*dev
= dev_id
;
2966 struct tg3
*tp
= netdev_priv(dev
);
2967 struct tg3_hw_status
*sblk
= tp
->hw_status
;
2968 unsigned long flags
;
2969 unsigned int handled
= 1;
2971 spin_lock_irqsave(&tp
->lock
, flags
);
2973 /* In INTx mode, it is possible for the interrupt to arrive at
2974 * the CPU before the status block posted prior to the interrupt.
2975 * Reading the PCI State register will confirm whether the
2976 * interrupt is ours and will flush the status block.
2978 if ((sblk
->status
& SD_STATUS_UPDATED
) ||
2979 !(tr32(TG3PCI_PCISTATE
) & PCISTATE_INT_NOT_ACTIVE
)) {
2981 * Writing any value to intr-mbox-0 clears PCI INTA# and
2982 * chip-internal interrupt pending events.
2983 * Writing non-zero to intr-mbox-0 additional tells the
2984 * NIC to stop sending us irqs, engaging "in-intr-handler"
2987 tw32_mailbox(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
,
2989 sblk
->status
&= ~SD_STATUS_UPDATED
;
2990 if (likely(tg3_has_work(tp
)))
2991 netif_rx_schedule(dev
); /* schedule NAPI poll */
2993 /* No work, shared interrupt perhaps? re-enable
2994 * interrupts, and flush that PCI write
2996 tw32_mailbox(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
,
2998 tr32(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
);
3000 } else { /* shared interrupt */
3004 spin_unlock_irqrestore(&tp
->lock
, flags
);
3006 return IRQ_RETVAL(handled
);
3009 static irqreturn_t
tg3_interrupt_tagged(int irq
, void *dev_id
, struct pt_regs
*regs
)
3011 struct net_device
*dev
= dev_id
;
3012 struct tg3
*tp
= netdev_priv(dev
);
3013 struct tg3_hw_status
*sblk
= tp
->hw_status
;
3014 unsigned long flags
;
3015 unsigned int handled
= 1;
3017 spin_lock_irqsave(&tp
->lock
, flags
);
3019 /* In INTx mode, it is possible for the interrupt to arrive at
3020 * the CPU before the status block posted prior to the interrupt.
3021 * Reading the PCI State register will confirm whether the
3022 * interrupt is ours and will flush the status block.
3024 if ((sblk
->status
& SD_STATUS_UPDATED
) ||
3025 !(tr32(TG3PCI_PCISTATE
) & PCISTATE_INT_NOT_ACTIVE
)) {
3027 * writing any value to intr-mbox-0 clears PCI INTA# and
3028 * chip-internal interrupt pending events.
3029 * writing non-zero to intr-mbox-0 additional tells the
3030 * NIC to stop sending us irqs, engaging "in-intr-handler"
3033 tw32_mailbox(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
,
3035 tp
->last_tag
= sblk
->status_tag
;
3036 sblk
->status
&= ~SD_STATUS_UPDATED
;
3037 if (likely(tg3_has_work(tp
)))
3038 netif_rx_schedule(dev
); /* schedule NAPI poll */
3040 /* no work, shared interrupt perhaps? re-enable
3041 * interrupts, and flush that PCI write
3043 tw32_mailbox(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
,
3044 tp
->last_tag
<< 24);
3045 tr32(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
);
3047 } else { /* shared interrupt */
3051 spin_unlock_irqrestore(&tp
->lock
, flags
);
3053 return IRQ_RETVAL(handled
);
3056 /* ISR for interrupt test */
3057 static irqreturn_t
tg3_test_isr(int irq
, void *dev_id
,
3058 struct pt_regs
*regs
)
3060 struct net_device
*dev
= dev_id
;
3061 struct tg3
*tp
= netdev_priv(dev
);
3062 struct tg3_hw_status
*sblk
= tp
->hw_status
;
3064 if (sblk
->status
& SD_STATUS_UPDATED
) {
3065 tw32_mailbox(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
,
3067 return IRQ_RETVAL(1);
3069 return IRQ_RETVAL(0);
3072 static int tg3_init_hw(struct tg3
*);
3073 static int tg3_halt(struct tg3
*, int);
3075 #ifdef CONFIG_NET_POLL_CONTROLLER
3076 static void tg3_poll_controller(struct net_device
*dev
)
3078 struct tg3
*tp
= netdev_priv(dev
);
3080 tg3_interrupt(tp
->pdev
->irq
, dev
, NULL
);
3084 static void tg3_reset_task(void *_data
)
3086 struct tg3
*tp
= _data
;
3087 unsigned int restart_timer
;
3091 spin_lock_irq(&tp
->lock
);
3092 spin_lock(&tp
->tx_lock
);
3094 restart_timer
= tp
->tg3_flags2
& TG3_FLG2_RESTART_TIMER
;
3095 tp
->tg3_flags2
&= ~TG3_FLG2_RESTART_TIMER
;
3100 tg3_netif_start(tp
);
3102 spin_unlock(&tp
->tx_lock
);
3103 spin_unlock_irq(&tp
->lock
);
3106 mod_timer(&tp
->timer
, jiffies
+ 1);
3109 static void tg3_tx_timeout(struct net_device
*dev
)
3111 struct tg3
*tp
= netdev_priv(dev
);
3113 printk(KERN_ERR PFX
"%s: transmit timed out, resetting\n",
3116 schedule_work(&tp
->reset_task
);
3119 static void tg3_set_txd(struct tg3
*, int, dma_addr_t
, int, u32
, u32
);
3121 static int tigon3_4gb_hwbug_workaround(struct tg3
*tp
, struct sk_buff
*skb
,
3122 u32 guilty_entry
, int guilty_len
,
3123 u32 last_plus_one
, u32
*start
, u32 mss
)
3125 struct sk_buff
*new_skb
= skb_copy(skb
, GFP_ATOMIC
);
3126 dma_addr_t new_addr
;
3135 /* New SKB is guaranteed to be linear. */
3137 new_addr
= pci_map_single(tp
->pdev
, new_skb
->data
, new_skb
->len
,
3139 tg3_set_txd(tp
, entry
, new_addr
, new_skb
->len
,
3140 (skb
->ip_summed
== CHECKSUM_HW
) ?
3141 TXD_FLAG_TCPUDP_CSUM
: 0, 1 | (mss
<< 1));
3142 *start
= NEXT_TX(entry
);
3144 /* Now clean up the sw ring entries. */
3146 while (entry
!= last_plus_one
) {
3150 len
= skb_headlen(skb
);
3152 len
= skb_shinfo(skb
)->frags
[i
-1].size
;
3153 pci_unmap_single(tp
->pdev
,
3154 pci_unmap_addr(&tp
->tx_buffers
[entry
], mapping
),
3155 len
, PCI_DMA_TODEVICE
);
3157 tp
->tx_buffers
[entry
].skb
= new_skb
;
3158 pci_unmap_addr_set(&tp
->tx_buffers
[entry
], mapping
, new_addr
);
3160 tp
->tx_buffers
[entry
].skb
= NULL
;
3162 entry
= NEXT_TX(entry
);
3171 static void tg3_set_txd(struct tg3
*tp
, int entry
,
3172 dma_addr_t mapping
, int len
, u32 flags
,
3175 struct tg3_tx_buffer_desc
*txd
= &tp
->tx_ring
[entry
];
3176 int is_end
= (mss_and_is_end
& 0x1);
3177 u32 mss
= (mss_and_is_end
>> 1);
3181 flags
|= TXD_FLAG_END
;
3182 if (flags
& TXD_FLAG_VLAN
) {
3183 vlan_tag
= flags
>> 16;
3186 vlan_tag
|= (mss
<< TXD_MSS_SHIFT
);
3188 txd
->addr_hi
= ((u64
) mapping
>> 32);
3189 txd
->addr_lo
= ((u64
) mapping
& 0xffffffff);
3190 txd
->len_flags
= (len
<< TXD_LEN_SHIFT
) | flags
;
3191 txd
->vlan_tag
= vlan_tag
<< TXD_VLAN_TAG_SHIFT
;
3194 static inline int tg3_4g_overflow_test(dma_addr_t mapping
, int len
)
3196 u32 base
= (u32
) mapping
& 0xffffffff;
3198 return ((base
> 0xffffdcc0) &&
3199 (base
+ len
+ 8 < base
));
3202 static int tg3_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
3204 struct tg3
*tp
= netdev_priv(dev
);
3207 u32 len
, entry
, base_flags
, mss
;
3208 int would_hit_hwbug
;
3209 unsigned long flags
;
3211 len
= skb_headlen(skb
);
3213 /* No BH disabling for tx_lock here. We are running in BH disabled
3214 * context and TX reclaim runs via tp->poll inside of a software
3215 * interrupt. Rejoice!
3217 * Actually, things are not so simple. If we are to take a hw
3218 * IRQ here, we can deadlock, consider:
3227 * spin on tp->tx_lock
3229 * So we really do need to disable interrupts when taking
3232 local_irq_save(flags
);
3233 if (!spin_trylock(&tp
->tx_lock
)) {
3234 local_irq_restore(flags
);
3235 return NETDEV_TX_LOCKED
;
3238 /* This is a hard error, log it. */
3239 if (unlikely(TX_BUFFS_AVAIL(tp
) <= (skb_shinfo(skb
)->nr_frags
+ 1))) {
3240 netif_stop_queue(dev
);
3241 spin_unlock_irqrestore(&tp
->tx_lock
, flags
);
3242 printk(KERN_ERR PFX
"%s: BUG! Tx Ring full when queue awake!\n",
3244 return NETDEV_TX_BUSY
;
3247 entry
= tp
->tx_prod
;
3249 if (skb
->ip_summed
== CHECKSUM_HW
)
3250 base_flags
|= TXD_FLAG_TCPUDP_CSUM
;
3251 #if TG3_TSO_SUPPORT != 0
3253 if (skb
->len
> (tp
->dev
->mtu
+ ETH_HLEN
) &&
3254 (mss
= skb_shinfo(skb
)->tso_size
) != 0) {
3255 int tcp_opt_len
, ip_tcp_len
;
3257 if (skb_header_cloned(skb
) &&
3258 pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
)) {
3263 tcp_opt_len
= ((skb
->h
.th
->doff
- 5) * 4);
3264 ip_tcp_len
= (skb
->nh
.iph
->ihl
* 4) + sizeof(struct tcphdr
);
3266 base_flags
|= (TXD_FLAG_CPU_PRE_DMA
|
3267 TXD_FLAG_CPU_POST_DMA
);
3269 skb
->nh
.iph
->check
= 0;
3270 skb
->nh
.iph
->tot_len
= ntohs(mss
+ ip_tcp_len
+ tcp_opt_len
);
3271 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
) {
3272 skb
->h
.th
->check
= 0;
3273 base_flags
&= ~TXD_FLAG_TCPUDP_CSUM
;
3277 ~csum_tcpudp_magic(skb
->nh
.iph
->saddr
,
3282 if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO
) ||
3283 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
)) {
3284 if (tcp_opt_len
|| skb
->nh
.iph
->ihl
> 5) {
3287 tsflags
= ((skb
->nh
.iph
->ihl
- 5) +
3288 (tcp_opt_len
>> 2));
3289 mss
|= (tsflags
<< 11);
3292 if (tcp_opt_len
|| skb
->nh
.iph
->ihl
> 5) {
3295 tsflags
= ((skb
->nh
.iph
->ihl
- 5) +
3296 (tcp_opt_len
>> 2));
3297 base_flags
|= tsflags
<< 12;
3304 #if TG3_VLAN_TAG_USED
3305 if (tp
->vlgrp
!= NULL
&& vlan_tx_tag_present(skb
))
3306 base_flags
|= (TXD_FLAG_VLAN
|
3307 (vlan_tx_tag_get(skb
) << 16));
3310 /* Queue skb data, a.k.a. the main skb fragment. */
3311 mapping
= pci_map_single(tp
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
3313 tp
->tx_buffers
[entry
].skb
= skb
;
3314 pci_unmap_addr_set(&tp
->tx_buffers
[entry
], mapping
, mapping
);
3316 would_hit_hwbug
= 0;
3318 if (tg3_4g_overflow_test(mapping
, len
))
3319 would_hit_hwbug
= entry
+ 1;
3321 tg3_set_txd(tp
, entry
, mapping
, len
, base_flags
,
3322 (skb_shinfo(skb
)->nr_frags
== 0) | (mss
<< 1));
3324 entry
= NEXT_TX(entry
);
3326 /* Now loop through additional data fragments, and queue them. */
3327 if (skb_shinfo(skb
)->nr_frags
> 0) {
3328 unsigned int i
, last
;
3330 last
= skb_shinfo(skb
)->nr_frags
- 1;
3331 for (i
= 0; i
<= last
; i
++) {
3332 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
3335 mapping
= pci_map_page(tp
->pdev
,
3338 len
, PCI_DMA_TODEVICE
);
3340 tp
->tx_buffers
[entry
].skb
= NULL
;
3341 pci_unmap_addr_set(&tp
->tx_buffers
[entry
], mapping
, mapping
);
3343 if (tg3_4g_overflow_test(mapping
, len
)) {
3344 /* Only one should match. */
3345 if (would_hit_hwbug
)
3347 would_hit_hwbug
= entry
+ 1;
3350 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
3351 tg3_set_txd(tp
, entry
, mapping
, len
,
3352 base_flags
, (i
== last
)|(mss
<< 1));
3354 tg3_set_txd(tp
, entry
, mapping
, len
,
3355 base_flags
, (i
== last
));
3357 entry
= NEXT_TX(entry
);
3361 if (would_hit_hwbug
) {
3362 u32 last_plus_one
= entry
;
3364 unsigned int len
= 0;
3366 would_hit_hwbug
-= 1;
3367 entry
= entry
- 1 - skb_shinfo(skb
)->nr_frags
;
3368 entry
&= (TG3_TX_RING_SIZE
- 1);
3371 while (entry
!= last_plus_one
) {
3373 len
= skb_headlen(skb
);
3375 len
= skb_shinfo(skb
)->frags
[i
-1].size
;
3377 if (entry
== would_hit_hwbug
)
3381 entry
= NEXT_TX(entry
);
3385 /* If the workaround fails due to memory/mapping
3386 * failure, silently drop this packet.
3388 if (tigon3_4gb_hwbug_workaround(tp
, skb
,
3397 /* Packets are ready, update Tx producer idx local and on card. */
3398 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0
+ TG3_64BIT_REG_LOW
), entry
);
3400 tp
->tx_prod
= entry
;
3401 if (TX_BUFFS_AVAIL(tp
) <= (MAX_SKB_FRAGS
+ 1))
3402 netif_stop_queue(dev
);
3406 spin_unlock_irqrestore(&tp
->tx_lock
, flags
);
3408 dev
->trans_start
= jiffies
;
3410 return NETDEV_TX_OK
;
3413 static inline void tg3_set_mtu(struct net_device
*dev
, struct tg3
*tp
,
3418 if (new_mtu
> ETH_DATA_LEN
)
3419 tp
->tg3_flags
|= TG3_FLAG_JUMBO_ENABLE
;
3421 tp
->tg3_flags
&= ~TG3_FLAG_JUMBO_ENABLE
;
3424 static int tg3_change_mtu(struct net_device
*dev
, int new_mtu
)
3426 struct tg3
*tp
= netdev_priv(dev
);
3428 if (new_mtu
< TG3_MIN_MTU
|| new_mtu
> TG3_MAX_MTU(tp
))
3431 if (!netif_running(dev
)) {
3432 /* We'll just catch it later when the
3435 tg3_set_mtu(dev
, tp
, new_mtu
);
3440 spin_lock_irq(&tp
->lock
);
3441 spin_lock(&tp
->tx_lock
);
3445 tg3_set_mtu(dev
, tp
, new_mtu
);
3449 tg3_netif_start(tp
);
3451 spin_unlock(&tp
->tx_lock
);
3452 spin_unlock_irq(&tp
->lock
);
3457 /* Free up pending packets in all rx/tx rings.
3459 * The chip has been shut down and the driver detached from
3460 * the networking, so no interrupts or new tx packets will
3461 * end up in the driver. tp->{tx,}lock is not held and we are not
3462 * in an interrupt context and thus may sleep.
3464 static void tg3_free_rings(struct tg3
*tp
)
3466 struct ring_info
*rxp
;
3469 for (i
= 0; i
< TG3_RX_RING_SIZE
; i
++) {
3470 rxp
= &tp
->rx_std_buffers
[i
];
3472 if (rxp
->skb
== NULL
)
3474 pci_unmap_single(tp
->pdev
,
3475 pci_unmap_addr(rxp
, mapping
),
3476 RX_PKT_BUF_SZ
- tp
->rx_offset
,
3477 PCI_DMA_FROMDEVICE
);
3478 dev_kfree_skb_any(rxp
->skb
);
3482 for (i
= 0; i
< TG3_RX_JUMBO_RING_SIZE
; i
++) {
3483 rxp
= &tp
->rx_jumbo_buffers
[i
];
3485 if (rxp
->skb
== NULL
)
3487 pci_unmap_single(tp
->pdev
,
3488 pci_unmap_addr(rxp
, mapping
),
3489 RX_JUMBO_PKT_BUF_SZ
- tp
->rx_offset
,
3490 PCI_DMA_FROMDEVICE
);
3491 dev_kfree_skb_any(rxp
->skb
);
3495 for (i
= 0; i
< TG3_TX_RING_SIZE
; ) {
3496 struct tx_ring_info
*txp
;
3497 struct sk_buff
*skb
;
3500 txp
= &tp
->tx_buffers
[i
];
3508 pci_unmap_single(tp
->pdev
,
3509 pci_unmap_addr(txp
, mapping
),
3516 for (j
= 0; j
< skb_shinfo(skb
)->nr_frags
; j
++) {
3517 txp
= &tp
->tx_buffers
[i
& (TG3_TX_RING_SIZE
- 1)];
3518 pci_unmap_page(tp
->pdev
,
3519 pci_unmap_addr(txp
, mapping
),
3520 skb_shinfo(skb
)->frags
[j
].size
,
3525 dev_kfree_skb_any(skb
);
3529 /* Initialize tx/rx rings for packet processing.
3531 * The chip has been shut down and the driver detached from
3532 * the networking, so no interrupts or new tx packets will
3533 * end up in the driver. tp->{tx,}lock are held and thus
3536 static void tg3_init_rings(struct tg3
*tp
)
3540 /* Free up all the SKBs. */
3543 /* Zero out all descriptors. */
3544 memset(tp
->rx_std
, 0, TG3_RX_RING_BYTES
);
3545 memset(tp
->rx_jumbo
, 0, TG3_RX_JUMBO_RING_BYTES
);
3546 memset(tp
->rx_rcb
, 0, TG3_RX_RCB_RING_BYTES(tp
));
3547 memset(tp
->tx_ring
, 0, TG3_TX_RING_BYTES
);
3549 /* Initialize invariants of the rings, we only set this
3550 * stuff once. This works because the card does not
3551 * write into the rx buffer posting rings.
3553 for (i
= 0; i
< TG3_RX_RING_SIZE
; i
++) {
3554 struct tg3_rx_buffer_desc
*rxd
;
3556 rxd
= &tp
->rx_std
[i
];
3557 rxd
->idx_len
= (RX_PKT_BUF_SZ
- tp
->rx_offset
- 64)
3559 rxd
->type_flags
= (RXD_FLAG_END
<< RXD_FLAGS_SHIFT
);
3560 rxd
->opaque
= (RXD_OPAQUE_RING_STD
|
3561 (i
<< RXD_OPAQUE_INDEX_SHIFT
));
3564 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_ENABLE
) {
3565 for (i
= 0; i
< TG3_RX_JUMBO_RING_SIZE
; i
++) {
3566 struct tg3_rx_buffer_desc
*rxd
;
3568 rxd
= &tp
->rx_jumbo
[i
];
3569 rxd
->idx_len
= (RX_JUMBO_PKT_BUF_SZ
- tp
->rx_offset
- 64)
3571 rxd
->type_flags
= (RXD_FLAG_END
<< RXD_FLAGS_SHIFT
) |
3573 rxd
->opaque
= (RXD_OPAQUE_RING_JUMBO
|
3574 (i
<< RXD_OPAQUE_INDEX_SHIFT
));
3578 /* Now allocate fresh SKBs for each rx ring. */
3579 for (i
= 0; i
< tp
->rx_pending
; i
++) {
3580 if (tg3_alloc_rx_skb(tp
, RXD_OPAQUE_RING_STD
,
3585 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_ENABLE
) {
3586 for (i
= 0; i
< tp
->rx_jumbo_pending
; i
++) {
3587 if (tg3_alloc_rx_skb(tp
, RXD_OPAQUE_RING_JUMBO
,
3595 * Must not be invoked with interrupt sources disabled and
3596 * the hardware shutdown down.
3598 static void tg3_free_consistent(struct tg3
*tp
)
3600 if (tp
->rx_std_buffers
) {
3601 kfree(tp
->rx_std_buffers
);
3602 tp
->rx_std_buffers
= NULL
;
3605 pci_free_consistent(tp
->pdev
, TG3_RX_RING_BYTES
,
3606 tp
->rx_std
, tp
->rx_std_mapping
);
3610 pci_free_consistent(tp
->pdev
, TG3_RX_JUMBO_RING_BYTES
,
3611 tp
->rx_jumbo
, tp
->rx_jumbo_mapping
);
3612 tp
->rx_jumbo
= NULL
;
3615 pci_free_consistent(tp
->pdev
, TG3_RX_RCB_RING_BYTES(tp
),
3616 tp
->rx_rcb
, tp
->rx_rcb_mapping
);
3620 pci_free_consistent(tp
->pdev
, TG3_TX_RING_BYTES
,
3621 tp
->tx_ring
, tp
->tx_desc_mapping
);
3624 if (tp
->hw_status
) {
3625 pci_free_consistent(tp
->pdev
, TG3_HW_STATUS_SIZE
,
3626 tp
->hw_status
, tp
->status_mapping
);
3627 tp
->hw_status
= NULL
;
3630 pci_free_consistent(tp
->pdev
, sizeof(struct tg3_hw_stats
),
3631 tp
->hw_stats
, tp
->stats_mapping
);
3632 tp
->hw_stats
= NULL
;
3637 * Must not be invoked with interrupt sources disabled and
3638 * the hardware shutdown down. Can sleep.
3640 static int tg3_alloc_consistent(struct tg3
*tp
)
3642 tp
->rx_std_buffers
= kmalloc((sizeof(struct ring_info
) *
3644 TG3_RX_JUMBO_RING_SIZE
)) +
3645 (sizeof(struct tx_ring_info
) *
3648 if (!tp
->rx_std_buffers
)
3651 memset(tp
->rx_std_buffers
, 0,
3652 (sizeof(struct ring_info
) *
3654 TG3_RX_JUMBO_RING_SIZE
)) +
3655 (sizeof(struct tx_ring_info
) *
3658 tp
->rx_jumbo_buffers
= &tp
->rx_std_buffers
[TG3_RX_RING_SIZE
];
3659 tp
->tx_buffers
= (struct tx_ring_info
*)
3660 &tp
->rx_jumbo_buffers
[TG3_RX_JUMBO_RING_SIZE
];
3662 tp
->rx_std
= pci_alloc_consistent(tp
->pdev
, TG3_RX_RING_BYTES
,
3663 &tp
->rx_std_mapping
);
3667 tp
->rx_jumbo
= pci_alloc_consistent(tp
->pdev
, TG3_RX_JUMBO_RING_BYTES
,
3668 &tp
->rx_jumbo_mapping
);
3673 tp
->rx_rcb
= pci_alloc_consistent(tp
->pdev
, TG3_RX_RCB_RING_BYTES(tp
),
3674 &tp
->rx_rcb_mapping
);
3678 tp
->tx_ring
= pci_alloc_consistent(tp
->pdev
, TG3_TX_RING_BYTES
,
3679 &tp
->tx_desc_mapping
);
3683 tp
->hw_status
= pci_alloc_consistent(tp
->pdev
,
3685 &tp
->status_mapping
);
3689 tp
->hw_stats
= pci_alloc_consistent(tp
->pdev
,
3690 sizeof(struct tg3_hw_stats
),
3691 &tp
->stats_mapping
);
3695 memset(tp
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
3696 memset(tp
->hw_stats
, 0, sizeof(struct tg3_hw_stats
));
3701 tg3_free_consistent(tp
);
3705 #define MAX_WAIT_CNT 1000
3707 /* To stop a block, clear the enable bit and poll till it
3708 * clears. tp->lock is held.
3710 static int tg3_stop_block(struct tg3
*tp
, unsigned long ofs
, u32 enable_bit
, int silent
)
3715 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
3722 /* We can't enable/disable these bits of the
3723 * 5705/5750, just say success.
3736 for (i
= 0; i
< MAX_WAIT_CNT
; i
++) {
3739 if ((val
& enable_bit
) == 0)
3743 if (i
== MAX_WAIT_CNT
&& !silent
) {
3744 printk(KERN_ERR PFX
"tg3_stop_block timed out, "
3745 "ofs=%lx enable_bit=%x\n",
3753 /* tp->lock is held. */
3754 static int tg3_abort_hw(struct tg3
*tp
, int silent
)
3758 tg3_disable_ints(tp
);
3760 tp
->rx_mode
&= ~RX_MODE_ENABLE
;
3761 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
3764 err
= tg3_stop_block(tp
, RCVBDI_MODE
, RCVBDI_MODE_ENABLE
, silent
);
3765 err
|= tg3_stop_block(tp
, RCVLPC_MODE
, RCVLPC_MODE_ENABLE
, silent
);
3766 err
|= tg3_stop_block(tp
, RCVLSC_MODE
, RCVLSC_MODE_ENABLE
, silent
);
3767 err
|= tg3_stop_block(tp
, RCVDBDI_MODE
, RCVDBDI_MODE_ENABLE
, silent
);
3768 err
|= tg3_stop_block(tp
, RCVDCC_MODE
, RCVDCC_MODE_ENABLE
, silent
);
3769 err
|= tg3_stop_block(tp
, RCVCC_MODE
, RCVCC_MODE_ENABLE
, silent
);
3771 err
|= tg3_stop_block(tp
, SNDBDS_MODE
, SNDBDS_MODE_ENABLE
, silent
);
3772 err
|= tg3_stop_block(tp
, SNDBDI_MODE
, SNDBDI_MODE_ENABLE
, silent
);
3773 err
|= tg3_stop_block(tp
, SNDDATAI_MODE
, SNDDATAI_MODE_ENABLE
, silent
);
3774 err
|= tg3_stop_block(tp
, RDMAC_MODE
, RDMAC_MODE_ENABLE
, silent
);
3775 err
|= tg3_stop_block(tp
, SNDDATAC_MODE
, SNDDATAC_MODE_ENABLE
, silent
);
3776 err
|= tg3_stop_block(tp
, DMAC_MODE
, DMAC_MODE_ENABLE
, silent
);
3777 err
|= tg3_stop_block(tp
, SNDBDC_MODE
, SNDBDC_MODE_ENABLE
, silent
);
3779 tp
->mac_mode
&= ~MAC_MODE_TDE_ENABLE
;
3780 tw32_f(MAC_MODE
, tp
->mac_mode
);
3783 tp
->tx_mode
&= ~TX_MODE_ENABLE
;
3784 tw32_f(MAC_TX_MODE
, tp
->tx_mode
);
3786 for (i
= 0; i
< MAX_WAIT_CNT
; i
++) {
3788 if (!(tr32(MAC_TX_MODE
) & TX_MODE_ENABLE
))
3791 if (i
>= MAX_WAIT_CNT
) {
3792 printk(KERN_ERR PFX
"tg3_abort_hw timed out for %s, "
3793 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
3794 tp
->dev
->name
, tr32(MAC_TX_MODE
));
3798 err
|= tg3_stop_block(tp
, HOSTCC_MODE
, HOSTCC_MODE_ENABLE
, silent
);
3799 err
|= tg3_stop_block(tp
, WDMAC_MODE
, WDMAC_MODE_ENABLE
, silent
);
3800 err
|= tg3_stop_block(tp
, MBFREE_MODE
, MBFREE_MODE_ENABLE
, silent
);
3802 tw32(FTQ_RESET
, 0xffffffff);
3803 tw32(FTQ_RESET
, 0x00000000);
3805 err
|= tg3_stop_block(tp
, BUFMGR_MODE
, BUFMGR_MODE_ENABLE
, silent
);
3806 err
|= tg3_stop_block(tp
, MEMARB_MODE
, MEMARB_MODE_ENABLE
, silent
);
3809 memset(tp
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
3811 memset(tp
->hw_stats
, 0, sizeof(struct tg3_hw_stats
));
3816 /* tp->lock is held. */
3817 static int tg3_nvram_lock(struct tg3
*tp
)
3819 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
) {
3822 tw32(NVRAM_SWARB
, SWARB_REQ_SET1
);
3823 for (i
= 0; i
< 8000; i
++) {
3824 if (tr32(NVRAM_SWARB
) & SWARB_GNT1
)
3834 /* tp->lock is held. */
3835 static void tg3_nvram_unlock(struct tg3
*tp
)
3837 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
)
3838 tw32_f(NVRAM_SWARB
, SWARB_REQ_CLR1
);
3841 /* tp->lock is held. */
3842 static void tg3_enable_nvram_access(struct tg3
*tp
)
3844 if ((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
3845 !(tp
->tg3_flags2
& TG3_FLG2_PROTECTED_NVRAM
)) {
3846 u32 nvaccess
= tr32(NVRAM_ACCESS
);
3848 tw32(NVRAM_ACCESS
, nvaccess
| ACCESS_ENABLE
);
3852 /* tp->lock is held. */
3853 static void tg3_disable_nvram_access(struct tg3
*tp
)
3855 if ((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
3856 !(tp
->tg3_flags2
& TG3_FLG2_PROTECTED_NVRAM
)) {
3857 u32 nvaccess
= tr32(NVRAM_ACCESS
);
3859 tw32(NVRAM_ACCESS
, nvaccess
& ~ACCESS_ENABLE
);
3863 /* tp->lock is held. */
3864 static void tg3_write_sig_pre_reset(struct tg3
*tp
, int kind
)
3866 if (!(tp
->tg3_flags2
& TG3_FLG2_SUN_570X
))
3867 tg3_write_mem(tp
, NIC_SRAM_FIRMWARE_MBOX
,
3868 NIC_SRAM_FIRMWARE_MBOX_MAGIC1
);
3870 if (tp
->tg3_flags2
& TG3_FLG2_ASF_NEW_HANDSHAKE
) {
3872 case RESET_KIND_INIT
:
3873 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
3877 case RESET_KIND_SHUTDOWN
:
3878 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
3882 case RESET_KIND_SUSPEND
:
3883 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
3893 /* tp->lock is held. */
3894 static void tg3_write_sig_post_reset(struct tg3
*tp
, int kind
)
3896 if (tp
->tg3_flags2
& TG3_FLG2_ASF_NEW_HANDSHAKE
) {
3898 case RESET_KIND_INIT
:
3899 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
3900 DRV_STATE_START_DONE
);
3903 case RESET_KIND_SHUTDOWN
:
3904 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
3905 DRV_STATE_UNLOAD_DONE
);
3914 /* tp->lock is held. */
3915 static void tg3_write_sig_legacy(struct tg3
*tp
, int kind
)
3917 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) {
3919 case RESET_KIND_INIT
:
3920 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
3924 case RESET_KIND_SHUTDOWN
:
3925 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
3929 case RESET_KIND_SUSPEND
:
3930 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
3940 static void tg3_stop_fw(struct tg3
*);
3942 /* tp->lock is held. */
3943 static int tg3_chip_reset(struct tg3
*tp
)
3949 if (!(tp
->tg3_flags2
& TG3_FLG2_SUN_570X
))
3953 * We must avoid the readl() that normally takes place.
3954 * It locks machines, causes machine checks, and other
3955 * fun things. So, temporarily disable the 5701
3956 * hardware workaround, while we do the reset.
3958 flags_save
= tp
->tg3_flags
;
3959 tp
->tg3_flags
&= ~TG3_FLAG_5701_REG_WRITE_BUG
;
3962 val
= GRC_MISC_CFG_CORECLK_RESET
;
3964 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
3965 if (tr32(0x7e2c) == 0x60) {
3968 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
) {
3969 tw32(GRC_MISC_CFG
, (1 << 29));
3974 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
3975 val
|= GRC_MISC_CFG_KEEP_GPHY_POWER
;
3976 tw32(GRC_MISC_CFG
, val
);
3978 /* restore 5701 hardware bug workaround flag */
3979 tp
->tg3_flags
= flags_save
;
3981 /* Unfortunately, we have to delay before the PCI read back.
3982 * Some 575X chips even will not respond to a PCI cfg access
3983 * when the reset command is given to the chip.
3985 * How do these hardware designers expect things to work
3986 * properly if the PCI write is posted for a long period
3987 * of time? It is always necessary to have some method by
3988 * which a register read back can occur to push the write
3989 * out which does the reset.
3991 * For most tg3 variants the trick below was working.
3996 /* Flush PCI posted writes. The normal MMIO registers
3997 * are inaccessible at this time so this is the only
3998 * way to make this reliably (actually, this is no longer
3999 * the case, see above). I tried to use indirect
4000 * register read/write but this upset some 5701 variants.
4002 pci_read_config_dword(tp
->pdev
, PCI_COMMAND
, &val
);
4006 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
4007 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5750_A0
) {
4011 /* Wait for link training to complete. */
4012 for (i
= 0; i
< 5000; i
++)
4015 pci_read_config_dword(tp
->pdev
, 0xc4, &cfg_val
);
4016 pci_write_config_dword(tp
->pdev
, 0xc4,
4017 cfg_val
| (1 << 15));
4019 /* Set PCIE max payload size and clear error status. */
4020 pci_write_config_dword(tp
->pdev
, 0xd8, 0xf5000);
4023 /* Re-enable indirect register accesses. */
4024 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
4025 tp
->misc_host_ctrl
);
4027 /* Set MAX PCI retry to zero. */
4028 val
= (PCISTATE_ROM_ENABLE
| PCISTATE_ROM_RETRY_ENABLE
);
4029 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
&&
4030 (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
))
4031 val
|= PCISTATE_RETRY_SAME_DMA
;
4032 pci_write_config_dword(tp
->pdev
, TG3PCI_PCISTATE
, val
);
4034 pci_restore_state(tp
->pdev
);
4036 /* Make sure PCI-X relaxed ordering bit is clear. */
4037 pci_read_config_dword(tp
->pdev
, TG3PCI_X_CAPS
, &val
);
4038 val
&= ~PCIX_CAPS_RELAXED_ORDERING
;
4039 pci_write_config_dword(tp
->pdev
, TG3PCI_X_CAPS
, val
);
4041 tw32(MEMARB_MODE
, MEMARB_MODE_ENABLE
);
4043 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5750_A3
) {
4045 tw32(0x5000, 0x400);
4048 tw32(GRC_MODE
, tp
->grc_mode
);
4050 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A0
) {
4051 u32 val
= tr32(0xc4);
4053 tw32(0xc4, val
| (1 << 15));
4056 if ((tp
->nic_sram_data_cfg
& NIC_SRAM_DATA_CFG_MINI_PCI
) != 0 &&
4057 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
4058 tp
->pci_clock_ctrl
|= CLOCK_CTRL_CLKRUN_OENABLE
;
4059 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A0
)
4060 tp
->pci_clock_ctrl
|= CLOCK_CTRL_FORCE_CLKRUN
;
4061 tw32(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
);
4064 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
4065 tp
->mac_mode
= MAC_MODE_PORT_MODE_TBI
;
4066 tw32_f(MAC_MODE
, tp
->mac_mode
);
4068 tw32_f(MAC_MODE
, 0);
4071 if (!(tp
->tg3_flags2
& TG3_FLG2_SUN_570X
)) {
4072 /* Wait for firmware initialization to complete. */
4073 for (i
= 0; i
< 100000; i
++) {
4074 tg3_read_mem(tp
, NIC_SRAM_FIRMWARE_MBOX
, &val
);
4075 if (val
== ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1
)
4080 printk(KERN_ERR PFX
"tg3_reset_hw timed out for %s, "
4081 "firmware will not restart magic=%08x\n",
4082 tp
->dev
->name
, val
);
4087 if ((tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) &&
4088 tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
) {
4089 u32 val
= tr32(0x7c00);
4091 tw32(0x7c00, val
| (1 << 25));
4094 /* Reprobe ASF enable state. */
4095 tp
->tg3_flags
&= ~TG3_FLAG_ENABLE_ASF
;
4096 tp
->tg3_flags2
&= ~TG3_FLG2_ASF_NEW_HANDSHAKE
;
4097 tg3_read_mem(tp
, NIC_SRAM_DATA_SIG
, &val
);
4098 if (val
== NIC_SRAM_DATA_SIG_MAGIC
) {
4101 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG
, &nic_cfg
);
4102 if (nic_cfg
& NIC_SRAM_DATA_CFG_ASF_ENABLE
) {
4103 tp
->tg3_flags
|= TG3_FLAG_ENABLE_ASF
;
4104 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
4105 tp
->tg3_flags2
|= TG3_FLG2_ASF_NEW_HANDSHAKE
;
4112 /* tp->lock is held. */
4113 static void tg3_stop_fw(struct tg3
*tp
)
4115 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) {
4119 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_MBOX
, FWCMD_NICDRV_PAUSE_FW
);
4120 val
= tr32(GRC_RX_CPU_EVENT
);
4122 tw32(GRC_RX_CPU_EVENT
, val
);
4124 /* Wait for RX cpu to ACK the event. */
4125 for (i
= 0; i
< 100; i
++) {
4126 if (!(tr32(GRC_RX_CPU_EVENT
) & (1 << 14)))
4133 /* tp->lock is held. */
4134 static int tg3_halt(struct tg3
*tp
, int silent
)
4140 tg3_write_sig_pre_reset(tp
, RESET_KIND_SHUTDOWN
);
4142 tg3_abort_hw(tp
, silent
);
4143 err
= tg3_chip_reset(tp
);
4145 tg3_write_sig_legacy(tp
, RESET_KIND_SHUTDOWN
);
4146 tg3_write_sig_post_reset(tp
, RESET_KIND_SHUTDOWN
);
4154 #define TG3_FW_RELEASE_MAJOR 0x0
4155 #define TG3_FW_RELASE_MINOR 0x0
4156 #define TG3_FW_RELEASE_FIX 0x0
4157 #define TG3_FW_START_ADDR 0x08000000
4158 #define TG3_FW_TEXT_ADDR 0x08000000
4159 #define TG3_FW_TEXT_LEN 0x9c0
4160 #define TG3_FW_RODATA_ADDR 0x080009c0
4161 #define TG3_FW_RODATA_LEN 0x60
4162 #define TG3_FW_DATA_ADDR 0x08000a40
4163 #define TG3_FW_DATA_LEN 0x20
4164 #define TG3_FW_SBSS_ADDR 0x08000a60
4165 #define TG3_FW_SBSS_LEN 0xc
4166 #define TG3_FW_BSS_ADDR 0x08000a70
4167 #define TG3_FW_BSS_LEN 0x10
4169 static u32 tg3FwText
[(TG3_FW_TEXT_LEN
/ sizeof(u32
)) + 1] = {
4170 0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
4171 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
4172 0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
4173 0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
4174 0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
4175 0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
4176 0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
4177 0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
4178 0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
4179 0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
4180 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
4181 0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
4182 0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
4183 0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
4184 0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
4185 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
4186 0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
4187 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
4188 0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
4189 0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
4190 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
4191 0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
4192 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
4193 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4194 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4196 0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
4197 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4198 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4199 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4200 0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
4201 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
4202 0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
4203 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
4204 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4205 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4206 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
4207 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4208 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4209 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4210 0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
4211 0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
4212 0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
4213 0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
4214 0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
4215 0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
4216 0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
4217 0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
4218 0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
4219 0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
4220 0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
4221 0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
4222 0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
4223 0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
4224 0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
4225 0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
4226 0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
4227 0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
4228 0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
4229 0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
4230 0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
4231 0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
4232 0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
4233 0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
4234 0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
4235 0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
4236 0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
4237 0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
4238 0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
4239 0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
4240 0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
4241 0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
4242 0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
4243 0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
4244 0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
4245 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
4246 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
4247 0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
4248 0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
4249 0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
4250 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
4251 0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
4252 0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
4253 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
4254 0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
4255 0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
4256 0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
4257 0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
4258 0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
4259 0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
4260 0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
4263 static u32 tg3FwRodata
[(TG3_FW_RODATA_LEN
/ sizeof(u32
)) + 1] = {
4264 0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
4265 0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
4266 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
4267 0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
4271 #if 0 /* All zeros, don't eat up space with it. */
4272 u32 tg3FwData
[(TG3_FW_DATA_LEN
/ sizeof(u32
)) + 1] = {
4273 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4274 0x00000000, 0x00000000, 0x00000000, 0x00000000
4278 #define RX_CPU_SCRATCH_BASE 0x30000
4279 #define RX_CPU_SCRATCH_SIZE 0x04000
4280 #define TX_CPU_SCRATCH_BASE 0x34000
4281 #define TX_CPU_SCRATCH_SIZE 0x04000
4283 /* tp->lock is held. */
4284 static int tg3_halt_cpu(struct tg3
*tp
, u32 offset
)
4288 if (offset
== TX_CPU_BASE
&&
4289 (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
4292 if (offset
== RX_CPU_BASE
) {
4293 for (i
= 0; i
< 10000; i
++) {
4294 tw32(offset
+ CPU_STATE
, 0xffffffff);
4295 tw32(offset
+ CPU_MODE
, CPU_MODE_HALT
);
4296 if (tr32(offset
+ CPU_MODE
) & CPU_MODE_HALT
)
4300 tw32(offset
+ CPU_STATE
, 0xffffffff);
4301 tw32_f(offset
+ CPU_MODE
, CPU_MODE_HALT
);
4304 for (i
= 0; i
< 10000; i
++) {
4305 tw32(offset
+ CPU_STATE
, 0xffffffff);
4306 tw32(offset
+ CPU_MODE
, CPU_MODE_HALT
);
4307 if (tr32(offset
+ CPU_MODE
) & CPU_MODE_HALT
)
4313 printk(KERN_ERR PFX
"tg3_reset_cpu timed out for %s, "
4316 (offset
== RX_CPU_BASE
? "RX" : "TX"));
4323 unsigned int text_base
;
4324 unsigned int text_len
;
4326 unsigned int rodata_base
;
4327 unsigned int rodata_len
;
4329 unsigned int data_base
;
4330 unsigned int data_len
;
4334 /* tp->lock is held. */
4335 static int tg3_load_firmware_cpu(struct tg3
*tp
, u32 cpu_base
, u32 cpu_scratch_base
,
4336 int cpu_scratch_size
, struct fw_info
*info
)
4339 u32 orig_tg3_flags
= tp
->tg3_flags
;
4340 void (*write_op
)(struct tg3
*, u32
, u32
);
4342 if (cpu_base
== TX_CPU_BASE
&&
4343 (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
4344 printk(KERN_ERR PFX
"tg3_load_firmware_cpu: Trying to load "
4345 "TX cpu firmware on %s which is 5705.\n",
4350 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
4351 write_op
= tg3_write_mem
;
4353 write_op
= tg3_write_indirect_reg32
;
4355 /* Force use of PCI config space for indirect register
4358 tp
->tg3_flags
|= TG3_FLAG_PCIX_TARGET_HWBUG
;
4360 err
= tg3_halt_cpu(tp
, cpu_base
);
4364 for (i
= 0; i
< cpu_scratch_size
; i
+= sizeof(u32
))
4365 write_op(tp
, cpu_scratch_base
+ i
, 0);
4366 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
4367 tw32(cpu_base
+ CPU_MODE
, tr32(cpu_base
+CPU_MODE
)|CPU_MODE_HALT
);
4368 for (i
= 0; i
< (info
->text_len
/ sizeof(u32
)); i
++)
4369 write_op(tp
, (cpu_scratch_base
+
4370 (info
->text_base
& 0xffff) +
4373 info
->text_data
[i
] : 0));
4374 for (i
= 0; i
< (info
->rodata_len
/ sizeof(u32
)); i
++)
4375 write_op(tp
, (cpu_scratch_base
+
4376 (info
->rodata_base
& 0xffff) +
4378 (info
->rodata_data
?
4379 info
->rodata_data
[i
] : 0));
4380 for (i
= 0; i
< (info
->data_len
/ sizeof(u32
)); i
++)
4381 write_op(tp
, (cpu_scratch_base
+
4382 (info
->data_base
& 0xffff) +
4385 info
->data_data
[i
] : 0));
4390 tp
->tg3_flags
= orig_tg3_flags
;
4394 /* tp->lock is held. */
4395 static int tg3_load_5701_a0_firmware_fix(struct tg3
*tp
)
4397 struct fw_info info
;
4400 info
.text_base
= TG3_FW_TEXT_ADDR
;
4401 info
.text_len
= TG3_FW_TEXT_LEN
;
4402 info
.text_data
= &tg3FwText
[0];
4403 info
.rodata_base
= TG3_FW_RODATA_ADDR
;
4404 info
.rodata_len
= TG3_FW_RODATA_LEN
;
4405 info
.rodata_data
= &tg3FwRodata
[0];
4406 info
.data_base
= TG3_FW_DATA_ADDR
;
4407 info
.data_len
= TG3_FW_DATA_LEN
;
4408 info
.data_data
= NULL
;
4410 err
= tg3_load_firmware_cpu(tp
, RX_CPU_BASE
,
4411 RX_CPU_SCRATCH_BASE
, RX_CPU_SCRATCH_SIZE
,
4416 err
= tg3_load_firmware_cpu(tp
, TX_CPU_BASE
,
4417 TX_CPU_SCRATCH_BASE
, TX_CPU_SCRATCH_SIZE
,
4422 /* Now startup only the RX cpu. */
4423 tw32(RX_CPU_BASE
+ CPU_STATE
, 0xffffffff);
4424 tw32_f(RX_CPU_BASE
+ CPU_PC
, TG3_FW_TEXT_ADDR
);
4426 for (i
= 0; i
< 5; i
++) {
4427 if (tr32(RX_CPU_BASE
+ CPU_PC
) == TG3_FW_TEXT_ADDR
)
4429 tw32(RX_CPU_BASE
+ CPU_STATE
, 0xffffffff);
4430 tw32(RX_CPU_BASE
+ CPU_MODE
, CPU_MODE_HALT
);
4431 tw32_f(RX_CPU_BASE
+ CPU_PC
, TG3_FW_TEXT_ADDR
);
4435 printk(KERN_ERR PFX
"tg3_load_firmware fails for %s "
4436 "to set RX CPU PC, is %08x should be %08x\n",
4437 tp
->dev
->name
, tr32(RX_CPU_BASE
+ CPU_PC
),
4441 tw32(RX_CPU_BASE
+ CPU_STATE
, 0xffffffff);
4442 tw32_f(RX_CPU_BASE
+ CPU_MODE
, 0x00000000);
4447 #if TG3_TSO_SUPPORT != 0
4449 #define TG3_TSO_FW_RELEASE_MAJOR 0x1
4450 #define TG3_TSO_FW_RELASE_MINOR 0x6
4451 #define TG3_TSO_FW_RELEASE_FIX 0x0
4452 #define TG3_TSO_FW_START_ADDR 0x08000000
4453 #define TG3_TSO_FW_TEXT_ADDR 0x08000000
4454 #define TG3_TSO_FW_TEXT_LEN 0x1aa0
4455 #define TG3_TSO_FW_RODATA_ADDR 0x08001aa0
4456 #define TG3_TSO_FW_RODATA_LEN 0x60
4457 #define TG3_TSO_FW_DATA_ADDR 0x08001b20
4458 #define TG3_TSO_FW_DATA_LEN 0x30
4459 #define TG3_TSO_FW_SBSS_ADDR 0x08001b50
4460 #define TG3_TSO_FW_SBSS_LEN 0x2c
4461 #define TG3_TSO_FW_BSS_ADDR 0x08001b80
4462 #define TG3_TSO_FW_BSS_LEN 0x894
4464 static u32 tg3TsoFwText
[(TG3_TSO_FW_TEXT_LEN
/ 4) + 1] = {
4465 0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
4466 0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
4467 0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
4468 0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
4469 0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
4470 0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
4471 0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
4472 0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
4473 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
4474 0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
4475 0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
4476 0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
4477 0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
4478 0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
4479 0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
4480 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
4481 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
4482 0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
4483 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
4484 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
4485 0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
4486 0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
4487 0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
4488 0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
4489 0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
4490 0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
4491 0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
4492 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
4493 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
4494 0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
4495 0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
4496 0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
4497 0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
4498 0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
4499 0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
4500 0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
4501 0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
4502 0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
4503 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
4504 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
4505 0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
4506 0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
4507 0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
4508 0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
4509 0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
4510 0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
4511 0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
4512 0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
4513 0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
4514 0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
4515 0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
4516 0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
4517 0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
4518 0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
4519 0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
4520 0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
4521 0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
4522 0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
4523 0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
4524 0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
4525 0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
4526 0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
4527 0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
4528 0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
4529 0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
4530 0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
4531 0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
4532 0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
4533 0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
4534 0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
4535 0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
4536 0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
4537 0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
4538 0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
4539 0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
4540 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
4541 0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
4542 0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
4543 0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
4544 0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
4545 0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
4546 0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
4547 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
4548 0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
4549 0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
4550 0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
4551 0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
4552 0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
4553 0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
4554 0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
4555 0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
4556 0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
4557 0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
4558 0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
4559 0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
4560 0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
4561 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
4562 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
4563 0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
4564 0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
4565 0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
4566 0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
4567 0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
4568 0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
4569 0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
4570 0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
4571 0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
4572 0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
4573 0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
4574 0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
4575 0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
4576 0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
4577 0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
4578 0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
4579 0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
4580 0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
4581 0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
4582 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
4583 0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
4584 0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
4585 0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
4586 0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
4587 0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
4588 0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
4589 0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
4590 0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
4591 0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
4592 0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
4593 0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
4594 0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
4595 0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
4596 0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
4597 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
4598 0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
4599 0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
4600 0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
4601 0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
4602 0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
4603 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
4604 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
4605 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
4606 0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
4607 0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
4608 0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
4609 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
4610 0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
4611 0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
4612 0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
4613 0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
4614 0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
4615 0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
4616 0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
4617 0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
4618 0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
4619 0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
4620 0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
4621 0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
4622 0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
4623 0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
4624 0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
4625 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
4626 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
4627 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
4628 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
4629 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
4630 0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
4631 0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
4632 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
4633 0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
4634 0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
4635 0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
4636 0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
4637 0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
4638 0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
4639 0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
4640 0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
4641 0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
4642 0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
4643 0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
4644 0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
4645 0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
4646 0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
4647 0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
4648 0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
4649 0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
4650 0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
4651 0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
4652 0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
4653 0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
4654 0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
4655 0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
4656 0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
4657 0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
4658 0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
4659 0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
4660 0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
4661 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
4662 0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
4663 0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
4664 0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
4665 0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
4666 0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
4667 0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
4668 0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
4669 0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
4670 0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
4671 0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
4672 0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
4673 0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
4674 0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
4675 0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
4676 0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
4677 0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
4678 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
4679 0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
4680 0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
4681 0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
4682 0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
4683 0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
4684 0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
4685 0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
4686 0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
4687 0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
4688 0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
4689 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
4690 0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
4691 0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
4692 0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
4693 0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
4694 0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
4695 0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
4696 0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
4697 0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
4698 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
4699 0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
4700 0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
4701 0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
4702 0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
4703 0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
4704 0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
4705 0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
4706 0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
4707 0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
4708 0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
4709 0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
4710 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
4711 0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
4712 0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
4713 0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
4714 0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
4715 0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
4716 0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
4717 0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
4718 0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
4719 0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
4720 0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
4721 0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
4722 0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
4723 0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
4724 0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
4725 0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
4726 0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
4727 0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
4728 0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
4729 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
4730 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
4731 0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
4732 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
4733 0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
4734 0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
4735 0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
4736 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
4737 0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
4738 0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
4739 0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
4740 0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
4741 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
4742 0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
4743 0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
4744 0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
4745 0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
4746 0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
4747 0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
4748 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
4751 static u32 tg3TsoFwRodata
[] = {
4752 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
4753 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
4754 0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
4755 0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
4759 static u32 tg3TsoFwData
[] = {
4760 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
4761 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4765 /* 5705 needs a special version of the TSO firmware. */
4766 #define TG3_TSO5_FW_RELEASE_MAJOR 0x1
4767 #define TG3_TSO5_FW_RELASE_MINOR 0x2
4768 #define TG3_TSO5_FW_RELEASE_FIX 0x0
4769 #define TG3_TSO5_FW_START_ADDR 0x00010000
4770 #define TG3_TSO5_FW_TEXT_ADDR 0x00010000
4771 #define TG3_TSO5_FW_TEXT_LEN 0xe90
4772 #define TG3_TSO5_FW_RODATA_ADDR 0x00010e90
4773 #define TG3_TSO5_FW_RODATA_LEN 0x50
4774 #define TG3_TSO5_FW_DATA_ADDR 0x00010f00
4775 #define TG3_TSO5_FW_DATA_LEN 0x20
4776 #define TG3_TSO5_FW_SBSS_ADDR 0x00010f20
4777 #define TG3_TSO5_FW_SBSS_LEN 0x28
4778 #define TG3_TSO5_FW_BSS_ADDR 0x00010f50
4779 #define TG3_TSO5_FW_BSS_LEN 0x88
4781 static u32 tg3Tso5FwText
[(TG3_TSO5_FW_TEXT_LEN
/ 4) + 1] = {
4782 0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
4783 0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
4784 0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
4785 0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
4786 0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
4787 0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
4788 0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
4789 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
4790 0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
4791 0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
4792 0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
4793 0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
4794 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
4795 0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
4796 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
4797 0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
4798 0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
4799 0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
4800 0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
4801 0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
4802 0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
4803 0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
4804 0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
4805 0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
4806 0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
4807 0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
4808 0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
4809 0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
4810 0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
4811 0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
4812 0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
4813 0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
4814 0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
4815 0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
4816 0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
4817 0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
4818 0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
4819 0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
4820 0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
4821 0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
4822 0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
4823 0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
4824 0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
4825 0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
4826 0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
4827 0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
4828 0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
4829 0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
4830 0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
4831 0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
4832 0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
4833 0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
4834 0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
4835 0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
4836 0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
4837 0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
4838 0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
4839 0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
4840 0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
4841 0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
4842 0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
4843 0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
4844 0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
4845 0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
4846 0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
4847 0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
4848 0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
4849 0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
4850 0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
4851 0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
4852 0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
4853 0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
4854 0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
4855 0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
4856 0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
4857 0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
4858 0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
4859 0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
4860 0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
4861 0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
4862 0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
4863 0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
4864 0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
4865 0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
4866 0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
4867 0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
4868 0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
4869 0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
4870 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
4871 0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
4872 0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
4873 0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
4874 0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
4875 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
4876 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
4877 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
4878 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
4879 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
4880 0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
4881 0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
4882 0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
4883 0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
4884 0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
4885 0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
4886 0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
4887 0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
4888 0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
4889 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
4890 0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
4891 0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
4892 0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
4893 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
4894 0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
4895 0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
4896 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
4897 0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
4898 0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
4899 0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
4900 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
4901 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
4902 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
4903 0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
4904 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
4905 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
4906 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
4907 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
4908 0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
4909 0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
4910 0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
4911 0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
4912 0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
4913 0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
4914 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
4915 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
4916 0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
4917 0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
4918 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
4919 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
4920 0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
4921 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
4922 0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
4923 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
4924 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
4925 0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
4926 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
4927 0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
4928 0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
4929 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
4930 0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
4931 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
4932 0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
4933 0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
4934 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
4935 0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
4936 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
4937 0x00000000, 0x00000000, 0x00000000,
4940 static u32 tg3Tso5FwRodata
[(TG3_TSO5_FW_RODATA_LEN
/ 4) + 1] = {
4941 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
4942 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
4943 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
4944 0x00000000, 0x00000000, 0x00000000,
4947 static u32 tg3Tso5FwData
[(TG3_TSO5_FW_DATA_LEN
/ 4) + 1] = {
4948 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
4949 0x00000000, 0x00000000, 0x00000000,
4952 /* tp->lock is held. */
4953 static int tg3_load_tso_firmware(struct tg3
*tp
)
4955 struct fw_info info
;
4956 unsigned long cpu_base
, cpu_scratch_base
, cpu_scratch_size
;
4959 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
4962 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
4963 info
.text_base
= TG3_TSO5_FW_TEXT_ADDR
;
4964 info
.text_len
= TG3_TSO5_FW_TEXT_LEN
;
4965 info
.text_data
= &tg3Tso5FwText
[0];
4966 info
.rodata_base
= TG3_TSO5_FW_RODATA_ADDR
;
4967 info
.rodata_len
= TG3_TSO5_FW_RODATA_LEN
;
4968 info
.rodata_data
= &tg3Tso5FwRodata
[0];
4969 info
.data_base
= TG3_TSO5_FW_DATA_ADDR
;
4970 info
.data_len
= TG3_TSO5_FW_DATA_LEN
;
4971 info
.data_data
= &tg3Tso5FwData
[0];
4972 cpu_base
= RX_CPU_BASE
;
4973 cpu_scratch_base
= NIC_SRAM_MBUF_POOL_BASE5705
;
4974 cpu_scratch_size
= (info
.text_len
+
4977 TG3_TSO5_FW_SBSS_LEN
+
4978 TG3_TSO5_FW_BSS_LEN
);
4980 info
.text_base
= TG3_TSO_FW_TEXT_ADDR
;
4981 info
.text_len
= TG3_TSO_FW_TEXT_LEN
;
4982 info
.text_data
= &tg3TsoFwText
[0];
4983 info
.rodata_base
= TG3_TSO_FW_RODATA_ADDR
;
4984 info
.rodata_len
= TG3_TSO_FW_RODATA_LEN
;
4985 info
.rodata_data
= &tg3TsoFwRodata
[0];
4986 info
.data_base
= TG3_TSO_FW_DATA_ADDR
;
4987 info
.data_len
= TG3_TSO_FW_DATA_LEN
;
4988 info
.data_data
= &tg3TsoFwData
[0];
4989 cpu_base
= TX_CPU_BASE
;
4990 cpu_scratch_base
= TX_CPU_SCRATCH_BASE
;
4991 cpu_scratch_size
= TX_CPU_SCRATCH_SIZE
;
4994 err
= tg3_load_firmware_cpu(tp
, cpu_base
,
4995 cpu_scratch_base
, cpu_scratch_size
,
5000 /* Now startup the cpu. */
5001 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
5002 tw32_f(cpu_base
+ CPU_PC
, info
.text_base
);
5004 for (i
= 0; i
< 5; i
++) {
5005 if (tr32(cpu_base
+ CPU_PC
) == info
.text_base
)
5007 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
5008 tw32(cpu_base
+ CPU_MODE
, CPU_MODE_HALT
);
5009 tw32_f(cpu_base
+ CPU_PC
, info
.text_base
);
5013 printk(KERN_ERR PFX
"tg3_load_tso_firmware fails for %s "
5014 "to set CPU PC, is %08x should be %08x\n",
5015 tp
->dev
->name
, tr32(cpu_base
+ CPU_PC
),
5019 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
5020 tw32_f(cpu_base
+ CPU_MODE
, 0x00000000);
5024 #endif /* TG3_TSO_SUPPORT != 0 */
5026 /* tp->lock is held. */
5027 static void __tg3_set_mac_addr(struct tg3
*tp
)
5029 u32 addr_high
, addr_low
;
5032 addr_high
= ((tp
->dev
->dev_addr
[0] << 8) |
5033 tp
->dev
->dev_addr
[1]);
5034 addr_low
= ((tp
->dev
->dev_addr
[2] << 24) |
5035 (tp
->dev
->dev_addr
[3] << 16) |
5036 (tp
->dev
->dev_addr
[4] << 8) |
5037 (tp
->dev
->dev_addr
[5] << 0));
5038 for (i
= 0; i
< 4; i
++) {
5039 tw32(MAC_ADDR_0_HIGH
+ (i
* 8), addr_high
);
5040 tw32(MAC_ADDR_0_LOW
+ (i
* 8), addr_low
);
5043 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
5044 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
5045 for (i
= 0; i
< 12; i
++) {
5046 tw32(MAC_EXTADDR_0_HIGH
+ (i
* 8), addr_high
);
5047 tw32(MAC_EXTADDR_0_LOW
+ (i
* 8), addr_low
);
5051 addr_high
= (tp
->dev
->dev_addr
[0] +
5052 tp
->dev
->dev_addr
[1] +
5053 tp
->dev
->dev_addr
[2] +
5054 tp
->dev
->dev_addr
[3] +
5055 tp
->dev
->dev_addr
[4] +
5056 tp
->dev
->dev_addr
[5]) &
5057 TX_BACKOFF_SEED_MASK
;
5058 tw32(MAC_TX_BACKOFF_SEED
, addr_high
);
5061 static int tg3_set_mac_addr(struct net_device
*dev
, void *p
)
5063 struct tg3
*tp
= netdev_priv(dev
);
5064 struct sockaddr
*addr
= p
;
5066 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
5068 spin_lock_irq(&tp
->lock
);
5069 __tg3_set_mac_addr(tp
);
5070 spin_unlock_irq(&tp
->lock
);
5075 /* tp->lock is held. */
5076 static void tg3_set_bdinfo(struct tg3
*tp
, u32 bdinfo_addr
,
5077 dma_addr_t mapping
, u32 maxlen_flags
,
5081 (bdinfo_addr
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_HIGH
),
5082 ((u64
) mapping
>> 32));
5084 (bdinfo_addr
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_LOW
),
5085 ((u64
) mapping
& 0xffffffff));
5087 (bdinfo_addr
+ TG3_BDINFO_MAXLEN_FLAGS
),
5090 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
5092 (bdinfo_addr
+ TG3_BDINFO_NIC_ADDR
),
5096 static void __tg3_set_rx_mode(struct net_device
*);
5098 /* tp->lock is held. */
5099 static int tg3_reset_hw(struct tg3
*tp
)
5101 u32 val
, rdmac_mode
;
5104 tg3_disable_ints(tp
);
5108 tg3_write_sig_pre_reset(tp
, RESET_KIND_INIT
);
5110 if (tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
) {
5111 tg3_abort_hw(tp
, 1);
5114 err
= tg3_chip_reset(tp
);
5118 tg3_write_sig_legacy(tp
, RESET_KIND_INIT
);
5120 /* This works around an issue with Athlon chipsets on
5121 * B3 tigon3 silicon. This bit has no effect on any
5122 * other revision. But do not set this on PCI Express
5125 if (!(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
))
5126 tp
->pci_clock_ctrl
|= CLOCK_CTRL_DELAY_PCI_GRANT
;
5127 tw32_f(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
);
5129 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
&&
5130 (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
)) {
5131 val
= tr32(TG3PCI_PCISTATE
);
5132 val
|= PCISTATE_RETRY_SAME_DMA
;
5133 tw32(TG3PCI_PCISTATE
, val
);
5136 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5704_BX
) {
5137 /* Enable some hw fixes. */
5138 val
= tr32(TG3PCI_MSI_DATA
);
5139 val
|= (1 << 26) | (1 << 28) | (1 << 29);
5140 tw32(TG3PCI_MSI_DATA
, val
);
5143 /* Descriptor ring init may make accesses to the
5144 * NIC SRAM area to setup the TX descriptors, so we
5145 * can only do this after the hardware has been
5146 * successfully reset.
5150 /* This value is determined during the probe time DMA
5151 * engine test, tg3_test_dma.
5153 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
5155 tp
->grc_mode
&= ~(GRC_MODE_HOST_SENDBDS
|
5156 GRC_MODE_4X_NIC_SEND_RINGS
|
5157 GRC_MODE_NO_TX_PHDR_CSUM
|
5158 GRC_MODE_NO_RX_PHDR_CSUM
);
5159 tp
->grc_mode
|= GRC_MODE_HOST_SENDBDS
;
5160 if (tp
->tg3_flags
& TG3_FLAG_NO_TX_PSEUDO_CSUM
)
5161 tp
->grc_mode
|= GRC_MODE_NO_TX_PHDR_CSUM
;
5162 if (tp
->tg3_flags
& TG3_FLAG_NO_RX_PSEUDO_CSUM
)
5163 tp
->grc_mode
|= GRC_MODE_NO_RX_PHDR_CSUM
;
5167 (GRC_MODE_IRQ_ON_MAC_ATTN
| GRC_MODE_HOST_STACKUP
));
5169 /* Setup the timer prescalar register. Clock is always 66Mhz. */
5170 val
= tr32(GRC_MISC_CFG
);
5172 val
|= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT
);
5173 tw32(GRC_MISC_CFG
, val
);
5175 /* Initialize MBUF/DESC pool. */
5176 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) {
5178 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5705
) {
5179 tw32(BUFMGR_MB_POOL_ADDR
, NIC_SRAM_MBUF_POOL_BASE
);
5180 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
)
5181 tw32(BUFMGR_MB_POOL_SIZE
, NIC_SRAM_MBUF_POOL_SIZE64
);
5183 tw32(BUFMGR_MB_POOL_SIZE
, NIC_SRAM_MBUF_POOL_SIZE96
);
5184 tw32(BUFMGR_DMA_DESC_POOL_ADDR
, NIC_SRAM_DMA_DESC_POOL_BASE
);
5185 tw32(BUFMGR_DMA_DESC_POOL_SIZE
, NIC_SRAM_DMA_DESC_POOL_SIZE
);
5187 #if TG3_TSO_SUPPORT != 0
5188 else if (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) {
5191 fw_len
= (TG3_TSO5_FW_TEXT_LEN
+
5192 TG3_TSO5_FW_RODATA_LEN
+
5193 TG3_TSO5_FW_DATA_LEN
+
5194 TG3_TSO5_FW_SBSS_LEN
+
5195 TG3_TSO5_FW_BSS_LEN
);
5196 fw_len
= (fw_len
+ (0x80 - 1)) & ~(0x80 - 1);
5197 tw32(BUFMGR_MB_POOL_ADDR
,
5198 NIC_SRAM_MBUF_POOL_BASE5705
+ fw_len
);
5199 tw32(BUFMGR_MB_POOL_SIZE
,
5200 NIC_SRAM_MBUF_POOL_SIZE5705
- fw_len
- 0xa00);
5204 if (!(tp
->tg3_flags
& TG3_FLAG_JUMBO_ENABLE
)) {
5205 tw32(BUFMGR_MB_RDMA_LOW_WATER
,
5206 tp
->bufmgr_config
.mbuf_read_dma_low_water
);
5207 tw32(BUFMGR_MB_MACRX_LOW_WATER
,
5208 tp
->bufmgr_config
.mbuf_mac_rx_low_water
);
5209 tw32(BUFMGR_MB_HIGH_WATER
,
5210 tp
->bufmgr_config
.mbuf_high_water
);
5212 tw32(BUFMGR_MB_RDMA_LOW_WATER
,
5213 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
);
5214 tw32(BUFMGR_MB_MACRX_LOW_WATER
,
5215 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
);
5216 tw32(BUFMGR_MB_HIGH_WATER
,
5217 tp
->bufmgr_config
.mbuf_high_water_jumbo
);
5219 tw32(BUFMGR_DMA_LOW_WATER
,
5220 tp
->bufmgr_config
.dma_low_water
);
5221 tw32(BUFMGR_DMA_HIGH_WATER
,
5222 tp
->bufmgr_config
.dma_high_water
);
5224 tw32(BUFMGR_MODE
, BUFMGR_MODE_ENABLE
| BUFMGR_MODE_ATTN_ENABLE
);
5225 for (i
= 0; i
< 2000; i
++) {
5226 if (tr32(BUFMGR_MODE
) & BUFMGR_MODE_ENABLE
)
5231 printk(KERN_ERR PFX
"tg3_reset_hw cannot enable BUFMGR for %s.\n",
5236 /* Setup replenish threshold. */
5237 tw32(RCVBDI_STD_THRESH
, tp
->rx_pending
/ 8);
5239 /* Initialize TG3_BDINFO's at:
5240 * RCVDBDI_STD_BD: standard eth size rx ring
5241 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
5242 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
5245 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
5246 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
5247 * ring attribute flags
5248 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
5250 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
5251 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
5253 * The size of each ring is fixed in the firmware, but the location is
5256 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
5257 ((u64
) tp
->rx_std_mapping
>> 32));
5258 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
5259 ((u64
) tp
->rx_std_mapping
& 0xffffffff));
5260 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_NIC_ADDR
,
5261 NIC_SRAM_RX_BUFFER_DESC
);
5263 /* Don't even try to program the JUMBO/MINI buffer descriptor
5266 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
5267 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
5268 RX_STD_MAX_SIZE_5705
<< BDINFO_FLAGS_MAXLEN_SHIFT
);
5270 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
5271 RX_STD_MAX_SIZE
<< BDINFO_FLAGS_MAXLEN_SHIFT
);
5273 tw32(RCVDBDI_MINI_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
5274 BDINFO_FLAGS_DISABLED
);
5276 /* Setup replenish threshold. */
5277 tw32(RCVBDI_JUMBO_THRESH
, tp
->rx_jumbo_pending
/ 8);
5279 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_ENABLE
) {
5280 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
5281 ((u64
) tp
->rx_jumbo_mapping
>> 32));
5282 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
5283 ((u64
) tp
->rx_jumbo_mapping
& 0xffffffff));
5284 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
5285 RX_JUMBO_MAX_SIZE
<< BDINFO_FLAGS_MAXLEN_SHIFT
);
5286 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_NIC_ADDR
,
5287 NIC_SRAM_RX_JUMBO_BUFFER_DESC
);
5289 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
5290 BDINFO_FLAGS_DISABLED
);
5295 /* There is only one send ring on 5705/5750, no need to explicitly
5296 * disable the others.
5298 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
5299 /* Clear out send RCB ring in SRAM. */
5300 for (i
= NIC_SRAM_SEND_RCB
; i
< NIC_SRAM_RCV_RET_RCB
; i
+= TG3_BDINFO_SIZE
)
5301 tg3_write_mem(tp
, i
+ TG3_BDINFO_MAXLEN_FLAGS
,
5302 BDINFO_FLAGS_DISABLED
);
5307 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0
+ TG3_64BIT_REG_LOW
, 0);
5308 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0
+ TG3_64BIT_REG_LOW
, 0);
5310 tg3_set_bdinfo(tp
, NIC_SRAM_SEND_RCB
,
5311 tp
->tx_desc_mapping
,
5312 (TG3_TX_RING_SIZE
<<
5313 BDINFO_FLAGS_MAXLEN_SHIFT
),
5314 NIC_SRAM_TX_BUFFER_DESC
);
5316 /* There is only one receive return ring on 5705/5750, no need
5317 * to explicitly disable the others.
5319 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
5320 for (i
= NIC_SRAM_RCV_RET_RCB
; i
< NIC_SRAM_STATS_BLK
;
5321 i
+= TG3_BDINFO_SIZE
) {
5322 tg3_write_mem(tp
, i
+ TG3_BDINFO_MAXLEN_FLAGS
,
5323 BDINFO_FLAGS_DISABLED
);
5328 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0
+ TG3_64BIT_REG_LOW
, 0);
5330 tg3_set_bdinfo(tp
, NIC_SRAM_RCV_RET_RCB
,
5332 (TG3_RX_RCB_RING_SIZE(tp
) <<
5333 BDINFO_FLAGS_MAXLEN_SHIFT
),
5336 tp
->rx_std_ptr
= tp
->rx_pending
;
5337 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX
+ TG3_64BIT_REG_LOW
,
5340 tp
->rx_jumbo_ptr
= (tp
->tg3_flags
& TG3_FLAG_JUMBO_ENABLE
) ?
5341 tp
->rx_jumbo_pending
: 0;
5342 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX
+ TG3_64BIT_REG_LOW
,
5345 /* Initialize MAC address and backoff seed. */
5346 __tg3_set_mac_addr(tp
);
5348 /* MTU + ethernet header + FCS + optional VLAN tag */
5349 tw32(MAC_RX_MTU_SIZE
, tp
->dev
->mtu
+ ETH_HLEN
+ 8);
5351 /* The slot time is changed by tg3_setup_phy if we
5352 * run at gigabit with half duplex.
5354 tw32(MAC_TX_LENGTHS
,
5355 (2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
5356 (6 << TX_LENGTHS_IPG_SHIFT
) |
5357 (32 << TX_LENGTHS_SLOT_TIME_SHIFT
));
5359 /* Receive rules. */
5360 tw32(MAC_RCV_RULE_CFG
, RCV_RULE_CFG_DEFAULT_CLASS
);
5361 tw32(RCVLPC_CONFIG
, 0x0181);
5363 /* Calculate RDMAC_MODE setting early, we need it to determine
5364 * the RCVLPC_STATE_ENABLE mask.
5366 rdmac_mode
= (RDMAC_MODE_ENABLE
| RDMAC_MODE_TGTABORT_ENAB
|
5367 RDMAC_MODE_MSTABORT_ENAB
| RDMAC_MODE_PARITYERR_ENAB
|
5368 RDMAC_MODE_ADDROFLOW_ENAB
| RDMAC_MODE_FIFOOFLOW_ENAB
|
5369 RDMAC_MODE_FIFOURUN_ENAB
| RDMAC_MODE_FIFOOREAD_ENAB
|
5370 RDMAC_MODE_LNGREAD_ENAB
);
5371 if (tp
->tg3_flags
& TG3_FLAG_SPLIT_MODE
)
5372 rdmac_mode
|= RDMAC_MODE_SPLIT_ENABLE
;
5374 /* If statement applies to 5705 and 5750 PCI devices only */
5375 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
5376 tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A0
) ||
5377 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
)) {
5378 if (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
&&
5379 (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A1
||
5380 tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A2
)) {
5381 rdmac_mode
|= RDMAC_MODE_FIFO_SIZE_128
;
5382 } else if (!(tr32(TG3PCI_PCISTATE
) & PCISTATE_BUS_SPEED_HIGH
) &&
5383 !(tp
->tg3_flags2
& TG3_FLG2_IS_5788
)) {
5384 rdmac_mode
|= RDMAC_MODE_FIFO_LONG_BURST
;
5388 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)
5389 rdmac_mode
|= RDMAC_MODE_FIFO_LONG_BURST
;
5391 #if TG3_TSO_SUPPORT != 0
5392 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
5393 rdmac_mode
|= (1 << 27);
5396 /* Receive/send statistics. */
5397 if ((rdmac_mode
& RDMAC_MODE_FIFO_SIZE_128
) &&
5398 (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
)) {
5399 val
= tr32(RCVLPC_STATS_ENABLE
);
5400 val
&= ~RCVLPC_STATSENAB_LNGBRST_RFIX
;
5401 tw32(RCVLPC_STATS_ENABLE
, val
);
5403 tw32(RCVLPC_STATS_ENABLE
, 0xffffff);
5405 tw32(RCVLPC_STATSCTRL
, RCVLPC_STATSCTRL_ENABLE
);
5406 tw32(SNDDATAI_STATSENAB
, 0xffffff);
5407 tw32(SNDDATAI_STATSCTRL
,
5408 (SNDDATAI_SCTRL_ENABLE
|
5409 SNDDATAI_SCTRL_FASTUPD
));
5411 /* Setup host coalescing engine. */
5412 tw32(HOSTCC_MODE
, 0);
5413 for (i
= 0; i
< 2000; i
++) {
5414 if (!(tr32(HOSTCC_MODE
) & HOSTCC_MODE_ENABLE
))
5419 tw32(HOSTCC_RXCOL_TICKS
, 0);
5420 tw32(HOSTCC_TXCOL_TICKS
, LOW_TXCOL_TICKS
);
5421 tw32(HOSTCC_RXMAX_FRAMES
, 1);
5422 tw32(HOSTCC_TXMAX_FRAMES
, LOW_RXMAX_FRAMES
);
5423 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
5424 tw32(HOSTCC_RXCOAL_TICK_INT
, 0);
5425 tw32(HOSTCC_TXCOAL_TICK_INT
, 0);
5427 tw32(HOSTCC_RXCOAL_MAXF_INT
, 1);
5428 tw32(HOSTCC_TXCOAL_MAXF_INT
, 0);
5430 /* set status block DMA address */
5431 tw32(HOSTCC_STATUS_BLK_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
5432 ((u64
) tp
->status_mapping
>> 32));
5433 tw32(HOSTCC_STATUS_BLK_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
5434 ((u64
) tp
->status_mapping
& 0xffffffff));
5436 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
5437 /* Status/statistics block address. See tg3_timer,
5438 * the tg3_periodic_fetch_stats call there, and
5439 * tg3_get_stats to see how this works for 5705/5750 chips.
5441 tw32(HOSTCC_STAT_COAL_TICKS
,
5442 DEFAULT_STAT_COAL_TICKS
);
5443 tw32(HOSTCC_STATS_BLK_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
5444 ((u64
) tp
->stats_mapping
>> 32));
5445 tw32(HOSTCC_STATS_BLK_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
5446 ((u64
) tp
->stats_mapping
& 0xffffffff));
5447 tw32(HOSTCC_STATS_BLK_NIC_ADDR
, NIC_SRAM_STATS_BLK
);
5448 tw32(HOSTCC_STATUS_BLK_NIC_ADDR
, NIC_SRAM_STATUS_BLK
);
5451 tw32(HOSTCC_MODE
, HOSTCC_MODE_ENABLE
| tp
->coalesce_mode
);
5453 tw32(RCVCC_MODE
, RCVCC_MODE_ENABLE
| RCVCC_MODE_ATTN_ENABLE
);
5454 tw32(RCVLPC_MODE
, RCVLPC_MODE_ENABLE
);
5455 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
5456 tw32(RCVLSC_MODE
, RCVLSC_MODE_ENABLE
| RCVLSC_MODE_ATTN_ENABLE
);
5458 /* Clear statistics/status block in chip, and status block in ram. */
5459 for (i
= NIC_SRAM_STATS_BLK
;
5460 i
< NIC_SRAM_STATUS_BLK
+ TG3_HW_STATUS_SIZE
;
5462 tg3_write_mem(tp
, i
, 0);
5465 memset(tp
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
5467 tp
->mac_mode
= MAC_MODE_TXSTAT_ENABLE
| MAC_MODE_RXSTAT_ENABLE
|
5468 MAC_MODE_TDE_ENABLE
| MAC_MODE_RDE_ENABLE
| MAC_MODE_FHDE_ENABLE
;
5469 tw32_f(MAC_MODE
, tp
->mac_mode
| MAC_MODE_RXSTAT_CLEAR
| MAC_MODE_TXSTAT_CLEAR
);
5472 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
5473 * If TG3_FLAG_EEPROM_WRITE_PROT is set, we should read the
5474 * register to preserve the GPIO settings for LOMs. The GPIOs,
5475 * whether used as inputs or outputs, are set by boot code after
5478 if (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
) {
5481 gpio_mask
= GRC_LCLCTRL_GPIO_OE0
| GRC_LCLCTRL_GPIO_OE2
|
5482 GRC_LCLCTRL_GPIO_OUTPUT0
| GRC_LCLCTRL_GPIO_OUTPUT2
;
5484 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
)
5485 gpio_mask
|= GRC_LCLCTRL_GPIO_OE3
|
5486 GRC_LCLCTRL_GPIO_OUTPUT3
;
5488 tp
->grc_local_ctrl
|= tr32(GRC_LOCAL_CTRL
) & gpio_mask
;
5490 /* GPIO1 must be driven high for eeprom write protect */
5491 tp
->grc_local_ctrl
|= (GRC_LCLCTRL_GPIO_OE1
|
5492 GRC_LCLCTRL_GPIO_OUTPUT1
);
5494 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
);
5497 tw32_mailbox(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0);
5498 tr32(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
);
5501 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
5502 tw32_f(DMAC_MODE
, DMAC_MODE_ENABLE
);
5506 val
= (WDMAC_MODE_ENABLE
| WDMAC_MODE_TGTABORT_ENAB
|
5507 WDMAC_MODE_MSTABORT_ENAB
| WDMAC_MODE_PARITYERR_ENAB
|
5508 WDMAC_MODE_ADDROFLOW_ENAB
| WDMAC_MODE_FIFOOFLOW_ENAB
|
5509 WDMAC_MODE_FIFOURUN_ENAB
| WDMAC_MODE_FIFOOREAD_ENAB
|
5510 WDMAC_MODE_LNGREAD_ENAB
);
5512 /* If statement applies to 5705 and 5750 PCI devices only */
5513 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
5514 tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A0
) ||
5515 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
) {
5516 if ((tp
->tg3_flags
& TG3_FLG2_TSO_CAPABLE
) &&
5517 (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A1
||
5518 tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A2
)) {
5520 } else if (!(tr32(TG3PCI_PCISTATE
) & PCISTATE_BUS_SPEED_HIGH
) &&
5521 !(tp
->tg3_flags2
& TG3_FLG2_IS_5788
) &&
5522 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)) {
5523 val
|= WDMAC_MODE_RX_ACCEL
;
5527 tw32_f(WDMAC_MODE
, val
);
5530 if ((tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) != 0) {
5531 val
= tr32(TG3PCI_X_CAPS
);
5532 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
) {
5533 val
&= ~PCIX_CAPS_BURST_MASK
;
5534 val
|= (PCIX_CAPS_MAX_BURST_CPIOB
<< PCIX_CAPS_BURST_SHIFT
);
5535 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
5536 val
&= ~(PCIX_CAPS_SPLIT_MASK
| PCIX_CAPS_BURST_MASK
);
5537 val
|= (PCIX_CAPS_MAX_BURST_CPIOB
<< PCIX_CAPS_BURST_SHIFT
);
5538 if (tp
->tg3_flags
& TG3_FLAG_SPLIT_MODE
)
5539 val
|= (tp
->split_mode_max_reqs
<<
5540 PCIX_CAPS_SPLIT_SHIFT
);
5542 tw32(TG3PCI_X_CAPS
, val
);
5545 tw32_f(RDMAC_MODE
, rdmac_mode
);
5548 tw32(RCVDCC_MODE
, RCVDCC_MODE_ENABLE
| RCVDCC_MODE_ATTN_ENABLE
);
5549 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
5550 tw32(MBFREE_MODE
, MBFREE_MODE_ENABLE
);
5551 tw32(SNDDATAC_MODE
, SNDDATAC_MODE_ENABLE
);
5552 tw32(SNDBDC_MODE
, SNDBDC_MODE_ENABLE
| SNDBDC_MODE_ATTN_ENABLE
);
5553 tw32(RCVBDI_MODE
, RCVBDI_MODE_ENABLE
| RCVBDI_MODE_RCB_ATTN_ENAB
);
5554 tw32(RCVDBDI_MODE
, RCVDBDI_MODE_ENABLE
| RCVDBDI_MODE_INV_RING_SZ
);
5555 tw32(SNDDATAI_MODE
, SNDDATAI_MODE_ENABLE
);
5556 #if TG3_TSO_SUPPORT != 0
5557 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
5558 tw32(SNDDATAI_MODE
, SNDDATAI_MODE_ENABLE
| 0x8);
5560 tw32(SNDBDI_MODE
, SNDBDI_MODE_ENABLE
| SNDBDI_MODE_ATTN_ENABLE
);
5561 tw32(SNDBDS_MODE
, SNDBDS_MODE_ENABLE
| SNDBDS_MODE_ATTN_ENABLE
);
5563 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
) {
5564 err
= tg3_load_5701_a0_firmware_fix(tp
);
5569 #if TG3_TSO_SUPPORT != 0
5570 if (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) {
5571 err
= tg3_load_tso_firmware(tp
);
5577 tp
->tx_mode
= TX_MODE_ENABLE
;
5578 tw32_f(MAC_TX_MODE
, tp
->tx_mode
);
5581 tp
->rx_mode
= RX_MODE_ENABLE
;
5582 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
5585 if (tp
->link_config
.phy_is_low_power
) {
5586 tp
->link_config
.phy_is_low_power
= 0;
5587 tp
->link_config
.speed
= tp
->link_config
.orig_speed
;
5588 tp
->link_config
.duplex
= tp
->link_config
.orig_duplex
;
5589 tp
->link_config
.autoneg
= tp
->link_config
.orig_autoneg
;
5592 tp
->mi_mode
= MAC_MI_MODE_BASE
;
5593 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
5596 tw32(MAC_LED_CTRL
, tp
->led_ctrl
);
5598 tw32(MAC_MI_STAT
, MAC_MI_STAT_LNKSTAT_ATTN_ENAB
);
5599 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
5600 tw32_f(MAC_RX_MODE
, RX_MODE_RESET
);
5603 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
5606 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
5607 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) &&
5608 !(tp
->tg3_flags2
& TG3_FLG2_SERDES_PREEMPHASIS
)) {
5609 /* Set drive transmission level to 1.2V */
5610 /* only if the signal pre-emphasis bit is not set */
5611 val
= tr32(MAC_SERDES_CFG
);
5614 tw32(MAC_SERDES_CFG
, val
);
5616 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5703_A1
)
5617 tw32(MAC_SERDES_CFG
, 0x616000);
5620 /* Prevent chip from dropping frames when flow control
5623 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME
, 2);
5625 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
&&
5626 (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)) {
5627 /* Use hardware link auto-negotiation */
5628 tp
->tg3_flags2
|= TG3_FLG2_HW_AUTONEG
;
5631 err
= tg3_setup_phy(tp
, 1);
5635 if (!(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)) {
5638 /* Clear CRC stats. */
5639 if (!tg3_readphy(tp
, 0x1e, &tmp
)) {
5640 tg3_writephy(tp
, 0x1e, tmp
| 0x8000);
5641 tg3_readphy(tp
, 0x14, &tmp
);
5645 __tg3_set_rx_mode(tp
->dev
);
5647 /* Initialize receive rules. */
5648 tw32(MAC_RCV_RULE_0
, 0xc2000000 & RCV_RULE_DISABLE_MASK
);
5649 tw32(MAC_RCV_VALUE_0
, 0xffffffff & RCV_RULE_DISABLE_MASK
);
5650 tw32(MAC_RCV_RULE_1
, 0x86000004 & RCV_RULE_DISABLE_MASK
);
5651 tw32(MAC_RCV_VALUE_1
, 0xffffffff & RCV_RULE_DISABLE_MASK
);
5653 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
5657 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)
5661 tw32(MAC_RCV_RULE_15
, 0); tw32(MAC_RCV_VALUE_15
, 0);
5663 tw32(MAC_RCV_RULE_14
, 0); tw32(MAC_RCV_VALUE_14
, 0);
5665 tw32(MAC_RCV_RULE_13
, 0); tw32(MAC_RCV_VALUE_13
, 0);
5667 tw32(MAC_RCV_RULE_12
, 0); tw32(MAC_RCV_VALUE_12
, 0);
5669 tw32(MAC_RCV_RULE_11
, 0); tw32(MAC_RCV_VALUE_11
, 0);
5671 tw32(MAC_RCV_RULE_10
, 0); tw32(MAC_RCV_VALUE_10
, 0);
5673 tw32(MAC_RCV_RULE_9
, 0); tw32(MAC_RCV_VALUE_9
, 0);
5675 tw32(MAC_RCV_RULE_8
, 0); tw32(MAC_RCV_VALUE_8
, 0);
5677 tw32(MAC_RCV_RULE_7
, 0); tw32(MAC_RCV_VALUE_7
, 0);
5679 tw32(MAC_RCV_RULE_6
, 0); tw32(MAC_RCV_VALUE_6
, 0);
5681 tw32(MAC_RCV_RULE_5
, 0); tw32(MAC_RCV_VALUE_5
, 0);
5683 tw32(MAC_RCV_RULE_4
, 0); tw32(MAC_RCV_VALUE_4
, 0);
5685 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
5687 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
5695 tg3_write_sig_post_reset(tp
, RESET_KIND_INIT
);
5697 if (tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
)
5698 tg3_enable_ints(tp
);
5703 /* Called at device open time to get the chip ready for
5704 * packet processing. Invoked with tp->lock held.
5706 static int tg3_init_hw(struct tg3
*tp
)
5710 /* Force the chip into D0. */
5711 err
= tg3_set_power_state(tp
, 0);
5715 tg3_switch_clocks(tp
);
5717 tw32(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
5719 err
= tg3_reset_hw(tp
);
5725 #define TG3_STAT_ADD32(PSTAT, REG) \
5726 do { u32 __val = tr32(REG); \
5727 (PSTAT)->low += __val; \
5728 if ((PSTAT)->low < __val) \
5729 (PSTAT)->high += 1; \
5732 static void tg3_periodic_fetch_stats(struct tg3
*tp
)
5734 struct tg3_hw_stats
*sp
= tp
->hw_stats
;
5736 if (!netif_carrier_ok(tp
->dev
))
5739 TG3_STAT_ADD32(&sp
->tx_octets
, MAC_TX_STATS_OCTETS
);
5740 TG3_STAT_ADD32(&sp
->tx_collisions
, MAC_TX_STATS_COLLISIONS
);
5741 TG3_STAT_ADD32(&sp
->tx_xon_sent
, MAC_TX_STATS_XON_SENT
);
5742 TG3_STAT_ADD32(&sp
->tx_xoff_sent
, MAC_TX_STATS_XOFF_SENT
);
5743 TG3_STAT_ADD32(&sp
->tx_mac_errors
, MAC_TX_STATS_MAC_ERRORS
);
5744 TG3_STAT_ADD32(&sp
->tx_single_collisions
, MAC_TX_STATS_SINGLE_COLLISIONS
);
5745 TG3_STAT_ADD32(&sp
->tx_mult_collisions
, MAC_TX_STATS_MULT_COLLISIONS
);
5746 TG3_STAT_ADD32(&sp
->tx_deferred
, MAC_TX_STATS_DEFERRED
);
5747 TG3_STAT_ADD32(&sp
->tx_excessive_collisions
, MAC_TX_STATS_EXCESSIVE_COL
);
5748 TG3_STAT_ADD32(&sp
->tx_late_collisions
, MAC_TX_STATS_LATE_COL
);
5749 TG3_STAT_ADD32(&sp
->tx_ucast_packets
, MAC_TX_STATS_UCAST
);
5750 TG3_STAT_ADD32(&sp
->tx_mcast_packets
, MAC_TX_STATS_MCAST
);
5751 TG3_STAT_ADD32(&sp
->tx_bcast_packets
, MAC_TX_STATS_BCAST
);
5753 TG3_STAT_ADD32(&sp
->rx_octets
, MAC_RX_STATS_OCTETS
);
5754 TG3_STAT_ADD32(&sp
->rx_fragments
, MAC_RX_STATS_FRAGMENTS
);
5755 TG3_STAT_ADD32(&sp
->rx_ucast_packets
, MAC_RX_STATS_UCAST
);
5756 TG3_STAT_ADD32(&sp
->rx_mcast_packets
, MAC_RX_STATS_MCAST
);
5757 TG3_STAT_ADD32(&sp
->rx_bcast_packets
, MAC_RX_STATS_BCAST
);
5758 TG3_STAT_ADD32(&sp
->rx_fcs_errors
, MAC_RX_STATS_FCS_ERRORS
);
5759 TG3_STAT_ADD32(&sp
->rx_align_errors
, MAC_RX_STATS_ALIGN_ERRORS
);
5760 TG3_STAT_ADD32(&sp
->rx_xon_pause_rcvd
, MAC_RX_STATS_XON_PAUSE_RECVD
);
5761 TG3_STAT_ADD32(&sp
->rx_xoff_pause_rcvd
, MAC_RX_STATS_XOFF_PAUSE_RECVD
);
5762 TG3_STAT_ADD32(&sp
->rx_mac_ctrl_rcvd
, MAC_RX_STATS_MAC_CTRL_RECVD
);
5763 TG3_STAT_ADD32(&sp
->rx_xoff_entered
, MAC_RX_STATS_XOFF_ENTERED
);
5764 TG3_STAT_ADD32(&sp
->rx_frame_too_long_errors
, MAC_RX_STATS_FRAME_TOO_LONG
);
5765 TG3_STAT_ADD32(&sp
->rx_jabbers
, MAC_RX_STATS_JABBERS
);
5766 TG3_STAT_ADD32(&sp
->rx_undersize_packets
, MAC_RX_STATS_UNDERSIZE
);
5769 static void tg3_timer(unsigned long __opaque
)
5771 struct tg3
*tp
= (struct tg3
*) __opaque
;
5772 unsigned long flags
;
5774 spin_lock_irqsave(&tp
->lock
, flags
);
5775 spin_lock(&tp
->tx_lock
);
5777 if (!(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)) {
5778 /* All of this garbage is because when using non-tagged
5779 * IRQ status the mailbox/status_block protocol the chip
5780 * uses with the cpu is race prone.
5782 if (tp
->hw_status
->status
& SD_STATUS_UPDATED
) {
5783 tw32(GRC_LOCAL_CTRL
,
5784 tp
->grc_local_ctrl
| GRC_LCLCTRL_SETINT
);
5786 tw32(HOSTCC_MODE
, tp
->coalesce_mode
|
5787 (HOSTCC_MODE_ENABLE
| HOSTCC_MODE_NOW
));
5790 if (!(tr32(WDMAC_MODE
) & WDMAC_MODE_ENABLE
)) {
5791 tp
->tg3_flags2
|= TG3_FLG2_RESTART_TIMER
;
5792 spin_unlock(&tp
->tx_lock
);
5793 spin_unlock_irqrestore(&tp
->lock
, flags
);
5794 schedule_work(&tp
->reset_task
);
5799 /* This part only runs once per second. */
5800 if (!--tp
->timer_counter
) {
5801 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
5802 tg3_periodic_fetch_stats(tp
);
5804 if (tp
->tg3_flags
& TG3_FLAG_USE_LINKCHG_REG
) {
5808 mac_stat
= tr32(MAC_STATUS
);
5811 if (tp
->tg3_flags
& TG3_FLAG_USE_MI_INTERRUPT
) {
5812 if (mac_stat
& MAC_STATUS_MI_INTERRUPT
)
5814 } else if (mac_stat
& MAC_STATUS_LNKSTATE_CHANGED
)
5818 tg3_setup_phy(tp
, 0);
5819 } else if (tp
->tg3_flags
& TG3_FLAG_POLL_SERDES
) {
5820 u32 mac_stat
= tr32(MAC_STATUS
);
5823 if (netif_carrier_ok(tp
->dev
) &&
5824 (mac_stat
& MAC_STATUS_LNKSTATE_CHANGED
)) {
5827 if (! netif_carrier_ok(tp
->dev
) &&
5828 (mac_stat
& (MAC_STATUS_PCS_SYNCED
|
5829 MAC_STATUS_SIGNAL_DET
))) {
5835 ~MAC_MODE_PORT_MODE_MASK
));
5837 tw32_f(MAC_MODE
, tp
->mac_mode
);
5839 tg3_setup_phy(tp
, 0);
5843 tp
->timer_counter
= tp
->timer_multiplier
;
5846 /* Heartbeat is only sent once every 120 seconds. */
5847 if (!--tp
->asf_counter
) {
5848 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) {
5851 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_MBOX
, FWCMD_NICDRV_ALIVE
);
5852 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_LEN_MBOX
, 4);
5853 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
, 3);
5854 val
= tr32(GRC_RX_CPU_EVENT
);
5856 tw32(GRC_RX_CPU_EVENT
, val
);
5858 tp
->asf_counter
= tp
->asf_multiplier
;
5861 spin_unlock(&tp
->tx_lock
);
5862 spin_unlock_irqrestore(&tp
->lock
, flags
);
5864 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
5865 add_timer(&tp
->timer
);
5868 static int tg3_test_interrupt(struct tg3
*tp
)
5870 struct net_device
*dev
= tp
->dev
;
5874 tg3_disable_ints(tp
);
5876 free_irq(tp
->pdev
->irq
, dev
);
5878 err
= request_irq(tp
->pdev
->irq
, tg3_test_isr
,
5879 SA_SHIRQ
| SA_SAMPLE_RANDOM
, dev
->name
, dev
);
5883 tg3_enable_ints(tp
);
5885 tw32_f(HOSTCC_MODE
, tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
|
5888 for (i
= 0; i
< 5; i
++) {
5889 int_mbox
= tr32(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
);
5895 tg3_disable_ints(tp
);
5897 free_irq(tp
->pdev
->irq
, dev
);
5899 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
)
5900 err
= request_irq(tp
->pdev
->irq
, tg3_msi
,
5901 SA_SAMPLE_RANDOM
, dev
->name
, dev
);
5903 irqreturn_t (*fn
)(int, void *, struct pt_regs
*)=tg3_interrupt
;
5904 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)
5905 fn
= tg3_interrupt_tagged
;
5906 err
= request_irq(tp
->pdev
->irq
, fn
,
5907 SA_SHIRQ
| SA_SAMPLE_RANDOM
, dev
->name
, dev
);
5919 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
5920 * successfully restored
5922 static int tg3_test_msi(struct tg3
*tp
)
5924 struct net_device
*dev
= tp
->dev
;
5928 if (!(tp
->tg3_flags2
& TG3_FLG2_USING_MSI
))
5931 /* Turn off SERR reporting in case MSI terminates with Master
5934 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
5935 pci_write_config_word(tp
->pdev
, PCI_COMMAND
,
5936 pci_cmd
& ~PCI_COMMAND_SERR
);
5938 err
= tg3_test_interrupt(tp
);
5940 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
5945 /* other failures */
5949 /* MSI test failed, go back to INTx mode */
5950 printk(KERN_WARNING PFX
"%s: No interrupt was generated using MSI, "
5951 "switching to INTx mode. Please report this failure to "
5952 "the PCI maintainer and include system chipset information.\n",
5955 free_irq(tp
->pdev
->irq
, dev
);
5956 pci_disable_msi(tp
->pdev
);
5958 tp
->tg3_flags2
&= ~TG3_FLG2_USING_MSI
;
5961 irqreturn_t (*fn
)(int, void *, struct pt_regs
*)=tg3_interrupt
;
5962 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)
5963 fn
= tg3_interrupt_tagged
;
5965 err
= request_irq(tp
->pdev
->irq
, fn
,
5966 SA_SHIRQ
| SA_SAMPLE_RANDOM
, dev
->name
, dev
);
5971 /* Need to reset the chip because the MSI cycle may have terminated
5972 * with Master Abort.
5974 spin_lock_irq(&tp
->lock
);
5975 spin_lock(&tp
->tx_lock
);
5978 err
= tg3_init_hw(tp
);
5980 spin_unlock(&tp
->tx_lock
);
5981 spin_unlock_irq(&tp
->lock
);
5984 free_irq(tp
->pdev
->irq
, dev
);
5989 static int tg3_open(struct net_device
*dev
)
5991 struct tg3
*tp
= netdev_priv(dev
);
5994 spin_lock_irq(&tp
->lock
);
5995 spin_lock(&tp
->tx_lock
);
5997 tg3_disable_ints(tp
);
5998 tp
->tg3_flags
&= ~TG3_FLAG_INIT_COMPLETE
;
6000 spin_unlock(&tp
->tx_lock
);
6001 spin_unlock_irq(&tp
->lock
);
6003 /* The placement of this call is tied
6004 * to the setup and use of Host TX descriptors.
6006 err
= tg3_alloc_consistent(tp
);
6010 if ((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
6011 (GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5750_AX
) &&
6012 (GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5750_BX
)) {
6013 /* All MSI supporting chips should support tagged
6014 * status. Assert that this is the case.
6016 if (!(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)) {
6017 printk(KERN_WARNING PFX
"%s: MSI without TAGGED? "
6018 "Not using MSI.\n", tp
->dev
->name
);
6019 } else if (pci_enable_msi(tp
->pdev
) == 0) {
6022 msi_mode
= tr32(MSGINT_MODE
);
6023 tw32(MSGINT_MODE
, msi_mode
| MSGINT_MODE_ENABLE
);
6024 tp
->tg3_flags2
|= TG3_FLG2_USING_MSI
;
6027 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
)
6028 err
= request_irq(tp
->pdev
->irq
, tg3_msi
,
6029 SA_SAMPLE_RANDOM
, dev
->name
, dev
);
6031 irqreturn_t (*fn
)(int, void *, struct pt_regs
*)=tg3_interrupt
;
6032 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)
6033 fn
= tg3_interrupt_tagged
;
6035 err
= request_irq(tp
->pdev
->irq
, fn
,
6036 SA_SHIRQ
| SA_SAMPLE_RANDOM
, dev
->name
, dev
);
6040 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
6041 pci_disable_msi(tp
->pdev
);
6042 tp
->tg3_flags2
&= ~TG3_FLG2_USING_MSI
;
6044 tg3_free_consistent(tp
);
6048 spin_lock_irq(&tp
->lock
);
6049 spin_lock(&tp
->tx_lock
);
6051 err
= tg3_init_hw(tp
);
6056 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)
6057 tp
->timer_offset
= HZ
;
6059 tp
->timer_offset
= HZ
/ 10;
6061 BUG_ON(tp
->timer_offset
> HZ
);
6062 tp
->timer_counter
= tp
->timer_multiplier
=
6063 (HZ
/ tp
->timer_offset
);
6064 tp
->asf_counter
= tp
->asf_multiplier
=
6065 ((HZ
/ tp
->timer_offset
) * 120);
6067 init_timer(&tp
->timer
);
6068 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
6069 tp
->timer
.data
= (unsigned long) tp
;
6070 tp
->timer
.function
= tg3_timer
;
6073 spin_unlock(&tp
->tx_lock
);
6074 spin_unlock_irq(&tp
->lock
);
6077 free_irq(tp
->pdev
->irq
, dev
);
6078 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
6079 pci_disable_msi(tp
->pdev
);
6080 tp
->tg3_flags2
&= ~TG3_FLG2_USING_MSI
;
6082 tg3_free_consistent(tp
);
6086 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
6087 err
= tg3_test_msi(tp
);
6090 spin_lock_irq(&tp
->lock
);
6091 spin_lock(&tp
->tx_lock
);
6093 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
6094 pci_disable_msi(tp
->pdev
);
6095 tp
->tg3_flags2
&= ~TG3_FLG2_USING_MSI
;
6099 tg3_free_consistent(tp
);
6101 spin_unlock(&tp
->tx_lock
);
6102 spin_unlock_irq(&tp
->lock
);
6108 spin_lock_irq(&tp
->lock
);
6109 spin_lock(&tp
->tx_lock
);
6111 add_timer(&tp
->timer
);
6112 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
6113 tg3_enable_ints(tp
);
6115 spin_unlock(&tp
->tx_lock
);
6116 spin_unlock_irq(&tp
->lock
);
6118 netif_start_queue(dev
);
6124 /*static*/ void tg3_dump_state(struct tg3
*tp
)
6126 u32 val32
, val32_2
, val32_3
, val32_4
, val32_5
;
6130 pci_read_config_word(tp
->pdev
, PCI_STATUS
, &val16
);
6131 pci_read_config_dword(tp
->pdev
, TG3PCI_PCISTATE
, &val32
);
6132 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
6136 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
6137 tr32(MAC_MODE
), tr32(MAC_STATUS
));
6138 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
6139 tr32(MAC_EVENT
), tr32(MAC_LED_CTRL
));
6140 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
6141 tr32(MAC_TX_MODE
), tr32(MAC_TX_STATUS
));
6142 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
6143 tr32(MAC_RX_MODE
), tr32(MAC_RX_STATUS
));
6145 /* Send data initiator control block */
6146 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
6147 tr32(SNDDATAI_MODE
), tr32(SNDDATAI_STATUS
));
6148 printk(" SNDDATAI_STATSCTRL[%08x]\n",
6149 tr32(SNDDATAI_STATSCTRL
));
6151 /* Send data completion control block */
6152 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE
));
6154 /* Send BD ring selector block */
6155 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
6156 tr32(SNDBDS_MODE
), tr32(SNDBDS_STATUS
));
6158 /* Send BD initiator control block */
6159 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
6160 tr32(SNDBDI_MODE
), tr32(SNDBDI_STATUS
));
6162 /* Send BD completion control block */
6163 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE
));
6165 /* Receive list placement control block */
6166 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
6167 tr32(RCVLPC_MODE
), tr32(RCVLPC_STATUS
));
6168 printk(" RCVLPC_STATSCTRL[%08x]\n",
6169 tr32(RCVLPC_STATSCTRL
));
6171 /* Receive data and receive BD initiator control block */
6172 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
6173 tr32(RCVDBDI_MODE
), tr32(RCVDBDI_STATUS
));
6175 /* Receive data completion control block */
6176 printk("DEBUG: RCVDCC_MODE[%08x]\n",
6179 /* Receive BD initiator control block */
6180 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
6181 tr32(RCVBDI_MODE
), tr32(RCVBDI_STATUS
));
6183 /* Receive BD completion control block */
6184 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
6185 tr32(RCVCC_MODE
), tr32(RCVCC_STATUS
));
6187 /* Receive list selector control block */
6188 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
6189 tr32(RCVLSC_MODE
), tr32(RCVLSC_STATUS
));
6191 /* Mbuf cluster free block */
6192 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
6193 tr32(MBFREE_MODE
), tr32(MBFREE_STATUS
));
6195 /* Host coalescing control block */
6196 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
6197 tr32(HOSTCC_MODE
), tr32(HOSTCC_STATUS
));
6198 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
6199 tr32(HOSTCC_STATS_BLK_HOST_ADDR
+ TG3_64BIT_REG_HIGH
),
6200 tr32(HOSTCC_STATS_BLK_HOST_ADDR
+ TG3_64BIT_REG_LOW
));
6201 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
6202 tr32(HOSTCC_STATUS_BLK_HOST_ADDR
+ TG3_64BIT_REG_HIGH
),
6203 tr32(HOSTCC_STATUS_BLK_HOST_ADDR
+ TG3_64BIT_REG_LOW
));
6204 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
6205 tr32(HOSTCC_STATS_BLK_NIC_ADDR
));
6206 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
6207 tr32(HOSTCC_STATUS_BLK_NIC_ADDR
));
6209 /* Memory arbiter control block */
6210 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
6211 tr32(MEMARB_MODE
), tr32(MEMARB_STATUS
));
6213 /* Buffer manager control block */
6214 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
6215 tr32(BUFMGR_MODE
), tr32(BUFMGR_STATUS
));
6216 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
6217 tr32(BUFMGR_MB_POOL_ADDR
), tr32(BUFMGR_MB_POOL_SIZE
));
6218 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
6219 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
6220 tr32(BUFMGR_DMA_DESC_POOL_ADDR
),
6221 tr32(BUFMGR_DMA_DESC_POOL_SIZE
));
6223 /* Read DMA control block */
6224 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
6225 tr32(RDMAC_MODE
), tr32(RDMAC_STATUS
));
6227 /* Write DMA control block */
6228 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
6229 tr32(WDMAC_MODE
), tr32(WDMAC_STATUS
));
6231 /* DMA completion block */
6232 printk("DEBUG: DMAC_MODE[%08x]\n",
6236 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
6237 tr32(GRC_MODE
), tr32(GRC_MISC_CFG
));
6238 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
6239 tr32(GRC_LOCAL_CTRL
));
6242 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
6243 tr32(RCVDBDI_JUMBO_BD
+ 0x0),
6244 tr32(RCVDBDI_JUMBO_BD
+ 0x4),
6245 tr32(RCVDBDI_JUMBO_BD
+ 0x8),
6246 tr32(RCVDBDI_JUMBO_BD
+ 0xc));
6247 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
6248 tr32(RCVDBDI_STD_BD
+ 0x0),
6249 tr32(RCVDBDI_STD_BD
+ 0x4),
6250 tr32(RCVDBDI_STD_BD
+ 0x8),
6251 tr32(RCVDBDI_STD_BD
+ 0xc));
6252 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
6253 tr32(RCVDBDI_MINI_BD
+ 0x0),
6254 tr32(RCVDBDI_MINI_BD
+ 0x4),
6255 tr32(RCVDBDI_MINI_BD
+ 0x8),
6256 tr32(RCVDBDI_MINI_BD
+ 0xc));
6258 tg3_read_mem(tp
, NIC_SRAM_SEND_RCB
+ 0x0, &val32
);
6259 tg3_read_mem(tp
, NIC_SRAM_SEND_RCB
+ 0x4, &val32_2
);
6260 tg3_read_mem(tp
, NIC_SRAM_SEND_RCB
+ 0x8, &val32_3
);
6261 tg3_read_mem(tp
, NIC_SRAM_SEND_RCB
+ 0xc, &val32_4
);
6262 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
6263 val32
, val32_2
, val32_3
, val32_4
);
6265 tg3_read_mem(tp
, NIC_SRAM_RCV_RET_RCB
+ 0x0, &val32
);
6266 tg3_read_mem(tp
, NIC_SRAM_RCV_RET_RCB
+ 0x4, &val32_2
);
6267 tg3_read_mem(tp
, NIC_SRAM_RCV_RET_RCB
+ 0x8, &val32_3
);
6268 tg3_read_mem(tp
, NIC_SRAM_RCV_RET_RCB
+ 0xc, &val32_4
);
6269 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
6270 val32
, val32_2
, val32_3
, val32_4
);
6272 tg3_read_mem(tp
, NIC_SRAM_STATUS_BLK
+ 0x0, &val32
);
6273 tg3_read_mem(tp
, NIC_SRAM_STATUS_BLK
+ 0x4, &val32_2
);
6274 tg3_read_mem(tp
, NIC_SRAM_STATUS_BLK
+ 0x8, &val32_3
);
6275 tg3_read_mem(tp
, NIC_SRAM_STATUS_BLK
+ 0xc, &val32_4
);
6276 tg3_read_mem(tp
, NIC_SRAM_STATUS_BLK
+ 0x10, &val32_5
);
6277 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
6278 val32
, val32_2
, val32_3
, val32_4
, val32_5
);
6280 /* SW status block */
6281 printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
6282 tp
->hw_status
->status
,
6283 tp
->hw_status
->status_tag
,
6284 tp
->hw_status
->rx_jumbo_consumer
,
6285 tp
->hw_status
->rx_consumer
,
6286 tp
->hw_status
->rx_mini_consumer
,
6287 tp
->hw_status
->idx
[0].rx_producer
,
6288 tp
->hw_status
->idx
[0].tx_consumer
);
6290 /* SW statistics block */
6291 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
6292 ((u32
*)tp
->hw_stats
)[0],
6293 ((u32
*)tp
->hw_stats
)[1],
6294 ((u32
*)tp
->hw_stats
)[2],
6295 ((u32
*)tp
->hw_stats
)[3]);
6298 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
6299 tr32(MAILBOX_SNDHOST_PROD_IDX_0
+ 0x0),
6300 tr32(MAILBOX_SNDHOST_PROD_IDX_0
+ 0x4),
6301 tr32(MAILBOX_SNDNIC_PROD_IDX_0
+ 0x0),
6302 tr32(MAILBOX_SNDNIC_PROD_IDX_0
+ 0x4));
6304 /* NIC side send descriptors. */
6305 for (i
= 0; i
< 6; i
++) {
6308 txd
= tp
->regs
+ NIC_SRAM_WIN_BASE
+ NIC_SRAM_TX_BUFFER_DESC
6309 + (i
* sizeof(struct tg3_tx_buffer_desc
));
6310 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
6312 readl(txd
+ 0x0), readl(txd
+ 0x4),
6313 readl(txd
+ 0x8), readl(txd
+ 0xc));
6316 /* NIC side RX descriptors. */
6317 for (i
= 0; i
< 6; i
++) {
6320 rxd
= tp
->regs
+ NIC_SRAM_WIN_BASE
+ NIC_SRAM_RX_BUFFER_DESC
6321 + (i
* sizeof(struct tg3_rx_buffer_desc
));
6322 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
6324 readl(rxd
+ 0x0), readl(rxd
+ 0x4),
6325 readl(rxd
+ 0x8), readl(rxd
+ 0xc));
6326 rxd
+= (4 * sizeof(u32
));
6327 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
6329 readl(rxd
+ 0x0), readl(rxd
+ 0x4),
6330 readl(rxd
+ 0x8), readl(rxd
+ 0xc));
6333 for (i
= 0; i
< 6; i
++) {
6336 rxd
= tp
->regs
+ NIC_SRAM_WIN_BASE
+ NIC_SRAM_RX_JUMBO_BUFFER_DESC
6337 + (i
* sizeof(struct tg3_rx_buffer_desc
));
6338 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
6340 readl(rxd
+ 0x0), readl(rxd
+ 0x4),
6341 readl(rxd
+ 0x8), readl(rxd
+ 0xc));
6342 rxd
+= (4 * sizeof(u32
));
6343 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
6345 readl(rxd
+ 0x0), readl(rxd
+ 0x4),
6346 readl(rxd
+ 0x8), readl(rxd
+ 0xc));
6351 static struct net_device_stats
*tg3_get_stats(struct net_device
*);
6352 static struct tg3_ethtool_stats
*tg3_get_estats(struct tg3
*);
6354 static int tg3_close(struct net_device
*dev
)
6356 struct tg3
*tp
= netdev_priv(dev
);
6358 netif_stop_queue(dev
);
6360 del_timer_sync(&tp
->timer
);
6362 spin_lock_irq(&tp
->lock
);
6363 spin_lock(&tp
->tx_lock
);
6368 tg3_disable_ints(tp
);
6373 ~(TG3_FLAG_INIT_COMPLETE
|
6374 TG3_FLAG_GOT_SERDES_FLOWCTL
);
6375 netif_carrier_off(tp
->dev
);
6377 spin_unlock(&tp
->tx_lock
);
6378 spin_unlock_irq(&tp
->lock
);
6380 free_irq(tp
->pdev
->irq
, dev
);
6381 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
6382 pci_disable_msi(tp
->pdev
);
6383 tp
->tg3_flags2
&= ~TG3_FLG2_USING_MSI
;
6386 memcpy(&tp
->net_stats_prev
, tg3_get_stats(tp
->dev
),
6387 sizeof(tp
->net_stats_prev
));
6388 memcpy(&tp
->estats_prev
, tg3_get_estats(tp
),
6389 sizeof(tp
->estats_prev
));
6391 tg3_free_consistent(tp
);
6396 static inline unsigned long get_stat64(tg3_stat64_t
*val
)
6400 #if (BITS_PER_LONG == 32)
6403 ret
= ((u64
)val
->high
<< 32) | ((u64
)val
->low
);
6408 static unsigned long calc_crc_errors(struct tg3
*tp
)
6410 struct tg3_hw_stats
*hw_stats
= tp
->hw_stats
;
6412 if (!(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) &&
6413 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
6414 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)) {
6415 unsigned long flags
;
6418 spin_lock_irqsave(&tp
->lock
, flags
);
6419 if (!tg3_readphy(tp
, 0x1e, &val
)) {
6420 tg3_writephy(tp
, 0x1e, val
| 0x8000);
6421 tg3_readphy(tp
, 0x14, &val
);
6424 spin_unlock_irqrestore(&tp
->lock
, flags
);
6426 tp
->phy_crc_errors
+= val
;
6428 return tp
->phy_crc_errors
;
6431 return get_stat64(&hw_stats
->rx_fcs_errors
);
6434 #define ESTAT_ADD(member) \
6435 estats->member = old_estats->member + \
6436 get_stat64(&hw_stats->member)
6438 static struct tg3_ethtool_stats
*tg3_get_estats(struct tg3
*tp
)
6440 struct tg3_ethtool_stats
*estats
= &tp
->estats
;
6441 struct tg3_ethtool_stats
*old_estats
= &tp
->estats_prev
;
6442 struct tg3_hw_stats
*hw_stats
= tp
->hw_stats
;
6447 ESTAT_ADD(rx_octets
);
6448 ESTAT_ADD(rx_fragments
);
6449 ESTAT_ADD(rx_ucast_packets
);
6450 ESTAT_ADD(rx_mcast_packets
);
6451 ESTAT_ADD(rx_bcast_packets
);
6452 ESTAT_ADD(rx_fcs_errors
);
6453 ESTAT_ADD(rx_align_errors
);
6454 ESTAT_ADD(rx_xon_pause_rcvd
);
6455 ESTAT_ADD(rx_xoff_pause_rcvd
);
6456 ESTAT_ADD(rx_mac_ctrl_rcvd
);
6457 ESTAT_ADD(rx_xoff_entered
);
6458 ESTAT_ADD(rx_frame_too_long_errors
);
6459 ESTAT_ADD(rx_jabbers
);
6460 ESTAT_ADD(rx_undersize_packets
);
6461 ESTAT_ADD(rx_in_length_errors
);
6462 ESTAT_ADD(rx_out_length_errors
);
6463 ESTAT_ADD(rx_64_or_less_octet_packets
);
6464 ESTAT_ADD(rx_65_to_127_octet_packets
);
6465 ESTAT_ADD(rx_128_to_255_octet_packets
);
6466 ESTAT_ADD(rx_256_to_511_octet_packets
);
6467 ESTAT_ADD(rx_512_to_1023_octet_packets
);
6468 ESTAT_ADD(rx_1024_to_1522_octet_packets
);
6469 ESTAT_ADD(rx_1523_to_2047_octet_packets
);
6470 ESTAT_ADD(rx_2048_to_4095_octet_packets
);
6471 ESTAT_ADD(rx_4096_to_8191_octet_packets
);
6472 ESTAT_ADD(rx_8192_to_9022_octet_packets
);
6474 ESTAT_ADD(tx_octets
);
6475 ESTAT_ADD(tx_collisions
);
6476 ESTAT_ADD(tx_xon_sent
);
6477 ESTAT_ADD(tx_xoff_sent
);
6478 ESTAT_ADD(tx_flow_control
);
6479 ESTAT_ADD(tx_mac_errors
);
6480 ESTAT_ADD(tx_single_collisions
);
6481 ESTAT_ADD(tx_mult_collisions
);
6482 ESTAT_ADD(tx_deferred
);
6483 ESTAT_ADD(tx_excessive_collisions
);
6484 ESTAT_ADD(tx_late_collisions
);
6485 ESTAT_ADD(tx_collide_2times
);
6486 ESTAT_ADD(tx_collide_3times
);
6487 ESTAT_ADD(tx_collide_4times
);
6488 ESTAT_ADD(tx_collide_5times
);
6489 ESTAT_ADD(tx_collide_6times
);
6490 ESTAT_ADD(tx_collide_7times
);
6491 ESTAT_ADD(tx_collide_8times
);
6492 ESTAT_ADD(tx_collide_9times
);
6493 ESTAT_ADD(tx_collide_10times
);
6494 ESTAT_ADD(tx_collide_11times
);
6495 ESTAT_ADD(tx_collide_12times
);
6496 ESTAT_ADD(tx_collide_13times
);
6497 ESTAT_ADD(tx_collide_14times
);
6498 ESTAT_ADD(tx_collide_15times
);
6499 ESTAT_ADD(tx_ucast_packets
);
6500 ESTAT_ADD(tx_mcast_packets
);
6501 ESTAT_ADD(tx_bcast_packets
);
6502 ESTAT_ADD(tx_carrier_sense_errors
);
6503 ESTAT_ADD(tx_discards
);
6504 ESTAT_ADD(tx_errors
);
6506 ESTAT_ADD(dma_writeq_full
);
6507 ESTAT_ADD(dma_write_prioq_full
);
6508 ESTAT_ADD(rxbds_empty
);
6509 ESTAT_ADD(rx_discards
);
6510 ESTAT_ADD(rx_errors
);
6511 ESTAT_ADD(rx_threshold_hit
);
6513 ESTAT_ADD(dma_readq_full
);
6514 ESTAT_ADD(dma_read_prioq_full
);
6515 ESTAT_ADD(tx_comp_queue_full
);
6517 ESTAT_ADD(ring_set_send_prod_index
);
6518 ESTAT_ADD(ring_status_update
);
6519 ESTAT_ADD(nic_irqs
);
6520 ESTAT_ADD(nic_avoided_irqs
);
6521 ESTAT_ADD(nic_tx_threshold_hit
);
6526 static struct net_device_stats
*tg3_get_stats(struct net_device
*dev
)
6528 struct tg3
*tp
= netdev_priv(dev
);
6529 struct net_device_stats
*stats
= &tp
->net_stats
;
6530 struct net_device_stats
*old_stats
= &tp
->net_stats_prev
;
6531 struct tg3_hw_stats
*hw_stats
= tp
->hw_stats
;
6536 stats
->rx_packets
= old_stats
->rx_packets
+
6537 get_stat64(&hw_stats
->rx_ucast_packets
) +
6538 get_stat64(&hw_stats
->rx_mcast_packets
) +
6539 get_stat64(&hw_stats
->rx_bcast_packets
);
6541 stats
->tx_packets
= old_stats
->tx_packets
+
6542 get_stat64(&hw_stats
->tx_ucast_packets
) +
6543 get_stat64(&hw_stats
->tx_mcast_packets
) +
6544 get_stat64(&hw_stats
->tx_bcast_packets
);
6546 stats
->rx_bytes
= old_stats
->rx_bytes
+
6547 get_stat64(&hw_stats
->rx_octets
);
6548 stats
->tx_bytes
= old_stats
->tx_bytes
+
6549 get_stat64(&hw_stats
->tx_octets
);
6551 stats
->rx_errors
= old_stats
->rx_errors
+
6552 get_stat64(&hw_stats
->rx_errors
) +
6553 get_stat64(&hw_stats
->rx_discards
);
6554 stats
->tx_errors
= old_stats
->tx_errors
+
6555 get_stat64(&hw_stats
->tx_errors
) +
6556 get_stat64(&hw_stats
->tx_mac_errors
) +
6557 get_stat64(&hw_stats
->tx_carrier_sense_errors
) +
6558 get_stat64(&hw_stats
->tx_discards
);
6560 stats
->multicast
= old_stats
->multicast
+
6561 get_stat64(&hw_stats
->rx_mcast_packets
);
6562 stats
->collisions
= old_stats
->collisions
+
6563 get_stat64(&hw_stats
->tx_collisions
);
6565 stats
->rx_length_errors
= old_stats
->rx_length_errors
+
6566 get_stat64(&hw_stats
->rx_frame_too_long_errors
) +
6567 get_stat64(&hw_stats
->rx_undersize_packets
);
6569 stats
->rx_over_errors
= old_stats
->rx_over_errors
+
6570 get_stat64(&hw_stats
->rxbds_empty
);
6571 stats
->rx_frame_errors
= old_stats
->rx_frame_errors
+
6572 get_stat64(&hw_stats
->rx_align_errors
);
6573 stats
->tx_aborted_errors
= old_stats
->tx_aborted_errors
+
6574 get_stat64(&hw_stats
->tx_discards
);
6575 stats
->tx_carrier_errors
= old_stats
->tx_carrier_errors
+
6576 get_stat64(&hw_stats
->tx_carrier_sense_errors
);
6578 stats
->rx_crc_errors
= old_stats
->rx_crc_errors
+
6579 calc_crc_errors(tp
);
6584 static inline u32
calc_crc(unsigned char *buf
, int len
)
6592 for (j
= 0; j
< len
; j
++) {
6595 for (k
= 0; k
< 8; k
++) {
6609 static void tg3_set_multi(struct tg3
*tp
, unsigned int accept_all
)
6611 /* accept or reject all multicast frames */
6612 tw32(MAC_HASH_REG_0
, accept_all
? 0xffffffff : 0);
6613 tw32(MAC_HASH_REG_1
, accept_all
? 0xffffffff : 0);
6614 tw32(MAC_HASH_REG_2
, accept_all
? 0xffffffff : 0);
6615 tw32(MAC_HASH_REG_3
, accept_all
? 0xffffffff : 0);
6618 static void __tg3_set_rx_mode(struct net_device
*dev
)
6620 struct tg3
*tp
= netdev_priv(dev
);
6623 rx_mode
= tp
->rx_mode
& ~(RX_MODE_PROMISC
|
6624 RX_MODE_KEEP_VLAN_TAG
);
6626 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
6629 #if TG3_VLAN_TAG_USED
6631 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
6632 rx_mode
|= RX_MODE_KEEP_VLAN_TAG
;
6634 /* By definition, VLAN is disabled always in this
6637 if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
6638 rx_mode
|= RX_MODE_KEEP_VLAN_TAG
;
6641 if (dev
->flags
& IFF_PROMISC
) {
6642 /* Promiscuous mode. */
6643 rx_mode
|= RX_MODE_PROMISC
;
6644 } else if (dev
->flags
& IFF_ALLMULTI
) {
6645 /* Accept all multicast. */
6646 tg3_set_multi (tp
, 1);
6647 } else if (dev
->mc_count
< 1) {
6648 /* Reject all multicast. */
6649 tg3_set_multi (tp
, 0);
6651 /* Accept one or more multicast(s). */
6652 struct dev_mc_list
*mclist
;
6654 u32 mc_filter
[4] = { 0, };
6659 for (i
= 0, mclist
= dev
->mc_list
; mclist
&& i
< dev
->mc_count
;
6660 i
++, mclist
= mclist
->next
) {
6662 crc
= calc_crc (mclist
->dmi_addr
, ETH_ALEN
);
6664 regidx
= (bit
& 0x60) >> 5;
6666 mc_filter
[regidx
] |= (1 << bit
);
6669 tw32(MAC_HASH_REG_0
, mc_filter
[0]);
6670 tw32(MAC_HASH_REG_1
, mc_filter
[1]);
6671 tw32(MAC_HASH_REG_2
, mc_filter
[2]);
6672 tw32(MAC_HASH_REG_3
, mc_filter
[3]);
6675 if (rx_mode
!= tp
->rx_mode
) {
6676 tp
->rx_mode
= rx_mode
;
6677 tw32_f(MAC_RX_MODE
, rx_mode
);
6682 static void tg3_set_rx_mode(struct net_device
*dev
)
6684 struct tg3
*tp
= netdev_priv(dev
);
6686 spin_lock_irq(&tp
->lock
);
6687 spin_lock(&tp
->tx_lock
);
6688 __tg3_set_rx_mode(dev
);
6689 spin_unlock(&tp
->tx_lock
);
6690 spin_unlock_irq(&tp
->lock
);
6693 #define TG3_REGDUMP_LEN (32 * 1024)
6695 static int tg3_get_regs_len(struct net_device
*dev
)
6697 return TG3_REGDUMP_LEN
;
6700 static void tg3_get_regs(struct net_device
*dev
,
6701 struct ethtool_regs
*regs
, void *_p
)
6704 struct tg3
*tp
= netdev_priv(dev
);
6710 memset(p
, 0, TG3_REGDUMP_LEN
);
6712 spin_lock_irq(&tp
->lock
);
6713 spin_lock(&tp
->tx_lock
);
6715 #define __GET_REG32(reg) (*(p)++ = tr32(reg))
6716 #define GET_REG32_LOOP(base,len) \
6717 do { p = (u32 *)(orig_p + (base)); \
6718 for (i = 0; i < len; i += 4) \
6719 __GET_REG32((base) + i); \
6721 #define GET_REG32_1(reg) \
6722 do { p = (u32 *)(orig_p + (reg)); \
6723 __GET_REG32((reg)); \
6726 GET_REG32_LOOP(TG3PCI_VENDOR
, 0xb0);
6727 GET_REG32_LOOP(MAILBOX_INTERRUPT_0
, 0x200);
6728 GET_REG32_LOOP(MAC_MODE
, 0x4f0);
6729 GET_REG32_LOOP(SNDDATAI_MODE
, 0xe0);
6730 GET_REG32_1(SNDDATAC_MODE
);
6731 GET_REG32_LOOP(SNDBDS_MODE
, 0x80);
6732 GET_REG32_LOOP(SNDBDI_MODE
, 0x48);
6733 GET_REG32_1(SNDBDC_MODE
);
6734 GET_REG32_LOOP(RCVLPC_MODE
, 0x20);
6735 GET_REG32_LOOP(RCVLPC_SELLST_BASE
, 0x15c);
6736 GET_REG32_LOOP(RCVDBDI_MODE
, 0x0c);
6737 GET_REG32_LOOP(RCVDBDI_JUMBO_BD
, 0x3c);
6738 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0
, 0x44);
6739 GET_REG32_1(RCVDCC_MODE
);
6740 GET_REG32_LOOP(RCVBDI_MODE
, 0x20);
6741 GET_REG32_LOOP(RCVCC_MODE
, 0x14);
6742 GET_REG32_LOOP(RCVLSC_MODE
, 0x08);
6743 GET_REG32_1(MBFREE_MODE
);
6744 GET_REG32_LOOP(HOSTCC_MODE
, 0x100);
6745 GET_REG32_LOOP(MEMARB_MODE
, 0x10);
6746 GET_REG32_LOOP(BUFMGR_MODE
, 0x58);
6747 GET_REG32_LOOP(RDMAC_MODE
, 0x08);
6748 GET_REG32_LOOP(WDMAC_MODE
, 0x08);
6749 GET_REG32_LOOP(RX_CPU_BASE
, 0x280);
6750 GET_REG32_LOOP(TX_CPU_BASE
, 0x280);
6751 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0
, 0x110);
6752 GET_REG32_LOOP(FTQ_RESET
, 0x120);
6753 GET_REG32_LOOP(MSGINT_MODE
, 0x0c);
6754 GET_REG32_1(DMAC_MODE
);
6755 GET_REG32_LOOP(GRC_MODE
, 0x4c);
6756 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
)
6757 GET_REG32_LOOP(NVRAM_CMD
, 0x24);
6760 #undef GET_REG32_LOOP
6763 spin_unlock(&tp
->tx_lock
);
6764 spin_unlock_irq(&tp
->lock
);
6767 static int tg3_get_eeprom_len(struct net_device
*dev
)
6769 struct tg3
*tp
= netdev_priv(dev
);
6771 return tp
->nvram_size
;
6774 static int tg3_nvram_read(struct tg3
*tp
, u32 offset
, u32
*val
);
6776 static int tg3_get_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
, u8
*data
)
6778 struct tg3
*tp
= netdev_priv(dev
);
6781 u32 i
, offset
, len
, val
, b_offset
, b_count
;
6783 offset
= eeprom
->offset
;
6787 eeprom
->magic
= TG3_EEPROM_MAGIC
;
6790 /* adjustments to start on required 4 byte boundary */
6791 b_offset
= offset
& 3;
6792 b_count
= 4 - b_offset
;
6793 if (b_count
> len
) {
6794 /* i.e. offset=1 len=2 */
6797 ret
= tg3_nvram_read(tp
, offset
-b_offset
, &val
);
6800 val
= cpu_to_le32(val
);
6801 memcpy(data
, ((char*)&val
) + b_offset
, b_count
);
6804 eeprom
->len
+= b_count
;
6807 /* read bytes upto the last 4 byte boundary */
6808 pd
= &data
[eeprom
->len
];
6809 for (i
= 0; i
< (len
- (len
& 3)); i
+= 4) {
6810 ret
= tg3_nvram_read(tp
, offset
+ i
, &val
);
6815 val
= cpu_to_le32(val
);
6816 memcpy(pd
+ i
, &val
, 4);
6821 /* read last bytes not ending on 4 byte boundary */
6822 pd
= &data
[eeprom
->len
];
6824 b_offset
= offset
+ len
- b_count
;
6825 ret
= tg3_nvram_read(tp
, b_offset
, &val
);
6828 val
= cpu_to_le32(val
);
6829 memcpy(pd
, ((char*)&val
), b_count
);
6830 eeprom
->len
+= b_count
;
6835 static int tg3_nvram_write_block(struct tg3
*tp
, u32 offset
, u32 len
, u8
*buf
);
6837 static int tg3_set_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
, u8
*data
)
6839 struct tg3
*tp
= netdev_priv(dev
);
6841 u32 offset
, len
, b_offset
, odd_len
, start
, end
;
6844 if (eeprom
->magic
!= TG3_EEPROM_MAGIC
)
6847 offset
= eeprom
->offset
;
6850 if ((b_offset
= (offset
& 3))) {
6851 /* adjustments to start on required 4 byte boundary */
6852 ret
= tg3_nvram_read(tp
, offset
-b_offset
, &start
);
6855 start
= cpu_to_le32(start
);
6864 /* adjustments to end on required 4 byte boundary */
6866 len
= (len
+ 3) & ~3;
6867 ret
= tg3_nvram_read(tp
, offset
+len
-4, &end
);
6870 end
= cpu_to_le32(end
);
6874 if (b_offset
|| odd_len
) {
6875 buf
= kmalloc(len
, GFP_KERNEL
);
6879 memcpy(buf
, &start
, 4);
6881 memcpy(buf
+len
-4, &end
, 4);
6882 memcpy(buf
+ b_offset
, data
, eeprom
->len
);
6885 ret
= tg3_nvram_write_block(tp
, offset
, len
, buf
);
6893 static int tg3_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
6895 struct tg3
*tp
= netdev_priv(dev
);
6897 cmd
->supported
= (SUPPORTED_Autoneg
);
6899 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
))
6900 cmd
->supported
|= (SUPPORTED_1000baseT_Half
|
6901 SUPPORTED_1000baseT_Full
);
6903 if (!(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
))
6904 cmd
->supported
|= (SUPPORTED_100baseT_Half
|
6905 SUPPORTED_100baseT_Full
|
6906 SUPPORTED_10baseT_Half
|
6907 SUPPORTED_10baseT_Full
|
6910 cmd
->supported
|= SUPPORTED_FIBRE
;
6912 cmd
->advertising
= tp
->link_config
.advertising
;
6913 if (netif_running(dev
)) {
6914 cmd
->speed
= tp
->link_config
.active_speed
;
6915 cmd
->duplex
= tp
->link_config
.active_duplex
;
6918 cmd
->phy_address
= PHY_ADDR
;
6919 cmd
->transceiver
= 0;
6920 cmd
->autoneg
= tp
->link_config
.autoneg
;
6926 static int tg3_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
6928 struct tg3
*tp
= netdev_priv(dev
);
6930 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
6931 /* These are the only valid advertisement bits allowed. */
6932 if (cmd
->autoneg
== AUTONEG_ENABLE
&&
6933 (cmd
->advertising
& ~(ADVERTISED_1000baseT_Half
|
6934 ADVERTISED_1000baseT_Full
|
6935 ADVERTISED_Autoneg
|
6940 spin_lock_irq(&tp
->lock
);
6941 spin_lock(&tp
->tx_lock
);
6943 tp
->link_config
.autoneg
= cmd
->autoneg
;
6944 if (cmd
->autoneg
== AUTONEG_ENABLE
) {
6945 tp
->link_config
.advertising
= cmd
->advertising
;
6946 tp
->link_config
.speed
= SPEED_INVALID
;
6947 tp
->link_config
.duplex
= DUPLEX_INVALID
;
6949 tp
->link_config
.advertising
= 0;
6950 tp
->link_config
.speed
= cmd
->speed
;
6951 tp
->link_config
.duplex
= cmd
->duplex
;
6954 if (netif_running(dev
))
6955 tg3_setup_phy(tp
, 1);
6957 spin_unlock(&tp
->tx_lock
);
6958 spin_unlock_irq(&tp
->lock
);
6963 static void tg3_get_drvinfo(struct net_device
*dev
, struct ethtool_drvinfo
*info
)
6965 struct tg3
*tp
= netdev_priv(dev
);
6967 strcpy(info
->driver
, DRV_MODULE_NAME
);
6968 strcpy(info
->version
, DRV_MODULE_VERSION
);
6969 strcpy(info
->bus_info
, pci_name(tp
->pdev
));
6972 static void tg3_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
6974 struct tg3
*tp
= netdev_priv(dev
);
6976 wol
->supported
= WAKE_MAGIC
;
6978 if (tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
)
6979 wol
->wolopts
= WAKE_MAGIC
;
6980 memset(&wol
->sopass
, 0, sizeof(wol
->sopass
));
6983 static int tg3_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
6985 struct tg3
*tp
= netdev_priv(dev
);
6987 if (wol
->wolopts
& ~WAKE_MAGIC
)
6989 if ((wol
->wolopts
& WAKE_MAGIC
) &&
6990 tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
&&
6991 !(tp
->tg3_flags
& TG3_FLAG_SERDES_WOL_CAP
))
6994 spin_lock_irq(&tp
->lock
);
6995 if (wol
->wolopts
& WAKE_MAGIC
)
6996 tp
->tg3_flags
|= TG3_FLAG_WOL_ENABLE
;
6998 tp
->tg3_flags
&= ~TG3_FLAG_WOL_ENABLE
;
6999 spin_unlock_irq(&tp
->lock
);
7004 static u32
tg3_get_msglevel(struct net_device
*dev
)
7006 struct tg3
*tp
= netdev_priv(dev
);
7007 return tp
->msg_enable
;
7010 static void tg3_set_msglevel(struct net_device
*dev
, u32 value
)
7012 struct tg3
*tp
= netdev_priv(dev
);
7013 tp
->msg_enable
= value
;
7016 #if TG3_TSO_SUPPORT != 0
7017 static int tg3_set_tso(struct net_device
*dev
, u32 value
)
7019 struct tg3
*tp
= netdev_priv(dev
);
7021 if (!(tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
)) {
7026 return ethtool_op_set_tso(dev
, value
);
7030 static int tg3_nway_reset(struct net_device
*dev
)
7032 struct tg3
*tp
= netdev_priv(dev
);
7036 if (!netif_running(dev
))
7039 spin_lock_irq(&tp
->lock
);
7041 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
7042 if (!tg3_readphy(tp
, MII_BMCR
, &bmcr
) &&
7043 (bmcr
& BMCR_ANENABLE
)) {
7044 tg3_writephy(tp
, MII_BMCR
, bmcr
| BMCR_ANRESTART
);
7047 spin_unlock_irq(&tp
->lock
);
7052 static void tg3_get_ringparam(struct net_device
*dev
, struct ethtool_ringparam
*ering
)
7054 struct tg3
*tp
= netdev_priv(dev
);
7056 ering
->rx_max_pending
= TG3_RX_RING_SIZE
- 1;
7057 ering
->rx_mini_max_pending
= 0;
7058 ering
->rx_jumbo_max_pending
= TG3_RX_JUMBO_RING_SIZE
- 1;
7060 ering
->rx_pending
= tp
->rx_pending
;
7061 ering
->rx_mini_pending
= 0;
7062 ering
->rx_jumbo_pending
= tp
->rx_jumbo_pending
;
7063 ering
->tx_pending
= tp
->tx_pending
;
7066 static int tg3_set_ringparam(struct net_device
*dev
, struct ethtool_ringparam
*ering
)
7068 struct tg3
*tp
= netdev_priv(dev
);
7070 if ((ering
->rx_pending
> TG3_RX_RING_SIZE
- 1) ||
7071 (ering
->rx_jumbo_pending
> TG3_RX_JUMBO_RING_SIZE
- 1) ||
7072 (ering
->tx_pending
> TG3_TX_RING_SIZE
- 1))
7075 if (netif_running(dev
))
7078 spin_lock_irq(&tp
->lock
);
7079 spin_lock(&tp
->tx_lock
);
7081 tp
->rx_pending
= ering
->rx_pending
;
7083 if ((tp
->tg3_flags2
& TG3_FLG2_MAX_RXPEND_64
) &&
7084 tp
->rx_pending
> 63)
7085 tp
->rx_pending
= 63;
7086 tp
->rx_jumbo_pending
= ering
->rx_jumbo_pending
;
7087 tp
->tx_pending
= ering
->tx_pending
;
7089 if (netif_running(dev
)) {
7092 tg3_netif_start(tp
);
7095 spin_unlock(&tp
->tx_lock
);
7096 spin_unlock_irq(&tp
->lock
);
7101 static void tg3_get_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
*epause
)
7103 struct tg3
*tp
= netdev_priv(dev
);
7105 epause
->autoneg
= (tp
->tg3_flags
& TG3_FLAG_PAUSE_AUTONEG
) != 0;
7106 epause
->rx_pause
= (tp
->tg3_flags
& TG3_FLAG_RX_PAUSE
) != 0;
7107 epause
->tx_pause
= (tp
->tg3_flags
& TG3_FLAG_TX_PAUSE
) != 0;
7110 static int tg3_set_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
*epause
)
7112 struct tg3
*tp
= netdev_priv(dev
);
7114 if (netif_running(dev
))
7117 spin_lock_irq(&tp
->lock
);
7118 spin_lock(&tp
->tx_lock
);
7119 if (epause
->autoneg
)
7120 tp
->tg3_flags
|= TG3_FLAG_PAUSE_AUTONEG
;
7122 tp
->tg3_flags
&= ~TG3_FLAG_PAUSE_AUTONEG
;
7123 if (epause
->rx_pause
)
7124 tp
->tg3_flags
|= TG3_FLAG_RX_PAUSE
;
7126 tp
->tg3_flags
&= ~TG3_FLAG_RX_PAUSE
;
7127 if (epause
->tx_pause
)
7128 tp
->tg3_flags
|= TG3_FLAG_TX_PAUSE
;
7130 tp
->tg3_flags
&= ~TG3_FLAG_TX_PAUSE
;
7132 if (netif_running(dev
)) {
7135 tg3_netif_start(tp
);
7137 spin_unlock(&tp
->tx_lock
);
7138 spin_unlock_irq(&tp
->lock
);
7143 static u32
tg3_get_rx_csum(struct net_device
*dev
)
7145 struct tg3
*tp
= netdev_priv(dev
);
7146 return (tp
->tg3_flags
& TG3_FLAG_RX_CHECKSUMS
) != 0;
7149 static int tg3_set_rx_csum(struct net_device
*dev
, u32 data
)
7151 struct tg3
*tp
= netdev_priv(dev
);
7153 if (tp
->tg3_flags
& TG3_FLAG_BROKEN_CHECKSUMS
) {
7159 spin_lock_irq(&tp
->lock
);
7161 tp
->tg3_flags
|= TG3_FLAG_RX_CHECKSUMS
;
7163 tp
->tg3_flags
&= ~TG3_FLAG_RX_CHECKSUMS
;
7164 spin_unlock_irq(&tp
->lock
);
7169 static int tg3_set_tx_csum(struct net_device
*dev
, u32 data
)
7171 struct tg3
*tp
= netdev_priv(dev
);
7173 if (tp
->tg3_flags
& TG3_FLAG_BROKEN_CHECKSUMS
) {
7180 dev
->features
|= NETIF_F_IP_CSUM
;
7182 dev
->features
&= ~NETIF_F_IP_CSUM
;
7187 static int tg3_get_stats_count (struct net_device
*dev
)
7189 return TG3_NUM_STATS
;
7192 static void tg3_get_strings (struct net_device
*dev
, u32 stringset
, u8
*buf
)
7194 switch (stringset
) {
7196 memcpy(buf
, ðtool_stats_keys
, sizeof(ethtool_stats_keys
));
7199 WARN_ON(1); /* we need a WARN() */
7204 static void tg3_get_ethtool_stats (struct net_device
*dev
,
7205 struct ethtool_stats
*estats
, u64
*tmp_stats
)
7207 struct tg3
*tp
= netdev_priv(dev
);
7208 memcpy(tmp_stats
, tg3_get_estats(tp
), sizeof(tp
->estats
));
7211 static int tg3_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
7213 struct mii_ioctl_data
*data
= if_mii(ifr
);
7214 struct tg3
*tp
= netdev_priv(dev
);
7219 data
->phy_id
= PHY_ADDR
;
7225 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)
7226 break; /* We have no PHY */
7228 spin_lock_irq(&tp
->lock
);
7229 err
= tg3_readphy(tp
, data
->reg_num
& 0x1f, &mii_regval
);
7230 spin_unlock_irq(&tp
->lock
);
7232 data
->val_out
= mii_regval
;
7238 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)
7239 break; /* We have no PHY */
7241 if (!capable(CAP_NET_ADMIN
))
7244 spin_lock_irq(&tp
->lock
);
7245 err
= tg3_writephy(tp
, data
->reg_num
& 0x1f, data
->val_in
);
7246 spin_unlock_irq(&tp
->lock
);
7257 #if TG3_VLAN_TAG_USED
7258 static void tg3_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*grp
)
7260 struct tg3
*tp
= netdev_priv(dev
);
7262 spin_lock_irq(&tp
->lock
);
7263 spin_lock(&tp
->tx_lock
);
7267 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
7268 __tg3_set_rx_mode(dev
);
7270 spin_unlock(&tp
->tx_lock
);
7271 spin_unlock_irq(&tp
->lock
);
7274 static void tg3_vlan_rx_kill_vid(struct net_device
*dev
, unsigned short vid
)
7276 struct tg3
*tp
= netdev_priv(dev
);
7278 spin_lock_irq(&tp
->lock
);
7279 spin_lock(&tp
->tx_lock
);
7281 tp
->vlgrp
->vlan_devices
[vid
] = NULL
;
7282 spin_unlock(&tp
->tx_lock
);
7283 spin_unlock_irq(&tp
->lock
);
7287 static struct ethtool_ops tg3_ethtool_ops
= {
7288 .get_settings
= tg3_get_settings
,
7289 .set_settings
= tg3_set_settings
,
7290 .get_drvinfo
= tg3_get_drvinfo
,
7291 .get_regs_len
= tg3_get_regs_len
,
7292 .get_regs
= tg3_get_regs
,
7293 .get_wol
= tg3_get_wol
,
7294 .set_wol
= tg3_set_wol
,
7295 .get_msglevel
= tg3_get_msglevel
,
7296 .set_msglevel
= tg3_set_msglevel
,
7297 .nway_reset
= tg3_nway_reset
,
7298 .get_link
= ethtool_op_get_link
,
7299 .get_eeprom_len
= tg3_get_eeprom_len
,
7300 .get_eeprom
= tg3_get_eeprom
,
7301 .set_eeprom
= tg3_set_eeprom
,
7302 .get_ringparam
= tg3_get_ringparam
,
7303 .set_ringparam
= tg3_set_ringparam
,
7304 .get_pauseparam
= tg3_get_pauseparam
,
7305 .set_pauseparam
= tg3_set_pauseparam
,
7306 .get_rx_csum
= tg3_get_rx_csum
,
7307 .set_rx_csum
= tg3_set_rx_csum
,
7308 .get_tx_csum
= ethtool_op_get_tx_csum
,
7309 .set_tx_csum
= tg3_set_tx_csum
,
7310 .get_sg
= ethtool_op_get_sg
,
7311 .set_sg
= ethtool_op_set_sg
,
7312 #if TG3_TSO_SUPPORT != 0
7313 .get_tso
= ethtool_op_get_tso
,
7314 .set_tso
= tg3_set_tso
,
7316 .get_strings
= tg3_get_strings
,
7317 .get_stats_count
= tg3_get_stats_count
,
7318 .get_ethtool_stats
= tg3_get_ethtool_stats
,
7321 static void __devinit
tg3_get_eeprom_size(struct tg3
*tp
)
7325 tp
->nvram_size
= EEPROM_CHIP_SIZE
;
7327 if (tg3_nvram_read(tp
, 0, &val
) != 0)
7330 if (swab32(val
) != TG3_EEPROM_MAGIC
)
7334 * Size the chip by reading offsets at increasing powers of two.
7335 * When we encounter our validation signature, we know the addressing
7336 * has wrapped around, and thus have our chip size.
7340 while (cursize
< tp
->nvram_size
) {
7341 if (tg3_nvram_read(tp
, cursize
, &val
) != 0)
7344 if (swab32(val
) == TG3_EEPROM_MAGIC
)
7350 tp
->nvram_size
= cursize
;
7353 static void __devinit
tg3_get_nvram_size(struct tg3
*tp
)
7357 if (tg3_nvram_read(tp
, 0xf0, &val
) == 0) {
7359 tp
->nvram_size
= (val
>> 16) * 1024;
7363 tp
->nvram_size
= 0x20000;
7366 static void __devinit
tg3_get_nvram_info(struct tg3
*tp
)
7370 nvcfg1
= tr32(NVRAM_CFG1
);
7371 if (nvcfg1
& NVRAM_CFG1_FLASHIF_ENAB
) {
7372 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
7375 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
7376 tw32(NVRAM_CFG1
, nvcfg1
);
7379 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
) {
7380 switch (nvcfg1
& NVRAM_CFG1_VENDOR_MASK
) {
7381 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED
:
7382 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
7383 tp
->nvram_pagesize
= ATMEL_AT45DB0X1B_PAGE_SIZE
;
7384 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
7386 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED
:
7387 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
7388 tp
->nvram_pagesize
= ATMEL_AT25F512_PAGE_SIZE
;
7390 case FLASH_VENDOR_ATMEL_EEPROM
:
7391 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
7392 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
7393 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
7395 case FLASH_VENDOR_ST
:
7396 tp
->nvram_jedecnum
= JEDEC_ST
;
7397 tp
->nvram_pagesize
= ST_M45PEX0_PAGE_SIZE
;
7398 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
7400 case FLASH_VENDOR_SAIFUN
:
7401 tp
->nvram_jedecnum
= JEDEC_SAIFUN
;
7402 tp
->nvram_pagesize
= SAIFUN_SA25F0XX_PAGE_SIZE
;
7404 case FLASH_VENDOR_SST_SMALL
:
7405 case FLASH_VENDOR_SST_LARGE
:
7406 tp
->nvram_jedecnum
= JEDEC_SST
;
7407 tp
->nvram_pagesize
= SST_25VF0X0_PAGE_SIZE
;
7412 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
7413 tp
->nvram_pagesize
= ATMEL_AT45DB0X1B_PAGE_SIZE
;
7414 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
7418 static void __devinit
tg3_get_5752_nvram_info(struct tg3
*tp
)
7422 nvcfg1
= tr32(NVRAM_CFG1
);
7424 /* NVRAM protection for TPM */
7425 if (nvcfg1
& (1 << 27))
7426 tp
->tg3_flags2
|= TG3_FLG2_PROTECTED_NVRAM
;
7428 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
7429 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ
:
7430 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ
:
7431 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
7432 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
7434 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
7435 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
7436 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
7437 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
7439 case FLASH_5752VENDOR_ST_M45PE10
:
7440 case FLASH_5752VENDOR_ST_M45PE20
:
7441 case FLASH_5752VENDOR_ST_M45PE40
:
7442 tp
->nvram_jedecnum
= JEDEC_ST
;
7443 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
7444 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
7448 if (tp
->tg3_flags2
& TG3_FLG2_FLASH
) {
7449 switch (nvcfg1
& NVRAM_CFG1_5752PAGE_SIZE_MASK
) {
7450 case FLASH_5752PAGE_SIZE_256
:
7451 tp
->nvram_pagesize
= 256;
7453 case FLASH_5752PAGE_SIZE_512
:
7454 tp
->nvram_pagesize
= 512;
7456 case FLASH_5752PAGE_SIZE_1K
:
7457 tp
->nvram_pagesize
= 1024;
7459 case FLASH_5752PAGE_SIZE_2K
:
7460 tp
->nvram_pagesize
= 2048;
7462 case FLASH_5752PAGE_SIZE_4K
:
7463 tp
->nvram_pagesize
= 4096;
7465 case FLASH_5752PAGE_SIZE_264
:
7466 tp
->nvram_pagesize
= 264;
7471 /* For eeprom, set pagesize to maximum eeprom size */
7472 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
7474 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
7475 tw32(NVRAM_CFG1
, nvcfg1
);
7479 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
7480 static void __devinit
tg3_nvram_init(struct tg3
*tp
)
7484 if (tp
->tg3_flags2
& TG3_FLG2_SUN_570X
)
7487 tw32_f(GRC_EEPROM_ADDR
,
7488 (EEPROM_ADDR_FSM_RESET
|
7489 (EEPROM_DEFAULT_CLOCK_PERIOD
<<
7490 EEPROM_ADDR_CLKPERD_SHIFT
)));
7492 /* XXX schedule_timeout() ... */
7493 for (j
= 0; j
< 100; j
++)
7496 /* Enable seeprom accesses. */
7497 tw32_f(GRC_LOCAL_CTRL
,
7498 tr32(GRC_LOCAL_CTRL
) | GRC_LCLCTRL_AUTO_SEEPROM
);
7501 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
7502 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
) {
7503 tp
->tg3_flags
|= TG3_FLAG_NVRAM
;
7505 tg3_enable_nvram_access(tp
);
7507 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
)
7508 tg3_get_5752_nvram_info(tp
);
7510 tg3_get_nvram_info(tp
);
7512 tg3_get_nvram_size(tp
);
7514 tg3_disable_nvram_access(tp
);
7517 tp
->tg3_flags
&= ~(TG3_FLAG_NVRAM
| TG3_FLAG_NVRAM_BUFFERED
);
7519 tg3_get_eeprom_size(tp
);
7523 static int tg3_nvram_read_using_eeprom(struct tg3
*tp
,
7524 u32 offset
, u32
*val
)
7529 if (offset
> EEPROM_ADDR_ADDR_MASK
||
7533 tmp
= tr32(GRC_EEPROM_ADDR
) & ~(EEPROM_ADDR_ADDR_MASK
|
7534 EEPROM_ADDR_DEVID_MASK
|
7536 tw32(GRC_EEPROM_ADDR
,
7538 (0 << EEPROM_ADDR_DEVID_SHIFT
) |
7539 ((offset
<< EEPROM_ADDR_ADDR_SHIFT
) &
7540 EEPROM_ADDR_ADDR_MASK
) |
7541 EEPROM_ADDR_READ
| EEPROM_ADDR_START
);
7543 for (i
= 0; i
< 10000; i
++) {
7544 tmp
= tr32(GRC_EEPROM_ADDR
);
7546 if (tmp
& EEPROM_ADDR_COMPLETE
)
7550 if (!(tmp
& EEPROM_ADDR_COMPLETE
))
7553 *val
= tr32(GRC_EEPROM_DATA
);
7557 #define NVRAM_CMD_TIMEOUT 10000
7559 static int tg3_nvram_exec_cmd(struct tg3
*tp
, u32 nvram_cmd
)
7563 tw32(NVRAM_CMD
, nvram_cmd
);
7564 for (i
= 0; i
< NVRAM_CMD_TIMEOUT
; i
++) {
7566 if (tr32(NVRAM_CMD
) & NVRAM_CMD_DONE
) {
7571 if (i
== NVRAM_CMD_TIMEOUT
) {
7577 static int tg3_nvram_read(struct tg3
*tp
, u32 offset
, u32
*val
)
7581 if (tp
->tg3_flags2
& TG3_FLG2_SUN_570X
) {
7582 printk(KERN_ERR PFX
"Attempt to do nvram_read on Sun 570X\n");
7586 if (!(tp
->tg3_flags
& TG3_FLAG_NVRAM
))
7587 return tg3_nvram_read_using_eeprom(tp
, offset
, val
);
7589 if ((tp
->tg3_flags
& TG3_FLAG_NVRAM_BUFFERED
) &&
7590 (tp
->tg3_flags2
& TG3_FLG2_FLASH
) &&
7591 (tp
->nvram_jedecnum
== JEDEC_ATMEL
)) {
7593 offset
= ((offset
/ tp
->nvram_pagesize
) <<
7594 ATMEL_AT45DB0X1B_PAGE_POS
) +
7595 (offset
% tp
->nvram_pagesize
);
7598 if (offset
> NVRAM_ADDR_MSK
)
7603 tg3_enable_nvram_access(tp
);
7605 tw32(NVRAM_ADDR
, offset
);
7606 ret
= tg3_nvram_exec_cmd(tp
, NVRAM_CMD_RD
| NVRAM_CMD_GO
|
7607 NVRAM_CMD_FIRST
| NVRAM_CMD_LAST
| NVRAM_CMD_DONE
);
7610 *val
= swab32(tr32(NVRAM_RDDATA
));
7612 tg3_nvram_unlock(tp
);
7614 tg3_disable_nvram_access(tp
);
7619 static int tg3_nvram_write_block_using_eeprom(struct tg3
*tp
,
7620 u32 offset
, u32 len
, u8
*buf
)
7625 for (i
= 0; i
< len
; i
+= 4) {
7630 memcpy(&data
, buf
+ i
, 4);
7632 tw32(GRC_EEPROM_DATA
, cpu_to_le32(data
));
7634 val
= tr32(GRC_EEPROM_ADDR
);
7635 tw32(GRC_EEPROM_ADDR
, val
| EEPROM_ADDR_COMPLETE
);
7637 val
&= ~(EEPROM_ADDR_ADDR_MASK
| EEPROM_ADDR_DEVID_MASK
|
7639 tw32(GRC_EEPROM_ADDR
, val
|
7640 (0 << EEPROM_ADDR_DEVID_SHIFT
) |
7641 (addr
& EEPROM_ADDR_ADDR_MASK
) |
7645 for (j
= 0; j
< 10000; j
++) {
7646 val
= tr32(GRC_EEPROM_ADDR
);
7648 if (val
& EEPROM_ADDR_COMPLETE
)
7652 if (!(val
& EEPROM_ADDR_COMPLETE
)) {
7661 /* offset and length are dword aligned */
7662 static int tg3_nvram_write_block_unbuffered(struct tg3
*tp
, u32 offset
, u32 len
,
7666 u32 pagesize
= tp
->nvram_pagesize
;
7667 u32 pagemask
= pagesize
- 1;
7671 tmp
= kmalloc(pagesize
, GFP_KERNEL
);
7677 u32 phy_addr
, page_off
, size
;
7679 phy_addr
= offset
& ~pagemask
;
7681 for (j
= 0; j
< pagesize
; j
+= 4) {
7682 if ((ret
= tg3_nvram_read(tp
, phy_addr
+ j
,
7683 (u32
*) (tmp
+ j
))))
7689 page_off
= offset
& pagemask
;
7696 memcpy(tmp
+ page_off
, buf
, size
);
7698 offset
= offset
+ (pagesize
- page_off
);
7700 tg3_enable_nvram_access(tp
);
7703 * Before we can erase the flash page, we need
7704 * to issue a special "write enable" command.
7706 nvram_cmd
= NVRAM_CMD_WREN
| NVRAM_CMD_GO
| NVRAM_CMD_DONE
;
7708 if (tg3_nvram_exec_cmd(tp
, nvram_cmd
))
7711 /* Erase the target page */
7712 tw32(NVRAM_ADDR
, phy_addr
);
7714 nvram_cmd
= NVRAM_CMD_GO
| NVRAM_CMD_DONE
| NVRAM_CMD_WR
|
7715 NVRAM_CMD_FIRST
| NVRAM_CMD_LAST
| NVRAM_CMD_ERASE
;
7717 if (tg3_nvram_exec_cmd(tp
, nvram_cmd
))
7720 /* Issue another write enable to start the write. */
7721 nvram_cmd
= NVRAM_CMD_WREN
| NVRAM_CMD_GO
| NVRAM_CMD_DONE
;
7723 if (tg3_nvram_exec_cmd(tp
, nvram_cmd
))
7726 for (j
= 0; j
< pagesize
; j
+= 4) {
7729 data
= *((u32
*) (tmp
+ j
));
7730 tw32(NVRAM_WRDATA
, cpu_to_be32(data
));
7732 tw32(NVRAM_ADDR
, phy_addr
+ j
);
7734 nvram_cmd
= NVRAM_CMD_GO
| NVRAM_CMD_DONE
|
7738 nvram_cmd
|= NVRAM_CMD_FIRST
;
7739 else if (j
== (pagesize
- 4))
7740 nvram_cmd
|= NVRAM_CMD_LAST
;
7742 if ((ret
= tg3_nvram_exec_cmd(tp
, nvram_cmd
)))
7749 nvram_cmd
= NVRAM_CMD_WRDI
| NVRAM_CMD_GO
| NVRAM_CMD_DONE
;
7750 tg3_nvram_exec_cmd(tp
, nvram_cmd
);
7757 /* offset and length are dword aligned */
7758 static int tg3_nvram_write_block_buffered(struct tg3
*tp
, u32 offset
, u32 len
,
7763 for (i
= 0; i
< len
; i
+= 4, offset
+= 4) {
7764 u32 data
, page_off
, phy_addr
, nvram_cmd
;
7766 memcpy(&data
, buf
+ i
, 4);
7767 tw32(NVRAM_WRDATA
, cpu_to_be32(data
));
7769 page_off
= offset
% tp
->nvram_pagesize
;
7771 if ((tp
->tg3_flags2
& TG3_FLG2_FLASH
) &&
7772 (tp
->nvram_jedecnum
== JEDEC_ATMEL
)) {
7774 phy_addr
= ((offset
/ tp
->nvram_pagesize
) <<
7775 ATMEL_AT45DB0X1B_PAGE_POS
) + page_off
;
7781 tw32(NVRAM_ADDR
, phy_addr
);
7783 nvram_cmd
= NVRAM_CMD_GO
| NVRAM_CMD_DONE
| NVRAM_CMD_WR
;
7785 if ((page_off
== 0) || (i
== 0))
7786 nvram_cmd
|= NVRAM_CMD_FIRST
;
7787 else if (page_off
== (tp
->nvram_pagesize
- 4))
7788 nvram_cmd
|= NVRAM_CMD_LAST
;
7791 nvram_cmd
|= NVRAM_CMD_LAST
;
7793 if ((tp
->nvram_jedecnum
== JEDEC_ST
) &&
7794 (nvram_cmd
& NVRAM_CMD_FIRST
)) {
7796 if ((ret
= tg3_nvram_exec_cmd(tp
,
7797 NVRAM_CMD_WREN
| NVRAM_CMD_GO
|
7802 if (!(tp
->tg3_flags2
& TG3_FLG2_FLASH
)) {
7803 /* We always do complete word writes to eeprom. */
7804 nvram_cmd
|= (NVRAM_CMD_FIRST
| NVRAM_CMD_LAST
);
7807 if ((ret
= tg3_nvram_exec_cmd(tp
, nvram_cmd
)))
7813 /* offset and length are dword aligned */
7814 static int tg3_nvram_write_block(struct tg3
*tp
, u32 offset
, u32 len
, u8
*buf
)
7818 if (tp
->tg3_flags2
& TG3_FLG2_SUN_570X
) {
7819 printk(KERN_ERR PFX
"Attempt to do nvram_write on Sun 570X\n");
7823 if (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
) {
7824 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
&
7825 ~GRC_LCLCTRL_GPIO_OUTPUT1
);
7829 if (!(tp
->tg3_flags
& TG3_FLAG_NVRAM
)) {
7830 ret
= tg3_nvram_write_block_using_eeprom(tp
, offset
, len
, buf
);
7837 tg3_enable_nvram_access(tp
);
7838 if ((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
7839 !(tp
->tg3_flags2
& TG3_FLG2_PROTECTED_NVRAM
))
7840 tw32(NVRAM_WRITE1
, 0x406);
7842 grc_mode
= tr32(GRC_MODE
);
7843 tw32(GRC_MODE
, grc_mode
| GRC_MODE_NVRAM_WR_ENABLE
);
7845 if ((tp
->tg3_flags
& TG3_FLAG_NVRAM_BUFFERED
) ||
7846 !(tp
->tg3_flags2
& TG3_FLG2_FLASH
)) {
7848 ret
= tg3_nvram_write_block_buffered(tp
, offset
, len
,
7852 ret
= tg3_nvram_write_block_unbuffered(tp
, offset
, len
,
7856 grc_mode
= tr32(GRC_MODE
);
7857 tw32(GRC_MODE
, grc_mode
& ~GRC_MODE_NVRAM_WR_ENABLE
);
7859 tg3_disable_nvram_access(tp
);
7860 tg3_nvram_unlock(tp
);
7863 if (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
) {
7864 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
);
7871 struct subsys_tbl_ent
{
7872 u16 subsys_vendor
, subsys_devid
;
7876 static struct subsys_tbl_ent subsys_id_to_phy_id
[] = {
7877 /* Broadcom boards. */
7878 { PCI_VENDOR_ID_BROADCOM
, 0x1644, PHY_ID_BCM5401
}, /* BCM95700A6 */
7879 { PCI_VENDOR_ID_BROADCOM
, 0x0001, PHY_ID_BCM5701
}, /* BCM95701A5 */
7880 { PCI_VENDOR_ID_BROADCOM
, 0x0002, PHY_ID_BCM8002
}, /* BCM95700T6 */
7881 { PCI_VENDOR_ID_BROADCOM
, 0x0003, 0 }, /* BCM95700A9 */
7882 { PCI_VENDOR_ID_BROADCOM
, 0x0005, PHY_ID_BCM5701
}, /* BCM95701T1 */
7883 { PCI_VENDOR_ID_BROADCOM
, 0x0006, PHY_ID_BCM5701
}, /* BCM95701T8 */
7884 { PCI_VENDOR_ID_BROADCOM
, 0x0007, 0 }, /* BCM95701A7 */
7885 { PCI_VENDOR_ID_BROADCOM
, 0x0008, PHY_ID_BCM5701
}, /* BCM95701A10 */
7886 { PCI_VENDOR_ID_BROADCOM
, 0x8008, PHY_ID_BCM5701
}, /* BCM95701A12 */
7887 { PCI_VENDOR_ID_BROADCOM
, 0x0009, PHY_ID_BCM5703
}, /* BCM95703Ax1 */
7888 { PCI_VENDOR_ID_BROADCOM
, 0x8009, PHY_ID_BCM5703
}, /* BCM95703Ax2 */
7891 { PCI_VENDOR_ID_3COM
, 0x1000, PHY_ID_BCM5401
}, /* 3C996T */
7892 { PCI_VENDOR_ID_3COM
, 0x1006, PHY_ID_BCM5701
}, /* 3C996BT */
7893 { PCI_VENDOR_ID_3COM
, 0x1004, 0 }, /* 3C996SX */
7894 { PCI_VENDOR_ID_3COM
, 0x1007, PHY_ID_BCM5701
}, /* 3C1000T */
7895 { PCI_VENDOR_ID_3COM
, 0x1008, PHY_ID_BCM5701
}, /* 3C940BR01 */
7898 { PCI_VENDOR_ID_DELL
, 0x00d1, PHY_ID_BCM5401
}, /* VIPER */
7899 { PCI_VENDOR_ID_DELL
, 0x0106, PHY_ID_BCM5401
}, /* JAGUAR */
7900 { PCI_VENDOR_ID_DELL
, 0x0109, PHY_ID_BCM5411
}, /* MERLOT */
7901 { PCI_VENDOR_ID_DELL
, 0x010a, PHY_ID_BCM5411
}, /* SLIM_MERLOT */
7903 /* Compaq boards. */
7904 { PCI_VENDOR_ID_COMPAQ
, 0x007c, PHY_ID_BCM5701
}, /* BANSHEE */
7905 { PCI_VENDOR_ID_COMPAQ
, 0x009a, PHY_ID_BCM5701
}, /* BANSHEE_2 */
7906 { PCI_VENDOR_ID_COMPAQ
, 0x007d, 0 }, /* CHANGELING */
7907 { PCI_VENDOR_ID_COMPAQ
, 0x0085, PHY_ID_BCM5701
}, /* NC7780 */
7908 { PCI_VENDOR_ID_COMPAQ
, 0x0099, PHY_ID_BCM5701
}, /* NC7780_2 */
7911 { PCI_VENDOR_ID_IBM
, 0x0281, 0 } /* IBM??? */
7914 static inline struct subsys_tbl_ent
*lookup_by_subsys(struct tg3
*tp
)
7918 for (i
= 0; i
< ARRAY_SIZE(subsys_id_to_phy_id
); i
++) {
7919 if ((subsys_id_to_phy_id
[i
].subsys_vendor
==
7920 tp
->pdev
->subsystem_vendor
) &&
7921 (subsys_id_to_phy_id
[i
].subsys_devid
==
7922 tp
->pdev
->subsystem_device
))
7923 return &subsys_id_to_phy_id
[i
];
7928 /* Since this function may be called in D3-hot power state during
7929 * tg3_init_one(), only config cycles are allowed.
7931 static void __devinit
tg3_get_eeprom_hw_cfg(struct tg3
*tp
)
7935 /* Make sure register accesses (indirect or otherwise)
7936 * will function correctly.
7938 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
7939 tp
->misc_host_ctrl
);
7941 tp
->phy_id
= PHY_ID_INVALID
;
7942 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
7944 tg3_read_mem(tp
, NIC_SRAM_DATA_SIG
, &val
);
7945 if (val
== NIC_SRAM_DATA_SIG_MAGIC
) {
7946 u32 nic_cfg
, led_cfg
;
7947 u32 nic_phy_id
, ver
, cfg2
= 0, eeprom_phy_id
;
7948 int eeprom_phy_serdes
= 0;
7950 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG
, &nic_cfg
);
7951 tp
->nic_sram_data_cfg
= nic_cfg
;
7953 tg3_read_mem(tp
, NIC_SRAM_DATA_VER
, &ver
);
7954 ver
>>= NIC_SRAM_DATA_VER_SHIFT
;
7955 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
) &&
7956 (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
) &&
7957 (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5703
) &&
7958 (ver
> 0) && (ver
< 0x100))
7959 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG_2
, &cfg2
);
7961 if ((nic_cfg
& NIC_SRAM_DATA_CFG_PHY_TYPE_MASK
) ==
7962 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER
)
7963 eeprom_phy_serdes
= 1;
7965 tg3_read_mem(tp
, NIC_SRAM_DATA_PHY_ID
, &nic_phy_id
);
7966 if (nic_phy_id
!= 0) {
7967 u32 id1
= nic_phy_id
& NIC_SRAM_DATA_PHY_ID1_MASK
;
7968 u32 id2
= nic_phy_id
& NIC_SRAM_DATA_PHY_ID2_MASK
;
7970 eeprom_phy_id
= (id1
>> 16) << 10;
7971 eeprom_phy_id
|= (id2
& 0xfc00) << 16;
7972 eeprom_phy_id
|= (id2
& 0x03ff) << 0;
7976 tp
->phy_id
= eeprom_phy_id
;
7977 if (eeprom_phy_serdes
)
7978 tp
->tg3_flags2
|= TG3_FLG2_PHY_SERDES
;
7980 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
7981 led_cfg
= cfg2
& (NIC_SRAM_DATA_CFG_LED_MODE_MASK
|
7982 SHASTA_EXT_LED_MODE_MASK
);
7984 led_cfg
= nic_cfg
& NIC_SRAM_DATA_CFG_LED_MODE_MASK
;
7988 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1
:
7989 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
7992 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2
:
7993 tp
->led_ctrl
= LED_CTRL_MODE_PHY_2
;
7996 case NIC_SRAM_DATA_CFG_LED_MODE_MAC
:
7997 tp
->led_ctrl
= LED_CTRL_MODE_MAC
;
8000 case SHASTA_EXT_LED_SHARED
:
8001 tp
->led_ctrl
= LED_CTRL_MODE_SHARED
;
8002 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
&&
8003 tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A1
)
8004 tp
->led_ctrl
|= (LED_CTRL_MODE_PHY_1
|
8005 LED_CTRL_MODE_PHY_2
);
8008 case SHASTA_EXT_LED_MAC
:
8009 tp
->led_ctrl
= LED_CTRL_MODE_SHASTA_MAC
;
8012 case SHASTA_EXT_LED_COMBO
:
8013 tp
->led_ctrl
= LED_CTRL_MODE_COMBO
;
8014 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
)
8015 tp
->led_ctrl
|= (LED_CTRL_MODE_PHY_1
|
8016 LED_CTRL_MODE_PHY_2
);
8021 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
8022 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) &&
8023 tp
->pdev
->subsystem_vendor
== PCI_VENDOR_ID_DELL
)
8024 tp
->led_ctrl
= LED_CTRL_MODE_PHY_2
;
8026 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
) &&
8027 (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
) &&
8028 (nic_cfg
& NIC_SRAM_DATA_CFG_EEPROM_WP
))
8029 tp
->tg3_flags
|= TG3_FLAG_EEPROM_WRITE_PROT
;
8031 if (nic_cfg
& NIC_SRAM_DATA_CFG_ASF_ENABLE
) {
8032 tp
->tg3_flags
|= TG3_FLAG_ENABLE_ASF
;
8033 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
8034 tp
->tg3_flags2
|= TG3_FLG2_ASF_NEW_HANDSHAKE
;
8036 if (nic_cfg
& NIC_SRAM_DATA_CFG_FIBER_WOL
)
8037 tp
->tg3_flags
|= TG3_FLAG_SERDES_WOL_CAP
;
8039 if (cfg2
& (1 << 17))
8040 tp
->tg3_flags2
|= TG3_FLG2_CAPACITIVE_COUPLING
;
8042 /* serdes signal pre-emphasis in register 0x590 set by */
8043 /* bootcode if bit 18 is set */
8044 if (cfg2
& (1 << 18))
8045 tp
->tg3_flags2
|= TG3_FLG2_SERDES_PREEMPHASIS
;
8049 static int __devinit
tg3_phy_probe(struct tg3
*tp
)
8051 u32 hw_phy_id_1
, hw_phy_id_2
;
8052 u32 hw_phy_id
, hw_phy_id_masked
;
8055 /* Reading the PHY ID register can conflict with ASF
8056 * firwmare access to the PHY hardware.
8059 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) {
8060 hw_phy_id
= hw_phy_id_masked
= PHY_ID_INVALID
;
8062 /* Now read the physical PHY_ID from the chip and verify
8063 * that it is sane. If it doesn't look good, we fall back
8064 * to either the hard-coded table based PHY_ID and failing
8065 * that the value found in the eeprom area.
8067 err
|= tg3_readphy(tp
, MII_PHYSID1
, &hw_phy_id_1
);
8068 err
|= tg3_readphy(tp
, MII_PHYSID2
, &hw_phy_id_2
);
8070 hw_phy_id
= (hw_phy_id_1
& 0xffff) << 10;
8071 hw_phy_id
|= (hw_phy_id_2
& 0xfc00) << 16;
8072 hw_phy_id
|= (hw_phy_id_2
& 0x03ff) << 0;
8074 hw_phy_id_masked
= hw_phy_id
& PHY_ID_MASK
;
8077 if (!err
&& KNOWN_PHY_ID(hw_phy_id_masked
)) {
8078 tp
->phy_id
= hw_phy_id
;
8079 if (hw_phy_id_masked
== PHY_ID_BCM8002
)
8080 tp
->tg3_flags2
|= TG3_FLG2_PHY_SERDES
;
8082 if (tp
->phy_id
!= PHY_ID_INVALID
) {
8083 /* Do nothing, phy ID already set up in
8084 * tg3_get_eeprom_hw_cfg().
8087 struct subsys_tbl_ent
*p
;
8089 /* No eeprom signature? Try the hardcoded
8090 * subsys device table.
8092 p
= lookup_by_subsys(tp
);
8096 tp
->phy_id
= p
->phy_id
;
8098 tp
->phy_id
== PHY_ID_BCM8002
)
8099 tp
->tg3_flags2
|= TG3_FLG2_PHY_SERDES
;
8103 if (!(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) &&
8104 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)) {
8105 u32 bmsr
, adv_reg
, tg3_ctrl
;
8107 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
8108 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
8109 (bmsr
& BMSR_LSTATUS
))
8110 goto skip_phy_reset
;
8112 err
= tg3_phy_reset(tp
);
8116 adv_reg
= (ADVERTISE_10HALF
| ADVERTISE_10FULL
|
8117 ADVERTISE_100HALF
| ADVERTISE_100FULL
|
8118 ADVERTISE_CSMA
| ADVERTISE_PAUSE_CAP
);
8120 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)) {
8121 tg3_ctrl
= (MII_TG3_CTRL_ADV_1000_HALF
|
8122 MII_TG3_CTRL_ADV_1000_FULL
);
8123 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
8124 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
)
8125 tg3_ctrl
|= (MII_TG3_CTRL_AS_MASTER
|
8126 MII_TG3_CTRL_ENABLE_AS_MASTER
);
8129 if (!tg3_copper_is_advertising_all(tp
)) {
8130 tg3_writephy(tp
, MII_ADVERTISE
, adv_reg
);
8132 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
))
8133 tg3_writephy(tp
, MII_TG3_CTRL
, tg3_ctrl
);
8135 tg3_writephy(tp
, MII_BMCR
,
8136 BMCR_ANENABLE
| BMCR_ANRESTART
);
8138 tg3_phy_set_wirespeed(tp
);
8140 tg3_writephy(tp
, MII_ADVERTISE
, adv_reg
);
8141 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
))
8142 tg3_writephy(tp
, MII_TG3_CTRL
, tg3_ctrl
);
8146 if ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5401
) {
8147 err
= tg3_init_5401phy_dsp(tp
);
8152 if (!err
&& ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5401
)) {
8153 err
= tg3_init_5401phy_dsp(tp
);
8156 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)
8157 tp
->link_config
.advertising
=
8158 (ADVERTISED_1000baseT_Half
|
8159 ADVERTISED_1000baseT_Full
|
8160 ADVERTISED_Autoneg
|
8162 if (tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)
8163 tp
->link_config
.advertising
&=
8164 ~(ADVERTISED_1000baseT_Half
|
8165 ADVERTISED_1000baseT_Full
);
8170 static void __devinit
tg3_read_partno(struct tg3
*tp
)
8172 unsigned char vpd_data
[256];
8175 if (tp
->tg3_flags2
& TG3_FLG2_SUN_570X
) {
8176 /* Sun decided not to put the necessary bits in the
8177 * NVRAM of their onboard tg3 parts :(
8179 strcpy(tp
->board_part_number
, "Sun 570X");
8183 for (i
= 0; i
< 256; i
+= 4) {
8186 if (tg3_nvram_read(tp
, 0x100 + i
, &tmp
))
8189 vpd_data
[i
+ 0] = ((tmp
>> 0) & 0xff);
8190 vpd_data
[i
+ 1] = ((tmp
>> 8) & 0xff);
8191 vpd_data
[i
+ 2] = ((tmp
>> 16) & 0xff);
8192 vpd_data
[i
+ 3] = ((tmp
>> 24) & 0xff);
8195 /* Now parse and find the part number. */
8196 for (i
= 0; i
< 256; ) {
8197 unsigned char val
= vpd_data
[i
];
8200 if (val
== 0x82 || val
== 0x91) {
8203 (vpd_data
[i
+ 2] << 8)));
8210 block_end
= (i
+ 3 +
8212 (vpd_data
[i
+ 2] << 8)));
8214 while (i
< block_end
) {
8215 if (vpd_data
[i
+ 0] == 'P' &&
8216 vpd_data
[i
+ 1] == 'N') {
8217 int partno_len
= vpd_data
[i
+ 2];
8219 if (partno_len
> 24)
8222 memcpy(tp
->board_part_number
,
8231 /* Part number not found. */
8236 strcpy(tp
->board_part_number
, "none");
8239 #ifdef CONFIG_SPARC64
8240 static int __devinit
tg3_is_sun_570X(struct tg3
*tp
)
8242 struct pci_dev
*pdev
= tp
->pdev
;
8243 struct pcidev_cookie
*pcp
= pdev
->sysdata
;
8246 int node
= pcp
->prom_node
;
8250 err
= prom_getproperty(node
, "subsystem-vendor-id",
8251 (char *) &venid
, sizeof(venid
));
8252 if (err
== 0 || err
== -1)
8254 if (venid
== PCI_VENDOR_ID_SUN
)
8261 static int __devinit
tg3_get_invariants(struct tg3
*tp
)
8263 static struct pci_device_id write_reorder_chipsets
[] = {
8264 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
,
8265 PCI_DEVICE_ID_INTEL_82801AA_8
) },
8266 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
,
8267 PCI_DEVICE_ID_INTEL_82801AB_8
) },
8268 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
,
8269 PCI_DEVICE_ID_INTEL_82801BA_11
) },
8270 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
,
8271 PCI_DEVICE_ID_INTEL_82801BA_6
) },
8272 { PCI_DEVICE(PCI_VENDOR_ID_AMD
,
8273 PCI_DEVICE_ID_AMD_FE_GATE_700C
) },
8277 u32 cacheline_sz_reg
;
8278 u32 pci_state_reg
, grc_misc_cfg
;
8283 #ifdef CONFIG_SPARC64
8284 if (tg3_is_sun_570X(tp
))
8285 tp
->tg3_flags2
|= TG3_FLG2_SUN_570X
;
8288 /* If we have an AMD 762 or Intel ICH/ICH0/ICH2 chipset, write
8289 * reordering to the mailbox registers done by the host
8290 * controller can cause major troubles. We read back from
8291 * every mailbox register write to force the writes to be
8292 * posted to the chip in order.
8294 if (pci_dev_present(write_reorder_chipsets
))
8295 tp
->tg3_flags
|= TG3_FLAG_MBOX_WRITE_REORDER
;
8297 /* Force memory write invalidate off. If we leave it on,
8298 * then on 5700_BX chips we have to enable a workaround.
8299 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
8300 * to match the cacheline size. The Broadcom driver have this
8301 * workaround but turns MWI off all the times so never uses
8302 * it. This seems to suggest that the workaround is insufficient.
8304 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
8305 pci_cmd
&= ~PCI_COMMAND_INVALIDATE
;
8306 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
8308 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
8309 * has the register indirect write enable bit set before
8310 * we try to access any of the MMIO registers. It is also
8311 * critical that the PCI-X hw workaround situation is decided
8312 * before that as well.
8314 pci_read_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
8317 tp
->pci_chip_rev_id
= (misc_ctrl_reg
>>
8318 MISC_HOST_CTRL_CHIPREV_SHIFT
);
8320 /* Wrong chip ID in 5752 A0. This code can be removed later
8321 * as A0 is not in production.
8323 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5752_A0_HW
)
8324 tp
->pci_chip_rev_id
= CHIPREV_ID_5752_A0
;
8326 /* Initialize misc host control in PCI block. */
8327 tp
->misc_host_ctrl
|= (misc_ctrl_reg
&
8328 MISC_HOST_CTRL_CHIPREV
);
8329 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
8330 tp
->misc_host_ctrl
);
8332 pci_read_config_dword(tp
->pdev
, TG3PCI_CACHELINESZ
,
8335 tp
->pci_cacheline_sz
= (cacheline_sz_reg
>> 0) & 0xff;
8336 tp
->pci_lat_timer
= (cacheline_sz_reg
>> 8) & 0xff;
8337 tp
->pci_hdr_type
= (cacheline_sz_reg
>> 16) & 0xff;
8338 tp
->pci_bist
= (cacheline_sz_reg
>> 24) & 0xff;
8340 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
||
8341 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
)
8342 tp
->tg3_flags2
|= TG3_FLG2_5750_PLUS
;
8344 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) ||
8345 (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
))
8346 tp
->tg3_flags2
|= TG3_FLG2_5705_PLUS
;
8348 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
8349 tp
->tg3_flags2
|= TG3_FLG2_HW_TSO
;
8351 if (pci_find_capability(tp
->pdev
, PCI_CAP_ID_EXP
) != 0)
8352 tp
->tg3_flags2
|= TG3_FLG2_PCI_EXPRESS
;
8354 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
&&
8355 tp
->pci_lat_timer
< 64) {
8356 tp
->pci_lat_timer
= 64;
8358 cacheline_sz_reg
= ((tp
->pci_cacheline_sz
& 0xff) << 0);
8359 cacheline_sz_reg
|= ((tp
->pci_lat_timer
& 0xff) << 8);
8360 cacheline_sz_reg
|= ((tp
->pci_hdr_type
& 0xff) << 16);
8361 cacheline_sz_reg
|= ((tp
->pci_bist
& 0xff) << 24);
8363 pci_write_config_dword(tp
->pdev
, TG3PCI_CACHELINESZ
,
8367 pci_read_config_dword(tp
->pdev
, TG3PCI_PCISTATE
,
8370 if ((pci_state_reg
& PCISTATE_CONV_PCI_MODE
) == 0) {
8371 tp
->tg3_flags
|= TG3_FLAG_PCIX_MODE
;
8373 /* If this is a 5700 BX chipset, and we are in PCI-X
8374 * mode, enable register write workaround.
8376 * The workaround is to use indirect register accesses
8377 * for all chip writes not to mailbox registers.
8379 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5700_BX
) {
8383 tp
->tg3_flags
|= TG3_FLAG_PCIX_TARGET_HWBUG
;
8385 /* The chip can have it's power management PCI config
8386 * space registers clobbered due to this bug.
8387 * So explicitly force the chip into D0 here.
8389 pci_read_config_dword(tp
->pdev
, TG3PCI_PM_CTRL_STAT
,
8391 pm_reg
&= ~PCI_PM_CTRL_STATE_MASK
;
8392 pm_reg
|= PCI_PM_CTRL_PME_ENABLE
| 0 /* D0 */;
8393 pci_write_config_dword(tp
->pdev
, TG3PCI_PM_CTRL_STAT
,
8396 /* Also, force SERR#/PERR# in PCI command. */
8397 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
8398 pci_cmd
|= PCI_COMMAND_PARITY
| PCI_COMMAND_SERR
;
8399 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
8403 /* Back to back register writes can cause problems on this chip,
8404 * the workaround is to read back all reg writes except those to
8405 * mailbox regs. See tg3_write_indirect_reg32().
8407 * PCI Express 5750_A0 rev chips need this workaround too.
8409 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
||
8410 ((tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) &&
8411 tp
->pci_chip_rev_id
== CHIPREV_ID_5750_A0
))
8412 tp
->tg3_flags
|= TG3_FLAG_5701_REG_WRITE_BUG
;
8414 if ((pci_state_reg
& PCISTATE_BUS_SPEED_HIGH
) != 0)
8415 tp
->tg3_flags
|= TG3_FLAG_PCI_HIGH_SPEED
;
8416 if ((pci_state_reg
& PCISTATE_BUS_32BIT
) != 0)
8417 tp
->tg3_flags
|= TG3_FLAG_PCI_32BIT
;
8419 /* Chip-specific fixup from Broadcom driver */
8420 if ((tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
) &&
8421 (!(pci_state_reg
& PCISTATE_RETRY_SAME_DMA
))) {
8422 pci_state_reg
|= PCISTATE_RETRY_SAME_DMA
;
8423 pci_write_config_dword(tp
->pdev
, TG3PCI_PCISTATE
, pci_state_reg
);
8426 /* Get eeprom hw config before calling tg3_set_power_state().
8427 * In particular, the TG3_FLAG_EEPROM_WRITE_PROT flag must be
8428 * determined before calling tg3_set_power_state() so that
8429 * we know whether or not to switch out of Vaux power.
8430 * When the flag is set, it means that GPIO1 is used for eeprom
8431 * write protect and also implies that it is a LOM where GPIOs
8432 * are not used to switch power.
8434 tg3_get_eeprom_hw_cfg(tp
);
8436 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
8437 * GPIO1 driven high will bring 5700's external PHY out of reset.
8438 * It is also used as eeprom write protect on LOMs.
8440 tp
->grc_local_ctrl
= GRC_LCLCTRL_INT_ON_ATTN
| GRC_LCLCTRL_AUTO_SEEPROM
;
8441 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) ||
8442 (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
))
8443 tp
->grc_local_ctrl
|= (GRC_LCLCTRL_GPIO_OE1
|
8444 GRC_LCLCTRL_GPIO_OUTPUT1
);
8445 /* Unused GPIO3 must be driven as output on 5752 because there
8446 * are no pull-up resistors on unused GPIO pins.
8448 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
)
8449 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE3
;
8451 /* Force the chip into D0. */
8452 err
= tg3_set_power_state(tp
, 0);
8454 printk(KERN_ERR PFX
"(%s) transition to D0 failed\n",
8455 pci_name(tp
->pdev
));
8459 /* 5700 B0 chips do not support checksumming correctly due
8462 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5700_B0
)
8463 tp
->tg3_flags
|= TG3_FLAG_BROKEN_CHECKSUMS
;
8465 /* Pseudo-header checksum is done by hardware logic and not
8466 * the offload processers, so make the chip do the pseudo-
8467 * header checksums on receive. For transmit it is more
8468 * convenient to do the pseudo-header checksum in software
8469 * as Linux does that on transmit for us in all cases.
8471 tp
->tg3_flags
|= TG3_FLAG_NO_TX_PSEUDO_CSUM
;
8472 tp
->tg3_flags
&= ~TG3_FLAG_NO_RX_PSEUDO_CSUM
;
8474 /* Derive initial jumbo mode from MTU assigned in
8475 * ether_setup() via the alloc_etherdev() call
8477 if (tp
->dev
->mtu
> ETH_DATA_LEN
)
8478 tp
->tg3_flags
|= TG3_FLAG_JUMBO_ENABLE
;
8480 /* Determine WakeOnLan speed to use. */
8481 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
8482 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
8483 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
||
8484 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B2
) {
8485 tp
->tg3_flags
&= ~(TG3_FLAG_WOL_SPEED_100MB
);
8487 tp
->tg3_flags
|= TG3_FLAG_WOL_SPEED_100MB
;
8490 /* A few boards don't want Ethernet@WireSpeed phy feature */
8491 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) ||
8492 ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) &&
8493 (tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A0
) &&
8494 (tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A1
)))
8495 tp
->tg3_flags2
|= TG3_FLG2_NO_ETH_WIRE_SPEED
;
8497 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5703_AX
||
8498 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5704_AX
)
8499 tp
->tg3_flags2
|= TG3_FLG2_PHY_ADC_BUG
;
8500 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
)
8501 tp
->tg3_flags2
|= TG3_FLG2_PHY_5704_A0_BUG
;
8503 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
8504 tp
->tg3_flags2
|= TG3_FLG2_PHY_BER_BUG
;
8506 tp
->coalesce_mode
= 0;
8507 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5700_AX
&&
8508 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5700_BX
)
8509 tp
->coalesce_mode
|= HOSTCC_MODE_32BYTE
;
8511 /* Initialize MAC MI mode, polling disabled. */
8512 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
8515 /* Initialize data/descriptor byte/word swapping. */
8516 val
= tr32(GRC_MODE
);
8517 val
&= GRC_MODE_HOST_STACKUP
;
8518 tw32(GRC_MODE
, val
| tp
->grc_mode
);
8520 tg3_switch_clocks(tp
);
8522 /* Clear this out for sanity. */
8523 tw32(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
8525 pci_read_config_dword(tp
->pdev
, TG3PCI_PCISTATE
,
8527 if ((pci_state_reg
& PCISTATE_CONV_PCI_MODE
) == 0 &&
8528 (tp
->tg3_flags
& TG3_FLAG_PCIX_TARGET_HWBUG
) == 0) {
8529 u32 chiprevid
= GET_CHIP_REV_ID(tp
->misc_host_ctrl
);
8531 if (chiprevid
== CHIPREV_ID_5701_A0
||
8532 chiprevid
== CHIPREV_ID_5701_B0
||
8533 chiprevid
== CHIPREV_ID_5701_B2
||
8534 chiprevid
== CHIPREV_ID_5701_B5
) {
8535 void __iomem
*sram_base
;
8537 /* Write some dummy words into the SRAM status block
8538 * area, see if it reads back correctly. If the return
8539 * value is bad, force enable the PCIX workaround.
8541 sram_base
= tp
->regs
+ NIC_SRAM_WIN_BASE
+ NIC_SRAM_STATS_BLK
;
8543 writel(0x00000000, sram_base
);
8544 writel(0x00000000, sram_base
+ 4);
8545 writel(0xffffffff, sram_base
+ 4);
8546 if (readl(sram_base
) != 0x00000000)
8547 tp
->tg3_flags
|= TG3_FLAG_PCIX_TARGET_HWBUG
;
8554 grc_misc_cfg
= tr32(GRC_MISC_CFG
);
8555 grc_misc_cfg
&= GRC_MISC_CFG_BOARD_ID_MASK
;
8557 /* Broadcom's driver says that CIOBE multisplit has a bug */
8559 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
&&
8560 grc_misc_cfg
== GRC_MISC_CFG_BOARD_ID_5704CIOBE
) {
8561 tp
->tg3_flags
|= TG3_FLAG_SPLIT_MODE
;
8562 tp
->split_mode_max_reqs
= SPLIT_MODE_5704_MAX_REQ
;
8565 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
8566 (grc_misc_cfg
== GRC_MISC_CFG_BOARD_ID_5788
||
8567 grc_misc_cfg
== GRC_MISC_CFG_BOARD_ID_5788M
))
8568 tp
->tg3_flags2
|= TG3_FLG2_IS_5788
;
8570 if (!(tp
->tg3_flags2
& TG3_FLG2_IS_5788
) &&
8571 (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
))
8572 tp
->tg3_flags
|= TG3_FLAG_TAGGED_STATUS
;
8573 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) {
8574 tp
->coalesce_mode
|= (HOSTCC_MODE_CLRTICK_RXBD
|
8575 HOSTCC_MODE_CLRTICK_TXBD
);
8577 tp
->misc_host_ctrl
|= MISC_HOST_CTRL_TAGGED_STATUS
;
8578 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
8579 tp
->misc_host_ctrl
);
8582 /* these are limited to 10/100 only */
8583 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
&&
8584 (grc_misc_cfg
== 0x8000 || grc_misc_cfg
== 0x4000)) ||
8585 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
8586 tp
->pdev
->vendor
== PCI_VENDOR_ID_BROADCOM
&&
8587 (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5901
||
8588 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5901_2
||
8589 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5705F
)) ||
8590 (tp
->pdev
->vendor
== PCI_VENDOR_ID_BROADCOM
&&
8591 (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5751F
||
8592 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5753F
)))
8593 tp
->tg3_flags
|= TG3_FLAG_10_100_ONLY
;
8595 err
= tg3_phy_probe(tp
);
8597 printk(KERN_ERR PFX
"(%s) phy probe failed, err %d\n",
8598 pci_name(tp
->pdev
), err
);
8599 /* ... but do not return immediately ... */
8602 tg3_read_partno(tp
);
8604 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
8605 tp
->tg3_flags
&= ~TG3_FLAG_USE_MI_INTERRUPT
;
8607 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
)
8608 tp
->tg3_flags
|= TG3_FLAG_USE_MI_INTERRUPT
;
8610 tp
->tg3_flags
&= ~TG3_FLAG_USE_MI_INTERRUPT
;
8613 /* 5700 {AX,BX} chips have a broken status block link
8614 * change bit implementation, so we must use the
8615 * status register in those cases.
8617 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
)
8618 tp
->tg3_flags
|= TG3_FLAG_USE_LINKCHG_REG
;
8620 tp
->tg3_flags
&= ~TG3_FLAG_USE_LINKCHG_REG
;
8622 /* The led_ctrl is set during tg3_phy_probe, here we might
8623 * have to force the link status polling mechanism based
8624 * upon subsystem IDs.
8626 if (tp
->pdev
->subsystem_vendor
== PCI_VENDOR_ID_DELL
&&
8627 !(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)) {
8628 tp
->tg3_flags
|= (TG3_FLAG_USE_MI_INTERRUPT
|
8629 TG3_FLAG_USE_LINKCHG_REG
);
8632 /* For all SERDES we poll the MAC status register. */
8633 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)
8634 tp
->tg3_flags
|= TG3_FLAG_POLL_SERDES
;
8636 tp
->tg3_flags
&= ~TG3_FLAG_POLL_SERDES
;
8638 /* 5700 BX chips need to have their TX producer index mailboxes
8639 * written twice to workaround a bug.
8641 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5700_BX
)
8642 tp
->tg3_flags
|= TG3_FLAG_TXD_MBOX_HWBUG
;
8644 tp
->tg3_flags
&= ~TG3_FLAG_TXD_MBOX_HWBUG
;
8646 /* It seems all chips can get confused if TX buffers
8647 * straddle the 4GB address boundary in some cases.
8649 tp
->dev
->hard_start_xmit
= tg3_start_xmit
;
8652 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
&&
8653 (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) != 0)
8656 /* By default, disable wake-on-lan. User can change this
8657 * using ETHTOOL_SWOL.
8659 tp
->tg3_flags
&= ~TG3_FLAG_WOL_ENABLE
;
8664 #ifdef CONFIG_SPARC64
8665 static int __devinit
tg3_get_macaddr_sparc(struct tg3
*tp
)
8667 struct net_device
*dev
= tp
->dev
;
8668 struct pci_dev
*pdev
= tp
->pdev
;
8669 struct pcidev_cookie
*pcp
= pdev
->sysdata
;
8672 int node
= pcp
->prom_node
;
8674 if (prom_getproplen(node
, "local-mac-address") == 6) {
8675 prom_getproperty(node
, "local-mac-address",
8683 static int __devinit
tg3_get_default_macaddr_sparc(struct tg3
*tp
)
8685 struct net_device
*dev
= tp
->dev
;
8687 memcpy(dev
->dev_addr
, idprom
->id_ethaddr
, 6);
8692 static int __devinit
tg3_get_device_address(struct tg3
*tp
)
8694 struct net_device
*dev
= tp
->dev
;
8695 u32 hi
, lo
, mac_offset
;
8697 #ifdef CONFIG_SPARC64
8698 if (!tg3_get_macaddr_sparc(tp
))
8703 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
&&
8704 !(tp
->tg3_flags
& TG3_FLG2_SUN_570X
)) {
8705 if (tr32(TG3PCI_DUAL_MAC_CTRL
) & DUAL_MAC_CTRL_ID
)
8707 if (tg3_nvram_lock(tp
))
8708 tw32_f(NVRAM_CMD
, NVRAM_CMD_RESET
);
8710 tg3_nvram_unlock(tp
);
8713 /* First try to get it from MAC address mailbox. */
8714 tg3_read_mem(tp
, NIC_SRAM_MAC_ADDR_HIGH_MBOX
, &hi
);
8715 if ((hi
>> 16) == 0x484b) {
8716 dev
->dev_addr
[0] = (hi
>> 8) & 0xff;
8717 dev
->dev_addr
[1] = (hi
>> 0) & 0xff;
8719 tg3_read_mem(tp
, NIC_SRAM_MAC_ADDR_LOW_MBOX
, &lo
);
8720 dev
->dev_addr
[2] = (lo
>> 24) & 0xff;
8721 dev
->dev_addr
[3] = (lo
>> 16) & 0xff;
8722 dev
->dev_addr
[4] = (lo
>> 8) & 0xff;
8723 dev
->dev_addr
[5] = (lo
>> 0) & 0xff;
8725 /* Next, try NVRAM. */
8726 else if (!(tp
->tg3_flags
& TG3_FLG2_SUN_570X
) &&
8727 !tg3_nvram_read(tp
, mac_offset
+ 0, &hi
) &&
8728 !tg3_nvram_read(tp
, mac_offset
+ 4, &lo
)) {
8729 dev
->dev_addr
[0] = ((hi
>> 16) & 0xff);
8730 dev
->dev_addr
[1] = ((hi
>> 24) & 0xff);
8731 dev
->dev_addr
[2] = ((lo
>> 0) & 0xff);
8732 dev
->dev_addr
[3] = ((lo
>> 8) & 0xff);
8733 dev
->dev_addr
[4] = ((lo
>> 16) & 0xff);
8734 dev
->dev_addr
[5] = ((lo
>> 24) & 0xff);
8736 /* Finally just fetch it out of the MAC control regs. */
8738 hi
= tr32(MAC_ADDR_0_HIGH
);
8739 lo
= tr32(MAC_ADDR_0_LOW
);
8741 dev
->dev_addr
[5] = lo
& 0xff;
8742 dev
->dev_addr
[4] = (lo
>> 8) & 0xff;
8743 dev
->dev_addr
[3] = (lo
>> 16) & 0xff;
8744 dev
->dev_addr
[2] = (lo
>> 24) & 0xff;
8745 dev
->dev_addr
[1] = hi
& 0xff;
8746 dev
->dev_addr
[0] = (hi
>> 8) & 0xff;
8749 if (!is_valid_ether_addr(&dev
->dev_addr
[0])) {
8750 #ifdef CONFIG_SPARC64
8751 if (!tg3_get_default_macaddr_sparc(tp
))
8759 static int __devinit
tg3_do_test_dma(struct tg3
*tp
, u32
*buf
, dma_addr_t buf_dma
, int size
, int to_device
)
8761 struct tg3_internal_buffer_desc test_desc
;
8765 sram_dma_descs
= NIC_SRAM_DMA_DESC_POOL_BASE
;
8767 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ
, 0);
8768 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ
, 0);
8769 tw32(RDMAC_STATUS
, 0);
8770 tw32(WDMAC_STATUS
, 0);
8772 tw32(BUFMGR_MODE
, 0);
8775 test_desc
.addr_hi
= ((u64
) buf_dma
) >> 32;
8776 test_desc
.addr_lo
= buf_dma
& 0xffffffff;
8777 test_desc
.nic_mbuf
= 0x00002100;
8778 test_desc
.len
= size
;
8781 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
8782 * the *second* time the tg3 driver was getting loaded after an
8785 * Broadcom tells me:
8786 * ...the DMA engine is connected to the GRC block and a DMA
8787 * reset may affect the GRC block in some unpredictable way...
8788 * The behavior of resets to individual blocks has not been tested.
8790 * Broadcom noted the GRC reset will also reset all sub-components.
8793 test_desc
.cqid_sqid
= (13 << 8) | 2;
8795 tw32_f(RDMAC_MODE
, RDMAC_MODE_ENABLE
);
8798 test_desc
.cqid_sqid
= (16 << 8) | 7;
8800 tw32_f(WDMAC_MODE
, WDMAC_MODE_ENABLE
);
8803 test_desc
.flags
= 0x00000005;
8805 for (i
= 0; i
< (sizeof(test_desc
) / sizeof(u32
)); i
++) {
8808 val
= *(((u32
*)&test_desc
) + i
);
8809 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
,
8810 sram_dma_descs
+ (i
* sizeof(u32
)));
8811 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_DATA
, val
);
8813 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, 0);
8816 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ
, sram_dma_descs
);
8818 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ
, sram_dma_descs
);
8822 for (i
= 0; i
< 40; i
++) {
8826 val
= tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ
);
8828 val
= tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ
);
8829 if ((val
& 0xffff) == sram_dma_descs
) {
8840 #define TEST_BUFFER_SIZE 0x400
8842 static int __devinit
tg3_test_dma(struct tg3
*tp
)
8848 buf
= pci_alloc_consistent(tp
->pdev
, TEST_BUFFER_SIZE
, &buf_dma
);
8854 tp
->dma_rwctrl
= ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT
) |
8855 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT
));
8861 pci_read_config_byte(tp
->pdev
, PCI_CACHE_LINE_SIZE
, &byte
);
8864 cacheline_size
= 1024;
8866 cacheline_size
= (int) byte
* 4;
8868 switch (cacheline_size
) {
8873 if ((tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) &&
8874 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)) {
8876 DMA_RWCTRL_WRITE_BNDRY_384_PCIX
;
8878 } else if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
8880 ~(DMA_RWCTRL_PCI_WRITE_CMD
);
8882 DMA_RWCTRL_WRITE_BNDRY_128_PCIE
;
8887 if (!(tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) &&
8888 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
))
8890 DMA_RWCTRL_WRITE_BNDRY_256
;
8891 else if (!(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
))
8893 DMA_RWCTRL_WRITE_BNDRY_256_PCIX
;
8898 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
8899 /* DMA read watermark not used on PCIE */
8900 tp
->dma_rwctrl
|= 0x00180000;
8901 } else if (!(tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
)) {
8902 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
||
8903 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
)
8904 tp
->dma_rwctrl
|= 0x003f0000;
8906 tp
->dma_rwctrl
|= 0x003f000f;
8908 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
8909 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
8910 u32 ccval
= (tr32(TG3PCI_CLOCK_CTRL
) & 0x1f);
8912 if (ccval
== 0x6 || ccval
== 0x7)
8913 tp
->dma_rwctrl
|= DMA_RWCTRL_ONE_DMA
;
8915 /* Set bit 23 to renable PCIX hw bug fix */
8916 tp
->dma_rwctrl
|= 0x009f0000;
8918 tp
->dma_rwctrl
|= 0x001b000f;
8922 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
8923 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
)
8924 tp
->dma_rwctrl
&= 0xfffffff0;
8926 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
8927 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
8928 /* Remove this if it causes problems for some boards. */
8929 tp
->dma_rwctrl
|= DMA_RWCTRL_USE_MEM_READ_MULT
;
8931 /* On 5700/5701 chips, we need to set this bit.
8932 * Otherwise the chip will issue cacheline transactions
8933 * to streamable DMA memory with not all the byte
8934 * enables turned on. This is an error on several
8935 * RISC PCI controllers, in particular sparc64.
8937 * On 5703/5704 chips, this bit has been reassigned
8938 * a different meaning. In particular, it is used
8939 * on those chips to enable a PCI-X workaround.
8941 tp
->dma_rwctrl
|= DMA_RWCTRL_ASSERT_ALL_BE
;
8944 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
8947 /* Unneeded, already done by tg3_get_invariants. */
8948 tg3_switch_clocks(tp
);
8952 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
8953 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
)
8959 for (i
= 0; i
< TEST_BUFFER_SIZE
/ sizeof(u32
); i
++)
8962 /* Send the buffer to the chip. */
8963 ret
= tg3_do_test_dma(tp
, buf
, buf_dma
, TEST_BUFFER_SIZE
, 1);
8965 printk(KERN_ERR
"tg3_test_dma() Write the buffer failed %d\n", ret
);
8970 /* validate data reached card RAM correctly. */
8971 for (i
= 0; i
< TEST_BUFFER_SIZE
/ sizeof(u32
); i
++) {
8973 tg3_read_mem(tp
, 0x2100 + (i
*4), &val
);
8974 if (le32_to_cpu(val
) != p
[i
]) {
8975 printk(KERN_ERR
" tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val
, i
);
8976 /* ret = -ENODEV here? */
8981 /* Now read it back. */
8982 ret
= tg3_do_test_dma(tp
, buf
, buf_dma
, TEST_BUFFER_SIZE
, 0);
8984 printk(KERN_ERR
"tg3_test_dma() Read the buffer failed %d\n", ret
);
8990 for (i
= 0; i
< TEST_BUFFER_SIZE
/ sizeof(u32
); i
++) {
8994 if ((tp
->dma_rwctrl
& DMA_RWCTRL_WRITE_BNDRY_MASK
) ==
8995 DMA_RWCTRL_WRITE_BNDRY_DISAB
) {
8996 tp
->dma_rwctrl
|= DMA_RWCTRL_WRITE_BNDRY_16
;
8997 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
9000 printk(KERN_ERR
"tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p
[i
], i
);
9006 if (i
== (TEST_BUFFER_SIZE
/ sizeof(u32
))) {
9014 pci_free_consistent(tp
->pdev
, TEST_BUFFER_SIZE
, buf
, buf_dma
);
9019 static void __devinit
tg3_init_link_config(struct tg3
*tp
)
9021 tp
->link_config
.advertising
=
9022 (ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
9023 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
|
9024 ADVERTISED_1000baseT_Half
| ADVERTISED_1000baseT_Full
|
9025 ADVERTISED_Autoneg
| ADVERTISED_MII
);
9026 tp
->link_config
.speed
= SPEED_INVALID
;
9027 tp
->link_config
.duplex
= DUPLEX_INVALID
;
9028 tp
->link_config
.autoneg
= AUTONEG_ENABLE
;
9029 netif_carrier_off(tp
->dev
);
9030 tp
->link_config
.active_speed
= SPEED_INVALID
;
9031 tp
->link_config
.active_duplex
= DUPLEX_INVALID
;
9032 tp
->link_config
.phy_is_low_power
= 0;
9033 tp
->link_config
.orig_speed
= SPEED_INVALID
;
9034 tp
->link_config
.orig_duplex
= DUPLEX_INVALID
;
9035 tp
->link_config
.orig_autoneg
= AUTONEG_INVALID
;
9038 static void __devinit
tg3_init_bufmgr_config(struct tg3
*tp
)
9040 tp
->bufmgr_config
.mbuf_read_dma_low_water
=
9041 DEFAULT_MB_RDMA_LOW_WATER
;
9042 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
9043 DEFAULT_MB_MACRX_LOW_WATER
;
9044 tp
->bufmgr_config
.mbuf_high_water
=
9045 DEFAULT_MB_HIGH_WATER
;
9047 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
=
9048 DEFAULT_MB_RDMA_LOW_WATER_JUMBO
;
9049 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
=
9050 DEFAULT_MB_MACRX_LOW_WATER_JUMBO
;
9051 tp
->bufmgr_config
.mbuf_high_water_jumbo
=
9052 DEFAULT_MB_HIGH_WATER_JUMBO
;
9054 tp
->bufmgr_config
.dma_low_water
= DEFAULT_DMA_LOW_WATER
;
9055 tp
->bufmgr_config
.dma_high_water
= DEFAULT_DMA_HIGH_WATER
;
9058 static char * __devinit
tg3_phy_string(struct tg3
*tp
)
9060 switch (tp
->phy_id
& PHY_ID_MASK
) {
9061 case PHY_ID_BCM5400
: return "5400";
9062 case PHY_ID_BCM5401
: return "5401";
9063 case PHY_ID_BCM5411
: return "5411";
9064 case PHY_ID_BCM5701
: return "5701";
9065 case PHY_ID_BCM5703
: return "5703";
9066 case PHY_ID_BCM5704
: return "5704";
9067 case PHY_ID_BCM5705
: return "5705";
9068 case PHY_ID_BCM5750
: return "5750";
9069 case PHY_ID_BCM5752
: return "5752";
9070 case PHY_ID_BCM8002
: return "8002/serdes";
9071 case 0: return "serdes";
9072 default: return "unknown";
9076 static struct pci_dev
* __devinit
tg3_find_5704_peer(struct tg3
*tp
)
9078 struct pci_dev
*peer
;
9079 unsigned int func
, devnr
= tp
->pdev
->devfn
& ~7;
9081 for (func
= 0; func
< 8; func
++) {
9082 peer
= pci_get_slot(tp
->pdev
->bus
, devnr
| func
);
9083 if (peer
&& peer
!= tp
->pdev
)
9087 if (!peer
|| peer
== tp
->pdev
)
9091 * We don't need to keep the refcount elevated; there's no way
9092 * to remove one half of this device without removing the other
9099 static int __devinit
tg3_init_one(struct pci_dev
*pdev
,
9100 const struct pci_device_id
*ent
)
9102 static int tg3_version_printed
= 0;
9103 unsigned long tg3reg_base
, tg3reg_len
;
9104 struct net_device
*dev
;
9106 int i
, err
, pci_using_dac
, pm_cap
;
9108 if (tg3_version_printed
++ == 0)
9109 printk(KERN_INFO
"%s", version
);
9111 err
= pci_enable_device(pdev
);
9113 printk(KERN_ERR PFX
"Cannot enable PCI device, "
9118 if (!(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
)) {
9119 printk(KERN_ERR PFX
"Cannot find proper PCI device "
9120 "base address, aborting.\n");
9122 goto err_out_disable_pdev
;
9125 err
= pci_request_regions(pdev
, DRV_MODULE_NAME
);
9127 printk(KERN_ERR PFX
"Cannot obtain PCI resources, "
9129 goto err_out_disable_pdev
;
9132 pci_set_master(pdev
);
9134 /* Find power-management capability. */
9135 pm_cap
= pci_find_capability(pdev
, PCI_CAP_ID_PM
);
9137 printk(KERN_ERR PFX
"Cannot find PowerManagement capability, "
9140 goto err_out_free_res
;
9143 /* Configure DMA attributes. */
9144 err
= pci_set_dma_mask(pdev
, 0xffffffffffffffffULL
);
9147 err
= pci_set_consistent_dma_mask(pdev
, 0xffffffffffffffffULL
);
9149 printk(KERN_ERR PFX
"Unable to obtain 64 bit DMA "
9150 "for consistent allocations\n");
9151 goto err_out_free_res
;
9154 err
= pci_set_dma_mask(pdev
, 0xffffffffULL
);
9156 printk(KERN_ERR PFX
"No usable DMA configuration, "
9158 goto err_out_free_res
;
9163 tg3reg_base
= pci_resource_start(pdev
, 0);
9164 tg3reg_len
= pci_resource_len(pdev
, 0);
9166 dev
= alloc_etherdev(sizeof(*tp
));
9168 printk(KERN_ERR PFX
"Etherdev alloc failed, aborting.\n");
9170 goto err_out_free_res
;
9173 SET_MODULE_OWNER(dev
);
9174 SET_NETDEV_DEV(dev
, &pdev
->dev
);
9177 dev
->features
|= NETIF_F_HIGHDMA
;
9178 dev
->features
|= NETIF_F_LLTX
;
9179 #if TG3_VLAN_TAG_USED
9180 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
9181 dev
->vlan_rx_register
= tg3_vlan_rx_register
;
9182 dev
->vlan_rx_kill_vid
= tg3_vlan_rx_kill_vid
;
9185 tp
= netdev_priv(dev
);
9188 tp
->pm_cap
= pm_cap
;
9189 tp
->mac_mode
= TG3_DEF_MAC_MODE
;
9190 tp
->rx_mode
= TG3_DEF_RX_MODE
;
9191 tp
->tx_mode
= TG3_DEF_TX_MODE
;
9192 tp
->mi_mode
= MAC_MI_MODE_BASE
;
9194 tp
->msg_enable
= tg3_debug
;
9196 tp
->msg_enable
= TG3_DEF_MSG_ENABLE
;
9198 /* The word/byte swap controls here control register access byte
9199 * swapping. DMA data byte swapping is controlled in the GRC_MODE
9202 tp
->misc_host_ctrl
=
9203 MISC_HOST_CTRL_MASK_PCI_INT
|
9204 MISC_HOST_CTRL_WORD_SWAP
|
9205 MISC_HOST_CTRL_INDIR_ACCESS
|
9206 MISC_HOST_CTRL_PCISTATE_RW
;
9208 /* The NONFRM (non-frame) byte/word swap controls take effect
9209 * on descriptor entries, anything which isn't packet data.
9211 * The StrongARM chips on the board (one for tx, one for rx)
9212 * are running in big-endian mode.
9214 tp
->grc_mode
= (GRC_MODE_WSWAP_DATA
| GRC_MODE_BSWAP_DATA
|
9215 GRC_MODE_WSWAP_NONFRM_DATA
);
9217 tp
->grc_mode
|= GRC_MODE_BSWAP_NONFRM_DATA
;
9219 spin_lock_init(&tp
->lock
);
9220 spin_lock_init(&tp
->tx_lock
);
9221 spin_lock_init(&tp
->indirect_lock
);
9222 INIT_WORK(&tp
->reset_task
, tg3_reset_task
, tp
);
9224 tp
->regs
= ioremap_nocache(tg3reg_base
, tg3reg_len
);
9225 if (tp
->regs
== 0UL) {
9226 printk(KERN_ERR PFX
"Cannot map device registers, "
9229 goto err_out_free_dev
;
9232 tg3_init_link_config(tp
);
9234 tg3_init_bufmgr_config(tp
);
9236 tp
->rx_pending
= TG3_DEF_RX_RING_PENDING
;
9237 tp
->rx_jumbo_pending
= TG3_DEF_RX_JUMBO_RING_PENDING
;
9238 tp
->tx_pending
= TG3_DEF_TX_RING_PENDING
;
9240 dev
->open
= tg3_open
;
9241 dev
->stop
= tg3_close
;
9242 dev
->get_stats
= tg3_get_stats
;
9243 dev
->set_multicast_list
= tg3_set_rx_mode
;
9244 dev
->set_mac_address
= tg3_set_mac_addr
;
9245 dev
->do_ioctl
= tg3_ioctl
;
9246 dev
->tx_timeout
= tg3_tx_timeout
;
9247 dev
->poll
= tg3_poll
;
9248 dev
->ethtool_ops
= &tg3_ethtool_ops
;
9250 dev
->watchdog_timeo
= TG3_TX_TIMEOUT
;
9251 dev
->change_mtu
= tg3_change_mtu
;
9252 dev
->irq
= pdev
->irq
;
9253 #ifdef CONFIG_NET_POLL_CONTROLLER
9254 dev
->poll_controller
= tg3_poll_controller
;
9257 err
= tg3_get_invariants(tp
);
9259 printk(KERN_ERR PFX
"Problem fetching invariants of chip, "
9261 goto err_out_iounmap
;
9264 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
9265 tp
->bufmgr_config
.mbuf_read_dma_low_water
=
9266 DEFAULT_MB_RDMA_LOW_WATER_5705
;
9267 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
9268 DEFAULT_MB_MACRX_LOW_WATER_5705
;
9269 tp
->bufmgr_config
.mbuf_high_water
=
9270 DEFAULT_MB_HIGH_WATER_5705
;
9273 #if TG3_TSO_SUPPORT != 0
9274 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
) {
9275 tp
->tg3_flags2
|= TG3_FLG2_TSO_CAPABLE
;
9277 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
9278 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
||
9279 tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A0
||
9280 (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) != 0) {
9281 tp
->tg3_flags2
&= ~TG3_FLG2_TSO_CAPABLE
;
9283 tp
->tg3_flags2
|= TG3_FLG2_TSO_CAPABLE
;
9286 /* TSO is off by default, user can enable using ethtool. */
9288 if (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
)
9289 dev
->features
|= NETIF_F_TSO
;
9294 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A1
&&
9295 !(tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) &&
9296 !(tr32(TG3PCI_PCISTATE
) & PCISTATE_BUS_SPEED_HIGH
)) {
9297 tp
->tg3_flags2
|= TG3_FLG2_MAX_RXPEND_64
;
9298 tp
->rx_pending
= 63;
9301 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
)
9302 tp
->pdev_peer
= tg3_find_5704_peer(tp
);
9304 err
= tg3_get_device_address(tp
);
9306 printk(KERN_ERR PFX
"Could not obtain valid ethernet address, "
9308 goto err_out_iounmap
;
9312 * Reset chip in case UNDI or EFI driver did not shutdown
9313 * DMA self test will enable WDMAC and we'll see (spurious)
9314 * pending DMA on the PCI bus at that point.
9316 if ((tr32(HOSTCC_MODE
) & HOSTCC_MODE_ENABLE
) ||
9317 (tr32(WDMAC_MODE
) & WDMAC_MODE_ENABLE
)) {
9318 pci_save_state(tp
->pdev
);
9319 tw32(MEMARB_MODE
, MEMARB_MODE_ENABLE
);
9323 err
= tg3_test_dma(tp
);
9325 printk(KERN_ERR PFX
"DMA engine test failed, aborting.\n");
9326 goto err_out_iounmap
;
9329 /* Tigon3 can do ipv4 only... and some chips have buggy
9332 if ((tp
->tg3_flags
& TG3_FLAG_BROKEN_CHECKSUMS
) == 0) {
9333 dev
->features
|= NETIF_F_SG
| NETIF_F_IP_CSUM
;
9334 tp
->tg3_flags
|= TG3_FLAG_RX_CHECKSUMS
;
9336 tp
->tg3_flags
&= ~TG3_FLAG_RX_CHECKSUMS
;
9338 if (tp
->tg3_flags2
& TG3_FLG2_IS_5788
)
9339 dev
->features
&= ~NETIF_F_HIGHDMA
;
9341 /* flow control autonegotiation is default behavior */
9342 tp
->tg3_flags
|= TG3_FLAG_PAUSE_AUTONEG
;
9344 err
= register_netdev(dev
);
9346 printk(KERN_ERR PFX
"Cannot register net device, "
9348 goto err_out_iounmap
;
9351 pci_set_drvdata(pdev
, dev
);
9353 /* Now that we have fully setup the chip, save away a snapshot
9354 * of the PCI config space. We need to restore this after
9355 * GRC_MISC_CFG core clock resets and some resume events.
9357 pci_save_state(tp
->pdev
);
9359 printk(KERN_INFO
"%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (PCI%s:%s:%s) %sBaseT Ethernet ",
9361 tp
->board_part_number
,
9362 tp
->pci_chip_rev_id
,
9364 ((tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) ? "X" : ""),
9365 ((tp
->tg3_flags
& TG3_FLAG_PCI_HIGH_SPEED
) ?
9366 ((tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) ? "133MHz" : "66MHz") :
9367 ((tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) ? "100MHz" : "33MHz")),
9368 ((tp
->tg3_flags
& TG3_FLAG_PCI_32BIT
) ? "32-bit" : "64-bit"),
9369 (tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
) ? "10/100" : "10/100/1000");
9371 for (i
= 0; i
< 6; i
++)
9372 printk("%2.2x%c", dev
->dev_addr
[i
],
9373 i
== 5 ? '\n' : ':');
9375 printk(KERN_INFO
"%s: RXcsums[%d] LinkChgREG[%d] "
9376 "MIirq[%d] ASF[%d] Split[%d] WireSpeed[%d] "
9379 (tp
->tg3_flags
& TG3_FLAG_RX_CHECKSUMS
) != 0,
9380 (tp
->tg3_flags
& TG3_FLAG_USE_LINKCHG_REG
) != 0,
9381 (tp
->tg3_flags
& TG3_FLAG_USE_MI_INTERRUPT
) != 0,
9382 (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) != 0,
9383 (tp
->tg3_flags
& TG3_FLAG_SPLIT_MODE
) != 0,
9384 (tp
->tg3_flags2
& TG3_FLG2_NO_ETH_WIRE_SPEED
) == 0,
9385 (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) != 0);
9396 pci_release_regions(pdev
);
9398 err_out_disable_pdev
:
9399 pci_disable_device(pdev
);
9400 pci_set_drvdata(pdev
, NULL
);
9404 static void __devexit
tg3_remove_one(struct pci_dev
*pdev
)
9406 struct net_device
*dev
= pci_get_drvdata(pdev
);
9409 struct tg3
*tp
= netdev_priv(dev
);
9411 unregister_netdev(dev
);
9414 pci_release_regions(pdev
);
9415 pci_disable_device(pdev
);
9416 pci_set_drvdata(pdev
, NULL
);
9420 static int tg3_suspend(struct pci_dev
*pdev
, pm_message_t state
)
9422 struct net_device
*dev
= pci_get_drvdata(pdev
);
9423 struct tg3
*tp
= netdev_priv(dev
);
9426 if (!netif_running(dev
))
9431 del_timer_sync(&tp
->timer
);
9433 spin_lock_irq(&tp
->lock
);
9434 spin_lock(&tp
->tx_lock
);
9435 tg3_disable_ints(tp
);
9436 spin_unlock(&tp
->tx_lock
);
9437 spin_unlock_irq(&tp
->lock
);
9439 netif_device_detach(dev
);
9441 spin_lock_irq(&tp
->lock
);
9442 spin_lock(&tp
->tx_lock
);
9444 spin_unlock(&tp
->tx_lock
);
9445 spin_unlock_irq(&tp
->lock
);
9447 err
= tg3_set_power_state(tp
, pci_choose_state(pdev
, state
));
9449 spin_lock_irq(&tp
->lock
);
9450 spin_lock(&tp
->tx_lock
);
9454 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
9455 add_timer(&tp
->timer
);
9457 netif_device_attach(dev
);
9458 tg3_netif_start(tp
);
9460 spin_unlock(&tp
->tx_lock
);
9461 spin_unlock_irq(&tp
->lock
);
9467 static int tg3_resume(struct pci_dev
*pdev
)
9469 struct net_device
*dev
= pci_get_drvdata(pdev
);
9470 struct tg3
*tp
= netdev_priv(dev
);
9473 if (!netif_running(dev
))
9476 pci_restore_state(tp
->pdev
);
9478 err
= tg3_set_power_state(tp
, 0);
9482 netif_device_attach(dev
);
9484 spin_lock_irq(&tp
->lock
);
9485 spin_lock(&tp
->tx_lock
);
9489 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
9490 add_timer(&tp
->timer
);
9492 tg3_enable_ints(tp
);
9494 tg3_netif_start(tp
);
9496 spin_unlock(&tp
->tx_lock
);
9497 spin_unlock_irq(&tp
->lock
);
9502 static struct pci_driver tg3_driver
= {
9503 .name
= DRV_MODULE_NAME
,
9504 .id_table
= tg3_pci_tbl
,
9505 .probe
= tg3_init_one
,
9506 .remove
= __devexit_p(tg3_remove_one
),
9507 .suspend
= tg3_suspend
,
9508 .resume
= tg3_resume
9511 static int __init
tg3_init(void)
9513 return pci_module_init(&tg3_driver
);
9516 static void __exit
tg3_cleanup(void)
9518 pci_unregister_driver(&tg3_driver
);
9521 module_init(tg3_init
);
9522 module_exit(tg3_cleanup
);