2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2010 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/compiler.h>
24 #include <linux/slab.h>
25 #include <linux/delay.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/phy.h>
36 #include <linux/brcmphy.h>
37 #include <linux/if_vlan.h>
39 #include <linux/tcp.h>
40 #include <linux/workqueue.h>
41 #include <linux/prefetch.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/firmware.h>
45 #include <net/checksum.h>
48 #include <asm/system.h>
50 #include <asm/byteorder.h>
51 #include <asm/uaccess.h>
54 #include <asm/idprom.h>
61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62 #define TG3_VLAN_TAG_USED 1
64 #define TG3_VLAN_TAG_USED 0
69 #define DRV_MODULE_NAME "tg3"
70 #define DRV_MODULE_VERSION "3.110"
71 #define DRV_MODULE_RELDATE "April 9, 2010"
73 #define TG3_DEF_MAC_MODE 0
74 #define TG3_DEF_RX_MODE 0
75 #define TG3_DEF_TX_MODE 0
76 #define TG3_DEF_MSG_ENABLE \
86 /* length of time before we decide the hardware is borked,
87 * and dev->tx_timeout() should be called to fix the problem
89 #define TG3_TX_TIMEOUT (5 * HZ)
91 /* hardware minimum and maximum for a single frame's data payload */
92 #define TG3_MIN_MTU 60
93 #define TG3_MAX_MTU(tp) \
94 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
96 /* These numbers seem to be hard coded in the NIC firmware somehow.
97 * You can't change the ring sizes, but you can change where you place
98 * them in the NIC onboard memory.
100 #define TG3_RX_RING_SIZE 512
101 #define TG3_DEF_RX_RING_PENDING 200
102 #define TG3_RX_JUMBO_RING_SIZE 256
103 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
104 #define TG3_RSS_INDIR_TBL_SIZE 128
106 /* Do not place this n-ring entries value into the tp struct itself,
107 * we really want to expose these constants to GCC so that modulo et
108 * al. operations are done with shifts and masks instead of with
109 * hw multiply/modulo instructions. Another solution would be to
110 * replace things like '% foo' with '& (foo - 1)'.
112 #define TG3_RX_RCB_RING_SIZE(tp) \
113 (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
114 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
116 #define TG3_TX_RING_SIZE 512
117 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
119 #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
121 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
122 TG3_RX_JUMBO_RING_SIZE)
123 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
124 TG3_RX_RCB_RING_SIZE(tp))
125 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
127 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
129 #define TG3_RX_DMA_ALIGN 16
130 #define TG3_RX_HEADROOM ALIGN(VLAN_HLEN, TG3_RX_DMA_ALIGN)
132 #define TG3_DMA_BYTE_ENAB 64
134 #define TG3_RX_STD_DMA_SZ 1536
135 #define TG3_RX_JMB_DMA_SZ 9046
137 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
139 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
140 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
142 #define TG3_RX_STD_BUFF_RING_SIZE \
143 (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
145 #define TG3_RX_JMB_BUFF_RING_SIZE \
146 (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
148 #define TG3_RSS_MIN_NUM_MSIX_VECS 2
150 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
151 * that are at least dword aligned when used in PCIX mode. The driver
152 * works around this bug by double copying the packet. This workaround
153 * is built into the normal double copy length check for efficiency.
155 * However, the double copy is only necessary on those architectures
156 * where unaligned memory accesses are inefficient. For those architectures
157 * where unaligned memory accesses incur little penalty, we can reintegrate
158 * the 5701 in the normal rx path. Doing so saves a device structure
159 * dereference by hardcoding the double copy threshold in place.
161 #define TG3_RX_COPY_THRESHOLD 256
162 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
163 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
165 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
168 /* minimum number of free TX descriptors required to wake up TX process */
169 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
171 #define TG3_RAW_IP_ALIGN 2
173 /* number of ETHTOOL_GSTATS u64's */
174 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
176 #define TG3_NUM_TEST 6
178 #define TG3_FW_UPDATE_TIMEOUT_SEC 5
180 #define FIRMWARE_TG3 "tigon/tg3.bin"
181 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
182 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
184 static char version
[] __devinitdata
=
185 DRV_MODULE_NAME
".c:v" DRV_MODULE_VERSION
" (" DRV_MODULE_RELDATE
")";
187 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
188 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
189 MODULE_LICENSE("GPL");
190 MODULE_VERSION(DRV_MODULE_VERSION
);
191 MODULE_FIRMWARE(FIRMWARE_TG3
);
192 MODULE_FIRMWARE(FIRMWARE_TG3TSO
);
193 MODULE_FIRMWARE(FIRMWARE_TG3TSO5
);
195 static int tg3_debug
= -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
196 module_param(tg3_debug
, int, 0);
197 MODULE_PARM_DESC(tg3_debug
, "Tigon3 bitmapped debugging message enable value");
199 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl
) = {
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5700
)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5701
)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702
)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5703
)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5704
)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702FE
)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705
)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705_2
)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705M
)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705M_2
)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702X
)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5703X
)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5704S
)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702A3
)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5703A3
)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5782
)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5788
)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5789
)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5901
)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5901_2
)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5704S_2
)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705F
)},
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5720
)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5721
)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5722
)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5750
)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5751
)},
227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5750M
)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5751M
)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5751F
)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5752
)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5752M
)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5753
)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5753M
)},
234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5753F
)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5754
)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5754M
)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5755
)},
238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5755M
)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5756
)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5786
)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5787
)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5787M
)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5787F
)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5714
)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5714S
)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5715
)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5715S
)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5780
)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5780S
)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5781
)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5906
)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5906M
)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5784
)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5764
)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5723
)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5761
)},
257 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5761E
)},
258 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5761S
)},
259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5761SE
)},
260 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5785_G
)},
261 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5785_F
)},
262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57780
)},
263 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57760
)},
264 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57790
)},
265 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57788
)},
266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5717
)},
267 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5718
)},
268 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5724
)},
269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57781
)},
270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57785
)},
271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57761
)},
272 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57765
)},
273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57791
)},
274 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57795
)},
275 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, PCI_DEVICE_ID_SYSKONNECT_9DXX
)},
276 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, PCI_DEVICE_ID_SYSKONNECT_9MXX
)},
277 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC1000
)},
278 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC1001
)},
279 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC1003
)},
280 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC9100
)},
281 {PCI_DEVICE(PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_TIGON3
)},
285 MODULE_DEVICE_TABLE(pci
, tg3_pci_tbl
);
287 static const struct {
288 const char string
[ETH_GSTRING_LEN
];
289 } ethtool_stats_keys
[TG3_NUM_STATS
] = {
292 { "rx_ucast_packets" },
293 { "rx_mcast_packets" },
294 { "rx_bcast_packets" },
296 { "rx_align_errors" },
297 { "rx_xon_pause_rcvd" },
298 { "rx_xoff_pause_rcvd" },
299 { "rx_mac_ctrl_rcvd" },
300 { "rx_xoff_entered" },
301 { "rx_frame_too_long_errors" },
303 { "rx_undersize_packets" },
304 { "rx_in_length_errors" },
305 { "rx_out_length_errors" },
306 { "rx_64_or_less_octet_packets" },
307 { "rx_65_to_127_octet_packets" },
308 { "rx_128_to_255_octet_packets" },
309 { "rx_256_to_511_octet_packets" },
310 { "rx_512_to_1023_octet_packets" },
311 { "rx_1024_to_1522_octet_packets" },
312 { "rx_1523_to_2047_octet_packets" },
313 { "rx_2048_to_4095_octet_packets" },
314 { "rx_4096_to_8191_octet_packets" },
315 { "rx_8192_to_9022_octet_packets" },
322 { "tx_flow_control" },
324 { "tx_single_collisions" },
325 { "tx_mult_collisions" },
327 { "tx_excessive_collisions" },
328 { "tx_late_collisions" },
329 { "tx_collide_2times" },
330 { "tx_collide_3times" },
331 { "tx_collide_4times" },
332 { "tx_collide_5times" },
333 { "tx_collide_6times" },
334 { "tx_collide_7times" },
335 { "tx_collide_8times" },
336 { "tx_collide_9times" },
337 { "tx_collide_10times" },
338 { "tx_collide_11times" },
339 { "tx_collide_12times" },
340 { "tx_collide_13times" },
341 { "tx_collide_14times" },
342 { "tx_collide_15times" },
343 { "tx_ucast_packets" },
344 { "tx_mcast_packets" },
345 { "tx_bcast_packets" },
346 { "tx_carrier_sense_errors" },
350 { "dma_writeq_full" },
351 { "dma_write_prioq_full" },
355 { "rx_threshold_hit" },
357 { "dma_readq_full" },
358 { "dma_read_prioq_full" },
359 { "tx_comp_queue_full" },
361 { "ring_set_send_prod_index" },
362 { "ring_status_update" },
364 { "nic_avoided_irqs" },
365 { "nic_tx_threshold_hit" }
368 static const struct {
369 const char string
[ETH_GSTRING_LEN
];
370 } ethtool_test_keys
[TG3_NUM_TEST
] = {
371 { "nvram test (online) " },
372 { "link test (online) " },
373 { "register test (offline)" },
374 { "memory test (offline)" },
375 { "loopback test (offline)" },
376 { "interrupt test (offline)" },
379 static void tg3_write32(struct tg3
*tp
, u32 off
, u32 val
)
381 writel(val
, tp
->regs
+ off
);
384 static u32
tg3_read32(struct tg3
*tp
, u32 off
)
386 return readl(tp
->regs
+ off
);
389 static void tg3_ape_write32(struct tg3
*tp
, u32 off
, u32 val
)
391 writel(val
, tp
->aperegs
+ off
);
394 static u32
tg3_ape_read32(struct tg3
*tp
, u32 off
)
396 return readl(tp
->aperegs
+ off
);
399 static void tg3_write_indirect_reg32(struct tg3
*tp
, u32 off
, u32 val
)
403 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
404 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
);
405 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, val
);
406 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
409 static void tg3_write_flush_reg32(struct tg3
*tp
, u32 off
, u32 val
)
411 writel(val
, tp
->regs
+ off
);
412 readl(tp
->regs
+ off
);
415 static u32
tg3_read_indirect_reg32(struct tg3
*tp
, u32 off
)
420 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
421 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
);
422 pci_read_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, &val
);
423 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
427 static void tg3_write_indirect_mbox(struct tg3
*tp
, u32 off
, u32 val
)
431 if (off
== (MAILBOX_RCVRET_CON_IDX_0
+ TG3_64BIT_REG_LOW
)) {
432 pci_write_config_dword(tp
->pdev
, TG3PCI_RCV_RET_RING_CON_IDX
+
433 TG3_64BIT_REG_LOW
, val
);
436 if (off
== TG3_RX_STD_PROD_IDX_REG
) {
437 pci_write_config_dword(tp
->pdev
, TG3PCI_STD_RING_PROD_IDX
+
438 TG3_64BIT_REG_LOW
, val
);
442 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
443 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
+ 0x5600);
444 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, val
);
445 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
447 /* In indirect mode when disabling interrupts, we also need
448 * to clear the interrupt bit in the GRC local ctrl register.
450 if ((off
== (MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
)) &&
452 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_LOCAL_CTRL
,
453 tp
->grc_local_ctrl
|GRC_LCLCTRL_CLEARINT
);
457 static u32
tg3_read_indirect_mbox(struct tg3
*tp
, u32 off
)
462 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
463 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
+ 0x5600);
464 pci_read_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, &val
);
465 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
469 /* usec_wait specifies the wait time in usec when writing to certain registers
470 * where it is unsafe to read back the register without some delay.
471 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
472 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
474 static void _tw32_flush(struct tg3
*tp
, u32 off
, u32 val
, u32 usec_wait
)
476 if ((tp
->tg3_flags
& TG3_FLAG_PCIX_TARGET_HWBUG
) ||
477 (tp
->tg3_flags2
& TG3_FLG2_ICH_WORKAROUND
))
478 /* Non-posted methods */
479 tp
->write32(tp
, off
, val
);
482 tg3_write32(tp
, off
, val
);
487 /* Wait again after the read for the posted method to guarantee that
488 * the wait time is met.
494 static inline void tw32_mailbox_flush(struct tg3
*tp
, u32 off
, u32 val
)
496 tp
->write32_mbox(tp
, off
, val
);
497 if (!(tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
) &&
498 !(tp
->tg3_flags2
& TG3_FLG2_ICH_WORKAROUND
))
499 tp
->read32_mbox(tp
, off
);
502 static void tg3_write32_tx_mbox(struct tg3
*tp
, u32 off
, u32 val
)
504 void __iomem
*mbox
= tp
->regs
+ off
;
506 if (tp
->tg3_flags
& TG3_FLAG_TXD_MBOX_HWBUG
)
508 if (tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
)
512 static u32
tg3_read32_mbox_5906(struct tg3
*tp
, u32 off
)
514 return readl(tp
->regs
+ off
+ GRCMBOX_BASE
);
517 static void tg3_write32_mbox_5906(struct tg3
*tp
, u32 off
, u32 val
)
519 writel(val
, tp
->regs
+ off
+ GRCMBOX_BASE
);
522 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
523 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
524 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
525 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
526 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
528 #define tw32(reg, val) tp->write32(tp, reg, val)
529 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
530 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
531 #define tr32(reg) tp->read32(tp, reg)
533 static void tg3_write_mem(struct tg3
*tp
, u32 off
, u32 val
)
537 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) &&
538 (off
>= NIC_SRAM_STATS_BLK
) && (off
< NIC_SRAM_TX_BUFFER_DESC
))
541 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
542 if (tp
->tg3_flags
& TG3_FLAG_SRAM_USE_CONFIG
) {
543 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, off
);
544 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_DATA
, val
);
546 /* Always leave this as zero. */
547 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, 0);
549 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, off
);
550 tw32_f(TG3PCI_MEM_WIN_DATA
, val
);
552 /* Always leave this as zero. */
553 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
555 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
558 static void tg3_read_mem(struct tg3
*tp
, u32 off
, u32
*val
)
562 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) &&
563 (off
>= NIC_SRAM_STATS_BLK
) && (off
< NIC_SRAM_TX_BUFFER_DESC
)) {
568 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
569 if (tp
->tg3_flags
& TG3_FLAG_SRAM_USE_CONFIG
) {
570 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, off
);
571 pci_read_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_DATA
, val
);
573 /* Always leave this as zero. */
574 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, 0);
576 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, off
);
577 *val
= tr32(TG3PCI_MEM_WIN_DATA
);
579 /* Always leave this as zero. */
580 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
582 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
585 static void tg3_ape_lock_init(struct tg3
*tp
)
589 /* Make sure the driver hasn't any stale locks. */
590 for (i
= 0; i
< 8; i
++)
591 tg3_ape_write32(tp
, TG3_APE_LOCK_GRANT
+ 4 * i
,
592 APE_LOCK_GRANT_DRIVER
);
595 static int tg3_ape_lock(struct tg3
*tp
, int locknum
)
601 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
))
605 case TG3_APE_LOCK_GRC
:
606 case TG3_APE_LOCK_MEM
:
614 tg3_ape_write32(tp
, TG3_APE_LOCK_REQ
+ off
, APE_LOCK_REQ_DRIVER
);
616 /* Wait for up to 1 millisecond to acquire lock. */
617 for (i
= 0; i
< 100; i
++) {
618 status
= tg3_ape_read32(tp
, TG3_APE_LOCK_GRANT
+ off
);
619 if (status
== APE_LOCK_GRANT_DRIVER
)
624 if (status
!= APE_LOCK_GRANT_DRIVER
) {
625 /* Revoke the lock request. */
626 tg3_ape_write32(tp
, TG3_APE_LOCK_GRANT
+ off
,
627 APE_LOCK_GRANT_DRIVER
);
635 static void tg3_ape_unlock(struct tg3
*tp
, int locknum
)
639 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
))
643 case TG3_APE_LOCK_GRC
:
644 case TG3_APE_LOCK_MEM
:
651 tg3_ape_write32(tp
, TG3_APE_LOCK_GRANT
+ off
, APE_LOCK_GRANT_DRIVER
);
654 static void tg3_disable_ints(struct tg3
*tp
)
658 tw32(TG3PCI_MISC_HOST_CTRL
,
659 (tp
->misc_host_ctrl
| MISC_HOST_CTRL_MASK_PCI_INT
));
660 for (i
= 0; i
< tp
->irq_max
; i
++)
661 tw32_mailbox_f(tp
->napi
[i
].int_mbox
, 0x00000001);
664 static void tg3_enable_ints(struct tg3
*tp
)
671 tw32(TG3PCI_MISC_HOST_CTRL
,
672 (tp
->misc_host_ctrl
& ~MISC_HOST_CTRL_MASK_PCI_INT
));
674 tp
->coal_now
= tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
;
675 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
676 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
678 tw32_mailbox_f(tnapi
->int_mbox
, tnapi
->last_tag
<< 24);
679 if (tp
->tg3_flags2
& TG3_FLG2_1SHOT_MSI
)
680 tw32_mailbox_f(tnapi
->int_mbox
, tnapi
->last_tag
<< 24);
682 tp
->coal_now
|= tnapi
->coal_now
;
685 /* Force an initial interrupt */
686 if (!(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) &&
687 (tp
->napi
[0].hw_status
->status
& SD_STATUS_UPDATED
))
688 tw32(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
| GRC_LCLCTRL_SETINT
);
690 tw32(HOSTCC_MODE
, tp
->coal_now
);
692 tp
->coal_now
&= ~(tp
->napi
[0].coal_now
| tp
->napi
[1].coal_now
);
695 static inline unsigned int tg3_has_work(struct tg3_napi
*tnapi
)
697 struct tg3
*tp
= tnapi
->tp
;
698 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
699 unsigned int work_exists
= 0;
701 /* check for phy events */
702 if (!(tp
->tg3_flags
&
703 (TG3_FLAG_USE_LINKCHG_REG
|
704 TG3_FLAG_POLL_SERDES
))) {
705 if (sblk
->status
& SD_STATUS_LINK_CHG
)
708 /* check for RX/TX work to do */
709 if (sblk
->idx
[0].tx_consumer
!= tnapi
->tx_cons
||
710 *(tnapi
->rx_rcb_prod_idx
) != tnapi
->rx_rcb_ptr
)
717 * similar to tg3_enable_ints, but it accurately determines whether there
718 * is new work pending and can return without flushing the PIO write
719 * which reenables interrupts
721 static void tg3_int_reenable(struct tg3_napi
*tnapi
)
723 struct tg3
*tp
= tnapi
->tp
;
725 tw32_mailbox(tnapi
->int_mbox
, tnapi
->last_tag
<< 24);
728 /* When doing tagged status, this work check is unnecessary.
729 * The last_tag we write above tells the chip which piece of
730 * work we've completed.
732 if (!(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) &&
734 tw32(HOSTCC_MODE
, tp
->coalesce_mode
|
735 HOSTCC_MODE_ENABLE
| tnapi
->coal_now
);
738 static void tg3_napi_disable(struct tg3
*tp
)
742 for (i
= tp
->irq_cnt
- 1; i
>= 0; i
--)
743 napi_disable(&tp
->napi
[i
].napi
);
746 static void tg3_napi_enable(struct tg3
*tp
)
750 for (i
= 0; i
< tp
->irq_cnt
; i
++)
751 napi_enable(&tp
->napi
[i
].napi
);
754 static inline void tg3_netif_stop(struct tg3
*tp
)
756 tp
->dev
->trans_start
= jiffies
; /* prevent tx timeout */
757 tg3_napi_disable(tp
);
758 netif_tx_disable(tp
->dev
);
761 static inline void tg3_netif_start(struct tg3
*tp
)
763 /* NOTE: unconditional netif_tx_wake_all_queues is only
764 * appropriate so long as all callers are assured to
765 * have free tx slots (such as after tg3_init_hw)
767 netif_tx_wake_all_queues(tp
->dev
);
770 tp
->napi
[0].hw_status
->status
|= SD_STATUS_UPDATED
;
774 static void tg3_switch_clocks(struct tg3
*tp
)
779 if ((tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) ||
780 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
783 clock_ctrl
= tr32(TG3PCI_CLOCK_CTRL
);
785 orig_clock_ctrl
= clock_ctrl
;
786 clock_ctrl
&= (CLOCK_CTRL_FORCE_CLKRUN
|
787 CLOCK_CTRL_CLKRUN_OENABLE
|
789 tp
->pci_clock_ctrl
= clock_ctrl
;
791 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
792 if (orig_clock_ctrl
& CLOCK_CTRL_625_CORE
) {
793 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
794 clock_ctrl
| CLOCK_CTRL_625_CORE
, 40);
796 } else if ((orig_clock_ctrl
& CLOCK_CTRL_44MHZ_CORE
) != 0) {
797 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
799 (CLOCK_CTRL_44MHZ_CORE
| CLOCK_CTRL_ALTCLK
),
801 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
802 clock_ctrl
| (CLOCK_CTRL_ALTCLK
),
805 tw32_wait_f(TG3PCI_CLOCK_CTRL
, clock_ctrl
, 40);
808 #define PHY_BUSY_LOOPS 5000
810 static int tg3_readphy(struct tg3
*tp
, int reg
, u32
*val
)
816 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
818 (tp
->mi_mode
& ~MAC_MI_MODE_AUTO_POLL
));
824 frame_val
= ((tp
->phy_addr
<< MI_COM_PHY_ADDR_SHIFT
) &
825 MI_COM_PHY_ADDR_MASK
);
826 frame_val
|= ((reg
<< MI_COM_REG_ADDR_SHIFT
) &
827 MI_COM_REG_ADDR_MASK
);
828 frame_val
|= (MI_COM_CMD_READ
| MI_COM_START
);
830 tw32_f(MAC_MI_COM
, frame_val
);
832 loops
= PHY_BUSY_LOOPS
;
835 frame_val
= tr32(MAC_MI_COM
);
837 if ((frame_val
& MI_COM_BUSY
) == 0) {
839 frame_val
= tr32(MAC_MI_COM
);
847 *val
= frame_val
& MI_COM_DATA_MASK
;
851 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
852 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
859 static int tg3_writephy(struct tg3
*tp
, int reg
, u32 val
)
865 if ((tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
) &&
866 (reg
== MII_TG3_CTRL
|| reg
== MII_TG3_AUX_CTRL
))
869 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
871 (tp
->mi_mode
& ~MAC_MI_MODE_AUTO_POLL
));
875 frame_val
= ((tp
->phy_addr
<< MI_COM_PHY_ADDR_SHIFT
) &
876 MI_COM_PHY_ADDR_MASK
);
877 frame_val
|= ((reg
<< MI_COM_REG_ADDR_SHIFT
) &
878 MI_COM_REG_ADDR_MASK
);
879 frame_val
|= (val
& MI_COM_DATA_MASK
);
880 frame_val
|= (MI_COM_CMD_WRITE
| MI_COM_START
);
882 tw32_f(MAC_MI_COM
, frame_val
);
884 loops
= PHY_BUSY_LOOPS
;
887 frame_val
= tr32(MAC_MI_COM
);
888 if ((frame_val
& MI_COM_BUSY
) == 0) {
890 frame_val
= tr32(MAC_MI_COM
);
900 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
901 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
908 static int tg3_bmcr_reset(struct tg3
*tp
)
913 /* OK, reset it, and poll the BMCR_RESET bit until it
914 * clears or we time out.
916 phy_control
= BMCR_RESET
;
917 err
= tg3_writephy(tp
, MII_BMCR
, phy_control
);
923 err
= tg3_readphy(tp
, MII_BMCR
, &phy_control
);
927 if ((phy_control
& BMCR_RESET
) == 0) {
939 static int tg3_mdio_read(struct mii_bus
*bp
, int mii_id
, int reg
)
941 struct tg3
*tp
= bp
->priv
;
944 spin_lock_bh(&tp
->lock
);
946 if (tg3_readphy(tp
, reg
, &val
))
949 spin_unlock_bh(&tp
->lock
);
954 static int tg3_mdio_write(struct mii_bus
*bp
, int mii_id
, int reg
, u16 val
)
956 struct tg3
*tp
= bp
->priv
;
959 spin_lock_bh(&tp
->lock
);
961 if (tg3_writephy(tp
, reg
, val
))
964 spin_unlock_bh(&tp
->lock
);
969 static int tg3_mdio_reset(struct mii_bus
*bp
)
974 static void tg3_mdio_config_5785(struct tg3
*tp
)
977 struct phy_device
*phydev
;
979 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
980 switch (phydev
->drv
->phy_id
& phydev
->drv
->phy_id_mask
) {
981 case PHY_ID_BCM50610
:
982 case PHY_ID_BCM50610M
:
983 val
= MAC_PHYCFG2_50610_LED_MODES
;
985 case PHY_ID_BCMAC131
:
986 val
= MAC_PHYCFG2_AC131_LED_MODES
;
988 case PHY_ID_RTL8211C
:
989 val
= MAC_PHYCFG2_RTL8211C_LED_MODES
;
991 case PHY_ID_RTL8201E
:
992 val
= MAC_PHYCFG2_RTL8201E_LED_MODES
;
998 if (phydev
->interface
!= PHY_INTERFACE_MODE_RGMII
) {
999 tw32(MAC_PHYCFG2
, val
);
1001 val
= tr32(MAC_PHYCFG1
);
1002 val
&= ~(MAC_PHYCFG1_RGMII_INT
|
1003 MAC_PHYCFG1_RXCLK_TO_MASK
| MAC_PHYCFG1_TXCLK_TO_MASK
);
1004 val
|= MAC_PHYCFG1_RXCLK_TIMEOUT
| MAC_PHYCFG1_TXCLK_TIMEOUT
;
1005 tw32(MAC_PHYCFG1
, val
);
1010 if (!(tp
->tg3_flags3
& TG3_FLG3_RGMII_INBAND_DISABLE
))
1011 val
|= MAC_PHYCFG2_EMODE_MASK_MASK
|
1012 MAC_PHYCFG2_FMODE_MASK_MASK
|
1013 MAC_PHYCFG2_GMODE_MASK_MASK
|
1014 MAC_PHYCFG2_ACT_MASK_MASK
|
1015 MAC_PHYCFG2_QUAL_MASK_MASK
|
1016 MAC_PHYCFG2_INBAND_ENABLE
;
1018 tw32(MAC_PHYCFG2
, val
);
1020 val
= tr32(MAC_PHYCFG1
);
1021 val
&= ~(MAC_PHYCFG1_RXCLK_TO_MASK
| MAC_PHYCFG1_TXCLK_TO_MASK
|
1022 MAC_PHYCFG1_RGMII_EXT_RX_DEC
| MAC_PHYCFG1_RGMII_SND_STAT_EN
);
1023 if (!(tp
->tg3_flags3
& TG3_FLG3_RGMII_INBAND_DISABLE
)) {
1024 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_RX_EN
)
1025 val
|= MAC_PHYCFG1_RGMII_EXT_RX_DEC
;
1026 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_TX_EN
)
1027 val
|= MAC_PHYCFG1_RGMII_SND_STAT_EN
;
1029 val
|= MAC_PHYCFG1_RXCLK_TIMEOUT
| MAC_PHYCFG1_TXCLK_TIMEOUT
|
1030 MAC_PHYCFG1_RGMII_INT
| MAC_PHYCFG1_TXC_DRV
;
1031 tw32(MAC_PHYCFG1
, val
);
1033 val
= tr32(MAC_EXT_RGMII_MODE
);
1034 val
&= ~(MAC_RGMII_MODE_RX_INT_B
|
1035 MAC_RGMII_MODE_RX_QUALITY
|
1036 MAC_RGMII_MODE_RX_ACTIVITY
|
1037 MAC_RGMII_MODE_RX_ENG_DET
|
1038 MAC_RGMII_MODE_TX_ENABLE
|
1039 MAC_RGMII_MODE_TX_LOWPWR
|
1040 MAC_RGMII_MODE_TX_RESET
);
1041 if (!(tp
->tg3_flags3
& TG3_FLG3_RGMII_INBAND_DISABLE
)) {
1042 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_RX_EN
)
1043 val
|= MAC_RGMII_MODE_RX_INT_B
|
1044 MAC_RGMII_MODE_RX_QUALITY
|
1045 MAC_RGMII_MODE_RX_ACTIVITY
|
1046 MAC_RGMII_MODE_RX_ENG_DET
;
1047 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_TX_EN
)
1048 val
|= MAC_RGMII_MODE_TX_ENABLE
|
1049 MAC_RGMII_MODE_TX_LOWPWR
|
1050 MAC_RGMII_MODE_TX_RESET
;
1052 tw32(MAC_EXT_RGMII_MODE
, val
);
1055 static void tg3_mdio_start(struct tg3
*tp
)
1057 tp
->mi_mode
&= ~MAC_MI_MODE_AUTO_POLL
;
1058 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
1061 if ((tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_INITED
) &&
1062 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
1063 tg3_mdio_config_5785(tp
);
1066 static int tg3_mdio_init(struct tg3
*tp
)
1070 struct phy_device
*phydev
;
1072 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
) {
1073 u32 funcnum
, is_serdes
;
1075 funcnum
= tr32(TG3_CPMU_STATUS
) & TG3_CPMU_STATUS_PCIE_FUNC
;
1081 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5717_A0
)
1082 is_serdes
= tr32(SG_DIG_STATUS
) & SG_DIG_IS_SERDES
;
1084 is_serdes
= tr32(TG3_CPMU_PHY_STRAP
) &
1085 TG3_CPMU_PHY_STRAP_IS_SERDES
;
1089 tp
->phy_addr
= TG3_PHY_MII_ADDR
;
1093 if (!(tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) ||
1094 (tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_INITED
))
1097 tp
->mdio_bus
= mdiobus_alloc();
1098 if (tp
->mdio_bus
== NULL
)
1101 tp
->mdio_bus
->name
= "tg3 mdio bus";
1102 snprintf(tp
->mdio_bus
->id
, MII_BUS_ID_SIZE
, "%x",
1103 (tp
->pdev
->bus
->number
<< 8) | tp
->pdev
->devfn
);
1104 tp
->mdio_bus
->priv
= tp
;
1105 tp
->mdio_bus
->parent
= &tp
->pdev
->dev
;
1106 tp
->mdio_bus
->read
= &tg3_mdio_read
;
1107 tp
->mdio_bus
->write
= &tg3_mdio_write
;
1108 tp
->mdio_bus
->reset
= &tg3_mdio_reset
;
1109 tp
->mdio_bus
->phy_mask
= ~(1 << TG3_PHY_MII_ADDR
);
1110 tp
->mdio_bus
->irq
= &tp
->mdio_irq
[0];
1112 for (i
= 0; i
< PHY_MAX_ADDR
; i
++)
1113 tp
->mdio_bus
->irq
[i
] = PHY_POLL
;
1115 /* The bus registration will look for all the PHYs on the mdio bus.
1116 * Unfortunately, it does not ensure the PHY is powered up before
1117 * accessing the PHY ID registers. A chip reset is the
1118 * quickest way to bring the device back to an operational state..
1120 if (tg3_readphy(tp
, MII_BMCR
, ®
) || (reg
& BMCR_PDOWN
))
1123 i
= mdiobus_register(tp
->mdio_bus
);
1125 dev_warn(&tp
->pdev
->dev
, "mdiobus_reg failed (0x%x)\n", i
);
1126 mdiobus_free(tp
->mdio_bus
);
1130 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
1132 if (!phydev
|| !phydev
->drv
) {
1133 dev_warn(&tp
->pdev
->dev
, "No PHY devices\n");
1134 mdiobus_unregister(tp
->mdio_bus
);
1135 mdiobus_free(tp
->mdio_bus
);
1139 switch (phydev
->drv
->phy_id
& phydev
->drv
->phy_id_mask
) {
1140 case PHY_ID_BCM57780
:
1141 phydev
->interface
= PHY_INTERFACE_MODE_GMII
;
1142 phydev
->dev_flags
|= PHY_BRCM_AUTO_PWRDWN_ENABLE
;
1144 case PHY_ID_BCM50610
:
1145 case PHY_ID_BCM50610M
:
1146 phydev
->dev_flags
|= PHY_BRCM_CLEAR_RGMII_MODE
|
1147 PHY_BRCM_RX_REFCLK_UNUSED
|
1148 PHY_BRCM_DIS_TXCRXC_NOENRGY
|
1149 PHY_BRCM_AUTO_PWRDWN_ENABLE
;
1150 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_INBAND_DISABLE
)
1151 phydev
->dev_flags
|= PHY_BRCM_STD_IBND_DISABLE
;
1152 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_RX_EN
)
1153 phydev
->dev_flags
|= PHY_BRCM_EXT_IBND_RX_ENABLE
;
1154 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_TX_EN
)
1155 phydev
->dev_flags
|= PHY_BRCM_EXT_IBND_TX_ENABLE
;
1157 case PHY_ID_RTL8211C
:
1158 phydev
->interface
= PHY_INTERFACE_MODE_RGMII
;
1160 case PHY_ID_RTL8201E
:
1161 case PHY_ID_BCMAC131
:
1162 phydev
->interface
= PHY_INTERFACE_MODE_MII
;
1163 phydev
->dev_flags
|= PHY_BRCM_AUTO_PWRDWN_ENABLE
;
1164 tp
->tg3_flags3
|= TG3_FLG3_PHY_IS_FET
;
1168 tp
->tg3_flags3
|= TG3_FLG3_MDIOBUS_INITED
;
1170 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
1171 tg3_mdio_config_5785(tp
);
1176 static void tg3_mdio_fini(struct tg3
*tp
)
1178 if (tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_INITED
) {
1179 tp
->tg3_flags3
&= ~TG3_FLG3_MDIOBUS_INITED
;
1180 mdiobus_unregister(tp
->mdio_bus
);
1181 mdiobus_free(tp
->mdio_bus
);
1185 /* tp->lock is held. */
1186 static inline void tg3_generate_fw_event(struct tg3
*tp
)
1190 val
= tr32(GRC_RX_CPU_EVENT
);
1191 val
|= GRC_RX_CPU_DRIVER_EVENT
;
1192 tw32_f(GRC_RX_CPU_EVENT
, val
);
1194 tp
->last_event_jiffies
= jiffies
;
1197 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1199 /* tp->lock is held. */
1200 static void tg3_wait_for_event_ack(struct tg3
*tp
)
1203 unsigned int delay_cnt
;
1206 /* If enough time has passed, no wait is necessary. */
1207 time_remain
= (long)(tp
->last_event_jiffies
+ 1 +
1208 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC
)) -
1210 if (time_remain
< 0)
1213 /* Check if we can shorten the wait time. */
1214 delay_cnt
= jiffies_to_usecs(time_remain
);
1215 if (delay_cnt
> TG3_FW_EVENT_TIMEOUT_USEC
)
1216 delay_cnt
= TG3_FW_EVENT_TIMEOUT_USEC
;
1217 delay_cnt
= (delay_cnt
>> 3) + 1;
1219 for (i
= 0; i
< delay_cnt
; i
++) {
1220 if (!(tr32(GRC_RX_CPU_EVENT
) & GRC_RX_CPU_DRIVER_EVENT
))
1226 /* tp->lock is held. */
1227 static void tg3_ump_link_report(struct tg3
*tp
)
1232 if (!(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) ||
1233 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
1236 tg3_wait_for_event_ack(tp
);
1238 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_MBOX
, FWCMD_NICDRV_LINK_UPDATE
);
1240 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_LEN_MBOX
, 14);
1243 if (!tg3_readphy(tp
, MII_BMCR
, ®
))
1245 if (!tg3_readphy(tp
, MII_BMSR
, ®
))
1246 val
|= (reg
& 0xffff);
1247 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
, val
);
1250 if (!tg3_readphy(tp
, MII_ADVERTISE
, ®
))
1252 if (!tg3_readphy(tp
, MII_LPA
, ®
))
1253 val
|= (reg
& 0xffff);
1254 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
+ 4, val
);
1257 if (!(tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
)) {
1258 if (!tg3_readphy(tp
, MII_CTRL1000
, ®
))
1260 if (!tg3_readphy(tp
, MII_STAT1000
, ®
))
1261 val
|= (reg
& 0xffff);
1263 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
+ 8, val
);
1265 if (!tg3_readphy(tp
, MII_PHYADDR
, ®
))
1269 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
+ 12, val
);
1271 tg3_generate_fw_event(tp
);
1274 static void tg3_link_report(struct tg3
*tp
)
1276 if (!netif_carrier_ok(tp
->dev
)) {
1277 netif_info(tp
, link
, tp
->dev
, "Link is down\n");
1278 tg3_ump_link_report(tp
);
1279 } else if (netif_msg_link(tp
)) {
1280 netdev_info(tp
->dev
, "Link is up at %d Mbps, %s duplex\n",
1281 (tp
->link_config
.active_speed
== SPEED_1000
?
1283 (tp
->link_config
.active_speed
== SPEED_100
?
1285 (tp
->link_config
.active_duplex
== DUPLEX_FULL
?
1288 netdev_info(tp
->dev
, "Flow control is %s for TX and %s for RX\n",
1289 (tp
->link_config
.active_flowctrl
& FLOW_CTRL_TX
) ?
1291 (tp
->link_config
.active_flowctrl
& FLOW_CTRL_RX
) ?
1293 tg3_ump_link_report(tp
);
1297 static u16
tg3_advert_flowctrl_1000T(u8 flow_ctrl
)
1301 if ((flow_ctrl
& FLOW_CTRL_TX
) && (flow_ctrl
& FLOW_CTRL_RX
))
1302 miireg
= ADVERTISE_PAUSE_CAP
;
1303 else if (flow_ctrl
& FLOW_CTRL_TX
)
1304 miireg
= ADVERTISE_PAUSE_ASYM
;
1305 else if (flow_ctrl
& FLOW_CTRL_RX
)
1306 miireg
= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
1313 static u16
tg3_advert_flowctrl_1000X(u8 flow_ctrl
)
1317 if ((flow_ctrl
& FLOW_CTRL_TX
) && (flow_ctrl
& FLOW_CTRL_RX
))
1318 miireg
= ADVERTISE_1000XPAUSE
;
1319 else if (flow_ctrl
& FLOW_CTRL_TX
)
1320 miireg
= ADVERTISE_1000XPSE_ASYM
;
1321 else if (flow_ctrl
& FLOW_CTRL_RX
)
1322 miireg
= ADVERTISE_1000XPAUSE
| ADVERTISE_1000XPSE_ASYM
;
1329 static u8
tg3_resolve_flowctrl_1000X(u16 lcladv
, u16 rmtadv
)
1333 if (lcladv
& ADVERTISE_1000XPAUSE
) {
1334 if (lcladv
& ADVERTISE_1000XPSE_ASYM
) {
1335 if (rmtadv
& LPA_1000XPAUSE
)
1336 cap
= FLOW_CTRL_TX
| FLOW_CTRL_RX
;
1337 else if (rmtadv
& LPA_1000XPAUSE_ASYM
)
1340 if (rmtadv
& LPA_1000XPAUSE
)
1341 cap
= FLOW_CTRL_TX
| FLOW_CTRL_RX
;
1343 } else if (lcladv
& ADVERTISE_1000XPSE_ASYM
) {
1344 if ((rmtadv
& LPA_1000XPAUSE
) && (rmtadv
& LPA_1000XPAUSE_ASYM
))
1351 static void tg3_setup_flow_control(struct tg3
*tp
, u32 lcladv
, u32 rmtadv
)
1355 u32 old_rx_mode
= tp
->rx_mode
;
1356 u32 old_tx_mode
= tp
->tx_mode
;
1358 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
)
1359 autoneg
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
]->autoneg
;
1361 autoneg
= tp
->link_config
.autoneg
;
1363 if (autoneg
== AUTONEG_ENABLE
&&
1364 (tp
->tg3_flags
& TG3_FLAG_PAUSE_AUTONEG
)) {
1365 if (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
)
1366 flowctrl
= tg3_resolve_flowctrl_1000X(lcladv
, rmtadv
);
1368 flowctrl
= mii_resolve_flowctrl_fdx(lcladv
, rmtadv
);
1370 flowctrl
= tp
->link_config
.flowctrl
;
1372 tp
->link_config
.active_flowctrl
= flowctrl
;
1374 if (flowctrl
& FLOW_CTRL_RX
)
1375 tp
->rx_mode
|= RX_MODE_FLOW_CTRL_ENABLE
;
1377 tp
->rx_mode
&= ~RX_MODE_FLOW_CTRL_ENABLE
;
1379 if (old_rx_mode
!= tp
->rx_mode
)
1380 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
1382 if (flowctrl
& FLOW_CTRL_TX
)
1383 tp
->tx_mode
|= TX_MODE_FLOW_CTRL_ENABLE
;
1385 tp
->tx_mode
&= ~TX_MODE_FLOW_CTRL_ENABLE
;
1387 if (old_tx_mode
!= tp
->tx_mode
)
1388 tw32_f(MAC_TX_MODE
, tp
->tx_mode
);
1391 static void tg3_adjust_link(struct net_device
*dev
)
1393 u8 oldflowctrl
, linkmesg
= 0;
1394 u32 mac_mode
, lcl_adv
, rmt_adv
;
1395 struct tg3
*tp
= netdev_priv(dev
);
1396 struct phy_device
*phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
1398 spin_lock_bh(&tp
->lock
);
1400 mac_mode
= tp
->mac_mode
& ~(MAC_MODE_PORT_MODE_MASK
|
1401 MAC_MODE_HALF_DUPLEX
);
1403 oldflowctrl
= tp
->link_config
.active_flowctrl
;
1409 if (phydev
->speed
== SPEED_100
|| phydev
->speed
== SPEED_10
)
1410 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
1411 else if (phydev
->speed
== SPEED_1000
||
1412 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5785
)
1413 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
1415 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
1417 if (phydev
->duplex
== DUPLEX_HALF
)
1418 mac_mode
|= MAC_MODE_HALF_DUPLEX
;
1420 lcl_adv
= tg3_advert_flowctrl_1000T(
1421 tp
->link_config
.flowctrl
);
1424 rmt_adv
= LPA_PAUSE_CAP
;
1425 if (phydev
->asym_pause
)
1426 rmt_adv
|= LPA_PAUSE_ASYM
;
1429 tg3_setup_flow_control(tp
, lcl_adv
, rmt_adv
);
1431 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
1433 if (mac_mode
!= tp
->mac_mode
) {
1434 tp
->mac_mode
= mac_mode
;
1435 tw32_f(MAC_MODE
, tp
->mac_mode
);
1439 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
) {
1440 if (phydev
->speed
== SPEED_10
)
1442 MAC_MI_STAT_10MBPS_MODE
|
1443 MAC_MI_STAT_LNKSTAT_ATTN_ENAB
);
1445 tw32(MAC_MI_STAT
, MAC_MI_STAT_LNKSTAT_ATTN_ENAB
);
1448 if (phydev
->speed
== SPEED_1000
&& phydev
->duplex
== DUPLEX_HALF
)
1449 tw32(MAC_TX_LENGTHS
,
1450 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
1451 (6 << TX_LENGTHS_IPG_SHIFT
) |
1452 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT
)));
1454 tw32(MAC_TX_LENGTHS
,
1455 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
1456 (6 << TX_LENGTHS_IPG_SHIFT
) |
1457 (32 << TX_LENGTHS_SLOT_TIME_SHIFT
)));
1459 if ((phydev
->link
&& tp
->link_config
.active_speed
== SPEED_INVALID
) ||
1460 (!phydev
->link
&& tp
->link_config
.active_speed
!= SPEED_INVALID
) ||
1461 phydev
->speed
!= tp
->link_config
.active_speed
||
1462 phydev
->duplex
!= tp
->link_config
.active_duplex
||
1463 oldflowctrl
!= tp
->link_config
.active_flowctrl
)
1466 tp
->link_config
.active_speed
= phydev
->speed
;
1467 tp
->link_config
.active_duplex
= phydev
->duplex
;
1469 spin_unlock_bh(&tp
->lock
);
1472 tg3_link_report(tp
);
1475 static int tg3_phy_init(struct tg3
*tp
)
1477 struct phy_device
*phydev
;
1479 if (tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
)
1482 /* Bring the PHY back to a known state. */
1485 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
1487 /* Attach the MAC to the PHY. */
1488 phydev
= phy_connect(tp
->dev
, dev_name(&phydev
->dev
), tg3_adjust_link
,
1489 phydev
->dev_flags
, phydev
->interface
);
1490 if (IS_ERR(phydev
)) {
1491 dev_err(&tp
->pdev
->dev
, "Could not attach to PHY\n");
1492 return PTR_ERR(phydev
);
1495 /* Mask with MAC supported features. */
1496 switch (phydev
->interface
) {
1497 case PHY_INTERFACE_MODE_GMII
:
1498 case PHY_INTERFACE_MODE_RGMII
:
1499 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)) {
1500 phydev
->supported
&= (PHY_GBIT_FEATURES
|
1502 SUPPORTED_Asym_Pause
);
1506 case PHY_INTERFACE_MODE_MII
:
1507 phydev
->supported
&= (PHY_BASIC_FEATURES
|
1509 SUPPORTED_Asym_Pause
);
1512 phy_disconnect(tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
]);
1516 tp
->tg3_flags3
|= TG3_FLG3_PHY_CONNECTED
;
1518 phydev
->advertising
= phydev
->supported
;
1523 static void tg3_phy_start(struct tg3
*tp
)
1525 struct phy_device
*phydev
;
1527 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
1530 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
1532 if (tp
->link_config
.phy_is_low_power
) {
1533 tp
->link_config
.phy_is_low_power
= 0;
1534 phydev
->speed
= tp
->link_config
.orig_speed
;
1535 phydev
->duplex
= tp
->link_config
.orig_duplex
;
1536 phydev
->autoneg
= tp
->link_config
.orig_autoneg
;
1537 phydev
->advertising
= tp
->link_config
.orig_advertising
;
1542 phy_start_aneg(phydev
);
1545 static void tg3_phy_stop(struct tg3
*tp
)
1547 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
1550 phy_stop(tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
]);
1553 static void tg3_phy_fini(struct tg3
*tp
)
1555 if (tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
) {
1556 phy_disconnect(tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
]);
1557 tp
->tg3_flags3
&= ~TG3_FLG3_PHY_CONNECTED
;
1561 static void tg3_phydsp_write(struct tg3
*tp
, u32 reg
, u32 val
)
1563 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, reg
);
1564 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, val
);
1567 static void tg3_phy_fet_toggle_apd(struct tg3
*tp
, bool enable
)
1571 if (!tg3_readphy(tp
, MII_TG3_FET_TEST
, &phytest
)) {
1574 tg3_writephy(tp
, MII_TG3_FET_TEST
,
1575 phytest
| MII_TG3_FET_SHADOW_EN
);
1576 if (!tg3_readphy(tp
, MII_TG3_FET_SHDW_AUXSTAT2
, &phy
)) {
1578 phy
|= MII_TG3_FET_SHDW_AUXSTAT2_APD
;
1580 phy
&= ~MII_TG3_FET_SHDW_AUXSTAT2_APD
;
1581 tg3_writephy(tp
, MII_TG3_FET_SHDW_AUXSTAT2
, phy
);
1583 tg3_writephy(tp
, MII_TG3_FET_TEST
, phytest
);
1587 static void tg3_phy_toggle_apd(struct tg3
*tp
, bool enable
)
1591 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) ||
1592 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
&&
1593 (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
)))
1596 if (tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
) {
1597 tg3_phy_fet_toggle_apd(tp
, enable
);
1601 reg
= MII_TG3_MISC_SHDW_WREN
|
1602 MII_TG3_MISC_SHDW_SCR5_SEL
|
1603 MII_TG3_MISC_SHDW_SCR5_LPED
|
1604 MII_TG3_MISC_SHDW_SCR5_DLPTLM
|
1605 MII_TG3_MISC_SHDW_SCR5_SDTL
|
1606 MII_TG3_MISC_SHDW_SCR5_C125OE
;
1607 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5784
|| !enable
)
1608 reg
|= MII_TG3_MISC_SHDW_SCR5_DLLAPD
;
1610 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, reg
);
1613 reg
= MII_TG3_MISC_SHDW_WREN
|
1614 MII_TG3_MISC_SHDW_APD_SEL
|
1615 MII_TG3_MISC_SHDW_APD_WKTM_84MS
;
1617 reg
|= MII_TG3_MISC_SHDW_APD_ENABLE
;
1619 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, reg
);
1622 static void tg3_phy_toggle_automdix(struct tg3
*tp
, int enable
)
1626 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) ||
1627 (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
))
1630 if (tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
) {
1633 if (!tg3_readphy(tp
, MII_TG3_FET_TEST
, &ephy
)) {
1634 u32 reg
= MII_TG3_FET_SHDW_MISCCTRL
;
1636 tg3_writephy(tp
, MII_TG3_FET_TEST
,
1637 ephy
| MII_TG3_FET_SHADOW_EN
);
1638 if (!tg3_readphy(tp
, reg
, &phy
)) {
1640 phy
|= MII_TG3_FET_SHDW_MISCCTRL_MDIX
;
1642 phy
&= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX
;
1643 tg3_writephy(tp
, reg
, phy
);
1645 tg3_writephy(tp
, MII_TG3_FET_TEST
, ephy
);
1648 phy
= MII_TG3_AUXCTL_MISC_RDSEL_MISC
|
1649 MII_TG3_AUXCTL_SHDWSEL_MISC
;
1650 if (!tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy
) &&
1651 !tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &phy
)) {
1653 phy
|= MII_TG3_AUXCTL_MISC_FORCE_AMDIX
;
1655 phy
&= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX
;
1656 phy
|= MII_TG3_AUXCTL_MISC_WREN
;
1657 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy
);
1662 static void tg3_phy_set_wirespeed(struct tg3
*tp
)
1666 if (tp
->tg3_flags2
& TG3_FLG2_NO_ETH_WIRE_SPEED
)
1669 if (!tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x7007) &&
1670 !tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &val
))
1671 tg3_writephy(tp
, MII_TG3_AUX_CTRL
,
1672 (val
| (1 << 15) | (1 << 4)));
1675 static void tg3_phy_apply_otp(struct tg3
*tp
)
1684 /* Enable SM_DSP clock and tx 6dB coding. */
1685 phy
= MII_TG3_AUXCTL_SHDWSEL_AUXCTL
|
1686 MII_TG3_AUXCTL_ACTL_SMDSP_ENA
|
1687 MII_TG3_AUXCTL_ACTL_TX_6DB
;
1688 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy
);
1690 phy
= ((otp
& TG3_OTP_AGCTGT_MASK
) >> TG3_OTP_AGCTGT_SHIFT
);
1691 phy
|= MII_TG3_DSP_TAP1_AGCTGT_DFLT
;
1692 tg3_phydsp_write(tp
, MII_TG3_DSP_TAP1
, phy
);
1694 phy
= ((otp
& TG3_OTP_HPFFLTR_MASK
) >> TG3_OTP_HPFFLTR_SHIFT
) |
1695 ((otp
& TG3_OTP_HPFOVER_MASK
) >> TG3_OTP_HPFOVER_SHIFT
);
1696 tg3_phydsp_write(tp
, MII_TG3_DSP_AADJ1CH0
, phy
);
1698 phy
= ((otp
& TG3_OTP_LPFDIS_MASK
) >> TG3_OTP_LPFDIS_SHIFT
);
1699 phy
|= MII_TG3_DSP_AADJ1CH3_ADCCKADJ
;
1700 tg3_phydsp_write(tp
, MII_TG3_DSP_AADJ1CH3
, phy
);
1702 phy
= ((otp
& TG3_OTP_VDAC_MASK
) >> TG3_OTP_VDAC_SHIFT
);
1703 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP75
, phy
);
1705 phy
= ((otp
& TG3_OTP_10BTAMP_MASK
) >> TG3_OTP_10BTAMP_SHIFT
);
1706 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP96
, phy
);
1708 phy
= ((otp
& TG3_OTP_ROFF_MASK
) >> TG3_OTP_ROFF_SHIFT
) |
1709 ((otp
& TG3_OTP_RCOFF_MASK
) >> TG3_OTP_RCOFF_SHIFT
);
1710 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP97
, phy
);
1712 /* Turn off SM_DSP clock. */
1713 phy
= MII_TG3_AUXCTL_SHDWSEL_AUXCTL
|
1714 MII_TG3_AUXCTL_ACTL_TX_6DB
;
1715 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy
);
1718 static int tg3_wait_macro_done(struct tg3
*tp
)
1725 if (!tg3_readphy(tp
, 0x16, &tmp32
)) {
1726 if ((tmp32
& 0x1000) == 0)
1736 static int tg3_phy_write_and_check_testpat(struct tg3
*tp
, int *resetp
)
1738 static const u32 test_pat
[4][6] = {
1739 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1740 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1741 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1742 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1746 for (chan
= 0; chan
< 4; chan
++) {
1749 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
1750 (chan
* 0x2000) | 0x0200);
1751 tg3_writephy(tp
, 0x16, 0x0002);
1753 for (i
= 0; i
< 6; i
++)
1754 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
,
1757 tg3_writephy(tp
, 0x16, 0x0202);
1758 if (tg3_wait_macro_done(tp
)) {
1763 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
1764 (chan
* 0x2000) | 0x0200);
1765 tg3_writephy(tp
, 0x16, 0x0082);
1766 if (tg3_wait_macro_done(tp
)) {
1771 tg3_writephy(tp
, 0x16, 0x0802);
1772 if (tg3_wait_macro_done(tp
)) {
1777 for (i
= 0; i
< 6; i
+= 2) {
1780 if (tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &low
) ||
1781 tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &high
) ||
1782 tg3_wait_macro_done(tp
)) {
1788 if (low
!= test_pat
[chan
][i
] ||
1789 high
!= test_pat
[chan
][i
+1]) {
1790 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x000b);
1791 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x4001);
1792 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x4005);
1802 static int tg3_phy_reset_chanpat(struct tg3
*tp
)
1806 for (chan
= 0; chan
< 4; chan
++) {
1809 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
1810 (chan
* 0x2000) | 0x0200);
1811 tg3_writephy(tp
, 0x16, 0x0002);
1812 for (i
= 0; i
< 6; i
++)
1813 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x000);
1814 tg3_writephy(tp
, 0x16, 0x0202);
1815 if (tg3_wait_macro_done(tp
))
1822 static int tg3_phy_reset_5703_4_5(struct tg3
*tp
)
1824 u32 reg32
, phy9_orig
;
1825 int retries
, do_phy_reset
, err
;
1831 err
= tg3_bmcr_reset(tp
);
1837 /* Disable transmitter and interrupt. */
1838 if (tg3_readphy(tp
, MII_TG3_EXT_CTRL
, ®32
))
1842 tg3_writephy(tp
, MII_TG3_EXT_CTRL
, reg32
);
1844 /* Set full-duplex, 1000 mbps. */
1845 tg3_writephy(tp
, MII_BMCR
,
1846 BMCR_FULLDPLX
| TG3_BMCR_SPEED1000
);
1848 /* Set to master mode. */
1849 if (tg3_readphy(tp
, MII_TG3_CTRL
, &phy9_orig
))
1852 tg3_writephy(tp
, MII_TG3_CTRL
,
1853 (MII_TG3_CTRL_AS_MASTER
|
1854 MII_TG3_CTRL_ENABLE_AS_MASTER
));
1856 /* Enable SM_DSP_CLOCK and 6dB. */
1857 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
1859 /* Block the PHY control access. */
1860 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8005);
1861 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0800);
1863 err
= tg3_phy_write_and_check_testpat(tp
, &do_phy_reset
);
1866 } while (--retries
);
1868 err
= tg3_phy_reset_chanpat(tp
);
1872 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8005);
1873 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0000);
1875 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8200);
1876 tg3_writephy(tp
, 0x16, 0x0000);
1878 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
1879 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
1880 /* Set Extended packet length bit for jumbo frames */
1881 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4400);
1883 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
1886 tg3_writephy(tp
, MII_TG3_CTRL
, phy9_orig
);
1888 if (!tg3_readphy(tp
, MII_TG3_EXT_CTRL
, ®32
)) {
1890 tg3_writephy(tp
, MII_TG3_EXT_CTRL
, reg32
);
1897 /* This will reset the tigon3 PHY if there is no valid
1898 * link unless the FORCE argument is non-zero.
1900 static int tg3_phy_reset(struct tg3
*tp
)
1906 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
1909 val
= tr32(GRC_MISC_CFG
);
1910 tw32_f(GRC_MISC_CFG
, val
& ~GRC_MISC_CFG_EPHY_IDDQ
);
1913 err
= tg3_readphy(tp
, MII_BMSR
, &phy_status
);
1914 err
|= tg3_readphy(tp
, MII_BMSR
, &phy_status
);
1918 if (netif_running(tp
->dev
) && netif_carrier_ok(tp
->dev
)) {
1919 netif_carrier_off(tp
->dev
);
1920 tg3_link_report(tp
);
1923 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
1924 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
1925 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
1926 err
= tg3_phy_reset_5703_4_5(tp
);
1933 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
1934 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
) {
1935 cpmuctrl
= tr32(TG3_CPMU_CTRL
);
1936 if (cpmuctrl
& CPMU_CTRL_GPHY_10MB_RXONLY
)
1938 cpmuctrl
& ~CPMU_CTRL_GPHY_10MB_RXONLY
);
1941 err
= tg3_bmcr_reset(tp
);
1945 if (cpmuctrl
& CPMU_CTRL_GPHY_10MB_RXONLY
) {
1948 phy
= MII_TG3_DSP_EXP8_AEDW
| MII_TG3_DSP_EXP8_REJ2MHz
;
1949 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP8
, phy
);
1951 tw32(TG3_CPMU_CTRL
, cpmuctrl
);
1954 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
||
1955 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5761_AX
) {
1958 val
= tr32(TG3_CPMU_LSPD_1000MB_CLK
);
1959 if ((val
& CPMU_LSPD_1000MB_MACCLK_MASK
) ==
1960 CPMU_LSPD_1000MB_MACCLK_12_5
) {
1961 val
&= ~CPMU_LSPD_1000MB_MACCLK_MASK
;
1963 tw32_f(TG3_CPMU_LSPD_1000MB_CLK
, val
);
1967 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
&&
1968 (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
))
1971 tg3_phy_apply_otp(tp
);
1973 if (tp
->tg3_flags3
& TG3_FLG3_PHY_ENABLE_APD
)
1974 tg3_phy_toggle_apd(tp
, true);
1976 tg3_phy_toggle_apd(tp
, false);
1979 if (tp
->tg3_flags2
& TG3_FLG2_PHY_ADC_BUG
) {
1980 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
1981 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x201f);
1982 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x2aaa);
1983 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x000a);
1984 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0323);
1985 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
1987 if (tp
->tg3_flags2
& TG3_FLG2_PHY_5704_A0_BUG
) {
1988 tg3_writephy(tp
, 0x1c, 0x8d68);
1989 tg3_writephy(tp
, 0x1c, 0x8d68);
1991 if (tp
->tg3_flags2
& TG3_FLG2_PHY_BER_BUG
) {
1992 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
1993 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x000a);
1994 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x310b);
1995 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x201f);
1996 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x9506);
1997 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x401f);
1998 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x14e2);
1999 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
2000 } else if (tp
->tg3_flags2
& TG3_FLG2_PHY_JITTER_BUG
) {
2001 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
2002 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x000a);
2003 if (tp
->tg3_flags2
& TG3_FLG2_PHY_ADJUST_TRIM
) {
2004 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x110b);
2005 tg3_writephy(tp
, MII_TG3_TEST1
,
2006 MII_TG3_TEST1_TRIM_EN
| 0x4);
2008 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x010b);
2009 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
2011 /* Set Extended packet length bit (bit 14) on all chips that */
2012 /* support jumbo frames */
2013 if ((tp
->phy_id
& TG3_PHY_ID_MASK
) == TG3_PHY_ID_BCM5401
) {
2014 /* Cannot do read-modify-write on 5401 */
2015 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4c20);
2016 } else if (tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) {
2019 /* Set bit 14 with read-modify-write to preserve other bits */
2020 if (!tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0007) &&
2021 !tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &phy_reg
))
2022 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy_reg
| 0x4000);
2025 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2026 * jumbo frames transmission.
2028 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) {
2031 if (!tg3_readphy(tp
, MII_TG3_EXT_CTRL
, &phy_reg
))
2032 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
2033 phy_reg
| MII_TG3_EXT_CTRL_FIFO_ELASTIC
);
2036 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
2037 /* adjust output voltage */
2038 tg3_writephy(tp
, MII_TG3_FET_PTEST
, 0x12);
2041 tg3_phy_toggle_automdix(tp
, 1);
2042 tg3_phy_set_wirespeed(tp
);
2046 static void tg3_frob_aux_power(struct tg3
*tp
)
2048 struct tg3
*tp_peer
= tp
;
2050 /* The GPIOs do something completely different on 57765. */
2051 if ((tp
->tg3_flags2
& TG3_FLG2_IS_NIC
) == 0 ||
2052 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
2055 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
2056 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
||
2057 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
) {
2058 struct net_device
*dev_peer
;
2060 dev_peer
= pci_get_drvdata(tp
->pdev_peer
);
2061 /* remove_one() may have been run on the peer. */
2065 tp_peer
= netdev_priv(dev_peer
);
2068 if ((tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
) != 0 ||
2069 (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) != 0 ||
2070 (tp_peer
->tg3_flags
& TG3_FLAG_WOL_ENABLE
) != 0 ||
2071 (tp_peer
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) != 0) {
2072 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2073 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
2074 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2075 (GRC_LCLCTRL_GPIO_OE0
|
2076 GRC_LCLCTRL_GPIO_OE1
|
2077 GRC_LCLCTRL_GPIO_OE2
|
2078 GRC_LCLCTRL_GPIO_OUTPUT0
|
2079 GRC_LCLCTRL_GPIO_OUTPUT1
),
2081 } else if (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5761
||
2082 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5761S
) {
2083 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2084 u32 grc_local_ctrl
= GRC_LCLCTRL_GPIO_OE0
|
2085 GRC_LCLCTRL_GPIO_OE1
|
2086 GRC_LCLCTRL_GPIO_OE2
|
2087 GRC_LCLCTRL_GPIO_OUTPUT0
|
2088 GRC_LCLCTRL_GPIO_OUTPUT1
|
2090 tw32_wait_f(GRC_LOCAL_CTRL
, grc_local_ctrl
, 100);
2092 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OUTPUT2
;
2093 tw32_wait_f(GRC_LOCAL_CTRL
, grc_local_ctrl
, 100);
2095 grc_local_ctrl
&= ~GRC_LCLCTRL_GPIO_OUTPUT0
;
2096 tw32_wait_f(GRC_LOCAL_CTRL
, grc_local_ctrl
, 100);
2099 u32 grc_local_ctrl
= 0;
2101 if (tp_peer
!= tp
&&
2102 (tp_peer
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
) != 0)
2105 /* Workaround to prevent overdrawing Amps. */
2106 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
2108 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE3
;
2109 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2110 grc_local_ctrl
, 100);
2113 /* On 5753 and variants, GPIO2 cannot be used. */
2114 no_gpio2
= tp
->nic_sram_data_cfg
&
2115 NIC_SRAM_DATA_CFG_NO_GPIO2
;
2117 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE0
|
2118 GRC_LCLCTRL_GPIO_OE1
|
2119 GRC_LCLCTRL_GPIO_OE2
|
2120 GRC_LCLCTRL_GPIO_OUTPUT1
|
2121 GRC_LCLCTRL_GPIO_OUTPUT2
;
2123 grc_local_ctrl
&= ~(GRC_LCLCTRL_GPIO_OE2
|
2124 GRC_LCLCTRL_GPIO_OUTPUT2
);
2126 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2127 grc_local_ctrl
, 100);
2129 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OUTPUT0
;
2131 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2132 grc_local_ctrl
, 100);
2135 grc_local_ctrl
&= ~GRC_LCLCTRL_GPIO_OUTPUT2
;
2136 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2137 grc_local_ctrl
, 100);
2141 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
2142 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
) {
2143 if (tp_peer
!= tp
&&
2144 (tp_peer
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
) != 0)
2147 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2148 (GRC_LCLCTRL_GPIO_OE1
|
2149 GRC_LCLCTRL_GPIO_OUTPUT1
), 100);
2151 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2152 GRC_LCLCTRL_GPIO_OE1
, 100);
2154 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2155 (GRC_LCLCTRL_GPIO_OE1
|
2156 GRC_LCLCTRL_GPIO_OUTPUT1
), 100);
2161 static int tg3_5700_link_polarity(struct tg3
*tp
, u32 speed
)
2163 if (tp
->led_ctrl
== LED_CTRL_MODE_PHY_2
)
2165 else if ((tp
->phy_id
& TG3_PHY_ID_MASK
) == TG3_PHY_ID_BCM5411
) {
2166 if (speed
!= SPEED_10
)
2168 } else if (speed
== SPEED_10
)
2174 static int tg3_setup_phy(struct tg3
*, int);
2176 #define RESET_KIND_SHUTDOWN 0
2177 #define RESET_KIND_INIT 1
2178 #define RESET_KIND_SUSPEND 2
2180 static void tg3_write_sig_post_reset(struct tg3
*, int);
2181 static int tg3_halt_cpu(struct tg3
*, u32
);
2183 static void tg3_power_down_phy(struct tg3
*tp
, bool do_low_power
)
2187 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
2188 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
2189 u32 sg_dig_ctrl
= tr32(SG_DIG_CTRL
);
2190 u32 serdes_cfg
= tr32(MAC_SERDES_CFG
);
2193 SG_DIG_USING_HW_AUTONEG
| SG_DIG_SOFT_RESET
;
2194 tw32(SG_DIG_CTRL
, sg_dig_ctrl
);
2195 tw32(MAC_SERDES_CFG
, serdes_cfg
| (1 << 15));
2200 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
2202 val
= tr32(GRC_MISC_CFG
);
2203 tw32_f(GRC_MISC_CFG
, val
| GRC_MISC_CFG_EPHY_IDDQ
);
2206 } else if (tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
) {
2208 if (!tg3_readphy(tp
, MII_TG3_FET_TEST
, &phytest
)) {
2211 tg3_writephy(tp
, MII_ADVERTISE
, 0);
2212 tg3_writephy(tp
, MII_BMCR
,
2213 BMCR_ANENABLE
| BMCR_ANRESTART
);
2215 tg3_writephy(tp
, MII_TG3_FET_TEST
,
2216 phytest
| MII_TG3_FET_SHADOW_EN
);
2217 if (!tg3_readphy(tp
, MII_TG3_FET_SHDW_AUXMODE4
, &phy
)) {
2218 phy
|= MII_TG3_FET_SHDW_AUXMODE4_SBPD
;
2220 MII_TG3_FET_SHDW_AUXMODE4
,
2223 tg3_writephy(tp
, MII_TG3_FET_TEST
, phytest
);
2226 } else if (do_low_power
) {
2227 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
2228 MII_TG3_EXT_CTRL_FORCE_LED_OFF
);
2230 tg3_writephy(tp
, MII_TG3_AUX_CTRL
,
2231 MII_TG3_AUXCTL_SHDWSEL_PWRCTL
|
2232 MII_TG3_AUXCTL_PCTL_100TX_LPWR
|
2233 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE
|
2234 MII_TG3_AUXCTL_PCTL_VREG_11V
);
2237 /* The PHY should not be powered down on some chips because
2240 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2241 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
2242 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5780
&&
2243 (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
)))
2246 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
||
2247 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5761_AX
) {
2248 val
= tr32(TG3_CPMU_LSPD_1000MB_CLK
);
2249 val
&= ~CPMU_LSPD_1000MB_MACCLK_MASK
;
2250 val
|= CPMU_LSPD_1000MB_MACCLK_12_5
;
2251 tw32_f(TG3_CPMU_LSPD_1000MB_CLK
, val
);
2254 tg3_writephy(tp
, MII_BMCR
, BMCR_PDOWN
);
2257 /* tp->lock is held. */
2258 static int tg3_nvram_lock(struct tg3
*tp
)
2260 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
) {
2263 if (tp
->nvram_lock_cnt
== 0) {
2264 tw32(NVRAM_SWARB
, SWARB_REQ_SET1
);
2265 for (i
= 0; i
< 8000; i
++) {
2266 if (tr32(NVRAM_SWARB
) & SWARB_GNT1
)
2271 tw32(NVRAM_SWARB
, SWARB_REQ_CLR1
);
2275 tp
->nvram_lock_cnt
++;
2280 /* tp->lock is held. */
2281 static void tg3_nvram_unlock(struct tg3
*tp
)
2283 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
) {
2284 if (tp
->nvram_lock_cnt
> 0)
2285 tp
->nvram_lock_cnt
--;
2286 if (tp
->nvram_lock_cnt
== 0)
2287 tw32_f(NVRAM_SWARB
, SWARB_REQ_CLR1
);
2291 /* tp->lock is held. */
2292 static void tg3_enable_nvram_access(struct tg3
*tp
)
2294 if ((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
2295 !(tp
->tg3_flags3
& TG3_FLG3_PROTECTED_NVRAM
)) {
2296 u32 nvaccess
= tr32(NVRAM_ACCESS
);
2298 tw32(NVRAM_ACCESS
, nvaccess
| ACCESS_ENABLE
);
2302 /* tp->lock is held. */
2303 static void tg3_disable_nvram_access(struct tg3
*tp
)
2305 if ((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
2306 !(tp
->tg3_flags3
& TG3_FLG3_PROTECTED_NVRAM
)) {
2307 u32 nvaccess
= tr32(NVRAM_ACCESS
);
2309 tw32(NVRAM_ACCESS
, nvaccess
& ~ACCESS_ENABLE
);
2313 static int tg3_nvram_read_using_eeprom(struct tg3
*tp
,
2314 u32 offset
, u32
*val
)
2319 if (offset
> EEPROM_ADDR_ADDR_MASK
|| (offset
% 4) != 0)
2322 tmp
= tr32(GRC_EEPROM_ADDR
) & ~(EEPROM_ADDR_ADDR_MASK
|
2323 EEPROM_ADDR_DEVID_MASK
|
2325 tw32(GRC_EEPROM_ADDR
,
2327 (0 << EEPROM_ADDR_DEVID_SHIFT
) |
2328 ((offset
<< EEPROM_ADDR_ADDR_SHIFT
) &
2329 EEPROM_ADDR_ADDR_MASK
) |
2330 EEPROM_ADDR_READ
| EEPROM_ADDR_START
);
2332 for (i
= 0; i
< 1000; i
++) {
2333 tmp
= tr32(GRC_EEPROM_ADDR
);
2335 if (tmp
& EEPROM_ADDR_COMPLETE
)
2339 if (!(tmp
& EEPROM_ADDR_COMPLETE
))
2342 tmp
= tr32(GRC_EEPROM_DATA
);
2345 * The data will always be opposite the native endian
2346 * format. Perform a blind byteswap to compensate.
2353 #define NVRAM_CMD_TIMEOUT 10000
2355 static int tg3_nvram_exec_cmd(struct tg3
*tp
, u32 nvram_cmd
)
2359 tw32(NVRAM_CMD
, nvram_cmd
);
2360 for (i
= 0; i
< NVRAM_CMD_TIMEOUT
; i
++) {
2362 if (tr32(NVRAM_CMD
) & NVRAM_CMD_DONE
) {
2368 if (i
== NVRAM_CMD_TIMEOUT
)
2374 static u32
tg3_nvram_phys_addr(struct tg3
*tp
, u32 addr
)
2376 if ((tp
->tg3_flags
& TG3_FLAG_NVRAM
) &&
2377 (tp
->tg3_flags
& TG3_FLAG_NVRAM_BUFFERED
) &&
2378 (tp
->tg3_flags2
& TG3_FLG2_FLASH
) &&
2379 !(tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM_ADDR_TRANS
) &&
2380 (tp
->nvram_jedecnum
== JEDEC_ATMEL
))
2382 addr
= ((addr
/ tp
->nvram_pagesize
) <<
2383 ATMEL_AT45DB0X1B_PAGE_POS
) +
2384 (addr
% tp
->nvram_pagesize
);
2389 static u32
tg3_nvram_logical_addr(struct tg3
*tp
, u32 addr
)
2391 if ((tp
->tg3_flags
& TG3_FLAG_NVRAM
) &&
2392 (tp
->tg3_flags
& TG3_FLAG_NVRAM_BUFFERED
) &&
2393 (tp
->tg3_flags2
& TG3_FLG2_FLASH
) &&
2394 !(tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM_ADDR_TRANS
) &&
2395 (tp
->nvram_jedecnum
== JEDEC_ATMEL
))
2397 addr
= ((addr
>> ATMEL_AT45DB0X1B_PAGE_POS
) *
2398 tp
->nvram_pagesize
) +
2399 (addr
& ((1 << ATMEL_AT45DB0X1B_PAGE_POS
) - 1));
2404 /* NOTE: Data read in from NVRAM is byteswapped according to
2405 * the byteswapping settings for all other register accesses.
2406 * tg3 devices are BE devices, so on a BE machine, the data
2407 * returned will be exactly as it is seen in NVRAM. On a LE
2408 * machine, the 32-bit value will be byteswapped.
2410 static int tg3_nvram_read(struct tg3
*tp
, u32 offset
, u32
*val
)
2414 if (!(tp
->tg3_flags
& TG3_FLAG_NVRAM
))
2415 return tg3_nvram_read_using_eeprom(tp
, offset
, val
);
2417 offset
= tg3_nvram_phys_addr(tp
, offset
);
2419 if (offset
> NVRAM_ADDR_MSK
)
2422 ret
= tg3_nvram_lock(tp
);
2426 tg3_enable_nvram_access(tp
);
2428 tw32(NVRAM_ADDR
, offset
);
2429 ret
= tg3_nvram_exec_cmd(tp
, NVRAM_CMD_RD
| NVRAM_CMD_GO
|
2430 NVRAM_CMD_FIRST
| NVRAM_CMD_LAST
| NVRAM_CMD_DONE
);
2433 *val
= tr32(NVRAM_RDDATA
);
2435 tg3_disable_nvram_access(tp
);
2437 tg3_nvram_unlock(tp
);
2442 /* Ensures NVRAM data is in bytestream format. */
2443 static int tg3_nvram_read_be32(struct tg3
*tp
, u32 offset
, __be32
*val
)
2446 int res
= tg3_nvram_read(tp
, offset
, &v
);
2448 *val
= cpu_to_be32(v
);
2452 /* tp->lock is held. */
2453 static void __tg3_set_mac_addr(struct tg3
*tp
, int skip_mac_1
)
2455 u32 addr_high
, addr_low
;
2458 addr_high
= ((tp
->dev
->dev_addr
[0] << 8) |
2459 tp
->dev
->dev_addr
[1]);
2460 addr_low
= ((tp
->dev
->dev_addr
[2] << 24) |
2461 (tp
->dev
->dev_addr
[3] << 16) |
2462 (tp
->dev
->dev_addr
[4] << 8) |
2463 (tp
->dev
->dev_addr
[5] << 0));
2464 for (i
= 0; i
< 4; i
++) {
2465 if (i
== 1 && skip_mac_1
)
2467 tw32(MAC_ADDR_0_HIGH
+ (i
* 8), addr_high
);
2468 tw32(MAC_ADDR_0_LOW
+ (i
* 8), addr_low
);
2471 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
2472 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
2473 for (i
= 0; i
< 12; i
++) {
2474 tw32(MAC_EXTADDR_0_HIGH
+ (i
* 8), addr_high
);
2475 tw32(MAC_EXTADDR_0_LOW
+ (i
* 8), addr_low
);
2479 addr_high
= (tp
->dev
->dev_addr
[0] +
2480 tp
->dev
->dev_addr
[1] +
2481 tp
->dev
->dev_addr
[2] +
2482 tp
->dev
->dev_addr
[3] +
2483 tp
->dev
->dev_addr
[4] +
2484 tp
->dev
->dev_addr
[5]) &
2485 TX_BACKOFF_SEED_MASK
;
2486 tw32(MAC_TX_BACKOFF_SEED
, addr_high
);
2489 static int tg3_set_power_state(struct tg3
*tp
, pci_power_t state
)
2492 bool device_should_wake
, do_low_power
;
2494 /* Make sure register accesses (indirect or otherwise)
2495 * will function correctly.
2497 pci_write_config_dword(tp
->pdev
,
2498 TG3PCI_MISC_HOST_CTRL
,
2499 tp
->misc_host_ctrl
);
2503 pci_enable_wake(tp
->pdev
, state
, false);
2504 pci_set_power_state(tp
->pdev
, PCI_D0
);
2506 /* Switch out of Vaux if it is a NIC */
2507 if (tp
->tg3_flags2
& TG3_FLG2_IS_NIC
)
2508 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
, 100);
2518 netdev_err(tp
->dev
, "Invalid power state (D%d) requested\n",
2523 /* Restore the CLKREQ setting. */
2524 if (tp
->tg3_flags3
& TG3_FLG3_CLKREQ_BUG
) {
2527 pci_read_config_word(tp
->pdev
,
2528 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
2530 lnkctl
|= PCI_EXP_LNKCTL_CLKREQ_EN
;
2531 pci_write_config_word(tp
->pdev
,
2532 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
2536 misc_host_ctrl
= tr32(TG3PCI_MISC_HOST_CTRL
);
2537 tw32(TG3PCI_MISC_HOST_CTRL
,
2538 misc_host_ctrl
| MISC_HOST_CTRL_MASK_PCI_INT
);
2540 device_should_wake
= pci_pme_capable(tp
->pdev
, state
) &&
2541 device_may_wakeup(&tp
->pdev
->dev
) &&
2542 (tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
);
2544 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
2545 do_low_power
= false;
2546 if ((tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
) &&
2547 !tp
->link_config
.phy_is_low_power
) {
2548 struct phy_device
*phydev
;
2549 u32 phyid
, advertising
;
2551 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
2553 tp
->link_config
.phy_is_low_power
= 1;
2555 tp
->link_config
.orig_speed
= phydev
->speed
;
2556 tp
->link_config
.orig_duplex
= phydev
->duplex
;
2557 tp
->link_config
.orig_autoneg
= phydev
->autoneg
;
2558 tp
->link_config
.orig_advertising
= phydev
->advertising
;
2560 advertising
= ADVERTISED_TP
|
2562 ADVERTISED_Autoneg
|
2563 ADVERTISED_10baseT_Half
;
2565 if ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) ||
2566 device_should_wake
) {
2567 if (tp
->tg3_flags
& TG3_FLAG_WOL_SPEED_100MB
)
2569 ADVERTISED_100baseT_Half
|
2570 ADVERTISED_100baseT_Full
|
2571 ADVERTISED_10baseT_Full
;
2573 advertising
|= ADVERTISED_10baseT_Full
;
2576 phydev
->advertising
= advertising
;
2578 phy_start_aneg(phydev
);
2580 phyid
= phydev
->drv
->phy_id
& phydev
->drv
->phy_id_mask
;
2581 if (phyid
!= PHY_ID_BCMAC131
) {
2582 phyid
&= PHY_BCM_OUI_MASK
;
2583 if (phyid
== PHY_BCM_OUI_1
||
2584 phyid
== PHY_BCM_OUI_2
||
2585 phyid
== PHY_BCM_OUI_3
)
2586 do_low_power
= true;
2590 do_low_power
= true;
2592 if (tp
->link_config
.phy_is_low_power
== 0) {
2593 tp
->link_config
.phy_is_low_power
= 1;
2594 tp
->link_config
.orig_speed
= tp
->link_config
.speed
;
2595 tp
->link_config
.orig_duplex
= tp
->link_config
.duplex
;
2596 tp
->link_config
.orig_autoneg
= tp
->link_config
.autoneg
;
2599 if (!(tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
)) {
2600 tp
->link_config
.speed
= SPEED_10
;
2601 tp
->link_config
.duplex
= DUPLEX_HALF
;
2602 tp
->link_config
.autoneg
= AUTONEG_ENABLE
;
2603 tg3_setup_phy(tp
, 0);
2607 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
2610 val
= tr32(GRC_VCPU_EXT_CTRL
);
2611 tw32(GRC_VCPU_EXT_CTRL
, val
| GRC_VCPU_EXT_CTRL_DISABLE_WOL
);
2612 } else if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)) {
2616 for (i
= 0; i
< 200; i
++) {
2617 tg3_read_mem(tp
, NIC_SRAM_FW_ASF_STATUS_MBOX
, &val
);
2618 if (val
== ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1
)
2623 if (tp
->tg3_flags
& TG3_FLAG_WOL_CAP
)
2624 tg3_write_mem(tp
, NIC_SRAM_WOL_MBOX
, WOL_SIGNATURE
|
2625 WOL_DRV_STATE_SHUTDOWN
|
2629 if (device_should_wake
) {
2632 if (!(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)) {
2634 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x5a);
2638 if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
)
2639 mac_mode
= MAC_MODE_PORT_MODE_GMII
;
2641 mac_mode
= MAC_MODE_PORT_MODE_MII
;
2643 mac_mode
|= tp
->mac_mode
& MAC_MODE_LINK_POLARITY
;
2644 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
2646 u32 speed
= (tp
->tg3_flags
&
2647 TG3_FLAG_WOL_SPEED_100MB
) ?
2648 SPEED_100
: SPEED_10
;
2649 if (tg3_5700_link_polarity(tp
, speed
))
2650 mac_mode
|= MAC_MODE_LINK_POLARITY
;
2652 mac_mode
&= ~MAC_MODE_LINK_POLARITY
;
2655 mac_mode
= MAC_MODE_PORT_MODE_TBI
;
2658 if (!(tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
))
2659 tw32(MAC_LED_CTRL
, tp
->led_ctrl
);
2661 mac_mode
|= MAC_MODE_MAGIC_PKT_ENABLE
;
2662 if (((tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
2663 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) &&
2664 ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) ||
2665 (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)))
2666 mac_mode
|= MAC_MODE_KEEP_FRAME_IN_WOL
;
2668 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
2669 mac_mode
|= tp
->mac_mode
&
2670 (MAC_MODE_APE_TX_EN
| MAC_MODE_APE_RX_EN
);
2671 if (mac_mode
& MAC_MODE_APE_TX_EN
)
2672 mac_mode
|= MAC_MODE_TDE_ENABLE
;
2675 tw32_f(MAC_MODE
, mac_mode
);
2678 tw32_f(MAC_RX_MODE
, RX_MODE_ENABLE
);
2682 if (!(tp
->tg3_flags
& TG3_FLAG_WOL_SPEED_100MB
) &&
2683 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2684 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)) {
2687 base_val
= tp
->pci_clock_ctrl
;
2688 base_val
|= (CLOCK_CTRL_RXCLK_DISABLE
|
2689 CLOCK_CTRL_TXCLK_DISABLE
);
2691 tw32_wait_f(TG3PCI_CLOCK_CTRL
, base_val
| CLOCK_CTRL_ALTCLK
|
2692 CLOCK_CTRL_PWRDOWN_PLL133
, 40);
2693 } else if ((tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) ||
2694 (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) ||
2695 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)) {
2697 } else if (!((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
2698 (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))) {
2699 u32 newbits1
, newbits2
;
2701 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2702 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
2703 newbits1
= (CLOCK_CTRL_RXCLK_DISABLE
|
2704 CLOCK_CTRL_TXCLK_DISABLE
|
2706 newbits2
= newbits1
| CLOCK_CTRL_44MHZ_CORE
;
2707 } else if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
2708 newbits1
= CLOCK_CTRL_625_CORE
;
2709 newbits2
= newbits1
| CLOCK_CTRL_ALTCLK
;
2711 newbits1
= CLOCK_CTRL_ALTCLK
;
2712 newbits2
= newbits1
| CLOCK_CTRL_44MHZ_CORE
;
2715 tw32_wait_f(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
| newbits1
,
2718 tw32_wait_f(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
| newbits2
,
2721 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
2724 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2725 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
2726 newbits3
= (CLOCK_CTRL_RXCLK_DISABLE
|
2727 CLOCK_CTRL_TXCLK_DISABLE
|
2728 CLOCK_CTRL_44MHZ_CORE
);
2730 newbits3
= CLOCK_CTRL_44MHZ_CORE
;
2733 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
2734 tp
->pci_clock_ctrl
| newbits3
, 40);
2738 if (!(device_should_wake
) &&
2739 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
2740 tg3_power_down_phy(tp
, do_low_power
);
2742 tg3_frob_aux_power(tp
);
2744 /* Workaround for unstable PLL clock */
2745 if ((GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_AX
) ||
2746 (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_BX
)) {
2747 u32 val
= tr32(0x7d00);
2749 val
&= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2751 if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)) {
2754 err
= tg3_nvram_lock(tp
);
2755 tg3_halt_cpu(tp
, RX_CPU_BASE
);
2757 tg3_nvram_unlock(tp
);
2761 tg3_write_sig_post_reset(tp
, RESET_KIND_SHUTDOWN
);
2763 if (device_should_wake
)
2764 pci_enable_wake(tp
->pdev
, state
, true);
2766 /* Finally, set the new power state. */
2767 pci_set_power_state(tp
->pdev
, state
);
2772 static void tg3_aux_stat_to_speed_duplex(struct tg3
*tp
, u32 val
, u16
*speed
, u8
*duplex
)
2774 switch (val
& MII_TG3_AUX_STAT_SPDMASK
) {
2775 case MII_TG3_AUX_STAT_10HALF
:
2777 *duplex
= DUPLEX_HALF
;
2780 case MII_TG3_AUX_STAT_10FULL
:
2782 *duplex
= DUPLEX_FULL
;
2785 case MII_TG3_AUX_STAT_100HALF
:
2787 *duplex
= DUPLEX_HALF
;
2790 case MII_TG3_AUX_STAT_100FULL
:
2792 *duplex
= DUPLEX_FULL
;
2795 case MII_TG3_AUX_STAT_1000HALF
:
2796 *speed
= SPEED_1000
;
2797 *duplex
= DUPLEX_HALF
;
2800 case MII_TG3_AUX_STAT_1000FULL
:
2801 *speed
= SPEED_1000
;
2802 *duplex
= DUPLEX_FULL
;
2806 if (tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
) {
2807 *speed
= (val
& MII_TG3_AUX_STAT_100
) ? SPEED_100
:
2809 *duplex
= (val
& MII_TG3_AUX_STAT_FULL
) ? DUPLEX_FULL
:
2813 *speed
= SPEED_INVALID
;
2814 *duplex
= DUPLEX_INVALID
;
2819 static void tg3_phy_copper_begin(struct tg3
*tp
)
2824 if (tp
->link_config
.phy_is_low_power
) {
2825 /* Entering low power mode. Disable gigabit and
2826 * 100baseT advertisements.
2828 tg3_writephy(tp
, MII_TG3_CTRL
, 0);
2830 new_adv
= (ADVERTISE_10HALF
| ADVERTISE_10FULL
|
2831 ADVERTISE_CSMA
| ADVERTISE_PAUSE_CAP
);
2832 if (tp
->tg3_flags
& TG3_FLAG_WOL_SPEED_100MB
)
2833 new_adv
|= (ADVERTISE_100HALF
| ADVERTISE_100FULL
);
2835 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
2836 } else if (tp
->link_config
.speed
== SPEED_INVALID
) {
2837 if (tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)
2838 tp
->link_config
.advertising
&=
2839 ~(ADVERTISED_1000baseT_Half
|
2840 ADVERTISED_1000baseT_Full
);
2842 new_adv
= ADVERTISE_CSMA
;
2843 if (tp
->link_config
.advertising
& ADVERTISED_10baseT_Half
)
2844 new_adv
|= ADVERTISE_10HALF
;
2845 if (tp
->link_config
.advertising
& ADVERTISED_10baseT_Full
)
2846 new_adv
|= ADVERTISE_10FULL
;
2847 if (tp
->link_config
.advertising
& ADVERTISED_100baseT_Half
)
2848 new_adv
|= ADVERTISE_100HALF
;
2849 if (tp
->link_config
.advertising
& ADVERTISED_100baseT_Full
)
2850 new_adv
|= ADVERTISE_100FULL
;
2852 new_adv
|= tg3_advert_flowctrl_1000T(tp
->link_config
.flowctrl
);
2854 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
2856 if (tp
->link_config
.advertising
&
2857 (ADVERTISED_1000baseT_Half
| ADVERTISED_1000baseT_Full
)) {
2859 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Half
)
2860 new_adv
|= MII_TG3_CTRL_ADV_1000_HALF
;
2861 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Full
)
2862 new_adv
|= MII_TG3_CTRL_ADV_1000_FULL
;
2863 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
) &&
2864 (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
2865 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
))
2866 new_adv
|= (MII_TG3_CTRL_AS_MASTER
|
2867 MII_TG3_CTRL_ENABLE_AS_MASTER
);
2868 tg3_writephy(tp
, MII_TG3_CTRL
, new_adv
);
2870 tg3_writephy(tp
, MII_TG3_CTRL
, 0);
2873 new_adv
= tg3_advert_flowctrl_1000T(tp
->link_config
.flowctrl
);
2874 new_adv
|= ADVERTISE_CSMA
;
2876 /* Asking for a specific link mode. */
2877 if (tp
->link_config
.speed
== SPEED_1000
) {
2878 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
2880 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
2881 new_adv
= MII_TG3_CTRL_ADV_1000_FULL
;
2883 new_adv
= MII_TG3_CTRL_ADV_1000_HALF
;
2884 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
2885 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
)
2886 new_adv
|= (MII_TG3_CTRL_AS_MASTER
|
2887 MII_TG3_CTRL_ENABLE_AS_MASTER
);
2889 if (tp
->link_config
.speed
== SPEED_100
) {
2890 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
2891 new_adv
|= ADVERTISE_100FULL
;
2893 new_adv
|= ADVERTISE_100HALF
;
2895 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
2896 new_adv
|= ADVERTISE_10FULL
;
2898 new_adv
|= ADVERTISE_10HALF
;
2900 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
2905 tg3_writephy(tp
, MII_TG3_CTRL
, new_adv
);
2908 if (tp
->link_config
.autoneg
== AUTONEG_DISABLE
&&
2909 tp
->link_config
.speed
!= SPEED_INVALID
) {
2910 u32 bmcr
, orig_bmcr
;
2912 tp
->link_config
.active_speed
= tp
->link_config
.speed
;
2913 tp
->link_config
.active_duplex
= tp
->link_config
.duplex
;
2916 switch (tp
->link_config
.speed
) {
2922 bmcr
|= BMCR_SPEED100
;
2926 bmcr
|= TG3_BMCR_SPEED1000
;
2930 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
2931 bmcr
|= BMCR_FULLDPLX
;
2933 if (!tg3_readphy(tp
, MII_BMCR
, &orig_bmcr
) &&
2934 (bmcr
!= orig_bmcr
)) {
2935 tg3_writephy(tp
, MII_BMCR
, BMCR_LOOPBACK
);
2936 for (i
= 0; i
< 1500; i
++) {
2940 if (tg3_readphy(tp
, MII_BMSR
, &tmp
) ||
2941 tg3_readphy(tp
, MII_BMSR
, &tmp
))
2943 if (!(tmp
& BMSR_LSTATUS
)) {
2948 tg3_writephy(tp
, MII_BMCR
, bmcr
);
2952 tg3_writephy(tp
, MII_BMCR
,
2953 BMCR_ANENABLE
| BMCR_ANRESTART
);
2957 static int tg3_init_5401phy_dsp(struct tg3
*tp
)
2961 /* Turn off tap power management. */
2962 /* Set Extended packet length bit */
2963 err
= tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4c20);
2965 err
|= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x0012);
2966 err
|= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x1804);
2968 err
|= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x0013);
2969 err
|= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x1204);
2971 err
|= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8006);
2972 err
|= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0132);
2974 err
|= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8006);
2975 err
|= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0232);
2977 err
|= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x201f);
2978 err
|= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0a20);
2985 static int tg3_copper_is_advertising_all(struct tg3
*tp
, u32 mask
)
2987 u32 adv_reg
, all_mask
= 0;
2989 if (mask
& ADVERTISED_10baseT_Half
)
2990 all_mask
|= ADVERTISE_10HALF
;
2991 if (mask
& ADVERTISED_10baseT_Full
)
2992 all_mask
|= ADVERTISE_10FULL
;
2993 if (mask
& ADVERTISED_100baseT_Half
)
2994 all_mask
|= ADVERTISE_100HALF
;
2995 if (mask
& ADVERTISED_100baseT_Full
)
2996 all_mask
|= ADVERTISE_100FULL
;
2998 if (tg3_readphy(tp
, MII_ADVERTISE
, &adv_reg
))
3001 if ((adv_reg
& all_mask
) != all_mask
)
3003 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)) {
3007 if (mask
& ADVERTISED_1000baseT_Half
)
3008 all_mask
|= ADVERTISE_1000HALF
;
3009 if (mask
& ADVERTISED_1000baseT_Full
)
3010 all_mask
|= ADVERTISE_1000FULL
;
3012 if (tg3_readphy(tp
, MII_TG3_CTRL
, &tg3_ctrl
))
3015 if ((tg3_ctrl
& all_mask
) != all_mask
)
3021 static int tg3_adv_1000T_flowctrl_ok(struct tg3
*tp
, u32
*lcladv
, u32
*rmtadv
)
3025 if (tg3_readphy(tp
, MII_ADVERTISE
, lcladv
))
3028 curadv
= *lcladv
& (ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
3029 reqadv
= tg3_advert_flowctrl_1000T(tp
->link_config
.flowctrl
);
3031 if (tp
->link_config
.active_duplex
== DUPLEX_FULL
) {
3032 if (curadv
!= reqadv
)
3035 if (tp
->tg3_flags
& TG3_FLAG_PAUSE_AUTONEG
)
3036 tg3_readphy(tp
, MII_LPA
, rmtadv
);
3038 /* Reprogram the advertisement register, even if it
3039 * does not affect the current link. If the link
3040 * gets renegotiated in the future, we can save an
3041 * additional renegotiation cycle by advertising
3042 * it correctly in the first place.
3044 if (curadv
!= reqadv
) {
3045 *lcladv
&= ~(ADVERTISE_PAUSE_CAP
|
3046 ADVERTISE_PAUSE_ASYM
);
3047 tg3_writephy(tp
, MII_ADVERTISE
, *lcladv
| reqadv
);
3054 static int tg3_setup_copper_phy(struct tg3
*tp
, int force_reset
)
3056 int current_link_up
;
3058 u32 lcl_adv
, rmt_adv
;
3066 (MAC_STATUS_SYNC_CHANGED
|
3067 MAC_STATUS_CFG_CHANGED
|
3068 MAC_STATUS_MI_COMPLETION
|
3069 MAC_STATUS_LNKSTATE_CHANGED
));
3072 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
3074 (tp
->mi_mode
& ~MAC_MI_MODE_AUTO_POLL
));
3078 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x02);
3080 /* Some third-party PHYs need to be reset on link going
3083 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
3084 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
3085 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) &&
3086 netif_carrier_ok(tp
->dev
)) {
3087 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3088 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
3089 !(bmsr
& BMSR_LSTATUS
))
3095 if ((tp
->phy_id
& TG3_PHY_ID_MASK
) == TG3_PHY_ID_BCM5401
) {
3096 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3097 if (tg3_readphy(tp
, MII_BMSR
, &bmsr
) ||
3098 !(tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
))
3101 if (!(bmsr
& BMSR_LSTATUS
)) {
3102 err
= tg3_init_5401phy_dsp(tp
);
3106 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3107 for (i
= 0; i
< 1000; i
++) {
3109 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
3110 (bmsr
& BMSR_LSTATUS
)) {
3116 if ((tp
->phy_id
& TG3_PHY_ID_REV_MASK
) ==
3117 TG3_PHY_REV_BCM5401_B0
&&
3118 !(bmsr
& BMSR_LSTATUS
) &&
3119 tp
->link_config
.active_speed
== SPEED_1000
) {
3120 err
= tg3_phy_reset(tp
);
3122 err
= tg3_init_5401phy_dsp(tp
);
3127 } else if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
3128 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
) {
3129 /* 5701 {A0,B0} CRC bug workaround */
3130 tg3_writephy(tp
, 0x15, 0x0a75);
3131 tg3_writephy(tp
, 0x1c, 0x8c68);
3132 tg3_writephy(tp
, 0x1c, 0x8d68);
3133 tg3_writephy(tp
, 0x1c, 0x8c68);
3136 /* Clear pending interrupts... */
3137 tg3_readphy(tp
, MII_TG3_ISTAT
, &dummy
);
3138 tg3_readphy(tp
, MII_TG3_ISTAT
, &dummy
);
3140 if (tp
->tg3_flags
& TG3_FLAG_USE_MI_INTERRUPT
)
3141 tg3_writephy(tp
, MII_TG3_IMASK
, ~MII_TG3_INT_LINKCHG
);
3142 else if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
))
3143 tg3_writephy(tp
, MII_TG3_IMASK
, ~0);
3145 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
3146 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
3147 if (tp
->led_ctrl
== LED_CTRL_MODE_PHY_1
)
3148 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
3149 MII_TG3_EXT_CTRL_LNK3_LED_MODE
);
3151 tg3_writephy(tp
, MII_TG3_EXT_CTRL
, 0);
3154 current_link_up
= 0;
3155 current_speed
= SPEED_INVALID
;
3156 current_duplex
= DUPLEX_INVALID
;
3158 if (tp
->tg3_flags2
& TG3_FLG2_CAPACITIVE_COUPLING
) {
3161 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4007);
3162 tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &val
);
3163 if (!(val
& (1 << 10))) {
3165 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, val
);
3171 for (i
= 0; i
< 100; i
++) {
3172 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3173 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
3174 (bmsr
& BMSR_LSTATUS
))
3179 if (bmsr
& BMSR_LSTATUS
) {
3182 tg3_readphy(tp
, MII_TG3_AUX_STAT
, &aux_stat
);
3183 for (i
= 0; i
< 2000; i
++) {
3185 if (!tg3_readphy(tp
, MII_TG3_AUX_STAT
, &aux_stat
) &&
3190 tg3_aux_stat_to_speed_duplex(tp
, aux_stat
,
3195 for (i
= 0; i
< 200; i
++) {
3196 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
3197 if (tg3_readphy(tp
, MII_BMCR
, &bmcr
))
3199 if (bmcr
&& bmcr
!= 0x7fff)
3207 tp
->link_config
.active_speed
= current_speed
;
3208 tp
->link_config
.active_duplex
= current_duplex
;
3210 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) {
3211 if ((bmcr
& BMCR_ANENABLE
) &&
3212 tg3_copper_is_advertising_all(tp
,
3213 tp
->link_config
.advertising
)) {
3214 if (tg3_adv_1000T_flowctrl_ok(tp
, &lcl_adv
,
3216 current_link_up
= 1;
3219 if (!(bmcr
& BMCR_ANENABLE
) &&
3220 tp
->link_config
.speed
== current_speed
&&
3221 tp
->link_config
.duplex
== current_duplex
&&
3222 tp
->link_config
.flowctrl
==
3223 tp
->link_config
.active_flowctrl
) {
3224 current_link_up
= 1;
3228 if (current_link_up
== 1 &&
3229 tp
->link_config
.active_duplex
== DUPLEX_FULL
)
3230 tg3_setup_flow_control(tp
, lcl_adv
, rmt_adv
);
3234 if (current_link_up
== 0 || tp
->link_config
.phy_is_low_power
) {
3237 tg3_phy_copper_begin(tp
);
3239 tg3_readphy(tp
, MII_BMSR
, &tmp
);
3240 if (!tg3_readphy(tp
, MII_BMSR
, &tmp
) &&
3241 (tmp
& BMSR_LSTATUS
))
3242 current_link_up
= 1;
3245 tp
->mac_mode
&= ~MAC_MODE_PORT_MODE_MASK
;
3246 if (current_link_up
== 1) {
3247 if (tp
->link_config
.active_speed
== SPEED_100
||
3248 tp
->link_config
.active_speed
== SPEED_10
)
3249 tp
->mac_mode
|= MAC_MODE_PORT_MODE_MII
;
3251 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
3252 } else if (tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
)
3253 tp
->mac_mode
|= MAC_MODE_PORT_MODE_MII
;
3255 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
3257 tp
->mac_mode
&= ~MAC_MODE_HALF_DUPLEX
;
3258 if (tp
->link_config
.active_duplex
== DUPLEX_HALF
)
3259 tp
->mac_mode
|= MAC_MODE_HALF_DUPLEX
;
3261 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) {
3262 if (current_link_up
== 1 &&
3263 tg3_5700_link_polarity(tp
, tp
->link_config
.active_speed
))
3264 tp
->mac_mode
|= MAC_MODE_LINK_POLARITY
;
3266 tp
->mac_mode
&= ~MAC_MODE_LINK_POLARITY
;
3269 /* ??? Without this setting Netgear GA302T PHY does not
3270 * ??? send/receive packets...
3272 if ((tp
->phy_id
& TG3_PHY_ID_MASK
) == TG3_PHY_ID_BCM5411
&&
3273 tp
->pci_chip_rev_id
== CHIPREV_ID_5700_ALTIMA
) {
3274 tp
->mi_mode
|= MAC_MI_MODE_AUTO_POLL
;
3275 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
3279 tw32_f(MAC_MODE
, tp
->mac_mode
);
3282 if (tp
->tg3_flags
& TG3_FLAG_USE_LINKCHG_REG
) {
3283 /* Polled via timer. */
3284 tw32_f(MAC_EVENT
, 0);
3286 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
3290 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
&&
3291 current_link_up
== 1 &&
3292 tp
->link_config
.active_speed
== SPEED_1000
&&
3293 ((tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) ||
3294 (tp
->tg3_flags
& TG3_FLAG_PCI_HIGH_SPEED
))) {
3297 (MAC_STATUS_SYNC_CHANGED
|
3298 MAC_STATUS_CFG_CHANGED
));
3301 NIC_SRAM_FIRMWARE_MBOX
,
3302 NIC_SRAM_FIRMWARE_MBOX_MAGIC2
);
3305 /* Prevent send BD corruption. */
3306 if (tp
->tg3_flags3
& TG3_FLG3_CLKREQ_BUG
) {
3307 u16 oldlnkctl
, newlnkctl
;
3309 pci_read_config_word(tp
->pdev
,
3310 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
3312 if (tp
->link_config
.active_speed
== SPEED_100
||
3313 tp
->link_config
.active_speed
== SPEED_10
)
3314 newlnkctl
= oldlnkctl
& ~PCI_EXP_LNKCTL_CLKREQ_EN
;
3316 newlnkctl
= oldlnkctl
| PCI_EXP_LNKCTL_CLKREQ_EN
;
3317 if (newlnkctl
!= oldlnkctl
)
3318 pci_write_config_word(tp
->pdev
,
3319 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
3323 if (current_link_up
!= netif_carrier_ok(tp
->dev
)) {
3324 if (current_link_up
)
3325 netif_carrier_on(tp
->dev
);
3327 netif_carrier_off(tp
->dev
);
3328 tg3_link_report(tp
);
3334 struct tg3_fiber_aneginfo
{
3336 #define ANEG_STATE_UNKNOWN 0
3337 #define ANEG_STATE_AN_ENABLE 1
3338 #define ANEG_STATE_RESTART_INIT 2
3339 #define ANEG_STATE_RESTART 3
3340 #define ANEG_STATE_DISABLE_LINK_OK 4
3341 #define ANEG_STATE_ABILITY_DETECT_INIT 5
3342 #define ANEG_STATE_ABILITY_DETECT 6
3343 #define ANEG_STATE_ACK_DETECT_INIT 7
3344 #define ANEG_STATE_ACK_DETECT 8
3345 #define ANEG_STATE_COMPLETE_ACK_INIT 9
3346 #define ANEG_STATE_COMPLETE_ACK 10
3347 #define ANEG_STATE_IDLE_DETECT_INIT 11
3348 #define ANEG_STATE_IDLE_DETECT 12
3349 #define ANEG_STATE_LINK_OK 13
3350 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3351 #define ANEG_STATE_NEXT_PAGE_WAIT 15
3354 #define MR_AN_ENABLE 0x00000001
3355 #define MR_RESTART_AN 0x00000002
3356 #define MR_AN_COMPLETE 0x00000004
3357 #define MR_PAGE_RX 0x00000008
3358 #define MR_NP_LOADED 0x00000010
3359 #define MR_TOGGLE_TX 0x00000020
3360 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
3361 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
3362 #define MR_LP_ADV_SYM_PAUSE 0x00000100
3363 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
3364 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3365 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3366 #define MR_LP_ADV_NEXT_PAGE 0x00001000
3367 #define MR_TOGGLE_RX 0x00002000
3368 #define MR_NP_RX 0x00004000
3370 #define MR_LINK_OK 0x80000000
3372 unsigned long link_time
, cur_time
;
3374 u32 ability_match_cfg
;
3375 int ability_match_count
;
3377 char ability_match
, idle_match
, ack_match
;
3379 u32 txconfig
, rxconfig
;
3380 #define ANEG_CFG_NP 0x00000080
3381 #define ANEG_CFG_ACK 0x00000040
3382 #define ANEG_CFG_RF2 0x00000020
3383 #define ANEG_CFG_RF1 0x00000010
3384 #define ANEG_CFG_PS2 0x00000001
3385 #define ANEG_CFG_PS1 0x00008000
3386 #define ANEG_CFG_HD 0x00004000
3387 #define ANEG_CFG_FD 0x00002000
3388 #define ANEG_CFG_INVAL 0x00001f06
3393 #define ANEG_TIMER_ENAB 2
3394 #define ANEG_FAILED -1
3396 #define ANEG_STATE_SETTLE_TIME 10000
3398 static int tg3_fiber_aneg_smachine(struct tg3
*tp
,
3399 struct tg3_fiber_aneginfo
*ap
)
3402 unsigned long delta
;
3406 if (ap
->state
== ANEG_STATE_UNKNOWN
) {
3410 ap
->ability_match_cfg
= 0;
3411 ap
->ability_match_count
= 0;
3412 ap
->ability_match
= 0;
3418 if (tr32(MAC_STATUS
) & MAC_STATUS_RCVD_CFG
) {
3419 rx_cfg_reg
= tr32(MAC_RX_AUTO_NEG
);
3421 if (rx_cfg_reg
!= ap
->ability_match_cfg
) {
3422 ap
->ability_match_cfg
= rx_cfg_reg
;
3423 ap
->ability_match
= 0;
3424 ap
->ability_match_count
= 0;
3426 if (++ap
->ability_match_count
> 1) {
3427 ap
->ability_match
= 1;
3428 ap
->ability_match_cfg
= rx_cfg_reg
;
3431 if (rx_cfg_reg
& ANEG_CFG_ACK
)
3439 ap
->ability_match_cfg
= 0;
3440 ap
->ability_match_count
= 0;
3441 ap
->ability_match
= 0;
3447 ap
->rxconfig
= rx_cfg_reg
;
3450 switch (ap
->state
) {
3451 case ANEG_STATE_UNKNOWN
:
3452 if (ap
->flags
& (MR_AN_ENABLE
| MR_RESTART_AN
))
3453 ap
->state
= ANEG_STATE_AN_ENABLE
;
3456 case ANEG_STATE_AN_ENABLE
:
3457 ap
->flags
&= ~(MR_AN_COMPLETE
| MR_PAGE_RX
);
3458 if (ap
->flags
& MR_AN_ENABLE
) {
3461 ap
->ability_match_cfg
= 0;
3462 ap
->ability_match_count
= 0;
3463 ap
->ability_match
= 0;
3467 ap
->state
= ANEG_STATE_RESTART_INIT
;
3469 ap
->state
= ANEG_STATE_DISABLE_LINK_OK
;
3473 case ANEG_STATE_RESTART_INIT
:
3474 ap
->link_time
= ap
->cur_time
;
3475 ap
->flags
&= ~(MR_NP_LOADED
);
3477 tw32(MAC_TX_AUTO_NEG
, 0);
3478 tp
->mac_mode
|= MAC_MODE_SEND_CONFIGS
;
3479 tw32_f(MAC_MODE
, tp
->mac_mode
);
3482 ret
= ANEG_TIMER_ENAB
;
3483 ap
->state
= ANEG_STATE_RESTART
;
3486 case ANEG_STATE_RESTART
:
3487 delta
= ap
->cur_time
- ap
->link_time
;
3488 if (delta
> ANEG_STATE_SETTLE_TIME
)
3489 ap
->state
= ANEG_STATE_ABILITY_DETECT_INIT
;
3491 ret
= ANEG_TIMER_ENAB
;
3494 case ANEG_STATE_DISABLE_LINK_OK
:
3498 case ANEG_STATE_ABILITY_DETECT_INIT
:
3499 ap
->flags
&= ~(MR_TOGGLE_TX
);
3500 ap
->txconfig
= ANEG_CFG_FD
;
3501 flowctrl
= tg3_advert_flowctrl_1000X(tp
->link_config
.flowctrl
);
3502 if (flowctrl
& ADVERTISE_1000XPAUSE
)
3503 ap
->txconfig
|= ANEG_CFG_PS1
;
3504 if (flowctrl
& ADVERTISE_1000XPSE_ASYM
)
3505 ap
->txconfig
|= ANEG_CFG_PS2
;
3506 tw32(MAC_TX_AUTO_NEG
, ap
->txconfig
);
3507 tp
->mac_mode
|= MAC_MODE_SEND_CONFIGS
;
3508 tw32_f(MAC_MODE
, tp
->mac_mode
);
3511 ap
->state
= ANEG_STATE_ABILITY_DETECT
;
3514 case ANEG_STATE_ABILITY_DETECT
:
3515 if (ap
->ability_match
!= 0 && ap
->rxconfig
!= 0)
3516 ap
->state
= ANEG_STATE_ACK_DETECT_INIT
;
3519 case ANEG_STATE_ACK_DETECT_INIT
:
3520 ap
->txconfig
|= ANEG_CFG_ACK
;
3521 tw32(MAC_TX_AUTO_NEG
, ap
->txconfig
);
3522 tp
->mac_mode
|= MAC_MODE_SEND_CONFIGS
;
3523 tw32_f(MAC_MODE
, tp
->mac_mode
);
3526 ap
->state
= ANEG_STATE_ACK_DETECT
;
3529 case ANEG_STATE_ACK_DETECT
:
3530 if (ap
->ack_match
!= 0) {
3531 if ((ap
->rxconfig
& ~ANEG_CFG_ACK
) ==
3532 (ap
->ability_match_cfg
& ~ANEG_CFG_ACK
)) {
3533 ap
->state
= ANEG_STATE_COMPLETE_ACK_INIT
;
3535 ap
->state
= ANEG_STATE_AN_ENABLE
;
3537 } else if (ap
->ability_match
!= 0 &&
3538 ap
->rxconfig
== 0) {
3539 ap
->state
= ANEG_STATE_AN_ENABLE
;
3543 case ANEG_STATE_COMPLETE_ACK_INIT
:
3544 if (ap
->rxconfig
& ANEG_CFG_INVAL
) {
3548 ap
->flags
&= ~(MR_LP_ADV_FULL_DUPLEX
|
3549 MR_LP_ADV_HALF_DUPLEX
|
3550 MR_LP_ADV_SYM_PAUSE
|
3551 MR_LP_ADV_ASYM_PAUSE
|
3552 MR_LP_ADV_REMOTE_FAULT1
|
3553 MR_LP_ADV_REMOTE_FAULT2
|
3554 MR_LP_ADV_NEXT_PAGE
|
3557 if (ap
->rxconfig
& ANEG_CFG_FD
)
3558 ap
->flags
|= MR_LP_ADV_FULL_DUPLEX
;
3559 if (ap
->rxconfig
& ANEG_CFG_HD
)
3560 ap
->flags
|= MR_LP_ADV_HALF_DUPLEX
;
3561 if (ap
->rxconfig
& ANEG_CFG_PS1
)
3562 ap
->flags
|= MR_LP_ADV_SYM_PAUSE
;
3563 if (ap
->rxconfig
& ANEG_CFG_PS2
)
3564 ap
->flags
|= MR_LP_ADV_ASYM_PAUSE
;
3565 if (ap
->rxconfig
& ANEG_CFG_RF1
)
3566 ap
->flags
|= MR_LP_ADV_REMOTE_FAULT1
;
3567 if (ap
->rxconfig
& ANEG_CFG_RF2
)
3568 ap
->flags
|= MR_LP_ADV_REMOTE_FAULT2
;
3569 if (ap
->rxconfig
& ANEG_CFG_NP
)
3570 ap
->flags
|= MR_LP_ADV_NEXT_PAGE
;
3572 ap
->link_time
= ap
->cur_time
;
3574 ap
->flags
^= (MR_TOGGLE_TX
);
3575 if (ap
->rxconfig
& 0x0008)
3576 ap
->flags
|= MR_TOGGLE_RX
;
3577 if (ap
->rxconfig
& ANEG_CFG_NP
)
3578 ap
->flags
|= MR_NP_RX
;
3579 ap
->flags
|= MR_PAGE_RX
;
3581 ap
->state
= ANEG_STATE_COMPLETE_ACK
;
3582 ret
= ANEG_TIMER_ENAB
;
3585 case ANEG_STATE_COMPLETE_ACK
:
3586 if (ap
->ability_match
!= 0 &&
3587 ap
->rxconfig
== 0) {
3588 ap
->state
= ANEG_STATE_AN_ENABLE
;
3591 delta
= ap
->cur_time
- ap
->link_time
;
3592 if (delta
> ANEG_STATE_SETTLE_TIME
) {
3593 if (!(ap
->flags
& (MR_LP_ADV_NEXT_PAGE
))) {
3594 ap
->state
= ANEG_STATE_IDLE_DETECT_INIT
;
3596 if ((ap
->txconfig
& ANEG_CFG_NP
) == 0 &&
3597 !(ap
->flags
& MR_NP_RX
)) {
3598 ap
->state
= ANEG_STATE_IDLE_DETECT_INIT
;
3606 case ANEG_STATE_IDLE_DETECT_INIT
:
3607 ap
->link_time
= ap
->cur_time
;
3608 tp
->mac_mode
&= ~MAC_MODE_SEND_CONFIGS
;
3609 tw32_f(MAC_MODE
, tp
->mac_mode
);
3612 ap
->state
= ANEG_STATE_IDLE_DETECT
;
3613 ret
= ANEG_TIMER_ENAB
;
3616 case ANEG_STATE_IDLE_DETECT
:
3617 if (ap
->ability_match
!= 0 &&
3618 ap
->rxconfig
== 0) {
3619 ap
->state
= ANEG_STATE_AN_ENABLE
;
3622 delta
= ap
->cur_time
- ap
->link_time
;
3623 if (delta
> ANEG_STATE_SETTLE_TIME
) {
3624 /* XXX another gem from the Broadcom driver :( */
3625 ap
->state
= ANEG_STATE_LINK_OK
;
3629 case ANEG_STATE_LINK_OK
:
3630 ap
->flags
|= (MR_AN_COMPLETE
| MR_LINK_OK
);
3634 case ANEG_STATE_NEXT_PAGE_WAIT_INIT
:
3635 /* ??? unimplemented */
3638 case ANEG_STATE_NEXT_PAGE_WAIT
:
3639 /* ??? unimplemented */
3650 static int fiber_autoneg(struct tg3
*tp
, u32
*txflags
, u32
*rxflags
)
3653 struct tg3_fiber_aneginfo aninfo
;
3654 int status
= ANEG_FAILED
;
3658 tw32_f(MAC_TX_AUTO_NEG
, 0);
3660 tmp
= tp
->mac_mode
& ~MAC_MODE_PORT_MODE_MASK
;
3661 tw32_f(MAC_MODE
, tmp
| MAC_MODE_PORT_MODE_GMII
);
3664 tw32_f(MAC_MODE
, tp
->mac_mode
| MAC_MODE_SEND_CONFIGS
);
3667 memset(&aninfo
, 0, sizeof(aninfo
));
3668 aninfo
.flags
|= MR_AN_ENABLE
;
3669 aninfo
.state
= ANEG_STATE_UNKNOWN
;
3670 aninfo
.cur_time
= 0;
3672 while (++tick
< 195000) {
3673 status
= tg3_fiber_aneg_smachine(tp
, &aninfo
);
3674 if (status
== ANEG_DONE
|| status
== ANEG_FAILED
)
3680 tp
->mac_mode
&= ~MAC_MODE_SEND_CONFIGS
;
3681 tw32_f(MAC_MODE
, tp
->mac_mode
);
3684 *txflags
= aninfo
.txconfig
;
3685 *rxflags
= aninfo
.flags
;
3687 if (status
== ANEG_DONE
&&
3688 (aninfo
.flags
& (MR_AN_COMPLETE
| MR_LINK_OK
|
3689 MR_LP_ADV_FULL_DUPLEX
)))
3695 static void tg3_init_bcm8002(struct tg3
*tp
)
3697 u32 mac_status
= tr32(MAC_STATUS
);
3700 /* Reset when initting first time or we have a link. */
3701 if ((tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
) &&
3702 !(mac_status
& MAC_STATUS_PCS_SYNCED
))
3705 /* Set PLL lock range. */
3706 tg3_writephy(tp
, 0x16, 0x8007);
3709 tg3_writephy(tp
, MII_BMCR
, BMCR_RESET
);
3711 /* Wait for reset to complete. */
3712 /* XXX schedule_timeout() ... */
3713 for (i
= 0; i
< 500; i
++)
3716 /* Config mode; select PMA/Ch 1 regs. */
3717 tg3_writephy(tp
, 0x10, 0x8411);
3719 /* Enable auto-lock and comdet, select txclk for tx. */
3720 tg3_writephy(tp
, 0x11, 0x0a10);
3722 tg3_writephy(tp
, 0x18, 0x00a0);
3723 tg3_writephy(tp
, 0x16, 0x41ff);
3725 /* Assert and deassert POR. */
3726 tg3_writephy(tp
, 0x13, 0x0400);
3728 tg3_writephy(tp
, 0x13, 0x0000);
3730 tg3_writephy(tp
, 0x11, 0x0a50);
3732 tg3_writephy(tp
, 0x11, 0x0a10);
3734 /* Wait for signal to stabilize */
3735 /* XXX schedule_timeout() ... */
3736 for (i
= 0; i
< 15000; i
++)
3739 /* Deselect the channel register so we can read the PHYID
3742 tg3_writephy(tp
, 0x10, 0x8011);
3745 static int tg3_setup_fiber_hw_autoneg(struct tg3
*tp
, u32 mac_status
)
3748 u32 sg_dig_ctrl
, sg_dig_status
;
3749 u32 serdes_cfg
, expected_sg_dig_ctrl
;
3750 int workaround
, port_a
;
3751 int current_link_up
;
3754 expected_sg_dig_ctrl
= 0;
3757 current_link_up
= 0;
3759 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5704_A0
&&
3760 tp
->pci_chip_rev_id
!= CHIPREV_ID_5704_A1
) {
3762 if (tr32(TG3PCI_DUAL_MAC_CTRL
) & DUAL_MAC_CTRL_ID
)
3765 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3766 /* preserve bits 20-23 for voltage regulator */
3767 serdes_cfg
= tr32(MAC_SERDES_CFG
) & 0x00f06fff;
3770 sg_dig_ctrl
= tr32(SG_DIG_CTRL
);
3772 if (tp
->link_config
.autoneg
!= AUTONEG_ENABLE
) {
3773 if (sg_dig_ctrl
& SG_DIG_USING_HW_AUTONEG
) {
3775 u32 val
= serdes_cfg
;
3781 tw32_f(MAC_SERDES_CFG
, val
);
3784 tw32_f(SG_DIG_CTRL
, SG_DIG_COMMON_SETUP
);
3786 if (mac_status
& MAC_STATUS_PCS_SYNCED
) {
3787 tg3_setup_flow_control(tp
, 0, 0);
3788 current_link_up
= 1;
3793 /* Want auto-negotiation. */
3794 expected_sg_dig_ctrl
= SG_DIG_USING_HW_AUTONEG
| SG_DIG_COMMON_SETUP
;
3796 flowctrl
= tg3_advert_flowctrl_1000X(tp
->link_config
.flowctrl
);
3797 if (flowctrl
& ADVERTISE_1000XPAUSE
)
3798 expected_sg_dig_ctrl
|= SG_DIG_PAUSE_CAP
;
3799 if (flowctrl
& ADVERTISE_1000XPSE_ASYM
)
3800 expected_sg_dig_ctrl
|= SG_DIG_ASYM_PAUSE
;
3802 if (sg_dig_ctrl
!= expected_sg_dig_ctrl
) {
3803 if ((tp
->tg3_flags2
& TG3_FLG2_PARALLEL_DETECT
) &&
3804 tp
->serdes_counter
&&
3805 ((mac_status
& (MAC_STATUS_PCS_SYNCED
|
3806 MAC_STATUS_RCVD_CFG
)) ==
3807 MAC_STATUS_PCS_SYNCED
)) {
3808 tp
->serdes_counter
--;
3809 current_link_up
= 1;
3814 tw32_f(MAC_SERDES_CFG
, serdes_cfg
| 0xc011000);
3815 tw32_f(SG_DIG_CTRL
, expected_sg_dig_ctrl
| SG_DIG_SOFT_RESET
);
3817 tw32_f(SG_DIG_CTRL
, expected_sg_dig_ctrl
);
3819 tp
->serdes_counter
= SERDES_AN_TIMEOUT_5704S
;
3820 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
3821 } else if (mac_status
& (MAC_STATUS_PCS_SYNCED
|
3822 MAC_STATUS_SIGNAL_DET
)) {
3823 sg_dig_status
= tr32(SG_DIG_STATUS
);
3824 mac_status
= tr32(MAC_STATUS
);
3826 if ((sg_dig_status
& SG_DIG_AUTONEG_COMPLETE
) &&
3827 (mac_status
& MAC_STATUS_PCS_SYNCED
)) {
3828 u32 local_adv
= 0, remote_adv
= 0;
3830 if (sg_dig_ctrl
& SG_DIG_PAUSE_CAP
)
3831 local_adv
|= ADVERTISE_1000XPAUSE
;
3832 if (sg_dig_ctrl
& SG_DIG_ASYM_PAUSE
)
3833 local_adv
|= ADVERTISE_1000XPSE_ASYM
;
3835 if (sg_dig_status
& SG_DIG_PARTNER_PAUSE_CAPABLE
)
3836 remote_adv
|= LPA_1000XPAUSE
;
3837 if (sg_dig_status
& SG_DIG_PARTNER_ASYM_PAUSE
)
3838 remote_adv
|= LPA_1000XPAUSE_ASYM
;
3840 tg3_setup_flow_control(tp
, local_adv
, remote_adv
);
3841 current_link_up
= 1;
3842 tp
->serdes_counter
= 0;
3843 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
3844 } else if (!(sg_dig_status
& SG_DIG_AUTONEG_COMPLETE
)) {
3845 if (tp
->serdes_counter
)
3846 tp
->serdes_counter
--;
3849 u32 val
= serdes_cfg
;
3856 tw32_f(MAC_SERDES_CFG
, val
);
3859 tw32_f(SG_DIG_CTRL
, SG_DIG_COMMON_SETUP
);
3862 /* Link parallel detection - link is up */
3863 /* only if we have PCS_SYNC and not */
3864 /* receiving config code words */
3865 mac_status
= tr32(MAC_STATUS
);
3866 if ((mac_status
& MAC_STATUS_PCS_SYNCED
) &&
3867 !(mac_status
& MAC_STATUS_RCVD_CFG
)) {
3868 tg3_setup_flow_control(tp
, 0, 0);
3869 current_link_up
= 1;
3871 TG3_FLG2_PARALLEL_DETECT
;
3872 tp
->serdes_counter
=
3873 SERDES_PARALLEL_DET_TIMEOUT
;
3875 goto restart_autoneg
;
3879 tp
->serdes_counter
= SERDES_AN_TIMEOUT_5704S
;
3880 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
3884 return current_link_up
;
3887 static int tg3_setup_fiber_by_hand(struct tg3
*tp
, u32 mac_status
)
3889 int current_link_up
= 0;
3891 if (!(mac_status
& MAC_STATUS_PCS_SYNCED
))
3894 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) {
3895 u32 txflags
, rxflags
;
3898 if (fiber_autoneg(tp
, &txflags
, &rxflags
)) {
3899 u32 local_adv
= 0, remote_adv
= 0;
3901 if (txflags
& ANEG_CFG_PS1
)
3902 local_adv
|= ADVERTISE_1000XPAUSE
;
3903 if (txflags
& ANEG_CFG_PS2
)
3904 local_adv
|= ADVERTISE_1000XPSE_ASYM
;
3906 if (rxflags
& MR_LP_ADV_SYM_PAUSE
)
3907 remote_adv
|= LPA_1000XPAUSE
;
3908 if (rxflags
& MR_LP_ADV_ASYM_PAUSE
)
3909 remote_adv
|= LPA_1000XPAUSE_ASYM
;
3911 tg3_setup_flow_control(tp
, local_adv
, remote_adv
);
3913 current_link_up
= 1;
3915 for (i
= 0; i
< 30; i
++) {
3918 (MAC_STATUS_SYNC_CHANGED
|
3919 MAC_STATUS_CFG_CHANGED
));
3921 if ((tr32(MAC_STATUS
) &
3922 (MAC_STATUS_SYNC_CHANGED
|
3923 MAC_STATUS_CFG_CHANGED
)) == 0)
3927 mac_status
= tr32(MAC_STATUS
);
3928 if (current_link_up
== 0 &&
3929 (mac_status
& MAC_STATUS_PCS_SYNCED
) &&
3930 !(mac_status
& MAC_STATUS_RCVD_CFG
))
3931 current_link_up
= 1;
3933 tg3_setup_flow_control(tp
, 0, 0);
3935 /* Forcing 1000FD link up. */
3936 current_link_up
= 1;
3938 tw32_f(MAC_MODE
, (tp
->mac_mode
| MAC_MODE_SEND_CONFIGS
));
3941 tw32_f(MAC_MODE
, tp
->mac_mode
);
3946 return current_link_up
;
3949 static int tg3_setup_fiber_phy(struct tg3
*tp
, int force_reset
)
3952 u16 orig_active_speed
;
3953 u8 orig_active_duplex
;
3955 int current_link_up
;
3958 orig_pause_cfg
= tp
->link_config
.active_flowctrl
;
3959 orig_active_speed
= tp
->link_config
.active_speed
;
3960 orig_active_duplex
= tp
->link_config
.active_duplex
;
3962 if (!(tp
->tg3_flags2
& TG3_FLG2_HW_AUTONEG
) &&
3963 netif_carrier_ok(tp
->dev
) &&
3964 (tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
)) {
3965 mac_status
= tr32(MAC_STATUS
);
3966 mac_status
&= (MAC_STATUS_PCS_SYNCED
|
3967 MAC_STATUS_SIGNAL_DET
|
3968 MAC_STATUS_CFG_CHANGED
|
3969 MAC_STATUS_RCVD_CFG
);
3970 if (mac_status
== (MAC_STATUS_PCS_SYNCED
|
3971 MAC_STATUS_SIGNAL_DET
)) {
3972 tw32_f(MAC_STATUS
, (MAC_STATUS_SYNC_CHANGED
|
3973 MAC_STATUS_CFG_CHANGED
));
3978 tw32_f(MAC_TX_AUTO_NEG
, 0);
3980 tp
->mac_mode
&= ~(MAC_MODE_PORT_MODE_MASK
| MAC_MODE_HALF_DUPLEX
);
3981 tp
->mac_mode
|= MAC_MODE_PORT_MODE_TBI
;
3982 tw32_f(MAC_MODE
, tp
->mac_mode
);
3985 if (tp
->phy_id
== TG3_PHY_ID_BCM8002
)
3986 tg3_init_bcm8002(tp
);
3988 /* Enable link change event even when serdes polling. */
3989 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
3992 current_link_up
= 0;
3993 mac_status
= tr32(MAC_STATUS
);
3995 if (tp
->tg3_flags2
& TG3_FLG2_HW_AUTONEG
)
3996 current_link_up
= tg3_setup_fiber_hw_autoneg(tp
, mac_status
);
3998 current_link_up
= tg3_setup_fiber_by_hand(tp
, mac_status
);
4000 tp
->napi
[0].hw_status
->status
=
4001 (SD_STATUS_UPDATED
|
4002 (tp
->napi
[0].hw_status
->status
& ~SD_STATUS_LINK_CHG
));
4004 for (i
= 0; i
< 100; i
++) {
4005 tw32_f(MAC_STATUS
, (MAC_STATUS_SYNC_CHANGED
|
4006 MAC_STATUS_CFG_CHANGED
));
4008 if ((tr32(MAC_STATUS
) & (MAC_STATUS_SYNC_CHANGED
|
4009 MAC_STATUS_CFG_CHANGED
|
4010 MAC_STATUS_LNKSTATE_CHANGED
)) == 0)
4014 mac_status
= tr32(MAC_STATUS
);
4015 if ((mac_status
& MAC_STATUS_PCS_SYNCED
) == 0) {
4016 current_link_up
= 0;
4017 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
&&
4018 tp
->serdes_counter
== 0) {
4019 tw32_f(MAC_MODE
, (tp
->mac_mode
|
4020 MAC_MODE_SEND_CONFIGS
));
4022 tw32_f(MAC_MODE
, tp
->mac_mode
);
4026 if (current_link_up
== 1) {
4027 tp
->link_config
.active_speed
= SPEED_1000
;
4028 tp
->link_config
.active_duplex
= DUPLEX_FULL
;
4029 tw32(MAC_LED_CTRL
, (tp
->led_ctrl
|
4030 LED_CTRL_LNKLED_OVERRIDE
|
4031 LED_CTRL_1000MBPS_ON
));
4033 tp
->link_config
.active_speed
= SPEED_INVALID
;
4034 tp
->link_config
.active_duplex
= DUPLEX_INVALID
;
4035 tw32(MAC_LED_CTRL
, (tp
->led_ctrl
|
4036 LED_CTRL_LNKLED_OVERRIDE
|
4037 LED_CTRL_TRAFFIC_OVERRIDE
));
4040 if (current_link_up
!= netif_carrier_ok(tp
->dev
)) {
4041 if (current_link_up
)
4042 netif_carrier_on(tp
->dev
);
4044 netif_carrier_off(tp
->dev
);
4045 tg3_link_report(tp
);
4047 u32 now_pause_cfg
= tp
->link_config
.active_flowctrl
;
4048 if (orig_pause_cfg
!= now_pause_cfg
||
4049 orig_active_speed
!= tp
->link_config
.active_speed
||
4050 orig_active_duplex
!= tp
->link_config
.active_duplex
)
4051 tg3_link_report(tp
);
4057 static int tg3_setup_fiber_mii_phy(struct tg3
*tp
, int force_reset
)
4059 int current_link_up
, err
= 0;
4063 u32 local_adv
, remote_adv
;
4065 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
4066 tw32_f(MAC_MODE
, tp
->mac_mode
);
4072 (MAC_STATUS_SYNC_CHANGED
|
4073 MAC_STATUS_CFG_CHANGED
|
4074 MAC_STATUS_MI_COMPLETION
|
4075 MAC_STATUS_LNKSTATE_CHANGED
));
4081 current_link_up
= 0;
4082 current_speed
= SPEED_INVALID
;
4083 current_duplex
= DUPLEX_INVALID
;
4085 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
4086 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
4087 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
) {
4088 if (tr32(MAC_TX_STATUS
) & TX_STATUS_LINK_UP
)
4089 bmsr
|= BMSR_LSTATUS
;
4091 bmsr
&= ~BMSR_LSTATUS
;
4094 err
|= tg3_readphy(tp
, MII_BMCR
, &bmcr
);
4096 if ((tp
->link_config
.autoneg
== AUTONEG_ENABLE
) && !force_reset
&&
4097 (tp
->tg3_flags2
& TG3_FLG2_PARALLEL_DETECT
)) {
4098 /* do nothing, just check for link up at the end */
4099 } else if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) {
4102 err
|= tg3_readphy(tp
, MII_ADVERTISE
, &adv
);
4103 new_adv
= adv
& ~(ADVERTISE_1000XFULL
| ADVERTISE_1000XHALF
|
4104 ADVERTISE_1000XPAUSE
|
4105 ADVERTISE_1000XPSE_ASYM
|
4108 new_adv
|= tg3_advert_flowctrl_1000X(tp
->link_config
.flowctrl
);
4110 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Half
)
4111 new_adv
|= ADVERTISE_1000XHALF
;
4112 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Full
)
4113 new_adv
|= ADVERTISE_1000XFULL
;
4115 if ((new_adv
!= adv
) || !(bmcr
& BMCR_ANENABLE
)) {
4116 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
4117 bmcr
|= BMCR_ANENABLE
| BMCR_ANRESTART
;
4118 tg3_writephy(tp
, MII_BMCR
, bmcr
);
4120 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
4121 tp
->serdes_counter
= SERDES_AN_TIMEOUT_5714S
;
4122 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
4129 bmcr
&= ~BMCR_SPEED1000
;
4130 new_bmcr
= bmcr
& ~(BMCR_ANENABLE
| BMCR_FULLDPLX
);
4132 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
4133 new_bmcr
|= BMCR_FULLDPLX
;
4135 if (new_bmcr
!= bmcr
) {
4136 /* BMCR_SPEED1000 is a reserved bit that needs
4137 * to be set on write.
4139 new_bmcr
|= BMCR_SPEED1000
;
4141 /* Force a linkdown */
4142 if (netif_carrier_ok(tp
->dev
)) {
4145 err
|= tg3_readphy(tp
, MII_ADVERTISE
, &adv
);
4146 adv
&= ~(ADVERTISE_1000XFULL
|
4147 ADVERTISE_1000XHALF
|
4149 tg3_writephy(tp
, MII_ADVERTISE
, adv
);
4150 tg3_writephy(tp
, MII_BMCR
, bmcr
|
4154 netif_carrier_off(tp
->dev
);
4156 tg3_writephy(tp
, MII_BMCR
, new_bmcr
);
4158 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
4159 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
4160 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
4162 if (tr32(MAC_TX_STATUS
) & TX_STATUS_LINK_UP
)
4163 bmsr
|= BMSR_LSTATUS
;
4165 bmsr
&= ~BMSR_LSTATUS
;
4167 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
4171 if (bmsr
& BMSR_LSTATUS
) {
4172 current_speed
= SPEED_1000
;
4173 current_link_up
= 1;
4174 if (bmcr
& BMCR_FULLDPLX
)
4175 current_duplex
= DUPLEX_FULL
;
4177 current_duplex
= DUPLEX_HALF
;
4182 if (bmcr
& BMCR_ANENABLE
) {
4185 err
|= tg3_readphy(tp
, MII_ADVERTISE
, &local_adv
);
4186 err
|= tg3_readphy(tp
, MII_LPA
, &remote_adv
);
4187 common
= local_adv
& remote_adv
;
4188 if (common
& (ADVERTISE_1000XHALF
|
4189 ADVERTISE_1000XFULL
)) {
4190 if (common
& ADVERTISE_1000XFULL
)
4191 current_duplex
= DUPLEX_FULL
;
4193 current_duplex
= DUPLEX_HALF
;
4195 current_link_up
= 0;
4200 if (current_link_up
== 1 && current_duplex
== DUPLEX_FULL
)
4201 tg3_setup_flow_control(tp
, local_adv
, remote_adv
);
4203 tp
->mac_mode
&= ~MAC_MODE_HALF_DUPLEX
;
4204 if (tp
->link_config
.active_duplex
== DUPLEX_HALF
)
4205 tp
->mac_mode
|= MAC_MODE_HALF_DUPLEX
;
4207 tw32_f(MAC_MODE
, tp
->mac_mode
);
4210 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
4212 tp
->link_config
.active_speed
= current_speed
;
4213 tp
->link_config
.active_duplex
= current_duplex
;
4215 if (current_link_up
!= netif_carrier_ok(tp
->dev
)) {
4216 if (current_link_up
)
4217 netif_carrier_on(tp
->dev
);
4219 netif_carrier_off(tp
->dev
);
4220 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
4222 tg3_link_report(tp
);
4227 static void tg3_serdes_parallel_detect(struct tg3
*tp
)
4229 if (tp
->serdes_counter
) {
4230 /* Give autoneg time to complete. */
4231 tp
->serdes_counter
--;
4235 if (!netif_carrier_ok(tp
->dev
) &&
4236 (tp
->link_config
.autoneg
== AUTONEG_ENABLE
)) {
4239 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
4240 if (bmcr
& BMCR_ANENABLE
) {
4243 /* Select shadow register 0x1f */
4244 tg3_writephy(tp
, 0x1c, 0x7c00);
4245 tg3_readphy(tp
, 0x1c, &phy1
);
4247 /* Select expansion interrupt status register */
4248 tg3_writephy(tp
, 0x17, 0x0f01);
4249 tg3_readphy(tp
, 0x15, &phy2
);
4250 tg3_readphy(tp
, 0x15, &phy2
);
4252 if ((phy1
& 0x10) && !(phy2
& 0x20)) {
4253 /* We have signal detect and not receiving
4254 * config code words, link is up by parallel
4258 bmcr
&= ~BMCR_ANENABLE
;
4259 bmcr
|= BMCR_SPEED1000
| BMCR_FULLDPLX
;
4260 tg3_writephy(tp
, MII_BMCR
, bmcr
);
4261 tp
->tg3_flags2
|= TG3_FLG2_PARALLEL_DETECT
;
4264 } else if (netif_carrier_ok(tp
->dev
) &&
4265 (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) &&
4266 (tp
->tg3_flags2
& TG3_FLG2_PARALLEL_DETECT
)) {
4269 /* Select expansion interrupt status register */
4270 tg3_writephy(tp
, 0x17, 0x0f01);
4271 tg3_readphy(tp
, 0x15, &phy2
);
4275 /* Config code words received, turn on autoneg. */
4276 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
4277 tg3_writephy(tp
, MII_BMCR
, bmcr
| BMCR_ANENABLE
);
4279 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
4285 static int tg3_setup_phy(struct tg3
*tp
, int force_reset
)
4289 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)
4290 err
= tg3_setup_fiber_phy(tp
, force_reset
);
4291 else if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
)
4292 err
= tg3_setup_fiber_mii_phy(tp
, force_reset
);
4294 err
= tg3_setup_copper_phy(tp
, force_reset
);
4296 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
) {
4299 val
= tr32(TG3_CPMU_CLCK_STAT
) & CPMU_CLCK_STAT_MAC_CLCK_MASK
;
4300 if (val
== CPMU_CLCK_STAT_MAC_CLCK_62_5
)
4302 else if (val
== CPMU_CLCK_STAT_MAC_CLCK_6_25
)
4307 val
= tr32(GRC_MISC_CFG
) & ~GRC_MISC_CFG_PRESCALAR_MASK
;
4308 val
|= (scale
<< GRC_MISC_CFG_PRESCALAR_SHIFT
);
4309 tw32(GRC_MISC_CFG
, val
);
4312 if (tp
->link_config
.active_speed
== SPEED_1000
&&
4313 tp
->link_config
.active_duplex
== DUPLEX_HALF
)
4314 tw32(MAC_TX_LENGTHS
,
4315 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
4316 (6 << TX_LENGTHS_IPG_SHIFT
) |
4317 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT
)));
4319 tw32(MAC_TX_LENGTHS
,
4320 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
4321 (6 << TX_LENGTHS_IPG_SHIFT
) |
4322 (32 << TX_LENGTHS_SLOT_TIME_SHIFT
)));
4324 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
4325 if (netif_carrier_ok(tp
->dev
)) {
4326 tw32(HOSTCC_STAT_COAL_TICKS
,
4327 tp
->coal
.stats_block_coalesce_usecs
);
4329 tw32(HOSTCC_STAT_COAL_TICKS
, 0);
4333 if (tp
->tg3_flags
& TG3_FLAG_ASPM_WORKAROUND
) {
4334 u32 val
= tr32(PCIE_PWR_MGMT_THRESH
);
4335 if (!netif_carrier_ok(tp
->dev
))
4336 val
= (val
& ~PCIE_PWR_MGMT_L1_THRESH_MSK
) |
4339 val
|= PCIE_PWR_MGMT_L1_THRESH_MSK
;
4340 tw32(PCIE_PWR_MGMT_THRESH
, val
);
4346 /* This is called whenever we suspect that the system chipset is re-
4347 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4348 * is bogus tx completions. We try to recover by setting the
4349 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4352 static void tg3_tx_recover(struct tg3
*tp
)
4354 BUG_ON((tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
) ||
4355 tp
->write32_tx_mbox
== tg3_write_indirect_mbox
);
4357 netdev_warn(tp
->dev
,
4358 "The system may be re-ordering memory-mapped I/O "
4359 "cycles to the network device, attempting to recover. "
4360 "Please report the problem to the driver maintainer "
4361 "and include system chipset information.\n");
4363 spin_lock(&tp
->lock
);
4364 tp
->tg3_flags
|= TG3_FLAG_TX_RECOVERY_PENDING
;
4365 spin_unlock(&tp
->lock
);
4368 static inline u32
tg3_tx_avail(struct tg3_napi
*tnapi
)
4371 return tnapi
->tx_pending
-
4372 ((tnapi
->tx_prod
- tnapi
->tx_cons
) & (TG3_TX_RING_SIZE
- 1));
4375 /* Tigon3 never reports partial packet sends. So we do not
4376 * need special logic to handle SKBs that have not had all
4377 * of their frags sent yet, like SunGEM does.
4379 static void tg3_tx(struct tg3_napi
*tnapi
)
4381 struct tg3
*tp
= tnapi
->tp
;
4382 u32 hw_idx
= tnapi
->hw_status
->idx
[0].tx_consumer
;
4383 u32 sw_idx
= tnapi
->tx_cons
;
4384 struct netdev_queue
*txq
;
4385 int index
= tnapi
- tp
->napi
;
4387 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)
4390 txq
= netdev_get_tx_queue(tp
->dev
, index
);
4392 while (sw_idx
!= hw_idx
) {
4393 struct ring_info
*ri
= &tnapi
->tx_buffers
[sw_idx
];
4394 struct sk_buff
*skb
= ri
->skb
;
4397 if (unlikely(skb
== NULL
)) {
4402 pci_unmap_single(tp
->pdev
,
4403 pci_unmap_addr(ri
, mapping
),
4409 sw_idx
= NEXT_TX(sw_idx
);
4411 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
4412 ri
= &tnapi
->tx_buffers
[sw_idx
];
4413 if (unlikely(ri
->skb
!= NULL
|| sw_idx
== hw_idx
))
4416 pci_unmap_page(tp
->pdev
,
4417 pci_unmap_addr(ri
, mapping
),
4418 skb_shinfo(skb
)->frags
[i
].size
,
4420 sw_idx
= NEXT_TX(sw_idx
);
4425 if (unlikely(tx_bug
)) {
4431 tnapi
->tx_cons
= sw_idx
;
4433 /* Need to make the tx_cons update visible to tg3_start_xmit()
4434 * before checking for netif_queue_stopped(). Without the
4435 * memory barrier, there is a small possibility that tg3_start_xmit()
4436 * will miss it and cause the queue to be stopped forever.
4440 if (unlikely(netif_tx_queue_stopped(txq
) &&
4441 (tg3_tx_avail(tnapi
) > TG3_TX_WAKEUP_THRESH(tnapi
)))) {
4442 __netif_tx_lock(txq
, smp_processor_id());
4443 if (netif_tx_queue_stopped(txq
) &&
4444 (tg3_tx_avail(tnapi
) > TG3_TX_WAKEUP_THRESH(tnapi
)))
4445 netif_tx_wake_queue(txq
);
4446 __netif_tx_unlock(txq
);
4450 static void tg3_rx_skb_free(struct tg3
*tp
, struct ring_info
*ri
, u32 map_sz
)
4455 pci_unmap_single(tp
->pdev
, pci_unmap_addr(ri
, mapping
),
4456 map_sz
, PCI_DMA_FROMDEVICE
);
4457 dev_kfree_skb_any(ri
->skb
);
4461 /* Returns size of skb allocated or < 0 on error.
4463 * We only need to fill in the address because the other members
4464 * of the RX descriptor are invariant, see tg3_init_rings.
4466 * Note the purposeful assymetry of cpu vs. chip accesses. For
4467 * posting buffers we only dirty the first cache line of the RX
4468 * descriptor (containing the address). Whereas for the RX status
4469 * buffers the cpu only reads the last cacheline of the RX descriptor
4470 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4472 static int tg3_alloc_rx_skb(struct tg3
*tp
, struct tg3_rx_prodring_set
*tpr
,
4473 u32 opaque_key
, u32 dest_idx_unmasked
)
4475 struct tg3_rx_buffer_desc
*desc
;
4476 struct ring_info
*map
, *src_map
;
4477 struct sk_buff
*skb
;
4479 int skb_size
, dest_idx
;
4482 switch (opaque_key
) {
4483 case RXD_OPAQUE_RING_STD
:
4484 dest_idx
= dest_idx_unmasked
% TG3_RX_RING_SIZE
;
4485 desc
= &tpr
->rx_std
[dest_idx
];
4486 map
= &tpr
->rx_std_buffers
[dest_idx
];
4487 skb_size
= tp
->rx_pkt_map_sz
;
4490 case RXD_OPAQUE_RING_JUMBO
:
4491 dest_idx
= dest_idx_unmasked
% TG3_RX_JUMBO_RING_SIZE
;
4492 desc
= &tpr
->rx_jmb
[dest_idx
].std
;
4493 map
= &tpr
->rx_jmb_buffers
[dest_idx
];
4494 skb_size
= TG3_RX_JMB_MAP_SZ
;
4501 /* Do not overwrite any of the map or rp information
4502 * until we are sure we can commit to a new buffer.
4504 * Callers depend upon this behavior and assume that
4505 * we leave everything unchanged if we fail.
4507 skb
= netdev_alloc_skb(tp
->dev
, skb_size
+ tp
->rx_offset
);
4511 skb_reserve(skb
, tp
->rx_offset
);
4513 mapping
= pci_map_single(tp
->pdev
, skb
->data
, skb_size
,
4514 PCI_DMA_FROMDEVICE
);
4515 if (pci_dma_mapping_error(tp
->pdev
, mapping
)) {
4521 pci_unmap_addr_set(map
, mapping
, mapping
);
4523 desc
->addr_hi
= ((u64
)mapping
>> 32);
4524 desc
->addr_lo
= ((u64
)mapping
& 0xffffffff);
4529 /* We only need to move over in the address because the other
4530 * members of the RX descriptor are invariant. See notes above
4531 * tg3_alloc_rx_skb for full details.
4533 static void tg3_recycle_rx(struct tg3_napi
*tnapi
,
4534 struct tg3_rx_prodring_set
*dpr
,
4535 u32 opaque_key
, int src_idx
,
4536 u32 dest_idx_unmasked
)
4538 struct tg3
*tp
= tnapi
->tp
;
4539 struct tg3_rx_buffer_desc
*src_desc
, *dest_desc
;
4540 struct ring_info
*src_map
, *dest_map
;
4541 struct tg3_rx_prodring_set
*spr
= &tp
->prodring
[0];
4544 switch (opaque_key
) {
4545 case RXD_OPAQUE_RING_STD
:
4546 dest_idx
= dest_idx_unmasked
% TG3_RX_RING_SIZE
;
4547 dest_desc
= &dpr
->rx_std
[dest_idx
];
4548 dest_map
= &dpr
->rx_std_buffers
[dest_idx
];
4549 src_desc
= &spr
->rx_std
[src_idx
];
4550 src_map
= &spr
->rx_std_buffers
[src_idx
];
4553 case RXD_OPAQUE_RING_JUMBO
:
4554 dest_idx
= dest_idx_unmasked
% TG3_RX_JUMBO_RING_SIZE
;
4555 dest_desc
= &dpr
->rx_jmb
[dest_idx
].std
;
4556 dest_map
= &dpr
->rx_jmb_buffers
[dest_idx
];
4557 src_desc
= &spr
->rx_jmb
[src_idx
].std
;
4558 src_map
= &spr
->rx_jmb_buffers
[src_idx
];
4565 dest_map
->skb
= src_map
->skb
;
4566 pci_unmap_addr_set(dest_map
, mapping
,
4567 pci_unmap_addr(src_map
, mapping
));
4568 dest_desc
->addr_hi
= src_desc
->addr_hi
;
4569 dest_desc
->addr_lo
= src_desc
->addr_lo
;
4571 /* Ensure that the update to the skb happens after the physical
4572 * addresses have been transferred to the new BD location.
4576 src_map
->skb
= NULL
;
4579 /* The RX ring scheme is composed of multiple rings which post fresh
4580 * buffers to the chip, and one special ring the chip uses to report
4581 * status back to the host.
4583 * The special ring reports the status of received packets to the
4584 * host. The chip does not write into the original descriptor the
4585 * RX buffer was obtained from. The chip simply takes the original
4586 * descriptor as provided by the host, updates the status and length
4587 * field, then writes this into the next status ring entry.
4589 * Each ring the host uses to post buffers to the chip is described
4590 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4591 * it is first placed into the on-chip ram. When the packet's length
4592 * is known, it walks down the TG3_BDINFO entries to select the ring.
4593 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4594 * which is within the range of the new packet's length is chosen.
4596 * The "separate ring for rx status" scheme may sound queer, but it makes
4597 * sense from a cache coherency perspective. If only the host writes
4598 * to the buffer post rings, and only the chip writes to the rx status
4599 * rings, then cache lines never move beyond shared-modified state.
4600 * If both the host and chip were to write into the same ring, cache line
4601 * eviction could occur since both entities want it in an exclusive state.
4603 static int tg3_rx(struct tg3_napi
*tnapi
, int budget
)
4605 struct tg3
*tp
= tnapi
->tp
;
4606 u32 work_mask
, rx_std_posted
= 0;
4607 u32 std_prod_idx
, jmb_prod_idx
;
4608 u32 sw_idx
= tnapi
->rx_rcb_ptr
;
4611 struct tg3_rx_prodring_set
*tpr
= tnapi
->prodring
;
4613 hw_idx
= *(tnapi
->rx_rcb_prod_idx
);
4615 * We need to order the read of hw_idx and the read of
4616 * the opaque cookie.
4621 std_prod_idx
= tpr
->rx_std_prod_idx
;
4622 jmb_prod_idx
= tpr
->rx_jmb_prod_idx
;
4623 while (sw_idx
!= hw_idx
&& budget
> 0) {
4624 struct ring_info
*ri
;
4625 struct tg3_rx_buffer_desc
*desc
= &tnapi
->rx_rcb
[sw_idx
];
4627 struct sk_buff
*skb
;
4628 dma_addr_t dma_addr
;
4629 u32 opaque_key
, desc_idx
, *post_ptr
;
4630 bool hw_vlan __maybe_unused
= false;
4631 u16 vtag __maybe_unused
= 0;
4633 desc_idx
= desc
->opaque
& RXD_OPAQUE_INDEX_MASK
;
4634 opaque_key
= desc
->opaque
& RXD_OPAQUE_RING_MASK
;
4635 if (opaque_key
== RXD_OPAQUE_RING_STD
) {
4636 ri
= &tp
->prodring
[0].rx_std_buffers
[desc_idx
];
4637 dma_addr
= pci_unmap_addr(ri
, mapping
);
4639 post_ptr
= &std_prod_idx
;
4641 } else if (opaque_key
== RXD_OPAQUE_RING_JUMBO
) {
4642 ri
= &tp
->prodring
[0].rx_jmb_buffers
[desc_idx
];
4643 dma_addr
= pci_unmap_addr(ri
, mapping
);
4645 post_ptr
= &jmb_prod_idx
;
4647 goto next_pkt_nopost
;
4649 work_mask
|= opaque_key
;
4651 if ((desc
->err_vlan
& RXD_ERR_MASK
) != 0 &&
4652 (desc
->err_vlan
!= RXD_ERR_ODD_NIBBLE_RCVD_MII
)) {
4654 tg3_recycle_rx(tnapi
, tpr
, opaque_key
,
4655 desc_idx
, *post_ptr
);
4657 /* Other statistics kept track of by card. */
4658 tp
->net_stats
.rx_dropped
++;
4662 len
= ((desc
->idx_len
& RXD_LEN_MASK
) >> RXD_LEN_SHIFT
) -
4665 if (len
> TG3_RX_COPY_THRESH(tp
)) {
4668 skb_size
= tg3_alloc_rx_skb(tp
, tpr
, opaque_key
,
4673 pci_unmap_single(tp
->pdev
, dma_addr
, skb_size
,
4674 PCI_DMA_FROMDEVICE
);
4676 /* Ensure that the update to the skb happens
4677 * after the usage of the old DMA mapping.
4685 struct sk_buff
*copy_skb
;
4687 tg3_recycle_rx(tnapi
, tpr
, opaque_key
,
4688 desc_idx
, *post_ptr
);
4690 copy_skb
= netdev_alloc_skb(tp
->dev
, len
+ VLAN_HLEN
+
4692 if (copy_skb
== NULL
)
4693 goto drop_it_no_recycle
;
4695 skb_reserve(copy_skb
, TG3_RAW_IP_ALIGN
+ VLAN_HLEN
);
4696 skb_put(copy_skb
, len
);
4697 pci_dma_sync_single_for_cpu(tp
->pdev
, dma_addr
, len
, PCI_DMA_FROMDEVICE
);
4698 skb_copy_from_linear_data(skb
, copy_skb
->data
, len
);
4699 pci_dma_sync_single_for_device(tp
->pdev
, dma_addr
, len
, PCI_DMA_FROMDEVICE
);
4701 /* We'll reuse the original ring buffer. */
4705 if ((tp
->tg3_flags
& TG3_FLAG_RX_CHECKSUMS
) &&
4706 (desc
->type_flags
& RXD_FLAG_TCPUDP_CSUM
) &&
4707 (((desc
->ip_tcp_csum
& RXD_TCPCSUM_MASK
)
4708 >> RXD_TCPCSUM_SHIFT
) == 0xffff))
4709 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
4711 skb
->ip_summed
= CHECKSUM_NONE
;
4713 skb
->protocol
= eth_type_trans(skb
, tp
->dev
);
4715 if (len
> (tp
->dev
->mtu
+ ETH_HLEN
) &&
4716 skb
->protocol
!= htons(ETH_P_8021Q
)) {
4721 if (desc
->type_flags
& RXD_FLAG_VLAN
&&
4722 !(tp
->rx_mode
& RX_MODE_KEEP_VLAN_TAG
)) {
4723 vtag
= desc
->err_vlan
& RXD_VLAN_MASK
;
4724 #if TG3_VLAN_TAG_USED
4730 struct vlan_ethhdr
*ve
= (struct vlan_ethhdr
*)
4731 __skb_push(skb
, VLAN_HLEN
);
4733 memmove(ve
, skb
->data
+ VLAN_HLEN
,
4735 ve
->h_vlan_proto
= htons(ETH_P_8021Q
);
4736 ve
->h_vlan_TCI
= htons(vtag
);
4740 #if TG3_VLAN_TAG_USED
4742 vlan_gro_receive(&tnapi
->napi
, tp
->vlgrp
, vtag
, skb
);
4745 napi_gro_receive(&tnapi
->napi
, skb
);
4753 if (unlikely(rx_std_posted
>= tp
->rx_std_max_post
)) {
4754 tpr
->rx_std_prod_idx
= std_prod_idx
% TG3_RX_RING_SIZE
;
4755 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG
,
4756 tpr
->rx_std_prod_idx
);
4757 work_mask
&= ~RXD_OPAQUE_RING_STD
;
4762 sw_idx
&= (TG3_RX_RCB_RING_SIZE(tp
) - 1);
4764 /* Refresh hw_idx to see if there is new work */
4765 if (sw_idx
== hw_idx
) {
4766 hw_idx
= *(tnapi
->rx_rcb_prod_idx
);
4771 /* ACK the status ring. */
4772 tnapi
->rx_rcb_ptr
= sw_idx
;
4773 tw32_rx_mbox(tnapi
->consmbox
, sw_idx
);
4775 /* Refill RX ring(s). */
4776 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_RSS
)) {
4777 if (work_mask
& RXD_OPAQUE_RING_STD
) {
4778 tpr
->rx_std_prod_idx
= std_prod_idx
% TG3_RX_RING_SIZE
;
4779 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG
,
4780 tpr
->rx_std_prod_idx
);
4782 if (work_mask
& RXD_OPAQUE_RING_JUMBO
) {
4783 tpr
->rx_jmb_prod_idx
= jmb_prod_idx
%
4784 TG3_RX_JUMBO_RING_SIZE
;
4785 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG
,
4786 tpr
->rx_jmb_prod_idx
);
4789 } else if (work_mask
) {
4790 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4791 * updated before the producer indices can be updated.
4795 tpr
->rx_std_prod_idx
= std_prod_idx
% TG3_RX_RING_SIZE
;
4796 tpr
->rx_jmb_prod_idx
= jmb_prod_idx
% TG3_RX_JUMBO_RING_SIZE
;
4798 if (tnapi
!= &tp
->napi
[1])
4799 napi_schedule(&tp
->napi
[1].napi
);
4805 static void tg3_poll_link(struct tg3
*tp
)
4807 /* handle link change and other phy events */
4808 if (!(tp
->tg3_flags
&
4809 (TG3_FLAG_USE_LINKCHG_REG
|
4810 TG3_FLAG_POLL_SERDES
))) {
4811 struct tg3_hw_status
*sblk
= tp
->napi
[0].hw_status
;
4813 if (sblk
->status
& SD_STATUS_LINK_CHG
) {
4814 sblk
->status
= SD_STATUS_UPDATED
|
4815 (sblk
->status
& ~SD_STATUS_LINK_CHG
);
4816 spin_lock(&tp
->lock
);
4817 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
4819 (MAC_STATUS_SYNC_CHANGED
|
4820 MAC_STATUS_CFG_CHANGED
|
4821 MAC_STATUS_MI_COMPLETION
|
4822 MAC_STATUS_LNKSTATE_CHANGED
));
4825 tg3_setup_phy(tp
, 0);
4826 spin_unlock(&tp
->lock
);
4831 static int tg3_rx_prodring_xfer(struct tg3
*tp
,
4832 struct tg3_rx_prodring_set
*dpr
,
4833 struct tg3_rx_prodring_set
*spr
)
4835 u32 si
, di
, cpycnt
, src_prod_idx
;
4839 src_prod_idx
= spr
->rx_std_prod_idx
;
4841 /* Make sure updates to the rx_std_buffers[] entries and the
4842 * standard producer index are seen in the correct order.
4846 if (spr
->rx_std_cons_idx
== src_prod_idx
)
4849 if (spr
->rx_std_cons_idx
< src_prod_idx
)
4850 cpycnt
= src_prod_idx
- spr
->rx_std_cons_idx
;
4852 cpycnt
= TG3_RX_RING_SIZE
- spr
->rx_std_cons_idx
;
4854 cpycnt
= min(cpycnt
, TG3_RX_RING_SIZE
- dpr
->rx_std_prod_idx
);
4856 si
= spr
->rx_std_cons_idx
;
4857 di
= dpr
->rx_std_prod_idx
;
4859 for (i
= di
; i
< di
+ cpycnt
; i
++) {
4860 if (dpr
->rx_std_buffers
[i
].skb
) {
4870 /* Ensure that updates to the rx_std_buffers ring and the
4871 * shadowed hardware producer ring from tg3_recycle_skb() are
4872 * ordered correctly WRT the skb check above.
4876 memcpy(&dpr
->rx_std_buffers
[di
],
4877 &spr
->rx_std_buffers
[si
],
4878 cpycnt
* sizeof(struct ring_info
));
4880 for (i
= 0; i
< cpycnt
; i
++, di
++, si
++) {
4881 struct tg3_rx_buffer_desc
*sbd
, *dbd
;
4882 sbd
= &spr
->rx_std
[si
];
4883 dbd
= &dpr
->rx_std
[di
];
4884 dbd
->addr_hi
= sbd
->addr_hi
;
4885 dbd
->addr_lo
= sbd
->addr_lo
;
4888 spr
->rx_std_cons_idx
= (spr
->rx_std_cons_idx
+ cpycnt
) %
4890 dpr
->rx_std_prod_idx
= (dpr
->rx_std_prod_idx
+ cpycnt
) %
4895 src_prod_idx
= spr
->rx_jmb_prod_idx
;
4897 /* Make sure updates to the rx_jmb_buffers[] entries and
4898 * the jumbo producer index are seen in the correct order.
4902 if (spr
->rx_jmb_cons_idx
== src_prod_idx
)
4905 if (spr
->rx_jmb_cons_idx
< src_prod_idx
)
4906 cpycnt
= src_prod_idx
- spr
->rx_jmb_cons_idx
;
4908 cpycnt
= TG3_RX_JUMBO_RING_SIZE
- spr
->rx_jmb_cons_idx
;
4910 cpycnt
= min(cpycnt
,
4911 TG3_RX_JUMBO_RING_SIZE
- dpr
->rx_jmb_prod_idx
);
4913 si
= spr
->rx_jmb_cons_idx
;
4914 di
= dpr
->rx_jmb_prod_idx
;
4916 for (i
= di
; i
< di
+ cpycnt
; i
++) {
4917 if (dpr
->rx_jmb_buffers
[i
].skb
) {
4927 /* Ensure that updates to the rx_jmb_buffers ring and the
4928 * shadowed hardware producer ring from tg3_recycle_skb() are
4929 * ordered correctly WRT the skb check above.
4933 memcpy(&dpr
->rx_jmb_buffers
[di
],
4934 &spr
->rx_jmb_buffers
[si
],
4935 cpycnt
* sizeof(struct ring_info
));
4937 for (i
= 0; i
< cpycnt
; i
++, di
++, si
++) {
4938 struct tg3_rx_buffer_desc
*sbd
, *dbd
;
4939 sbd
= &spr
->rx_jmb
[si
].std
;
4940 dbd
= &dpr
->rx_jmb
[di
].std
;
4941 dbd
->addr_hi
= sbd
->addr_hi
;
4942 dbd
->addr_lo
= sbd
->addr_lo
;
4945 spr
->rx_jmb_cons_idx
= (spr
->rx_jmb_cons_idx
+ cpycnt
) %
4946 TG3_RX_JUMBO_RING_SIZE
;
4947 dpr
->rx_jmb_prod_idx
= (dpr
->rx_jmb_prod_idx
+ cpycnt
) %
4948 TG3_RX_JUMBO_RING_SIZE
;
4954 static int tg3_poll_work(struct tg3_napi
*tnapi
, int work_done
, int budget
)
4956 struct tg3
*tp
= tnapi
->tp
;
4958 /* run TX completion thread */
4959 if (tnapi
->hw_status
->idx
[0].tx_consumer
!= tnapi
->tx_cons
) {
4961 if (unlikely(tp
->tg3_flags
& TG3_FLAG_TX_RECOVERY_PENDING
))
4965 /* run RX thread, within the bounds set by NAPI.
4966 * All RX "locking" is done by ensuring outside
4967 * code synchronizes with tg3->napi.poll()
4969 if (*(tnapi
->rx_rcb_prod_idx
) != tnapi
->rx_rcb_ptr
)
4970 work_done
+= tg3_rx(tnapi
, budget
- work_done
);
4972 if ((tp
->tg3_flags3
& TG3_FLG3_ENABLE_RSS
) && tnapi
== &tp
->napi
[1]) {
4973 struct tg3_rx_prodring_set
*dpr
= &tp
->prodring
[0];
4975 u32 std_prod_idx
= dpr
->rx_std_prod_idx
;
4976 u32 jmb_prod_idx
= dpr
->rx_jmb_prod_idx
;
4978 for (i
= 1; i
< tp
->irq_cnt
; i
++)
4979 err
|= tg3_rx_prodring_xfer(tp
, dpr
,
4980 tp
->napi
[i
].prodring
);
4984 if (std_prod_idx
!= dpr
->rx_std_prod_idx
)
4985 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG
,
4986 dpr
->rx_std_prod_idx
);
4988 if (jmb_prod_idx
!= dpr
->rx_jmb_prod_idx
)
4989 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG
,
4990 dpr
->rx_jmb_prod_idx
);
4995 tw32_f(HOSTCC_MODE
, tp
->coal_now
);
5001 static int tg3_poll_msix(struct napi_struct
*napi
, int budget
)
5003 struct tg3_napi
*tnapi
= container_of(napi
, struct tg3_napi
, napi
);
5004 struct tg3
*tp
= tnapi
->tp
;
5006 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
5009 work_done
= tg3_poll_work(tnapi
, work_done
, budget
);
5011 if (unlikely(tp
->tg3_flags
& TG3_FLAG_TX_RECOVERY_PENDING
))
5014 if (unlikely(work_done
>= budget
))
5017 /* tp->last_tag is used in tg3_int_reenable() below
5018 * to tell the hw how much work has been processed,
5019 * so we must read it before checking for more work.
5021 tnapi
->last_tag
= sblk
->status_tag
;
5022 tnapi
->last_irq_tag
= tnapi
->last_tag
;
5025 /* check for RX/TX work to do */
5026 if (likely(sblk
->idx
[0].tx_consumer
== tnapi
->tx_cons
&&
5027 *(tnapi
->rx_rcb_prod_idx
) == tnapi
->rx_rcb_ptr
)) {
5028 napi_complete(napi
);
5029 /* Reenable interrupts. */
5030 tw32_mailbox(tnapi
->int_mbox
, tnapi
->last_tag
<< 24);
5039 /* work_done is guaranteed to be less than budget. */
5040 napi_complete(napi
);
5041 schedule_work(&tp
->reset_task
);
5045 static int tg3_poll(struct napi_struct
*napi
, int budget
)
5047 struct tg3_napi
*tnapi
= container_of(napi
, struct tg3_napi
, napi
);
5048 struct tg3
*tp
= tnapi
->tp
;
5050 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
5055 work_done
= tg3_poll_work(tnapi
, work_done
, budget
);
5057 if (unlikely(tp
->tg3_flags
& TG3_FLAG_TX_RECOVERY_PENDING
))
5060 if (unlikely(work_done
>= budget
))
5063 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) {
5064 /* tp->last_tag is used in tg3_int_reenable() below
5065 * to tell the hw how much work has been processed,
5066 * so we must read it before checking for more work.
5068 tnapi
->last_tag
= sblk
->status_tag
;
5069 tnapi
->last_irq_tag
= tnapi
->last_tag
;
5072 sblk
->status
&= ~SD_STATUS_UPDATED
;
5074 if (likely(!tg3_has_work(tnapi
))) {
5075 napi_complete(napi
);
5076 tg3_int_reenable(tnapi
);
5084 /* work_done is guaranteed to be less than budget. */
5085 napi_complete(napi
);
5086 schedule_work(&tp
->reset_task
);
5090 static void tg3_irq_quiesce(struct tg3
*tp
)
5094 BUG_ON(tp
->irq_sync
);
5099 for (i
= 0; i
< tp
->irq_cnt
; i
++)
5100 synchronize_irq(tp
->napi
[i
].irq_vec
);
5103 static inline int tg3_irq_sync(struct tg3
*tp
)
5105 return tp
->irq_sync
;
5108 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5109 * If irq_sync is non-zero, then the IRQ handler must be synchronized
5110 * with as well. Most of the time, this is not necessary except when
5111 * shutting down the device.
5113 static inline void tg3_full_lock(struct tg3
*tp
, int irq_sync
)
5115 spin_lock_bh(&tp
->lock
);
5117 tg3_irq_quiesce(tp
);
5120 static inline void tg3_full_unlock(struct tg3
*tp
)
5122 spin_unlock_bh(&tp
->lock
);
5125 /* One-shot MSI handler - Chip automatically disables interrupt
5126 * after sending MSI so driver doesn't have to do it.
5128 static irqreturn_t
tg3_msi_1shot(int irq
, void *dev_id
)
5130 struct tg3_napi
*tnapi
= dev_id
;
5131 struct tg3
*tp
= tnapi
->tp
;
5133 prefetch(tnapi
->hw_status
);
5135 prefetch(&tnapi
->rx_rcb
[tnapi
->rx_rcb_ptr
]);
5137 if (likely(!tg3_irq_sync(tp
)))
5138 napi_schedule(&tnapi
->napi
);
5143 /* MSI ISR - No need to check for interrupt sharing and no need to
5144 * flush status block and interrupt mailbox. PCI ordering rules
5145 * guarantee that MSI will arrive after the status block.
5147 static irqreturn_t
tg3_msi(int irq
, void *dev_id
)
5149 struct tg3_napi
*tnapi
= dev_id
;
5150 struct tg3
*tp
= tnapi
->tp
;
5152 prefetch(tnapi
->hw_status
);
5154 prefetch(&tnapi
->rx_rcb
[tnapi
->rx_rcb_ptr
]);
5156 * Writing any value to intr-mbox-0 clears PCI INTA# and
5157 * chip-internal interrupt pending events.
5158 * Writing non-zero to intr-mbox-0 additional tells the
5159 * NIC to stop sending us irqs, engaging "in-intr-handler"
5162 tw32_mailbox(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0x00000001);
5163 if (likely(!tg3_irq_sync(tp
)))
5164 napi_schedule(&tnapi
->napi
);
5166 return IRQ_RETVAL(1);
5169 static irqreturn_t
tg3_interrupt(int irq
, void *dev_id
)
5171 struct tg3_napi
*tnapi
= dev_id
;
5172 struct tg3
*tp
= tnapi
->tp
;
5173 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
5174 unsigned int handled
= 1;
5176 /* In INTx mode, it is possible for the interrupt to arrive at
5177 * the CPU before the status block posted prior to the interrupt.
5178 * Reading the PCI State register will confirm whether the
5179 * interrupt is ours and will flush the status block.
5181 if (unlikely(!(sblk
->status
& SD_STATUS_UPDATED
))) {
5182 if ((tp
->tg3_flags
& TG3_FLAG_CHIP_RESETTING
) ||
5183 (tr32(TG3PCI_PCISTATE
) & PCISTATE_INT_NOT_ACTIVE
)) {
5190 * Writing any value to intr-mbox-0 clears PCI INTA# and
5191 * chip-internal interrupt pending events.
5192 * Writing non-zero to intr-mbox-0 additional tells the
5193 * NIC to stop sending us irqs, engaging "in-intr-handler"
5196 * Flush the mailbox to de-assert the IRQ immediately to prevent
5197 * spurious interrupts. The flush impacts performance but
5198 * excessive spurious interrupts can be worse in some cases.
5200 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0x00000001);
5201 if (tg3_irq_sync(tp
))
5203 sblk
->status
&= ~SD_STATUS_UPDATED
;
5204 if (likely(tg3_has_work(tnapi
))) {
5205 prefetch(&tnapi
->rx_rcb
[tnapi
->rx_rcb_ptr
]);
5206 napi_schedule(&tnapi
->napi
);
5208 /* No work, shared interrupt perhaps? re-enable
5209 * interrupts, and flush that PCI write
5211 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
,
5215 return IRQ_RETVAL(handled
);
5218 static irqreturn_t
tg3_interrupt_tagged(int irq
, void *dev_id
)
5220 struct tg3_napi
*tnapi
= dev_id
;
5221 struct tg3
*tp
= tnapi
->tp
;
5222 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
5223 unsigned int handled
= 1;
5225 /* In INTx mode, it is possible for the interrupt to arrive at
5226 * the CPU before the status block posted prior to the interrupt.
5227 * Reading the PCI State register will confirm whether the
5228 * interrupt is ours and will flush the status block.
5230 if (unlikely(sblk
->status_tag
== tnapi
->last_irq_tag
)) {
5231 if ((tp
->tg3_flags
& TG3_FLAG_CHIP_RESETTING
) ||
5232 (tr32(TG3PCI_PCISTATE
) & PCISTATE_INT_NOT_ACTIVE
)) {
5239 * writing any value to intr-mbox-0 clears PCI INTA# and
5240 * chip-internal interrupt pending events.
5241 * writing non-zero to intr-mbox-0 additional tells the
5242 * NIC to stop sending us irqs, engaging "in-intr-handler"
5245 * Flush the mailbox to de-assert the IRQ immediately to prevent
5246 * spurious interrupts. The flush impacts performance but
5247 * excessive spurious interrupts can be worse in some cases.
5249 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0x00000001);
5252 * In a shared interrupt configuration, sometimes other devices'
5253 * interrupts will scream. We record the current status tag here
5254 * so that the above check can report that the screaming interrupts
5255 * are unhandled. Eventually they will be silenced.
5257 tnapi
->last_irq_tag
= sblk
->status_tag
;
5259 if (tg3_irq_sync(tp
))
5262 prefetch(&tnapi
->rx_rcb
[tnapi
->rx_rcb_ptr
]);
5264 napi_schedule(&tnapi
->napi
);
5267 return IRQ_RETVAL(handled
);
5270 /* ISR for interrupt test */
5271 static irqreturn_t
tg3_test_isr(int irq
, void *dev_id
)
5273 struct tg3_napi
*tnapi
= dev_id
;
5274 struct tg3
*tp
= tnapi
->tp
;
5275 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
5277 if ((sblk
->status
& SD_STATUS_UPDATED
) ||
5278 !(tr32(TG3PCI_PCISTATE
) & PCISTATE_INT_NOT_ACTIVE
)) {
5279 tg3_disable_ints(tp
);
5280 return IRQ_RETVAL(1);
5282 return IRQ_RETVAL(0);
5285 static int tg3_init_hw(struct tg3
*, int);
5286 static int tg3_halt(struct tg3
*, int, int);
5288 /* Restart hardware after configuration changes, self-test, etc.
5289 * Invoked with tp->lock held.
5291 static int tg3_restart_hw(struct tg3
*tp
, int reset_phy
)
5292 __releases(tp
->lock
)
5293 __acquires(tp
->lock
)
5297 err
= tg3_init_hw(tp
, reset_phy
);
5300 "Failed to re-initialize device, aborting\n");
5301 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
5302 tg3_full_unlock(tp
);
5303 del_timer_sync(&tp
->timer
);
5305 tg3_napi_enable(tp
);
5307 tg3_full_lock(tp
, 0);
5312 #ifdef CONFIG_NET_POLL_CONTROLLER
5313 static void tg3_poll_controller(struct net_device
*dev
)
5316 struct tg3
*tp
= netdev_priv(dev
);
5318 for (i
= 0; i
< tp
->irq_cnt
; i
++)
5319 tg3_interrupt(tp
->napi
[i
].irq_vec
, &tp
->napi
[i
]);
5323 static void tg3_reset_task(struct work_struct
*work
)
5325 struct tg3
*tp
= container_of(work
, struct tg3
, reset_task
);
5327 unsigned int restart_timer
;
5329 tg3_full_lock(tp
, 0);
5331 if (!netif_running(tp
->dev
)) {
5332 tg3_full_unlock(tp
);
5336 tg3_full_unlock(tp
);
5342 tg3_full_lock(tp
, 1);
5344 restart_timer
= tp
->tg3_flags2
& TG3_FLG2_RESTART_TIMER
;
5345 tp
->tg3_flags2
&= ~TG3_FLG2_RESTART_TIMER
;
5347 if (tp
->tg3_flags
& TG3_FLAG_TX_RECOVERY_PENDING
) {
5348 tp
->write32_tx_mbox
= tg3_write32_tx_mbox
;
5349 tp
->write32_rx_mbox
= tg3_write_flush_reg32
;
5350 tp
->tg3_flags
|= TG3_FLAG_MBOX_WRITE_REORDER
;
5351 tp
->tg3_flags
&= ~TG3_FLAG_TX_RECOVERY_PENDING
;
5354 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 0);
5355 err
= tg3_init_hw(tp
, 1);
5359 tg3_netif_start(tp
);
5362 mod_timer(&tp
->timer
, jiffies
+ 1);
5365 tg3_full_unlock(tp
);
5371 static void tg3_dump_short_state(struct tg3
*tp
)
5373 netdev_err(tp
->dev
, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5374 tr32(MAC_TX_STATUS
), tr32(MAC_RX_STATUS
));
5375 netdev_err(tp
->dev
, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5376 tr32(RDMAC_STATUS
), tr32(WDMAC_STATUS
));
5379 static void tg3_tx_timeout(struct net_device
*dev
)
5381 struct tg3
*tp
= netdev_priv(dev
);
5383 if (netif_msg_tx_err(tp
)) {
5384 netdev_err(dev
, "transmit timed out, resetting\n");
5385 tg3_dump_short_state(tp
);
5388 schedule_work(&tp
->reset_task
);
5391 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5392 static inline int tg3_4g_overflow_test(dma_addr_t mapping
, int len
)
5394 u32 base
= (u32
) mapping
& 0xffffffff;
5396 return ((base
> 0xffffdcc0) &&
5397 (base
+ len
+ 8 < base
));
5400 /* Test for DMA addresses > 40-bit */
5401 static inline int tg3_40bit_overflow_test(struct tg3
*tp
, dma_addr_t mapping
,
5404 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5405 if (tp
->tg3_flags
& TG3_FLAG_40BIT_DMA_BUG
)
5406 return (((u64
) mapping
+ len
) > DMA_BIT_MASK(40));
5413 static void tg3_set_txd(struct tg3_napi
*, int, dma_addr_t
, int, u32
, u32
);
5415 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5416 static int tigon3_dma_hwbug_workaround(struct tg3_napi
*tnapi
,
5417 struct sk_buff
*skb
, u32 last_plus_one
,
5418 u32
*start
, u32 base_flags
, u32 mss
)
5420 struct tg3
*tp
= tnapi
->tp
;
5421 struct sk_buff
*new_skb
;
5422 dma_addr_t new_addr
= 0;
5426 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
)
5427 new_skb
= skb_copy(skb
, GFP_ATOMIC
);
5429 int more_headroom
= 4 - ((unsigned long)skb
->data
& 3);
5431 new_skb
= skb_copy_expand(skb
,
5432 skb_headroom(skb
) + more_headroom
,
5433 skb_tailroom(skb
), GFP_ATOMIC
);
5439 /* New SKB is guaranteed to be linear. */
5441 new_addr
= pci_map_single(tp
->pdev
, new_skb
->data
, new_skb
->len
,
5443 /* Make sure the mapping succeeded */
5444 if (pci_dma_mapping_error(tp
->pdev
, new_addr
)) {
5446 dev_kfree_skb(new_skb
);
5449 /* Make sure new skb does not cross any 4G boundaries.
5450 * Drop the packet if it does.
5452 } else if ((tp
->tg3_flags3
& TG3_FLG3_4G_DMA_BNDRY_BUG
) &&
5453 tg3_4g_overflow_test(new_addr
, new_skb
->len
)) {
5454 pci_unmap_single(tp
->pdev
, new_addr
, new_skb
->len
,
5457 dev_kfree_skb(new_skb
);
5460 tg3_set_txd(tnapi
, entry
, new_addr
, new_skb
->len
,
5461 base_flags
, 1 | (mss
<< 1));
5462 *start
= NEXT_TX(entry
);
5466 /* Now clean up the sw ring entries. */
5468 while (entry
!= last_plus_one
) {
5472 len
= skb_headlen(skb
);
5474 len
= skb_shinfo(skb
)->frags
[i
-1].size
;
5476 pci_unmap_single(tp
->pdev
,
5477 pci_unmap_addr(&tnapi
->tx_buffers
[entry
],
5479 len
, PCI_DMA_TODEVICE
);
5481 tnapi
->tx_buffers
[entry
].skb
= new_skb
;
5482 pci_unmap_addr_set(&tnapi
->tx_buffers
[entry
], mapping
,
5485 tnapi
->tx_buffers
[entry
].skb
= NULL
;
5487 entry
= NEXT_TX(entry
);
5496 static void tg3_set_txd(struct tg3_napi
*tnapi
, int entry
,
5497 dma_addr_t mapping
, int len
, u32 flags
,
5500 struct tg3_tx_buffer_desc
*txd
= &tnapi
->tx_ring
[entry
];
5501 int is_end
= (mss_and_is_end
& 0x1);
5502 u32 mss
= (mss_and_is_end
>> 1);
5506 flags
|= TXD_FLAG_END
;
5507 if (flags
& TXD_FLAG_VLAN
) {
5508 vlan_tag
= flags
>> 16;
5511 vlan_tag
|= (mss
<< TXD_MSS_SHIFT
);
5513 txd
->addr_hi
= ((u64
) mapping
>> 32);
5514 txd
->addr_lo
= ((u64
) mapping
& 0xffffffff);
5515 txd
->len_flags
= (len
<< TXD_LEN_SHIFT
) | flags
;
5516 txd
->vlan_tag
= vlan_tag
<< TXD_VLAN_TAG_SHIFT
;
5519 /* hard_start_xmit for devices that don't have any bugs and
5520 * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5522 static netdev_tx_t
tg3_start_xmit(struct sk_buff
*skb
,
5523 struct net_device
*dev
)
5525 struct tg3
*tp
= netdev_priv(dev
);
5526 u32 len
, entry
, base_flags
, mss
;
5528 struct tg3_napi
*tnapi
;
5529 struct netdev_queue
*txq
;
5530 unsigned int i
, last
;
5532 txq
= netdev_get_tx_queue(dev
, skb_get_queue_mapping(skb
));
5533 tnapi
= &tp
->napi
[skb_get_queue_mapping(skb
)];
5534 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)
5537 /* We are running in BH disabled context with netif_tx_lock
5538 * and TX reclaim runs via tp->napi.poll inside of a software
5539 * interrupt. Furthermore, IRQ processing runs lockless so we have
5540 * no IRQ context deadlocks to worry about either. Rejoice!
5542 if (unlikely(tg3_tx_avail(tnapi
) <= (skb_shinfo(skb
)->nr_frags
+ 1))) {
5543 if (!netif_tx_queue_stopped(txq
)) {
5544 netif_tx_stop_queue(txq
);
5546 /* This is a hard error, log it. */
5548 "BUG! Tx Ring full when queue awake!\n");
5550 return NETDEV_TX_BUSY
;
5553 entry
= tnapi
->tx_prod
;
5556 if ((mss
= skb_shinfo(skb
)->gso_size
) != 0) {
5557 int tcp_opt_len
, ip_tcp_len
;
5560 if (skb_header_cloned(skb
) &&
5561 pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
)) {
5566 if (skb_shinfo(skb
)->gso_type
& SKB_GSO_TCPV6
)
5567 hdrlen
= skb_headlen(skb
) - ETH_HLEN
;
5569 struct iphdr
*iph
= ip_hdr(skb
);
5571 tcp_opt_len
= tcp_optlen(skb
);
5572 ip_tcp_len
= ip_hdrlen(skb
) + sizeof(struct tcphdr
);
5575 iph
->tot_len
= htons(mss
+ ip_tcp_len
+ tcp_opt_len
);
5576 hdrlen
= ip_tcp_len
+ tcp_opt_len
;
5579 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO_3
) {
5580 mss
|= (hdrlen
& 0xc) << 12;
5582 base_flags
|= 0x00000010;
5583 base_flags
|= (hdrlen
& 0x3e0) << 5;
5587 base_flags
|= (TXD_FLAG_CPU_PRE_DMA
|
5588 TXD_FLAG_CPU_POST_DMA
);
5590 tcp_hdr(skb
)->check
= 0;
5592 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
5593 base_flags
|= TXD_FLAG_TCPUDP_CSUM
;
5596 #if TG3_VLAN_TAG_USED
5597 if (tp
->vlgrp
!= NULL
&& vlan_tx_tag_present(skb
))
5598 base_flags
|= (TXD_FLAG_VLAN
|
5599 (vlan_tx_tag_get(skb
) << 16));
5602 len
= skb_headlen(skb
);
5604 /* Queue skb data, a.k.a. the main skb fragment. */
5605 mapping
= pci_map_single(tp
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
5606 if (pci_dma_mapping_error(tp
->pdev
, mapping
)) {
5611 tnapi
->tx_buffers
[entry
].skb
= skb
;
5612 pci_unmap_addr_set(&tnapi
->tx_buffers
[entry
], mapping
, mapping
);
5614 if ((tp
->tg3_flags3
& TG3_FLG3_USE_JUMBO_BDFLAG
) &&
5615 !mss
&& skb
->len
> ETH_DATA_LEN
)
5616 base_flags
|= TXD_FLAG_JMB_PKT
;
5618 tg3_set_txd(tnapi
, entry
, mapping
, len
, base_flags
,
5619 (skb_shinfo(skb
)->nr_frags
== 0) | (mss
<< 1));
5621 entry
= NEXT_TX(entry
);
5623 /* Now loop through additional data fragments, and queue them. */
5624 if (skb_shinfo(skb
)->nr_frags
> 0) {
5625 last
= skb_shinfo(skb
)->nr_frags
- 1;
5626 for (i
= 0; i
<= last
; i
++) {
5627 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
5630 mapping
= pci_map_page(tp
->pdev
,
5633 len
, PCI_DMA_TODEVICE
);
5634 if (pci_dma_mapping_error(tp
->pdev
, mapping
))
5637 tnapi
->tx_buffers
[entry
].skb
= NULL
;
5638 pci_unmap_addr_set(&tnapi
->tx_buffers
[entry
], mapping
,
5641 tg3_set_txd(tnapi
, entry
, mapping
, len
,
5642 base_flags
, (i
== last
) | (mss
<< 1));
5644 entry
= NEXT_TX(entry
);
5648 /* Packets are ready, update Tx producer idx local and on card. */
5649 tw32_tx_mbox(tnapi
->prodmbox
, entry
);
5651 tnapi
->tx_prod
= entry
;
5652 if (unlikely(tg3_tx_avail(tnapi
) <= (MAX_SKB_FRAGS
+ 1))) {
5653 netif_tx_stop_queue(txq
);
5654 if (tg3_tx_avail(tnapi
) > TG3_TX_WAKEUP_THRESH(tnapi
))
5655 netif_tx_wake_queue(txq
);
5661 return NETDEV_TX_OK
;
5665 entry
= tnapi
->tx_prod
;
5666 tnapi
->tx_buffers
[entry
].skb
= NULL
;
5667 pci_unmap_single(tp
->pdev
,
5668 pci_unmap_addr(&tnapi
->tx_buffers
[entry
], mapping
),
5671 for (i
= 0; i
<= last
; i
++) {
5672 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
5673 entry
= NEXT_TX(entry
);
5675 pci_unmap_page(tp
->pdev
,
5676 pci_unmap_addr(&tnapi
->tx_buffers
[entry
],
5678 frag
->size
, PCI_DMA_TODEVICE
);
5682 return NETDEV_TX_OK
;
5685 static netdev_tx_t
tg3_start_xmit_dma_bug(struct sk_buff
*,
5686 struct net_device
*);
5688 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5689 * TSO header is greater than 80 bytes.
5691 static int tg3_tso_bug(struct tg3
*tp
, struct sk_buff
*skb
)
5693 struct sk_buff
*segs
, *nskb
;
5694 u32 frag_cnt_est
= skb_shinfo(skb
)->gso_segs
* 3;
5696 /* Estimate the number of fragments in the worst case */
5697 if (unlikely(tg3_tx_avail(&tp
->napi
[0]) <= frag_cnt_est
)) {
5698 netif_stop_queue(tp
->dev
);
5699 if (tg3_tx_avail(&tp
->napi
[0]) <= frag_cnt_est
)
5700 return NETDEV_TX_BUSY
;
5702 netif_wake_queue(tp
->dev
);
5705 segs
= skb_gso_segment(skb
, tp
->dev
->features
& ~NETIF_F_TSO
);
5707 goto tg3_tso_bug_end
;
5713 tg3_start_xmit_dma_bug(nskb
, tp
->dev
);
5719 return NETDEV_TX_OK
;
5722 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5723 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5725 static netdev_tx_t
tg3_start_xmit_dma_bug(struct sk_buff
*skb
,
5726 struct net_device
*dev
)
5728 struct tg3
*tp
= netdev_priv(dev
);
5729 u32 len
, entry
, base_flags
, mss
;
5730 int would_hit_hwbug
;
5732 struct tg3_napi
*tnapi
;
5733 struct netdev_queue
*txq
;
5734 unsigned int i
, last
;
5736 txq
= netdev_get_tx_queue(dev
, skb_get_queue_mapping(skb
));
5737 tnapi
= &tp
->napi
[skb_get_queue_mapping(skb
)];
5738 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)
5741 /* We are running in BH disabled context with netif_tx_lock
5742 * and TX reclaim runs via tp->napi.poll inside of a software
5743 * interrupt. Furthermore, IRQ processing runs lockless so we have
5744 * no IRQ context deadlocks to worry about either. Rejoice!
5746 if (unlikely(tg3_tx_avail(tnapi
) <= (skb_shinfo(skb
)->nr_frags
+ 1))) {
5747 if (!netif_tx_queue_stopped(txq
)) {
5748 netif_tx_stop_queue(txq
);
5750 /* This is a hard error, log it. */
5752 "BUG! Tx Ring full when queue awake!\n");
5754 return NETDEV_TX_BUSY
;
5757 entry
= tnapi
->tx_prod
;
5759 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
5760 base_flags
|= TXD_FLAG_TCPUDP_CSUM
;
5762 if ((mss
= skb_shinfo(skb
)->gso_size
) != 0) {
5764 u32 tcp_opt_len
, ip_tcp_len
, hdr_len
;
5766 if (skb_header_cloned(skb
) &&
5767 pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
)) {
5772 tcp_opt_len
= tcp_optlen(skb
);
5773 ip_tcp_len
= ip_hdrlen(skb
) + sizeof(struct tcphdr
);
5775 hdr_len
= ip_tcp_len
+ tcp_opt_len
;
5776 if (unlikely((ETH_HLEN
+ hdr_len
) > 80) &&
5777 (tp
->tg3_flags2
& TG3_FLG2_TSO_BUG
))
5778 return tg3_tso_bug(tp
, skb
);
5780 base_flags
|= (TXD_FLAG_CPU_PRE_DMA
|
5781 TXD_FLAG_CPU_POST_DMA
);
5785 iph
->tot_len
= htons(mss
+ hdr_len
);
5786 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
) {
5787 tcp_hdr(skb
)->check
= 0;
5788 base_flags
&= ~TXD_FLAG_TCPUDP_CSUM
;
5790 tcp_hdr(skb
)->check
= ~csum_tcpudp_magic(iph
->saddr
,
5795 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO_3
) {
5796 mss
|= (hdr_len
& 0xc) << 12;
5798 base_flags
|= 0x00000010;
5799 base_flags
|= (hdr_len
& 0x3e0) << 5;
5800 } else if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO_2
)
5801 mss
|= hdr_len
<< 9;
5802 else if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO_1
) ||
5803 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
5804 if (tcp_opt_len
|| iph
->ihl
> 5) {
5807 tsflags
= (iph
->ihl
- 5) + (tcp_opt_len
>> 2);
5808 mss
|= (tsflags
<< 11);
5811 if (tcp_opt_len
|| iph
->ihl
> 5) {
5814 tsflags
= (iph
->ihl
- 5) + (tcp_opt_len
>> 2);
5815 base_flags
|= tsflags
<< 12;
5819 #if TG3_VLAN_TAG_USED
5820 if (tp
->vlgrp
!= NULL
&& vlan_tx_tag_present(skb
))
5821 base_flags
|= (TXD_FLAG_VLAN
|
5822 (vlan_tx_tag_get(skb
) << 16));
5825 if ((tp
->tg3_flags3
& TG3_FLG3_USE_JUMBO_BDFLAG
) &&
5826 !mss
&& skb
->len
> ETH_DATA_LEN
)
5827 base_flags
|= TXD_FLAG_JMB_PKT
;
5829 len
= skb_headlen(skb
);
5831 mapping
= pci_map_single(tp
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
5832 if (pci_dma_mapping_error(tp
->pdev
, mapping
)) {
5837 tnapi
->tx_buffers
[entry
].skb
= skb
;
5838 pci_unmap_addr_set(&tnapi
->tx_buffers
[entry
], mapping
, mapping
);
5840 would_hit_hwbug
= 0;
5842 if ((tp
->tg3_flags3
& TG3_FLG3_SHORT_DMA_BUG
) && len
<= 8)
5843 would_hit_hwbug
= 1;
5845 if ((tp
->tg3_flags3
& TG3_FLG3_4G_DMA_BNDRY_BUG
) &&
5846 tg3_4g_overflow_test(mapping
, len
))
5847 would_hit_hwbug
= 1;
5849 if ((tp
->tg3_flags3
& TG3_FLG3_40BIT_DMA_LIMIT_BUG
) &&
5850 tg3_40bit_overflow_test(tp
, mapping
, len
))
5851 would_hit_hwbug
= 1;
5853 if (tp
->tg3_flags3
& TG3_FLG3_5701_DMA_BUG
)
5854 would_hit_hwbug
= 1;
5856 tg3_set_txd(tnapi
, entry
, mapping
, len
, base_flags
,
5857 (skb_shinfo(skb
)->nr_frags
== 0) | (mss
<< 1));
5859 entry
= NEXT_TX(entry
);
5861 /* Now loop through additional data fragments, and queue them. */
5862 if (skb_shinfo(skb
)->nr_frags
> 0) {
5863 last
= skb_shinfo(skb
)->nr_frags
- 1;
5864 for (i
= 0; i
<= last
; i
++) {
5865 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
5868 mapping
= pci_map_page(tp
->pdev
,
5871 len
, PCI_DMA_TODEVICE
);
5873 tnapi
->tx_buffers
[entry
].skb
= NULL
;
5874 pci_unmap_addr_set(&tnapi
->tx_buffers
[entry
], mapping
,
5876 if (pci_dma_mapping_error(tp
->pdev
, mapping
))
5879 if ((tp
->tg3_flags3
& TG3_FLG3_SHORT_DMA_BUG
) &&
5881 would_hit_hwbug
= 1;
5883 if ((tp
->tg3_flags3
& TG3_FLG3_4G_DMA_BNDRY_BUG
) &&
5884 tg3_4g_overflow_test(mapping
, len
))
5885 would_hit_hwbug
= 1;
5887 if ((tp
->tg3_flags3
& TG3_FLG3_40BIT_DMA_LIMIT_BUG
) &&
5888 tg3_40bit_overflow_test(tp
, mapping
, len
))
5889 would_hit_hwbug
= 1;
5891 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
5892 tg3_set_txd(tnapi
, entry
, mapping
, len
,
5893 base_flags
, (i
== last
)|(mss
<< 1));
5895 tg3_set_txd(tnapi
, entry
, mapping
, len
,
5896 base_flags
, (i
== last
));
5898 entry
= NEXT_TX(entry
);
5902 if (would_hit_hwbug
) {
5903 u32 last_plus_one
= entry
;
5906 start
= entry
- 1 - skb_shinfo(skb
)->nr_frags
;
5907 start
&= (TG3_TX_RING_SIZE
- 1);
5909 /* If the workaround fails due to memory/mapping
5910 * failure, silently drop this packet.
5912 if (tigon3_dma_hwbug_workaround(tnapi
, skb
, last_plus_one
,
5913 &start
, base_flags
, mss
))
5919 /* Packets are ready, update Tx producer idx local and on card. */
5920 tw32_tx_mbox(tnapi
->prodmbox
, entry
);
5922 tnapi
->tx_prod
= entry
;
5923 if (unlikely(tg3_tx_avail(tnapi
) <= (MAX_SKB_FRAGS
+ 1))) {
5924 netif_tx_stop_queue(txq
);
5925 if (tg3_tx_avail(tnapi
) > TG3_TX_WAKEUP_THRESH(tnapi
))
5926 netif_tx_wake_queue(txq
);
5932 return NETDEV_TX_OK
;
5936 entry
= tnapi
->tx_prod
;
5937 tnapi
->tx_buffers
[entry
].skb
= NULL
;
5938 pci_unmap_single(tp
->pdev
,
5939 pci_unmap_addr(&tnapi
->tx_buffers
[entry
], mapping
),
5942 for (i
= 0; i
<= last
; i
++) {
5943 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
5944 entry
= NEXT_TX(entry
);
5946 pci_unmap_page(tp
->pdev
,
5947 pci_unmap_addr(&tnapi
->tx_buffers
[entry
],
5949 frag
->size
, PCI_DMA_TODEVICE
);
5953 return NETDEV_TX_OK
;
5956 static inline void tg3_set_mtu(struct net_device
*dev
, struct tg3
*tp
,
5961 if (new_mtu
> ETH_DATA_LEN
) {
5962 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) {
5963 tp
->tg3_flags2
&= ~TG3_FLG2_TSO_CAPABLE
;
5964 ethtool_op_set_tso(dev
, 0);
5966 tp
->tg3_flags
|= TG3_FLAG_JUMBO_RING_ENABLE
;
5969 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)
5970 tp
->tg3_flags2
|= TG3_FLG2_TSO_CAPABLE
;
5971 tp
->tg3_flags
&= ~TG3_FLAG_JUMBO_RING_ENABLE
;
5975 static int tg3_change_mtu(struct net_device
*dev
, int new_mtu
)
5977 struct tg3
*tp
= netdev_priv(dev
);
5980 if (new_mtu
< TG3_MIN_MTU
|| new_mtu
> TG3_MAX_MTU(tp
))
5983 if (!netif_running(dev
)) {
5984 /* We'll just catch it later when the
5987 tg3_set_mtu(dev
, tp
, new_mtu
);
5995 tg3_full_lock(tp
, 1);
5997 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
5999 tg3_set_mtu(dev
, tp
, new_mtu
);
6001 err
= tg3_restart_hw(tp
, 0);
6004 tg3_netif_start(tp
);
6006 tg3_full_unlock(tp
);
6014 static void tg3_rx_prodring_free(struct tg3
*tp
,
6015 struct tg3_rx_prodring_set
*tpr
)
6019 if (tpr
!= &tp
->prodring
[0]) {
6020 for (i
= tpr
->rx_std_cons_idx
; i
!= tpr
->rx_std_prod_idx
;
6021 i
= (i
+ 1) % TG3_RX_RING_SIZE
)
6022 tg3_rx_skb_free(tp
, &tpr
->rx_std_buffers
[i
],
6025 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) {
6026 for (i
= tpr
->rx_jmb_cons_idx
;
6027 i
!= tpr
->rx_jmb_prod_idx
;
6028 i
= (i
+ 1) % TG3_RX_JUMBO_RING_SIZE
) {
6029 tg3_rx_skb_free(tp
, &tpr
->rx_jmb_buffers
[i
],
6037 for (i
= 0; i
< TG3_RX_RING_SIZE
; i
++)
6038 tg3_rx_skb_free(tp
, &tpr
->rx_std_buffers
[i
],
6041 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) {
6042 for (i
= 0; i
< TG3_RX_JUMBO_RING_SIZE
; i
++)
6043 tg3_rx_skb_free(tp
, &tpr
->rx_jmb_buffers
[i
],
6048 /* Initialize rx rings for packet processing.
6050 * The chip has been shut down and the driver detached from
6051 * the networking, so no interrupts or new tx packets will
6052 * end up in the driver. tp->{tx,}lock are held and thus
6055 static int tg3_rx_prodring_alloc(struct tg3
*tp
,
6056 struct tg3_rx_prodring_set
*tpr
)
6058 u32 i
, rx_pkt_dma_sz
;
6060 tpr
->rx_std_cons_idx
= 0;
6061 tpr
->rx_std_prod_idx
= 0;
6062 tpr
->rx_jmb_cons_idx
= 0;
6063 tpr
->rx_jmb_prod_idx
= 0;
6065 if (tpr
!= &tp
->prodring
[0]) {
6066 memset(&tpr
->rx_std_buffers
[0], 0, TG3_RX_STD_BUFF_RING_SIZE
);
6067 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
)
6068 memset(&tpr
->rx_jmb_buffers
[0], 0,
6069 TG3_RX_JMB_BUFF_RING_SIZE
);
6073 /* Zero out all descriptors. */
6074 memset(tpr
->rx_std
, 0, TG3_RX_RING_BYTES
);
6076 rx_pkt_dma_sz
= TG3_RX_STD_DMA_SZ
;
6077 if ((tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) &&
6078 tp
->dev
->mtu
> ETH_DATA_LEN
)
6079 rx_pkt_dma_sz
= TG3_RX_JMB_DMA_SZ
;
6080 tp
->rx_pkt_map_sz
= TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz
);
6082 /* Initialize invariants of the rings, we only set this
6083 * stuff once. This works because the card does not
6084 * write into the rx buffer posting rings.
6086 for (i
= 0; i
< TG3_RX_RING_SIZE
; i
++) {
6087 struct tg3_rx_buffer_desc
*rxd
;
6089 rxd
= &tpr
->rx_std
[i
];
6090 rxd
->idx_len
= rx_pkt_dma_sz
<< RXD_LEN_SHIFT
;
6091 rxd
->type_flags
= (RXD_FLAG_END
<< RXD_FLAGS_SHIFT
);
6092 rxd
->opaque
= (RXD_OPAQUE_RING_STD
|
6093 (i
<< RXD_OPAQUE_INDEX_SHIFT
));
6096 /* Now allocate fresh SKBs for each rx ring. */
6097 for (i
= 0; i
< tp
->rx_pending
; i
++) {
6098 if (tg3_alloc_rx_skb(tp
, tpr
, RXD_OPAQUE_RING_STD
, i
) < 0) {
6099 netdev_warn(tp
->dev
,
6100 "Using a smaller RX standard ring. Only "
6101 "%d out of %d buffers were allocated "
6102 "successfully\n", i
, tp
->rx_pending
);
6110 if (!(tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
))
6113 memset(tpr
->rx_jmb
, 0, TG3_RX_JUMBO_RING_BYTES
);
6115 if (!(tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
))
6118 for (i
= 0; i
< TG3_RX_JUMBO_RING_SIZE
; i
++) {
6119 struct tg3_rx_buffer_desc
*rxd
;
6121 rxd
= &tpr
->rx_jmb
[i
].std
;
6122 rxd
->idx_len
= TG3_RX_JMB_DMA_SZ
<< RXD_LEN_SHIFT
;
6123 rxd
->type_flags
= (RXD_FLAG_END
<< RXD_FLAGS_SHIFT
) |
6125 rxd
->opaque
= (RXD_OPAQUE_RING_JUMBO
|
6126 (i
<< RXD_OPAQUE_INDEX_SHIFT
));
6129 for (i
= 0; i
< tp
->rx_jumbo_pending
; i
++) {
6130 if (tg3_alloc_rx_skb(tp
, tpr
, RXD_OPAQUE_RING_JUMBO
, i
) < 0) {
6131 netdev_warn(tp
->dev
,
6132 "Using a smaller RX jumbo ring. Only %d "
6133 "out of %d buffers were allocated "
6134 "successfully\n", i
, tp
->rx_jumbo_pending
);
6137 tp
->rx_jumbo_pending
= i
;
6146 tg3_rx_prodring_free(tp
, tpr
);
6150 static void tg3_rx_prodring_fini(struct tg3
*tp
,
6151 struct tg3_rx_prodring_set
*tpr
)
6153 kfree(tpr
->rx_std_buffers
);
6154 tpr
->rx_std_buffers
= NULL
;
6155 kfree(tpr
->rx_jmb_buffers
);
6156 tpr
->rx_jmb_buffers
= NULL
;
6158 pci_free_consistent(tp
->pdev
, TG3_RX_RING_BYTES
,
6159 tpr
->rx_std
, tpr
->rx_std_mapping
);
6163 pci_free_consistent(tp
->pdev
, TG3_RX_JUMBO_RING_BYTES
,
6164 tpr
->rx_jmb
, tpr
->rx_jmb_mapping
);
6169 static int tg3_rx_prodring_init(struct tg3
*tp
,
6170 struct tg3_rx_prodring_set
*tpr
)
6172 tpr
->rx_std_buffers
= kzalloc(TG3_RX_STD_BUFF_RING_SIZE
, GFP_KERNEL
);
6173 if (!tpr
->rx_std_buffers
)
6176 tpr
->rx_std
= pci_alloc_consistent(tp
->pdev
, TG3_RX_RING_BYTES
,
6177 &tpr
->rx_std_mapping
);
6181 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) {
6182 tpr
->rx_jmb_buffers
= kzalloc(TG3_RX_JMB_BUFF_RING_SIZE
,
6184 if (!tpr
->rx_jmb_buffers
)
6187 tpr
->rx_jmb
= pci_alloc_consistent(tp
->pdev
,
6188 TG3_RX_JUMBO_RING_BYTES
,
6189 &tpr
->rx_jmb_mapping
);
6197 tg3_rx_prodring_fini(tp
, tpr
);
6201 /* Free up pending packets in all rx/tx rings.
6203 * The chip has been shut down and the driver detached from
6204 * the networking, so no interrupts or new tx packets will
6205 * end up in the driver. tp->{tx,}lock is not held and we are not
6206 * in an interrupt context and thus may sleep.
6208 static void tg3_free_rings(struct tg3
*tp
)
6212 for (j
= 0; j
< tp
->irq_cnt
; j
++) {
6213 struct tg3_napi
*tnapi
= &tp
->napi
[j
];
6215 if (!tnapi
->tx_buffers
)
6218 for (i
= 0; i
< TG3_TX_RING_SIZE
; ) {
6219 struct ring_info
*txp
;
6220 struct sk_buff
*skb
;
6223 txp
= &tnapi
->tx_buffers
[i
];
6231 pci_unmap_single(tp
->pdev
,
6232 pci_unmap_addr(txp
, mapping
),
6239 for (k
= 0; k
< skb_shinfo(skb
)->nr_frags
; k
++) {
6240 txp
= &tnapi
->tx_buffers
[i
& (TG3_TX_RING_SIZE
- 1)];
6241 pci_unmap_page(tp
->pdev
,
6242 pci_unmap_addr(txp
, mapping
),
6243 skb_shinfo(skb
)->frags
[k
].size
,
6248 dev_kfree_skb_any(skb
);
6251 tg3_rx_prodring_free(tp
, &tp
->prodring
[j
]);
6255 /* Initialize tx/rx rings for packet processing.
6257 * The chip has been shut down and the driver detached from
6258 * the networking, so no interrupts or new tx packets will
6259 * end up in the driver. tp->{tx,}lock are held and thus
6262 static int tg3_init_rings(struct tg3
*tp
)
6266 /* Free up all the SKBs. */
6269 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
6270 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
6272 tnapi
->last_tag
= 0;
6273 tnapi
->last_irq_tag
= 0;
6274 tnapi
->hw_status
->status
= 0;
6275 tnapi
->hw_status
->status_tag
= 0;
6276 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
6281 memset(tnapi
->tx_ring
, 0, TG3_TX_RING_BYTES
);
6283 tnapi
->rx_rcb_ptr
= 0;
6285 memset(tnapi
->rx_rcb
, 0, TG3_RX_RCB_RING_BYTES(tp
));
6287 if (tg3_rx_prodring_alloc(tp
, &tp
->prodring
[i
])) {
6297 * Must not be invoked with interrupt sources disabled and
6298 * the hardware shutdown down.
6300 static void tg3_free_consistent(struct tg3
*tp
)
6304 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
6305 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
6307 if (tnapi
->tx_ring
) {
6308 pci_free_consistent(tp
->pdev
, TG3_TX_RING_BYTES
,
6309 tnapi
->tx_ring
, tnapi
->tx_desc_mapping
);
6310 tnapi
->tx_ring
= NULL
;
6313 kfree(tnapi
->tx_buffers
);
6314 tnapi
->tx_buffers
= NULL
;
6316 if (tnapi
->rx_rcb
) {
6317 pci_free_consistent(tp
->pdev
, TG3_RX_RCB_RING_BYTES(tp
),
6319 tnapi
->rx_rcb_mapping
);
6320 tnapi
->rx_rcb
= NULL
;
6323 if (tnapi
->hw_status
) {
6324 pci_free_consistent(tp
->pdev
, TG3_HW_STATUS_SIZE
,
6326 tnapi
->status_mapping
);
6327 tnapi
->hw_status
= NULL
;
6332 pci_free_consistent(tp
->pdev
, sizeof(struct tg3_hw_stats
),
6333 tp
->hw_stats
, tp
->stats_mapping
);
6334 tp
->hw_stats
= NULL
;
6337 for (i
= 0; i
< tp
->irq_cnt
; i
++)
6338 tg3_rx_prodring_fini(tp
, &tp
->prodring
[i
]);
6342 * Must not be invoked with interrupt sources disabled and
6343 * the hardware shutdown down. Can sleep.
6345 static int tg3_alloc_consistent(struct tg3
*tp
)
6349 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
6350 if (tg3_rx_prodring_init(tp
, &tp
->prodring
[i
]))
6354 tp
->hw_stats
= pci_alloc_consistent(tp
->pdev
,
6355 sizeof(struct tg3_hw_stats
),
6356 &tp
->stats_mapping
);
6360 memset(tp
->hw_stats
, 0, sizeof(struct tg3_hw_stats
));
6362 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
6363 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
6364 struct tg3_hw_status
*sblk
;
6366 tnapi
->hw_status
= pci_alloc_consistent(tp
->pdev
,
6368 &tnapi
->status_mapping
);
6369 if (!tnapi
->hw_status
)
6372 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
6373 sblk
= tnapi
->hw_status
;
6375 /* If multivector TSS is enabled, vector 0 does not handle
6376 * tx interrupts. Don't allocate any resources for it.
6378 if ((!i
&& !(tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)) ||
6379 (i
&& (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
))) {
6380 tnapi
->tx_buffers
= kzalloc(sizeof(struct ring_info
) *
6383 if (!tnapi
->tx_buffers
)
6386 tnapi
->tx_ring
= pci_alloc_consistent(tp
->pdev
,
6388 &tnapi
->tx_desc_mapping
);
6389 if (!tnapi
->tx_ring
)
6394 * When RSS is enabled, the status block format changes
6395 * slightly. The "rx_jumbo_consumer", "reserved",
6396 * and "rx_mini_consumer" members get mapped to the
6397 * other three rx return ring producer indexes.
6401 tnapi
->rx_rcb_prod_idx
= &sblk
->idx
[0].rx_producer
;
6404 tnapi
->rx_rcb_prod_idx
= &sblk
->rx_jumbo_consumer
;
6407 tnapi
->rx_rcb_prod_idx
= &sblk
->reserved
;
6410 tnapi
->rx_rcb_prod_idx
= &sblk
->rx_mini_consumer
;
6414 tnapi
->prodring
= &tp
->prodring
[i
];
6417 * If multivector RSS is enabled, vector 0 does not handle
6418 * rx or tx interrupts. Don't allocate any resources for it.
6420 if (!i
&& (tp
->tg3_flags3
& TG3_FLG3_ENABLE_RSS
))
6423 tnapi
->rx_rcb
= pci_alloc_consistent(tp
->pdev
,
6424 TG3_RX_RCB_RING_BYTES(tp
),
6425 &tnapi
->rx_rcb_mapping
);
6429 memset(tnapi
->rx_rcb
, 0, TG3_RX_RCB_RING_BYTES(tp
));
6435 tg3_free_consistent(tp
);
6439 #define MAX_WAIT_CNT 1000
6441 /* To stop a block, clear the enable bit and poll till it
6442 * clears. tp->lock is held.
6444 static int tg3_stop_block(struct tg3
*tp
, unsigned long ofs
, u32 enable_bit
, int silent
)
6449 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
6456 /* We can't enable/disable these bits of the
6457 * 5705/5750, just say success.
6470 for (i
= 0; i
< MAX_WAIT_CNT
; i
++) {
6473 if ((val
& enable_bit
) == 0)
6477 if (i
== MAX_WAIT_CNT
&& !silent
) {
6478 dev_err(&tp
->pdev
->dev
,
6479 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6487 /* tp->lock is held. */
6488 static int tg3_abort_hw(struct tg3
*tp
, int silent
)
6492 tg3_disable_ints(tp
);
6494 tp
->rx_mode
&= ~RX_MODE_ENABLE
;
6495 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
6498 err
= tg3_stop_block(tp
, RCVBDI_MODE
, RCVBDI_MODE_ENABLE
, silent
);
6499 err
|= tg3_stop_block(tp
, RCVLPC_MODE
, RCVLPC_MODE_ENABLE
, silent
);
6500 err
|= tg3_stop_block(tp
, RCVLSC_MODE
, RCVLSC_MODE_ENABLE
, silent
);
6501 err
|= tg3_stop_block(tp
, RCVDBDI_MODE
, RCVDBDI_MODE_ENABLE
, silent
);
6502 err
|= tg3_stop_block(tp
, RCVDCC_MODE
, RCVDCC_MODE_ENABLE
, silent
);
6503 err
|= tg3_stop_block(tp
, RCVCC_MODE
, RCVCC_MODE_ENABLE
, silent
);
6505 err
|= tg3_stop_block(tp
, SNDBDS_MODE
, SNDBDS_MODE_ENABLE
, silent
);
6506 err
|= tg3_stop_block(tp
, SNDBDI_MODE
, SNDBDI_MODE_ENABLE
, silent
);
6507 err
|= tg3_stop_block(tp
, SNDDATAI_MODE
, SNDDATAI_MODE_ENABLE
, silent
);
6508 err
|= tg3_stop_block(tp
, RDMAC_MODE
, RDMAC_MODE_ENABLE
, silent
);
6509 err
|= tg3_stop_block(tp
, SNDDATAC_MODE
, SNDDATAC_MODE_ENABLE
, silent
);
6510 err
|= tg3_stop_block(tp
, DMAC_MODE
, DMAC_MODE_ENABLE
, silent
);
6511 err
|= tg3_stop_block(tp
, SNDBDC_MODE
, SNDBDC_MODE_ENABLE
, silent
);
6513 tp
->mac_mode
&= ~MAC_MODE_TDE_ENABLE
;
6514 tw32_f(MAC_MODE
, tp
->mac_mode
);
6517 tp
->tx_mode
&= ~TX_MODE_ENABLE
;
6518 tw32_f(MAC_TX_MODE
, tp
->tx_mode
);
6520 for (i
= 0; i
< MAX_WAIT_CNT
; i
++) {
6522 if (!(tr32(MAC_TX_MODE
) & TX_MODE_ENABLE
))
6525 if (i
>= MAX_WAIT_CNT
) {
6526 dev_err(&tp
->pdev
->dev
,
6527 "%s timed out, TX_MODE_ENABLE will not clear "
6528 "MAC_TX_MODE=%08x\n", __func__
, tr32(MAC_TX_MODE
));
6532 err
|= tg3_stop_block(tp
, HOSTCC_MODE
, HOSTCC_MODE_ENABLE
, silent
);
6533 err
|= tg3_stop_block(tp
, WDMAC_MODE
, WDMAC_MODE_ENABLE
, silent
);
6534 err
|= tg3_stop_block(tp
, MBFREE_MODE
, MBFREE_MODE_ENABLE
, silent
);
6536 tw32(FTQ_RESET
, 0xffffffff);
6537 tw32(FTQ_RESET
, 0x00000000);
6539 err
|= tg3_stop_block(tp
, BUFMGR_MODE
, BUFMGR_MODE_ENABLE
, silent
);
6540 err
|= tg3_stop_block(tp
, MEMARB_MODE
, MEMARB_MODE_ENABLE
, silent
);
6542 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
6543 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
6544 if (tnapi
->hw_status
)
6545 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
6548 memset(tp
->hw_stats
, 0, sizeof(struct tg3_hw_stats
));
6553 static void tg3_ape_send_event(struct tg3
*tp
, u32 event
)
6558 apedata
= tg3_ape_read32(tp
, TG3_APE_SEG_SIG
);
6559 if (apedata
!= APE_SEG_SIG_MAGIC
)
6562 apedata
= tg3_ape_read32(tp
, TG3_APE_FW_STATUS
);
6563 if (!(apedata
& APE_FW_STATUS_READY
))
6566 /* Wait for up to 1 millisecond for APE to service previous event. */
6567 for (i
= 0; i
< 10; i
++) {
6568 if (tg3_ape_lock(tp
, TG3_APE_LOCK_MEM
))
6571 apedata
= tg3_ape_read32(tp
, TG3_APE_EVENT_STATUS
);
6573 if (!(apedata
& APE_EVENT_STATUS_EVENT_PENDING
))
6574 tg3_ape_write32(tp
, TG3_APE_EVENT_STATUS
,
6575 event
| APE_EVENT_STATUS_EVENT_PENDING
);
6577 tg3_ape_unlock(tp
, TG3_APE_LOCK_MEM
);
6579 if (!(apedata
& APE_EVENT_STATUS_EVENT_PENDING
))
6585 if (!(apedata
& APE_EVENT_STATUS_EVENT_PENDING
))
6586 tg3_ape_write32(tp
, TG3_APE_EVENT
, APE_EVENT_1
);
6589 static void tg3_ape_driver_state_change(struct tg3
*tp
, int kind
)
6594 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
))
6598 case RESET_KIND_INIT
:
6599 tg3_ape_write32(tp
, TG3_APE_HOST_SEG_SIG
,
6600 APE_HOST_SEG_SIG_MAGIC
);
6601 tg3_ape_write32(tp
, TG3_APE_HOST_SEG_LEN
,
6602 APE_HOST_SEG_LEN_MAGIC
);
6603 apedata
= tg3_ape_read32(tp
, TG3_APE_HOST_INIT_COUNT
);
6604 tg3_ape_write32(tp
, TG3_APE_HOST_INIT_COUNT
, ++apedata
);
6605 tg3_ape_write32(tp
, TG3_APE_HOST_DRIVER_ID
,
6606 APE_HOST_DRIVER_ID_MAGIC
);
6607 tg3_ape_write32(tp
, TG3_APE_HOST_BEHAVIOR
,
6608 APE_HOST_BEHAV_NO_PHYLOCK
);
6610 event
= APE_EVENT_STATUS_STATE_START
;
6612 case RESET_KIND_SHUTDOWN
:
6613 /* With the interface we are currently using,
6614 * APE does not track driver state. Wiping
6615 * out the HOST SEGMENT SIGNATURE forces
6616 * the APE to assume OS absent status.
6618 tg3_ape_write32(tp
, TG3_APE_HOST_SEG_SIG
, 0x0);
6620 event
= APE_EVENT_STATUS_STATE_UNLOAD
;
6622 case RESET_KIND_SUSPEND
:
6623 event
= APE_EVENT_STATUS_STATE_SUSPEND
;
6629 event
|= APE_EVENT_STATUS_DRIVER_EVNT
| APE_EVENT_STATUS_STATE_CHNGE
;
6631 tg3_ape_send_event(tp
, event
);
6634 /* tp->lock is held. */
6635 static void tg3_write_sig_pre_reset(struct tg3
*tp
, int kind
)
6637 tg3_write_mem(tp
, NIC_SRAM_FIRMWARE_MBOX
,
6638 NIC_SRAM_FIRMWARE_MBOX_MAGIC1
);
6640 if (tp
->tg3_flags2
& TG3_FLG2_ASF_NEW_HANDSHAKE
) {
6642 case RESET_KIND_INIT
:
6643 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6647 case RESET_KIND_SHUTDOWN
:
6648 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6652 case RESET_KIND_SUSPEND
:
6653 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6662 if (kind
== RESET_KIND_INIT
||
6663 kind
== RESET_KIND_SUSPEND
)
6664 tg3_ape_driver_state_change(tp
, kind
);
6667 /* tp->lock is held. */
6668 static void tg3_write_sig_post_reset(struct tg3
*tp
, int kind
)
6670 if (tp
->tg3_flags2
& TG3_FLG2_ASF_NEW_HANDSHAKE
) {
6672 case RESET_KIND_INIT
:
6673 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6674 DRV_STATE_START_DONE
);
6677 case RESET_KIND_SHUTDOWN
:
6678 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6679 DRV_STATE_UNLOAD_DONE
);
6687 if (kind
== RESET_KIND_SHUTDOWN
)
6688 tg3_ape_driver_state_change(tp
, kind
);
6691 /* tp->lock is held. */
6692 static void tg3_write_sig_legacy(struct tg3
*tp
, int kind
)
6694 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) {
6696 case RESET_KIND_INIT
:
6697 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6701 case RESET_KIND_SHUTDOWN
:
6702 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6706 case RESET_KIND_SUSPEND
:
6707 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6717 static int tg3_poll_fw(struct tg3
*tp
)
6722 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
6723 /* Wait up to 20ms for init done. */
6724 for (i
= 0; i
< 200; i
++) {
6725 if (tr32(VCPU_STATUS
) & VCPU_STATUS_INIT_DONE
)
6732 /* Wait for firmware initialization to complete. */
6733 for (i
= 0; i
< 100000; i
++) {
6734 tg3_read_mem(tp
, NIC_SRAM_FIRMWARE_MBOX
, &val
);
6735 if (val
== ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1
)
6740 /* Chip might not be fitted with firmware. Some Sun onboard
6741 * parts are configured like that. So don't signal the timeout
6742 * of the above loop as an error, but do report the lack of
6743 * running firmware once.
6746 !(tp
->tg3_flags2
& TG3_FLG2_NO_FWARE_REPORTED
)) {
6747 tp
->tg3_flags2
|= TG3_FLG2_NO_FWARE_REPORTED
;
6749 netdev_info(tp
->dev
, "No firmware running\n");
6752 if (tp
->pci_chip_rev_id
== CHIPREV_ID_57765_A0
) {
6753 /* The 57765 A0 needs a little more
6754 * time to do some important work.
6762 /* Save PCI command register before chip reset */
6763 static void tg3_save_pci_state(struct tg3
*tp
)
6765 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &tp
->pci_cmd
);
6768 /* Restore PCI state after chip reset */
6769 static void tg3_restore_pci_state(struct tg3
*tp
)
6773 /* Re-enable indirect register accesses. */
6774 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
6775 tp
->misc_host_ctrl
);
6777 /* Set MAX PCI retry to zero. */
6778 val
= (PCISTATE_ROM_ENABLE
| PCISTATE_ROM_RETRY_ENABLE
);
6779 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
&&
6780 (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
))
6781 val
|= PCISTATE_RETRY_SAME_DMA
;
6782 /* Allow reads and writes to the APE register and memory space. */
6783 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
6784 val
|= PCISTATE_ALLOW_APE_CTLSPC_WR
|
6785 PCISTATE_ALLOW_APE_SHMEM_WR
;
6786 pci_write_config_dword(tp
->pdev
, TG3PCI_PCISTATE
, val
);
6788 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, tp
->pci_cmd
);
6790 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5785
) {
6791 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)
6792 pcie_set_readrq(tp
->pdev
, 4096);
6794 pci_write_config_byte(tp
->pdev
, PCI_CACHE_LINE_SIZE
,
6795 tp
->pci_cacheline_sz
);
6796 pci_write_config_byte(tp
->pdev
, PCI_LATENCY_TIMER
,
6801 /* Make sure PCI-X relaxed ordering bit is clear. */
6802 if (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) {
6805 pci_read_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
6807 pcix_cmd
&= ~PCI_X_CMD_ERO
;
6808 pci_write_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
6812 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) {
6814 /* Chip reset on 5780 will reset MSI enable bit,
6815 * so need to restore it.
6817 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
6820 pci_read_config_word(tp
->pdev
,
6821 tp
->msi_cap
+ PCI_MSI_FLAGS
,
6823 pci_write_config_word(tp
->pdev
,
6824 tp
->msi_cap
+ PCI_MSI_FLAGS
,
6825 ctrl
| PCI_MSI_FLAGS_ENABLE
);
6826 val
= tr32(MSGINT_MODE
);
6827 tw32(MSGINT_MODE
, val
| MSGINT_MODE_ENABLE
);
6832 static void tg3_stop_fw(struct tg3
*);
6834 /* tp->lock is held. */
6835 static int tg3_chip_reset(struct tg3
*tp
)
6838 void (*write_op
)(struct tg3
*, u32
, u32
);
6843 tg3_ape_lock(tp
, TG3_APE_LOCK_GRC
);
6845 /* No matching tg3_nvram_unlock() after this because
6846 * chip reset below will undo the nvram lock.
6848 tp
->nvram_lock_cnt
= 0;
6850 /* GRC_MISC_CFG core clock reset will clear the memory
6851 * enable bit in PCI register 4 and the MSI enable bit
6852 * on some chips, so we save relevant registers here.
6854 tg3_save_pci_state(tp
);
6856 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
||
6857 (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
))
6858 tw32(GRC_FASTBOOT_PC
, 0);
6861 * We must avoid the readl() that normally takes place.
6862 * It locks machines, causes machine checks, and other
6863 * fun things. So, temporarily disable the 5701
6864 * hardware workaround, while we do the reset.
6866 write_op
= tp
->write32
;
6867 if (write_op
== tg3_write_flush_reg32
)
6868 tp
->write32
= tg3_write32
;
6870 /* Prevent the irq handler from reading or writing PCI registers
6871 * during chip reset when the memory enable bit in the PCI command
6872 * register may be cleared. The chip does not generate interrupt
6873 * at this time, but the irq handler may still be called due to irq
6874 * sharing or irqpoll.
6876 tp
->tg3_flags
|= TG3_FLAG_CHIP_RESETTING
;
6877 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
6878 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
6879 if (tnapi
->hw_status
) {
6880 tnapi
->hw_status
->status
= 0;
6881 tnapi
->hw_status
->status_tag
= 0;
6883 tnapi
->last_tag
= 0;
6884 tnapi
->last_irq_tag
= 0;
6888 for (i
= 0; i
< tp
->irq_cnt
; i
++)
6889 synchronize_irq(tp
->napi
[i
].irq_vec
);
6891 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
) {
6892 val
= tr32(TG3_PCIE_LNKCTL
) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN
;
6893 tw32(TG3_PCIE_LNKCTL
, val
| TG3_PCIE_LNKCTL_L1_PLL_PD_DIS
);
6897 val
= GRC_MISC_CFG_CORECLK_RESET
;
6899 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
6900 if (tr32(0x7e2c) == 0x60) {
6903 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
) {
6904 tw32(GRC_MISC_CFG
, (1 << 29));
6909 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
6910 tw32(VCPU_STATUS
, tr32(VCPU_STATUS
) | VCPU_STATUS_DRV_RESET
);
6911 tw32(GRC_VCPU_EXT_CTRL
,
6912 tr32(GRC_VCPU_EXT_CTRL
) & ~GRC_VCPU_EXT_CTRL_HALT_CPU
);
6915 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
6916 val
|= GRC_MISC_CFG_KEEP_GPHY_POWER
;
6917 tw32(GRC_MISC_CFG
, val
);
6919 /* restore 5701 hardware bug workaround write method */
6920 tp
->write32
= write_op
;
6922 /* Unfortunately, we have to delay before the PCI read back.
6923 * Some 575X chips even will not respond to a PCI cfg access
6924 * when the reset command is given to the chip.
6926 * How do these hardware designers expect things to work
6927 * properly if the PCI write is posted for a long period
6928 * of time? It is always necessary to have some method by
6929 * which a register read back can occur to push the write
6930 * out which does the reset.
6932 * For most tg3 variants the trick below was working.
6937 /* Flush PCI posted writes. The normal MMIO registers
6938 * are inaccessible at this time so this is the only
6939 * way to make this reliably (actually, this is no longer
6940 * the case, see above). I tried to use indirect
6941 * register read/write but this upset some 5701 variants.
6943 pci_read_config_dword(tp
->pdev
, PCI_COMMAND
, &val
);
6947 if ((tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) && tp
->pcie_cap
) {
6950 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5750_A0
) {
6954 /* Wait for link training to complete. */
6955 for (i
= 0; i
< 5000; i
++)
6958 pci_read_config_dword(tp
->pdev
, 0xc4, &cfg_val
);
6959 pci_write_config_dword(tp
->pdev
, 0xc4,
6960 cfg_val
| (1 << 15));
6963 /* Clear the "no snoop" and "relaxed ordering" bits. */
6964 pci_read_config_word(tp
->pdev
,
6965 tp
->pcie_cap
+ PCI_EXP_DEVCTL
,
6967 val16
&= ~(PCI_EXP_DEVCTL_RELAX_EN
|
6968 PCI_EXP_DEVCTL_NOSNOOP_EN
);
6970 * Older PCIe devices only support the 128 byte
6971 * MPS setting. Enforce the restriction.
6973 if (!(tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) ||
6974 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
))
6975 val16
&= ~PCI_EXP_DEVCTL_PAYLOAD
;
6976 pci_write_config_word(tp
->pdev
,
6977 tp
->pcie_cap
+ PCI_EXP_DEVCTL
,
6980 pcie_set_readrq(tp
->pdev
, 4096);
6982 /* Clear error status */
6983 pci_write_config_word(tp
->pdev
,
6984 tp
->pcie_cap
+ PCI_EXP_DEVSTA
,
6985 PCI_EXP_DEVSTA_CED
|
6986 PCI_EXP_DEVSTA_NFED
|
6987 PCI_EXP_DEVSTA_FED
|
6988 PCI_EXP_DEVSTA_URD
);
6991 tg3_restore_pci_state(tp
);
6993 tp
->tg3_flags
&= ~TG3_FLAG_CHIP_RESETTING
;
6996 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)
6997 val
= tr32(MEMARB_MODE
);
6998 tw32(MEMARB_MODE
, val
| MEMARB_MODE_ENABLE
);
7000 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5750_A3
) {
7002 tw32(0x5000, 0x400);
7005 tw32(GRC_MODE
, tp
->grc_mode
);
7007 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A0
) {
7010 tw32(0xc4, val
| (1 << 15));
7013 if ((tp
->nic_sram_data_cfg
& NIC_SRAM_DATA_CFG_MINI_PCI
) != 0 &&
7014 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
7015 tp
->pci_clock_ctrl
|= CLOCK_CTRL_CLKRUN_OENABLE
;
7016 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A0
)
7017 tp
->pci_clock_ctrl
|= CLOCK_CTRL_FORCE_CLKRUN
;
7018 tw32(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
);
7021 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
7022 tp
->mac_mode
= MAC_MODE_PORT_MODE_TBI
;
7023 tw32_f(MAC_MODE
, tp
->mac_mode
);
7024 } else if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
) {
7025 tp
->mac_mode
= MAC_MODE_PORT_MODE_GMII
;
7026 tw32_f(MAC_MODE
, tp
->mac_mode
);
7027 } else if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
7028 tp
->mac_mode
&= (MAC_MODE_APE_TX_EN
| MAC_MODE_APE_RX_EN
);
7029 if (tp
->mac_mode
& MAC_MODE_APE_TX_EN
)
7030 tp
->mac_mode
|= MAC_MODE_TDE_ENABLE
;
7031 tw32_f(MAC_MODE
, tp
->mac_mode
);
7033 tw32_f(MAC_MODE
, 0);
7036 tg3_ape_unlock(tp
, TG3_APE_LOCK_GRC
);
7038 err
= tg3_poll_fw(tp
);
7044 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
) {
7047 phy_addr
= tp
->phy_addr
;
7048 tp
->phy_addr
= TG3_PHY_PCIE_ADDR
;
7050 tg3_writephy(tp
, TG3_PCIEPHY_BLOCK_ADDR
,
7051 TG3_PCIEPHY_TXB_BLK
<< TG3_PCIEPHY_BLOCK_SHIFT
);
7052 val
= TG3_PCIEPHY_TX0CTRL1_TXOCM
| TG3_PCIEPHY_TX0CTRL1_RDCTL
|
7053 TG3_PCIEPHY_TX0CTRL1_TXCMV
| TG3_PCIEPHY_TX0CTRL1_TKSEL
|
7054 TG3_PCIEPHY_TX0CTRL1_NB_EN
;
7055 tg3_writephy(tp
, TG3_PCIEPHY_TX0CTRL1
, val
);
7058 tg3_writephy(tp
, TG3_PCIEPHY_BLOCK_ADDR
,
7059 TG3_PCIEPHY_XGXS_BLK1
<< TG3_PCIEPHY_BLOCK_SHIFT
);
7060 val
= TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN
|
7061 TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN
;
7062 tg3_writephy(tp
, TG3_PCIEPHY_PWRMGMT4
, val
);
7065 tp
->phy_addr
= phy_addr
;
7068 if ((tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) &&
7069 tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
&&
7070 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5785
&&
7071 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5717
&&
7072 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_57765
) {
7075 tw32(0x7c00, val
| (1 << 25));
7078 /* Reprobe ASF enable state. */
7079 tp
->tg3_flags
&= ~TG3_FLAG_ENABLE_ASF
;
7080 tp
->tg3_flags2
&= ~TG3_FLG2_ASF_NEW_HANDSHAKE
;
7081 tg3_read_mem(tp
, NIC_SRAM_DATA_SIG
, &val
);
7082 if (val
== NIC_SRAM_DATA_SIG_MAGIC
) {
7085 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG
, &nic_cfg
);
7086 if (nic_cfg
& NIC_SRAM_DATA_CFG_ASF_ENABLE
) {
7087 tp
->tg3_flags
|= TG3_FLAG_ENABLE_ASF
;
7088 tp
->last_event_jiffies
= jiffies
;
7089 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
7090 tp
->tg3_flags2
|= TG3_FLG2_ASF_NEW_HANDSHAKE
;
7097 /* tp->lock is held. */
7098 static void tg3_stop_fw(struct tg3
*tp
)
7100 if ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) &&
7101 !(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)) {
7102 /* Wait for RX cpu to ACK the previous event. */
7103 tg3_wait_for_event_ack(tp
);
7105 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_MBOX
, FWCMD_NICDRV_PAUSE_FW
);
7107 tg3_generate_fw_event(tp
);
7109 /* Wait for RX cpu to ACK this event. */
7110 tg3_wait_for_event_ack(tp
);
7114 /* tp->lock is held. */
7115 static int tg3_halt(struct tg3
*tp
, int kind
, int silent
)
7121 tg3_write_sig_pre_reset(tp
, kind
);
7123 tg3_abort_hw(tp
, silent
);
7124 err
= tg3_chip_reset(tp
);
7126 __tg3_set_mac_addr(tp
, 0);
7128 tg3_write_sig_legacy(tp
, kind
);
7129 tg3_write_sig_post_reset(tp
, kind
);
7137 #define RX_CPU_SCRATCH_BASE 0x30000
7138 #define RX_CPU_SCRATCH_SIZE 0x04000
7139 #define TX_CPU_SCRATCH_BASE 0x34000
7140 #define TX_CPU_SCRATCH_SIZE 0x04000
7142 /* tp->lock is held. */
7143 static int tg3_halt_cpu(struct tg3
*tp
, u32 offset
)
7147 BUG_ON(offset
== TX_CPU_BASE
&&
7148 (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
));
7150 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
7151 u32 val
= tr32(GRC_VCPU_EXT_CTRL
);
7153 tw32(GRC_VCPU_EXT_CTRL
, val
| GRC_VCPU_EXT_CTRL_HALT_CPU
);
7156 if (offset
== RX_CPU_BASE
) {
7157 for (i
= 0; i
< 10000; i
++) {
7158 tw32(offset
+ CPU_STATE
, 0xffffffff);
7159 tw32(offset
+ CPU_MODE
, CPU_MODE_HALT
);
7160 if (tr32(offset
+ CPU_MODE
) & CPU_MODE_HALT
)
7164 tw32(offset
+ CPU_STATE
, 0xffffffff);
7165 tw32_f(offset
+ CPU_MODE
, CPU_MODE_HALT
);
7168 for (i
= 0; i
< 10000; i
++) {
7169 tw32(offset
+ CPU_STATE
, 0xffffffff);
7170 tw32(offset
+ CPU_MODE
, CPU_MODE_HALT
);
7171 if (tr32(offset
+ CPU_MODE
) & CPU_MODE_HALT
)
7177 netdev_err(tp
->dev
, "%s timed out, %s CPU\n",
7178 __func__
, offset
== RX_CPU_BASE
? "RX" : "TX");
7182 /* Clear firmware's nvram arbitration. */
7183 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
)
7184 tw32(NVRAM_SWARB
, SWARB_REQ_CLR0
);
7189 unsigned int fw_base
;
7190 unsigned int fw_len
;
7191 const __be32
*fw_data
;
7194 /* tp->lock is held. */
7195 static int tg3_load_firmware_cpu(struct tg3
*tp
, u32 cpu_base
, u32 cpu_scratch_base
,
7196 int cpu_scratch_size
, struct fw_info
*info
)
7198 int err
, lock_err
, i
;
7199 void (*write_op
)(struct tg3
*, u32
, u32
);
7201 if (cpu_base
== TX_CPU_BASE
&&
7202 (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
7204 "%s: Trying to load TX cpu firmware which is 5705\n",
7209 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
7210 write_op
= tg3_write_mem
;
7212 write_op
= tg3_write_indirect_reg32
;
7214 /* It is possible that bootcode is still loading at this point.
7215 * Get the nvram lock first before halting the cpu.
7217 lock_err
= tg3_nvram_lock(tp
);
7218 err
= tg3_halt_cpu(tp
, cpu_base
);
7220 tg3_nvram_unlock(tp
);
7224 for (i
= 0; i
< cpu_scratch_size
; i
+= sizeof(u32
))
7225 write_op(tp
, cpu_scratch_base
+ i
, 0);
7226 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
7227 tw32(cpu_base
+ CPU_MODE
, tr32(cpu_base
+CPU_MODE
)|CPU_MODE_HALT
);
7228 for (i
= 0; i
< (info
->fw_len
/ sizeof(u32
)); i
++)
7229 write_op(tp
, (cpu_scratch_base
+
7230 (info
->fw_base
& 0xffff) +
7232 be32_to_cpu(info
->fw_data
[i
]));
7240 /* tp->lock is held. */
7241 static int tg3_load_5701_a0_firmware_fix(struct tg3
*tp
)
7243 struct fw_info info
;
7244 const __be32
*fw_data
;
7247 fw_data
= (void *)tp
->fw
->data
;
7249 /* Firmware blob starts with version numbers, followed by
7250 start address and length. We are setting complete length.
7251 length = end_address_of_bss - start_address_of_text.
7252 Remainder is the blob to be loaded contiguously
7253 from start address. */
7255 info
.fw_base
= be32_to_cpu(fw_data
[1]);
7256 info
.fw_len
= tp
->fw
->size
- 12;
7257 info
.fw_data
= &fw_data
[3];
7259 err
= tg3_load_firmware_cpu(tp
, RX_CPU_BASE
,
7260 RX_CPU_SCRATCH_BASE
, RX_CPU_SCRATCH_SIZE
,
7265 err
= tg3_load_firmware_cpu(tp
, TX_CPU_BASE
,
7266 TX_CPU_SCRATCH_BASE
, TX_CPU_SCRATCH_SIZE
,
7271 /* Now startup only the RX cpu. */
7272 tw32(RX_CPU_BASE
+ CPU_STATE
, 0xffffffff);
7273 tw32_f(RX_CPU_BASE
+ CPU_PC
, info
.fw_base
);
7275 for (i
= 0; i
< 5; i
++) {
7276 if (tr32(RX_CPU_BASE
+ CPU_PC
) == info
.fw_base
)
7278 tw32(RX_CPU_BASE
+ CPU_STATE
, 0xffffffff);
7279 tw32(RX_CPU_BASE
+ CPU_MODE
, CPU_MODE_HALT
);
7280 tw32_f(RX_CPU_BASE
+ CPU_PC
, info
.fw_base
);
7284 netdev_err(tp
->dev
, "%s fails to set RX CPU PC, is %08x "
7285 "should be %08x\n", __func__
,
7286 tr32(RX_CPU_BASE
+ CPU_PC
), info
.fw_base
);
7289 tw32(RX_CPU_BASE
+ CPU_STATE
, 0xffffffff);
7290 tw32_f(RX_CPU_BASE
+ CPU_MODE
, 0x00000000);
7295 /* 5705 needs a special version of the TSO firmware. */
7297 /* tp->lock is held. */
7298 static int tg3_load_tso_firmware(struct tg3
*tp
)
7300 struct fw_info info
;
7301 const __be32
*fw_data
;
7302 unsigned long cpu_base
, cpu_scratch_base
, cpu_scratch_size
;
7305 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
7308 fw_data
= (void *)tp
->fw
->data
;
7310 /* Firmware blob starts with version numbers, followed by
7311 start address and length. We are setting complete length.
7312 length = end_address_of_bss - start_address_of_text.
7313 Remainder is the blob to be loaded contiguously
7314 from start address. */
7316 info
.fw_base
= be32_to_cpu(fw_data
[1]);
7317 cpu_scratch_size
= tp
->fw_len
;
7318 info
.fw_len
= tp
->fw
->size
- 12;
7319 info
.fw_data
= &fw_data
[3];
7321 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
7322 cpu_base
= RX_CPU_BASE
;
7323 cpu_scratch_base
= NIC_SRAM_MBUF_POOL_BASE5705
;
7325 cpu_base
= TX_CPU_BASE
;
7326 cpu_scratch_base
= TX_CPU_SCRATCH_BASE
;
7327 cpu_scratch_size
= TX_CPU_SCRATCH_SIZE
;
7330 err
= tg3_load_firmware_cpu(tp
, cpu_base
,
7331 cpu_scratch_base
, cpu_scratch_size
,
7336 /* Now startup the cpu. */
7337 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
7338 tw32_f(cpu_base
+ CPU_PC
, info
.fw_base
);
7340 for (i
= 0; i
< 5; i
++) {
7341 if (tr32(cpu_base
+ CPU_PC
) == info
.fw_base
)
7343 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
7344 tw32(cpu_base
+ CPU_MODE
, CPU_MODE_HALT
);
7345 tw32_f(cpu_base
+ CPU_PC
, info
.fw_base
);
7350 "%s fails to set CPU PC, is %08x should be %08x\n",
7351 __func__
, tr32(cpu_base
+ CPU_PC
), info
.fw_base
);
7354 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
7355 tw32_f(cpu_base
+ CPU_MODE
, 0x00000000);
7360 static int tg3_set_mac_addr(struct net_device
*dev
, void *p
)
7362 struct tg3
*tp
= netdev_priv(dev
);
7363 struct sockaddr
*addr
= p
;
7364 int err
= 0, skip_mac_1
= 0;
7366 if (!is_valid_ether_addr(addr
->sa_data
))
7369 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
7371 if (!netif_running(dev
))
7374 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) {
7375 u32 addr0_high
, addr0_low
, addr1_high
, addr1_low
;
7377 addr0_high
= tr32(MAC_ADDR_0_HIGH
);
7378 addr0_low
= tr32(MAC_ADDR_0_LOW
);
7379 addr1_high
= tr32(MAC_ADDR_1_HIGH
);
7380 addr1_low
= tr32(MAC_ADDR_1_LOW
);
7382 /* Skip MAC addr 1 if ASF is using it. */
7383 if ((addr0_high
!= addr1_high
|| addr0_low
!= addr1_low
) &&
7384 !(addr1_high
== 0 && addr1_low
== 0))
7387 spin_lock_bh(&tp
->lock
);
7388 __tg3_set_mac_addr(tp
, skip_mac_1
);
7389 spin_unlock_bh(&tp
->lock
);
7394 /* tp->lock is held. */
7395 static void tg3_set_bdinfo(struct tg3
*tp
, u32 bdinfo_addr
,
7396 dma_addr_t mapping
, u32 maxlen_flags
,
7400 (bdinfo_addr
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_HIGH
),
7401 ((u64
) mapping
>> 32));
7403 (bdinfo_addr
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_LOW
),
7404 ((u64
) mapping
& 0xffffffff));
7406 (bdinfo_addr
+ TG3_BDINFO_MAXLEN_FLAGS
),
7409 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
7411 (bdinfo_addr
+ TG3_BDINFO_NIC_ADDR
),
7415 static void __tg3_set_rx_mode(struct net_device
*);
7416 static void __tg3_set_coalesce(struct tg3
*tp
, struct ethtool_coalesce
*ec
)
7420 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)) {
7421 tw32(HOSTCC_TXCOL_TICKS
, ec
->tx_coalesce_usecs
);
7422 tw32(HOSTCC_TXMAX_FRAMES
, ec
->tx_max_coalesced_frames
);
7423 tw32(HOSTCC_TXCOAL_MAXF_INT
, ec
->tx_max_coalesced_frames_irq
);
7425 tw32(HOSTCC_TXCOL_TICKS
, 0);
7426 tw32(HOSTCC_TXMAX_FRAMES
, 0);
7427 tw32(HOSTCC_TXCOAL_MAXF_INT
, 0);
7430 if (!(tp
->tg3_flags2
& TG3_FLG2_USING_MSIX
)) {
7431 tw32(HOSTCC_RXCOL_TICKS
, ec
->rx_coalesce_usecs
);
7432 tw32(HOSTCC_RXMAX_FRAMES
, ec
->rx_max_coalesced_frames
);
7433 tw32(HOSTCC_RXCOAL_MAXF_INT
, ec
->rx_max_coalesced_frames_irq
);
7435 tw32(HOSTCC_RXCOL_TICKS
, 0);
7436 tw32(HOSTCC_RXMAX_FRAMES
, 0);
7437 tw32(HOSTCC_RXCOAL_MAXF_INT
, 0);
7440 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
7441 u32 val
= ec
->stats_block_coalesce_usecs
;
7443 tw32(HOSTCC_RXCOAL_TICK_INT
, ec
->rx_coalesce_usecs_irq
);
7444 tw32(HOSTCC_TXCOAL_TICK_INT
, ec
->tx_coalesce_usecs_irq
);
7446 if (!netif_carrier_ok(tp
->dev
))
7449 tw32(HOSTCC_STAT_COAL_TICKS
, val
);
7452 for (i
= 0; i
< tp
->irq_cnt
- 1; i
++) {
7455 reg
= HOSTCC_RXCOL_TICKS_VEC1
+ i
* 0x18;
7456 tw32(reg
, ec
->rx_coalesce_usecs
);
7457 reg
= HOSTCC_RXMAX_FRAMES_VEC1
+ i
* 0x18;
7458 tw32(reg
, ec
->rx_max_coalesced_frames
);
7459 reg
= HOSTCC_RXCOAL_MAXF_INT_VEC1
+ i
* 0x18;
7460 tw32(reg
, ec
->rx_max_coalesced_frames_irq
);
7462 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
) {
7463 reg
= HOSTCC_TXCOL_TICKS_VEC1
+ i
* 0x18;
7464 tw32(reg
, ec
->tx_coalesce_usecs
);
7465 reg
= HOSTCC_TXMAX_FRAMES_VEC1
+ i
* 0x18;
7466 tw32(reg
, ec
->tx_max_coalesced_frames
);
7467 reg
= HOSTCC_TXCOAL_MAXF_INT_VEC1
+ i
* 0x18;
7468 tw32(reg
, ec
->tx_max_coalesced_frames_irq
);
7472 for (; i
< tp
->irq_max
- 1; i
++) {
7473 tw32(HOSTCC_RXCOL_TICKS_VEC1
+ i
* 0x18, 0);
7474 tw32(HOSTCC_RXMAX_FRAMES_VEC1
+ i
* 0x18, 0);
7475 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1
+ i
* 0x18, 0);
7477 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
) {
7478 tw32(HOSTCC_TXCOL_TICKS_VEC1
+ i
* 0x18, 0);
7479 tw32(HOSTCC_TXMAX_FRAMES_VEC1
+ i
* 0x18, 0);
7480 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1
+ i
* 0x18, 0);
7485 /* tp->lock is held. */
7486 static void tg3_rings_reset(struct tg3
*tp
)
7489 u32 stblk
, txrcb
, rxrcb
, limit
;
7490 struct tg3_napi
*tnapi
= &tp
->napi
[0];
7492 /* Disable all transmit rings but the first. */
7493 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
7494 limit
= NIC_SRAM_SEND_RCB
+ TG3_BDINFO_SIZE
* 16;
7495 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
7496 limit
= NIC_SRAM_SEND_RCB
+ TG3_BDINFO_SIZE
* 2;
7498 limit
= NIC_SRAM_SEND_RCB
+ TG3_BDINFO_SIZE
;
7500 for (txrcb
= NIC_SRAM_SEND_RCB
+ TG3_BDINFO_SIZE
;
7501 txrcb
< limit
; txrcb
+= TG3_BDINFO_SIZE
)
7502 tg3_write_mem(tp
, txrcb
+ TG3_BDINFO_MAXLEN_FLAGS
,
7503 BDINFO_FLAGS_DISABLED
);
7506 /* Disable all receive return rings but the first. */
7507 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
)
7508 limit
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
* 17;
7509 else if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
7510 limit
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
* 16;
7511 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
||
7512 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
7513 limit
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
* 4;
7515 limit
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
;
7517 for (rxrcb
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
;
7518 rxrcb
< limit
; rxrcb
+= TG3_BDINFO_SIZE
)
7519 tg3_write_mem(tp
, rxrcb
+ TG3_BDINFO_MAXLEN_FLAGS
,
7520 BDINFO_FLAGS_DISABLED
);
7522 /* Disable interrupts */
7523 tw32_mailbox_f(tp
->napi
[0].int_mbox
, 1);
7525 /* Zero mailbox registers. */
7526 if (tp
->tg3_flags
& TG3_FLAG_SUPPORT_MSIX
) {
7527 for (i
= 1; i
< TG3_IRQ_MAX_VECS
; i
++) {
7528 tp
->napi
[i
].tx_prod
= 0;
7529 tp
->napi
[i
].tx_cons
= 0;
7530 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)
7531 tw32_mailbox(tp
->napi
[i
].prodmbox
, 0);
7532 tw32_rx_mbox(tp
->napi
[i
].consmbox
, 0);
7533 tw32_mailbox_f(tp
->napi
[i
].int_mbox
, 1);
7535 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
))
7536 tw32_mailbox(tp
->napi
[0].prodmbox
, 0);
7538 tp
->napi
[0].tx_prod
= 0;
7539 tp
->napi
[0].tx_cons
= 0;
7540 tw32_mailbox(tp
->napi
[0].prodmbox
, 0);
7541 tw32_rx_mbox(tp
->napi
[0].consmbox
, 0);
7544 /* Make sure the NIC-based send BD rings are disabled. */
7545 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
7546 u32 mbox
= MAILBOX_SNDNIC_PROD_IDX_0
+ TG3_64BIT_REG_LOW
;
7547 for (i
= 0; i
< 16; i
++)
7548 tw32_tx_mbox(mbox
+ i
* 8, 0);
7551 txrcb
= NIC_SRAM_SEND_RCB
;
7552 rxrcb
= NIC_SRAM_RCV_RET_RCB
;
7554 /* Clear status block in ram. */
7555 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
7557 /* Set status block DMA address */
7558 tw32(HOSTCC_STATUS_BLK_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
7559 ((u64
) tnapi
->status_mapping
>> 32));
7560 tw32(HOSTCC_STATUS_BLK_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
7561 ((u64
) tnapi
->status_mapping
& 0xffffffff));
7563 if (tnapi
->tx_ring
) {
7564 tg3_set_bdinfo(tp
, txrcb
, tnapi
->tx_desc_mapping
,
7565 (TG3_TX_RING_SIZE
<<
7566 BDINFO_FLAGS_MAXLEN_SHIFT
),
7567 NIC_SRAM_TX_BUFFER_DESC
);
7568 txrcb
+= TG3_BDINFO_SIZE
;
7571 if (tnapi
->rx_rcb
) {
7572 tg3_set_bdinfo(tp
, rxrcb
, tnapi
->rx_rcb_mapping
,
7573 (TG3_RX_RCB_RING_SIZE(tp
) <<
7574 BDINFO_FLAGS_MAXLEN_SHIFT
), 0);
7575 rxrcb
+= TG3_BDINFO_SIZE
;
7578 stblk
= HOSTCC_STATBLCK_RING1
;
7580 for (i
= 1, tnapi
++; i
< tp
->irq_cnt
; i
++, tnapi
++) {
7581 u64 mapping
= (u64
)tnapi
->status_mapping
;
7582 tw32(stblk
+ TG3_64BIT_REG_HIGH
, mapping
>> 32);
7583 tw32(stblk
+ TG3_64BIT_REG_LOW
, mapping
& 0xffffffff);
7585 /* Clear status block in ram. */
7586 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
7588 if (tnapi
->tx_ring
) {
7589 tg3_set_bdinfo(tp
, txrcb
, tnapi
->tx_desc_mapping
,
7590 (TG3_TX_RING_SIZE
<<
7591 BDINFO_FLAGS_MAXLEN_SHIFT
),
7592 NIC_SRAM_TX_BUFFER_DESC
);
7593 txrcb
+= TG3_BDINFO_SIZE
;
7596 tg3_set_bdinfo(tp
, rxrcb
, tnapi
->rx_rcb_mapping
,
7597 (TG3_RX_RCB_RING_SIZE(tp
) <<
7598 BDINFO_FLAGS_MAXLEN_SHIFT
), 0);
7601 rxrcb
+= TG3_BDINFO_SIZE
;
7605 /* tp->lock is held. */
7606 static int tg3_reset_hw(struct tg3
*tp
, int reset_phy
)
7608 u32 val
, rdmac_mode
;
7610 struct tg3_rx_prodring_set
*tpr
= &tp
->prodring
[0];
7612 tg3_disable_ints(tp
);
7616 tg3_write_sig_pre_reset(tp
, RESET_KIND_INIT
);
7618 if (tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
)
7619 tg3_abort_hw(tp
, 1);
7624 err
= tg3_chip_reset(tp
);
7628 tg3_write_sig_legacy(tp
, RESET_KIND_INIT
);
7630 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
) {
7631 val
= tr32(TG3_CPMU_CTRL
);
7632 val
&= ~(CPMU_CTRL_LINK_AWARE_MODE
| CPMU_CTRL_LINK_IDLE_MODE
);
7633 tw32(TG3_CPMU_CTRL
, val
);
7635 val
= tr32(TG3_CPMU_LSPD_10MB_CLK
);
7636 val
&= ~CPMU_LSPD_10MB_MACCLK_MASK
;
7637 val
|= CPMU_LSPD_10MB_MACCLK_6_25
;
7638 tw32(TG3_CPMU_LSPD_10MB_CLK
, val
);
7640 val
= tr32(TG3_CPMU_LNK_AWARE_PWRMD
);
7641 val
&= ~CPMU_LNK_AWARE_MACCLK_MASK
;
7642 val
|= CPMU_LNK_AWARE_MACCLK_6_25
;
7643 tw32(TG3_CPMU_LNK_AWARE_PWRMD
, val
);
7645 val
= tr32(TG3_CPMU_HST_ACC
);
7646 val
&= ~CPMU_HST_ACC_MACCLK_MASK
;
7647 val
|= CPMU_HST_ACC_MACCLK_6_25
;
7648 tw32(TG3_CPMU_HST_ACC
, val
);
7651 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
) {
7652 val
= tr32(PCIE_PWR_MGMT_THRESH
) & ~PCIE_PWR_MGMT_L1_THRESH_MSK
;
7653 val
|= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN
|
7654 PCIE_PWR_MGMT_L1_THRESH_4MS
;
7655 tw32(PCIE_PWR_MGMT_THRESH
, val
);
7657 val
= tr32(TG3_PCIE_EIDLE_DELAY
) & ~TG3_PCIE_EIDLE_DELAY_MASK
;
7658 tw32(TG3_PCIE_EIDLE_DELAY
, val
| TG3_PCIE_EIDLE_DELAY_13_CLKS
);
7660 tw32(TG3_CORR_ERR_STAT
, TG3_CORR_ERR_STAT_CLEAR
);
7662 val
= tr32(TG3_PCIE_LNKCTL
) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN
;
7663 tw32(TG3_PCIE_LNKCTL
, val
| TG3_PCIE_LNKCTL_L1_PLL_PD_DIS
);
7666 if (tp
->tg3_flags3
& TG3_FLG3_L1PLLPD_EN
) {
7667 u32 grc_mode
= tr32(GRC_MODE
);
7669 /* Access the lower 1K of PL PCIE block registers. */
7670 val
= grc_mode
& ~GRC_MODE_PCIE_PORT_MASK
;
7671 tw32(GRC_MODE
, val
| GRC_MODE_PCIE_PL_SEL
);
7673 val
= tr32(TG3_PCIE_TLDLPL_PORT
+ TG3_PCIE_PL_LO_PHYCTL1
);
7674 tw32(TG3_PCIE_TLDLPL_PORT
+ TG3_PCIE_PL_LO_PHYCTL1
,
7675 val
| TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN
);
7677 tw32(GRC_MODE
, grc_mode
);
7680 if (tp
->pci_chip_rev_id
== CHIPREV_ID_57765_A0
) {
7681 u32 grc_mode
= tr32(GRC_MODE
);
7683 /* Access the lower 1K of PL PCIE block registers. */
7684 val
= grc_mode
& ~GRC_MODE_PCIE_PORT_MASK
;
7685 tw32(GRC_MODE
, val
| GRC_MODE_PCIE_PL_SEL
);
7687 val
= tr32(TG3_PCIE_TLDLPL_PORT
+ TG3_PCIE_PL_LO_PHYCTL5
);
7688 tw32(TG3_PCIE_TLDLPL_PORT
+ TG3_PCIE_PL_LO_PHYCTL5
,
7689 val
| TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ
);
7691 tw32(GRC_MODE
, grc_mode
);
7693 val
= tr32(TG3_CPMU_LSPD_10MB_CLK
);
7694 val
&= ~CPMU_LSPD_10MB_MACCLK_MASK
;
7695 val
|= CPMU_LSPD_10MB_MACCLK_6_25
;
7696 tw32(TG3_CPMU_LSPD_10MB_CLK
, val
);
7699 /* This works around an issue with Athlon chipsets on
7700 * B3 tigon3 silicon. This bit has no effect on any
7701 * other revision. But do not set this on PCI Express
7702 * chips and don't even touch the clocks if the CPMU is present.
7704 if (!(tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
)) {
7705 if (!(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
))
7706 tp
->pci_clock_ctrl
|= CLOCK_CTRL_DELAY_PCI_GRANT
;
7707 tw32_f(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
);
7710 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
&&
7711 (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
)) {
7712 val
= tr32(TG3PCI_PCISTATE
);
7713 val
|= PCISTATE_RETRY_SAME_DMA
;
7714 tw32(TG3PCI_PCISTATE
, val
);
7717 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
7718 /* Allow reads and writes to the
7719 * APE register and memory space.
7721 val
= tr32(TG3PCI_PCISTATE
);
7722 val
|= PCISTATE_ALLOW_APE_CTLSPC_WR
|
7723 PCISTATE_ALLOW_APE_SHMEM_WR
;
7724 tw32(TG3PCI_PCISTATE
, val
);
7727 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5704_BX
) {
7728 /* Enable some hw fixes. */
7729 val
= tr32(TG3PCI_MSI_DATA
);
7730 val
|= (1 << 26) | (1 << 28) | (1 << 29);
7731 tw32(TG3PCI_MSI_DATA
, val
);
7734 /* Descriptor ring init may make accesses to the
7735 * NIC SRAM area to setup the TX descriptors, so we
7736 * can only do this after the hardware has been
7737 * successfully reset.
7739 err
= tg3_init_rings(tp
);
7743 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
7744 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
) {
7745 val
= tr32(TG3PCI_DMA_RW_CTRL
) &
7746 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT
;
7747 if (tp
->pci_chip_rev_id
== CHIPREV_ID_57765_A0
)
7748 val
&= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK
;
7749 tw32(TG3PCI_DMA_RW_CTRL
, val
| tp
->dma_rwctrl
);
7750 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5784
&&
7751 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5761
) {
7752 /* This value is determined during the probe time DMA
7753 * engine test, tg3_test_dma.
7755 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
7758 tp
->grc_mode
&= ~(GRC_MODE_HOST_SENDBDS
|
7759 GRC_MODE_4X_NIC_SEND_RINGS
|
7760 GRC_MODE_NO_TX_PHDR_CSUM
|
7761 GRC_MODE_NO_RX_PHDR_CSUM
);
7762 tp
->grc_mode
|= GRC_MODE_HOST_SENDBDS
;
7764 /* Pseudo-header checksum is done by hardware logic and not
7765 * the offload processers, so make the chip do the pseudo-
7766 * header checksums on receive. For transmit it is more
7767 * convenient to do the pseudo-header checksum in software
7768 * as Linux does that on transmit for us in all cases.
7770 tp
->grc_mode
|= GRC_MODE_NO_TX_PHDR_CSUM
;
7774 (GRC_MODE_IRQ_ON_MAC_ATTN
| GRC_MODE_HOST_STACKUP
));
7776 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7777 val
= tr32(GRC_MISC_CFG
);
7779 val
|= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT
);
7780 tw32(GRC_MISC_CFG
, val
);
7782 /* Initialize MBUF/DESC pool. */
7783 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) {
7785 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5705
) {
7786 tw32(BUFMGR_MB_POOL_ADDR
, NIC_SRAM_MBUF_POOL_BASE
);
7787 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
)
7788 tw32(BUFMGR_MB_POOL_SIZE
, NIC_SRAM_MBUF_POOL_SIZE64
);
7790 tw32(BUFMGR_MB_POOL_SIZE
, NIC_SRAM_MBUF_POOL_SIZE96
);
7791 tw32(BUFMGR_DMA_DESC_POOL_ADDR
, NIC_SRAM_DMA_DESC_POOL_BASE
);
7792 tw32(BUFMGR_DMA_DESC_POOL_SIZE
, NIC_SRAM_DMA_DESC_POOL_SIZE
);
7793 } else if (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) {
7796 fw_len
= tp
->fw_len
;
7797 fw_len
= (fw_len
+ (0x80 - 1)) & ~(0x80 - 1);
7798 tw32(BUFMGR_MB_POOL_ADDR
,
7799 NIC_SRAM_MBUF_POOL_BASE5705
+ fw_len
);
7800 tw32(BUFMGR_MB_POOL_SIZE
,
7801 NIC_SRAM_MBUF_POOL_SIZE5705
- fw_len
- 0xa00);
7804 if (tp
->dev
->mtu
<= ETH_DATA_LEN
) {
7805 tw32(BUFMGR_MB_RDMA_LOW_WATER
,
7806 tp
->bufmgr_config
.mbuf_read_dma_low_water
);
7807 tw32(BUFMGR_MB_MACRX_LOW_WATER
,
7808 tp
->bufmgr_config
.mbuf_mac_rx_low_water
);
7809 tw32(BUFMGR_MB_HIGH_WATER
,
7810 tp
->bufmgr_config
.mbuf_high_water
);
7812 tw32(BUFMGR_MB_RDMA_LOW_WATER
,
7813 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
);
7814 tw32(BUFMGR_MB_MACRX_LOW_WATER
,
7815 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
);
7816 tw32(BUFMGR_MB_HIGH_WATER
,
7817 tp
->bufmgr_config
.mbuf_high_water_jumbo
);
7819 tw32(BUFMGR_DMA_LOW_WATER
,
7820 tp
->bufmgr_config
.dma_low_water
);
7821 tw32(BUFMGR_DMA_HIGH_WATER
,
7822 tp
->bufmgr_config
.dma_high_water
);
7824 tw32(BUFMGR_MODE
, BUFMGR_MODE_ENABLE
| BUFMGR_MODE_ATTN_ENABLE
);
7825 for (i
= 0; i
< 2000; i
++) {
7826 if (tr32(BUFMGR_MODE
) & BUFMGR_MODE_ENABLE
)
7831 netdev_err(tp
->dev
, "%s cannot enable BUFMGR\n", __func__
);
7835 /* Setup replenish threshold. */
7836 val
= tp
->rx_pending
/ 8;
7839 else if (val
> tp
->rx_std_max_post
)
7840 val
= tp
->rx_std_max_post
;
7841 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
7842 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5906_A1
)
7843 tw32(ISO_PKT_TX
, (tr32(ISO_PKT_TX
) & ~0x3) | 0x2);
7845 if (val
> (TG3_RX_INTERNAL_RING_SZ_5906
/ 2))
7846 val
= TG3_RX_INTERNAL_RING_SZ_5906
/ 2;
7849 tw32(RCVBDI_STD_THRESH
, val
);
7851 /* Initialize TG3_BDINFO's at:
7852 * RCVDBDI_STD_BD: standard eth size rx ring
7853 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7854 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7857 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7858 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7859 * ring attribute flags
7860 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7862 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7863 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7865 * The size of each ring is fixed in the firmware, but the location is
7868 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
7869 ((u64
) tpr
->rx_std_mapping
>> 32));
7870 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
7871 ((u64
) tpr
->rx_std_mapping
& 0xffffffff));
7872 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5717
)
7873 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_NIC_ADDR
,
7874 NIC_SRAM_RX_BUFFER_DESC
);
7876 /* Disable the mini ring */
7877 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
7878 tw32(RCVDBDI_MINI_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
7879 BDINFO_FLAGS_DISABLED
);
7881 /* Program the jumbo buffer descriptor ring control
7882 * blocks on those devices that have them.
7884 if ((tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) &&
7885 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
7886 /* Setup replenish threshold. */
7887 tw32(RCVBDI_JUMBO_THRESH
, tp
->rx_jumbo_pending
/ 8);
7889 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
) {
7890 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
7891 ((u64
) tpr
->rx_jmb_mapping
>> 32));
7892 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
7893 ((u64
) tpr
->rx_jmb_mapping
& 0xffffffff));
7894 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
7895 (RX_JUMBO_MAX_SIZE
<< BDINFO_FLAGS_MAXLEN_SHIFT
) |
7896 BDINFO_FLAGS_USE_EXT_RECV
);
7897 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5717
)
7898 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_NIC_ADDR
,
7899 NIC_SRAM_RX_JUMBO_BUFFER_DESC
);
7901 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
7902 BDINFO_FLAGS_DISABLED
);
7905 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
7906 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
7907 val
= (RX_STD_MAX_SIZE_5705
<< BDINFO_FLAGS_MAXLEN_SHIFT
) |
7908 (TG3_RX_STD_DMA_SZ
<< 2);
7910 val
= TG3_RX_STD_DMA_SZ
<< BDINFO_FLAGS_MAXLEN_SHIFT
;
7912 val
= RX_STD_MAX_SIZE_5705
<< BDINFO_FLAGS_MAXLEN_SHIFT
;
7914 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_MAXLEN_FLAGS
, val
);
7916 tpr
->rx_std_prod_idx
= tp
->rx_pending
;
7917 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG
, tpr
->rx_std_prod_idx
);
7919 tpr
->rx_jmb_prod_idx
= (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
) ?
7920 tp
->rx_jumbo_pending
: 0;
7921 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG
, tpr
->rx_jmb_prod_idx
);
7923 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
7924 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
) {
7925 tw32(STD_REPLENISH_LWM
, 32);
7926 tw32(JMB_REPLENISH_LWM
, 16);
7929 tg3_rings_reset(tp
);
7931 /* Initialize MAC address and backoff seed. */
7932 __tg3_set_mac_addr(tp
, 0);
7934 /* MTU + ethernet header + FCS + optional VLAN tag */
7935 tw32(MAC_RX_MTU_SIZE
,
7936 tp
->dev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
+ VLAN_HLEN
);
7938 /* The slot time is changed by tg3_setup_phy if we
7939 * run at gigabit with half duplex.
7941 tw32(MAC_TX_LENGTHS
,
7942 (2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
7943 (6 << TX_LENGTHS_IPG_SHIFT
) |
7944 (32 << TX_LENGTHS_SLOT_TIME_SHIFT
));
7946 /* Receive rules. */
7947 tw32(MAC_RCV_RULE_CFG
, RCV_RULE_CFG_DEFAULT_CLASS
);
7948 tw32(RCVLPC_CONFIG
, 0x0181);
7950 /* Calculate RDMAC_MODE setting early, we need it to determine
7951 * the RCVLPC_STATE_ENABLE mask.
7953 rdmac_mode
= (RDMAC_MODE_ENABLE
| RDMAC_MODE_TGTABORT_ENAB
|
7954 RDMAC_MODE_MSTABORT_ENAB
| RDMAC_MODE_PARITYERR_ENAB
|
7955 RDMAC_MODE_ADDROFLOW_ENAB
| RDMAC_MODE_FIFOOFLOW_ENAB
|
7956 RDMAC_MODE_FIFOURUN_ENAB
| RDMAC_MODE_FIFOOREAD_ENAB
|
7957 RDMAC_MODE_LNGREAD_ENAB
);
7959 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
)
7960 rdmac_mode
|= RDMAC_MODE_MULT_DMA_RD_DIS
;
7962 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
7963 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
7964 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
7965 rdmac_mode
|= RDMAC_MODE_BD_SBD_CRPT_ENAB
|
7966 RDMAC_MODE_MBUF_RBD_CRPT_ENAB
|
7967 RDMAC_MODE_MBUF_SBD_CRPT_ENAB
;
7969 /* If statement applies to 5705 and 5750 PCI devices only */
7970 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
7971 tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A0
) ||
7972 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
)) {
7973 if (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
&&
7974 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
7975 rdmac_mode
|= RDMAC_MODE_FIFO_SIZE_128
;
7976 } else if (!(tr32(TG3PCI_PCISTATE
) & PCISTATE_BUS_SPEED_HIGH
) &&
7977 !(tp
->tg3_flags2
& TG3_FLG2_IS_5788
)) {
7978 rdmac_mode
|= RDMAC_MODE_FIFO_LONG_BURST
;
7982 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)
7983 rdmac_mode
|= RDMAC_MODE_FIFO_LONG_BURST
;
7985 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
7986 rdmac_mode
|= RDMAC_MODE_IPV4_LSO_EN
;
7988 if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO_3
) ||
7989 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
7990 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
7991 rdmac_mode
|= RDMAC_MODE_IPV6_LSO_EN
;
7993 /* Receive/send statistics. */
7994 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) {
7995 val
= tr32(RCVLPC_STATS_ENABLE
);
7996 val
&= ~RCVLPC_STATSENAB_DACK_FIX
;
7997 tw32(RCVLPC_STATS_ENABLE
, val
);
7998 } else if ((rdmac_mode
& RDMAC_MODE_FIFO_SIZE_128
) &&
7999 (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
)) {
8000 val
= tr32(RCVLPC_STATS_ENABLE
);
8001 val
&= ~RCVLPC_STATSENAB_LNGBRST_RFIX
;
8002 tw32(RCVLPC_STATS_ENABLE
, val
);
8004 tw32(RCVLPC_STATS_ENABLE
, 0xffffff);
8006 tw32(RCVLPC_STATSCTRL
, RCVLPC_STATSCTRL_ENABLE
);
8007 tw32(SNDDATAI_STATSENAB
, 0xffffff);
8008 tw32(SNDDATAI_STATSCTRL
,
8009 (SNDDATAI_SCTRL_ENABLE
|
8010 SNDDATAI_SCTRL_FASTUPD
));
8012 /* Setup host coalescing engine. */
8013 tw32(HOSTCC_MODE
, 0);
8014 for (i
= 0; i
< 2000; i
++) {
8015 if (!(tr32(HOSTCC_MODE
) & HOSTCC_MODE_ENABLE
))
8020 __tg3_set_coalesce(tp
, &tp
->coal
);
8022 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
8023 /* Status/statistics block address. See tg3_timer,
8024 * the tg3_periodic_fetch_stats call there, and
8025 * tg3_get_stats to see how this works for 5705/5750 chips.
8027 tw32(HOSTCC_STATS_BLK_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
8028 ((u64
) tp
->stats_mapping
>> 32));
8029 tw32(HOSTCC_STATS_BLK_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
8030 ((u64
) tp
->stats_mapping
& 0xffffffff));
8031 tw32(HOSTCC_STATS_BLK_NIC_ADDR
, NIC_SRAM_STATS_BLK
);
8033 tw32(HOSTCC_STATUS_BLK_NIC_ADDR
, NIC_SRAM_STATUS_BLK
);
8035 /* Clear statistics and status block memory areas */
8036 for (i
= NIC_SRAM_STATS_BLK
;
8037 i
< NIC_SRAM_STATUS_BLK
+ TG3_HW_STATUS_SIZE
;
8039 tg3_write_mem(tp
, i
, 0);
8044 tw32(HOSTCC_MODE
, HOSTCC_MODE_ENABLE
| tp
->coalesce_mode
);
8046 tw32(RCVCC_MODE
, RCVCC_MODE_ENABLE
| RCVCC_MODE_ATTN_ENABLE
);
8047 tw32(RCVLPC_MODE
, RCVLPC_MODE_ENABLE
);
8048 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
8049 tw32(RCVLSC_MODE
, RCVLSC_MODE_ENABLE
| RCVLSC_MODE_ATTN_ENABLE
);
8051 if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
) {
8052 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
8053 /* reset to prevent losing 1st rx packet intermittently */
8054 tw32_f(MAC_RX_MODE
, RX_MODE_RESET
);
8058 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
8059 tp
->mac_mode
&= MAC_MODE_APE_TX_EN
| MAC_MODE_APE_RX_EN
;
8062 tp
->mac_mode
|= MAC_MODE_TXSTAT_ENABLE
| MAC_MODE_RXSTAT_ENABLE
|
8063 MAC_MODE_TDE_ENABLE
| MAC_MODE_RDE_ENABLE
| MAC_MODE_FHDE_ENABLE
;
8064 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
8065 !(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) &&
8066 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
)
8067 tp
->mac_mode
|= MAC_MODE_LINK_POLARITY
;
8068 tw32_f(MAC_MODE
, tp
->mac_mode
| MAC_MODE_RXSTAT_CLEAR
| MAC_MODE_TXSTAT_CLEAR
);
8071 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8072 * If TG3_FLG2_IS_NIC is zero, we should read the
8073 * register to preserve the GPIO settings for LOMs. The GPIOs,
8074 * whether used as inputs or outputs, are set by boot code after
8077 if (!(tp
->tg3_flags2
& TG3_FLG2_IS_NIC
)) {
8080 gpio_mask
= GRC_LCLCTRL_GPIO_OE0
| GRC_LCLCTRL_GPIO_OE1
|
8081 GRC_LCLCTRL_GPIO_OE2
| GRC_LCLCTRL_GPIO_OUTPUT0
|
8082 GRC_LCLCTRL_GPIO_OUTPUT1
| GRC_LCLCTRL_GPIO_OUTPUT2
;
8084 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
)
8085 gpio_mask
|= GRC_LCLCTRL_GPIO_OE3
|
8086 GRC_LCLCTRL_GPIO_OUTPUT3
;
8088 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
)
8089 gpio_mask
|= GRC_LCLCTRL_GPIO_UART_SEL
;
8091 tp
->grc_local_ctrl
&= ~gpio_mask
;
8092 tp
->grc_local_ctrl
|= tr32(GRC_LOCAL_CTRL
) & gpio_mask
;
8094 /* GPIO1 must be driven high for eeprom write protect */
8095 if (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
)
8096 tp
->grc_local_ctrl
|= (GRC_LCLCTRL_GPIO_OE1
|
8097 GRC_LCLCTRL_GPIO_OUTPUT1
);
8099 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
);
8102 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSIX
) {
8103 val
= tr32(MSGINT_MODE
);
8104 val
|= MSGINT_MODE_MULTIVEC_EN
| MSGINT_MODE_ENABLE
;
8105 tw32(MSGINT_MODE
, val
);
8108 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
8109 tw32_f(DMAC_MODE
, DMAC_MODE_ENABLE
);
8113 val
= (WDMAC_MODE_ENABLE
| WDMAC_MODE_TGTABORT_ENAB
|
8114 WDMAC_MODE_MSTABORT_ENAB
| WDMAC_MODE_PARITYERR_ENAB
|
8115 WDMAC_MODE_ADDROFLOW_ENAB
| WDMAC_MODE_FIFOOFLOW_ENAB
|
8116 WDMAC_MODE_FIFOURUN_ENAB
| WDMAC_MODE_FIFOOREAD_ENAB
|
8117 WDMAC_MODE_LNGREAD_ENAB
);
8119 /* If statement applies to 5705 and 5750 PCI devices only */
8120 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
8121 tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A0
) ||
8122 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
) {
8123 if ((tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) &&
8124 (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A1
||
8125 tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A2
)) {
8127 } else if (!(tr32(TG3PCI_PCISTATE
) & PCISTATE_BUS_SPEED_HIGH
) &&
8128 !(tp
->tg3_flags2
& TG3_FLG2_IS_5788
) &&
8129 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)) {
8130 val
|= WDMAC_MODE_RX_ACCEL
;
8134 /* Enable host coalescing bug fix */
8135 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
8136 val
|= WDMAC_MODE_STATUS_TAG_FIX
;
8138 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
8139 val
|= WDMAC_MODE_BURST_ALL_DATA
;
8141 tw32_f(WDMAC_MODE
, val
);
8144 if (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) {
8147 pci_read_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
8149 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
) {
8150 pcix_cmd
&= ~PCI_X_CMD_MAX_READ
;
8151 pcix_cmd
|= PCI_X_CMD_READ_2K
;
8152 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
8153 pcix_cmd
&= ~(PCI_X_CMD_MAX_SPLIT
| PCI_X_CMD_MAX_READ
);
8154 pcix_cmd
|= PCI_X_CMD_READ_2K
;
8156 pci_write_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
8160 tw32_f(RDMAC_MODE
, rdmac_mode
);
8163 tw32(RCVDCC_MODE
, RCVDCC_MODE_ENABLE
| RCVDCC_MODE_ATTN_ENABLE
);
8164 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
8165 tw32(MBFREE_MODE
, MBFREE_MODE_ENABLE
);
8167 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
)
8169 SNDDATAC_MODE_ENABLE
| SNDDATAC_MODE_CDELAY
);
8171 tw32(SNDDATAC_MODE
, SNDDATAC_MODE_ENABLE
);
8173 tw32(SNDBDC_MODE
, SNDBDC_MODE_ENABLE
| SNDBDC_MODE_ATTN_ENABLE
);
8174 tw32(RCVBDI_MODE
, RCVBDI_MODE_ENABLE
| RCVBDI_MODE_RCB_ATTN_ENAB
);
8175 tw32(RCVDBDI_MODE
, RCVDBDI_MODE_ENABLE
| RCVDBDI_MODE_INV_RING_SZ
);
8176 tw32(SNDDATAI_MODE
, SNDDATAI_MODE_ENABLE
);
8177 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
8178 tw32(SNDDATAI_MODE
, SNDDATAI_MODE_ENABLE
| 0x8);
8179 val
= SNDBDI_MODE_ENABLE
| SNDBDI_MODE_ATTN_ENABLE
;
8180 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)
8181 val
|= SNDBDI_MODE_MULTI_TXQ_EN
;
8182 tw32(SNDBDI_MODE
, val
);
8183 tw32(SNDBDS_MODE
, SNDBDS_MODE_ENABLE
| SNDBDS_MODE_ATTN_ENABLE
);
8185 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
) {
8186 err
= tg3_load_5701_a0_firmware_fix(tp
);
8191 if (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) {
8192 err
= tg3_load_tso_firmware(tp
);
8197 tp
->tx_mode
= TX_MODE_ENABLE
;
8198 tw32_f(MAC_TX_MODE
, tp
->tx_mode
);
8201 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_RSS
) {
8202 u32 reg
= MAC_RSS_INDIR_TBL_0
;
8203 u8
*ent
= (u8
*)&val
;
8205 /* Setup the indirection table */
8206 for (i
= 0; i
< TG3_RSS_INDIR_TBL_SIZE
; i
++) {
8207 int idx
= i
% sizeof(val
);
8209 ent
[idx
] = i
% (tp
->irq_cnt
- 1);
8210 if (idx
== sizeof(val
) - 1) {
8216 /* Setup the "secret" hash key. */
8217 tw32(MAC_RSS_HASH_KEY_0
, 0x5f865437);
8218 tw32(MAC_RSS_HASH_KEY_1
, 0xe4ac62cc);
8219 tw32(MAC_RSS_HASH_KEY_2
, 0x50103a45);
8220 tw32(MAC_RSS_HASH_KEY_3
, 0x36621985);
8221 tw32(MAC_RSS_HASH_KEY_4
, 0xbf14c0e8);
8222 tw32(MAC_RSS_HASH_KEY_5
, 0x1bc27a1e);
8223 tw32(MAC_RSS_HASH_KEY_6
, 0x84f4b556);
8224 tw32(MAC_RSS_HASH_KEY_7
, 0x094ea6fe);
8225 tw32(MAC_RSS_HASH_KEY_8
, 0x7dda01e7);
8226 tw32(MAC_RSS_HASH_KEY_9
, 0xc04d7481);
8229 tp
->rx_mode
= RX_MODE_ENABLE
;
8230 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
8231 tp
->rx_mode
|= RX_MODE_IPV6_CSUM_ENABLE
;
8233 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_RSS
)
8234 tp
->rx_mode
|= RX_MODE_RSS_ENABLE
|
8235 RX_MODE_RSS_ITBL_HASH_BITS_7
|
8236 RX_MODE_RSS_IPV6_HASH_EN
|
8237 RX_MODE_RSS_TCP_IPV6_HASH_EN
|
8238 RX_MODE_RSS_IPV4_HASH_EN
|
8239 RX_MODE_RSS_TCP_IPV4_HASH_EN
;
8241 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
8244 tw32(MAC_LED_CTRL
, tp
->led_ctrl
);
8246 tw32(MAC_MI_STAT
, MAC_MI_STAT_LNKSTAT_ATTN_ENAB
);
8247 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
8248 tw32_f(MAC_RX_MODE
, RX_MODE_RESET
);
8251 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
8254 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
8255 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) &&
8256 !(tp
->tg3_flags2
& TG3_FLG2_SERDES_PREEMPHASIS
)) {
8257 /* Set drive transmission level to 1.2V */
8258 /* only if the signal pre-emphasis bit is not set */
8259 val
= tr32(MAC_SERDES_CFG
);
8262 tw32(MAC_SERDES_CFG
, val
);
8264 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5703_A1
)
8265 tw32(MAC_SERDES_CFG
, 0x616000);
8268 /* Prevent chip from dropping frames when flow control
8271 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
8275 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME
, val
);
8277 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
&&
8278 (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)) {
8279 /* Use hardware link auto-negotiation */
8280 tp
->tg3_flags2
|= TG3_FLG2_HW_AUTONEG
;
8283 if ((tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
) &&
8284 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
)) {
8287 tmp
= tr32(SERDES_RX_CTRL
);
8288 tw32(SERDES_RX_CTRL
, tmp
| SERDES_RX_SIG_DETECT
);
8289 tp
->grc_local_ctrl
&= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT
;
8290 tp
->grc_local_ctrl
|= GRC_LCLCTRL_USE_SIG_DETECT
;
8291 tw32(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
);
8294 if (!(tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
)) {
8295 if (tp
->link_config
.phy_is_low_power
) {
8296 tp
->link_config
.phy_is_low_power
= 0;
8297 tp
->link_config
.speed
= tp
->link_config
.orig_speed
;
8298 tp
->link_config
.duplex
= tp
->link_config
.orig_duplex
;
8299 tp
->link_config
.autoneg
= tp
->link_config
.orig_autoneg
;
8302 err
= tg3_setup_phy(tp
, 0);
8306 if (!(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) &&
8307 !(tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
)) {
8310 /* Clear CRC stats. */
8311 if (!tg3_readphy(tp
, MII_TG3_TEST1
, &tmp
)) {
8312 tg3_writephy(tp
, MII_TG3_TEST1
,
8313 tmp
| MII_TG3_TEST1_CRC_EN
);
8314 tg3_readphy(tp
, 0x14, &tmp
);
8319 __tg3_set_rx_mode(tp
->dev
);
8321 /* Initialize receive rules. */
8322 tw32(MAC_RCV_RULE_0
, 0xc2000000 & RCV_RULE_DISABLE_MASK
);
8323 tw32(MAC_RCV_VALUE_0
, 0xffffffff & RCV_RULE_DISABLE_MASK
);
8324 tw32(MAC_RCV_RULE_1
, 0x86000004 & RCV_RULE_DISABLE_MASK
);
8325 tw32(MAC_RCV_VALUE_1
, 0xffffffff & RCV_RULE_DISABLE_MASK
);
8327 if ((tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
8328 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
8332 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)
8336 tw32(MAC_RCV_RULE_15
, 0); tw32(MAC_RCV_VALUE_15
, 0);
8338 tw32(MAC_RCV_RULE_14
, 0); tw32(MAC_RCV_VALUE_14
, 0);
8340 tw32(MAC_RCV_RULE_13
, 0); tw32(MAC_RCV_VALUE_13
, 0);
8342 tw32(MAC_RCV_RULE_12
, 0); tw32(MAC_RCV_VALUE_12
, 0);
8344 tw32(MAC_RCV_RULE_11
, 0); tw32(MAC_RCV_VALUE_11
, 0);
8346 tw32(MAC_RCV_RULE_10
, 0); tw32(MAC_RCV_VALUE_10
, 0);
8348 tw32(MAC_RCV_RULE_9
, 0); tw32(MAC_RCV_VALUE_9
, 0);
8350 tw32(MAC_RCV_RULE_8
, 0); tw32(MAC_RCV_VALUE_8
, 0);
8352 tw32(MAC_RCV_RULE_7
, 0); tw32(MAC_RCV_VALUE_7
, 0);
8354 tw32(MAC_RCV_RULE_6
, 0); tw32(MAC_RCV_VALUE_6
, 0);
8356 tw32(MAC_RCV_RULE_5
, 0); tw32(MAC_RCV_VALUE_5
, 0);
8358 tw32(MAC_RCV_RULE_4
, 0); tw32(MAC_RCV_VALUE_4
, 0);
8360 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
8362 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
8370 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
8371 /* Write our heartbeat update interval to APE. */
8372 tg3_ape_write32(tp
, TG3_APE_HOST_HEARTBEAT_INT_MS
,
8373 APE_HOST_HEARTBEAT_INT_DISABLE
);
8375 tg3_write_sig_post_reset(tp
, RESET_KIND_INIT
);
8380 /* Called at device open time to get the chip ready for
8381 * packet processing. Invoked with tp->lock held.
8383 static int tg3_init_hw(struct tg3
*tp
, int reset_phy
)
8385 tg3_switch_clocks(tp
);
8387 tw32(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
8389 return tg3_reset_hw(tp
, reset_phy
);
8392 #define TG3_STAT_ADD32(PSTAT, REG) \
8393 do { u32 __val = tr32(REG); \
8394 (PSTAT)->low += __val; \
8395 if ((PSTAT)->low < __val) \
8396 (PSTAT)->high += 1; \
8399 static void tg3_periodic_fetch_stats(struct tg3
*tp
)
8401 struct tg3_hw_stats
*sp
= tp
->hw_stats
;
8403 if (!netif_carrier_ok(tp
->dev
))
8406 TG3_STAT_ADD32(&sp
->tx_octets
, MAC_TX_STATS_OCTETS
);
8407 TG3_STAT_ADD32(&sp
->tx_collisions
, MAC_TX_STATS_COLLISIONS
);
8408 TG3_STAT_ADD32(&sp
->tx_xon_sent
, MAC_TX_STATS_XON_SENT
);
8409 TG3_STAT_ADD32(&sp
->tx_xoff_sent
, MAC_TX_STATS_XOFF_SENT
);
8410 TG3_STAT_ADD32(&sp
->tx_mac_errors
, MAC_TX_STATS_MAC_ERRORS
);
8411 TG3_STAT_ADD32(&sp
->tx_single_collisions
, MAC_TX_STATS_SINGLE_COLLISIONS
);
8412 TG3_STAT_ADD32(&sp
->tx_mult_collisions
, MAC_TX_STATS_MULT_COLLISIONS
);
8413 TG3_STAT_ADD32(&sp
->tx_deferred
, MAC_TX_STATS_DEFERRED
);
8414 TG3_STAT_ADD32(&sp
->tx_excessive_collisions
, MAC_TX_STATS_EXCESSIVE_COL
);
8415 TG3_STAT_ADD32(&sp
->tx_late_collisions
, MAC_TX_STATS_LATE_COL
);
8416 TG3_STAT_ADD32(&sp
->tx_ucast_packets
, MAC_TX_STATS_UCAST
);
8417 TG3_STAT_ADD32(&sp
->tx_mcast_packets
, MAC_TX_STATS_MCAST
);
8418 TG3_STAT_ADD32(&sp
->tx_bcast_packets
, MAC_TX_STATS_BCAST
);
8420 TG3_STAT_ADD32(&sp
->rx_octets
, MAC_RX_STATS_OCTETS
);
8421 TG3_STAT_ADD32(&sp
->rx_fragments
, MAC_RX_STATS_FRAGMENTS
);
8422 TG3_STAT_ADD32(&sp
->rx_ucast_packets
, MAC_RX_STATS_UCAST
);
8423 TG3_STAT_ADD32(&sp
->rx_mcast_packets
, MAC_RX_STATS_MCAST
);
8424 TG3_STAT_ADD32(&sp
->rx_bcast_packets
, MAC_RX_STATS_BCAST
);
8425 TG3_STAT_ADD32(&sp
->rx_fcs_errors
, MAC_RX_STATS_FCS_ERRORS
);
8426 TG3_STAT_ADD32(&sp
->rx_align_errors
, MAC_RX_STATS_ALIGN_ERRORS
);
8427 TG3_STAT_ADD32(&sp
->rx_xon_pause_rcvd
, MAC_RX_STATS_XON_PAUSE_RECVD
);
8428 TG3_STAT_ADD32(&sp
->rx_xoff_pause_rcvd
, MAC_RX_STATS_XOFF_PAUSE_RECVD
);
8429 TG3_STAT_ADD32(&sp
->rx_mac_ctrl_rcvd
, MAC_RX_STATS_MAC_CTRL_RECVD
);
8430 TG3_STAT_ADD32(&sp
->rx_xoff_entered
, MAC_RX_STATS_XOFF_ENTERED
);
8431 TG3_STAT_ADD32(&sp
->rx_frame_too_long_errors
, MAC_RX_STATS_FRAME_TOO_LONG
);
8432 TG3_STAT_ADD32(&sp
->rx_jabbers
, MAC_RX_STATS_JABBERS
);
8433 TG3_STAT_ADD32(&sp
->rx_undersize_packets
, MAC_RX_STATS_UNDERSIZE
);
8435 TG3_STAT_ADD32(&sp
->rxbds_empty
, RCVLPC_NO_RCV_BD_CNT
);
8436 TG3_STAT_ADD32(&sp
->rx_discards
, RCVLPC_IN_DISCARDS_CNT
);
8437 TG3_STAT_ADD32(&sp
->rx_errors
, RCVLPC_IN_ERRORS_CNT
);
8440 static void tg3_timer(unsigned long __opaque
)
8442 struct tg3
*tp
= (struct tg3
*) __opaque
;
8447 spin_lock(&tp
->lock
);
8449 if (!(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)) {
8450 /* All of this garbage is because when using non-tagged
8451 * IRQ status the mailbox/status_block protocol the chip
8452 * uses with the cpu is race prone.
8454 if (tp
->napi
[0].hw_status
->status
& SD_STATUS_UPDATED
) {
8455 tw32(GRC_LOCAL_CTRL
,
8456 tp
->grc_local_ctrl
| GRC_LCLCTRL_SETINT
);
8458 tw32(HOSTCC_MODE
, tp
->coalesce_mode
|
8459 HOSTCC_MODE_ENABLE
| HOSTCC_MODE_NOW
);
8462 if (!(tr32(WDMAC_MODE
) & WDMAC_MODE_ENABLE
)) {
8463 tp
->tg3_flags2
|= TG3_FLG2_RESTART_TIMER
;
8464 spin_unlock(&tp
->lock
);
8465 schedule_work(&tp
->reset_task
);
8470 /* This part only runs once per second. */
8471 if (!--tp
->timer_counter
) {
8472 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
8473 tg3_periodic_fetch_stats(tp
);
8475 if (tp
->tg3_flags
& TG3_FLAG_USE_LINKCHG_REG
) {
8479 mac_stat
= tr32(MAC_STATUS
);
8482 if (tp
->tg3_flags
& TG3_FLAG_USE_MI_INTERRUPT
) {
8483 if (mac_stat
& MAC_STATUS_MI_INTERRUPT
)
8485 } else if (mac_stat
& MAC_STATUS_LNKSTATE_CHANGED
)
8489 tg3_setup_phy(tp
, 0);
8490 } else if (tp
->tg3_flags
& TG3_FLAG_POLL_SERDES
) {
8491 u32 mac_stat
= tr32(MAC_STATUS
);
8494 if (netif_carrier_ok(tp
->dev
) &&
8495 (mac_stat
& MAC_STATUS_LNKSTATE_CHANGED
)) {
8498 if (! netif_carrier_ok(tp
->dev
) &&
8499 (mac_stat
& (MAC_STATUS_PCS_SYNCED
|
8500 MAC_STATUS_SIGNAL_DET
))) {
8504 if (!tp
->serdes_counter
) {
8507 ~MAC_MODE_PORT_MODE_MASK
));
8509 tw32_f(MAC_MODE
, tp
->mac_mode
);
8512 tg3_setup_phy(tp
, 0);
8514 } else if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
)
8515 tg3_serdes_parallel_detect(tp
);
8517 tp
->timer_counter
= tp
->timer_multiplier
;
8520 /* Heartbeat is only sent once every 2 seconds.
8522 * The heartbeat is to tell the ASF firmware that the host
8523 * driver is still alive. In the event that the OS crashes,
8524 * ASF needs to reset the hardware to free up the FIFO space
8525 * that may be filled with rx packets destined for the host.
8526 * If the FIFO is full, ASF will no longer function properly.
8528 * Unintended resets have been reported on real time kernels
8529 * where the timer doesn't run on time. Netpoll will also have
8532 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8533 * to check the ring condition when the heartbeat is expiring
8534 * before doing the reset. This will prevent most unintended
8537 if (!--tp
->asf_counter
) {
8538 if ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) &&
8539 !(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)) {
8540 tg3_wait_for_event_ack(tp
);
8542 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_MBOX
,
8543 FWCMD_NICDRV_ALIVE3
);
8544 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_LEN_MBOX
, 4);
8545 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
,
8546 TG3_FW_UPDATE_TIMEOUT_SEC
);
8548 tg3_generate_fw_event(tp
);
8550 tp
->asf_counter
= tp
->asf_multiplier
;
8553 spin_unlock(&tp
->lock
);
8556 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
8557 add_timer(&tp
->timer
);
8560 static int tg3_request_irq(struct tg3
*tp
, int irq_num
)
8563 unsigned long flags
;
8565 struct tg3_napi
*tnapi
= &tp
->napi
[irq_num
];
8567 if (tp
->irq_cnt
== 1)
8568 name
= tp
->dev
->name
;
8570 name
= &tnapi
->irq_lbl
[0];
8571 snprintf(name
, IFNAMSIZ
, "%s-%d", tp
->dev
->name
, irq_num
);
8572 name
[IFNAMSIZ
-1] = 0;
8575 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI_OR_MSIX
) {
8577 if (tp
->tg3_flags2
& TG3_FLG2_1SHOT_MSI
)
8579 flags
= IRQF_SAMPLE_RANDOM
;
8582 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)
8583 fn
= tg3_interrupt_tagged
;
8584 flags
= IRQF_SHARED
| IRQF_SAMPLE_RANDOM
;
8587 return request_irq(tnapi
->irq_vec
, fn
, flags
, name
, tnapi
);
8590 static int tg3_test_interrupt(struct tg3
*tp
)
8592 struct tg3_napi
*tnapi
= &tp
->napi
[0];
8593 struct net_device
*dev
= tp
->dev
;
8594 int err
, i
, intr_ok
= 0;
8597 if (!netif_running(dev
))
8600 tg3_disable_ints(tp
);
8602 free_irq(tnapi
->irq_vec
, tnapi
);
8605 * Turn off MSI one shot mode. Otherwise this test has no
8606 * observable way to know whether the interrupt was delivered.
8608 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
8609 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
) &&
8610 (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
)) {
8611 val
= tr32(MSGINT_MODE
) | MSGINT_MODE_ONE_SHOT_DISABLE
;
8612 tw32(MSGINT_MODE
, val
);
8615 err
= request_irq(tnapi
->irq_vec
, tg3_test_isr
,
8616 IRQF_SHARED
| IRQF_SAMPLE_RANDOM
, dev
->name
, tnapi
);
8620 tnapi
->hw_status
->status
&= ~SD_STATUS_UPDATED
;
8621 tg3_enable_ints(tp
);
8623 tw32_f(HOSTCC_MODE
, tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
|
8626 for (i
= 0; i
< 5; i
++) {
8627 u32 int_mbox
, misc_host_ctrl
;
8629 int_mbox
= tr32_mailbox(tnapi
->int_mbox
);
8630 misc_host_ctrl
= tr32(TG3PCI_MISC_HOST_CTRL
);
8632 if ((int_mbox
!= 0) ||
8633 (misc_host_ctrl
& MISC_HOST_CTRL_MASK_PCI_INT
)) {
8641 tg3_disable_ints(tp
);
8643 free_irq(tnapi
->irq_vec
, tnapi
);
8645 err
= tg3_request_irq(tp
, 0);
8651 /* Reenable MSI one shot mode. */
8652 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
8653 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
) &&
8654 (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
)) {
8655 val
= tr32(MSGINT_MODE
) & ~MSGINT_MODE_ONE_SHOT_DISABLE
;
8656 tw32(MSGINT_MODE
, val
);
8664 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8665 * successfully restored
8667 static int tg3_test_msi(struct tg3
*tp
)
8672 if (!(tp
->tg3_flags2
& TG3_FLG2_USING_MSI
))
8675 /* Turn off SERR reporting in case MSI terminates with Master
8678 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
8679 pci_write_config_word(tp
->pdev
, PCI_COMMAND
,
8680 pci_cmd
& ~PCI_COMMAND_SERR
);
8682 err
= tg3_test_interrupt(tp
);
8684 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
8689 /* other failures */
8693 /* MSI test failed, go back to INTx mode */
8694 netdev_warn(tp
->dev
, "No interrupt was generated using MSI. Switching "
8695 "to INTx mode. Please report this failure to the PCI "
8696 "maintainer and include system chipset information\n");
8698 free_irq(tp
->napi
[0].irq_vec
, &tp
->napi
[0]);
8700 pci_disable_msi(tp
->pdev
);
8702 tp
->tg3_flags2
&= ~TG3_FLG2_USING_MSI
;
8704 err
= tg3_request_irq(tp
, 0);
8708 /* Need to reset the chip because the MSI cycle may have terminated
8709 * with Master Abort.
8711 tg3_full_lock(tp
, 1);
8713 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
8714 err
= tg3_init_hw(tp
, 1);
8716 tg3_full_unlock(tp
);
8719 free_irq(tp
->napi
[0].irq_vec
, &tp
->napi
[0]);
8724 static int tg3_request_firmware(struct tg3
*tp
)
8726 const __be32
*fw_data
;
8728 if (request_firmware(&tp
->fw
, tp
->fw_needed
, &tp
->pdev
->dev
)) {
8729 netdev_err(tp
->dev
, "Failed to load firmware \"%s\"\n",
8734 fw_data
= (void *)tp
->fw
->data
;
8736 /* Firmware blob starts with version numbers, followed by
8737 * start address and _full_ length including BSS sections
8738 * (which must be longer than the actual data, of course
8741 tp
->fw_len
= be32_to_cpu(fw_data
[2]); /* includes bss */
8742 if (tp
->fw_len
< (tp
->fw
->size
- 12)) {
8743 netdev_err(tp
->dev
, "bogus length %d in \"%s\"\n",
8744 tp
->fw_len
, tp
->fw_needed
);
8745 release_firmware(tp
->fw
);
8750 /* We no longer need firmware; we have it. */
8751 tp
->fw_needed
= NULL
;
8755 static bool tg3_enable_msix(struct tg3
*tp
)
8757 int i
, rc
, cpus
= num_online_cpus();
8758 struct msix_entry msix_ent
[tp
->irq_max
];
8761 /* Just fallback to the simpler MSI mode. */
8765 * We want as many rx rings enabled as there are cpus.
8766 * The first MSIX vector only deals with link interrupts, etc,
8767 * so we add one to the number of vectors we are requesting.
8769 tp
->irq_cnt
= min_t(unsigned, cpus
+ 1, tp
->irq_max
);
8771 for (i
= 0; i
< tp
->irq_max
; i
++) {
8772 msix_ent
[i
].entry
= i
;
8773 msix_ent
[i
].vector
= 0;
8776 rc
= pci_enable_msix(tp
->pdev
, msix_ent
, tp
->irq_cnt
);
8778 if (rc
< TG3_RSS_MIN_NUM_MSIX_VECS
)
8780 if (pci_enable_msix(tp
->pdev
, msix_ent
, rc
))
8782 netdev_notice(tp
->dev
, "Requested %d MSI-X vectors, received %d\n",
8787 tp
->tg3_flags3
|= TG3_FLG3_ENABLE_RSS
;
8789 for (i
= 0; i
< tp
->irq_max
; i
++)
8790 tp
->napi
[i
].irq_vec
= msix_ent
[i
].vector
;
8792 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
) {
8793 tp
->tg3_flags3
|= TG3_FLG3_ENABLE_TSS
;
8794 tp
->dev
->real_num_tx_queues
= tp
->irq_cnt
- 1;
8796 tp
->dev
->real_num_tx_queues
= 1;
8801 static void tg3_ints_init(struct tg3
*tp
)
8803 if ((tp
->tg3_flags
& TG3_FLAG_SUPPORT_MSI_OR_MSIX
) &&
8804 !(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)) {
8805 /* All MSI supporting chips should support tagged
8806 * status. Assert that this is the case.
8808 netdev_warn(tp
->dev
,
8809 "MSI without TAGGED_STATUS? Not using MSI\n");
8813 if ((tp
->tg3_flags
& TG3_FLAG_SUPPORT_MSIX
) && tg3_enable_msix(tp
))
8814 tp
->tg3_flags2
|= TG3_FLG2_USING_MSIX
;
8815 else if ((tp
->tg3_flags
& TG3_FLAG_SUPPORT_MSI
) &&
8816 pci_enable_msi(tp
->pdev
) == 0)
8817 tp
->tg3_flags2
|= TG3_FLG2_USING_MSI
;
8819 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI_OR_MSIX
) {
8820 u32 msi_mode
= tr32(MSGINT_MODE
);
8821 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSIX
)
8822 msi_mode
|= MSGINT_MODE_MULTIVEC_EN
;
8823 tw32(MSGINT_MODE
, msi_mode
| MSGINT_MODE_ENABLE
);
8826 if (!(tp
->tg3_flags2
& TG3_FLG2_USING_MSIX
)) {
8828 tp
->napi
[0].irq_vec
= tp
->pdev
->irq
;
8829 tp
->dev
->real_num_tx_queues
= 1;
8833 static void tg3_ints_fini(struct tg3
*tp
)
8835 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSIX
)
8836 pci_disable_msix(tp
->pdev
);
8837 else if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
)
8838 pci_disable_msi(tp
->pdev
);
8839 tp
->tg3_flags2
&= ~TG3_FLG2_USING_MSI_OR_MSIX
;
8840 tp
->tg3_flags3
&= ~TG3_FLG3_ENABLE_RSS
;
8843 static int tg3_open(struct net_device
*dev
)
8845 struct tg3
*tp
= netdev_priv(dev
);
8848 if (tp
->fw_needed
) {
8849 err
= tg3_request_firmware(tp
);
8850 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
) {
8854 netdev_warn(tp
->dev
, "TSO capability disabled\n");
8855 tp
->tg3_flags2
&= ~TG3_FLG2_TSO_CAPABLE
;
8856 } else if (!(tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
)) {
8857 netdev_notice(tp
->dev
, "TSO capability restored\n");
8858 tp
->tg3_flags2
|= TG3_FLG2_TSO_CAPABLE
;
8862 netif_carrier_off(tp
->dev
);
8864 err
= tg3_set_power_state(tp
, PCI_D0
);
8868 tg3_full_lock(tp
, 0);
8870 tg3_disable_ints(tp
);
8871 tp
->tg3_flags
&= ~TG3_FLAG_INIT_COMPLETE
;
8873 tg3_full_unlock(tp
);
8876 * Setup interrupts first so we know how
8877 * many NAPI resources to allocate
8881 /* The placement of this call is tied
8882 * to the setup and use of Host TX descriptors.
8884 err
= tg3_alloc_consistent(tp
);
8888 tg3_napi_enable(tp
);
8890 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
8891 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
8892 err
= tg3_request_irq(tp
, i
);
8894 for (i
--; i
>= 0; i
--)
8895 free_irq(tnapi
->irq_vec
, tnapi
);
8903 tg3_full_lock(tp
, 0);
8905 err
= tg3_init_hw(tp
, 1);
8907 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
8910 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)
8911 tp
->timer_offset
= HZ
;
8913 tp
->timer_offset
= HZ
/ 10;
8915 BUG_ON(tp
->timer_offset
> HZ
);
8916 tp
->timer_counter
= tp
->timer_multiplier
=
8917 (HZ
/ tp
->timer_offset
);
8918 tp
->asf_counter
= tp
->asf_multiplier
=
8919 ((HZ
/ tp
->timer_offset
) * 2);
8921 init_timer(&tp
->timer
);
8922 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
8923 tp
->timer
.data
= (unsigned long) tp
;
8924 tp
->timer
.function
= tg3_timer
;
8927 tg3_full_unlock(tp
);
8932 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
8933 err
= tg3_test_msi(tp
);
8936 tg3_full_lock(tp
, 0);
8937 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
8939 tg3_full_unlock(tp
);
8944 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5717
&&
8945 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_57765
&&
8946 (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) &&
8947 (tp
->tg3_flags2
& TG3_FLG2_1SHOT_MSI
)) {
8948 u32 val
= tr32(PCIE_TRANSACTION_CFG
);
8950 tw32(PCIE_TRANSACTION_CFG
,
8951 val
| PCIE_TRANS_CFG_1SHOT_MSI
);
8957 tg3_full_lock(tp
, 0);
8959 add_timer(&tp
->timer
);
8960 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
8961 tg3_enable_ints(tp
);
8963 tg3_full_unlock(tp
);
8965 netif_tx_start_all_queues(dev
);
8970 for (i
= tp
->irq_cnt
- 1; i
>= 0; i
--) {
8971 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
8972 free_irq(tnapi
->irq_vec
, tnapi
);
8976 tg3_napi_disable(tp
);
8977 tg3_free_consistent(tp
);
8984 static struct net_device_stats
*tg3_get_stats(struct net_device
*);
8985 static struct tg3_ethtool_stats
*tg3_get_estats(struct tg3
*);
8987 static int tg3_close(struct net_device
*dev
)
8990 struct tg3
*tp
= netdev_priv(dev
);
8992 tg3_napi_disable(tp
);
8993 cancel_work_sync(&tp
->reset_task
);
8995 netif_tx_stop_all_queues(dev
);
8997 del_timer_sync(&tp
->timer
);
9001 tg3_full_lock(tp
, 1);
9003 tg3_disable_ints(tp
);
9005 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
9007 tp
->tg3_flags
&= ~TG3_FLAG_INIT_COMPLETE
;
9009 tg3_full_unlock(tp
);
9011 for (i
= tp
->irq_cnt
- 1; i
>= 0; i
--) {
9012 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
9013 free_irq(tnapi
->irq_vec
, tnapi
);
9018 memcpy(&tp
->net_stats_prev
, tg3_get_stats(tp
->dev
),
9019 sizeof(tp
->net_stats_prev
));
9020 memcpy(&tp
->estats_prev
, tg3_get_estats(tp
),
9021 sizeof(tp
->estats_prev
));
9023 tg3_free_consistent(tp
);
9025 tg3_set_power_state(tp
, PCI_D3hot
);
9027 netif_carrier_off(tp
->dev
);
9032 static inline unsigned long get_stat64(tg3_stat64_t
*val
)
9036 #if (BITS_PER_LONG == 32)
9039 ret
= ((u64
)val
->high
<< 32) | ((u64
)val
->low
);
9044 static inline u64
get_estat64(tg3_stat64_t
*val
)
9046 return ((u64
)val
->high
<< 32) | ((u64
)val
->low
);
9049 static unsigned long calc_crc_errors(struct tg3
*tp
)
9051 struct tg3_hw_stats
*hw_stats
= tp
->hw_stats
;
9053 if (!(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) &&
9054 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
9055 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)) {
9058 spin_lock_bh(&tp
->lock
);
9059 if (!tg3_readphy(tp
, MII_TG3_TEST1
, &val
)) {
9060 tg3_writephy(tp
, MII_TG3_TEST1
,
9061 val
| MII_TG3_TEST1_CRC_EN
);
9062 tg3_readphy(tp
, 0x14, &val
);
9065 spin_unlock_bh(&tp
->lock
);
9067 tp
->phy_crc_errors
+= val
;
9069 return tp
->phy_crc_errors
;
9072 return get_stat64(&hw_stats
->rx_fcs_errors
);
9075 #define ESTAT_ADD(member) \
9076 estats->member = old_estats->member + \
9077 get_estat64(&hw_stats->member)
9079 static struct tg3_ethtool_stats
*tg3_get_estats(struct tg3
*tp
)
9081 struct tg3_ethtool_stats
*estats
= &tp
->estats
;
9082 struct tg3_ethtool_stats
*old_estats
= &tp
->estats_prev
;
9083 struct tg3_hw_stats
*hw_stats
= tp
->hw_stats
;
9088 ESTAT_ADD(rx_octets
);
9089 ESTAT_ADD(rx_fragments
);
9090 ESTAT_ADD(rx_ucast_packets
);
9091 ESTAT_ADD(rx_mcast_packets
);
9092 ESTAT_ADD(rx_bcast_packets
);
9093 ESTAT_ADD(rx_fcs_errors
);
9094 ESTAT_ADD(rx_align_errors
);
9095 ESTAT_ADD(rx_xon_pause_rcvd
);
9096 ESTAT_ADD(rx_xoff_pause_rcvd
);
9097 ESTAT_ADD(rx_mac_ctrl_rcvd
);
9098 ESTAT_ADD(rx_xoff_entered
);
9099 ESTAT_ADD(rx_frame_too_long_errors
);
9100 ESTAT_ADD(rx_jabbers
);
9101 ESTAT_ADD(rx_undersize_packets
);
9102 ESTAT_ADD(rx_in_length_errors
);
9103 ESTAT_ADD(rx_out_length_errors
);
9104 ESTAT_ADD(rx_64_or_less_octet_packets
);
9105 ESTAT_ADD(rx_65_to_127_octet_packets
);
9106 ESTAT_ADD(rx_128_to_255_octet_packets
);
9107 ESTAT_ADD(rx_256_to_511_octet_packets
);
9108 ESTAT_ADD(rx_512_to_1023_octet_packets
);
9109 ESTAT_ADD(rx_1024_to_1522_octet_packets
);
9110 ESTAT_ADD(rx_1523_to_2047_octet_packets
);
9111 ESTAT_ADD(rx_2048_to_4095_octet_packets
);
9112 ESTAT_ADD(rx_4096_to_8191_octet_packets
);
9113 ESTAT_ADD(rx_8192_to_9022_octet_packets
);
9115 ESTAT_ADD(tx_octets
);
9116 ESTAT_ADD(tx_collisions
);
9117 ESTAT_ADD(tx_xon_sent
);
9118 ESTAT_ADD(tx_xoff_sent
);
9119 ESTAT_ADD(tx_flow_control
);
9120 ESTAT_ADD(tx_mac_errors
);
9121 ESTAT_ADD(tx_single_collisions
);
9122 ESTAT_ADD(tx_mult_collisions
);
9123 ESTAT_ADD(tx_deferred
);
9124 ESTAT_ADD(tx_excessive_collisions
);
9125 ESTAT_ADD(tx_late_collisions
);
9126 ESTAT_ADD(tx_collide_2times
);
9127 ESTAT_ADD(tx_collide_3times
);
9128 ESTAT_ADD(tx_collide_4times
);
9129 ESTAT_ADD(tx_collide_5times
);
9130 ESTAT_ADD(tx_collide_6times
);
9131 ESTAT_ADD(tx_collide_7times
);
9132 ESTAT_ADD(tx_collide_8times
);
9133 ESTAT_ADD(tx_collide_9times
);
9134 ESTAT_ADD(tx_collide_10times
);
9135 ESTAT_ADD(tx_collide_11times
);
9136 ESTAT_ADD(tx_collide_12times
);
9137 ESTAT_ADD(tx_collide_13times
);
9138 ESTAT_ADD(tx_collide_14times
);
9139 ESTAT_ADD(tx_collide_15times
);
9140 ESTAT_ADD(tx_ucast_packets
);
9141 ESTAT_ADD(tx_mcast_packets
);
9142 ESTAT_ADD(tx_bcast_packets
);
9143 ESTAT_ADD(tx_carrier_sense_errors
);
9144 ESTAT_ADD(tx_discards
);
9145 ESTAT_ADD(tx_errors
);
9147 ESTAT_ADD(dma_writeq_full
);
9148 ESTAT_ADD(dma_write_prioq_full
);
9149 ESTAT_ADD(rxbds_empty
);
9150 ESTAT_ADD(rx_discards
);
9151 ESTAT_ADD(rx_errors
);
9152 ESTAT_ADD(rx_threshold_hit
);
9154 ESTAT_ADD(dma_readq_full
);
9155 ESTAT_ADD(dma_read_prioq_full
);
9156 ESTAT_ADD(tx_comp_queue_full
);
9158 ESTAT_ADD(ring_set_send_prod_index
);
9159 ESTAT_ADD(ring_status_update
);
9160 ESTAT_ADD(nic_irqs
);
9161 ESTAT_ADD(nic_avoided_irqs
);
9162 ESTAT_ADD(nic_tx_threshold_hit
);
9167 static struct net_device_stats
*tg3_get_stats(struct net_device
*dev
)
9169 struct tg3
*tp
= netdev_priv(dev
);
9170 struct net_device_stats
*stats
= &tp
->net_stats
;
9171 struct net_device_stats
*old_stats
= &tp
->net_stats_prev
;
9172 struct tg3_hw_stats
*hw_stats
= tp
->hw_stats
;
9177 stats
->rx_packets
= old_stats
->rx_packets
+
9178 get_stat64(&hw_stats
->rx_ucast_packets
) +
9179 get_stat64(&hw_stats
->rx_mcast_packets
) +
9180 get_stat64(&hw_stats
->rx_bcast_packets
);
9182 stats
->tx_packets
= old_stats
->tx_packets
+
9183 get_stat64(&hw_stats
->tx_ucast_packets
) +
9184 get_stat64(&hw_stats
->tx_mcast_packets
) +
9185 get_stat64(&hw_stats
->tx_bcast_packets
);
9187 stats
->rx_bytes
= old_stats
->rx_bytes
+
9188 get_stat64(&hw_stats
->rx_octets
);
9189 stats
->tx_bytes
= old_stats
->tx_bytes
+
9190 get_stat64(&hw_stats
->tx_octets
);
9192 stats
->rx_errors
= old_stats
->rx_errors
+
9193 get_stat64(&hw_stats
->rx_errors
);
9194 stats
->tx_errors
= old_stats
->tx_errors
+
9195 get_stat64(&hw_stats
->tx_errors
) +
9196 get_stat64(&hw_stats
->tx_mac_errors
) +
9197 get_stat64(&hw_stats
->tx_carrier_sense_errors
) +
9198 get_stat64(&hw_stats
->tx_discards
);
9200 stats
->multicast
= old_stats
->multicast
+
9201 get_stat64(&hw_stats
->rx_mcast_packets
);
9202 stats
->collisions
= old_stats
->collisions
+
9203 get_stat64(&hw_stats
->tx_collisions
);
9205 stats
->rx_length_errors
= old_stats
->rx_length_errors
+
9206 get_stat64(&hw_stats
->rx_frame_too_long_errors
) +
9207 get_stat64(&hw_stats
->rx_undersize_packets
);
9209 stats
->rx_over_errors
= old_stats
->rx_over_errors
+
9210 get_stat64(&hw_stats
->rxbds_empty
);
9211 stats
->rx_frame_errors
= old_stats
->rx_frame_errors
+
9212 get_stat64(&hw_stats
->rx_align_errors
);
9213 stats
->tx_aborted_errors
= old_stats
->tx_aborted_errors
+
9214 get_stat64(&hw_stats
->tx_discards
);
9215 stats
->tx_carrier_errors
= old_stats
->tx_carrier_errors
+
9216 get_stat64(&hw_stats
->tx_carrier_sense_errors
);
9218 stats
->rx_crc_errors
= old_stats
->rx_crc_errors
+
9219 calc_crc_errors(tp
);
9221 stats
->rx_missed_errors
= old_stats
->rx_missed_errors
+
9222 get_stat64(&hw_stats
->rx_discards
);
9227 static inline u32
calc_crc(unsigned char *buf
, int len
)
9235 for (j
= 0; j
< len
; j
++) {
9238 for (k
= 0; k
< 8; k
++) {
9251 static void tg3_set_multi(struct tg3
*tp
, unsigned int accept_all
)
9253 /* accept or reject all multicast frames */
9254 tw32(MAC_HASH_REG_0
, accept_all
? 0xffffffff : 0);
9255 tw32(MAC_HASH_REG_1
, accept_all
? 0xffffffff : 0);
9256 tw32(MAC_HASH_REG_2
, accept_all
? 0xffffffff : 0);
9257 tw32(MAC_HASH_REG_3
, accept_all
? 0xffffffff : 0);
9260 static void __tg3_set_rx_mode(struct net_device
*dev
)
9262 struct tg3
*tp
= netdev_priv(dev
);
9265 rx_mode
= tp
->rx_mode
& ~(RX_MODE_PROMISC
|
9266 RX_MODE_KEEP_VLAN_TAG
);
9268 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9271 #if TG3_VLAN_TAG_USED
9273 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
9274 rx_mode
|= RX_MODE_KEEP_VLAN_TAG
;
9276 /* By definition, VLAN is disabled always in this
9279 if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
9280 rx_mode
|= RX_MODE_KEEP_VLAN_TAG
;
9283 if (dev
->flags
& IFF_PROMISC
) {
9284 /* Promiscuous mode. */
9285 rx_mode
|= RX_MODE_PROMISC
;
9286 } else if (dev
->flags
& IFF_ALLMULTI
) {
9287 /* Accept all multicast. */
9288 tg3_set_multi(tp
, 1);
9289 } else if (netdev_mc_empty(dev
)) {
9290 /* Reject all multicast. */
9291 tg3_set_multi(tp
, 0);
9293 /* Accept one or more multicast(s). */
9294 struct netdev_hw_addr
*ha
;
9295 u32 mc_filter
[4] = { 0, };
9300 netdev_for_each_mc_addr(ha
, dev
) {
9301 crc
= calc_crc(ha
->addr
, ETH_ALEN
);
9303 regidx
= (bit
& 0x60) >> 5;
9305 mc_filter
[regidx
] |= (1 << bit
);
9308 tw32(MAC_HASH_REG_0
, mc_filter
[0]);
9309 tw32(MAC_HASH_REG_1
, mc_filter
[1]);
9310 tw32(MAC_HASH_REG_2
, mc_filter
[2]);
9311 tw32(MAC_HASH_REG_3
, mc_filter
[3]);
9314 if (rx_mode
!= tp
->rx_mode
) {
9315 tp
->rx_mode
= rx_mode
;
9316 tw32_f(MAC_RX_MODE
, rx_mode
);
9321 static void tg3_set_rx_mode(struct net_device
*dev
)
9323 struct tg3
*tp
= netdev_priv(dev
);
9325 if (!netif_running(dev
))
9328 tg3_full_lock(tp
, 0);
9329 __tg3_set_rx_mode(dev
);
9330 tg3_full_unlock(tp
);
9333 #define TG3_REGDUMP_LEN (32 * 1024)
9335 static int tg3_get_regs_len(struct net_device
*dev
)
9337 return TG3_REGDUMP_LEN
;
9340 static void tg3_get_regs(struct net_device
*dev
,
9341 struct ethtool_regs
*regs
, void *_p
)
9344 struct tg3
*tp
= netdev_priv(dev
);
9350 memset(p
, 0, TG3_REGDUMP_LEN
);
9352 if (tp
->link_config
.phy_is_low_power
)
9355 tg3_full_lock(tp
, 0);
9357 #define __GET_REG32(reg) (*(p)++ = tr32(reg))
9358 #define GET_REG32_LOOP(base,len) \
9359 do { p = (u32 *)(orig_p + (base)); \
9360 for (i = 0; i < len; i += 4) \
9361 __GET_REG32((base) + i); \
9363 #define GET_REG32_1(reg) \
9364 do { p = (u32 *)(orig_p + (reg)); \
9365 __GET_REG32((reg)); \
9368 GET_REG32_LOOP(TG3PCI_VENDOR
, 0xb0);
9369 GET_REG32_LOOP(MAILBOX_INTERRUPT_0
, 0x200);
9370 GET_REG32_LOOP(MAC_MODE
, 0x4f0);
9371 GET_REG32_LOOP(SNDDATAI_MODE
, 0xe0);
9372 GET_REG32_1(SNDDATAC_MODE
);
9373 GET_REG32_LOOP(SNDBDS_MODE
, 0x80);
9374 GET_REG32_LOOP(SNDBDI_MODE
, 0x48);
9375 GET_REG32_1(SNDBDC_MODE
);
9376 GET_REG32_LOOP(RCVLPC_MODE
, 0x20);
9377 GET_REG32_LOOP(RCVLPC_SELLST_BASE
, 0x15c);
9378 GET_REG32_LOOP(RCVDBDI_MODE
, 0x0c);
9379 GET_REG32_LOOP(RCVDBDI_JUMBO_BD
, 0x3c);
9380 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0
, 0x44);
9381 GET_REG32_1(RCVDCC_MODE
);
9382 GET_REG32_LOOP(RCVBDI_MODE
, 0x20);
9383 GET_REG32_LOOP(RCVCC_MODE
, 0x14);
9384 GET_REG32_LOOP(RCVLSC_MODE
, 0x08);
9385 GET_REG32_1(MBFREE_MODE
);
9386 GET_REG32_LOOP(HOSTCC_MODE
, 0x100);
9387 GET_REG32_LOOP(MEMARB_MODE
, 0x10);
9388 GET_REG32_LOOP(BUFMGR_MODE
, 0x58);
9389 GET_REG32_LOOP(RDMAC_MODE
, 0x08);
9390 GET_REG32_LOOP(WDMAC_MODE
, 0x08);
9391 GET_REG32_1(RX_CPU_MODE
);
9392 GET_REG32_1(RX_CPU_STATE
);
9393 GET_REG32_1(RX_CPU_PGMCTR
);
9394 GET_REG32_1(RX_CPU_HWBKPT
);
9395 GET_REG32_1(TX_CPU_MODE
);
9396 GET_REG32_1(TX_CPU_STATE
);
9397 GET_REG32_1(TX_CPU_PGMCTR
);
9398 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0
, 0x110);
9399 GET_REG32_LOOP(FTQ_RESET
, 0x120);
9400 GET_REG32_LOOP(MSGINT_MODE
, 0x0c);
9401 GET_REG32_1(DMAC_MODE
);
9402 GET_REG32_LOOP(GRC_MODE
, 0x4c);
9403 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
)
9404 GET_REG32_LOOP(NVRAM_CMD
, 0x24);
9407 #undef GET_REG32_LOOP
9410 tg3_full_unlock(tp
);
9413 static int tg3_get_eeprom_len(struct net_device
*dev
)
9415 struct tg3
*tp
= netdev_priv(dev
);
9417 return tp
->nvram_size
;
9420 static int tg3_get_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
, u8
*data
)
9422 struct tg3
*tp
= netdev_priv(dev
);
9425 u32 i
, offset
, len
, b_offset
, b_count
;
9428 if (tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
)
9431 if (tp
->link_config
.phy_is_low_power
)
9434 offset
= eeprom
->offset
;
9438 eeprom
->magic
= TG3_EEPROM_MAGIC
;
9441 /* adjustments to start on required 4 byte boundary */
9442 b_offset
= offset
& 3;
9443 b_count
= 4 - b_offset
;
9444 if (b_count
> len
) {
9445 /* i.e. offset=1 len=2 */
9448 ret
= tg3_nvram_read_be32(tp
, offset
-b_offset
, &val
);
9451 memcpy(data
, ((char*)&val
) + b_offset
, b_count
);
9454 eeprom
->len
+= b_count
;
9457 /* read bytes upto the last 4 byte boundary */
9458 pd
= &data
[eeprom
->len
];
9459 for (i
= 0; i
< (len
- (len
& 3)); i
+= 4) {
9460 ret
= tg3_nvram_read_be32(tp
, offset
+ i
, &val
);
9465 memcpy(pd
+ i
, &val
, 4);
9470 /* read last bytes not ending on 4 byte boundary */
9471 pd
= &data
[eeprom
->len
];
9473 b_offset
= offset
+ len
- b_count
;
9474 ret
= tg3_nvram_read_be32(tp
, b_offset
, &val
);
9477 memcpy(pd
, &val
, b_count
);
9478 eeprom
->len
+= b_count
;
9483 static int tg3_nvram_write_block(struct tg3
*tp
, u32 offset
, u32 len
, u8
*buf
);
9485 static int tg3_set_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
, u8
*data
)
9487 struct tg3
*tp
= netdev_priv(dev
);
9489 u32 offset
, len
, b_offset
, odd_len
;
9493 if (tp
->link_config
.phy_is_low_power
)
9496 if ((tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) ||
9497 eeprom
->magic
!= TG3_EEPROM_MAGIC
)
9500 offset
= eeprom
->offset
;
9503 if ((b_offset
= (offset
& 3))) {
9504 /* adjustments to start on required 4 byte boundary */
9505 ret
= tg3_nvram_read_be32(tp
, offset
-b_offset
, &start
);
9516 /* adjustments to end on required 4 byte boundary */
9518 len
= (len
+ 3) & ~3;
9519 ret
= tg3_nvram_read_be32(tp
, offset
+len
-4, &end
);
9525 if (b_offset
|| odd_len
) {
9526 buf
= kmalloc(len
, GFP_KERNEL
);
9530 memcpy(buf
, &start
, 4);
9532 memcpy(buf
+len
-4, &end
, 4);
9533 memcpy(buf
+ b_offset
, data
, eeprom
->len
);
9536 ret
= tg3_nvram_write_block(tp
, offset
, len
, buf
);
9544 static int tg3_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
9546 struct tg3
*tp
= netdev_priv(dev
);
9548 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
9549 struct phy_device
*phydev
;
9550 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
9552 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
9553 return phy_ethtool_gset(phydev
, cmd
);
9556 cmd
->supported
= (SUPPORTED_Autoneg
);
9558 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
))
9559 cmd
->supported
|= (SUPPORTED_1000baseT_Half
|
9560 SUPPORTED_1000baseT_Full
);
9562 if (!(tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
)) {
9563 cmd
->supported
|= (SUPPORTED_100baseT_Half
|
9564 SUPPORTED_100baseT_Full
|
9565 SUPPORTED_10baseT_Half
|
9566 SUPPORTED_10baseT_Full
|
9568 cmd
->port
= PORT_TP
;
9570 cmd
->supported
|= SUPPORTED_FIBRE
;
9571 cmd
->port
= PORT_FIBRE
;
9574 cmd
->advertising
= tp
->link_config
.advertising
;
9575 if (netif_running(dev
)) {
9576 cmd
->speed
= tp
->link_config
.active_speed
;
9577 cmd
->duplex
= tp
->link_config
.active_duplex
;
9579 cmd
->phy_address
= tp
->phy_addr
;
9580 cmd
->transceiver
= XCVR_INTERNAL
;
9581 cmd
->autoneg
= tp
->link_config
.autoneg
;
9587 static int tg3_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
9589 struct tg3
*tp
= netdev_priv(dev
);
9591 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
9592 struct phy_device
*phydev
;
9593 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
9595 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
9596 return phy_ethtool_sset(phydev
, cmd
);
9599 if (cmd
->autoneg
!= AUTONEG_ENABLE
&&
9600 cmd
->autoneg
!= AUTONEG_DISABLE
)
9603 if (cmd
->autoneg
== AUTONEG_DISABLE
&&
9604 cmd
->duplex
!= DUPLEX_FULL
&&
9605 cmd
->duplex
!= DUPLEX_HALF
)
9608 if (cmd
->autoneg
== AUTONEG_ENABLE
) {
9609 u32 mask
= ADVERTISED_Autoneg
|
9611 ADVERTISED_Asym_Pause
;
9613 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
))
9614 mask
|= ADVERTISED_1000baseT_Half
|
9615 ADVERTISED_1000baseT_Full
;
9617 if (!(tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
))
9618 mask
|= ADVERTISED_100baseT_Half
|
9619 ADVERTISED_100baseT_Full
|
9620 ADVERTISED_10baseT_Half
|
9621 ADVERTISED_10baseT_Full
|
9624 mask
|= ADVERTISED_FIBRE
;
9626 if (cmd
->advertising
& ~mask
)
9629 mask
&= (ADVERTISED_1000baseT_Half
|
9630 ADVERTISED_1000baseT_Full
|
9631 ADVERTISED_100baseT_Half
|
9632 ADVERTISED_100baseT_Full
|
9633 ADVERTISED_10baseT_Half
|
9634 ADVERTISED_10baseT_Full
);
9636 cmd
->advertising
&= mask
;
9638 if (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
) {
9639 if (cmd
->speed
!= SPEED_1000
)
9642 if (cmd
->duplex
!= DUPLEX_FULL
)
9645 if (cmd
->speed
!= SPEED_100
&&
9646 cmd
->speed
!= SPEED_10
)
9651 tg3_full_lock(tp
, 0);
9653 tp
->link_config
.autoneg
= cmd
->autoneg
;
9654 if (cmd
->autoneg
== AUTONEG_ENABLE
) {
9655 tp
->link_config
.advertising
= (cmd
->advertising
|
9656 ADVERTISED_Autoneg
);
9657 tp
->link_config
.speed
= SPEED_INVALID
;
9658 tp
->link_config
.duplex
= DUPLEX_INVALID
;
9660 tp
->link_config
.advertising
= 0;
9661 tp
->link_config
.speed
= cmd
->speed
;
9662 tp
->link_config
.duplex
= cmd
->duplex
;
9665 tp
->link_config
.orig_speed
= tp
->link_config
.speed
;
9666 tp
->link_config
.orig_duplex
= tp
->link_config
.duplex
;
9667 tp
->link_config
.orig_autoneg
= tp
->link_config
.autoneg
;
9669 if (netif_running(dev
))
9670 tg3_setup_phy(tp
, 1);
9672 tg3_full_unlock(tp
);
9677 static void tg3_get_drvinfo(struct net_device
*dev
, struct ethtool_drvinfo
*info
)
9679 struct tg3
*tp
= netdev_priv(dev
);
9681 strcpy(info
->driver
, DRV_MODULE_NAME
);
9682 strcpy(info
->version
, DRV_MODULE_VERSION
);
9683 strcpy(info
->fw_version
, tp
->fw_ver
);
9684 strcpy(info
->bus_info
, pci_name(tp
->pdev
));
9687 static void tg3_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
9689 struct tg3
*tp
= netdev_priv(dev
);
9691 if ((tp
->tg3_flags
& TG3_FLAG_WOL_CAP
) &&
9692 device_can_wakeup(&tp
->pdev
->dev
))
9693 wol
->supported
= WAKE_MAGIC
;
9697 if ((tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
) &&
9698 device_can_wakeup(&tp
->pdev
->dev
))
9699 wol
->wolopts
= WAKE_MAGIC
;
9700 memset(&wol
->sopass
, 0, sizeof(wol
->sopass
));
9703 static int tg3_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
9705 struct tg3
*tp
= netdev_priv(dev
);
9706 struct device
*dp
= &tp
->pdev
->dev
;
9708 if (wol
->wolopts
& ~WAKE_MAGIC
)
9710 if ((wol
->wolopts
& WAKE_MAGIC
) &&
9711 !((tp
->tg3_flags
& TG3_FLAG_WOL_CAP
) && device_can_wakeup(dp
)))
9714 spin_lock_bh(&tp
->lock
);
9715 if (wol
->wolopts
& WAKE_MAGIC
) {
9716 tp
->tg3_flags
|= TG3_FLAG_WOL_ENABLE
;
9717 device_set_wakeup_enable(dp
, true);
9719 tp
->tg3_flags
&= ~TG3_FLAG_WOL_ENABLE
;
9720 device_set_wakeup_enable(dp
, false);
9722 spin_unlock_bh(&tp
->lock
);
9727 static u32
tg3_get_msglevel(struct net_device
*dev
)
9729 struct tg3
*tp
= netdev_priv(dev
);
9730 return tp
->msg_enable
;
9733 static void tg3_set_msglevel(struct net_device
*dev
, u32 value
)
9735 struct tg3
*tp
= netdev_priv(dev
);
9736 tp
->msg_enable
= value
;
9739 static int tg3_set_tso(struct net_device
*dev
, u32 value
)
9741 struct tg3
*tp
= netdev_priv(dev
);
9743 if (!(tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
)) {
9748 if ((dev
->features
& NETIF_F_IPV6_CSUM
) &&
9749 ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO_2
) ||
9750 (tp
->tg3_flags2
& TG3_FLG2_HW_TSO_3
))) {
9752 dev
->features
|= NETIF_F_TSO6
;
9753 if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO_3
) ||
9754 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
9755 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
9756 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
) ||
9757 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
9758 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
9759 dev
->features
|= NETIF_F_TSO_ECN
;
9761 dev
->features
&= ~(NETIF_F_TSO6
| NETIF_F_TSO_ECN
);
9763 return ethtool_op_set_tso(dev
, value
);
9766 static int tg3_nway_reset(struct net_device
*dev
)
9768 struct tg3
*tp
= netdev_priv(dev
);
9771 if (!netif_running(dev
))
9774 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)
9777 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
9778 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
9780 r
= phy_start_aneg(tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
]);
9784 spin_lock_bh(&tp
->lock
);
9786 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
9787 if (!tg3_readphy(tp
, MII_BMCR
, &bmcr
) &&
9788 ((bmcr
& BMCR_ANENABLE
) ||
9789 (tp
->tg3_flags2
& TG3_FLG2_PARALLEL_DETECT
))) {
9790 tg3_writephy(tp
, MII_BMCR
, bmcr
| BMCR_ANRESTART
|
9794 spin_unlock_bh(&tp
->lock
);
9800 static void tg3_get_ringparam(struct net_device
*dev
, struct ethtool_ringparam
*ering
)
9802 struct tg3
*tp
= netdev_priv(dev
);
9804 ering
->rx_max_pending
= TG3_RX_RING_SIZE
- 1;
9805 ering
->rx_mini_max_pending
= 0;
9806 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
)
9807 ering
->rx_jumbo_max_pending
= TG3_RX_JUMBO_RING_SIZE
- 1;
9809 ering
->rx_jumbo_max_pending
= 0;
9811 ering
->tx_max_pending
= TG3_TX_RING_SIZE
- 1;
9813 ering
->rx_pending
= tp
->rx_pending
;
9814 ering
->rx_mini_pending
= 0;
9815 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
)
9816 ering
->rx_jumbo_pending
= tp
->rx_jumbo_pending
;
9818 ering
->rx_jumbo_pending
= 0;
9820 ering
->tx_pending
= tp
->napi
[0].tx_pending
;
9823 static int tg3_set_ringparam(struct net_device
*dev
, struct ethtool_ringparam
*ering
)
9825 struct tg3
*tp
= netdev_priv(dev
);
9826 int i
, irq_sync
= 0, err
= 0;
9828 if ((ering
->rx_pending
> TG3_RX_RING_SIZE
- 1) ||
9829 (ering
->rx_jumbo_pending
> TG3_RX_JUMBO_RING_SIZE
- 1) ||
9830 (ering
->tx_pending
> TG3_TX_RING_SIZE
- 1) ||
9831 (ering
->tx_pending
<= MAX_SKB_FRAGS
) ||
9832 ((tp
->tg3_flags2
& TG3_FLG2_TSO_BUG
) &&
9833 (ering
->tx_pending
<= (MAX_SKB_FRAGS
* 3))))
9836 if (netif_running(dev
)) {
9842 tg3_full_lock(tp
, irq_sync
);
9844 tp
->rx_pending
= ering
->rx_pending
;
9846 if ((tp
->tg3_flags2
& TG3_FLG2_MAX_RXPEND_64
) &&
9847 tp
->rx_pending
> 63)
9848 tp
->rx_pending
= 63;
9849 tp
->rx_jumbo_pending
= ering
->rx_jumbo_pending
;
9851 for (i
= 0; i
< TG3_IRQ_MAX_VECS
; i
++)
9852 tp
->napi
[i
].tx_pending
= ering
->tx_pending
;
9854 if (netif_running(dev
)) {
9855 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
9856 err
= tg3_restart_hw(tp
, 1);
9858 tg3_netif_start(tp
);
9861 tg3_full_unlock(tp
);
9863 if (irq_sync
&& !err
)
9869 static void tg3_get_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
*epause
)
9871 struct tg3
*tp
= netdev_priv(dev
);
9873 epause
->autoneg
= (tp
->tg3_flags
& TG3_FLAG_PAUSE_AUTONEG
) != 0;
9875 if (tp
->link_config
.active_flowctrl
& FLOW_CTRL_RX
)
9876 epause
->rx_pause
= 1;
9878 epause
->rx_pause
= 0;
9880 if (tp
->link_config
.active_flowctrl
& FLOW_CTRL_TX
)
9881 epause
->tx_pause
= 1;
9883 epause
->tx_pause
= 0;
9886 static int tg3_set_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
*epause
)
9888 struct tg3
*tp
= netdev_priv(dev
);
9891 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
9893 struct phy_device
*phydev
;
9895 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
9897 if (!(phydev
->supported
& SUPPORTED_Pause
) ||
9898 (!(phydev
->supported
& SUPPORTED_Asym_Pause
) &&
9899 ((epause
->rx_pause
&& !epause
->tx_pause
) ||
9900 (!epause
->rx_pause
&& epause
->tx_pause
))))
9903 tp
->link_config
.flowctrl
= 0;
9904 if (epause
->rx_pause
) {
9905 tp
->link_config
.flowctrl
|= FLOW_CTRL_RX
;
9907 if (epause
->tx_pause
) {
9908 tp
->link_config
.flowctrl
|= FLOW_CTRL_TX
;
9909 newadv
= ADVERTISED_Pause
;
9911 newadv
= ADVERTISED_Pause
|
9912 ADVERTISED_Asym_Pause
;
9913 } else if (epause
->tx_pause
) {
9914 tp
->link_config
.flowctrl
|= FLOW_CTRL_TX
;
9915 newadv
= ADVERTISED_Asym_Pause
;
9919 if (epause
->autoneg
)
9920 tp
->tg3_flags
|= TG3_FLAG_PAUSE_AUTONEG
;
9922 tp
->tg3_flags
&= ~TG3_FLAG_PAUSE_AUTONEG
;
9924 if (tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
) {
9925 u32 oldadv
= phydev
->advertising
&
9926 (ADVERTISED_Pause
| ADVERTISED_Asym_Pause
);
9927 if (oldadv
!= newadv
) {
9928 phydev
->advertising
&=
9929 ~(ADVERTISED_Pause
|
9930 ADVERTISED_Asym_Pause
);
9931 phydev
->advertising
|= newadv
;
9932 if (phydev
->autoneg
) {
9934 * Always renegotiate the link to
9935 * inform our link partner of our
9936 * flow control settings, even if the
9937 * flow control is forced. Let
9938 * tg3_adjust_link() do the final
9939 * flow control setup.
9941 return phy_start_aneg(phydev
);
9945 if (!epause
->autoneg
)
9946 tg3_setup_flow_control(tp
, 0, 0);
9948 tp
->link_config
.orig_advertising
&=
9949 ~(ADVERTISED_Pause
|
9950 ADVERTISED_Asym_Pause
);
9951 tp
->link_config
.orig_advertising
|= newadv
;
9956 if (netif_running(dev
)) {
9961 tg3_full_lock(tp
, irq_sync
);
9963 if (epause
->autoneg
)
9964 tp
->tg3_flags
|= TG3_FLAG_PAUSE_AUTONEG
;
9966 tp
->tg3_flags
&= ~TG3_FLAG_PAUSE_AUTONEG
;
9967 if (epause
->rx_pause
)
9968 tp
->link_config
.flowctrl
|= FLOW_CTRL_RX
;
9970 tp
->link_config
.flowctrl
&= ~FLOW_CTRL_RX
;
9971 if (epause
->tx_pause
)
9972 tp
->link_config
.flowctrl
|= FLOW_CTRL_TX
;
9974 tp
->link_config
.flowctrl
&= ~FLOW_CTRL_TX
;
9976 if (netif_running(dev
)) {
9977 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
9978 err
= tg3_restart_hw(tp
, 1);
9980 tg3_netif_start(tp
);
9983 tg3_full_unlock(tp
);
9989 static u32
tg3_get_rx_csum(struct net_device
*dev
)
9991 struct tg3
*tp
= netdev_priv(dev
);
9992 return (tp
->tg3_flags
& TG3_FLAG_RX_CHECKSUMS
) != 0;
9995 static int tg3_set_rx_csum(struct net_device
*dev
, u32 data
)
9997 struct tg3
*tp
= netdev_priv(dev
);
9999 if (tp
->tg3_flags
& TG3_FLAG_BROKEN_CHECKSUMS
) {
10005 spin_lock_bh(&tp
->lock
);
10007 tp
->tg3_flags
|= TG3_FLAG_RX_CHECKSUMS
;
10009 tp
->tg3_flags
&= ~TG3_FLAG_RX_CHECKSUMS
;
10010 spin_unlock_bh(&tp
->lock
);
10015 static int tg3_set_tx_csum(struct net_device
*dev
, u32 data
)
10017 struct tg3
*tp
= netdev_priv(dev
);
10019 if (tp
->tg3_flags
& TG3_FLAG_BROKEN_CHECKSUMS
) {
10025 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
10026 ethtool_op_set_tx_ipv6_csum(dev
, data
);
10028 ethtool_op_set_tx_csum(dev
, data
);
10033 static int tg3_get_sset_count(struct net_device
*dev
, int sset
)
10037 return TG3_NUM_TEST
;
10039 return TG3_NUM_STATS
;
10041 return -EOPNOTSUPP
;
10045 static void tg3_get_strings(struct net_device
*dev
, u32 stringset
, u8
*buf
)
10047 switch (stringset
) {
10049 memcpy(buf
, ðtool_stats_keys
, sizeof(ethtool_stats_keys
));
10052 memcpy(buf
, ðtool_test_keys
, sizeof(ethtool_test_keys
));
10055 WARN_ON(1); /* we need a WARN() */
10060 static int tg3_phys_id(struct net_device
*dev
, u32 data
)
10062 struct tg3
*tp
= netdev_priv(dev
);
10065 if (!netif_running(tp
->dev
))
10069 data
= UINT_MAX
/ 2;
10071 for (i
= 0; i
< (data
* 2); i
++) {
10073 tw32(MAC_LED_CTRL
, LED_CTRL_LNKLED_OVERRIDE
|
10074 LED_CTRL_1000MBPS_ON
|
10075 LED_CTRL_100MBPS_ON
|
10076 LED_CTRL_10MBPS_ON
|
10077 LED_CTRL_TRAFFIC_OVERRIDE
|
10078 LED_CTRL_TRAFFIC_BLINK
|
10079 LED_CTRL_TRAFFIC_LED
);
10082 tw32(MAC_LED_CTRL
, LED_CTRL_LNKLED_OVERRIDE
|
10083 LED_CTRL_TRAFFIC_OVERRIDE
);
10085 if (msleep_interruptible(500))
10088 tw32(MAC_LED_CTRL
, tp
->led_ctrl
);
10092 static void tg3_get_ethtool_stats(struct net_device
*dev
,
10093 struct ethtool_stats
*estats
, u64
*tmp_stats
)
10095 struct tg3
*tp
= netdev_priv(dev
);
10096 memcpy(tmp_stats
, tg3_get_estats(tp
), sizeof(tp
->estats
));
10099 #define NVRAM_TEST_SIZE 0x100
10100 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
10101 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
10102 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
10103 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10104 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10106 static int tg3_test_nvram(struct tg3
*tp
)
10110 int i
, j
, k
, err
= 0, size
;
10112 if (tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
)
10115 if (tg3_nvram_read(tp
, 0, &magic
) != 0)
10118 if (magic
== TG3_EEPROM_MAGIC
)
10119 size
= NVRAM_TEST_SIZE
;
10120 else if ((magic
& TG3_EEPROM_MAGIC_FW_MSK
) == TG3_EEPROM_MAGIC_FW
) {
10121 if ((magic
& TG3_EEPROM_SB_FORMAT_MASK
) ==
10122 TG3_EEPROM_SB_FORMAT_1
) {
10123 switch (magic
& TG3_EEPROM_SB_REVISION_MASK
) {
10124 case TG3_EEPROM_SB_REVISION_0
:
10125 size
= NVRAM_SELFBOOT_FORMAT1_0_SIZE
;
10127 case TG3_EEPROM_SB_REVISION_2
:
10128 size
= NVRAM_SELFBOOT_FORMAT1_2_SIZE
;
10130 case TG3_EEPROM_SB_REVISION_3
:
10131 size
= NVRAM_SELFBOOT_FORMAT1_3_SIZE
;
10138 } else if ((magic
& TG3_EEPROM_MAGIC_HW_MSK
) == TG3_EEPROM_MAGIC_HW
)
10139 size
= NVRAM_SELFBOOT_HW_SIZE
;
10143 buf
= kmalloc(size
, GFP_KERNEL
);
10148 for (i
= 0, j
= 0; i
< size
; i
+= 4, j
++) {
10149 err
= tg3_nvram_read_be32(tp
, i
, &buf
[j
]);
10156 /* Selfboot format */
10157 magic
= be32_to_cpu(buf
[0]);
10158 if ((magic
& TG3_EEPROM_MAGIC_FW_MSK
) ==
10159 TG3_EEPROM_MAGIC_FW
) {
10160 u8
*buf8
= (u8
*) buf
, csum8
= 0;
10162 if ((magic
& TG3_EEPROM_SB_REVISION_MASK
) ==
10163 TG3_EEPROM_SB_REVISION_2
) {
10164 /* For rev 2, the csum doesn't include the MBA. */
10165 for (i
= 0; i
< TG3_EEPROM_SB_F1R2_MBA_OFF
; i
++)
10167 for (i
= TG3_EEPROM_SB_F1R2_MBA_OFF
+ 4; i
< size
; i
++)
10170 for (i
= 0; i
< size
; i
++)
10183 if ((magic
& TG3_EEPROM_MAGIC_HW_MSK
) ==
10184 TG3_EEPROM_MAGIC_HW
) {
10185 u8 data
[NVRAM_SELFBOOT_DATA_SIZE
];
10186 u8 parity
[NVRAM_SELFBOOT_DATA_SIZE
];
10187 u8
*buf8
= (u8
*) buf
;
10189 /* Separate the parity bits and the data bytes. */
10190 for (i
= 0, j
= 0, k
= 0; i
< NVRAM_SELFBOOT_HW_SIZE
; i
++) {
10191 if ((i
== 0) || (i
== 8)) {
10195 for (l
= 0, msk
= 0x80; l
< 7; l
++, msk
>>= 1)
10196 parity
[k
++] = buf8
[i
] & msk
;
10198 } else if (i
== 16) {
10202 for (l
= 0, msk
= 0x20; l
< 6; l
++, msk
>>= 1)
10203 parity
[k
++] = buf8
[i
] & msk
;
10206 for (l
= 0, msk
= 0x80; l
< 8; l
++, msk
>>= 1)
10207 parity
[k
++] = buf8
[i
] & msk
;
10210 data
[j
++] = buf8
[i
];
10214 for (i
= 0; i
< NVRAM_SELFBOOT_DATA_SIZE
; i
++) {
10215 u8 hw8
= hweight8(data
[i
]);
10217 if ((hw8
& 0x1) && parity
[i
])
10219 else if (!(hw8
& 0x1) && !parity
[i
])
10226 /* Bootstrap checksum at offset 0x10 */
10227 csum
= calc_crc((unsigned char *) buf
, 0x10);
10228 if (csum
!= be32_to_cpu(buf
[0x10/4]))
10231 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10232 csum
= calc_crc((unsigned char *) &buf
[0x74/4], 0x88);
10233 if (csum
!= be32_to_cpu(buf
[0xfc/4]))
10243 #define TG3_SERDES_TIMEOUT_SEC 2
10244 #define TG3_COPPER_TIMEOUT_SEC 6
10246 static int tg3_test_link(struct tg3
*tp
)
10250 if (!netif_running(tp
->dev
))
10253 if (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
)
10254 max
= TG3_SERDES_TIMEOUT_SEC
;
10256 max
= TG3_COPPER_TIMEOUT_SEC
;
10258 for (i
= 0; i
< max
; i
++) {
10259 if (netif_carrier_ok(tp
->dev
))
10262 if (msleep_interruptible(1000))
10269 /* Only test the commonly used registers */
10270 static int tg3_test_registers(struct tg3
*tp
)
10272 int i
, is_5705
, is_5750
;
10273 u32 offset
, read_mask
, write_mask
, val
, save_val
, read_val
;
10277 #define TG3_FL_5705 0x1
10278 #define TG3_FL_NOT_5705 0x2
10279 #define TG3_FL_NOT_5788 0x4
10280 #define TG3_FL_NOT_5750 0x8
10284 /* MAC Control Registers */
10285 { MAC_MODE
, TG3_FL_NOT_5705
,
10286 0x00000000, 0x00ef6f8c },
10287 { MAC_MODE
, TG3_FL_5705
,
10288 0x00000000, 0x01ef6b8c },
10289 { MAC_STATUS
, TG3_FL_NOT_5705
,
10290 0x03800107, 0x00000000 },
10291 { MAC_STATUS
, TG3_FL_5705
,
10292 0x03800100, 0x00000000 },
10293 { MAC_ADDR_0_HIGH
, 0x0000,
10294 0x00000000, 0x0000ffff },
10295 { MAC_ADDR_0_LOW
, 0x0000,
10296 0x00000000, 0xffffffff },
10297 { MAC_RX_MTU_SIZE
, 0x0000,
10298 0x00000000, 0x0000ffff },
10299 { MAC_TX_MODE
, 0x0000,
10300 0x00000000, 0x00000070 },
10301 { MAC_TX_LENGTHS
, 0x0000,
10302 0x00000000, 0x00003fff },
10303 { MAC_RX_MODE
, TG3_FL_NOT_5705
,
10304 0x00000000, 0x000007fc },
10305 { MAC_RX_MODE
, TG3_FL_5705
,
10306 0x00000000, 0x000007dc },
10307 { MAC_HASH_REG_0
, 0x0000,
10308 0x00000000, 0xffffffff },
10309 { MAC_HASH_REG_1
, 0x0000,
10310 0x00000000, 0xffffffff },
10311 { MAC_HASH_REG_2
, 0x0000,
10312 0x00000000, 0xffffffff },
10313 { MAC_HASH_REG_3
, 0x0000,
10314 0x00000000, 0xffffffff },
10316 /* Receive Data and Receive BD Initiator Control Registers. */
10317 { RCVDBDI_JUMBO_BD
+0, TG3_FL_NOT_5705
,
10318 0x00000000, 0xffffffff },
10319 { RCVDBDI_JUMBO_BD
+4, TG3_FL_NOT_5705
,
10320 0x00000000, 0xffffffff },
10321 { RCVDBDI_JUMBO_BD
+8, TG3_FL_NOT_5705
,
10322 0x00000000, 0x00000003 },
10323 { RCVDBDI_JUMBO_BD
+0xc, TG3_FL_NOT_5705
,
10324 0x00000000, 0xffffffff },
10325 { RCVDBDI_STD_BD
+0, 0x0000,
10326 0x00000000, 0xffffffff },
10327 { RCVDBDI_STD_BD
+4, 0x0000,
10328 0x00000000, 0xffffffff },
10329 { RCVDBDI_STD_BD
+8, 0x0000,
10330 0x00000000, 0xffff0002 },
10331 { RCVDBDI_STD_BD
+0xc, 0x0000,
10332 0x00000000, 0xffffffff },
10334 /* Receive BD Initiator Control Registers. */
10335 { RCVBDI_STD_THRESH
, TG3_FL_NOT_5705
,
10336 0x00000000, 0xffffffff },
10337 { RCVBDI_STD_THRESH
, TG3_FL_5705
,
10338 0x00000000, 0x000003ff },
10339 { RCVBDI_JUMBO_THRESH
, TG3_FL_NOT_5705
,
10340 0x00000000, 0xffffffff },
10342 /* Host Coalescing Control Registers. */
10343 { HOSTCC_MODE
, TG3_FL_NOT_5705
,
10344 0x00000000, 0x00000004 },
10345 { HOSTCC_MODE
, TG3_FL_5705
,
10346 0x00000000, 0x000000f6 },
10347 { HOSTCC_RXCOL_TICKS
, TG3_FL_NOT_5705
,
10348 0x00000000, 0xffffffff },
10349 { HOSTCC_RXCOL_TICKS
, TG3_FL_5705
,
10350 0x00000000, 0x000003ff },
10351 { HOSTCC_TXCOL_TICKS
, TG3_FL_NOT_5705
,
10352 0x00000000, 0xffffffff },
10353 { HOSTCC_TXCOL_TICKS
, TG3_FL_5705
,
10354 0x00000000, 0x000003ff },
10355 { HOSTCC_RXMAX_FRAMES
, TG3_FL_NOT_5705
,
10356 0x00000000, 0xffffffff },
10357 { HOSTCC_RXMAX_FRAMES
, TG3_FL_5705
| TG3_FL_NOT_5788
,
10358 0x00000000, 0x000000ff },
10359 { HOSTCC_TXMAX_FRAMES
, TG3_FL_NOT_5705
,
10360 0x00000000, 0xffffffff },
10361 { HOSTCC_TXMAX_FRAMES
, TG3_FL_5705
| TG3_FL_NOT_5788
,
10362 0x00000000, 0x000000ff },
10363 { HOSTCC_RXCOAL_TICK_INT
, TG3_FL_NOT_5705
,
10364 0x00000000, 0xffffffff },
10365 { HOSTCC_TXCOAL_TICK_INT
, TG3_FL_NOT_5705
,
10366 0x00000000, 0xffffffff },
10367 { HOSTCC_RXCOAL_MAXF_INT
, TG3_FL_NOT_5705
,
10368 0x00000000, 0xffffffff },
10369 { HOSTCC_RXCOAL_MAXF_INT
, TG3_FL_5705
| TG3_FL_NOT_5788
,
10370 0x00000000, 0x000000ff },
10371 { HOSTCC_TXCOAL_MAXF_INT
, TG3_FL_NOT_5705
,
10372 0x00000000, 0xffffffff },
10373 { HOSTCC_TXCOAL_MAXF_INT
, TG3_FL_5705
| TG3_FL_NOT_5788
,
10374 0x00000000, 0x000000ff },
10375 { HOSTCC_STAT_COAL_TICKS
, TG3_FL_NOT_5705
,
10376 0x00000000, 0xffffffff },
10377 { HOSTCC_STATS_BLK_HOST_ADDR
, TG3_FL_NOT_5705
,
10378 0x00000000, 0xffffffff },
10379 { HOSTCC_STATS_BLK_HOST_ADDR
+4, TG3_FL_NOT_5705
,
10380 0x00000000, 0xffffffff },
10381 { HOSTCC_STATUS_BLK_HOST_ADDR
, 0x0000,
10382 0x00000000, 0xffffffff },
10383 { HOSTCC_STATUS_BLK_HOST_ADDR
+4, 0x0000,
10384 0x00000000, 0xffffffff },
10385 { HOSTCC_STATS_BLK_NIC_ADDR
, 0x0000,
10386 0xffffffff, 0x00000000 },
10387 { HOSTCC_STATUS_BLK_NIC_ADDR
, 0x0000,
10388 0xffffffff, 0x00000000 },
10390 /* Buffer Manager Control Registers. */
10391 { BUFMGR_MB_POOL_ADDR
, TG3_FL_NOT_5750
,
10392 0x00000000, 0x007fff80 },
10393 { BUFMGR_MB_POOL_SIZE
, TG3_FL_NOT_5750
,
10394 0x00000000, 0x007fffff },
10395 { BUFMGR_MB_RDMA_LOW_WATER
, 0x0000,
10396 0x00000000, 0x0000003f },
10397 { BUFMGR_MB_MACRX_LOW_WATER
, 0x0000,
10398 0x00000000, 0x000001ff },
10399 { BUFMGR_MB_HIGH_WATER
, 0x0000,
10400 0x00000000, 0x000001ff },
10401 { BUFMGR_DMA_DESC_POOL_ADDR
, TG3_FL_NOT_5705
,
10402 0xffffffff, 0x00000000 },
10403 { BUFMGR_DMA_DESC_POOL_SIZE
, TG3_FL_NOT_5705
,
10404 0xffffffff, 0x00000000 },
10406 /* Mailbox Registers */
10407 { GRCMBOX_RCVSTD_PROD_IDX
+4, 0x0000,
10408 0x00000000, 0x000001ff },
10409 { GRCMBOX_RCVJUMBO_PROD_IDX
+4, TG3_FL_NOT_5705
,
10410 0x00000000, 0x000001ff },
10411 { GRCMBOX_RCVRET_CON_IDX_0
+4, 0x0000,
10412 0x00000000, 0x000007ff },
10413 { GRCMBOX_SNDHOST_PROD_IDX_0
+4, 0x0000,
10414 0x00000000, 0x000001ff },
10416 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10419 is_5705
= is_5750
= 0;
10420 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
10422 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
10426 for (i
= 0; reg_tbl
[i
].offset
!= 0xffff; i
++) {
10427 if (is_5705
&& (reg_tbl
[i
].flags
& TG3_FL_NOT_5705
))
10430 if (!is_5705
&& (reg_tbl
[i
].flags
& TG3_FL_5705
))
10433 if ((tp
->tg3_flags2
& TG3_FLG2_IS_5788
) &&
10434 (reg_tbl
[i
].flags
& TG3_FL_NOT_5788
))
10437 if (is_5750
&& (reg_tbl
[i
].flags
& TG3_FL_NOT_5750
))
10440 offset
= (u32
) reg_tbl
[i
].offset
;
10441 read_mask
= reg_tbl
[i
].read_mask
;
10442 write_mask
= reg_tbl
[i
].write_mask
;
10444 /* Save the original register content */
10445 save_val
= tr32(offset
);
10447 /* Determine the read-only value. */
10448 read_val
= save_val
& read_mask
;
10450 /* Write zero to the register, then make sure the read-only bits
10451 * are not changed and the read/write bits are all zeros.
10455 val
= tr32(offset
);
10457 /* Test the read-only and read/write bits. */
10458 if (((val
& read_mask
) != read_val
) || (val
& write_mask
))
10461 /* Write ones to all the bits defined by RdMask and WrMask, then
10462 * make sure the read-only bits are not changed and the
10463 * read/write bits are all ones.
10465 tw32(offset
, read_mask
| write_mask
);
10467 val
= tr32(offset
);
10469 /* Test the read-only bits. */
10470 if ((val
& read_mask
) != read_val
)
10473 /* Test the read/write bits. */
10474 if ((val
& write_mask
) != write_mask
)
10477 tw32(offset
, save_val
);
10483 if (netif_msg_hw(tp
))
10484 netdev_err(tp
->dev
,
10485 "Register test failed at offset %x\n", offset
);
10486 tw32(offset
, save_val
);
10490 static int tg3_do_mem_test(struct tg3
*tp
, u32 offset
, u32 len
)
10492 static const u32 test_pattern
[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10496 for (i
= 0; i
< ARRAY_SIZE(test_pattern
); i
++) {
10497 for (j
= 0; j
< len
; j
+= 4) {
10500 tg3_write_mem(tp
, offset
+ j
, test_pattern
[i
]);
10501 tg3_read_mem(tp
, offset
+ j
, &val
);
10502 if (val
!= test_pattern
[i
])
10509 static int tg3_test_memory(struct tg3
*tp
)
10511 static struct mem_entry
{
10514 } mem_tbl_570x
[] = {
10515 { 0x00000000, 0x00b50},
10516 { 0x00002000, 0x1c000},
10517 { 0xffffffff, 0x00000}
10518 }, mem_tbl_5705
[] = {
10519 { 0x00000100, 0x0000c},
10520 { 0x00000200, 0x00008},
10521 { 0x00004000, 0x00800},
10522 { 0x00006000, 0x01000},
10523 { 0x00008000, 0x02000},
10524 { 0x00010000, 0x0e000},
10525 { 0xffffffff, 0x00000}
10526 }, mem_tbl_5755
[] = {
10527 { 0x00000200, 0x00008},
10528 { 0x00004000, 0x00800},
10529 { 0x00006000, 0x00800},
10530 { 0x00008000, 0x02000},
10531 { 0x00010000, 0x0c000},
10532 { 0xffffffff, 0x00000}
10533 }, mem_tbl_5906
[] = {
10534 { 0x00000200, 0x00008},
10535 { 0x00004000, 0x00400},
10536 { 0x00006000, 0x00400},
10537 { 0x00008000, 0x01000},
10538 { 0x00010000, 0x01000},
10539 { 0xffffffff, 0x00000}
10540 }, mem_tbl_5717
[] = {
10541 { 0x00000200, 0x00008},
10542 { 0x00010000, 0x0a000},
10543 { 0x00020000, 0x13c00},
10544 { 0xffffffff, 0x00000}
10545 }, mem_tbl_57765
[] = {
10546 { 0x00000200, 0x00008},
10547 { 0x00004000, 0x00800},
10548 { 0x00006000, 0x09800},
10549 { 0x00010000, 0x0a000},
10550 { 0xffffffff, 0x00000}
10552 struct mem_entry
*mem_tbl
;
10556 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
)
10557 mem_tbl
= mem_tbl_5717
;
10558 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
10559 mem_tbl
= mem_tbl_57765
;
10560 else if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
10561 mem_tbl
= mem_tbl_5755
;
10562 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
10563 mem_tbl
= mem_tbl_5906
;
10564 else if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
10565 mem_tbl
= mem_tbl_5705
;
10567 mem_tbl
= mem_tbl_570x
;
10569 for (i
= 0; mem_tbl
[i
].offset
!= 0xffffffff; i
++) {
10570 if ((err
= tg3_do_mem_test(tp
, mem_tbl
[i
].offset
,
10571 mem_tbl
[i
].len
)) != 0)
10578 #define TG3_MAC_LOOPBACK 0
10579 #define TG3_PHY_LOOPBACK 1
10581 static int tg3_run_loopback(struct tg3
*tp
, int loopback_mode
)
10583 u32 mac_mode
, rx_start_idx
, rx_idx
, tx_idx
, opaque_key
;
10584 u32 desc_idx
, coal_now
;
10585 struct sk_buff
*skb
, *rx_skb
;
10588 int num_pkts
, tx_len
, rx_len
, i
, err
;
10589 struct tg3_rx_buffer_desc
*desc
;
10590 struct tg3_napi
*tnapi
, *rnapi
;
10591 struct tg3_rx_prodring_set
*tpr
= &tp
->prodring
[0];
10593 tnapi
= &tp
->napi
[0];
10594 rnapi
= &tp
->napi
[0];
10595 if (tp
->irq_cnt
> 1) {
10596 rnapi
= &tp
->napi
[1];
10597 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)
10598 tnapi
= &tp
->napi
[1];
10600 coal_now
= tnapi
->coal_now
| rnapi
->coal_now
;
10602 if (loopback_mode
== TG3_MAC_LOOPBACK
) {
10603 /* HW errata - mac loopback fails in some cases on 5780.
10604 * Normal traffic and PHY loopback are not affected by
10607 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5780
)
10610 mac_mode
= (tp
->mac_mode
& ~MAC_MODE_PORT_MODE_MASK
) |
10611 MAC_MODE_PORT_INT_LPBACK
;
10612 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
10613 mac_mode
|= MAC_MODE_LINK_POLARITY
;
10614 if (tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)
10615 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
10617 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
10618 tw32(MAC_MODE
, mac_mode
);
10619 } else if (loopback_mode
== TG3_PHY_LOOPBACK
) {
10622 if (tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
) {
10623 tg3_phy_fet_toggle_apd(tp
, false);
10624 val
= BMCR_LOOPBACK
| BMCR_FULLDPLX
| BMCR_SPEED100
;
10626 val
= BMCR_LOOPBACK
| BMCR_FULLDPLX
| BMCR_SPEED1000
;
10628 tg3_phy_toggle_automdix(tp
, 0);
10630 tg3_writephy(tp
, MII_BMCR
, val
);
10633 mac_mode
= tp
->mac_mode
& ~MAC_MODE_PORT_MODE_MASK
;
10634 if (tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
) {
10635 tg3_writephy(tp
, MII_TG3_FET_PTEST
,
10636 MII_TG3_FET_PTEST_FRC_TX_LINK
|
10637 MII_TG3_FET_PTEST_FRC_TX_LOCK
);
10638 /* The write needs to be flushed for the AC131 */
10639 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
10640 tg3_readphy(tp
, MII_TG3_FET_PTEST
, &val
);
10641 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
10643 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
10645 /* reset to prevent losing 1st rx packet intermittently */
10646 if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
) {
10647 tw32_f(MAC_RX_MODE
, RX_MODE_RESET
);
10649 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
10651 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) {
10652 u32 masked_phy_id
= tp
->phy_id
& TG3_PHY_ID_MASK
;
10653 if (masked_phy_id
== TG3_PHY_ID_BCM5401
)
10654 mac_mode
&= ~MAC_MODE_LINK_POLARITY
;
10655 else if (masked_phy_id
== TG3_PHY_ID_BCM5411
)
10656 mac_mode
|= MAC_MODE_LINK_POLARITY
;
10657 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
10658 MII_TG3_EXT_CTRL_LNK3_LED_MODE
);
10660 tw32(MAC_MODE
, mac_mode
);
10668 skb
= netdev_alloc_skb(tp
->dev
, tx_len
);
10672 tx_data
= skb_put(skb
, tx_len
);
10673 memcpy(tx_data
, tp
->dev
->dev_addr
, 6);
10674 memset(tx_data
+ 6, 0x0, 8);
10676 tw32(MAC_RX_MTU_SIZE
, tx_len
+ 4);
10678 for (i
= 14; i
< tx_len
; i
++)
10679 tx_data
[i
] = (u8
) (i
& 0xff);
10681 map
= pci_map_single(tp
->pdev
, skb
->data
, tx_len
, PCI_DMA_TODEVICE
);
10682 if (pci_dma_mapping_error(tp
->pdev
, map
)) {
10683 dev_kfree_skb(skb
);
10687 tw32_f(HOSTCC_MODE
, tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
|
10692 rx_start_idx
= rnapi
->hw_status
->idx
[0].rx_producer
;
10696 tg3_set_txd(tnapi
, tnapi
->tx_prod
, map
, tx_len
, 0, 1);
10701 tw32_tx_mbox(tnapi
->prodmbox
, tnapi
->tx_prod
);
10702 tr32_mailbox(tnapi
->prodmbox
);
10706 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
10707 for (i
= 0; i
< 35; i
++) {
10708 tw32_f(HOSTCC_MODE
, tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
|
10713 tx_idx
= tnapi
->hw_status
->idx
[0].tx_consumer
;
10714 rx_idx
= rnapi
->hw_status
->idx
[0].rx_producer
;
10715 if ((tx_idx
== tnapi
->tx_prod
) &&
10716 (rx_idx
== (rx_start_idx
+ num_pkts
)))
10720 pci_unmap_single(tp
->pdev
, map
, tx_len
, PCI_DMA_TODEVICE
);
10721 dev_kfree_skb(skb
);
10723 if (tx_idx
!= tnapi
->tx_prod
)
10726 if (rx_idx
!= rx_start_idx
+ num_pkts
)
10729 desc
= &rnapi
->rx_rcb
[rx_start_idx
];
10730 desc_idx
= desc
->opaque
& RXD_OPAQUE_INDEX_MASK
;
10731 opaque_key
= desc
->opaque
& RXD_OPAQUE_RING_MASK
;
10732 if (opaque_key
!= RXD_OPAQUE_RING_STD
)
10735 if ((desc
->err_vlan
& RXD_ERR_MASK
) != 0 &&
10736 (desc
->err_vlan
!= RXD_ERR_ODD_NIBBLE_RCVD_MII
))
10739 rx_len
= ((desc
->idx_len
& RXD_LEN_MASK
) >> RXD_LEN_SHIFT
) - 4;
10740 if (rx_len
!= tx_len
)
10743 rx_skb
= tpr
->rx_std_buffers
[desc_idx
].skb
;
10745 map
= pci_unmap_addr(&tpr
->rx_std_buffers
[desc_idx
], mapping
);
10746 pci_dma_sync_single_for_cpu(tp
->pdev
, map
, rx_len
, PCI_DMA_FROMDEVICE
);
10748 for (i
= 14; i
< tx_len
; i
++) {
10749 if (*(rx_skb
->data
+ i
) != (u8
) (i
& 0xff))
10754 /* tg3_free_rings will unmap and free the rx_skb */
10759 #define TG3_MAC_LOOPBACK_FAILED 1
10760 #define TG3_PHY_LOOPBACK_FAILED 2
10761 #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
10762 TG3_PHY_LOOPBACK_FAILED)
10764 static int tg3_test_loopback(struct tg3
*tp
)
10769 if (!netif_running(tp
->dev
))
10770 return TG3_LOOPBACK_FAILED
;
10772 err
= tg3_reset_hw(tp
, 1);
10774 return TG3_LOOPBACK_FAILED
;
10776 /* Turn off gphy autopowerdown. */
10777 if (tp
->tg3_flags3
& TG3_FLG3_PHY_ENABLE_APD
)
10778 tg3_phy_toggle_apd(tp
, false);
10780 if (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) {
10784 tw32(TG3_CPMU_MUTEX_REQ
, CPMU_MUTEX_REQ_DRIVER
);
10786 /* Wait for up to 40 microseconds to acquire lock. */
10787 for (i
= 0; i
< 4; i
++) {
10788 status
= tr32(TG3_CPMU_MUTEX_GNT
);
10789 if (status
== CPMU_MUTEX_GNT_DRIVER
)
10794 if (status
!= CPMU_MUTEX_GNT_DRIVER
)
10795 return TG3_LOOPBACK_FAILED
;
10797 /* Turn off link-based power management. */
10798 cpmuctrl
= tr32(TG3_CPMU_CTRL
);
10799 tw32(TG3_CPMU_CTRL
,
10800 cpmuctrl
& ~(CPMU_CTRL_LINK_SPEED_MODE
|
10801 CPMU_CTRL_LINK_AWARE_MODE
));
10804 if (tg3_run_loopback(tp
, TG3_MAC_LOOPBACK
))
10805 err
|= TG3_MAC_LOOPBACK_FAILED
;
10807 if (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) {
10808 tw32(TG3_CPMU_CTRL
, cpmuctrl
);
10810 /* Release the mutex */
10811 tw32(TG3_CPMU_MUTEX_GNT
, CPMU_MUTEX_GNT_DRIVER
);
10814 if (!(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) &&
10815 !(tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
)) {
10816 if (tg3_run_loopback(tp
, TG3_PHY_LOOPBACK
))
10817 err
|= TG3_PHY_LOOPBACK_FAILED
;
10820 /* Re-enable gphy autopowerdown. */
10821 if (tp
->tg3_flags3
& TG3_FLG3_PHY_ENABLE_APD
)
10822 tg3_phy_toggle_apd(tp
, true);
10827 static void tg3_self_test(struct net_device
*dev
, struct ethtool_test
*etest
,
10830 struct tg3
*tp
= netdev_priv(dev
);
10832 if (tp
->link_config
.phy_is_low_power
)
10833 tg3_set_power_state(tp
, PCI_D0
);
10835 memset(data
, 0, sizeof(u64
) * TG3_NUM_TEST
);
10837 if (tg3_test_nvram(tp
) != 0) {
10838 etest
->flags
|= ETH_TEST_FL_FAILED
;
10841 if (tg3_test_link(tp
) != 0) {
10842 etest
->flags
|= ETH_TEST_FL_FAILED
;
10845 if (etest
->flags
& ETH_TEST_FL_OFFLINE
) {
10846 int err
, err2
= 0, irq_sync
= 0;
10848 if (netif_running(dev
)) {
10850 tg3_netif_stop(tp
);
10854 tg3_full_lock(tp
, irq_sync
);
10856 tg3_halt(tp
, RESET_KIND_SUSPEND
, 1);
10857 err
= tg3_nvram_lock(tp
);
10858 tg3_halt_cpu(tp
, RX_CPU_BASE
);
10859 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
10860 tg3_halt_cpu(tp
, TX_CPU_BASE
);
10862 tg3_nvram_unlock(tp
);
10864 if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
)
10867 if (tg3_test_registers(tp
) != 0) {
10868 etest
->flags
|= ETH_TEST_FL_FAILED
;
10871 if (tg3_test_memory(tp
) != 0) {
10872 etest
->flags
|= ETH_TEST_FL_FAILED
;
10875 if ((data
[4] = tg3_test_loopback(tp
)) != 0)
10876 etest
->flags
|= ETH_TEST_FL_FAILED
;
10878 tg3_full_unlock(tp
);
10880 if (tg3_test_interrupt(tp
) != 0) {
10881 etest
->flags
|= ETH_TEST_FL_FAILED
;
10885 tg3_full_lock(tp
, 0);
10887 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
10888 if (netif_running(dev
)) {
10889 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
10890 err2
= tg3_restart_hw(tp
, 1);
10892 tg3_netif_start(tp
);
10895 tg3_full_unlock(tp
);
10897 if (irq_sync
&& !err2
)
10900 if (tp
->link_config
.phy_is_low_power
)
10901 tg3_set_power_state(tp
, PCI_D3hot
);
10905 static int tg3_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
10907 struct mii_ioctl_data
*data
= if_mii(ifr
);
10908 struct tg3
*tp
= netdev_priv(dev
);
10911 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
10912 struct phy_device
*phydev
;
10913 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
10915 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
10916 return phy_mii_ioctl(phydev
, data
, cmd
);
10921 data
->phy_id
= tp
->phy_addr
;
10924 case SIOCGMIIREG
: {
10927 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)
10928 break; /* We have no PHY */
10930 if (tp
->link_config
.phy_is_low_power
)
10933 spin_lock_bh(&tp
->lock
);
10934 err
= tg3_readphy(tp
, data
->reg_num
& 0x1f, &mii_regval
);
10935 spin_unlock_bh(&tp
->lock
);
10937 data
->val_out
= mii_regval
;
10943 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)
10944 break; /* We have no PHY */
10946 if (tp
->link_config
.phy_is_low_power
)
10949 spin_lock_bh(&tp
->lock
);
10950 err
= tg3_writephy(tp
, data
->reg_num
& 0x1f, data
->val_in
);
10951 spin_unlock_bh(&tp
->lock
);
10959 return -EOPNOTSUPP
;
10962 #if TG3_VLAN_TAG_USED
10963 static void tg3_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*grp
)
10965 struct tg3
*tp
= netdev_priv(dev
);
10967 if (!netif_running(dev
)) {
10972 tg3_netif_stop(tp
);
10974 tg3_full_lock(tp
, 0);
10978 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10979 __tg3_set_rx_mode(dev
);
10981 tg3_netif_start(tp
);
10983 tg3_full_unlock(tp
);
10987 static int tg3_get_coalesce(struct net_device
*dev
, struct ethtool_coalesce
*ec
)
10989 struct tg3
*tp
= netdev_priv(dev
);
10991 memcpy(ec
, &tp
->coal
, sizeof(*ec
));
10995 static int tg3_set_coalesce(struct net_device
*dev
, struct ethtool_coalesce
*ec
)
10997 struct tg3
*tp
= netdev_priv(dev
);
10998 u32 max_rxcoal_tick_int
= 0, max_txcoal_tick_int
= 0;
10999 u32 max_stat_coal_ticks
= 0, min_stat_coal_ticks
= 0;
11001 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
11002 max_rxcoal_tick_int
= MAX_RXCOAL_TICK_INT
;
11003 max_txcoal_tick_int
= MAX_TXCOAL_TICK_INT
;
11004 max_stat_coal_ticks
= MAX_STAT_COAL_TICKS
;
11005 min_stat_coal_ticks
= MIN_STAT_COAL_TICKS
;
11008 if ((ec
->rx_coalesce_usecs
> MAX_RXCOL_TICKS
) ||
11009 (ec
->tx_coalesce_usecs
> MAX_TXCOL_TICKS
) ||
11010 (ec
->rx_max_coalesced_frames
> MAX_RXMAX_FRAMES
) ||
11011 (ec
->tx_max_coalesced_frames
> MAX_TXMAX_FRAMES
) ||
11012 (ec
->rx_coalesce_usecs_irq
> max_rxcoal_tick_int
) ||
11013 (ec
->tx_coalesce_usecs_irq
> max_txcoal_tick_int
) ||
11014 (ec
->rx_max_coalesced_frames_irq
> MAX_RXCOAL_MAXF_INT
) ||
11015 (ec
->tx_max_coalesced_frames_irq
> MAX_TXCOAL_MAXF_INT
) ||
11016 (ec
->stats_block_coalesce_usecs
> max_stat_coal_ticks
) ||
11017 (ec
->stats_block_coalesce_usecs
< min_stat_coal_ticks
))
11020 /* No rx interrupts will be generated if both are zero */
11021 if ((ec
->rx_coalesce_usecs
== 0) &&
11022 (ec
->rx_max_coalesced_frames
== 0))
11025 /* No tx interrupts will be generated if both are zero */
11026 if ((ec
->tx_coalesce_usecs
== 0) &&
11027 (ec
->tx_max_coalesced_frames
== 0))
11030 /* Only copy relevant parameters, ignore all others. */
11031 tp
->coal
.rx_coalesce_usecs
= ec
->rx_coalesce_usecs
;
11032 tp
->coal
.tx_coalesce_usecs
= ec
->tx_coalesce_usecs
;
11033 tp
->coal
.rx_max_coalesced_frames
= ec
->rx_max_coalesced_frames
;
11034 tp
->coal
.tx_max_coalesced_frames
= ec
->tx_max_coalesced_frames
;
11035 tp
->coal
.rx_coalesce_usecs_irq
= ec
->rx_coalesce_usecs_irq
;
11036 tp
->coal
.tx_coalesce_usecs_irq
= ec
->tx_coalesce_usecs_irq
;
11037 tp
->coal
.rx_max_coalesced_frames_irq
= ec
->rx_max_coalesced_frames_irq
;
11038 tp
->coal
.tx_max_coalesced_frames_irq
= ec
->tx_max_coalesced_frames_irq
;
11039 tp
->coal
.stats_block_coalesce_usecs
= ec
->stats_block_coalesce_usecs
;
11041 if (netif_running(dev
)) {
11042 tg3_full_lock(tp
, 0);
11043 __tg3_set_coalesce(tp
, &tp
->coal
);
11044 tg3_full_unlock(tp
);
11049 static const struct ethtool_ops tg3_ethtool_ops
= {
11050 .get_settings
= tg3_get_settings
,
11051 .set_settings
= tg3_set_settings
,
11052 .get_drvinfo
= tg3_get_drvinfo
,
11053 .get_regs_len
= tg3_get_regs_len
,
11054 .get_regs
= tg3_get_regs
,
11055 .get_wol
= tg3_get_wol
,
11056 .set_wol
= tg3_set_wol
,
11057 .get_msglevel
= tg3_get_msglevel
,
11058 .set_msglevel
= tg3_set_msglevel
,
11059 .nway_reset
= tg3_nway_reset
,
11060 .get_link
= ethtool_op_get_link
,
11061 .get_eeprom_len
= tg3_get_eeprom_len
,
11062 .get_eeprom
= tg3_get_eeprom
,
11063 .set_eeprom
= tg3_set_eeprom
,
11064 .get_ringparam
= tg3_get_ringparam
,
11065 .set_ringparam
= tg3_set_ringparam
,
11066 .get_pauseparam
= tg3_get_pauseparam
,
11067 .set_pauseparam
= tg3_set_pauseparam
,
11068 .get_rx_csum
= tg3_get_rx_csum
,
11069 .set_rx_csum
= tg3_set_rx_csum
,
11070 .set_tx_csum
= tg3_set_tx_csum
,
11071 .set_sg
= ethtool_op_set_sg
,
11072 .set_tso
= tg3_set_tso
,
11073 .self_test
= tg3_self_test
,
11074 .get_strings
= tg3_get_strings
,
11075 .phys_id
= tg3_phys_id
,
11076 .get_ethtool_stats
= tg3_get_ethtool_stats
,
11077 .get_coalesce
= tg3_get_coalesce
,
11078 .set_coalesce
= tg3_set_coalesce
,
11079 .get_sset_count
= tg3_get_sset_count
,
11082 static void __devinit
tg3_get_eeprom_size(struct tg3
*tp
)
11084 u32 cursize
, val
, magic
;
11086 tp
->nvram_size
= EEPROM_CHIP_SIZE
;
11088 if (tg3_nvram_read(tp
, 0, &magic
) != 0)
11091 if ((magic
!= TG3_EEPROM_MAGIC
) &&
11092 ((magic
& TG3_EEPROM_MAGIC_FW_MSK
) != TG3_EEPROM_MAGIC_FW
) &&
11093 ((magic
& TG3_EEPROM_MAGIC_HW_MSK
) != TG3_EEPROM_MAGIC_HW
))
11097 * Size the chip by reading offsets at increasing powers of two.
11098 * When we encounter our validation signature, we know the addressing
11099 * has wrapped around, and thus have our chip size.
11103 while (cursize
< tp
->nvram_size
) {
11104 if (tg3_nvram_read(tp
, cursize
, &val
) != 0)
11113 tp
->nvram_size
= cursize
;
11116 static void __devinit
tg3_get_nvram_size(struct tg3
*tp
)
11120 if ((tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) ||
11121 tg3_nvram_read(tp
, 0, &val
) != 0)
11124 /* Selfboot format */
11125 if (val
!= TG3_EEPROM_MAGIC
) {
11126 tg3_get_eeprom_size(tp
);
11130 if (tg3_nvram_read(tp
, 0xf0, &val
) == 0) {
11132 /* This is confusing. We want to operate on the
11133 * 16-bit value at offset 0xf2. The tg3_nvram_read()
11134 * call will read from NVRAM and byteswap the data
11135 * according to the byteswapping settings for all
11136 * other register accesses. This ensures the data we
11137 * want will always reside in the lower 16-bits.
11138 * However, the data in NVRAM is in LE format, which
11139 * means the data from the NVRAM read will always be
11140 * opposite the endianness of the CPU. The 16-bit
11141 * byteswap then brings the data to CPU endianness.
11143 tp
->nvram_size
= swab16((u16
)(val
& 0x0000ffff)) * 1024;
11147 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
11150 static void __devinit
tg3_get_nvram_info(struct tg3
*tp
)
11154 nvcfg1
= tr32(NVRAM_CFG1
);
11155 if (nvcfg1
& NVRAM_CFG1_FLASHIF_ENAB
) {
11156 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11158 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
11159 tw32(NVRAM_CFG1
, nvcfg1
);
11162 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
) ||
11163 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
11164 switch (nvcfg1
& NVRAM_CFG1_VENDOR_MASK
) {
11165 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED
:
11166 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11167 tp
->nvram_pagesize
= ATMEL_AT45DB0X1B_PAGE_SIZE
;
11168 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11170 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED
:
11171 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11172 tp
->nvram_pagesize
= ATMEL_AT25F512_PAGE_SIZE
;
11174 case FLASH_VENDOR_ATMEL_EEPROM
:
11175 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11176 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
11177 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11179 case FLASH_VENDOR_ST
:
11180 tp
->nvram_jedecnum
= JEDEC_ST
;
11181 tp
->nvram_pagesize
= ST_M45PEX0_PAGE_SIZE
;
11182 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11184 case FLASH_VENDOR_SAIFUN
:
11185 tp
->nvram_jedecnum
= JEDEC_SAIFUN
;
11186 tp
->nvram_pagesize
= SAIFUN_SA25F0XX_PAGE_SIZE
;
11188 case FLASH_VENDOR_SST_SMALL
:
11189 case FLASH_VENDOR_SST_LARGE
:
11190 tp
->nvram_jedecnum
= JEDEC_SST
;
11191 tp
->nvram_pagesize
= SST_25VF0X0_PAGE_SIZE
;
11195 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11196 tp
->nvram_pagesize
= ATMEL_AT45DB0X1B_PAGE_SIZE
;
11197 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11201 static void __devinit
tg3_nvram_get_pagesize(struct tg3
*tp
, u32 nvmcfg1
)
11203 switch (nvmcfg1
& NVRAM_CFG1_5752PAGE_SIZE_MASK
) {
11204 case FLASH_5752PAGE_SIZE_256
:
11205 tp
->nvram_pagesize
= 256;
11207 case FLASH_5752PAGE_SIZE_512
:
11208 tp
->nvram_pagesize
= 512;
11210 case FLASH_5752PAGE_SIZE_1K
:
11211 tp
->nvram_pagesize
= 1024;
11213 case FLASH_5752PAGE_SIZE_2K
:
11214 tp
->nvram_pagesize
= 2048;
11216 case FLASH_5752PAGE_SIZE_4K
:
11217 tp
->nvram_pagesize
= 4096;
11219 case FLASH_5752PAGE_SIZE_264
:
11220 tp
->nvram_pagesize
= 264;
11222 case FLASH_5752PAGE_SIZE_528
:
11223 tp
->nvram_pagesize
= 528;
11228 static void __devinit
tg3_get_5752_nvram_info(struct tg3
*tp
)
11232 nvcfg1
= tr32(NVRAM_CFG1
);
11234 /* NVRAM protection for TPM */
11235 if (nvcfg1
& (1 << 27))
11236 tp
->tg3_flags3
|= TG3_FLG3_PROTECTED_NVRAM
;
11238 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11239 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ
:
11240 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ
:
11241 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11242 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11244 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
11245 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11246 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11247 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11249 case FLASH_5752VENDOR_ST_M45PE10
:
11250 case FLASH_5752VENDOR_ST_M45PE20
:
11251 case FLASH_5752VENDOR_ST_M45PE40
:
11252 tp
->nvram_jedecnum
= JEDEC_ST
;
11253 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11254 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11258 if (tp
->tg3_flags2
& TG3_FLG2_FLASH
) {
11259 tg3_nvram_get_pagesize(tp
, nvcfg1
);
11261 /* For eeprom, set pagesize to maximum eeprom size */
11262 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
11264 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
11265 tw32(NVRAM_CFG1
, nvcfg1
);
11269 static void __devinit
tg3_get_5755_nvram_info(struct tg3
*tp
)
11271 u32 nvcfg1
, protect
= 0;
11273 nvcfg1
= tr32(NVRAM_CFG1
);
11275 /* NVRAM protection for TPM */
11276 if (nvcfg1
& (1 << 27)) {
11277 tp
->tg3_flags3
|= TG3_FLG3_PROTECTED_NVRAM
;
11281 nvcfg1
&= NVRAM_CFG1_5752VENDOR_MASK
;
11283 case FLASH_5755VENDOR_ATMEL_FLASH_1
:
11284 case FLASH_5755VENDOR_ATMEL_FLASH_2
:
11285 case FLASH_5755VENDOR_ATMEL_FLASH_3
:
11286 case FLASH_5755VENDOR_ATMEL_FLASH_5
:
11287 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11288 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11289 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11290 tp
->nvram_pagesize
= 264;
11291 if (nvcfg1
== FLASH_5755VENDOR_ATMEL_FLASH_1
||
11292 nvcfg1
== FLASH_5755VENDOR_ATMEL_FLASH_5
)
11293 tp
->nvram_size
= (protect
? 0x3e200 :
11294 TG3_NVRAM_SIZE_512KB
);
11295 else if (nvcfg1
== FLASH_5755VENDOR_ATMEL_FLASH_2
)
11296 tp
->nvram_size
= (protect
? 0x1f200 :
11297 TG3_NVRAM_SIZE_256KB
);
11299 tp
->nvram_size
= (protect
? 0x1f200 :
11300 TG3_NVRAM_SIZE_128KB
);
11302 case FLASH_5752VENDOR_ST_M45PE10
:
11303 case FLASH_5752VENDOR_ST_M45PE20
:
11304 case FLASH_5752VENDOR_ST_M45PE40
:
11305 tp
->nvram_jedecnum
= JEDEC_ST
;
11306 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11307 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11308 tp
->nvram_pagesize
= 256;
11309 if (nvcfg1
== FLASH_5752VENDOR_ST_M45PE10
)
11310 tp
->nvram_size
= (protect
?
11311 TG3_NVRAM_SIZE_64KB
:
11312 TG3_NVRAM_SIZE_128KB
);
11313 else if (nvcfg1
== FLASH_5752VENDOR_ST_M45PE20
)
11314 tp
->nvram_size
= (protect
?
11315 TG3_NVRAM_SIZE_64KB
:
11316 TG3_NVRAM_SIZE_256KB
);
11318 tp
->nvram_size
= (protect
?
11319 TG3_NVRAM_SIZE_128KB
:
11320 TG3_NVRAM_SIZE_512KB
);
11325 static void __devinit
tg3_get_5787_nvram_info(struct tg3
*tp
)
11329 nvcfg1
= tr32(NVRAM_CFG1
);
11331 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11332 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ
:
11333 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ
:
11334 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ
:
11335 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ
:
11336 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11337 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11338 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
11340 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
11341 tw32(NVRAM_CFG1
, nvcfg1
);
11343 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
11344 case FLASH_5755VENDOR_ATMEL_FLASH_1
:
11345 case FLASH_5755VENDOR_ATMEL_FLASH_2
:
11346 case FLASH_5755VENDOR_ATMEL_FLASH_3
:
11347 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11348 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11349 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11350 tp
->nvram_pagesize
= 264;
11352 case FLASH_5752VENDOR_ST_M45PE10
:
11353 case FLASH_5752VENDOR_ST_M45PE20
:
11354 case FLASH_5752VENDOR_ST_M45PE40
:
11355 tp
->nvram_jedecnum
= JEDEC_ST
;
11356 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11357 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11358 tp
->nvram_pagesize
= 256;
11363 static void __devinit
tg3_get_5761_nvram_info(struct tg3
*tp
)
11365 u32 nvcfg1
, protect
= 0;
11367 nvcfg1
= tr32(NVRAM_CFG1
);
11369 /* NVRAM protection for TPM */
11370 if (nvcfg1
& (1 << 27)) {
11371 tp
->tg3_flags3
|= TG3_FLG3_PROTECTED_NVRAM
;
11375 nvcfg1
&= NVRAM_CFG1_5752VENDOR_MASK
;
11377 case FLASH_5761VENDOR_ATMEL_ADB021D
:
11378 case FLASH_5761VENDOR_ATMEL_ADB041D
:
11379 case FLASH_5761VENDOR_ATMEL_ADB081D
:
11380 case FLASH_5761VENDOR_ATMEL_ADB161D
:
11381 case FLASH_5761VENDOR_ATMEL_MDB021D
:
11382 case FLASH_5761VENDOR_ATMEL_MDB041D
:
11383 case FLASH_5761VENDOR_ATMEL_MDB081D
:
11384 case FLASH_5761VENDOR_ATMEL_MDB161D
:
11385 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11386 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11387 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11388 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
11389 tp
->nvram_pagesize
= 256;
11391 case FLASH_5761VENDOR_ST_A_M45PE20
:
11392 case FLASH_5761VENDOR_ST_A_M45PE40
:
11393 case FLASH_5761VENDOR_ST_A_M45PE80
:
11394 case FLASH_5761VENDOR_ST_A_M45PE16
:
11395 case FLASH_5761VENDOR_ST_M_M45PE20
:
11396 case FLASH_5761VENDOR_ST_M_M45PE40
:
11397 case FLASH_5761VENDOR_ST_M_M45PE80
:
11398 case FLASH_5761VENDOR_ST_M_M45PE16
:
11399 tp
->nvram_jedecnum
= JEDEC_ST
;
11400 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11401 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11402 tp
->nvram_pagesize
= 256;
11407 tp
->nvram_size
= tr32(NVRAM_ADDR_LOCKOUT
);
11410 case FLASH_5761VENDOR_ATMEL_ADB161D
:
11411 case FLASH_5761VENDOR_ATMEL_MDB161D
:
11412 case FLASH_5761VENDOR_ST_A_M45PE16
:
11413 case FLASH_5761VENDOR_ST_M_M45PE16
:
11414 tp
->nvram_size
= TG3_NVRAM_SIZE_2MB
;
11416 case FLASH_5761VENDOR_ATMEL_ADB081D
:
11417 case FLASH_5761VENDOR_ATMEL_MDB081D
:
11418 case FLASH_5761VENDOR_ST_A_M45PE80
:
11419 case FLASH_5761VENDOR_ST_M_M45PE80
:
11420 tp
->nvram_size
= TG3_NVRAM_SIZE_1MB
;
11422 case FLASH_5761VENDOR_ATMEL_ADB041D
:
11423 case FLASH_5761VENDOR_ATMEL_MDB041D
:
11424 case FLASH_5761VENDOR_ST_A_M45PE40
:
11425 case FLASH_5761VENDOR_ST_M_M45PE40
:
11426 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
11428 case FLASH_5761VENDOR_ATMEL_ADB021D
:
11429 case FLASH_5761VENDOR_ATMEL_MDB021D
:
11430 case FLASH_5761VENDOR_ST_A_M45PE20
:
11431 case FLASH_5761VENDOR_ST_M_M45PE20
:
11432 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
11438 static void __devinit
tg3_get_5906_nvram_info(struct tg3
*tp
)
11440 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11441 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11442 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
11445 static void __devinit
tg3_get_57780_nvram_info(struct tg3
*tp
)
11449 nvcfg1
= tr32(NVRAM_CFG1
);
11451 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11452 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ
:
11453 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ
:
11454 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11455 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11456 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
11458 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
11459 tw32(NVRAM_CFG1
, nvcfg1
);
11461 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
11462 case FLASH_57780VENDOR_ATMEL_AT45DB011D
:
11463 case FLASH_57780VENDOR_ATMEL_AT45DB011B
:
11464 case FLASH_57780VENDOR_ATMEL_AT45DB021D
:
11465 case FLASH_57780VENDOR_ATMEL_AT45DB021B
:
11466 case FLASH_57780VENDOR_ATMEL_AT45DB041D
:
11467 case FLASH_57780VENDOR_ATMEL_AT45DB041B
:
11468 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11469 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11470 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11472 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11473 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
11474 case FLASH_57780VENDOR_ATMEL_AT45DB011D
:
11475 case FLASH_57780VENDOR_ATMEL_AT45DB011B
:
11476 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
11478 case FLASH_57780VENDOR_ATMEL_AT45DB021D
:
11479 case FLASH_57780VENDOR_ATMEL_AT45DB021B
:
11480 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
11482 case FLASH_57780VENDOR_ATMEL_AT45DB041D
:
11483 case FLASH_57780VENDOR_ATMEL_AT45DB041B
:
11484 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
11488 case FLASH_5752VENDOR_ST_M45PE10
:
11489 case FLASH_5752VENDOR_ST_M45PE20
:
11490 case FLASH_5752VENDOR_ST_M45PE40
:
11491 tp
->nvram_jedecnum
= JEDEC_ST
;
11492 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11493 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11495 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11496 case FLASH_5752VENDOR_ST_M45PE10
:
11497 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
11499 case FLASH_5752VENDOR_ST_M45PE20
:
11500 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
11502 case FLASH_5752VENDOR_ST_M45PE40
:
11503 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
11508 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM
;
11512 tg3_nvram_get_pagesize(tp
, nvcfg1
);
11513 if (tp
->nvram_pagesize
!= 264 && tp
->nvram_pagesize
!= 528)
11514 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
11518 static void __devinit
tg3_get_5717_nvram_info(struct tg3
*tp
)
11522 nvcfg1
= tr32(NVRAM_CFG1
);
11524 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11525 case FLASH_5717VENDOR_ATMEL_EEPROM
:
11526 case FLASH_5717VENDOR_MICRO_EEPROM
:
11527 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11528 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11529 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
11531 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
11532 tw32(NVRAM_CFG1
, nvcfg1
);
11534 case FLASH_5717VENDOR_ATMEL_MDB011D
:
11535 case FLASH_5717VENDOR_ATMEL_ADB011B
:
11536 case FLASH_5717VENDOR_ATMEL_ADB011D
:
11537 case FLASH_5717VENDOR_ATMEL_MDB021D
:
11538 case FLASH_5717VENDOR_ATMEL_ADB021B
:
11539 case FLASH_5717VENDOR_ATMEL_ADB021D
:
11540 case FLASH_5717VENDOR_ATMEL_45USPT
:
11541 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11542 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11543 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11545 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11546 case FLASH_5717VENDOR_ATMEL_MDB021D
:
11547 case FLASH_5717VENDOR_ATMEL_ADB021B
:
11548 case FLASH_5717VENDOR_ATMEL_ADB021D
:
11549 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
11552 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
11556 case FLASH_5717VENDOR_ST_M_M25PE10
:
11557 case FLASH_5717VENDOR_ST_A_M25PE10
:
11558 case FLASH_5717VENDOR_ST_M_M45PE10
:
11559 case FLASH_5717VENDOR_ST_A_M45PE10
:
11560 case FLASH_5717VENDOR_ST_M_M25PE20
:
11561 case FLASH_5717VENDOR_ST_A_M25PE20
:
11562 case FLASH_5717VENDOR_ST_M_M45PE20
:
11563 case FLASH_5717VENDOR_ST_A_M45PE20
:
11564 case FLASH_5717VENDOR_ST_25USPT
:
11565 case FLASH_5717VENDOR_ST_45USPT
:
11566 tp
->nvram_jedecnum
= JEDEC_ST
;
11567 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11568 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11570 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11571 case FLASH_5717VENDOR_ST_M_M25PE20
:
11572 case FLASH_5717VENDOR_ST_A_M25PE20
:
11573 case FLASH_5717VENDOR_ST_M_M45PE20
:
11574 case FLASH_5717VENDOR_ST_A_M45PE20
:
11575 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
11578 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
11583 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM
;
11587 tg3_nvram_get_pagesize(tp
, nvcfg1
);
11588 if (tp
->nvram_pagesize
!= 264 && tp
->nvram_pagesize
!= 528)
11589 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
11592 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11593 static void __devinit
tg3_nvram_init(struct tg3
*tp
)
11595 tw32_f(GRC_EEPROM_ADDR
,
11596 (EEPROM_ADDR_FSM_RESET
|
11597 (EEPROM_DEFAULT_CLOCK_PERIOD
<<
11598 EEPROM_ADDR_CLKPERD_SHIFT
)));
11602 /* Enable seeprom accesses. */
11603 tw32_f(GRC_LOCAL_CTRL
,
11604 tr32(GRC_LOCAL_CTRL
) | GRC_LCLCTRL_AUTO_SEEPROM
);
11607 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
11608 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
) {
11609 tp
->tg3_flags
|= TG3_FLAG_NVRAM
;
11611 if (tg3_nvram_lock(tp
)) {
11612 netdev_warn(tp
->dev
,
11613 "Cannot get nvram lock, %s failed\n",
11617 tg3_enable_nvram_access(tp
);
11619 tp
->nvram_size
= 0;
11621 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
)
11622 tg3_get_5752_nvram_info(tp
);
11623 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
)
11624 tg3_get_5755_nvram_info(tp
);
11625 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5787
||
11626 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
11627 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
11628 tg3_get_5787_nvram_info(tp
);
11629 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
)
11630 tg3_get_5761_nvram_info(tp
);
11631 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
11632 tg3_get_5906_nvram_info(tp
);
11633 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
||
11634 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
11635 tg3_get_57780_nvram_info(tp
);
11636 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
)
11637 tg3_get_5717_nvram_info(tp
);
11639 tg3_get_nvram_info(tp
);
11641 if (tp
->nvram_size
== 0)
11642 tg3_get_nvram_size(tp
);
11644 tg3_disable_nvram_access(tp
);
11645 tg3_nvram_unlock(tp
);
11648 tp
->tg3_flags
&= ~(TG3_FLAG_NVRAM
| TG3_FLAG_NVRAM_BUFFERED
);
11650 tg3_get_eeprom_size(tp
);
11654 static int tg3_nvram_write_block_using_eeprom(struct tg3
*tp
,
11655 u32 offset
, u32 len
, u8
*buf
)
11660 for (i
= 0; i
< len
; i
+= 4) {
11666 memcpy(&data
, buf
+ i
, 4);
11669 * The SEEPROM interface expects the data to always be opposite
11670 * the native endian format. We accomplish this by reversing
11671 * all the operations that would have been performed on the
11672 * data from a call to tg3_nvram_read_be32().
11674 tw32(GRC_EEPROM_DATA
, swab32(be32_to_cpu(data
)));
11676 val
= tr32(GRC_EEPROM_ADDR
);
11677 tw32(GRC_EEPROM_ADDR
, val
| EEPROM_ADDR_COMPLETE
);
11679 val
&= ~(EEPROM_ADDR_ADDR_MASK
| EEPROM_ADDR_DEVID_MASK
|
11681 tw32(GRC_EEPROM_ADDR
, val
|
11682 (0 << EEPROM_ADDR_DEVID_SHIFT
) |
11683 (addr
& EEPROM_ADDR_ADDR_MASK
) |
11684 EEPROM_ADDR_START
|
11685 EEPROM_ADDR_WRITE
);
11687 for (j
= 0; j
< 1000; j
++) {
11688 val
= tr32(GRC_EEPROM_ADDR
);
11690 if (val
& EEPROM_ADDR_COMPLETE
)
11694 if (!(val
& EEPROM_ADDR_COMPLETE
)) {
11703 /* offset and length are dword aligned */
11704 static int tg3_nvram_write_block_unbuffered(struct tg3
*tp
, u32 offset
, u32 len
,
11708 u32 pagesize
= tp
->nvram_pagesize
;
11709 u32 pagemask
= pagesize
- 1;
11713 tmp
= kmalloc(pagesize
, GFP_KERNEL
);
11719 u32 phy_addr
, page_off
, size
;
11721 phy_addr
= offset
& ~pagemask
;
11723 for (j
= 0; j
< pagesize
; j
+= 4) {
11724 ret
= tg3_nvram_read_be32(tp
, phy_addr
+ j
,
11725 (__be32
*) (tmp
+ j
));
11732 page_off
= offset
& pagemask
;
11739 memcpy(tmp
+ page_off
, buf
, size
);
11741 offset
= offset
+ (pagesize
- page_off
);
11743 tg3_enable_nvram_access(tp
);
11746 * Before we can erase the flash page, we need
11747 * to issue a special "write enable" command.
11749 nvram_cmd
= NVRAM_CMD_WREN
| NVRAM_CMD_GO
| NVRAM_CMD_DONE
;
11751 if (tg3_nvram_exec_cmd(tp
, nvram_cmd
))
11754 /* Erase the target page */
11755 tw32(NVRAM_ADDR
, phy_addr
);
11757 nvram_cmd
= NVRAM_CMD_GO
| NVRAM_CMD_DONE
| NVRAM_CMD_WR
|
11758 NVRAM_CMD_FIRST
| NVRAM_CMD_LAST
| NVRAM_CMD_ERASE
;
11760 if (tg3_nvram_exec_cmd(tp
, nvram_cmd
))
11763 /* Issue another write enable to start the write. */
11764 nvram_cmd
= NVRAM_CMD_WREN
| NVRAM_CMD_GO
| NVRAM_CMD_DONE
;
11766 if (tg3_nvram_exec_cmd(tp
, nvram_cmd
))
11769 for (j
= 0; j
< pagesize
; j
+= 4) {
11772 data
= *((__be32
*) (tmp
+ j
));
11774 tw32(NVRAM_WRDATA
, be32_to_cpu(data
));
11776 tw32(NVRAM_ADDR
, phy_addr
+ j
);
11778 nvram_cmd
= NVRAM_CMD_GO
| NVRAM_CMD_DONE
|
11782 nvram_cmd
|= NVRAM_CMD_FIRST
;
11783 else if (j
== (pagesize
- 4))
11784 nvram_cmd
|= NVRAM_CMD_LAST
;
11786 if ((ret
= tg3_nvram_exec_cmd(tp
, nvram_cmd
)))
11793 nvram_cmd
= NVRAM_CMD_WRDI
| NVRAM_CMD_GO
| NVRAM_CMD_DONE
;
11794 tg3_nvram_exec_cmd(tp
, nvram_cmd
);
11801 /* offset and length are dword aligned */
11802 static int tg3_nvram_write_block_buffered(struct tg3
*tp
, u32 offset
, u32 len
,
11807 for (i
= 0; i
< len
; i
+= 4, offset
+= 4) {
11808 u32 page_off
, phy_addr
, nvram_cmd
;
11811 memcpy(&data
, buf
+ i
, 4);
11812 tw32(NVRAM_WRDATA
, be32_to_cpu(data
));
11814 page_off
= offset
% tp
->nvram_pagesize
;
11816 phy_addr
= tg3_nvram_phys_addr(tp
, offset
);
11818 tw32(NVRAM_ADDR
, phy_addr
);
11820 nvram_cmd
= NVRAM_CMD_GO
| NVRAM_CMD_DONE
| NVRAM_CMD_WR
;
11822 if (page_off
== 0 || i
== 0)
11823 nvram_cmd
|= NVRAM_CMD_FIRST
;
11824 if (page_off
== (tp
->nvram_pagesize
- 4))
11825 nvram_cmd
|= NVRAM_CMD_LAST
;
11827 if (i
== (len
- 4))
11828 nvram_cmd
|= NVRAM_CMD_LAST
;
11830 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5752
&&
11831 !(tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) &&
11832 (tp
->nvram_jedecnum
== JEDEC_ST
) &&
11833 (nvram_cmd
& NVRAM_CMD_FIRST
)) {
11835 if ((ret
= tg3_nvram_exec_cmd(tp
,
11836 NVRAM_CMD_WREN
| NVRAM_CMD_GO
|
11841 if (!(tp
->tg3_flags2
& TG3_FLG2_FLASH
)) {
11842 /* We always do complete word writes to eeprom. */
11843 nvram_cmd
|= (NVRAM_CMD_FIRST
| NVRAM_CMD_LAST
);
11846 if ((ret
= tg3_nvram_exec_cmd(tp
, nvram_cmd
)))
11852 /* offset and length are dword aligned */
11853 static int tg3_nvram_write_block(struct tg3
*tp
, u32 offset
, u32 len
, u8
*buf
)
11857 if (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
) {
11858 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
&
11859 ~GRC_LCLCTRL_GPIO_OUTPUT1
);
11863 if (!(tp
->tg3_flags
& TG3_FLAG_NVRAM
)) {
11864 ret
= tg3_nvram_write_block_using_eeprom(tp
, offset
, len
, buf
);
11868 ret
= tg3_nvram_lock(tp
);
11872 tg3_enable_nvram_access(tp
);
11873 if ((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
11874 !(tp
->tg3_flags3
& TG3_FLG3_PROTECTED_NVRAM
))
11875 tw32(NVRAM_WRITE1
, 0x406);
11877 grc_mode
= tr32(GRC_MODE
);
11878 tw32(GRC_MODE
, grc_mode
| GRC_MODE_NVRAM_WR_ENABLE
);
11880 if ((tp
->tg3_flags
& TG3_FLAG_NVRAM_BUFFERED
) ||
11881 !(tp
->tg3_flags2
& TG3_FLG2_FLASH
)) {
11883 ret
= tg3_nvram_write_block_buffered(tp
, offset
, len
,
11886 ret
= tg3_nvram_write_block_unbuffered(tp
, offset
, len
,
11890 grc_mode
= tr32(GRC_MODE
);
11891 tw32(GRC_MODE
, grc_mode
& ~GRC_MODE_NVRAM_WR_ENABLE
);
11893 tg3_disable_nvram_access(tp
);
11894 tg3_nvram_unlock(tp
);
11897 if (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
) {
11898 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
);
11905 struct subsys_tbl_ent
{
11906 u16 subsys_vendor
, subsys_devid
;
11910 static struct subsys_tbl_ent subsys_id_to_phy_id
[] __devinitdata
= {
11911 /* Broadcom boards. */
11912 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11913 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6
, TG3_PHY_ID_BCM5401
},
11914 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11915 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5
, TG3_PHY_ID_BCM5701
},
11916 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11917 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6
, TG3_PHY_ID_BCM8002
},
11918 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11919 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9
, 0 },
11920 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11921 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1
, TG3_PHY_ID_BCM5701
},
11922 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11923 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8
, TG3_PHY_ID_BCM5701
},
11924 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11925 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7
, 0 },
11926 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11927 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10
, TG3_PHY_ID_BCM5701
},
11928 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11929 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12
, TG3_PHY_ID_BCM5701
},
11930 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11931 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1
, TG3_PHY_ID_BCM5703
},
11932 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11933 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2
, TG3_PHY_ID_BCM5703
},
11936 { TG3PCI_SUBVENDOR_ID_3COM
,
11937 TG3PCI_SUBDEVICE_ID_3COM_3C996T
, TG3_PHY_ID_BCM5401
},
11938 { TG3PCI_SUBVENDOR_ID_3COM
,
11939 TG3PCI_SUBDEVICE_ID_3COM_3C996BT
, TG3_PHY_ID_BCM5701
},
11940 { TG3PCI_SUBVENDOR_ID_3COM
,
11941 TG3PCI_SUBDEVICE_ID_3COM_3C996SX
, 0 },
11942 { TG3PCI_SUBVENDOR_ID_3COM
,
11943 TG3PCI_SUBDEVICE_ID_3COM_3C1000T
, TG3_PHY_ID_BCM5701
},
11944 { TG3PCI_SUBVENDOR_ID_3COM
,
11945 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01
, TG3_PHY_ID_BCM5701
},
11948 { TG3PCI_SUBVENDOR_ID_DELL
,
11949 TG3PCI_SUBDEVICE_ID_DELL_VIPER
, TG3_PHY_ID_BCM5401
},
11950 { TG3PCI_SUBVENDOR_ID_DELL
,
11951 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR
, TG3_PHY_ID_BCM5401
},
11952 { TG3PCI_SUBVENDOR_ID_DELL
,
11953 TG3PCI_SUBDEVICE_ID_DELL_MERLOT
, TG3_PHY_ID_BCM5411
},
11954 { TG3PCI_SUBVENDOR_ID_DELL
,
11955 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT
, TG3_PHY_ID_BCM5411
},
11957 /* Compaq boards. */
11958 { TG3PCI_SUBVENDOR_ID_COMPAQ
,
11959 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE
, TG3_PHY_ID_BCM5701
},
11960 { TG3PCI_SUBVENDOR_ID_COMPAQ
,
11961 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2
, TG3_PHY_ID_BCM5701
},
11962 { TG3PCI_SUBVENDOR_ID_COMPAQ
,
11963 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING
, 0 },
11964 { TG3PCI_SUBVENDOR_ID_COMPAQ
,
11965 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780
, TG3_PHY_ID_BCM5701
},
11966 { TG3PCI_SUBVENDOR_ID_COMPAQ
,
11967 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2
, TG3_PHY_ID_BCM5701
},
11970 { TG3PCI_SUBVENDOR_ID_IBM
,
11971 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2
, 0 }
11974 static struct subsys_tbl_ent
* __devinit
tg3_lookup_by_subsys(struct tg3
*tp
)
11978 for (i
= 0; i
< ARRAY_SIZE(subsys_id_to_phy_id
); i
++) {
11979 if ((subsys_id_to_phy_id
[i
].subsys_vendor
==
11980 tp
->pdev
->subsystem_vendor
) &&
11981 (subsys_id_to_phy_id
[i
].subsys_devid
==
11982 tp
->pdev
->subsystem_device
))
11983 return &subsys_id_to_phy_id
[i
];
11988 static void __devinit
tg3_get_eeprom_hw_cfg(struct tg3
*tp
)
11993 /* On some early chips the SRAM cannot be accessed in D3hot state,
11994 * so need make sure we're in D0.
11996 pci_read_config_word(tp
->pdev
, tp
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
11997 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
11998 pci_write_config_word(tp
->pdev
, tp
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
12001 /* Make sure register accesses (indirect or otherwise)
12002 * will function correctly.
12004 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
12005 tp
->misc_host_ctrl
);
12007 /* The memory arbiter has to be enabled in order for SRAM accesses
12008 * to succeed. Normally on powerup the tg3 chip firmware will make
12009 * sure it is enabled, but other entities such as system netboot
12010 * code might disable it.
12012 val
= tr32(MEMARB_MODE
);
12013 tw32(MEMARB_MODE
, val
| MEMARB_MODE_ENABLE
);
12015 tp
->phy_id
= TG3_PHY_ID_INVALID
;
12016 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
12018 /* Assume an onboard device and WOL capable by default. */
12019 tp
->tg3_flags
|= TG3_FLAG_EEPROM_WRITE_PROT
| TG3_FLAG_WOL_CAP
;
12021 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
12022 if (!(tr32(PCIE_TRANSACTION_CFG
) & PCIE_TRANS_CFG_LOM
)) {
12023 tp
->tg3_flags
&= ~TG3_FLAG_EEPROM_WRITE_PROT
;
12024 tp
->tg3_flags2
|= TG3_FLG2_IS_NIC
;
12026 val
= tr32(VCPU_CFGSHDW
);
12027 if (val
& VCPU_CFGSHDW_ASPM_DBNC
)
12028 tp
->tg3_flags
|= TG3_FLAG_ASPM_WORKAROUND
;
12029 if ((val
& VCPU_CFGSHDW_WOL_ENABLE
) &&
12030 (val
& VCPU_CFGSHDW_WOL_MAGPKT
))
12031 tp
->tg3_flags
|= TG3_FLAG_WOL_ENABLE
;
12035 tg3_read_mem(tp
, NIC_SRAM_DATA_SIG
, &val
);
12036 if (val
== NIC_SRAM_DATA_SIG_MAGIC
) {
12037 u32 nic_cfg
, led_cfg
;
12038 u32 nic_phy_id
, ver
, cfg2
= 0, cfg4
= 0, eeprom_phy_id
;
12039 int eeprom_phy_serdes
= 0;
12041 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG
, &nic_cfg
);
12042 tp
->nic_sram_data_cfg
= nic_cfg
;
12044 tg3_read_mem(tp
, NIC_SRAM_DATA_VER
, &ver
);
12045 ver
>>= NIC_SRAM_DATA_VER_SHIFT
;
12046 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
) &&
12047 (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
) &&
12048 (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5703
) &&
12049 (ver
> 0) && (ver
< 0x100))
12050 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG_2
, &cfg2
);
12052 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
12053 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG_4
, &cfg4
);
12055 if ((nic_cfg
& NIC_SRAM_DATA_CFG_PHY_TYPE_MASK
) ==
12056 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER
)
12057 eeprom_phy_serdes
= 1;
12059 tg3_read_mem(tp
, NIC_SRAM_DATA_PHY_ID
, &nic_phy_id
);
12060 if (nic_phy_id
!= 0) {
12061 u32 id1
= nic_phy_id
& NIC_SRAM_DATA_PHY_ID1_MASK
;
12062 u32 id2
= nic_phy_id
& NIC_SRAM_DATA_PHY_ID2_MASK
;
12064 eeprom_phy_id
= (id1
>> 16) << 10;
12065 eeprom_phy_id
|= (id2
& 0xfc00) << 16;
12066 eeprom_phy_id
|= (id2
& 0x03ff) << 0;
12070 tp
->phy_id
= eeprom_phy_id
;
12071 if (eeprom_phy_serdes
) {
12072 if ((tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) ||
12073 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
)
12074 tp
->tg3_flags2
|= TG3_FLG2_MII_SERDES
;
12076 tp
->tg3_flags2
|= TG3_FLG2_PHY_SERDES
;
12079 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
12080 led_cfg
= cfg2
& (NIC_SRAM_DATA_CFG_LED_MODE_MASK
|
12081 SHASTA_EXT_LED_MODE_MASK
);
12083 led_cfg
= nic_cfg
& NIC_SRAM_DATA_CFG_LED_MODE_MASK
;
12087 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1
:
12088 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
12091 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2
:
12092 tp
->led_ctrl
= LED_CTRL_MODE_PHY_2
;
12095 case NIC_SRAM_DATA_CFG_LED_MODE_MAC
:
12096 tp
->led_ctrl
= LED_CTRL_MODE_MAC
;
12098 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12099 * read on some older 5700/5701 bootcode.
12101 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
12103 GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
12105 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
12109 case SHASTA_EXT_LED_SHARED
:
12110 tp
->led_ctrl
= LED_CTRL_MODE_SHARED
;
12111 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
&&
12112 tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A1
)
12113 tp
->led_ctrl
|= (LED_CTRL_MODE_PHY_1
|
12114 LED_CTRL_MODE_PHY_2
);
12117 case SHASTA_EXT_LED_MAC
:
12118 tp
->led_ctrl
= LED_CTRL_MODE_SHASTA_MAC
;
12121 case SHASTA_EXT_LED_COMBO
:
12122 tp
->led_ctrl
= LED_CTRL_MODE_COMBO
;
12123 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
)
12124 tp
->led_ctrl
|= (LED_CTRL_MODE_PHY_1
|
12125 LED_CTRL_MODE_PHY_2
);
12130 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
12131 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) &&
12132 tp
->pdev
->subsystem_vendor
== PCI_VENDOR_ID_DELL
)
12133 tp
->led_ctrl
= LED_CTRL_MODE_PHY_2
;
12135 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
)
12136 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
12138 if (nic_cfg
& NIC_SRAM_DATA_CFG_EEPROM_WP
) {
12139 tp
->tg3_flags
|= TG3_FLAG_EEPROM_WRITE_PROT
;
12140 if ((tp
->pdev
->subsystem_vendor
==
12141 PCI_VENDOR_ID_ARIMA
) &&
12142 (tp
->pdev
->subsystem_device
== 0x205a ||
12143 tp
->pdev
->subsystem_device
== 0x2063))
12144 tp
->tg3_flags
&= ~TG3_FLAG_EEPROM_WRITE_PROT
;
12146 tp
->tg3_flags
&= ~TG3_FLAG_EEPROM_WRITE_PROT
;
12147 tp
->tg3_flags2
|= TG3_FLG2_IS_NIC
;
12150 if (nic_cfg
& NIC_SRAM_DATA_CFG_ASF_ENABLE
) {
12151 tp
->tg3_flags
|= TG3_FLAG_ENABLE_ASF
;
12152 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
12153 tp
->tg3_flags2
|= TG3_FLG2_ASF_NEW_HANDSHAKE
;
12156 if ((nic_cfg
& NIC_SRAM_DATA_CFG_APE_ENABLE
) &&
12157 (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
))
12158 tp
->tg3_flags3
|= TG3_FLG3_ENABLE_APE
;
12160 if (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
&&
12161 !(nic_cfg
& NIC_SRAM_DATA_CFG_FIBER_WOL
))
12162 tp
->tg3_flags
&= ~TG3_FLAG_WOL_CAP
;
12164 if ((tp
->tg3_flags
& TG3_FLAG_WOL_CAP
) &&
12165 (nic_cfg
& NIC_SRAM_DATA_CFG_WOL_ENABLE
))
12166 tp
->tg3_flags
|= TG3_FLAG_WOL_ENABLE
;
12168 if (cfg2
& (1 << 17))
12169 tp
->tg3_flags2
|= TG3_FLG2_CAPACITIVE_COUPLING
;
12171 /* serdes signal pre-emphasis in register 0x590 set by */
12172 /* bootcode if bit 18 is set */
12173 if (cfg2
& (1 << 18))
12174 tp
->tg3_flags2
|= TG3_FLG2_SERDES_PREEMPHASIS
;
12176 if (((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
12177 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
)) &&
12178 (cfg2
& NIC_SRAM_DATA_CFG_2_APD_EN
))
12179 tp
->tg3_flags3
|= TG3_FLG3_PHY_ENABLE_APD
;
12181 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
12184 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG_3
, &cfg3
);
12185 if (cfg3
& NIC_SRAM_ASPM_DEBOUNCE
)
12186 tp
->tg3_flags
|= TG3_FLAG_ASPM_WORKAROUND
;
12189 if (cfg4
& NIC_SRAM_RGMII_INBAND_DISABLE
)
12190 tp
->tg3_flags3
|= TG3_FLG3_RGMII_INBAND_DISABLE
;
12191 if (cfg4
& NIC_SRAM_RGMII_EXT_IBND_RX_EN
)
12192 tp
->tg3_flags3
|= TG3_FLG3_RGMII_EXT_IBND_RX_EN
;
12193 if (cfg4
& NIC_SRAM_RGMII_EXT_IBND_TX_EN
)
12194 tp
->tg3_flags3
|= TG3_FLG3_RGMII_EXT_IBND_TX_EN
;
12197 device_init_wakeup(&tp
->pdev
->dev
, tp
->tg3_flags
& TG3_FLAG_WOL_CAP
);
12198 device_set_wakeup_enable(&tp
->pdev
->dev
,
12199 tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
);
12202 static int __devinit
tg3_issue_otp_command(struct tg3
*tp
, u32 cmd
)
12207 tw32(OTP_CTRL
, cmd
| OTP_CTRL_OTP_CMD_START
);
12208 tw32(OTP_CTRL
, cmd
);
12210 /* Wait for up to 1 ms for command to execute. */
12211 for (i
= 0; i
< 100; i
++) {
12212 val
= tr32(OTP_STATUS
);
12213 if (val
& OTP_STATUS_CMD_DONE
)
12218 return (val
& OTP_STATUS_CMD_DONE
) ? 0 : -EBUSY
;
12221 /* Read the gphy configuration from the OTP region of the chip. The gphy
12222 * configuration is a 32-bit value that straddles the alignment boundary.
12223 * We do two 32-bit reads and then shift and merge the results.
12225 static u32 __devinit
tg3_read_otp_phycfg(struct tg3
*tp
)
12227 u32 bhalf_otp
, thalf_otp
;
12229 tw32(OTP_MODE
, OTP_MODE_OTP_THRU_GRC
);
12231 if (tg3_issue_otp_command(tp
, OTP_CTRL_OTP_CMD_INIT
))
12234 tw32(OTP_ADDRESS
, OTP_ADDRESS_MAGIC1
);
12236 if (tg3_issue_otp_command(tp
, OTP_CTRL_OTP_CMD_READ
))
12239 thalf_otp
= tr32(OTP_READ_DATA
);
12241 tw32(OTP_ADDRESS
, OTP_ADDRESS_MAGIC2
);
12243 if (tg3_issue_otp_command(tp
, OTP_CTRL_OTP_CMD_READ
))
12246 bhalf_otp
= tr32(OTP_READ_DATA
);
12248 return ((thalf_otp
& 0x0000ffff) << 16) | (bhalf_otp
>> 16);
12251 static int __devinit
tg3_phy_probe(struct tg3
*tp
)
12253 u32 hw_phy_id_1
, hw_phy_id_2
;
12254 u32 hw_phy_id
, hw_phy_id_masked
;
12257 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
)
12258 return tg3_phy_init(tp
);
12260 /* Reading the PHY ID register can conflict with ASF
12261 * firmware access to the PHY hardware.
12264 if ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) ||
12265 (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)) {
12266 hw_phy_id
= hw_phy_id_masked
= TG3_PHY_ID_INVALID
;
12268 /* Now read the physical PHY_ID from the chip and verify
12269 * that it is sane. If it doesn't look good, we fall back
12270 * to either the hard-coded table based PHY_ID and failing
12271 * that the value found in the eeprom area.
12273 err
|= tg3_readphy(tp
, MII_PHYSID1
, &hw_phy_id_1
);
12274 err
|= tg3_readphy(tp
, MII_PHYSID2
, &hw_phy_id_2
);
12276 hw_phy_id
= (hw_phy_id_1
& 0xffff) << 10;
12277 hw_phy_id
|= (hw_phy_id_2
& 0xfc00) << 16;
12278 hw_phy_id
|= (hw_phy_id_2
& 0x03ff) << 0;
12280 hw_phy_id_masked
= hw_phy_id
& TG3_PHY_ID_MASK
;
12283 if (!err
&& TG3_KNOWN_PHY_ID(hw_phy_id_masked
)) {
12284 tp
->phy_id
= hw_phy_id
;
12285 if (hw_phy_id_masked
== TG3_PHY_ID_BCM8002
)
12286 tp
->tg3_flags2
|= TG3_FLG2_PHY_SERDES
;
12288 tp
->tg3_flags2
&= ~TG3_FLG2_PHY_SERDES
;
12290 if (tp
->phy_id
!= TG3_PHY_ID_INVALID
) {
12291 /* Do nothing, phy ID already set up in
12292 * tg3_get_eeprom_hw_cfg().
12295 struct subsys_tbl_ent
*p
;
12297 /* No eeprom signature? Try the hardcoded
12298 * subsys device table.
12300 p
= tg3_lookup_by_subsys(tp
);
12304 tp
->phy_id
= p
->phy_id
;
12306 tp
->phy_id
== TG3_PHY_ID_BCM8002
)
12307 tp
->tg3_flags2
|= TG3_FLG2_PHY_SERDES
;
12311 if (!(tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
) &&
12312 !(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) &&
12313 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)) {
12314 u32 bmsr
, adv_reg
, tg3_ctrl
, mask
;
12316 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
12317 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
12318 (bmsr
& BMSR_LSTATUS
))
12319 goto skip_phy_reset
;
12321 err
= tg3_phy_reset(tp
);
12325 adv_reg
= (ADVERTISE_10HALF
| ADVERTISE_10FULL
|
12326 ADVERTISE_100HALF
| ADVERTISE_100FULL
|
12327 ADVERTISE_CSMA
| ADVERTISE_PAUSE_CAP
);
12329 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)) {
12330 tg3_ctrl
= (MII_TG3_CTRL_ADV_1000_HALF
|
12331 MII_TG3_CTRL_ADV_1000_FULL
);
12332 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
12333 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
)
12334 tg3_ctrl
|= (MII_TG3_CTRL_AS_MASTER
|
12335 MII_TG3_CTRL_ENABLE_AS_MASTER
);
12338 mask
= (ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
12339 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
|
12340 ADVERTISED_1000baseT_Half
| ADVERTISED_1000baseT_Full
);
12341 if (!tg3_copper_is_advertising_all(tp
, mask
)) {
12342 tg3_writephy(tp
, MII_ADVERTISE
, adv_reg
);
12344 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
))
12345 tg3_writephy(tp
, MII_TG3_CTRL
, tg3_ctrl
);
12347 tg3_writephy(tp
, MII_BMCR
,
12348 BMCR_ANENABLE
| BMCR_ANRESTART
);
12350 tg3_phy_set_wirespeed(tp
);
12352 tg3_writephy(tp
, MII_ADVERTISE
, adv_reg
);
12353 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
))
12354 tg3_writephy(tp
, MII_TG3_CTRL
, tg3_ctrl
);
12358 if ((tp
->phy_id
& TG3_PHY_ID_MASK
) == TG3_PHY_ID_BCM5401
) {
12359 err
= tg3_init_5401phy_dsp(tp
);
12363 err
= tg3_init_5401phy_dsp(tp
);
12366 if (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
)
12367 tp
->link_config
.advertising
=
12368 (ADVERTISED_1000baseT_Half
|
12369 ADVERTISED_1000baseT_Full
|
12370 ADVERTISED_Autoneg
|
12372 if (tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)
12373 tp
->link_config
.advertising
&=
12374 ~(ADVERTISED_1000baseT_Half
|
12375 ADVERTISED_1000baseT_Full
);
12380 static void __devinit
tg3_read_vpd(struct tg3
*tp
)
12382 u8 vpd_data
[TG3_NVM_VPD_LEN
];
12383 unsigned int block_end
, rosize
, len
;
12387 if ((tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) ||
12388 tg3_nvram_read(tp
, 0x0, &magic
))
12389 goto out_not_found
;
12391 if (magic
== TG3_EEPROM_MAGIC
) {
12392 for (i
= 0; i
< TG3_NVM_VPD_LEN
; i
+= 4) {
12395 /* The data is in little-endian format in NVRAM.
12396 * Use the big-endian read routines to preserve
12397 * the byte order as it exists in NVRAM.
12399 if (tg3_nvram_read_be32(tp
, TG3_NVM_VPD_OFF
+ i
, &tmp
))
12400 goto out_not_found
;
12402 memcpy(&vpd_data
[i
], &tmp
, sizeof(tmp
));
12406 unsigned int pos
= 0;
12408 for (; pos
< TG3_NVM_VPD_LEN
&& i
< 3; i
++, pos
+= cnt
) {
12409 cnt
= pci_read_vpd(tp
->pdev
, pos
,
12410 TG3_NVM_VPD_LEN
- pos
,
12412 if (cnt
== -ETIMEDOUT
|| -EINTR
)
12415 goto out_not_found
;
12417 if (pos
!= TG3_NVM_VPD_LEN
)
12418 goto out_not_found
;
12421 i
= pci_vpd_find_tag(vpd_data
, 0, TG3_NVM_VPD_LEN
,
12422 PCI_VPD_LRDT_RO_DATA
);
12424 goto out_not_found
;
12426 rosize
= pci_vpd_lrdt_size(&vpd_data
[i
]);
12427 block_end
= i
+ PCI_VPD_LRDT_TAG_SIZE
+ rosize
;
12428 i
+= PCI_VPD_LRDT_TAG_SIZE
;
12430 if (block_end
> TG3_NVM_VPD_LEN
)
12431 goto out_not_found
;
12433 j
= pci_vpd_find_info_keyword(vpd_data
, i
, rosize
,
12434 PCI_VPD_RO_KEYWORD_MFR_ID
);
12436 len
= pci_vpd_info_field_size(&vpd_data
[j
]);
12438 j
+= PCI_VPD_INFO_FLD_HDR_SIZE
;
12439 if (j
+ len
> block_end
|| len
!= 4 ||
12440 memcmp(&vpd_data
[j
], "1028", 4))
12443 j
= pci_vpd_find_info_keyword(vpd_data
, i
, rosize
,
12444 PCI_VPD_RO_KEYWORD_VENDOR0
);
12448 len
= pci_vpd_info_field_size(&vpd_data
[j
]);
12450 j
+= PCI_VPD_INFO_FLD_HDR_SIZE
;
12451 if (j
+ len
> block_end
)
12454 memcpy(tp
->fw_ver
, &vpd_data
[j
], len
);
12455 strncat(tp
->fw_ver
, " bc ", TG3_NVM_VPD_LEN
- len
- 1);
12459 i
= pci_vpd_find_info_keyword(vpd_data
, i
, rosize
,
12460 PCI_VPD_RO_KEYWORD_PARTNO
);
12462 goto out_not_found
;
12464 len
= pci_vpd_info_field_size(&vpd_data
[i
]);
12466 i
+= PCI_VPD_INFO_FLD_HDR_SIZE
;
12467 if (len
> TG3_BPN_SIZE
||
12468 (len
+ i
) > TG3_NVM_VPD_LEN
)
12469 goto out_not_found
;
12471 memcpy(tp
->board_part_number
, &vpd_data
[i
], len
);
12476 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
12477 strcpy(tp
->board_part_number
, "BCM95906");
12478 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
&&
12479 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57780
)
12480 strcpy(tp
->board_part_number
, "BCM57780");
12481 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
&&
12482 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57760
)
12483 strcpy(tp
->board_part_number
, "BCM57760");
12484 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
&&
12485 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57790
)
12486 strcpy(tp
->board_part_number
, "BCM57790");
12487 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
&&
12488 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57788
)
12489 strcpy(tp
->board_part_number
, "BCM57788");
12490 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
&&
12491 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57761
)
12492 strcpy(tp
->board_part_number
, "BCM57761");
12493 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
&&
12494 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57765
)
12495 strcpy(tp
->board_part_number
, "BCM57765");
12496 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
&&
12497 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57781
)
12498 strcpy(tp
->board_part_number
, "BCM57781");
12499 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
&&
12500 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57785
)
12501 strcpy(tp
->board_part_number
, "BCM57785");
12502 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
&&
12503 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57791
)
12504 strcpy(tp
->board_part_number
, "BCM57791");
12505 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
&&
12506 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57795
)
12507 strcpy(tp
->board_part_number
, "BCM57795");
12509 strcpy(tp
->board_part_number
, "none");
12512 static int __devinit
tg3_fw_img_is_valid(struct tg3
*tp
, u32 offset
)
12516 if (tg3_nvram_read(tp
, offset
, &val
) ||
12517 (val
& 0xfc000000) != 0x0c000000 ||
12518 tg3_nvram_read(tp
, offset
+ 4, &val
) ||
12525 static void __devinit
tg3_read_bc_ver(struct tg3
*tp
)
12527 u32 val
, offset
, start
, ver_offset
;
12529 bool newver
= false;
12531 if (tg3_nvram_read(tp
, 0xc, &offset
) ||
12532 tg3_nvram_read(tp
, 0x4, &start
))
12535 offset
= tg3_nvram_logical_addr(tp
, offset
);
12537 if (tg3_nvram_read(tp
, offset
, &val
))
12540 if ((val
& 0xfc000000) == 0x0c000000) {
12541 if (tg3_nvram_read(tp
, offset
+ 4, &val
))
12548 dst_off
= strlen(tp
->fw_ver
);
12551 if (TG3_VER_SIZE
- dst_off
< 16 ||
12552 tg3_nvram_read(tp
, offset
+ 8, &ver_offset
))
12555 offset
= offset
+ ver_offset
- start
;
12556 for (i
= 0; i
< 16; i
+= 4) {
12558 if (tg3_nvram_read_be32(tp
, offset
+ i
, &v
))
12561 memcpy(tp
->fw_ver
+ dst_off
+ i
, &v
, sizeof(v
));
12566 if (tg3_nvram_read(tp
, TG3_NVM_PTREV_BCVER
, &ver_offset
))
12569 major
= (ver_offset
& TG3_NVM_BCVER_MAJMSK
) >>
12570 TG3_NVM_BCVER_MAJSFT
;
12571 minor
= ver_offset
& TG3_NVM_BCVER_MINMSK
;
12572 snprintf(&tp
->fw_ver
[dst_off
], TG3_VER_SIZE
- dst_off
,
12573 "v%d.%02d", major
, minor
);
12577 static void __devinit
tg3_read_hwsb_ver(struct tg3
*tp
)
12579 u32 val
, major
, minor
;
12581 /* Use native endian representation */
12582 if (tg3_nvram_read(tp
, TG3_NVM_HWSB_CFG1
, &val
))
12585 major
= (val
& TG3_NVM_HWSB_CFG1_MAJMSK
) >>
12586 TG3_NVM_HWSB_CFG1_MAJSFT
;
12587 minor
= (val
& TG3_NVM_HWSB_CFG1_MINMSK
) >>
12588 TG3_NVM_HWSB_CFG1_MINSFT
;
12590 snprintf(&tp
->fw_ver
[0], 32, "sb v%d.%02d", major
, minor
);
12593 static void __devinit
tg3_read_sb_ver(struct tg3
*tp
, u32 val
)
12595 u32 offset
, major
, minor
, build
;
12597 strncat(tp
->fw_ver
, "sb", TG3_VER_SIZE
- strlen(tp
->fw_ver
) - 1);
12599 if ((val
& TG3_EEPROM_SB_FORMAT_MASK
) != TG3_EEPROM_SB_FORMAT_1
)
12602 switch (val
& TG3_EEPROM_SB_REVISION_MASK
) {
12603 case TG3_EEPROM_SB_REVISION_0
:
12604 offset
= TG3_EEPROM_SB_F1R0_EDH_OFF
;
12606 case TG3_EEPROM_SB_REVISION_2
:
12607 offset
= TG3_EEPROM_SB_F1R2_EDH_OFF
;
12609 case TG3_EEPROM_SB_REVISION_3
:
12610 offset
= TG3_EEPROM_SB_F1R3_EDH_OFF
;
12612 case TG3_EEPROM_SB_REVISION_4
:
12613 offset
= TG3_EEPROM_SB_F1R4_EDH_OFF
;
12615 case TG3_EEPROM_SB_REVISION_5
:
12616 offset
= TG3_EEPROM_SB_F1R5_EDH_OFF
;
12622 if (tg3_nvram_read(tp
, offset
, &val
))
12625 build
= (val
& TG3_EEPROM_SB_EDH_BLD_MASK
) >>
12626 TG3_EEPROM_SB_EDH_BLD_SHFT
;
12627 major
= (val
& TG3_EEPROM_SB_EDH_MAJ_MASK
) >>
12628 TG3_EEPROM_SB_EDH_MAJ_SHFT
;
12629 minor
= val
& TG3_EEPROM_SB_EDH_MIN_MASK
;
12631 if (minor
> 99 || build
> 26)
12634 offset
= strlen(tp
->fw_ver
);
12635 snprintf(&tp
->fw_ver
[offset
], TG3_VER_SIZE
- offset
,
12636 " v%d.%02d", major
, minor
);
12639 offset
= strlen(tp
->fw_ver
);
12640 if (offset
< TG3_VER_SIZE
- 1)
12641 tp
->fw_ver
[offset
] = 'a' + build
- 1;
12645 static void __devinit
tg3_read_mgmtfw_ver(struct tg3
*tp
)
12647 u32 val
, offset
, start
;
12650 for (offset
= TG3_NVM_DIR_START
;
12651 offset
< TG3_NVM_DIR_END
;
12652 offset
+= TG3_NVM_DIRENT_SIZE
) {
12653 if (tg3_nvram_read(tp
, offset
, &val
))
12656 if ((val
>> TG3_NVM_DIRTYPE_SHIFT
) == TG3_NVM_DIRTYPE_ASFINI
)
12660 if (offset
== TG3_NVM_DIR_END
)
12663 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
12664 start
= 0x08000000;
12665 else if (tg3_nvram_read(tp
, offset
- 4, &start
))
12668 if (tg3_nvram_read(tp
, offset
+ 4, &offset
) ||
12669 !tg3_fw_img_is_valid(tp
, offset
) ||
12670 tg3_nvram_read(tp
, offset
+ 8, &val
))
12673 offset
+= val
- start
;
12675 vlen
= strlen(tp
->fw_ver
);
12677 tp
->fw_ver
[vlen
++] = ',';
12678 tp
->fw_ver
[vlen
++] = ' ';
12680 for (i
= 0; i
< 4; i
++) {
12682 if (tg3_nvram_read_be32(tp
, offset
, &v
))
12685 offset
+= sizeof(v
);
12687 if (vlen
> TG3_VER_SIZE
- sizeof(v
)) {
12688 memcpy(&tp
->fw_ver
[vlen
], &v
, TG3_VER_SIZE
- vlen
);
12692 memcpy(&tp
->fw_ver
[vlen
], &v
, sizeof(v
));
12697 static void __devinit
tg3_read_dash_ver(struct tg3
*tp
)
12702 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) ||
12703 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
12706 apedata
= tg3_ape_read32(tp
, TG3_APE_SEG_SIG
);
12707 if (apedata
!= APE_SEG_SIG_MAGIC
)
12710 apedata
= tg3_ape_read32(tp
, TG3_APE_FW_STATUS
);
12711 if (!(apedata
& APE_FW_STATUS_READY
))
12714 apedata
= tg3_ape_read32(tp
, TG3_APE_FW_VERSION
);
12716 vlen
= strlen(tp
->fw_ver
);
12718 snprintf(&tp
->fw_ver
[vlen
], TG3_VER_SIZE
- vlen
, " DASH v%d.%d.%d.%d",
12719 (apedata
& APE_FW_VERSION_MAJMSK
) >> APE_FW_VERSION_MAJSFT
,
12720 (apedata
& APE_FW_VERSION_MINMSK
) >> APE_FW_VERSION_MINSFT
,
12721 (apedata
& APE_FW_VERSION_REVMSK
) >> APE_FW_VERSION_REVSFT
,
12722 (apedata
& APE_FW_VERSION_BLDMSK
));
12725 static void __devinit
tg3_read_fw_ver(struct tg3
*tp
)
12728 bool vpd_vers
= false;
12730 if (tp
->fw_ver
[0] != 0)
12733 if (tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) {
12734 strcat(tp
->fw_ver
, "sb");
12738 if (tg3_nvram_read(tp
, 0, &val
))
12741 if (val
== TG3_EEPROM_MAGIC
)
12742 tg3_read_bc_ver(tp
);
12743 else if ((val
& TG3_EEPROM_MAGIC_FW_MSK
) == TG3_EEPROM_MAGIC_FW
)
12744 tg3_read_sb_ver(tp
, val
);
12745 else if ((val
& TG3_EEPROM_MAGIC_HW_MSK
) == TG3_EEPROM_MAGIC_HW
)
12746 tg3_read_hwsb_ver(tp
);
12750 if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) ||
12751 (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) || vpd_vers
)
12754 tg3_read_mgmtfw_ver(tp
);
12757 tp
->fw_ver
[TG3_VER_SIZE
- 1] = 0;
12760 static struct pci_dev
* __devinit
tg3_find_peer(struct tg3
*);
12762 static int __devinit
tg3_get_invariants(struct tg3
*tp
)
12764 static struct pci_device_id write_reorder_chipsets
[] = {
12765 { PCI_DEVICE(PCI_VENDOR_ID_AMD
,
12766 PCI_DEVICE_ID_AMD_FE_GATE_700C
) },
12767 { PCI_DEVICE(PCI_VENDOR_ID_AMD
,
12768 PCI_DEVICE_ID_AMD_8131_BRIDGE
) },
12769 { PCI_DEVICE(PCI_VENDOR_ID_VIA
,
12770 PCI_DEVICE_ID_VIA_8385_0
) },
12774 u32 pci_state_reg
, grc_misc_cfg
;
12779 /* Force memory write invalidate off. If we leave it on,
12780 * then on 5700_BX chips we have to enable a workaround.
12781 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12782 * to match the cacheline size. The Broadcom driver have this
12783 * workaround but turns MWI off all the times so never uses
12784 * it. This seems to suggest that the workaround is insufficient.
12786 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
12787 pci_cmd
&= ~PCI_COMMAND_INVALIDATE
;
12788 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
12790 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12791 * has the register indirect write enable bit set before
12792 * we try to access any of the MMIO registers. It is also
12793 * critical that the PCI-X hw workaround situation is decided
12794 * before that as well.
12796 pci_read_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
12799 tp
->pci_chip_rev_id
= (misc_ctrl_reg
>>
12800 MISC_HOST_CTRL_CHIPREV_SHIFT
);
12801 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_USE_PROD_ID_REG
) {
12802 u32 prod_id_asic_rev
;
12804 if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5717
||
12805 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5718
||
12806 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5724
)
12807 pci_read_config_dword(tp
->pdev
,
12808 TG3PCI_GEN2_PRODID_ASICREV
,
12809 &prod_id_asic_rev
);
12810 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57781
||
12811 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57785
||
12812 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57761
||
12813 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57765
||
12814 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57791
||
12815 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57795
)
12816 pci_read_config_dword(tp
->pdev
,
12817 TG3PCI_GEN15_PRODID_ASICREV
,
12818 &prod_id_asic_rev
);
12820 pci_read_config_dword(tp
->pdev
, TG3PCI_PRODID_ASICREV
,
12821 &prod_id_asic_rev
);
12823 tp
->pci_chip_rev_id
= prod_id_asic_rev
;
12826 /* Wrong chip ID in 5752 A0. This code can be removed later
12827 * as A0 is not in production.
12829 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5752_A0_HW
)
12830 tp
->pci_chip_rev_id
= CHIPREV_ID_5752_A0
;
12832 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12833 * we need to disable memory and use config. cycles
12834 * only to access all registers. The 5702/03 chips
12835 * can mistakenly decode the special cycles from the
12836 * ICH chipsets as memory write cycles, causing corruption
12837 * of register and memory space. Only certain ICH bridges
12838 * will drive special cycles with non-zero data during the
12839 * address phase which can fall within the 5703's address
12840 * range. This is not an ICH bug as the PCI spec allows
12841 * non-zero address during special cycles. However, only
12842 * these ICH bridges are known to drive non-zero addresses
12843 * during special cycles.
12845 * Since special cycles do not cross PCI bridges, we only
12846 * enable this workaround if the 5703 is on the secondary
12847 * bus of these ICH bridges.
12849 if ((tp
->pci_chip_rev_id
== CHIPREV_ID_5703_A1
) ||
12850 (tp
->pci_chip_rev_id
== CHIPREV_ID_5703_A2
)) {
12851 static struct tg3_dev_id
{
12855 } ich_chipsets
[] = {
12856 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AA_8
,
12858 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AB_8
,
12860 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_11
,
12862 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_6
,
12866 struct tg3_dev_id
*pci_id
= &ich_chipsets
[0];
12867 struct pci_dev
*bridge
= NULL
;
12869 while (pci_id
->vendor
!= 0) {
12870 bridge
= pci_get_device(pci_id
->vendor
, pci_id
->device
,
12876 if (pci_id
->rev
!= PCI_ANY_ID
) {
12877 if (bridge
->revision
> pci_id
->rev
)
12880 if (bridge
->subordinate
&&
12881 (bridge
->subordinate
->number
==
12882 tp
->pdev
->bus
->number
)) {
12884 tp
->tg3_flags2
|= TG3_FLG2_ICH_WORKAROUND
;
12885 pci_dev_put(bridge
);
12891 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)) {
12892 static struct tg3_dev_id
{
12895 } bridge_chipsets
[] = {
12896 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_0
},
12897 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_1
},
12900 struct tg3_dev_id
*pci_id
= &bridge_chipsets
[0];
12901 struct pci_dev
*bridge
= NULL
;
12903 while (pci_id
->vendor
!= 0) {
12904 bridge
= pci_get_device(pci_id
->vendor
,
12911 if (bridge
->subordinate
&&
12912 (bridge
->subordinate
->number
<=
12913 tp
->pdev
->bus
->number
) &&
12914 (bridge
->subordinate
->subordinate
>=
12915 tp
->pdev
->bus
->number
)) {
12916 tp
->tg3_flags3
|= TG3_FLG3_5701_DMA_BUG
;
12917 pci_dev_put(bridge
);
12923 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12924 * DMA addresses > 40-bit. This bridge may have other additional
12925 * 57xx devices behind it in some 4-port NIC designs for example.
12926 * Any tg3 device found behind the bridge will also need the 40-bit
12929 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5780
||
12930 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
) {
12931 tp
->tg3_flags2
|= TG3_FLG2_5780_CLASS
;
12932 tp
->tg3_flags
|= TG3_FLAG_40BIT_DMA_BUG
;
12933 tp
->msi_cap
= pci_find_capability(tp
->pdev
, PCI_CAP_ID_MSI
);
12935 struct pci_dev
*bridge
= NULL
;
12938 bridge
= pci_get_device(PCI_VENDOR_ID_SERVERWORKS
,
12939 PCI_DEVICE_ID_SERVERWORKS_EPB
,
12941 if (bridge
&& bridge
->subordinate
&&
12942 (bridge
->subordinate
->number
<=
12943 tp
->pdev
->bus
->number
) &&
12944 (bridge
->subordinate
->subordinate
>=
12945 tp
->pdev
->bus
->number
)) {
12946 tp
->tg3_flags
|= TG3_FLAG_40BIT_DMA_BUG
;
12947 pci_dev_put(bridge
);
12953 /* Initialize misc host control in PCI block. */
12954 tp
->misc_host_ctrl
|= (misc_ctrl_reg
&
12955 MISC_HOST_CTRL_CHIPREV
);
12956 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
12957 tp
->misc_host_ctrl
);
12959 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
12960 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
||
12961 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
)
12962 tp
->pdev_peer
= tg3_find_peer(tp
);
12964 /* Intentionally exclude ASIC_REV_5906 */
12965 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
||
12966 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5787
||
12967 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
12968 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
12969 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
12970 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
||
12971 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
12972 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
12973 tp
->tg3_flags3
|= TG3_FLG3_5755_PLUS
;
12975 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
||
12976 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
||
12977 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
||
12978 (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) ||
12979 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
12980 tp
->tg3_flags2
|= TG3_FLG2_5750_PLUS
;
12982 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) ||
12983 (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
))
12984 tp
->tg3_flags2
|= TG3_FLG2_5705_PLUS
;
12986 /* 5700 B0 chips do not support checksumming correctly due
12987 * to hardware bugs.
12989 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5700_B0
)
12990 tp
->tg3_flags
|= TG3_FLAG_BROKEN_CHECKSUMS
;
12992 tp
->tg3_flags
|= TG3_FLAG_RX_CHECKSUMS
;
12993 tp
->dev
->features
|= NETIF_F_IP_CSUM
| NETIF_F_SG
;
12994 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
12995 tp
->dev
->features
|= NETIF_F_IPV6_CSUM
;
12998 /* Determine TSO capabilities */
12999 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
13000 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
13001 tp
->tg3_flags2
|= TG3_FLG2_HW_TSO_3
;
13002 else if ((tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) ||
13003 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
13004 tp
->tg3_flags2
|= TG3_FLG2_HW_TSO_2
;
13005 else if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) {
13006 tp
->tg3_flags2
|= TG3_FLG2_HW_TSO_1
| TG3_FLG2_TSO_BUG
;
13007 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
&&
13008 tp
->pci_chip_rev_id
>= CHIPREV_ID_5750_C2
)
13009 tp
->tg3_flags2
&= ~TG3_FLG2_TSO_BUG
;
13010 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
13011 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
&&
13012 tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A0
) {
13013 tp
->tg3_flags2
|= TG3_FLG2_TSO_BUG
;
13014 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
)
13015 tp
->fw_needed
= FIRMWARE_TG3TSO5
;
13017 tp
->fw_needed
= FIRMWARE_TG3TSO
;
13022 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) {
13023 tp
->tg3_flags
|= TG3_FLAG_SUPPORT_MSI
;
13024 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_AX
||
13025 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_BX
||
13026 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
&&
13027 tp
->pci_chip_rev_id
<= CHIPREV_ID_5714_A2
&&
13028 tp
->pdev_peer
== tp
->pdev
))
13029 tp
->tg3_flags
&= ~TG3_FLAG_SUPPORT_MSI
;
13031 if ((tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) ||
13032 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
13033 tp
->tg3_flags2
|= TG3_FLG2_1SHOT_MSI
;
13036 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
13037 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
) {
13038 tp
->tg3_flags
|= TG3_FLAG_SUPPORT_MSIX
;
13039 tp
->irq_max
= TG3_IRQ_MAX_VECS
;
13043 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
13044 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
13045 tp
->tg3_flags3
|= TG3_FLG3_SHORT_DMA_BUG
;
13046 else if (!(tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)) {
13047 tp
->tg3_flags3
|= TG3_FLG3_4G_DMA_BNDRY_BUG
;
13048 tp
->tg3_flags3
|= TG3_FLG3_40BIT_DMA_LIMIT_BUG
;
13051 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
13052 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
13053 tp
->tg3_flags3
|= TG3_FLG3_USE_JUMBO_BDFLAG
;
13055 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) ||
13056 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) ||
13057 (tp
->tg3_flags3
& TG3_FLG3_USE_JUMBO_BDFLAG
))
13058 tp
->tg3_flags
|= TG3_FLAG_JUMBO_CAPABLE
;
13060 pci_read_config_dword(tp
->pdev
, TG3PCI_PCISTATE
,
13063 tp
->pcie_cap
= pci_find_capability(tp
->pdev
, PCI_CAP_ID_EXP
);
13064 if (tp
->pcie_cap
!= 0) {
13067 tp
->tg3_flags2
|= TG3_FLG2_PCI_EXPRESS
;
13069 pcie_set_readrq(tp
->pdev
, 4096);
13071 pci_read_config_word(tp
->pdev
,
13072 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
13074 if (lnkctl
& PCI_EXP_LNKCTL_CLKREQ_EN
) {
13075 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
13076 tp
->tg3_flags2
&= ~TG3_FLG2_HW_TSO_2
;
13077 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
13078 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
13079 tp
->pci_chip_rev_id
== CHIPREV_ID_57780_A0
||
13080 tp
->pci_chip_rev_id
== CHIPREV_ID_57780_A1
)
13081 tp
->tg3_flags3
|= TG3_FLG3_CLKREQ_BUG
;
13082 } else if (tp
->pci_chip_rev_id
== CHIPREV_ID_5717_A0
) {
13083 tp
->tg3_flags3
|= TG3_FLG3_L1PLLPD_EN
;
13085 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
) {
13086 tp
->tg3_flags2
|= TG3_FLG2_PCI_EXPRESS
;
13087 } else if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) ||
13088 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
13089 tp
->pcix_cap
= pci_find_capability(tp
->pdev
, PCI_CAP_ID_PCIX
);
13090 if (!tp
->pcix_cap
) {
13091 dev_err(&tp
->pdev
->dev
,
13092 "Cannot find PCI-X capability, aborting\n");
13096 if (!(pci_state_reg
& PCISTATE_CONV_PCI_MODE
))
13097 tp
->tg3_flags
|= TG3_FLAG_PCIX_MODE
;
13100 /* If we have an AMD 762 or VIA K8T800 chipset, write
13101 * reordering to the mailbox registers done by the host
13102 * controller can cause major troubles. We read back from
13103 * every mailbox register write to force the writes to be
13104 * posted to the chip in order.
13106 if (pci_dev_present(write_reorder_chipsets
) &&
13107 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
))
13108 tp
->tg3_flags
|= TG3_FLAG_MBOX_WRITE_REORDER
;
13110 pci_read_config_byte(tp
->pdev
, PCI_CACHE_LINE_SIZE
,
13111 &tp
->pci_cacheline_sz
);
13112 pci_read_config_byte(tp
->pdev
, PCI_LATENCY_TIMER
,
13113 &tp
->pci_lat_timer
);
13114 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
&&
13115 tp
->pci_lat_timer
< 64) {
13116 tp
->pci_lat_timer
= 64;
13117 pci_write_config_byte(tp
->pdev
, PCI_LATENCY_TIMER
,
13118 tp
->pci_lat_timer
);
13121 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5700_BX
) {
13122 /* 5700 BX chips need to have their TX producer index
13123 * mailboxes written twice to workaround a bug.
13125 tp
->tg3_flags
|= TG3_FLAG_TXD_MBOX_HWBUG
;
13127 /* If we are in PCI-X mode, enable register write workaround.
13129 * The workaround is to use indirect register accesses
13130 * for all chip writes not to mailbox registers.
13132 if (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) {
13135 tp
->tg3_flags
|= TG3_FLAG_PCIX_TARGET_HWBUG
;
13137 /* The chip can have it's power management PCI config
13138 * space registers clobbered due to this bug.
13139 * So explicitly force the chip into D0 here.
13141 pci_read_config_dword(tp
->pdev
,
13142 tp
->pm_cap
+ PCI_PM_CTRL
,
13144 pm_reg
&= ~PCI_PM_CTRL_STATE_MASK
;
13145 pm_reg
|= PCI_PM_CTRL_PME_ENABLE
| 0 /* D0 */;
13146 pci_write_config_dword(tp
->pdev
,
13147 tp
->pm_cap
+ PCI_PM_CTRL
,
13150 /* Also, force SERR#/PERR# in PCI command. */
13151 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
13152 pci_cmd
|= PCI_COMMAND_PARITY
| PCI_COMMAND_SERR
;
13153 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
13157 if ((pci_state_reg
& PCISTATE_BUS_SPEED_HIGH
) != 0)
13158 tp
->tg3_flags
|= TG3_FLAG_PCI_HIGH_SPEED
;
13159 if ((pci_state_reg
& PCISTATE_BUS_32BIT
) != 0)
13160 tp
->tg3_flags
|= TG3_FLAG_PCI_32BIT
;
13162 /* Chip-specific fixup from Broadcom driver */
13163 if ((tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
) &&
13164 (!(pci_state_reg
& PCISTATE_RETRY_SAME_DMA
))) {
13165 pci_state_reg
|= PCISTATE_RETRY_SAME_DMA
;
13166 pci_write_config_dword(tp
->pdev
, TG3PCI_PCISTATE
, pci_state_reg
);
13169 /* Default fast path register access methods */
13170 tp
->read32
= tg3_read32
;
13171 tp
->write32
= tg3_write32
;
13172 tp
->read32_mbox
= tg3_read32
;
13173 tp
->write32_mbox
= tg3_write32
;
13174 tp
->write32_tx_mbox
= tg3_write32
;
13175 tp
->write32_rx_mbox
= tg3_write32
;
13177 /* Various workaround register access methods */
13178 if (tp
->tg3_flags
& TG3_FLAG_PCIX_TARGET_HWBUG
)
13179 tp
->write32
= tg3_write_indirect_reg32
;
13180 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
||
13181 ((tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) &&
13182 tp
->pci_chip_rev_id
== CHIPREV_ID_5750_A0
)) {
13184 * Back to back register writes can cause problems on these
13185 * chips, the workaround is to read back all reg writes
13186 * except those to mailbox regs.
13188 * See tg3_write_indirect_reg32().
13190 tp
->write32
= tg3_write_flush_reg32
;
13193 if ((tp
->tg3_flags
& TG3_FLAG_TXD_MBOX_HWBUG
) ||
13194 (tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
)) {
13195 tp
->write32_tx_mbox
= tg3_write32_tx_mbox
;
13196 if (tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
)
13197 tp
->write32_rx_mbox
= tg3_write_flush_reg32
;
13200 if (tp
->tg3_flags2
& TG3_FLG2_ICH_WORKAROUND
) {
13201 tp
->read32
= tg3_read_indirect_reg32
;
13202 tp
->write32
= tg3_write_indirect_reg32
;
13203 tp
->read32_mbox
= tg3_read_indirect_mbox
;
13204 tp
->write32_mbox
= tg3_write_indirect_mbox
;
13205 tp
->write32_tx_mbox
= tg3_write_indirect_mbox
;
13206 tp
->write32_rx_mbox
= tg3_write_indirect_mbox
;
13211 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
13212 pci_cmd
&= ~PCI_COMMAND_MEMORY
;
13213 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
13215 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
13216 tp
->read32_mbox
= tg3_read32_mbox_5906
;
13217 tp
->write32_mbox
= tg3_write32_mbox_5906
;
13218 tp
->write32_tx_mbox
= tg3_write32_mbox_5906
;
13219 tp
->write32_rx_mbox
= tg3_write32_mbox_5906
;
13222 if (tp
->write32
== tg3_write_indirect_reg32
||
13223 ((tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) &&
13224 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
13225 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)))
13226 tp
->tg3_flags
|= TG3_FLAG_SRAM_USE_CONFIG
;
13228 /* Get eeprom hw config before calling tg3_set_power_state().
13229 * In particular, the TG3_FLG2_IS_NIC flag must be
13230 * determined before calling tg3_set_power_state() so that
13231 * we know whether or not to switch out of Vaux power.
13232 * When the flag is set, it means that GPIO1 is used for eeprom
13233 * write protect and also implies that it is a LOM where GPIOs
13234 * are not used to switch power.
13236 tg3_get_eeprom_hw_cfg(tp
);
13238 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
13239 /* Allow reads and writes to the
13240 * APE register and memory space.
13242 pci_state_reg
|= PCISTATE_ALLOW_APE_CTLSPC_WR
|
13243 PCISTATE_ALLOW_APE_SHMEM_WR
;
13244 pci_write_config_dword(tp
->pdev
, TG3PCI_PCISTATE
,
13248 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
13249 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
13250 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
13251 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
||
13252 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
13253 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
13254 tp
->tg3_flags
|= TG3_FLAG_CPMU_PRESENT
;
13256 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13257 * GPIO1 driven high will bring 5700's external PHY out of reset.
13258 * It is also used as eeprom write protect on LOMs.
13260 tp
->grc_local_ctrl
= GRC_LCLCTRL_INT_ON_ATTN
| GRC_LCLCTRL_AUTO_SEEPROM
;
13261 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) ||
13262 (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
))
13263 tp
->grc_local_ctrl
|= (GRC_LCLCTRL_GPIO_OE1
|
13264 GRC_LCLCTRL_GPIO_OUTPUT1
);
13265 /* Unused GPIO3 must be driven as output on 5752 because there
13266 * are no pull-up resistors on unused GPIO pins.
13268 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
)
13269 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE3
;
13271 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
||
13272 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
||
13273 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
13274 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_UART_SEL
;
13276 if (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5761
||
13277 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5761S
) {
13278 /* Turn off the debug UART. */
13279 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_UART_SEL
;
13280 if (tp
->tg3_flags2
& TG3_FLG2_IS_NIC
)
13281 /* Keep VMain power. */
13282 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE0
|
13283 GRC_LCLCTRL_GPIO_OUTPUT0
;
13286 /* Force the chip into D0. */
13287 err
= tg3_set_power_state(tp
, PCI_D0
);
13289 dev_err(&tp
->pdev
->dev
, "Transition to D0 failed\n");
13293 /* Derive initial jumbo mode from MTU assigned in
13294 * ether_setup() via the alloc_etherdev() call
13296 if (tp
->dev
->mtu
> ETH_DATA_LEN
&&
13297 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
13298 tp
->tg3_flags
|= TG3_FLAG_JUMBO_RING_ENABLE
;
13300 /* Determine WakeOnLan speed to use. */
13301 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
13302 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
13303 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
||
13304 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B2
) {
13305 tp
->tg3_flags
&= ~(TG3_FLAG_WOL_SPEED_100MB
);
13307 tp
->tg3_flags
|= TG3_FLAG_WOL_SPEED_100MB
;
13310 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
13311 tp
->tg3_flags3
|= TG3_FLG3_PHY_IS_FET
;
13313 /* A few boards don't want Ethernet@WireSpeed phy feature */
13314 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) ||
13315 ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) &&
13316 (tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A0
) &&
13317 (tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A1
)) ||
13318 (tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
) ||
13319 (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
))
13320 tp
->tg3_flags2
|= TG3_FLG2_NO_ETH_WIRE_SPEED
;
13322 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5703_AX
||
13323 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5704_AX
)
13324 tp
->tg3_flags2
|= TG3_FLG2_PHY_ADC_BUG
;
13325 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
)
13326 tp
->tg3_flags2
|= TG3_FLG2_PHY_5704_A0_BUG
;
13328 if ((tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
13329 !(tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
) &&
13330 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5785
&&
13331 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_57780
&&
13332 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5717
&&
13333 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_57765
) {
13334 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
||
13335 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5787
||
13336 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
13337 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
) {
13338 if (tp
->pdev
->device
!= PCI_DEVICE_ID_TIGON3_5756
&&
13339 tp
->pdev
->device
!= PCI_DEVICE_ID_TIGON3_5722
)
13340 tp
->tg3_flags2
|= TG3_FLG2_PHY_JITTER_BUG
;
13341 if (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5755M
)
13342 tp
->tg3_flags2
|= TG3_FLG2_PHY_ADJUST_TRIM
;
13344 tp
->tg3_flags2
|= TG3_FLG2_PHY_BER_BUG
;
13347 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
13348 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
) {
13349 tp
->phy_otp
= tg3_read_otp_phycfg(tp
);
13350 if (tp
->phy_otp
== 0)
13351 tp
->phy_otp
= TG3_OTP_DEFAULT
;
13354 if (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
)
13355 tp
->mi_mode
= MAC_MI_MODE_500KHZ_CONST
;
13357 tp
->mi_mode
= MAC_MI_MODE_BASE
;
13359 tp
->coalesce_mode
= 0;
13360 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5700_AX
&&
13361 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5700_BX
)
13362 tp
->coalesce_mode
|= HOSTCC_MODE_32BYTE
;
13364 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
13365 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
13366 tp
->tg3_flags3
|= TG3_FLG3_USE_PHYLIB
;
13368 err
= tg3_mdio_init(tp
);
13372 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
&&
13373 (tp
->pci_chip_rev_id
!= CHIPREV_ID_5717_A0
||
13374 (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
)))
13377 /* Initialize data/descriptor byte/word swapping. */
13378 val
= tr32(GRC_MODE
);
13379 val
&= GRC_MODE_HOST_STACKUP
;
13380 tw32(GRC_MODE
, val
| tp
->grc_mode
);
13382 tg3_switch_clocks(tp
);
13384 /* Clear this out for sanity. */
13385 tw32(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
13387 pci_read_config_dword(tp
->pdev
, TG3PCI_PCISTATE
,
13389 if ((pci_state_reg
& PCISTATE_CONV_PCI_MODE
) == 0 &&
13390 (tp
->tg3_flags
& TG3_FLAG_PCIX_TARGET_HWBUG
) == 0) {
13391 u32 chiprevid
= GET_CHIP_REV_ID(tp
->misc_host_ctrl
);
13393 if (chiprevid
== CHIPREV_ID_5701_A0
||
13394 chiprevid
== CHIPREV_ID_5701_B0
||
13395 chiprevid
== CHIPREV_ID_5701_B2
||
13396 chiprevid
== CHIPREV_ID_5701_B5
) {
13397 void __iomem
*sram_base
;
13399 /* Write some dummy words into the SRAM status block
13400 * area, see if it reads back correctly. If the return
13401 * value is bad, force enable the PCIX workaround.
13403 sram_base
= tp
->regs
+ NIC_SRAM_WIN_BASE
+ NIC_SRAM_STATS_BLK
;
13405 writel(0x00000000, sram_base
);
13406 writel(0x00000000, sram_base
+ 4);
13407 writel(0xffffffff, sram_base
+ 4);
13408 if (readl(sram_base
) != 0x00000000)
13409 tp
->tg3_flags
|= TG3_FLAG_PCIX_TARGET_HWBUG
;
13414 tg3_nvram_init(tp
);
13416 grc_misc_cfg
= tr32(GRC_MISC_CFG
);
13417 grc_misc_cfg
&= GRC_MISC_CFG_BOARD_ID_MASK
;
13419 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
13420 (grc_misc_cfg
== GRC_MISC_CFG_BOARD_ID_5788
||
13421 grc_misc_cfg
== GRC_MISC_CFG_BOARD_ID_5788M
))
13422 tp
->tg3_flags2
|= TG3_FLG2_IS_5788
;
13424 if (!(tp
->tg3_flags2
& TG3_FLG2_IS_5788
) &&
13425 (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
))
13426 tp
->tg3_flags
|= TG3_FLAG_TAGGED_STATUS
;
13427 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) {
13428 tp
->coalesce_mode
|= (HOSTCC_MODE_CLRTICK_RXBD
|
13429 HOSTCC_MODE_CLRTICK_TXBD
);
13431 tp
->misc_host_ctrl
|= MISC_HOST_CTRL_TAGGED_STATUS
;
13432 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
13433 tp
->misc_host_ctrl
);
13436 /* Preserve the APE MAC_MODE bits */
13437 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
13438 tp
->mac_mode
= tr32(MAC_MODE
) |
13439 MAC_MODE_APE_TX_EN
| MAC_MODE_APE_RX_EN
;
13441 tp
->mac_mode
= TG3_DEF_MAC_MODE
;
13443 /* these are limited to 10/100 only */
13444 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
&&
13445 (grc_misc_cfg
== 0x8000 || grc_misc_cfg
== 0x4000)) ||
13446 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
13447 tp
->pdev
->vendor
== PCI_VENDOR_ID_BROADCOM
&&
13448 (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5901
||
13449 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5901_2
||
13450 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5705F
)) ||
13451 (tp
->pdev
->vendor
== PCI_VENDOR_ID_BROADCOM
&&
13452 (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5751F
||
13453 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5753F
||
13454 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5787F
)) ||
13455 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57790
||
13456 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57791
||
13457 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57795
||
13458 (tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
))
13459 tp
->tg3_flags
|= TG3_FLAG_10_100_ONLY
;
13461 err
= tg3_phy_probe(tp
);
13463 dev_err(&tp
->pdev
->dev
, "phy probe failed, err %d\n", err
);
13464 /* ... but do not return immediately ... */
13469 tg3_read_fw_ver(tp
);
13471 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
13472 tp
->tg3_flags
&= ~TG3_FLAG_USE_MI_INTERRUPT
;
13474 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
)
13475 tp
->tg3_flags
|= TG3_FLAG_USE_MI_INTERRUPT
;
13477 tp
->tg3_flags
&= ~TG3_FLAG_USE_MI_INTERRUPT
;
13480 /* 5700 {AX,BX} chips have a broken status block link
13481 * change bit implementation, so we must use the
13482 * status register in those cases.
13484 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
)
13485 tp
->tg3_flags
|= TG3_FLAG_USE_LINKCHG_REG
;
13487 tp
->tg3_flags
&= ~TG3_FLAG_USE_LINKCHG_REG
;
13489 /* The led_ctrl is set during tg3_phy_probe, here we might
13490 * have to force the link status polling mechanism based
13491 * upon subsystem IDs.
13493 if (tp
->pdev
->subsystem_vendor
== PCI_VENDOR_ID_DELL
&&
13494 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
&&
13495 !(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)) {
13496 tp
->tg3_flags
|= (TG3_FLAG_USE_MI_INTERRUPT
|
13497 TG3_FLAG_USE_LINKCHG_REG
);
13500 /* For all SERDES we poll the MAC status register. */
13501 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)
13502 tp
->tg3_flags
|= TG3_FLAG_POLL_SERDES
;
13504 tp
->tg3_flags
&= ~TG3_FLAG_POLL_SERDES
;
13506 tp
->rx_offset
= NET_IP_ALIGN
+ TG3_RX_HEADROOM
;
13507 tp
->rx_copy_thresh
= TG3_RX_COPY_THRESHOLD
;
13508 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
&&
13509 (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) != 0) {
13510 tp
->rx_offset
-= NET_IP_ALIGN
;
13511 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
13512 tp
->rx_copy_thresh
= ~(u16
)0;
13516 tp
->rx_std_max_post
= TG3_RX_RING_SIZE
;
13518 /* Increment the rx prod index on the rx std ring by at most
13519 * 8 for these chips to workaround hw errata.
13521 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
||
13522 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
||
13523 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
)
13524 tp
->rx_std_max_post
= 8;
13526 if (tp
->tg3_flags
& TG3_FLAG_ASPM_WORKAROUND
)
13527 tp
->pwrmgmt_thresh
= tr32(PCIE_PWR_MGMT_THRESH
) &
13528 PCIE_PWR_MGMT_L1_THRESH_MSK
;
13533 #ifdef CONFIG_SPARC
13534 static int __devinit
tg3_get_macaddr_sparc(struct tg3
*tp
)
13536 struct net_device
*dev
= tp
->dev
;
13537 struct pci_dev
*pdev
= tp
->pdev
;
13538 struct device_node
*dp
= pci_device_to_OF_node(pdev
);
13539 const unsigned char *addr
;
13542 addr
= of_get_property(dp
, "local-mac-address", &len
);
13543 if (addr
&& len
== 6) {
13544 memcpy(dev
->dev_addr
, addr
, 6);
13545 memcpy(dev
->perm_addr
, dev
->dev_addr
, 6);
13551 static int __devinit
tg3_get_default_macaddr_sparc(struct tg3
*tp
)
13553 struct net_device
*dev
= tp
->dev
;
13555 memcpy(dev
->dev_addr
, idprom
->id_ethaddr
, 6);
13556 memcpy(dev
->perm_addr
, idprom
->id_ethaddr
, 6);
13561 static int __devinit
tg3_get_device_address(struct tg3
*tp
)
13563 struct net_device
*dev
= tp
->dev
;
13564 u32 hi
, lo
, mac_offset
;
13567 #ifdef CONFIG_SPARC
13568 if (!tg3_get_macaddr_sparc(tp
))
13573 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) ||
13574 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
13575 if (tr32(TG3PCI_DUAL_MAC_CTRL
) & DUAL_MAC_CTRL_ID
)
13577 if (tg3_nvram_lock(tp
))
13578 tw32_f(NVRAM_CMD
, NVRAM_CMD_RESET
);
13580 tg3_nvram_unlock(tp
);
13581 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
) {
13582 if (tr32(TG3_CPMU_STATUS
) & TG3_CPMU_STATUS_PCIE_FUNC
)
13584 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
13587 /* First try to get it from MAC address mailbox. */
13588 tg3_read_mem(tp
, NIC_SRAM_MAC_ADDR_HIGH_MBOX
, &hi
);
13589 if ((hi
>> 16) == 0x484b) {
13590 dev
->dev_addr
[0] = (hi
>> 8) & 0xff;
13591 dev
->dev_addr
[1] = (hi
>> 0) & 0xff;
13593 tg3_read_mem(tp
, NIC_SRAM_MAC_ADDR_LOW_MBOX
, &lo
);
13594 dev
->dev_addr
[2] = (lo
>> 24) & 0xff;
13595 dev
->dev_addr
[3] = (lo
>> 16) & 0xff;
13596 dev
->dev_addr
[4] = (lo
>> 8) & 0xff;
13597 dev
->dev_addr
[5] = (lo
>> 0) & 0xff;
13599 /* Some old bootcode may report a 0 MAC address in SRAM */
13600 addr_ok
= is_valid_ether_addr(&dev
->dev_addr
[0]);
13603 /* Next, try NVRAM. */
13604 if (!(tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) &&
13605 !tg3_nvram_read_be32(tp
, mac_offset
+ 0, &hi
) &&
13606 !tg3_nvram_read_be32(tp
, mac_offset
+ 4, &lo
)) {
13607 memcpy(&dev
->dev_addr
[0], ((char *)&hi
) + 2, 2);
13608 memcpy(&dev
->dev_addr
[2], (char *)&lo
, sizeof(lo
));
13610 /* Finally just fetch it out of the MAC control regs. */
13612 hi
= tr32(MAC_ADDR_0_HIGH
);
13613 lo
= tr32(MAC_ADDR_0_LOW
);
13615 dev
->dev_addr
[5] = lo
& 0xff;
13616 dev
->dev_addr
[4] = (lo
>> 8) & 0xff;
13617 dev
->dev_addr
[3] = (lo
>> 16) & 0xff;
13618 dev
->dev_addr
[2] = (lo
>> 24) & 0xff;
13619 dev
->dev_addr
[1] = hi
& 0xff;
13620 dev
->dev_addr
[0] = (hi
>> 8) & 0xff;
13624 if (!is_valid_ether_addr(&dev
->dev_addr
[0])) {
13625 #ifdef CONFIG_SPARC
13626 if (!tg3_get_default_macaddr_sparc(tp
))
13631 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
13635 #define BOUNDARY_SINGLE_CACHELINE 1
13636 #define BOUNDARY_MULTI_CACHELINE 2
13638 static u32 __devinit
tg3_calc_dma_bndry(struct tg3
*tp
, u32 val
)
13640 int cacheline_size
;
13644 pci_read_config_byte(tp
->pdev
, PCI_CACHE_LINE_SIZE
, &byte
);
13646 cacheline_size
= 1024;
13648 cacheline_size
= (int) byte
* 4;
13650 /* On 5703 and later chips, the boundary bits have no
13653 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
13654 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
&&
13655 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
))
13658 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13659 goal
= BOUNDARY_MULTI_CACHELINE
;
13661 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13662 goal
= BOUNDARY_SINGLE_CACHELINE
;
13668 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
13669 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
) {
13670 val
= goal
? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT
;
13677 /* PCI controllers on most RISC systems tend to disconnect
13678 * when a device tries to burst across a cache-line boundary.
13679 * Therefore, letting tg3 do so just wastes PCI bandwidth.
13681 * Unfortunately, for PCI-E there are only limited
13682 * write-side controls for this, and thus for reads
13683 * we will still get the disconnects. We'll also waste
13684 * these PCI cycles for both read and write for chips
13685 * other than 5700 and 5701 which do not implement the
13688 if ((tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) &&
13689 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)) {
13690 switch (cacheline_size
) {
13695 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
13696 val
|= (DMA_RWCTRL_READ_BNDRY_128_PCIX
|
13697 DMA_RWCTRL_WRITE_BNDRY_128_PCIX
);
13699 val
|= (DMA_RWCTRL_READ_BNDRY_384_PCIX
|
13700 DMA_RWCTRL_WRITE_BNDRY_384_PCIX
);
13705 val
|= (DMA_RWCTRL_READ_BNDRY_256_PCIX
|
13706 DMA_RWCTRL_WRITE_BNDRY_256_PCIX
);
13710 val
|= (DMA_RWCTRL_READ_BNDRY_384_PCIX
|
13711 DMA_RWCTRL_WRITE_BNDRY_384_PCIX
);
13714 } else if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
13715 switch (cacheline_size
) {
13719 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
13720 val
&= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE
;
13721 val
|= DMA_RWCTRL_WRITE_BNDRY_64_PCIE
;
13727 val
&= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE
;
13728 val
|= DMA_RWCTRL_WRITE_BNDRY_128_PCIE
;
13732 switch (cacheline_size
) {
13734 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
13735 val
|= (DMA_RWCTRL_READ_BNDRY_16
|
13736 DMA_RWCTRL_WRITE_BNDRY_16
);
13741 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
13742 val
|= (DMA_RWCTRL_READ_BNDRY_32
|
13743 DMA_RWCTRL_WRITE_BNDRY_32
);
13748 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
13749 val
|= (DMA_RWCTRL_READ_BNDRY_64
|
13750 DMA_RWCTRL_WRITE_BNDRY_64
);
13755 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
13756 val
|= (DMA_RWCTRL_READ_BNDRY_128
|
13757 DMA_RWCTRL_WRITE_BNDRY_128
);
13762 val
|= (DMA_RWCTRL_READ_BNDRY_256
|
13763 DMA_RWCTRL_WRITE_BNDRY_256
);
13766 val
|= (DMA_RWCTRL_READ_BNDRY_512
|
13767 DMA_RWCTRL_WRITE_BNDRY_512
);
13771 val
|= (DMA_RWCTRL_READ_BNDRY_1024
|
13772 DMA_RWCTRL_WRITE_BNDRY_1024
);
13781 static int __devinit
tg3_do_test_dma(struct tg3
*tp
, u32
*buf
, dma_addr_t buf_dma
, int size
, int to_device
)
13783 struct tg3_internal_buffer_desc test_desc
;
13784 u32 sram_dma_descs
;
13787 sram_dma_descs
= NIC_SRAM_DMA_DESC_POOL_BASE
;
13789 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ
, 0);
13790 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ
, 0);
13791 tw32(RDMAC_STATUS
, 0);
13792 tw32(WDMAC_STATUS
, 0);
13794 tw32(BUFMGR_MODE
, 0);
13795 tw32(FTQ_RESET
, 0);
13797 test_desc
.addr_hi
= ((u64
) buf_dma
) >> 32;
13798 test_desc
.addr_lo
= buf_dma
& 0xffffffff;
13799 test_desc
.nic_mbuf
= 0x00002100;
13800 test_desc
.len
= size
;
13803 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13804 * the *second* time the tg3 driver was getting loaded after an
13807 * Broadcom tells me:
13808 * ...the DMA engine is connected to the GRC block and a DMA
13809 * reset may affect the GRC block in some unpredictable way...
13810 * The behavior of resets to individual blocks has not been tested.
13812 * Broadcom noted the GRC reset will also reset all sub-components.
13815 test_desc
.cqid_sqid
= (13 << 8) | 2;
13817 tw32_f(RDMAC_MODE
, RDMAC_MODE_ENABLE
);
13820 test_desc
.cqid_sqid
= (16 << 8) | 7;
13822 tw32_f(WDMAC_MODE
, WDMAC_MODE_ENABLE
);
13825 test_desc
.flags
= 0x00000005;
13827 for (i
= 0; i
< (sizeof(test_desc
) / sizeof(u32
)); i
++) {
13830 val
= *(((u32
*)&test_desc
) + i
);
13831 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
,
13832 sram_dma_descs
+ (i
* sizeof(u32
)));
13833 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_DATA
, val
);
13835 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, 0);
13838 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ
, sram_dma_descs
);
13840 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ
, sram_dma_descs
);
13843 for (i
= 0; i
< 40; i
++) {
13847 val
= tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ
);
13849 val
= tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ
);
13850 if ((val
& 0xffff) == sram_dma_descs
) {
13861 #define TEST_BUFFER_SIZE 0x2000
13863 static int __devinit
tg3_test_dma(struct tg3
*tp
)
13865 dma_addr_t buf_dma
;
13866 u32
*buf
, saved_dma_rwctrl
;
13869 buf
= pci_alloc_consistent(tp
->pdev
, TEST_BUFFER_SIZE
, &buf_dma
);
13875 tp
->dma_rwctrl
= ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT
) |
13876 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT
));
13878 tp
->dma_rwctrl
= tg3_calc_dma_bndry(tp
, tp
->dma_rwctrl
);
13880 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
13881 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
13884 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
13885 /* DMA read watermark not used on PCIE */
13886 tp
->dma_rwctrl
|= 0x00180000;
13887 } else if (!(tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
)) {
13888 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
||
13889 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
)
13890 tp
->dma_rwctrl
|= 0x003f0000;
13892 tp
->dma_rwctrl
|= 0x003f000f;
13894 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
13895 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
13896 u32 ccval
= (tr32(TG3PCI_CLOCK_CTRL
) & 0x1f);
13897 u32 read_water
= 0x7;
13899 /* If the 5704 is behind the EPB bridge, we can
13900 * do the less restrictive ONE_DMA workaround for
13901 * better performance.
13903 if ((tp
->tg3_flags
& TG3_FLAG_40BIT_DMA_BUG
) &&
13904 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
)
13905 tp
->dma_rwctrl
|= 0x8000;
13906 else if (ccval
== 0x6 || ccval
== 0x7)
13907 tp
->dma_rwctrl
|= DMA_RWCTRL_ONE_DMA
;
13909 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
)
13911 /* Set bit 23 to enable PCIX hw bug fix */
13913 (read_water
<< DMA_RWCTRL_READ_WATER_SHIFT
) |
13914 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT
) |
13916 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5780
) {
13917 /* 5780 always in PCIX mode */
13918 tp
->dma_rwctrl
|= 0x00144000;
13919 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
) {
13920 /* 5714 always in PCIX mode */
13921 tp
->dma_rwctrl
|= 0x00148000;
13923 tp
->dma_rwctrl
|= 0x001b000f;
13927 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
13928 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
)
13929 tp
->dma_rwctrl
&= 0xfffffff0;
13931 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
13932 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
13933 /* Remove this if it causes problems for some boards. */
13934 tp
->dma_rwctrl
|= DMA_RWCTRL_USE_MEM_READ_MULT
;
13936 /* On 5700/5701 chips, we need to set this bit.
13937 * Otherwise the chip will issue cacheline transactions
13938 * to streamable DMA memory with not all the byte
13939 * enables turned on. This is an error on several
13940 * RISC PCI controllers, in particular sparc64.
13942 * On 5703/5704 chips, this bit has been reassigned
13943 * a different meaning. In particular, it is used
13944 * on those chips to enable a PCI-X workaround.
13946 tp
->dma_rwctrl
|= DMA_RWCTRL_ASSERT_ALL_BE
;
13949 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
13952 /* Unneeded, already done by tg3_get_invariants. */
13953 tg3_switch_clocks(tp
);
13956 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
13957 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
)
13960 /* It is best to perform DMA test with maximum write burst size
13961 * to expose the 5700/5701 write DMA bug.
13963 saved_dma_rwctrl
= tp
->dma_rwctrl
;
13964 tp
->dma_rwctrl
&= ~DMA_RWCTRL_WRITE_BNDRY_MASK
;
13965 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
13970 for (i
= 0; i
< TEST_BUFFER_SIZE
/ sizeof(u32
); i
++)
13973 /* Send the buffer to the chip. */
13974 ret
= tg3_do_test_dma(tp
, buf
, buf_dma
, TEST_BUFFER_SIZE
, 1);
13976 dev_err(&tp
->pdev
->dev
,
13977 "%s: Buffer write failed. err = %d\n",
13983 /* validate data reached card RAM correctly. */
13984 for (i
= 0; i
< TEST_BUFFER_SIZE
/ sizeof(u32
); i
++) {
13986 tg3_read_mem(tp
, 0x2100 + (i
*4), &val
);
13987 if (le32_to_cpu(val
) != p
[i
]) {
13988 dev_err(&tp
->pdev
->dev
,
13989 "%s: Buffer corrupted on device! "
13990 "(%d != %d)\n", __func__
, val
, i
);
13991 /* ret = -ENODEV here? */
13996 /* Now read it back. */
13997 ret
= tg3_do_test_dma(tp
, buf
, buf_dma
, TEST_BUFFER_SIZE
, 0);
13999 dev_err(&tp
->pdev
->dev
, "%s: Buffer read failed. "
14000 "err = %d\n", __func__
, ret
);
14005 for (i
= 0; i
< TEST_BUFFER_SIZE
/ sizeof(u32
); i
++) {
14009 if ((tp
->dma_rwctrl
& DMA_RWCTRL_WRITE_BNDRY_MASK
) !=
14010 DMA_RWCTRL_WRITE_BNDRY_16
) {
14011 tp
->dma_rwctrl
&= ~DMA_RWCTRL_WRITE_BNDRY_MASK
;
14012 tp
->dma_rwctrl
|= DMA_RWCTRL_WRITE_BNDRY_16
;
14013 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
14016 dev_err(&tp
->pdev
->dev
,
14017 "%s: Buffer corrupted on read back! "
14018 "(%d != %d)\n", __func__
, p
[i
], i
);
14024 if (i
== (TEST_BUFFER_SIZE
/ sizeof(u32
))) {
14030 if ((tp
->dma_rwctrl
& DMA_RWCTRL_WRITE_BNDRY_MASK
) !=
14031 DMA_RWCTRL_WRITE_BNDRY_16
) {
14032 static struct pci_device_id dma_wait_state_chipsets
[] = {
14033 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
,
14034 PCI_DEVICE_ID_APPLE_UNI_N_PCI15
) },
14038 /* DMA test passed without adjusting DMA boundary,
14039 * now look for chipsets that are known to expose the
14040 * DMA bug without failing the test.
14042 if (pci_dev_present(dma_wait_state_chipsets
)) {
14043 tp
->dma_rwctrl
&= ~DMA_RWCTRL_WRITE_BNDRY_MASK
;
14044 tp
->dma_rwctrl
|= DMA_RWCTRL_WRITE_BNDRY_16
;
14046 /* Safe to use the calculated DMA boundary. */
14047 tp
->dma_rwctrl
= saved_dma_rwctrl
;
14050 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
14054 pci_free_consistent(tp
->pdev
, TEST_BUFFER_SIZE
, buf
, buf_dma
);
14059 static void __devinit
tg3_init_link_config(struct tg3
*tp
)
14061 tp
->link_config
.advertising
=
14062 (ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
14063 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
|
14064 ADVERTISED_1000baseT_Half
| ADVERTISED_1000baseT_Full
|
14065 ADVERTISED_Autoneg
| ADVERTISED_MII
);
14066 tp
->link_config
.speed
= SPEED_INVALID
;
14067 tp
->link_config
.duplex
= DUPLEX_INVALID
;
14068 tp
->link_config
.autoneg
= AUTONEG_ENABLE
;
14069 tp
->link_config
.active_speed
= SPEED_INVALID
;
14070 tp
->link_config
.active_duplex
= DUPLEX_INVALID
;
14071 tp
->link_config
.phy_is_low_power
= 0;
14072 tp
->link_config
.orig_speed
= SPEED_INVALID
;
14073 tp
->link_config
.orig_duplex
= DUPLEX_INVALID
;
14074 tp
->link_config
.orig_autoneg
= AUTONEG_INVALID
;
14077 static void __devinit
tg3_init_bufmgr_config(struct tg3
*tp
)
14079 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
14080 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
) {
14081 tp
->bufmgr_config
.mbuf_read_dma_low_water
=
14082 DEFAULT_MB_RDMA_LOW_WATER_5705
;
14083 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
14084 DEFAULT_MB_MACRX_LOW_WATER_57765
;
14085 tp
->bufmgr_config
.mbuf_high_water
=
14086 DEFAULT_MB_HIGH_WATER_57765
;
14088 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
=
14089 DEFAULT_MB_RDMA_LOW_WATER_5705
;
14090 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
=
14091 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765
;
14092 tp
->bufmgr_config
.mbuf_high_water_jumbo
=
14093 DEFAULT_MB_HIGH_WATER_JUMBO_57765
;
14094 } else if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
14095 tp
->bufmgr_config
.mbuf_read_dma_low_water
=
14096 DEFAULT_MB_RDMA_LOW_WATER_5705
;
14097 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
14098 DEFAULT_MB_MACRX_LOW_WATER_5705
;
14099 tp
->bufmgr_config
.mbuf_high_water
=
14100 DEFAULT_MB_HIGH_WATER_5705
;
14101 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
14102 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
14103 DEFAULT_MB_MACRX_LOW_WATER_5906
;
14104 tp
->bufmgr_config
.mbuf_high_water
=
14105 DEFAULT_MB_HIGH_WATER_5906
;
14108 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
=
14109 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780
;
14110 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
=
14111 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780
;
14112 tp
->bufmgr_config
.mbuf_high_water_jumbo
=
14113 DEFAULT_MB_HIGH_WATER_JUMBO_5780
;
14115 tp
->bufmgr_config
.mbuf_read_dma_low_water
=
14116 DEFAULT_MB_RDMA_LOW_WATER
;
14117 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
14118 DEFAULT_MB_MACRX_LOW_WATER
;
14119 tp
->bufmgr_config
.mbuf_high_water
=
14120 DEFAULT_MB_HIGH_WATER
;
14122 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
=
14123 DEFAULT_MB_RDMA_LOW_WATER_JUMBO
;
14124 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
=
14125 DEFAULT_MB_MACRX_LOW_WATER_JUMBO
;
14126 tp
->bufmgr_config
.mbuf_high_water_jumbo
=
14127 DEFAULT_MB_HIGH_WATER_JUMBO
;
14130 tp
->bufmgr_config
.dma_low_water
= DEFAULT_DMA_LOW_WATER
;
14131 tp
->bufmgr_config
.dma_high_water
= DEFAULT_DMA_HIGH_WATER
;
14134 static char * __devinit
tg3_phy_string(struct tg3
*tp
)
14136 switch (tp
->phy_id
& TG3_PHY_ID_MASK
) {
14137 case TG3_PHY_ID_BCM5400
: return "5400";
14138 case TG3_PHY_ID_BCM5401
: return "5401";
14139 case TG3_PHY_ID_BCM5411
: return "5411";
14140 case TG3_PHY_ID_BCM5701
: return "5701";
14141 case TG3_PHY_ID_BCM5703
: return "5703";
14142 case TG3_PHY_ID_BCM5704
: return "5704";
14143 case TG3_PHY_ID_BCM5705
: return "5705";
14144 case TG3_PHY_ID_BCM5750
: return "5750";
14145 case TG3_PHY_ID_BCM5752
: return "5752";
14146 case TG3_PHY_ID_BCM5714
: return "5714";
14147 case TG3_PHY_ID_BCM5780
: return "5780";
14148 case TG3_PHY_ID_BCM5755
: return "5755";
14149 case TG3_PHY_ID_BCM5787
: return "5787";
14150 case TG3_PHY_ID_BCM5784
: return "5784";
14151 case TG3_PHY_ID_BCM5756
: return "5722/5756";
14152 case TG3_PHY_ID_BCM5906
: return "5906";
14153 case TG3_PHY_ID_BCM5761
: return "5761";
14154 case TG3_PHY_ID_BCM5718C
: return "5718C";
14155 case TG3_PHY_ID_BCM5718S
: return "5718S";
14156 case TG3_PHY_ID_BCM57765
: return "57765";
14157 case TG3_PHY_ID_BCM8002
: return "8002/serdes";
14158 case 0: return "serdes";
14159 default: return "unknown";
14163 static char * __devinit
tg3_bus_string(struct tg3
*tp
, char *str
)
14165 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
14166 strcpy(str
, "PCI Express");
14168 } else if (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) {
14169 u32 clock_ctrl
= tr32(TG3PCI_CLOCK_CTRL
) & 0x1f;
14171 strcpy(str
, "PCIX:");
14173 if ((clock_ctrl
== 7) ||
14174 ((tr32(GRC_MISC_CFG
) & GRC_MISC_CFG_BOARD_ID_MASK
) ==
14175 GRC_MISC_CFG_BOARD_ID_5704CIOBE
))
14176 strcat(str
, "133MHz");
14177 else if (clock_ctrl
== 0)
14178 strcat(str
, "33MHz");
14179 else if (clock_ctrl
== 2)
14180 strcat(str
, "50MHz");
14181 else if (clock_ctrl
== 4)
14182 strcat(str
, "66MHz");
14183 else if (clock_ctrl
== 6)
14184 strcat(str
, "100MHz");
14186 strcpy(str
, "PCI:");
14187 if (tp
->tg3_flags
& TG3_FLAG_PCI_HIGH_SPEED
)
14188 strcat(str
, "66MHz");
14190 strcat(str
, "33MHz");
14192 if (tp
->tg3_flags
& TG3_FLAG_PCI_32BIT
)
14193 strcat(str
, ":32-bit");
14195 strcat(str
, ":64-bit");
14199 static struct pci_dev
* __devinit
tg3_find_peer(struct tg3
*tp
)
14201 struct pci_dev
*peer
;
14202 unsigned int func
, devnr
= tp
->pdev
->devfn
& ~7;
14204 for (func
= 0; func
< 8; func
++) {
14205 peer
= pci_get_slot(tp
->pdev
->bus
, devnr
| func
);
14206 if (peer
&& peer
!= tp
->pdev
)
14210 /* 5704 can be configured in single-port mode, set peer to
14211 * tp->pdev in that case.
14219 * We don't need to keep the refcount elevated; there's no way
14220 * to remove one half of this device without removing the other
14227 static void __devinit
tg3_init_coal(struct tg3
*tp
)
14229 struct ethtool_coalesce
*ec
= &tp
->coal
;
14231 memset(ec
, 0, sizeof(*ec
));
14232 ec
->cmd
= ETHTOOL_GCOALESCE
;
14233 ec
->rx_coalesce_usecs
= LOW_RXCOL_TICKS
;
14234 ec
->tx_coalesce_usecs
= LOW_TXCOL_TICKS
;
14235 ec
->rx_max_coalesced_frames
= LOW_RXMAX_FRAMES
;
14236 ec
->tx_max_coalesced_frames
= LOW_TXMAX_FRAMES
;
14237 ec
->rx_coalesce_usecs_irq
= DEFAULT_RXCOAL_TICK_INT
;
14238 ec
->tx_coalesce_usecs_irq
= DEFAULT_TXCOAL_TICK_INT
;
14239 ec
->rx_max_coalesced_frames_irq
= DEFAULT_RXCOAL_MAXF_INT
;
14240 ec
->tx_max_coalesced_frames_irq
= DEFAULT_TXCOAL_MAXF_INT
;
14241 ec
->stats_block_coalesce_usecs
= DEFAULT_STAT_COAL_TICKS
;
14243 if (tp
->coalesce_mode
& (HOSTCC_MODE_CLRTICK_RXBD
|
14244 HOSTCC_MODE_CLRTICK_TXBD
)) {
14245 ec
->rx_coalesce_usecs
= LOW_RXCOL_TICKS_CLRTCKS
;
14246 ec
->rx_coalesce_usecs_irq
= DEFAULT_RXCOAL_TICK_INT_CLRTCKS
;
14247 ec
->tx_coalesce_usecs
= LOW_TXCOL_TICKS_CLRTCKS
;
14248 ec
->tx_coalesce_usecs_irq
= DEFAULT_TXCOAL_TICK_INT_CLRTCKS
;
14251 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
14252 ec
->rx_coalesce_usecs_irq
= 0;
14253 ec
->tx_coalesce_usecs_irq
= 0;
14254 ec
->stats_block_coalesce_usecs
= 0;
14258 static const struct net_device_ops tg3_netdev_ops
= {
14259 .ndo_open
= tg3_open
,
14260 .ndo_stop
= tg3_close
,
14261 .ndo_start_xmit
= tg3_start_xmit
,
14262 .ndo_get_stats
= tg3_get_stats
,
14263 .ndo_validate_addr
= eth_validate_addr
,
14264 .ndo_set_multicast_list
= tg3_set_rx_mode
,
14265 .ndo_set_mac_address
= tg3_set_mac_addr
,
14266 .ndo_do_ioctl
= tg3_ioctl
,
14267 .ndo_tx_timeout
= tg3_tx_timeout
,
14268 .ndo_change_mtu
= tg3_change_mtu
,
14269 #if TG3_VLAN_TAG_USED
14270 .ndo_vlan_rx_register
= tg3_vlan_rx_register
,
14272 #ifdef CONFIG_NET_POLL_CONTROLLER
14273 .ndo_poll_controller
= tg3_poll_controller
,
14277 static const struct net_device_ops tg3_netdev_ops_dma_bug
= {
14278 .ndo_open
= tg3_open
,
14279 .ndo_stop
= tg3_close
,
14280 .ndo_start_xmit
= tg3_start_xmit_dma_bug
,
14281 .ndo_get_stats
= tg3_get_stats
,
14282 .ndo_validate_addr
= eth_validate_addr
,
14283 .ndo_set_multicast_list
= tg3_set_rx_mode
,
14284 .ndo_set_mac_address
= tg3_set_mac_addr
,
14285 .ndo_do_ioctl
= tg3_ioctl
,
14286 .ndo_tx_timeout
= tg3_tx_timeout
,
14287 .ndo_change_mtu
= tg3_change_mtu
,
14288 #if TG3_VLAN_TAG_USED
14289 .ndo_vlan_rx_register
= tg3_vlan_rx_register
,
14291 #ifdef CONFIG_NET_POLL_CONTROLLER
14292 .ndo_poll_controller
= tg3_poll_controller
,
14296 static int __devinit
tg3_init_one(struct pci_dev
*pdev
,
14297 const struct pci_device_id
*ent
)
14299 struct net_device
*dev
;
14301 int i
, err
, pm_cap
;
14302 u32 sndmbx
, rcvmbx
, intmbx
;
14304 u64 dma_mask
, persist_dma_mask
;
14306 printk_once(KERN_INFO
"%s\n", version
);
14308 err
= pci_enable_device(pdev
);
14310 dev_err(&pdev
->dev
, "Cannot enable PCI device, aborting\n");
14314 err
= pci_request_regions(pdev
, DRV_MODULE_NAME
);
14316 dev_err(&pdev
->dev
, "Cannot obtain PCI resources, aborting\n");
14317 goto err_out_disable_pdev
;
14320 pci_set_master(pdev
);
14322 /* Find power-management capability. */
14323 pm_cap
= pci_find_capability(pdev
, PCI_CAP_ID_PM
);
14325 dev_err(&pdev
->dev
,
14326 "Cannot find Power Management capability, aborting\n");
14328 goto err_out_free_res
;
14331 dev
= alloc_etherdev_mq(sizeof(*tp
), TG3_IRQ_MAX_VECS
);
14333 dev_err(&pdev
->dev
, "Etherdev alloc failed, aborting\n");
14335 goto err_out_free_res
;
14338 SET_NETDEV_DEV(dev
, &pdev
->dev
);
14340 #if TG3_VLAN_TAG_USED
14341 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
14344 tp
= netdev_priv(dev
);
14347 tp
->pm_cap
= pm_cap
;
14348 tp
->rx_mode
= TG3_DEF_RX_MODE
;
14349 tp
->tx_mode
= TG3_DEF_TX_MODE
;
14352 tp
->msg_enable
= tg3_debug
;
14354 tp
->msg_enable
= TG3_DEF_MSG_ENABLE
;
14356 /* The word/byte swap controls here control register access byte
14357 * swapping. DMA data byte swapping is controlled in the GRC_MODE
14360 tp
->misc_host_ctrl
=
14361 MISC_HOST_CTRL_MASK_PCI_INT
|
14362 MISC_HOST_CTRL_WORD_SWAP
|
14363 MISC_HOST_CTRL_INDIR_ACCESS
|
14364 MISC_HOST_CTRL_PCISTATE_RW
;
14366 /* The NONFRM (non-frame) byte/word swap controls take effect
14367 * on descriptor entries, anything which isn't packet data.
14369 * The StrongARM chips on the board (one for tx, one for rx)
14370 * are running in big-endian mode.
14372 tp
->grc_mode
= (GRC_MODE_WSWAP_DATA
| GRC_MODE_BSWAP_DATA
|
14373 GRC_MODE_WSWAP_NONFRM_DATA
);
14374 #ifdef __BIG_ENDIAN
14375 tp
->grc_mode
|= GRC_MODE_BSWAP_NONFRM_DATA
;
14377 spin_lock_init(&tp
->lock
);
14378 spin_lock_init(&tp
->indirect_lock
);
14379 INIT_WORK(&tp
->reset_task
, tg3_reset_task
);
14381 tp
->regs
= pci_ioremap_bar(pdev
, BAR_0
);
14383 dev_err(&pdev
->dev
, "Cannot map device registers, aborting\n");
14385 goto err_out_free_dev
;
14388 tg3_init_link_config(tp
);
14390 tp
->rx_pending
= TG3_DEF_RX_RING_PENDING
;
14391 tp
->rx_jumbo_pending
= TG3_DEF_RX_JUMBO_RING_PENDING
;
14393 dev
->ethtool_ops
= &tg3_ethtool_ops
;
14394 dev
->watchdog_timeo
= TG3_TX_TIMEOUT
;
14395 dev
->irq
= pdev
->irq
;
14397 err
= tg3_get_invariants(tp
);
14399 dev_err(&pdev
->dev
,
14400 "Problem fetching invariants of chip, aborting\n");
14401 goto err_out_iounmap
;
14404 if ((tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) &&
14405 tp
->pci_chip_rev_id
!= CHIPREV_ID_5717_A0
)
14406 dev
->netdev_ops
= &tg3_netdev_ops
;
14408 dev
->netdev_ops
= &tg3_netdev_ops_dma_bug
;
14411 /* The EPB bridge inside 5714, 5715, and 5780 and any
14412 * device behind the EPB cannot support DMA addresses > 40-bit.
14413 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14414 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14415 * do DMA address check in tg3_start_xmit().
14417 if (tp
->tg3_flags2
& TG3_FLG2_IS_5788
)
14418 persist_dma_mask
= dma_mask
= DMA_BIT_MASK(32);
14419 else if (tp
->tg3_flags
& TG3_FLAG_40BIT_DMA_BUG
) {
14420 persist_dma_mask
= dma_mask
= DMA_BIT_MASK(40);
14421 #ifdef CONFIG_HIGHMEM
14422 dma_mask
= DMA_BIT_MASK(64);
14425 persist_dma_mask
= dma_mask
= DMA_BIT_MASK(64);
14427 /* Configure DMA attributes. */
14428 if (dma_mask
> DMA_BIT_MASK(32)) {
14429 err
= pci_set_dma_mask(pdev
, dma_mask
);
14431 dev
->features
|= NETIF_F_HIGHDMA
;
14432 err
= pci_set_consistent_dma_mask(pdev
,
14435 dev_err(&pdev
->dev
, "Unable to obtain 64 bit "
14436 "DMA for consistent allocations\n");
14437 goto err_out_iounmap
;
14441 if (err
|| dma_mask
== DMA_BIT_MASK(32)) {
14442 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
14444 dev_err(&pdev
->dev
,
14445 "No usable DMA configuration, aborting\n");
14446 goto err_out_iounmap
;
14450 tg3_init_bufmgr_config(tp
);
14452 /* Selectively allow TSO based on operating conditions */
14453 if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO
) ||
14454 (tp
->fw_needed
&& !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)))
14455 tp
->tg3_flags2
|= TG3_FLG2_TSO_CAPABLE
;
14457 tp
->tg3_flags2
&= ~(TG3_FLG2_TSO_CAPABLE
| TG3_FLG2_TSO_BUG
);
14458 tp
->fw_needed
= NULL
;
14461 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
)
14462 tp
->fw_needed
= FIRMWARE_TG3
;
14464 /* TSO is on by default on chips that support hardware TSO.
14465 * Firmware TSO on older chips gives lower performance, so it
14466 * is off by default, but can be enabled using ethtool.
14468 if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO
) &&
14469 (dev
->features
& NETIF_F_IP_CSUM
))
14470 dev
->features
|= NETIF_F_TSO
;
14472 if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO_2
) ||
14473 (tp
->tg3_flags2
& TG3_FLG2_HW_TSO_3
)) {
14474 if (dev
->features
& NETIF_F_IPV6_CSUM
)
14475 dev
->features
|= NETIF_F_TSO6
;
14476 if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO_3
) ||
14477 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
14478 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
14479 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
) ||
14480 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
14481 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
14482 dev
->features
|= NETIF_F_TSO_ECN
;
14485 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A1
&&
14486 !(tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) &&
14487 !(tr32(TG3PCI_PCISTATE
) & PCISTATE_BUS_SPEED_HIGH
)) {
14488 tp
->tg3_flags2
|= TG3_FLG2_MAX_RXPEND_64
;
14489 tp
->rx_pending
= 63;
14492 err
= tg3_get_device_address(tp
);
14494 dev_err(&pdev
->dev
,
14495 "Could not obtain valid ethernet address, aborting\n");
14496 goto err_out_iounmap
;
14499 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
14500 tp
->aperegs
= pci_ioremap_bar(pdev
, BAR_2
);
14501 if (!tp
->aperegs
) {
14502 dev_err(&pdev
->dev
,
14503 "Cannot map APE registers, aborting\n");
14505 goto err_out_iounmap
;
14508 tg3_ape_lock_init(tp
);
14510 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)
14511 tg3_read_dash_ver(tp
);
14515 * Reset chip in case UNDI or EFI driver did not shutdown
14516 * DMA self test will enable WDMAC and we'll see (spurious)
14517 * pending DMA on the PCI bus at that point.
14519 if ((tr32(HOSTCC_MODE
) & HOSTCC_MODE_ENABLE
) ||
14520 (tr32(WDMAC_MODE
) & WDMAC_MODE_ENABLE
)) {
14521 tw32(MEMARB_MODE
, MEMARB_MODE_ENABLE
);
14522 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
14525 err
= tg3_test_dma(tp
);
14527 dev_err(&pdev
->dev
, "DMA engine test failed, aborting\n");
14528 goto err_out_apeunmap
;
14531 /* flow control autonegotiation is default behavior */
14532 tp
->tg3_flags
|= TG3_FLAG_PAUSE_AUTONEG
;
14533 tp
->link_config
.flowctrl
= FLOW_CTRL_TX
| FLOW_CTRL_RX
;
14535 intmbx
= MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
;
14536 rcvmbx
= MAILBOX_RCVRET_CON_IDX_0
+ TG3_64BIT_REG_LOW
;
14537 sndmbx
= MAILBOX_SNDHOST_PROD_IDX_0
+ TG3_64BIT_REG_LOW
;
14538 for (i
= 0; i
< TG3_IRQ_MAX_VECS
; i
++) {
14539 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
14542 tnapi
->tx_pending
= TG3_DEF_TX_RING_PENDING
;
14544 tnapi
->int_mbox
= intmbx
;
14550 tnapi
->consmbox
= rcvmbx
;
14551 tnapi
->prodmbox
= sndmbx
;
14554 tnapi
->coal_now
= HOSTCC_MODE_COAL_VEC1_NOW
<< (i
- 1);
14555 netif_napi_add(dev
, &tnapi
->napi
, tg3_poll_msix
, 64);
14557 tnapi
->coal_now
= HOSTCC_MODE_NOW
;
14558 netif_napi_add(dev
, &tnapi
->napi
, tg3_poll
, 64);
14561 if (!(tp
->tg3_flags
& TG3_FLAG_SUPPORT_MSIX
))
14565 * If we support MSIX, we'll be using RSS. If we're using
14566 * RSS, the first vector only handles link interrupts and the
14567 * remaining vectors handle rx and tx interrupts. Reuse the
14568 * mailbox values for the next iteration. The values we setup
14569 * above are still useful for the single vectored mode.
14584 pci_set_drvdata(pdev
, dev
);
14586 err
= register_netdev(dev
);
14588 dev_err(&pdev
->dev
, "Cannot register net device, aborting\n");
14589 goto err_out_apeunmap
;
14592 netdev_info(dev
, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14593 tp
->board_part_number
,
14594 tp
->pci_chip_rev_id
,
14595 tg3_bus_string(tp
, str
),
14598 if (tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
) {
14599 struct phy_device
*phydev
;
14600 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
14602 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14603 phydev
->drv
->name
, dev_name(&phydev
->dev
));
14605 netdev_info(dev
, "attached PHY is %s (%s Ethernet) "
14606 "(WireSpeed[%d])\n", tg3_phy_string(tp
),
14607 ((tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
) ? "10/100Base-TX" :
14608 ((tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
) ? "1000Base-SX" :
14609 "10/100/1000Base-T")),
14610 (tp
->tg3_flags2
& TG3_FLG2_NO_ETH_WIRE_SPEED
) == 0);
14612 netdev_info(dev
, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14613 (tp
->tg3_flags
& TG3_FLAG_RX_CHECKSUMS
) != 0,
14614 (tp
->tg3_flags
& TG3_FLAG_USE_LINKCHG_REG
) != 0,
14615 (tp
->tg3_flags
& TG3_FLAG_USE_MI_INTERRUPT
) != 0,
14616 (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) != 0,
14617 (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) != 0);
14618 netdev_info(dev
, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14620 pdev
->dma_mask
== DMA_BIT_MASK(32) ? 32 :
14621 ((u64
)pdev
->dma_mask
) == DMA_BIT_MASK(40) ? 40 : 64);
14627 iounmap(tp
->aperegs
);
14628 tp
->aperegs
= NULL
;
14641 pci_release_regions(pdev
);
14643 err_out_disable_pdev
:
14644 pci_disable_device(pdev
);
14645 pci_set_drvdata(pdev
, NULL
);
14649 static void __devexit
tg3_remove_one(struct pci_dev
*pdev
)
14651 struct net_device
*dev
= pci_get_drvdata(pdev
);
14654 struct tg3
*tp
= netdev_priv(dev
);
14657 release_firmware(tp
->fw
);
14659 flush_scheduled_work();
14661 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
14666 unregister_netdev(dev
);
14668 iounmap(tp
->aperegs
);
14669 tp
->aperegs
= NULL
;
14676 pci_release_regions(pdev
);
14677 pci_disable_device(pdev
);
14678 pci_set_drvdata(pdev
, NULL
);
14682 static int tg3_suspend(struct pci_dev
*pdev
, pm_message_t state
)
14684 struct net_device
*dev
= pci_get_drvdata(pdev
);
14685 struct tg3
*tp
= netdev_priv(dev
);
14686 pci_power_t target_state
;
14689 /* PCI register 4 needs to be saved whether netif_running() or not.
14690 * MSI address and data need to be saved if using MSI and
14693 pci_save_state(pdev
);
14695 if (!netif_running(dev
))
14698 flush_scheduled_work();
14700 tg3_netif_stop(tp
);
14702 del_timer_sync(&tp
->timer
);
14704 tg3_full_lock(tp
, 1);
14705 tg3_disable_ints(tp
);
14706 tg3_full_unlock(tp
);
14708 netif_device_detach(dev
);
14710 tg3_full_lock(tp
, 0);
14711 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
14712 tp
->tg3_flags
&= ~TG3_FLAG_INIT_COMPLETE
;
14713 tg3_full_unlock(tp
);
14715 target_state
= pdev
->pm_cap
? pci_target_state(pdev
) : PCI_D3hot
;
14717 err
= tg3_set_power_state(tp
, target_state
);
14721 tg3_full_lock(tp
, 0);
14723 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
14724 err2
= tg3_restart_hw(tp
, 1);
14728 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
14729 add_timer(&tp
->timer
);
14731 netif_device_attach(dev
);
14732 tg3_netif_start(tp
);
14735 tg3_full_unlock(tp
);
14744 static int tg3_resume(struct pci_dev
*pdev
)
14746 struct net_device
*dev
= pci_get_drvdata(pdev
);
14747 struct tg3
*tp
= netdev_priv(dev
);
14750 pci_restore_state(tp
->pdev
);
14752 if (!netif_running(dev
))
14755 err
= tg3_set_power_state(tp
, PCI_D0
);
14759 netif_device_attach(dev
);
14761 tg3_full_lock(tp
, 0);
14763 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
14764 err
= tg3_restart_hw(tp
, 1);
14768 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
14769 add_timer(&tp
->timer
);
14771 tg3_netif_start(tp
);
14774 tg3_full_unlock(tp
);
14782 static struct pci_driver tg3_driver
= {
14783 .name
= DRV_MODULE_NAME
,
14784 .id_table
= tg3_pci_tbl
,
14785 .probe
= tg3_init_one
,
14786 .remove
= __devexit_p(tg3_remove_one
),
14787 .suspend
= tg3_suspend
,
14788 .resume
= tg3_resume
14791 static int __init
tg3_init(void)
14793 return pci_register_driver(&tg3_driver
);
14796 static void __exit
tg3_cleanup(void)
14798 pci_unregister_driver(&tg3_driver
);
14801 module_init(tg3_init
);
14802 module_exit(tg3_cleanup
);