2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2011 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
28 #include <linux/init.h>
29 #include <linux/ioport.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/ethtool.h>
35 #include <linux/mdio.h>
36 #include <linux/mii.h>
37 #include <linux/phy.h>
38 #include <linux/brcmphy.h>
39 #include <linux/if_vlan.h>
41 #include <linux/tcp.h>
42 #include <linux/workqueue.h>
43 #include <linux/prefetch.h>
44 #include <linux/dma-mapping.h>
45 #include <linux/firmware.h>
47 #include <net/checksum.h>
50 #include <asm/system.h>
52 #include <asm/byteorder.h>
53 #include <linux/uaccess.h>
56 #include <asm/idprom.h>
65 #define DRV_MODULE_NAME "tg3"
67 #define TG3_MIN_NUM 117
68 #define DRV_MODULE_VERSION \
69 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
70 #define DRV_MODULE_RELDATE "January 25, 2011"
72 #define TG3_DEF_MAC_MODE 0
73 #define TG3_DEF_RX_MODE 0
74 #define TG3_DEF_TX_MODE 0
75 #define TG3_DEF_MSG_ENABLE \
85 /* length of time before we decide the hardware is borked,
86 * and dev->tx_timeout() should be called to fix the problem
88 #define TG3_TX_TIMEOUT (5 * HZ)
90 /* hardware minimum and maximum for a single frame's data payload */
91 #define TG3_MIN_MTU 60
92 #define TG3_MAX_MTU(tp) \
93 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
95 /* These numbers seem to be hard coded in the NIC firmware somehow.
96 * You can't change the ring sizes, but you can change where you place
97 * them in the NIC onboard memory.
99 #define TG3_RX_STD_RING_SIZE(tp) \
100 ((tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP) ? \
101 TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
102 #define TG3_DEF_RX_RING_PENDING 200
103 #define TG3_RX_JMB_RING_SIZE(tp) \
104 ((tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP) ? \
105 TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
106 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
107 #define TG3_RSS_INDIR_TBL_SIZE 128
109 /* Do not place this n-ring entries value into the tp struct itself,
110 * we really want to expose these constants to GCC so that modulo et
111 * al. operations are done with shifts and masks instead of with
112 * hw multiply/modulo instructions. Another solution would be to
113 * replace things like '% foo' with '& (foo - 1)'.
116 #define TG3_TX_RING_SIZE 512
117 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
119 #define TG3_RX_STD_RING_BYTES(tp) \
120 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
121 #define TG3_RX_JMB_RING_BYTES(tp) \
122 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
123 #define TG3_RX_RCB_RING_BYTES(tp) \
124 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
125 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
127 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
129 #define TG3_DMA_BYTE_ENAB 64
131 #define TG3_RX_STD_DMA_SZ 1536
132 #define TG3_RX_JMB_DMA_SZ 9046
134 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
136 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
137 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
139 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
140 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
142 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
143 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
145 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
146 * that are at least dword aligned when used in PCIX mode. The driver
147 * works around this bug by double copying the packet. This workaround
148 * is built into the normal double copy length check for efficiency.
150 * However, the double copy is only necessary on those architectures
151 * where unaligned memory accesses are inefficient. For those architectures
152 * where unaligned memory accesses incur little penalty, we can reintegrate
153 * the 5701 in the normal rx path. Doing so saves a device structure
154 * dereference by hardcoding the double copy threshold in place.
156 #define TG3_RX_COPY_THRESHOLD 256
157 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
158 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
160 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
163 /* minimum number of free TX descriptors required to wake up TX process */
164 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
166 #define TG3_RAW_IP_ALIGN 2
168 #define TG3_FW_UPDATE_TIMEOUT_SEC 5
170 #define FIRMWARE_TG3 "tigon/tg3.bin"
171 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
172 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
174 static char version
[] __devinitdata
=
175 DRV_MODULE_NAME
".c:v" DRV_MODULE_VERSION
" (" DRV_MODULE_RELDATE
")";
177 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
178 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
179 MODULE_LICENSE("GPL");
180 MODULE_VERSION(DRV_MODULE_VERSION
);
181 MODULE_FIRMWARE(FIRMWARE_TG3
);
182 MODULE_FIRMWARE(FIRMWARE_TG3TSO
);
183 MODULE_FIRMWARE(FIRMWARE_TG3TSO5
);
185 static int tg3_debug
= -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
186 module_param(tg3_debug
, int, 0);
187 MODULE_PARM_DESC(tg3_debug
, "Tigon3 bitmapped debugging message enable value");
189 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl
) = {
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5700
)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5701
)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702
)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5703
)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5704
)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702FE
)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705
)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705_2
)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705M
)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705M_2
)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702X
)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5703X
)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5704S
)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702A3
)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5703A3
)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5782
)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5788
)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5789
)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5901
)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5901_2
)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5704S_2
)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705F
)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5721
)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5722
)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5751
)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5751M
)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5751F
)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5752
)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5752M
)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5753
)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5753M
)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5753F
)},
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5754
)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5754M
)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5755
)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5755M
)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5756
)},
227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5786
)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5787
)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5787M
)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5787F
)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5714
)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5714S
)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5715
)},
234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5715S
)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5780
)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5780S
)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5781
)},
238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5906
)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5906M
)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5784
)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5764
)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5723
)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5761
)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5761E
)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5761S
)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5761SE
)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5785_G
)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5785_F
)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57780
)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57760
)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57790
)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57788
)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5717
)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5718
)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57781
)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57785
)},
257 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57761
)},
258 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57765
)},
259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57791
)},
260 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57795
)},
261 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5719
)},
262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5720
)},
263 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, PCI_DEVICE_ID_SYSKONNECT_9DXX
)},
264 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, PCI_DEVICE_ID_SYSKONNECT_9MXX
)},
265 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC1000
)},
266 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC1001
)},
267 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC1003
)},
268 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC9100
)},
269 {PCI_DEVICE(PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_TIGON3
)},
273 MODULE_DEVICE_TABLE(pci
, tg3_pci_tbl
);
275 static const struct {
276 const char string
[ETH_GSTRING_LEN
];
277 } ethtool_stats_keys
[] = {
280 { "rx_ucast_packets" },
281 { "rx_mcast_packets" },
282 { "rx_bcast_packets" },
284 { "rx_align_errors" },
285 { "rx_xon_pause_rcvd" },
286 { "rx_xoff_pause_rcvd" },
287 { "rx_mac_ctrl_rcvd" },
288 { "rx_xoff_entered" },
289 { "rx_frame_too_long_errors" },
291 { "rx_undersize_packets" },
292 { "rx_in_length_errors" },
293 { "rx_out_length_errors" },
294 { "rx_64_or_less_octet_packets" },
295 { "rx_65_to_127_octet_packets" },
296 { "rx_128_to_255_octet_packets" },
297 { "rx_256_to_511_octet_packets" },
298 { "rx_512_to_1023_octet_packets" },
299 { "rx_1024_to_1522_octet_packets" },
300 { "rx_1523_to_2047_octet_packets" },
301 { "rx_2048_to_4095_octet_packets" },
302 { "rx_4096_to_8191_octet_packets" },
303 { "rx_8192_to_9022_octet_packets" },
310 { "tx_flow_control" },
312 { "tx_single_collisions" },
313 { "tx_mult_collisions" },
315 { "tx_excessive_collisions" },
316 { "tx_late_collisions" },
317 { "tx_collide_2times" },
318 { "tx_collide_3times" },
319 { "tx_collide_4times" },
320 { "tx_collide_5times" },
321 { "tx_collide_6times" },
322 { "tx_collide_7times" },
323 { "tx_collide_8times" },
324 { "tx_collide_9times" },
325 { "tx_collide_10times" },
326 { "tx_collide_11times" },
327 { "tx_collide_12times" },
328 { "tx_collide_13times" },
329 { "tx_collide_14times" },
330 { "tx_collide_15times" },
331 { "tx_ucast_packets" },
332 { "tx_mcast_packets" },
333 { "tx_bcast_packets" },
334 { "tx_carrier_sense_errors" },
338 { "dma_writeq_full" },
339 { "dma_write_prioq_full" },
342 { "mbuf_lwm_thresh_hit" },
344 { "rx_threshold_hit" },
346 { "dma_readq_full" },
347 { "dma_read_prioq_full" },
348 { "tx_comp_queue_full" },
350 { "ring_set_send_prod_index" },
351 { "ring_status_update" },
353 { "nic_avoided_irqs" },
354 { "nic_tx_threshold_hit" }
357 #define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys)
360 static const struct {
361 const char string
[ETH_GSTRING_LEN
];
362 } ethtool_test_keys
[] = {
363 { "nvram test (online) " },
364 { "link test (online) " },
365 { "register test (offline)" },
366 { "memory test (offline)" },
367 { "loopback test (offline)" },
368 { "interrupt test (offline)" },
371 #define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys)
374 static void tg3_write32(struct tg3
*tp
, u32 off
, u32 val
)
376 writel(val
, tp
->regs
+ off
);
379 static u32
tg3_read32(struct tg3
*tp
, u32 off
)
381 return readl(tp
->regs
+ off
);
384 static void tg3_ape_write32(struct tg3
*tp
, u32 off
, u32 val
)
386 writel(val
, tp
->aperegs
+ off
);
389 static u32
tg3_ape_read32(struct tg3
*tp
, u32 off
)
391 return readl(tp
->aperegs
+ off
);
394 static void tg3_write_indirect_reg32(struct tg3
*tp
, u32 off
, u32 val
)
398 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
399 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
);
400 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, val
);
401 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
404 static void tg3_write_flush_reg32(struct tg3
*tp
, u32 off
, u32 val
)
406 writel(val
, tp
->regs
+ off
);
407 readl(tp
->regs
+ off
);
410 static u32
tg3_read_indirect_reg32(struct tg3
*tp
, u32 off
)
415 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
416 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
);
417 pci_read_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, &val
);
418 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
422 static void tg3_write_indirect_mbox(struct tg3
*tp
, u32 off
, u32 val
)
426 if (off
== (MAILBOX_RCVRET_CON_IDX_0
+ TG3_64BIT_REG_LOW
)) {
427 pci_write_config_dword(tp
->pdev
, TG3PCI_RCV_RET_RING_CON_IDX
+
428 TG3_64BIT_REG_LOW
, val
);
431 if (off
== TG3_RX_STD_PROD_IDX_REG
) {
432 pci_write_config_dword(tp
->pdev
, TG3PCI_STD_RING_PROD_IDX
+
433 TG3_64BIT_REG_LOW
, val
);
437 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
438 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
+ 0x5600);
439 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, val
);
440 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
442 /* In indirect mode when disabling interrupts, we also need
443 * to clear the interrupt bit in the GRC local ctrl register.
445 if ((off
== (MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
)) &&
447 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_LOCAL_CTRL
,
448 tp
->grc_local_ctrl
|GRC_LCLCTRL_CLEARINT
);
452 static u32
tg3_read_indirect_mbox(struct tg3
*tp
, u32 off
)
457 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
458 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
+ 0x5600);
459 pci_read_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, &val
);
460 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
464 /* usec_wait specifies the wait time in usec when writing to certain registers
465 * where it is unsafe to read back the register without some delay.
466 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
467 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
469 static void _tw32_flush(struct tg3
*tp
, u32 off
, u32 val
, u32 usec_wait
)
471 if ((tp
->tg3_flags
& TG3_FLAG_PCIX_TARGET_HWBUG
) ||
472 (tp
->tg3_flags2
& TG3_FLG2_ICH_WORKAROUND
))
473 /* Non-posted methods */
474 tp
->write32(tp
, off
, val
);
477 tg3_write32(tp
, off
, val
);
482 /* Wait again after the read for the posted method to guarantee that
483 * the wait time is met.
489 static inline void tw32_mailbox_flush(struct tg3
*tp
, u32 off
, u32 val
)
491 tp
->write32_mbox(tp
, off
, val
);
492 if (!(tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
) &&
493 !(tp
->tg3_flags2
& TG3_FLG2_ICH_WORKAROUND
))
494 tp
->read32_mbox(tp
, off
);
497 static void tg3_write32_tx_mbox(struct tg3
*tp
, u32 off
, u32 val
)
499 void __iomem
*mbox
= tp
->regs
+ off
;
501 if (tp
->tg3_flags
& TG3_FLAG_TXD_MBOX_HWBUG
)
503 if (tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
)
507 static u32
tg3_read32_mbox_5906(struct tg3
*tp
, u32 off
)
509 return readl(tp
->regs
+ off
+ GRCMBOX_BASE
);
512 static void tg3_write32_mbox_5906(struct tg3
*tp
, u32 off
, u32 val
)
514 writel(val
, tp
->regs
+ off
+ GRCMBOX_BASE
);
517 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
518 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
519 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
520 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
521 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
523 #define tw32(reg, val) tp->write32(tp, reg, val)
524 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
525 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
526 #define tr32(reg) tp->read32(tp, reg)
528 static void tg3_write_mem(struct tg3
*tp
, u32 off
, u32 val
)
532 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) &&
533 (off
>= NIC_SRAM_STATS_BLK
) && (off
< NIC_SRAM_TX_BUFFER_DESC
))
536 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
537 if (tp
->tg3_flags
& TG3_FLAG_SRAM_USE_CONFIG
) {
538 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, off
);
539 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_DATA
, val
);
541 /* Always leave this as zero. */
542 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, 0);
544 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, off
);
545 tw32_f(TG3PCI_MEM_WIN_DATA
, val
);
547 /* Always leave this as zero. */
548 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
550 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
553 static void tg3_read_mem(struct tg3
*tp
, u32 off
, u32
*val
)
557 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) &&
558 (off
>= NIC_SRAM_STATS_BLK
) && (off
< NIC_SRAM_TX_BUFFER_DESC
)) {
563 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
564 if (tp
->tg3_flags
& TG3_FLAG_SRAM_USE_CONFIG
) {
565 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, off
);
566 pci_read_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_DATA
, val
);
568 /* Always leave this as zero. */
569 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, 0);
571 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, off
);
572 *val
= tr32(TG3PCI_MEM_WIN_DATA
);
574 /* Always leave this as zero. */
575 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
577 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
580 static void tg3_ape_lock_init(struct tg3
*tp
)
585 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
)
586 regbase
= TG3_APE_LOCK_GRANT
;
588 regbase
= TG3_APE_PER_LOCK_GRANT
;
590 /* Make sure the driver hasn't any stale locks. */
591 for (i
= 0; i
< 8; i
++)
592 tg3_ape_write32(tp
, regbase
+ 4 * i
, APE_LOCK_GRANT_DRIVER
);
595 static int tg3_ape_lock(struct tg3
*tp
, int locknum
)
599 u32 status
, req
, gnt
;
601 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
))
605 case TG3_APE_LOCK_GRC
:
606 case TG3_APE_LOCK_MEM
:
612 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
) {
613 req
= TG3_APE_LOCK_REQ
;
614 gnt
= TG3_APE_LOCK_GRANT
;
616 req
= TG3_APE_PER_LOCK_REQ
;
617 gnt
= TG3_APE_PER_LOCK_GRANT
;
622 tg3_ape_write32(tp
, req
+ off
, APE_LOCK_REQ_DRIVER
);
624 /* Wait for up to 1 millisecond to acquire lock. */
625 for (i
= 0; i
< 100; i
++) {
626 status
= tg3_ape_read32(tp
, gnt
+ off
);
627 if (status
== APE_LOCK_GRANT_DRIVER
)
632 if (status
!= APE_LOCK_GRANT_DRIVER
) {
633 /* Revoke the lock request. */
634 tg3_ape_write32(tp
, gnt
+ off
,
635 APE_LOCK_GRANT_DRIVER
);
643 static void tg3_ape_unlock(struct tg3
*tp
, int locknum
)
647 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
))
651 case TG3_APE_LOCK_GRC
:
652 case TG3_APE_LOCK_MEM
:
658 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
)
659 gnt
= TG3_APE_LOCK_GRANT
;
661 gnt
= TG3_APE_PER_LOCK_GRANT
;
663 tg3_ape_write32(tp
, gnt
+ 4 * locknum
, APE_LOCK_GRANT_DRIVER
);
666 static void tg3_disable_ints(struct tg3
*tp
)
670 tw32(TG3PCI_MISC_HOST_CTRL
,
671 (tp
->misc_host_ctrl
| MISC_HOST_CTRL_MASK_PCI_INT
));
672 for (i
= 0; i
< tp
->irq_max
; i
++)
673 tw32_mailbox_f(tp
->napi
[i
].int_mbox
, 0x00000001);
676 static void tg3_enable_ints(struct tg3
*tp
)
683 tw32(TG3PCI_MISC_HOST_CTRL
,
684 (tp
->misc_host_ctrl
& ~MISC_HOST_CTRL_MASK_PCI_INT
));
686 tp
->coal_now
= tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
;
687 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
688 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
690 tw32_mailbox_f(tnapi
->int_mbox
, tnapi
->last_tag
<< 24);
691 if (tp
->tg3_flags2
& TG3_FLG2_1SHOT_MSI
)
692 tw32_mailbox_f(tnapi
->int_mbox
, tnapi
->last_tag
<< 24);
694 tp
->coal_now
|= tnapi
->coal_now
;
697 /* Force an initial interrupt */
698 if (!(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) &&
699 (tp
->napi
[0].hw_status
->status
& SD_STATUS_UPDATED
))
700 tw32(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
| GRC_LCLCTRL_SETINT
);
702 tw32(HOSTCC_MODE
, tp
->coal_now
);
704 tp
->coal_now
&= ~(tp
->napi
[0].coal_now
| tp
->napi
[1].coal_now
);
707 static inline unsigned int tg3_has_work(struct tg3_napi
*tnapi
)
709 struct tg3
*tp
= tnapi
->tp
;
710 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
711 unsigned int work_exists
= 0;
713 /* check for phy events */
714 if (!(tp
->tg3_flags
&
715 (TG3_FLAG_USE_LINKCHG_REG
|
716 TG3_FLAG_POLL_SERDES
))) {
717 if (sblk
->status
& SD_STATUS_LINK_CHG
)
720 /* check for RX/TX work to do */
721 if (sblk
->idx
[0].tx_consumer
!= tnapi
->tx_cons
||
722 *(tnapi
->rx_rcb_prod_idx
) != tnapi
->rx_rcb_ptr
)
729 * similar to tg3_enable_ints, but it accurately determines whether there
730 * is new work pending and can return without flushing the PIO write
731 * which reenables interrupts
733 static void tg3_int_reenable(struct tg3_napi
*tnapi
)
735 struct tg3
*tp
= tnapi
->tp
;
737 tw32_mailbox(tnapi
->int_mbox
, tnapi
->last_tag
<< 24);
740 /* When doing tagged status, this work check is unnecessary.
741 * The last_tag we write above tells the chip which piece of
742 * work we've completed.
744 if (!(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) &&
746 tw32(HOSTCC_MODE
, tp
->coalesce_mode
|
747 HOSTCC_MODE_ENABLE
| tnapi
->coal_now
);
750 static void tg3_switch_clocks(struct tg3
*tp
)
755 if ((tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) ||
756 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
759 clock_ctrl
= tr32(TG3PCI_CLOCK_CTRL
);
761 orig_clock_ctrl
= clock_ctrl
;
762 clock_ctrl
&= (CLOCK_CTRL_FORCE_CLKRUN
|
763 CLOCK_CTRL_CLKRUN_OENABLE
|
765 tp
->pci_clock_ctrl
= clock_ctrl
;
767 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
768 if (orig_clock_ctrl
& CLOCK_CTRL_625_CORE
) {
769 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
770 clock_ctrl
| CLOCK_CTRL_625_CORE
, 40);
772 } else if ((orig_clock_ctrl
& CLOCK_CTRL_44MHZ_CORE
) != 0) {
773 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
775 (CLOCK_CTRL_44MHZ_CORE
| CLOCK_CTRL_ALTCLK
),
777 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
778 clock_ctrl
| (CLOCK_CTRL_ALTCLK
),
781 tw32_wait_f(TG3PCI_CLOCK_CTRL
, clock_ctrl
, 40);
784 #define PHY_BUSY_LOOPS 5000
786 static int tg3_readphy(struct tg3
*tp
, int reg
, u32
*val
)
792 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
794 (tp
->mi_mode
& ~MAC_MI_MODE_AUTO_POLL
));
800 frame_val
= ((tp
->phy_addr
<< MI_COM_PHY_ADDR_SHIFT
) &
801 MI_COM_PHY_ADDR_MASK
);
802 frame_val
|= ((reg
<< MI_COM_REG_ADDR_SHIFT
) &
803 MI_COM_REG_ADDR_MASK
);
804 frame_val
|= (MI_COM_CMD_READ
| MI_COM_START
);
806 tw32_f(MAC_MI_COM
, frame_val
);
808 loops
= PHY_BUSY_LOOPS
;
811 frame_val
= tr32(MAC_MI_COM
);
813 if ((frame_val
& MI_COM_BUSY
) == 0) {
815 frame_val
= tr32(MAC_MI_COM
);
823 *val
= frame_val
& MI_COM_DATA_MASK
;
827 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
828 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
835 static int tg3_writephy(struct tg3
*tp
, int reg
, u32 val
)
841 if ((tp
->phy_flags
& TG3_PHYFLG_IS_FET
) &&
842 (reg
== MII_TG3_CTRL
|| reg
== MII_TG3_AUX_CTRL
))
845 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
847 (tp
->mi_mode
& ~MAC_MI_MODE_AUTO_POLL
));
851 frame_val
= ((tp
->phy_addr
<< MI_COM_PHY_ADDR_SHIFT
) &
852 MI_COM_PHY_ADDR_MASK
);
853 frame_val
|= ((reg
<< MI_COM_REG_ADDR_SHIFT
) &
854 MI_COM_REG_ADDR_MASK
);
855 frame_val
|= (val
& MI_COM_DATA_MASK
);
856 frame_val
|= (MI_COM_CMD_WRITE
| MI_COM_START
);
858 tw32_f(MAC_MI_COM
, frame_val
);
860 loops
= PHY_BUSY_LOOPS
;
863 frame_val
= tr32(MAC_MI_COM
);
864 if ((frame_val
& MI_COM_BUSY
) == 0) {
866 frame_val
= tr32(MAC_MI_COM
);
876 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
877 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
884 static int tg3_phy_cl45_write(struct tg3
*tp
, u32 devad
, u32 addr
, u32 val
)
888 err
= tg3_writephy(tp
, MII_TG3_MMD_CTRL
, devad
);
892 err
= tg3_writephy(tp
, MII_TG3_MMD_ADDRESS
, addr
);
896 err
= tg3_writephy(tp
, MII_TG3_MMD_CTRL
,
897 MII_TG3_MMD_CTRL_DATA_NOINC
| devad
);
901 err
= tg3_writephy(tp
, MII_TG3_MMD_ADDRESS
, val
);
907 static int tg3_phy_cl45_read(struct tg3
*tp
, u32 devad
, u32 addr
, u32
*val
)
911 err
= tg3_writephy(tp
, MII_TG3_MMD_CTRL
, devad
);
915 err
= tg3_writephy(tp
, MII_TG3_MMD_ADDRESS
, addr
);
919 err
= tg3_writephy(tp
, MII_TG3_MMD_CTRL
,
920 MII_TG3_MMD_CTRL_DATA_NOINC
| devad
);
924 err
= tg3_readphy(tp
, MII_TG3_MMD_ADDRESS
, val
);
930 static int tg3_phydsp_read(struct tg3
*tp
, u32 reg
, u32
*val
)
934 err
= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, reg
);
936 err
= tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, val
);
941 static int tg3_phydsp_write(struct tg3
*tp
, u32 reg
, u32 val
)
945 err
= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, reg
);
947 err
= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, val
);
952 static int tg3_phy_auxctl_read(struct tg3
*tp
, int reg
, u32
*val
)
956 err
= tg3_writephy(tp
, MII_TG3_AUX_CTRL
,
957 (reg
<< MII_TG3_AUXCTL_MISC_RDSEL_SHIFT
) |
958 MII_TG3_AUXCTL_SHDWSEL_MISC
);
960 err
= tg3_readphy(tp
, MII_TG3_AUX_CTRL
, val
);
965 static int tg3_phy_auxctl_write(struct tg3
*tp
, int reg
, u32 set
)
967 if (reg
== MII_TG3_AUXCTL_SHDWSEL_MISC
)
968 set
|= MII_TG3_AUXCTL_MISC_WREN
;
970 return tg3_writephy(tp
, MII_TG3_AUX_CTRL
, set
| reg
);
973 static int tg3_bmcr_reset(struct tg3
*tp
)
978 /* OK, reset it, and poll the BMCR_RESET bit until it
979 * clears or we time out.
981 phy_control
= BMCR_RESET
;
982 err
= tg3_writephy(tp
, MII_BMCR
, phy_control
);
988 err
= tg3_readphy(tp
, MII_BMCR
, &phy_control
);
992 if ((phy_control
& BMCR_RESET
) == 0) {
1004 static int tg3_mdio_read(struct mii_bus
*bp
, int mii_id
, int reg
)
1006 struct tg3
*tp
= bp
->priv
;
1009 spin_lock_bh(&tp
->lock
);
1011 if (tg3_readphy(tp
, reg
, &val
))
1014 spin_unlock_bh(&tp
->lock
);
1019 static int tg3_mdio_write(struct mii_bus
*bp
, int mii_id
, int reg
, u16 val
)
1021 struct tg3
*tp
= bp
->priv
;
1024 spin_lock_bh(&tp
->lock
);
1026 if (tg3_writephy(tp
, reg
, val
))
1029 spin_unlock_bh(&tp
->lock
);
1034 static int tg3_mdio_reset(struct mii_bus
*bp
)
1039 static void tg3_mdio_config_5785(struct tg3
*tp
)
1042 struct phy_device
*phydev
;
1044 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
1045 switch (phydev
->drv
->phy_id
& phydev
->drv
->phy_id_mask
) {
1046 case PHY_ID_BCM50610
:
1047 case PHY_ID_BCM50610M
:
1048 val
= MAC_PHYCFG2_50610_LED_MODES
;
1050 case PHY_ID_BCMAC131
:
1051 val
= MAC_PHYCFG2_AC131_LED_MODES
;
1053 case PHY_ID_RTL8211C
:
1054 val
= MAC_PHYCFG2_RTL8211C_LED_MODES
;
1056 case PHY_ID_RTL8201E
:
1057 val
= MAC_PHYCFG2_RTL8201E_LED_MODES
;
1063 if (phydev
->interface
!= PHY_INTERFACE_MODE_RGMII
) {
1064 tw32(MAC_PHYCFG2
, val
);
1066 val
= tr32(MAC_PHYCFG1
);
1067 val
&= ~(MAC_PHYCFG1_RGMII_INT
|
1068 MAC_PHYCFG1_RXCLK_TO_MASK
| MAC_PHYCFG1_TXCLK_TO_MASK
);
1069 val
|= MAC_PHYCFG1_RXCLK_TIMEOUT
| MAC_PHYCFG1_TXCLK_TIMEOUT
;
1070 tw32(MAC_PHYCFG1
, val
);
1075 if (!(tp
->tg3_flags3
& TG3_FLG3_RGMII_INBAND_DISABLE
))
1076 val
|= MAC_PHYCFG2_EMODE_MASK_MASK
|
1077 MAC_PHYCFG2_FMODE_MASK_MASK
|
1078 MAC_PHYCFG2_GMODE_MASK_MASK
|
1079 MAC_PHYCFG2_ACT_MASK_MASK
|
1080 MAC_PHYCFG2_QUAL_MASK_MASK
|
1081 MAC_PHYCFG2_INBAND_ENABLE
;
1083 tw32(MAC_PHYCFG2
, val
);
1085 val
= tr32(MAC_PHYCFG1
);
1086 val
&= ~(MAC_PHYCFG1_RXCLK_TO_MASK
| MAC_PHYCFG1_TXCLK_TO_MASK
|
1087 MAC_PHYCFG1_RGMII_EXT_RX_DEC
| MAC_PHYCFG1_RGMII_SND_STAT_EN
);
1088 if (!(tp
->tg3_flags3
& TG3_FLG3_RGMII_INBAND_DISABLE
)) {
1089 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_RX_EN
)
1090 val
|= MAC_PHYCFG1_RGMII_EXT_RX_DEC
;
1091 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_TX_EN
)
1092 val
|= MAC_PHYCFG1_RGMII_SND_STAT_EN
;
1094 val
|= MAC_PHYCFG1_RXCLK_TIMEOUT
| MAC_PHYCFG1_TXCLK_TIMEOUT
|
1095 MAC_PHYCFG1_RGMII_INT
| MAC_PHYCFG1_TXC_DRV
;
1096 tw32(MAC_PHYCFG1
, val
);
1098 val
= tr32(MAC_EXT_RGMII_MODE
);
1099 val
&= ~(MAC_RGMII_MODE_RX_INT_B
|
1100 MAC_RGMII_MODE_RX_QUALITY
|
1101 MAC_RGMII_MODE_RX_ACTIVITY
|
1102 MAC_RGMII_MODE_RX_ENG_DET
|
1103 MAC_RGMII_MODE_TX_ENABLE
|
1104 MAC_RGMII_MODE_TX_LOWPWR
|
1105 MAC_RGMII_MODE_TX_RESET
);
1106 if (!(tp
->tg3_flags3
& TG3_FLG3_RGMII_INBAND_DISABLE
)) {
1107 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_RX_EN
)
1108 val
|= MAC_RGMII_MODE_RX_INT_B
|
1109 MAC_RGMII_MODE_RX_QUALITY
|
1110 MAC_RGMII_MODE_RX_ACTIVITY
|
1111 MAC_RGMII_MODE_RX_ENG_DET
;
1112 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_TX_EN
)
1113 val
|= MAC_RGMII_MODE_TX_ENABLE
|
1114 MAC_RGMII_MODE_TX_LOWPWR
|
1115 MAC_RGMII_MODE_TX_RESET
;
1117 tw32(MAC_EXT_RGMII_MODE
, val
);
1120 static void tg3_mdio_start(struct tg3
*tp
)
1122 tp
->mi_mode
&= ~MAC_MI_MODE_AUTO_POLL
;
1123 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
1126 if ((tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_INITED
) &&
1127 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
1128 tg3_mdio_config_5785(tp
);
1131 static int tg3_mdio_init(struct tg3
*tp
)
1135 struct phy_device
*phydev
;
1137 if (tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
) {
1140 tp
->phy_addr
= PCI_FUNC(tp
->pdev
->devfn
) + 1;
1142 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5717_A0
)
1143 is_serdes
= tr32(SG_DIG_STATUS
) & SG_DIG_IS_SERDES
;
1145 is_serdes
= tr32(TG3_CPMU_PHY_STRAP
) &
1146 TG3_CPMU_PHY_STRAP_IS_SERDES
;
1150 tp
->phy_addr
= TG3_PHY_MII_ADDR
;
1154 if (!(tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) ||
1155 (tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_INITED
))
1158 tp
->mdio_bus
= mdiobus_alloc();
1159 if (tp
->mdio_bus
== NULL
)
1162 tp
->mdio_bus
->name
= "tg3 mdio bus";
1163 snprintf(tp
->mdio_bus
->id
, MII_BUS_ID_SIZE
, "%x",
1164 (tp
->pdev
->bus
->number
<< 8) | tp
->pdev
->devfn
);
1165 tp
->mdio_bus
->priv
= tp
;
1166 tp
->mdio_bus
->parent
= &tp
->pdev
->dev
;
1167 tp
->mdio_bus
->read
= &tg3_mdio_read
;
1168 tp
->mdio_bus
->write
= &tg3_mdio_write
;
1169 tp
->mdio_bus
->reset
= &tg3_mdio_reset
;
1170 tp
->mdio_bus
->phy_mask
= ~(1 << TG3_PHY_MII_ADDR
);
1171 tp
->mdio_bus
->irq
= &tp
->mdio_irq
[0];
1173 for (i
= 0; i
< PHY_MAX_ADDR
; i
++)
1174 tp
->mdio_bus
->irq
[i
] = PHY_POLL
;
1176 /* The bus registration will look for all the PHYs on the mdio bus.
1177 * Unfortunately, it does not ensure the PHY is powered up before
1178 * accessing the PHY ID registers. A chip reset is the
1179 * quickest way to bring the device back to an operational state..
1181 if (tg3_readphy(tp
, MII_BMCR
, ®
) || (reg
& BMCR_PDOWN
))
1184 i
= mdiobus_register(tp
->mdio_bus
);
1186 dev_warn(&tp
->pdev
->dev
, "mdiobus_reg failed (0x%x)\n", i
);
1187 mdiobus_free(tp
->mdio_bus
);
1191 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
1193 if (!phydev
|| !phydev
->drv
) {
1194 dev_warn(&tp
->pdev
->dev
, "No PHY devices\n");
1195 mdiobus_unregister(tp
->mdio_bus
);
1196 mdiobus_free(tp
->mdio_bus
);
1200 switch (phydev
->drv
->phy_id
& phydev
->drv
->phy_id_mask
) {
1201 case PHY_ID_BCM57780
:
1202 phydev
->interface
= PHY_INTERFACE_MODE_GMII
;
1203 phydev
->dev_flags
|= PHY_BRCM_AUTO_PWRDWN_ENABLE
;
1205 case PHY_ID_BCM50610
:
1206 case PHY_ID_BCM50610M
:
1207 phydev
->dev_flags
|= PHY_BRCM_CLEAR_RGMII_MODE
|
1208 PHY_BRCM_RX_REFCLK_UNUSED
|
1209 PHY_BRCM_DIS_TXCRXC_NOENRGY
|
1210 PHY_BRCM_AUTO_PWRDWN_ENABLE
;
1211 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_INBAND_DISABLE
)
1212 phydev
->dev_flags
|= PHY_BRCM_STD_IBND_DISABLE
;
1213 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_RX_EN
)
1214 phydev
->dev_flags
|= PHY_BRCM_EXT_IBND_RX_ENABLE
;
1215 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_TX_EN
)
1216 phydev
->dev_flags
|= PHY_BRCM_EXT_IBND_TX_ENABLE
;
1218 case PHY_ID_RTL8211C
:
1219 phydev
->interface
= PHY_INTERFACE_MODE_RGMII
;
1221 case PHY_ID_RTL8201E
:
1222 case PHY_ID_BCMAC131
:
1223 phydev
->interface
= PHY_INTERFACE_MODE_MII
;
1224 phydev
->dev_flags
|= PHY_BRCM_AUTO_PWRDWN_ENABLE
;
1225 tp
->phy_flags
|= TG3_PHYFLG_IS_FET
;
1229 tp
->tg3_flags3
|= TG3_FLG3_MDIOBUS_INITED
;
1231 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
1232 tg3_mdio_config_5785(tp
);
1237 static void tg3_mdio_fini(struct tg3
*tp
)
1239 if (tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_INITED
) {
1240 tp
->tg3_flags3
&= ~TG3_FLG3_MDIOBUS_INITED
;
1241 mdiobus_unregister(tp
->mdio_bus
);
1242 mdiobus_free(tp
->mdio_bus
);
1246 /* tp->lock is held. */
1247 static inline void tg3_generate_fw_event(struct tg3
*tp
)
1251 val
= tr32(GRC_RX_CPU_EVENT
);
1252 val
|= GRC_RX_CPU_DRIVER_EVENT
;
1253 tw32_f(GRC_RX_CPU_EVENT
, val
);
1255 tp
->last_event_jiffies
= jiffies
;
1258 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1260 /* tp->lock is held. */
1261 static void tg3_wait_for_event_ack(struct tg3
*tp
)
1264 unsigned int delay_cnt
;
1267 /* If enough time has passed, no wait is necessary. */
1268 time_remain
= (long)(tp
->last_event_jiffies
+ 1 +
1269 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC
)) -
1271 if (time_remain
< 0)
1274 /* Check if we can shorten the wait time. */
1275 delay_cnt
= jiffies_to_usecs(time_remain
);
1276 if (delay_cnt
> TG3_FW_EVENT_TIMEOUT_USEC
)
1277 delay_cnt
= TG3_FW_EVENT_TIMEOUT_USEC
;
1278 delay_cnt
= (delay_cnt
>> 3) + 1;
1280 for (i
= 0; i
< delay_cnt
; i
++) {
1281 if (!(tr32(GRC_RX_CPU_EVENT
) & GRC_RX_CPU_DRIVER_EVENT
))
1287 /* tp->lock is held. */
1288 static void tg3_ump_link_report(struct tg3
*tp
)
1293 if (!(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) ||
1294 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
1297 tg3_wait_for_event_ack(tp
);
1299 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_MBOX
, FWCMD_NICDRV_LINK_UPDATE
);
1301 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_LEN_MBOX
, 14);
1304 if (!tg3_readphy(tp
, MII_BMCR
, ®
))
1306 if (!tg3_readphy(tp
, MII_BMSR
, ®
))
1307 val
|= (reg
& 0xffff);
1308 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
, val
);
1311 if (!tg3_readphy(tp
, MII_ADVERTISE
, ®
))
1313 if (!tg3_readphy(tp
, MII_LPA
, ®
))
1314 val
|= (reg
& 0xffff);
1315 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
+ 4, val
);
1318 if (!(tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
)) {
1319 if (!tg3_readphy(tp
, MII_CTRL1000
, ®
))
1321 if (!tg3_readphy(tp
, MII_STAT1000
, ®
))
1322 val
|= (reg
& 0xffff);
1324 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
+ 8, val
);
1326 if (!tg3_readphy(tp
, MII_PHYADDR
, ®
))
1330 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
+ 12, val
);
1332 tg3_generate_fw_event(tp
);
1335 static void tg3_link_report(struct tg3
*tp
)
1337 if (!netif_carrier_ok(tp
->dev
)) {
1338 netif_info(tp
, link
, tp
->dev
, "Link is down\n");
1339 tg3_ump_link_report(tp
);
1340 } else if (netif_msg_link(tp
)) {
1341 netdev_info(tp
->dev
, "Link is up at %d Mbps, %s duplex\n",
1342 (tp
->link_config
.active_speed
== SPEED_1000
?
1344 (tp
->link_config
.active_speed
== SPEED_100
?
1346 (tp
->link_config
.active_duplex
== DUPLEX_FULL
?
1349 netdev_info(tp
->dev
, "Flow control is %s for TX and %s for RX\n",
1350 (tp
->link_config
.active_flowctrl
& FLOW_CTRL_TX
) ?
1352 (tp
->link_config
.active_flowctrl
& FLOW_CTRL_RX
) ?
1354 tg3_ump_link_report(tp
);
1358 static u16
tg3_advert_flowctrl_1000T(u8 flow_ctrl
)
1362 if ((flow_ctrl
& FLOW_CTRL_TX
) && (flow_ctrl
& FLOW_CTRL_RX
))
1363 miireg
= ADVERTISE_PAUSE_CAP
;
1364 else if (flow_ctrl
& FLOW_CTRL_TX
)
1365 miireg
= ADVERTISE_PAUSE_ASYM
;
1366 else if (flow_ctrl
& FLOW_CTRL_RX
)
1367 miireg
= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
1374 static u16
tg3_advert_flowctrl_1000X(u8 flow_ctrl
)
1378 if ((flow_ctrl
& FLOW_CTRL_TX
) && (flow_ctrl
& FLOW_CTRL_RX
))
1379 miireg
= ADVERTISE_1000XPAUSE
;
1380 else if (flow_ctrl
& FLOW_CTRL_TX
)
1381 miireg
= ADVERTISE_1000XPSE_ASYM
;
1382 else if (flow_ctrl
& FLOW_CTRL_RX
)
1383 miireg
= ADVERTISE_1000XPAUSE
| ADVERTISE_1000XPSE_ASYM
;
1390 static u8
tg3_resolve_flowctrl_1000X(u16 lcladv
, u16 rmtadv
)
1394 if (lcladv
& ADVERTISE_1000XPAUSE
) {
1395 if (lcladv
& ADVERTISE_1000XPSE_ASYM
) {
1396 if (rmtadv
& LPA_1000XPAUSE
)
1397 cap
= FLOW_CTRL_TX
| FLOW_CTRL_RX
;
1398 else if (rmtadv
& LPA_1000XPAUSE_ASYM
)
1401 if (rmtadv
& LPA_1000XPAUSE
)
1402 cap
= FLOW_CTRL_TX
| FLOW_CTRL_RX
;
1404 } else if (lcladv
& ADVERTISE_1000XPSE_ASYM
) {
1405 if ((rmtadv
& LPA_1000XPAUSE
) && (rmtadv
& LPA_1000XPAUSE_ASYM
))
1412 static void tg3_setup_flow_control(struct tg3
*tp
, u32 lcladv
, u32 rmtadv
)
1416 u32 old_rx_mode
= tp
->rx_mode
;
1417 u32 old_tx_mode
= tp
->tx_mode
;
1419 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
)
1420 autoneg
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
]->autoneg
;
1422 autoneg
= tp
->link_config
.autoneg
;
1424 if (autoneg
== AUTONEG_ENABLE
&&
1425 (tp
->tg3_flags
& TG3_FLAG_PAUSE_AUTONEG
)) {
1426 if (tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
)
1427 flowctrl
= tg3_resolve_flowctrl_1000X(lcladv
, rmtadv
);
1429 flowctrl
= mii_resolve_flowctrl_fdx(lcladv
, rmtadv
);
1431 flowctrl
= tp
->link_config
.flowctrl
;
1433 tp
->link_config
.active_flowctrl
= flowctrl
;
1435 if (flowctrl
& FLOW_CTRL_RX
)
1436 tp
->rx_mode
|= RX_MODE_FLOW_CTRL_ENABLE
;
1438 tp
->rx_mode
&= ~RX_MODE_FLOW_CTRL_ENABLE
;
1440 if (old_rx_mode
!= tp
->rx_mode
)
1441 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
1443 if (flowctrl
& FLOW_CTRL_TX
)
1444 tp
->tx_mode
|= TX_MODE_FLOW_CTRL_ENABLE
;
1446 tp
->tx_mode
&= ~TX_MODE_FLOW_CTRL_ENABLE
;
1448 if (old_tx_mode
!= tp
->tx_mode
)
1449 tw32_f(MAC_TX_MODE
, tp
->tx_mode
);
1452 static void tg3_adjust_link(struct net_device
*dev
)
1454 u8 oldflowctrl
, linkmesg
= 0;
1455 u32 mac_mode
, lcl_adv
, rmt_adv
;
1456 struct tg3
*tp
= netdev_priv(dev
);
1457 struct phy_device
*phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
1459 spin_lock_bh(&tp
->lock
);
1461 mac_mode
= tp
->mac_mode
& ~(MAC_MODE_PORT_MODE_MASK
|
1462 MAC_MODE_HALF_DUPLEX
);
1464 oldflowctrl
= tp
->link_config
.active_flowctrl
;
1470 if (phydev
->speed
== SPEED_100
|| phydev
->speed
== SPEED_10
)
1471 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
1472 else if (phydev
->speed
== SPEED_1000
||
1473 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5785
)
1474 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
1476 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
1478 if (phydev
->duplex
== DUPLEX_HALF
)
1479 mac_mode
|= MAC_MODE_HALF_DUPLEX
;
1481 lcl_adv
= tg3_advert_flowctrl_1000T(
1482 tp
->link_config
.flowctrl
);
1485 rmt_adv
= LPA_PAUSE_CAP
;
1486 if (phydev
->asym_pause
)
1487 rmt_adv
|= LPA_PAUSE_ASYM
;
1490 tg3_setup_flow_control(tp
, lcl_adv
, rmt_adv
);
1492 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
1494 if (mac_mode
!= tp
->mac_mode
) {
1495 tp
->mac_mode
= mac_mode
;
1496 tw32_f(MAC_MODE
, tp
->mac_mode
);
1500 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
) {
1501 if (phydev
->speed
== SPEED_10
)
1503 MAC_MI_STAT_10MBPS_MODE
|
1504 MAC_MI_STAT_LNKSTAT_ATTN_ENAB
);
1506 tw32(MAC_MI_STAT
, MAC_MI_STAT_LNKSTAT_ATTN_ENAB
);
1509 if (phydev
->speed
== SPEED_1000
&& phydev
->duplex
== DUPLEX_HALF
)
1510 tw32(MAC_TX_LENGTHS
,
1511 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
1512 (6 << TX_LENGTHS_IPG_SHIFT
) |
1513 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT
)));
1515 tw32(MAC_TX_LENGTHS
,
1516 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
1517 (6 << TX_LENGTHS_IPG_SHIFT
) |
1518 (32 << TX_LENGTHS_SLOT_TIME_SHIFT
)));
1520 if ((phydev
->link
&& tp
->link_config
.active_speed
== SPEED_INVALID
) ||
1521 (!phydev
->link
&& tp
->link_config
.active_speed
!= SPEED_INVALID
) ||
1522 phydev
->speed
!= tp
->link_config
.active_speed
||
1523 phydev
->duplex
!= tp
->link_config
.active_duplex
||
1524 oldflowctrl
!= tp
->link_config
.active_flowctrl
)
1527 tp
->link_config
.active_speed
= phydev
->speed
;
1528 tp
->link_config
.active_duplex
= phydev
->duplex
;
1530 spin_unlock_bh(&tp
->lock
);
1533 tg3_link_report(tp
);
1536 static int tg3_phy_init(struct tg3
*tp
)
1538 struct phy_device
*phydev
;
1540 if (tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
)
1543 /* Bring the PHY back to a known state. */
1546 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
1548 /* Attach the MAC to the PHY. */
1549 phydev
= phy_connect(tp
->dev
, dev_name(&phydev
->dev
), tg3_adjust_link
,
1550 phydev
->dev_flags
, phydev
->interface
);
1551 if (IS_ERR(phydev
)) {
1552 dev_err(&tp
->pdev
->dev
, "Could not attach to PHY\n");
1553 return PTR_ERR(phydev
);
1556 /* Mask with MAC supported features. */
1557 switch (phydev
->interface
) {
1558 case PHY_INTERFACE_MODE_GMII
:
1559 case PHY_INTERFACE_MODE_RGMII
:
1560 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
)) {
1561 phydev
->supported
&= (PHY_GBIT_FEATURES
|
1563 SUPPORTED_Asym_Pause
);
1567 case PHY_INTERFACE_MODE_MII
:
1568 phydev
->supported
&= (PHY_BASIC_FEATURES
|
1570 SUPPORTED_Asym_Pause
);
1573 phy_disconnect(tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
]);
1577 tp
->phy_flags
|= TG3_PHYFLG_IS_CONNECTED
;
1579 phydev
->advertising
= phydev
->supported
;
1584 static void tg3_phy_start(struct tg3
*tp
)
1586 struct phy_device
*phydev
;
1588 if (!(tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
))
1591 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
1593 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
) {
1594 tp
->phy_flags
&= ~TG3_PHYFLG_IS_LOW_POWER
;
1595 phydev
->speed
= tp
->link_config
.orig_speed
;
1596 phydev
->duplex
= tp
->link_config
.orig_duplex
;
1597 phydev
->autoneg
= tp
->link_config
.orig_autoneg
;
1598 phydev
->advertising
= tp
->link_config
.orig_advertising
;
1603 phy_start_aneg(phydev
);
1606 static void tg3_phy_stop(struct tg3
*tp
)
1608 if (!(tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
))
1611 phy_stop(tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
]);
1614 static void tg3_phy_fini(struct tg3
*tp
)
1616 if (tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
) {
1617 phy_disconnect(tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
]);
1618 tp
->phy_flags
&= ~TG3_PHYFLG_IS_CONNECTED
;
1622 static void tg3_phy_fet_toggle_apd(struct tg3
*tp
, bool enable
)
1626 if (!tg3_readphy(tp
, MII_TG3_FET_TEST
, &phytest
)) {
1629 tg3_writephy(tp
, MII_TG3_FET_TEST
,
1630 phytest
| MII_TG3_FET_SHADOW_EN
);
1631 if (!tg3_readphy(tp
, MII_TG3_FET_SHDW_AUXSTAT2
, &phy
)) {
1633 phy
|= MII_TG3_FET_SHDW_AUXSTAT2_APD
;
1635 phy
&= ~MII_TG3_FET_SHDW_AUXSTAT2_APD
;
1636 tg3_writephy(tp
, MII_TG3_FET_SHDW_AUXSTAT2
, phy
);
1638 tg3_writephy(tp
, MII_TG3_FET_TEST
, phytest
);
1642 static void tg3_phy_toggle_apd(struct tg3
*tp
, bool enable
)
1646 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) ||
1647 ((tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
) &&
1648 (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
)))
1651 if (tp
->phy_flags
& TG3_PHYFLG_IS_FET
) {
1652 tg3_phy_fet_toggle_apd(tp
, enable
);
1656 reg
= MII_TG3_MISC_SHDW_WREN
|
1657 MII_TG3_MISC_SHDW_SCR5_SEL
|
1658 MII_TG3_MISC_SHDW_SCR5_LPED
|
1659 MII_TG3_MISC_SHDW_SCR5_DLPTLM
|
1660 MII_TG3_MISC_SHDW_SCR5_SDTL
|
1661 MII_TG3_MISC_SHDW_SCR5_C125OE
;
1662 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5784
|| !enable
)
1663 reg
|= MII_TG3_MISC_SHDW_SCR5_DLLAPD
;
1665 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, reg
);
1668 reg
= MII_TG3_MISC_SHDW_WREN
|
1669 MII_TG3_MISC_SHDW_APD_SEL
|
1670 MII_TG3_MISC_SHDW_APD_WKTM_84MS
;
1672 reg
|= MII_TG3_MISC_SHDW_APD_ENABLE
;
1674 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, reg
);
1677 static void tg3_phy_toggle_automdix(struct tg3
*tp
, int enable
)
1681 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) ||
1682 (tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
))
1685 if (tp
->phy_flags
& TG3_PHYFLG_IS_FET
) {
1688 if (!tg3_readphy(tp
, MII_TG3_FET_TEST
, &ephy
)) {
1689 u32 reg
= MII_TG3_FET_SHDW_MISCCTRL
;
1691 tg3_writephy(tp
, MII_TG3_FET_TEST
,
1692 ephy
| MII_TG3_FET_SHADOW_EN
);
1693 if (!tg3_readphy(tp
, reg
, &phy
)) {
1695 phy
|= MII_TG3_FET_SHDW_MISCCTRL_MDIX
;
1697 phy
&= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX
;
1698 tg3_writephy(tp
, reg
, phy
);
1700 tg3_writephy(tp
, MII_TG3_FET_TEST
, ephy
);
1705 ret
= tg3_phy_auxctl_read(tp
,
1706 MII_TG3_AUXCTL_SHDWSEL_MISC
, &phy
);
1709 phy
|= MII_TG3_AUXCTL_MISC_FORCE_AMDIX
;
1711 phy
&= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX
;
1712 tg3_phy_auxctl_write(tp
,
1713 MII_TG3_AUXCTL_SHDWSEL_MISC
, phy
);
1718 static void tg3_phy_set_wirespeed(struct tg3
*tp
)
1723 if (tp
->phy_flags
& TG3_PHYFLG_NO_ETH_WIRE_SPEED
)
1726 ret
= tg3_phy_auxctl_read(tp
, MII_TG3_AUXCTL_SHDWSEL_MISC
, &val
);
1728 tg3_phy_auxctl_write(tp
, MII_TG3_AUXCTL_SHDWSEL_MISC
,
1729 val
| MII_TG3_AUXCTL_MISC_WIRESPD_EN
);
1732 static void tg3_phy_apply_otp(struct tg3
*tp
)
1741 /* Enable SM_DSP clock and tx 6dB coding. */
1742 phy
= MII_TG3_AUXCTL_SHDWSEL_AUXCTL
|
1743 MII_TG3_AUXCTL_ACTL_SMDSP_ENA
|
1744 MII_TG3_AUXCTL_ACTL_TX_6DB
;
1745 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy
);
1747 phy
= ((otp
& TG3_OTP_AGCTGT_MASK
) >> TG3_OTP_AGCTGT_SHIFT
);
1748 phy
|= MII_TG3_DSP_TAP1_AGCTGT_DFLT
;
1749 tg3_phydsp_write(tp
, MII_TG3_DSP_TAP1
, phy
);
1751 phy
= ((otp
& TG3_OTP_HPFFLTR_MASK
) >> TG3_OTP_HPFFLTR_SHIFT
) |
1752 ((otp
& TG3_OTP_HPFOVER_MASK
) >> TG3_OTP_HPFOVER_SHIFT
);
1753 tg3_phydsp_write(tp
, MII_TG3_DSP_AADJ1CH0
, phy
);
1755 phy
= ((otp
& TG3_OTP_LPFDIS_MASK
) >> TG3_OTP_LPFDIS_SHIFT
);
1756 phy
|= MII_TG3_DSP_AADJ1CH3_ADCCKADJ
;
1757 tg3_phydsp_write(tp
, MII_TG3_DSP_AADJ1CH3
, phy
);
1759 phy
= ((otp
& TG3_OTP_VDAC_MASK
) >> TG3_OTP_VDAC_SHIFT
);
1760 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP75
, phy
);
1762 phy
= ((otp
& TG3_OTP_10BTAMP_MASK
) >> TG3_OTP_10BTAMP_SHIFT
);
1763 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP96
, phy
);
1765 phy
= ((otp
& TG3_OTP_ROFF_MASK
) >> TG3_OTP_ROFF_SHIFT
) |
1766 ((otp
& TG3_OTP_RCOFF_MASK
) >> TG3_OTP_RCOFF_SHIFT
);
1767 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP97
, phy
);
1769 /* Turn off SM_DSP clock. */
1770 phy
= MII_TG3_AUXCTL_SHDWSEL_AUXCTL
|
1771 MII_TG3_AUXCTL_ACTL_TX_6DB
;
1772 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy
);
1775 static void tg3_phy_eee_adjust(struct tg3
*tp
, u32 current_link_up
)
1779 if (!(tp
->phy_flags
& TG3_PHYFLG_EEE_CAP
))
1784 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
&&
1785 current_link_up
== 1 &&
1786 tp
->link_config
.active_duplex
== DUPLEX_FULL
&&
1787 (tp
->link_config
.active_speed
== SPEED_100
||
1788 tp
->link_config
.active_speed
== SPEED_1000
)) {
1791 if (tp
->link_config
.active_speed
== SPEED_1000
)
1792 eeectl
= TG3_CPMU_EEE_CTRL_EXIT_16_5_US
;
1794 eeectl
= TG3_CPMU_EEE_CTRL_EXIT_36_US
;
1796 tw32(TG3_CPMU_EEE_CTRL
, eeectl
);
1798 tg3_phy_cl45_read(tp
, MDIO_MMD_AN
,
1799 TG3_CL45_D7_EEERES_STAT
, &val
);
1802 case TG3_CL45_D7_EEERES_STAT_LP_1000T
:
1803 switch (GET_ASIC_REV(tp
->pci_chip_rev_id
)) {
1806 case ASIC_REV_57765
:
1807 /* Enable SM_DSP clock and tx 6dB coding. */
1808 val
= MII_TG3_AUXCTL_SHDWSEL_AUXCTL
|
1809 MII_TG3_AUXCTL_ACTL_SMDSP_ENA
|
1810 MII_TG3_AUXCTL_ACTL_TX_6DB
;
1811 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, val
);
1813 tg3_phydsp_write(tp
, MII_TG3_DSP_TAP26
, 0x0000);
1815 /* Turn off SM_DSP clock. */
1816 val
= MII_TG3_AUXCTL_SHDWSEL_AUXCTL
|
1817 MII_TG3_AUXCTL_ACTL_TX_6DB
;
1818 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, val
);
1821 case TG3_CL45_D7_EEERES_STAT_LP_100TX
:
1826 if (!tp
->setlpicnt
) {
1827 val
= tr32(TG3_CPMU_EEE_MODE
);
1828 tw32(TG3_CPMU_EEE_MODE
, val
& ~TG3_CPMU_EEEMD_LPI_ENABLE
);
1832 static int tg3_wait_macro_done(struct tg3
*tp
)
1839 if (!tg3_readphy(tp
, MII_TG3_DSP_CONTROL
, &tmp32
)) {
1840 if ((tmp32
& 0x1000) == 0)
1850 static int tg3_phy_write_and_check_testpat(struct tg3
*tp
, int *resetp
)
1852 static const u32 test_pat
[4][6] = {
1853 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1854 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1855 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1856 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1860 for (chan
= 0; chan
< 4; chan
++) {
1863 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
1864 (chan
* 0x2000) | 0x0200);
1865 tg3_writephy(tp
, MII_TG3_DSP_CONTROL
, 0x0002);
1867 for (i
= 0; i
< 6; i
++)
1868 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
,
1871 tg3_writephy(tp
, MII_TG3_DSP_CONTROL
, 0x0202);
1872 if (tg3_wait_macro_done(tp
)) {
1877 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
1878 (chan
* 0x2000) | 0x0200);
1879 tg3_writephy(tp
, MII_TG3_DSP_CONTROL
, 0x0082);
1880 if (tg3_wait_macro_done(tp
)) {
1885 tg3_writephy(tp
, MII_TG3_DSP_CONTROL
, 0x0802);
1886 if (tg3_wait_macro_done(tp
)) {
1891 for (i
= 0; i
< 6; i
+= 2) {
1894 if (tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &low
) ||
1895 tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &high
) ||
1896 tg3_wait_macro_done(tp
)) {
1902 if (low
!= test_pat
[chan
][i
] ||
1903 high
!= test_pat
[chan
][i
+1]) {
1904 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x000b);
1905 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x4001);
1906 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x4005);
1916 static int tg3_phy_reset_chanpat(struct tg3
*tp
)
1920 for (chan
= 0; chan
< 4; chan
++) {
1923 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
1924 (chan
* 0x2000) | 0x0200);
1925 tg3_writephy(tp
, MII_TG3_DSP_CONTROL
, 0x0002);
1926 for (i
= 0; i
< 6; i
++)
1927 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x000);
1928 tg3_writephy(tp
, MII_TG3_DSP_CONTROL
, 0x0202);
1929 if (tg3_wait_macro_done(tp
))
1936 static int tg3_phy_reset_5703_4_5(struct tg3
*tp
)
1938 u32 reg32
, phy9_orig
;
1939 int retries
, do_phy_reset
, err
;
1945 err
= tg3_bmcr_reset(tp
);
1951 /* Disable transmitter and interrupt. */
1952 if (tg3_readphy(tp
, MII_TG3_EXT_CTRL
, ®32
))
1956 tg3_writephy(tp
, MII_TG3_EXT_CTRL
, reg32
);
1958 /* Set full-duplex, 1000 mbps. */
1959 tg3_writephy(tp
, MII_BMCR
,
1960 BMCR_FULLDPLX
| TG3_BMCR_SPEED1000
);
1962 /* Set to master mode. */
1963 if (tg3_readphy(tp
, MII_TG3_CTRL
, &phy9_orig
))
1966 tg3_writephy(tp
, MII_TG3_CTRL
,
1967 (MII_TG3_CTRL_AS_MASTER
|
1968 MII_TG3_CTRL_ENABLE_AS_MASTER
));
1970 /* Enable SM_DSP_CLOCK and 6dB. */
1971 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
1973 /* Block the PHY control access. */
1974 tg3_phydsp_write(tp
, 0x8005, 0x0800);
1976 err
= tg3_phy_write_and_check_testpat(tp
, &do_phy_reset
);
1979 } while (--retries
);
1981 err
= tg3_phy_reset_chanpat(tp
);
1985 tg3_phydsp_write(tp
, 0x8005, 0x0000);
1987 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8200);
1988 tg3_writephy(tp
, MII_TG3_DSP_CONTROL
, 0x0000);
1990 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
1991 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
1992 /* Set Extended packet length bit for jumbo frames */
1993 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4400);
1995 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
1998 tg3_writephy(tp
, MII_TG3_CTRL
, phy9_orig
);
2000 if (!tg3_readphy(tp
, MII_TG3_EXT_CTRL
, ®32
)) {
2002 tg3_writephy(tp
, MII_TG3_EXT_CTRL
, reg32
);
2009 /* This will reset the tigon3 PHY if there is no valid
2010 * link unless the FORCE argument is non-zero.
2012 static int tg3_phy_reset(struct tg3
*tp
)
2017 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
2018 val
= tr32(GRC_MISC_CFG
);
2019 tw32_f(GRC_MISC_CFG
, val
& ~GRC_MISC_CFG_EPHY_IDDQ
);
2022 err
= tg3_readphy(tp
, MII_BMSR
, &val
);
2023 err
|= tg3_readphy(tp
, MII_BMSR
, &val
);
2027 if (netif_running(tp
->dev
) && netif_carrier_ok(tp
->dev
)) {
2028 netif_carrier_off(tp
->dev
);
2029 tg3_link_report(tp
);
2032 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
2033 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
2034 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
2035 err
= tg3_phy_reset_5703_4_5(tp
);
2042 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
2043 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
) {
2044 cpmuctrl
= tr32(TG3_CPMU_CTRL
);
2045 if (cpmuctrl
& CPMU_CTRL_GPHY_10MB_RXONLY
)
2047 cpmuctrl
& ~CPMU_CTRL_GPHY_10MB_RXONLY
);
2050 err
= tg3_bmcr_reset(tp
);
2054 if (cpmuctrl
& CPMU_CTRL_GPHY_10MB_RXONLY
) {
2055 val
= MII_TG3_DSP_EXP8_AEDW
| MII_TG3_DSP_EXP8_REJ2MHz
;
2056 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP8
, val
);
2058 tw32(TG3_CPMU_CTRL
, cpmuctrl
);
2061 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
||
2062 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5761_AX
) {
2063 val
= tr32(TG3_CPMU_LSPD_1000MB_CLK
);
2064 if ((val
& CPMU_LSPD_1000MB_MACCLK_MASK
) ==
2065 CPMU_LSPD_1000MB_MACCLK_12_5
) {
2066 val
&= ~CPMU_LSPD_1000MB_MACCLK_MASK
;
2068 tw32_f(TG3_CPMU_LSPD_1000MB_CLK
, val
);
2072 if ((tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
) &&
2073 (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
))
2076 tg3_phy_apply_otp(tp
);
2078 if (tp
->phy_flags
& TG3_PHYFLG_ENABLE_APD
)
2079 tg3_phy_toggle_apd(tp
, true);
2081 tg3_phy_toggle_apd(tp
, false);
2084 if (tp
->phy_flags
& TG3_PHYFLG_ADC_BUG
) {
2085 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
2086 tg3_phydsp_write(tp
, 0x201f, 0x2aaa);
2087 tg3_phydsp_write(tp
, 0x000a, 0x0323);
2088 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
2090 if (tp
->phy_flags
& TG3_PHYFLG_5704_A0_BUG
) {
2091 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, 0x8d68);
2092 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, 0x8d68);
2094 if (tp
->phy_flags
& TG3_PHYFLG_BER_BUG
) {
2095 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
2096 tg3_phydsp_write(tp
, 0x000a, 0x310b);
2097 tg3_phydsp_write(tp
, 0x201f, 0x9506);
2098 tg3_phydsp_write(tp
, 0x401f, 0x14e2);
2099 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
2100 } else if (tp
->phy_flags
& TG3_PHYFLG_JITTER_BUG
) {
2101 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
2102 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x000a);
2103 if (tp
->phy_flags
& TG3_PHYFLG_ADJUST_TRIM
) {
2104 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x110b);
2105 tg3_writephy(tp
, MII_TG3_TEST1
,
2106 MII_TG3_TEST1_TRIM_EN
| 0x4);
2108 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x010b);
2109 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
2111 /* Set Extended packet length bit (bit 14) on all chips that */
2112 /* support jumbo frames */
2113 if ((tp
->phy_id
& TG3_PHY_ID_MASK
) == TG3_PHY_ID_BCM5401
) {
2114 /* Cannot do read-modify-write on 5401 */
2115 tg3_phy_auxctl_write(tp
, MII_TG3_AUXCTL_SHDWSEL_AUXCTL
, 0x4c20);
2116 } else if (tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) {
2117 /* Set bit 14 with read-modify-write to preserve other bits */
2118 err
= tg3_phy_auxctl_read(tp
,
2119 MII_TG3_AUXCTL_SHDWSEL_AUXCTL
, &val
);
2121 tg3_phy_auxctl_write(tp
, MII_TG3_AUXCTL_SHDWSEL_AUXCTL
,
2122 val
| MII_TG3_AUXCTL_ACTL_EXTPKTLEN
);
2125 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2126 * jumbo frames transmission.
2128 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) {
2129 if (!tg3_readphy(tp
, MII_TG3_EXT_CTRL
, &val
))
2130 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
2131 val
| MII_TG3_EXT_CTRL_FIFO_ELASTIC
);
2134 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
2135 /* adjust output voltage */
2136 tg3_writephy(tp
, MII_TG3_FET_PTEST
, 0x12);
2139 tg3_phy_toggle_automdix(tp
, 1);
2140 tg3_phy_set_wirespeed(tp
);
2144 static void tg3_frob_aux_power(struct tg3
*tp
)
2146 bool need_vaux
= false;
2148 /* The GPIOs do something completely different on 57765. */
2149 if ((tp
->tg3_flags2
& TG3_FLG2_IS_NIC
) == 0 ||
2150 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
||
2151 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
2154 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
2155 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
||
2156 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
2157 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5720
) &&
2158 tp
->pdev_peer
!= tp
->pdev
) {
2159 struct net_device
*dev_peer
;
2161 dev_peer
= pci_get_drvdata(tp
->pdev_peer
);
2163 /* remove_one() may have been run on the peer. */
2165 struct tg3
*tp_peer
= netdev_priv(dev_peer
);
2167 if (tp_peer
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
)
2170 if ((tp_peer
->tg3_flags
& TG3_FLAG_WOL_ENABLE
) ||
2171 (tp_peer
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
2176 if ((tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
) ||
2177 (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
2181 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2182 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
2183 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2184 (GRC_LCLCTRL_GPIO_OE0
|
2185 GRC_LCLCTRL_GPIO_OE1
|
2186 GRC_LCLCTRL_GPIO_OE2
|
2187 GRC_LCLCTRL_GPIO_OUTPUT0
|
2188 GRC_LCLCTRL_GPIO_OUTPUT1
),
2190 } else if (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5761
||
2191 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5761S
) {
2192 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2193 u32 grc_local_ctrl
= GRC_LCLCTRL_GPIO_OE0
|
2194 GRC_LCLCTRL_GPIO_OE1
|
2195 GRC_LCLCTRL_GPIO_OE2
|
2196 GRC_LCLCTRL_GPIO_OUTPUT0
|
2197 GRC_LCLCTRL_GPIO_OUTPUT1
|
2199 tw32_wait_f(GRC_LOCAL_CTRL
, grc_local_ctrl
, 100);
2201 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OUTPUT2
;
2202 tw32_wait_f(GRC_LOCAL_CTRL
, grc_local_ctrl
, 100);
2204 grc_local_ctrl
&= ~GRC_LCLCTRL_GPIO_OUTPUT0
;
2205 tw32_wait_f(GRC_LOCAL_CTRL
, grc_local_ctrl
, 100);
2208 u32 grc_local_ctrl
= 0;
2210 /* Workaround to prevent overdrawing Amps. */
2211 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
2213 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE3
;
2214 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2215 grc_local_ctrl
, 100);
2218 /* On 5753 and variants, GPIO2 cannot be used. */
2219 no_gpio2
= tp
->nic_sram_data_cfg
&
2220 NIC_SRAM_DATA_CFG_NO_GPIO2
;
2222 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE0
|
2223 GRC_LCLCTRL_GPIO_OE1
|
2224 GRC_LCLCTRL_GPIO_OE2
|
2225 GRC_LCLCTRL_GPIO_OUTPUT1
|
2226 GRC_LCLCTRL_GPIO_OUTPUT2
;
2228 grc_local_ctrl
&= ~(GRC_LCLCTRL_GPIO_OE2
|
2229 GRC_LCLCTRL_GPIO_OUTPUT2
);
2231 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2232 grc_local_ctrl
, 100);
2234 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OUTPUT0
;
2236 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2237 grc_local_ctrl
, 100);
2240 grc_local_ctrl
&= ~GRC_LCLCTRL_GPIO_OUTPUT2
;
2241 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2242 grc_local_ctrl
, 100);
2246 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
2247 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
) {
2248 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2249 (GRC_LCLCTRL_GPIO_OE1
|
2250 GRC_LCLCTRL_GPIO_OUTPUT1
), 100);
2252 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2253 GRC_LCLCTRL_GPIO_OE1
, 100);
2255 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2256 (GRC_LCLCTRL_GPIO_OE1
|
2257 GRC_LCLCTRL_GPIO_OUTPUT1
), 100);
2262 static int tg3_5700_link_polarity(struct tg3
*tp
, u32 speed
)
2264 if (tp
->led_ctrl
== LED_CTRL_MODE_PHY_2
)
2266 else if ((tp
->phy_id
& TG3_PHY_ID_MASK
) == TG3_PHY_ID_BCM5411
) {
2267 if (speed
!= SPEED_10
)
2269 } else if (speed
== SPEED_10
)
2275 static int tg3_setup_phy(struct tg3
*, int);
2277 #define RESET_KIND_SHUTDOWN 0
2278 #define RESET_KIND_INIT 1
2279 #define RESET_KIND_SUSPEND 2
2281 static void tg3_write_sig_post_reset(struct tg3
*, int);
2282 static int tg3_halt_cpu(struct tg3
*, u32
);
2284 static void tg3_power_down_phy(struct tg3
*tp
, bool do_low_power
)
2288 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) {
2289 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
2290 u32 sg_dig_ctrl
= tr32(SG_DIG_CTRL
);
2291 u32 serdes_cfg
= tr32(MAC_SERDES_CFG
);
2294 SG_DIG_USING_HW_AUTONEG
| SG_DIG_SOFT_RESET
;
2295 tw32(SG_DIG_CTRL
, sg_dig_ctrl
);
2296 tw32(MAC_SERDES_CFG
, serdes_cfg
| (1 << 15));
2301 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
2303 val
= tr32(GRC_MISC_CFG
);
2304 tw32_f(GRC_MISC_CFG
, val
| GRC_MISC_CFG_EPHY_IDDQ
);
2307 } else if (tp
->phy_flags
& TG3_PHYFLG_IS_FET
) {
2309 if (!tg3_readphy(tp
, MII_TG3_FET_TEST
, &phytest
)) {
2312 tg3_writephy(tp
, MII_ADVERTISE
, 0);
2313 tg3_writephy(tp
, MII_BMCR
,
2314 BMCR_ANENABLE
| BMCR_ANRESTART
);
2316 tg3_writephy(tp
, MII_TG3_FET_TEST
,
2317 phytest
| MII_TG3_FET_SHADOW_EN
);
2318 if (!tg3_readphy(tp
, MII_TG3_FET_SHDW_AUXMODE4
, &phy
)) {
2319 phy
|= MII_TG3_FET_SHDW_AUXMODE4_SBPD
;
2321 MII_TG3_FET_SHDW_AUXMODE4
,
2324 tg3_writephy(tp
, MII_TG3_FET_TEST
, phytest
);
2327 } else if (do_low_power
) {
2328 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
2329 MII_TG3_EXT_CTRL_FORCE_LED_OFF
);
2331 val
= MII_TG3_AUXCTL_PCTL_100TX_LPWR
|
2332 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE
|
2333 MII_TG3_AUXCTL_PCTL_VREG_11V
;
2334 tg3_phy_auxctl_write(tp
, MII_TG3_AUXCTL_SHDWSEL_PWRCTL
, val
);
2337 /* The PHY should not be powered down on some chips because
2340 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2341 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
2342 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5780
&&
2343 (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
)))
2346 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
||
2347 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5761_AX
) {
2348 val
= tr32(TG3_CPMU_LSPD_1000MB_CLK
);
2349 val
&= ~CPMU_LSPD_1000MB_MACCLK_MASK
;
2350 val
|= CPMU_LSPD_1000MB_MACCLK_12_5
;
2351 tw32_f(TG3_CPMU_LSPD_1000MB_CLK
, val
);
2354 tg3_writephy(tp
, MII_BMCR
, BMCR_PDOWN
);
2357 /* tp->lock is held. */
2358 static int tg3_nvram_lock(struct tg3
*tp
)
2360 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
) {
2363 if (tp
->nvram_lock_cnt
== 0) {
2364 tw32(NVRAM_SWARB
, SWARB_REQ_SET1
);
2365 for (i
= 0; i
< 8000; i
++) {
2366 if (tr32(NVRAM_SWARB
) & SWARB_GNT1
)
2371 tw32(NVRAM_SWARB
, SWARB_REQ_CLR1
);
2375 tp
->nvram_lock_cnt
++;
2380 /* tp->lock is held. */
2381 static void tg3_nvram_unlock(struct tg3
*tp
)
2383 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
) {
2384 if (tp
->nvram_lock_cnt
> 0)
2385 tp
->nvram_lock_cnt
--;
2386 if (tp
->nvram_lock_cnt
== 0)
2387 tw32_f(NVRAM_SWARB
, SWARB_REQ_CLR1
);
2391 /* tp->lock is held. */
2392 static void tg3_enable_nvram_access(struct tg3
*tp
)
2394 if ((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
2395 !(tp
->tg3_flags3
& TG3_FLG3_PROTECTED_NVRAM
)) {
2396 u32 nvaccess
= tr32(NVRAM_ACCESS
);
2398 tw32(NVRAM_ACCESS
, nvaccess
| ACCESS_ENABLE
);
2402 /* tp->lock is held. */
2403 static void tg3_disable_nvram_access(struct tg3
*tp
)
2405 if ((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
2406 !(tp
->tg3_flags3
& TG3_FLG3_PROTECTED_NVRAM
)) {
2407 u32 nvaccess
= tr32(NVRAM_ACCESS
);
2409 tw32(NVRAM_ACCESS
, nvaccess
& ~ACCESS_ENABLE
);
2413 static int tg3_nvram_read_using_eeprom(struct tg3
*tp
,
2414 u32 offset
, u32
*val
)
2419 if (offset
> EEPROM_ADDR_ADDR_MASK
|| (offset
% 4) != 0)
2422 tmp
= tr32(GRC_EEPROM_ADDR
) & ~(EEPROM_ADDR_ADDR_MASK
|
2423 EEPROM_ADDR_DEVID_MASK
|
2425 tw32(GRC_EEPROM_ADDR
,
2427 (0 << EEPROM_ADDR_DEVID_SHIFT
) |
2428 ((offset
<< EEPROM_ADDR_ADDR_SHIFT
) &
2429 EEPROM_ADDR_ADDR_MASK
) |
2430 EEPROM_ADDR_READ
| EEPROM_ADDR_START
);
2432 for (i
= 0; i
< 1000; i
++) {
2433 tmp
= tr32(GRC_EEPROM_ADDR
);
2435 if (tmp
& EEPROM_ADDR_COMPLETE
)
2439 if (!(tmp
& EEPROM_ADDR_COMPLETE
))
2442 tmp
= tr32(GRC_EEPROM_DATA
);
2445 * The data will always be opposite the native endian
2446 * format. Perform a blind byteswap to compensate.
2453 #define NVRAM_CMD_TIMEOUT 10000
2455 static int tg3_nvram_exec_cmd(struct tg3
*tp
, u32 nvram_cmd
)
2459 tw32(NVRAM_CMD
, nvram_cmd
);
2460 for (i
= 0; i
< NVRAM_CMD_TIMEOUT
; i
++) {
2462 if (tr32(NVRAM_CMD
) & NVRAM_CMD_DONE
) {
2468 if (i
== NVRAM_CMD_TIMEOUT
)
2474 static u32
tg3_nvram_phys_addr(struct tg3
*tp
, u32 addr
)
2476 if ((tp
->tg3_flags
& TG3_FLAG_NVRAM
) &&
2477 (tp
->tg3_flags
& TG3_FLAG_NVRAM_BUFFERED
) &&
2478 (tp
->tg3_flags2
& TG3_FLG2_FLASH
) &&
2479 !(tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM_ADDR_TRANS
) &&
2480 (tp
->nvram_jedecnum
== JEDEC_ATMEL
))
2482 addr
= ((addr
/ tp
->nvram_pagesize
) <<
2483 ATMEL_AT45DB0X1B_PAGE_POS
) +
2484 (addr
% tp
->nvram_pagesize
);
2489 static u32
tg3_nvram_logical_addr(struct tg3
*tp
, u32 addr
)
2491 if ((tp
->tg3_flags
& TG3_FLAG_NVRAM
) &&
2492 (tp
->tg3_flags
& TG3_FLAG_NVRAM_BUFFERED
) &&
2493 (tp
->tg3_flags2
& TG3_FLG2_FLASH
) &&
2494 !(tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM_ADDR_TRANS
) &&
2495 (tp
->nvram_jedecnum
== JEDEC_ATMEL
))
2497 addr
= ((addr
>> ATMEL_AT45DB0X1B_PAGE_POS
) *
2498 tp
->nvram_pagesize
) +
2499 (addr
& ((1 << ATMEL_AT45DB0X1B_PAGE_POS
) - 1));
2504 /* NOTE: Data read in from NVRAM is byteswapped according to
2505 * the byteswapping settings for all other register accesses.
2506 * tg3 devices are BE devices, so on a BE machine, the data
2507 * returned will be exactly as it is seen in NVRAM. On a LE
2508 * machine, the 32-bit value will be byteswapped.
2510 static int tg3_nvram_read(struct tg3
*tp
, u32 offset
, u32
*val
)
2514 if (!(tp
->tg3_flags
& TG3_FLAG_NVRAM
))
2515 return tg3_nvram_read_using_eeprom(tp
, offset
, val
);
2517 offset
= tg3_nvram_phys_addr(tp
, offset
);
2519 if (offset
> NVRAM_ADDR_MSK
)
2522 ret
= tg3_nvram_lock(tp
);
2526 tg3_enable_nvram_access(tp
);
2528 tw32(NVRAM_ADDR
, offset
);
2529 ret
= tg3_nvram_exec_cmd(tp
, NVRAM_CMD_RD
| NVRAM_CMD_GO
|
2530 NVRAM_CMD_FIRST
| NVRAM_CMD_LAST
| NVRAM_CMD_DONE
);
2533 *val
= tr32(NVRAM_RDDATA
);
2535 tg3_disable_nvram_access(tp
);
2537 tg3_nvram_unlock(tp
);
2542 /* Ensures NVRAM data is in bytestream format. */
2543 static int tg3_nvram_read_be32(struct tg3
*tp
, u32 offset
, __be32
*val
)
2546 int res
= tg3_nvram_read(tp
, offset
, &v
);
2548 *val
= cpu_to_be32(v
);
2552 /* tp->lock is held. */
2553 static void __tg3_set_mac_addr(struct tg3
*tp
, int skip_mac_1
)
2555 u32 addr_high
, addr_low
;
2558 addr_high
= ((tp
->dev
->dev_addr
[0] << 8) |
2559 tp
->dev
->dev_addr
[1]);
2560 addr_low
= ((tp
->dev
->dev_addr
[2] << 24) |
2561 (tp
->dev
->dev_addr
[3] << 16) |
2562 (tp
->dev
->dev_addr
[4] << 8) |
2563 (tp
->dev
->dev_addr
[5] << 0));
2564 for (i
= 0; i
< 4; i
++) {
2565 if (i
== 1 && skip_mac_1
)
2567 tw32(MAC_ADDR_0_HIGH
+ (i
* 8), addr_high
);
2568 tw32(MAC_ADDR_0_LOW
+ (i
* 8), addr_low
);
2571 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
2572 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
2573 for (i
= 0; i
< 12; i
++) {
2574 tw32(MAC_EXTADDR_0_HIGH
+ (i
* 8), addr_high
);
2575 tw32(MAC_EXTADDR_0_LOW
+ (i
* 8), addr_low
);
2579 addr_high
= (tp
->dev
->dev_addr
[0] +
2580 tp
->dev
->dev_addr
[1] +
2581 tp
->dev
->dev_addr
[2] +
2582 tp
->dev
->dev_addr
[3] +
2583 tp
->dev
->dev_addr
[4] +
2584 tp
->dev
->dev_addr
[5]) &
2585 TX_BACKOFF_SEED_MASK
;
2586 tw32(MAC_TX_BACKOFF_SEED
, addr_high
);
2589 static void tg3_enable_register_access(struct tg3
*tp
)
2592 * Make sure register accesses (indirect or otherwise) will function
2595 pci_write_config_dword(tp
->pdev
,
2596 TG3PCI_MISC_HOST_CTRL
, tp
->misc_host_ctrl
);
2599 static int tg3_power_up(struct tg3
*tp
)
2601 tg3_enable_register_access(tp
);
2603 pci_set_power_state(tp
->pdev
, PCI_D0
);
2605 /* Switch out of Vaux if it is a NIC */
2606 if (tp
->tg3_flags2
& TG3_FLG2_IS_NIC
)
2607 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
, 100);
2612 static int tg3_power_down_prepare(struct tg3
*tp
)
2615 bool device_should_wake
, do_low_power
;
2617 tg3_enable_register_access(tp
);
2619 /* Restore the CLKREQ setting. */
2620 if (tp
->tg3_flags3
& TG3_FLG3_CLKREQ_BUG
) {
2623 pci_read_config_word(tp
->pdev
,
2624 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
2626 lnkctl
|= PCI_EXP_LNKCTL_CLKREQ_EN
;
2627 pci_write_config_word(tp
->pdev
,
2628 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
2632 misc_host_ctrl
= tr32(TG3PCI_MISC_HOST_CTRL
);
2633 tw32(TG3PCI_MISC_HOST_CTRL
,
2634 misc_host_ctrl
| MISC_HOST_CTRL_MASK_PCI_INT
);
2636 device_should_wake
= device_may_wakeup(&tp
->pdev
->dev
) &&
2637 (tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
);
2639 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
2640 do_low_power
= false;
2641 if ((tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
) &&
2642 !(tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)) {
2643 struct phy_device
*phydev
;
2644 u32 phyid
, advertising
;
2646 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
2648 tp
->phy_flags
|= TG3_PHYFLG_IS_LOW_POWER
;
2650 tp
->link_config
.orig_speed
= phydev
->speed
;
2651 tp
->link_config
.orig_duplex
= phydev
->duplex
;
2652 tp
->link_config
.orig_autoneg
= phydev
->autoneg
;
2653 tp
->link_config
.orig_advertising
= phydev
->advertising
;
2655 advertising
= ADVERTISED_TP
|
2657 ADVERTISED_Autoneg
|
2658 ADVERTISED_10baseT_Half
;
2660 if ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) ||
2661 device_should_wake
) {
2662 if (tp
->tg3_flags
& TG3_FLAG_WOL_SPEED_100MB
)
2664 ADVERTISED_100baseT_Half
|
2665 ADVERTISED_100baseT_Full
|
2666 ADVERTISED_10baseT_Full
;
2668 advertising
|= ADVERTISED_10baseT_Full
;
2671 phydev
->advertising
= advertising
;
2673 phy_start_aneg(phydev
);
2675 phyid
= phydev
->drv
->phy_id
& phydev
->drv
->phy_id_mask
;
2676 if (phyid
!= PHY_ID_BCMAC131
) {
2677 phyid
&= PHY_BCM_OUI_MASK
;
2678 if (phyid
== PHY_BCM_OUI_1
||
2679 phyid
== PHY_BCM_OUI_2
||
2680 phyid
== PHY_BCM_OUI_3
)
2681 do_low_power
= true;
2685 do_low_power
= true;
2687 if (!(tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)) {
2688 tp
->phy_flags
|= TG3_PHYFLG_IS_LOW_POWER
;
2689 tp
->link_config
.orig_speed
= tp
->link_config
.speed
;
2690 tp
->link_config
.orig_duplex
= tp
->link_config
.duplex
;
2691 tp
->link_config
.orig_autoneg
= tp
->link_config
.autoneg
;
2694 if (!(tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
)) {
2695 tp
->link_config
.speed
= SPEED_10
;
2696 tp
->link_config
.duplex
= DUPLEX_HALF
;
2697 tp
->link_config
.autoneg
= AUTONEG_ENABLE
;
2698 tg3_setup_phy(tp
, 0);
2702 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
2705 val
= tr32(GRC_VCPU_EXT_CTRL
);
2706 tw32(GRC_VCPU_EXT_CTRL
, val
| GRC_VCPU_EXT_CTRL_DISABLE_WOL
);
2707 } else if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)) {
2711 for (i
= 0; i
< 200; i
++) {
2712 tg3_read_mem(tp
, NIC_SRAM_FW_ASF_STATUS_MBOX
, &val
);
2713 if (val
== ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1
)
2718 if (tp
->tg3_flags
& TG3_FLAG_WOL_CAP
)
2719 tg3_write_mem(tp
, NIC_SRAM_WOL_MBOX
, WOL_SIGNATURE
|
2720 WOL_DRV_STATE_SHUTDOWN
|
2724 if (device_should_wake
) {
2727 if (!(tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
)) {
2729 !(tp
->phy_flags
& TG3_PHYFLG_IS_FET
)) {
2730 tg3_phy_auxctl_write(tp
,
2731 MII_TG3_AUXCTL_SHDWSEL_PWRCTL
,
2732 MII_TG3_AUXCTL_PCTL_WOL_EN
|
2733 MII_TG3_AUXCTL_PCTL_100TX_LPWR
|
2734 MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC
);
2738 if (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
)
2739 mac_mode
= MAC_MODE_PORT_MODE_GMII
;
2741 mac_mode
= MAC_MODE_PORT_MODE_MII
;
2743 mac_mode
|= tp
->mac_mode
& MAC_MODE_LINK_POLARITY
;
2744 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
2746 u32 speed
= (tp
->tg3_flags
&
2747 TG3_FLAG_WOL_SPEED_100MB
) ?
2748 SPEED_100
: SPEED_10
;
2749 if (tg3_5700_link_polarity(tp
, speed
))
2750 mac_mode
|= MAC_MODE_LINK_POLARITY
;
2752 mac_mode
&= ~MAC_MODE_LINK_POLARITY
;
2755 mac_mode
= MAC_MODE_PORT_MODE_TBI
;
2758 if (!(tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
))
2759 tw32(MAC_LED_CTRL
, tp
->led_ctrl
);
2761 mac_mode
|= MAC_MODE_MAGIC_PKT_ENABLE
;
2762 if (((tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
2763 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) &&
2764 ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) ||
2765 (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)))
2766 mac_mode
|= MAC_MODE_KEEP_FRAME_IN_WOL
;
2768 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
2769 mac_mode
|= MAC_MODE_APE_TX_EN
|
2770 MAC_MODE_APE_RX_EN
|
2771 MAC_MODE_TDE_ENABLE
;
2773 tw32_f(MAC_MODE
, mac_mode
);
2776 tw32_f(MAC_RX_MODE
, RX_MODE_ENABLE
);
2780 if (!(tp
->tg3_flags
& TG3_FLAG_WOL_SPEED_100MB
) &&
2781 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2782 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)) {
2785 base_val
= tp
->pci_clock_ctrl
;
2786 base_val
|= (CLOCK_CTRL_RXCLK_DISABLE
|
2787 CLOCK_CTRL_TXCLK_DISABLE
);
2789 tw32_wait_f(TG3PCI_CLOCK_CTRL
, base_val
| CLOCK_CTRL_ALTCLK
|
2790 CLOCK_CTRL_PWRDOWN_PLL133
, 40);
2791 } else if ((tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) ||
2792 (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) ||
2793 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)) {
2795 } else if (!((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
2796 (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))) {
2797 u32 newbits1
, newbits2
;
2799 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2800 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
2801 newbits1
= (CLOCK_CTRL_RXCLK_DISABLE
|
2802 CLOCK_CTRL_TXCLK_DISABLE
|
2804 newbits2
= newbits1
| CLOCK_CTRL_44MHZ_CORE
;
2805 } else if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
2806 newbits1
= CLOCK_CTRL_625_CORE
;
2807 newbits2
= newbits1
| CLOCK_CTRL_ALTCLK
;
2809 newbits1
= CLOCK_CTRL_ALTCLK
;
2810 newbits2
= newbits1
| CLOCK_CTRL_44MHZ_CORE
;
2813 tw32_wait_f(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
| newbits1
,
2816 tw32_wait_f(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
| newbits2
,
2819 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
2822 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2823 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
2824 newbits3
= (CLOCK_CTRL_RXCLK_DISABLE
|
2825 CLOCK_CTRL_TXCLK_DISABLE
|
2826 CLOCK_CTRL_44MHZ_CORE
);
2828 newbits3
= CLOCK_CTRL_44MHZ_CORE
;
2831 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
2832 tp
->pci_clock_ctrl
| newbits3
, 40);
2836 if (!(device_should_wake
) &&
2837 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
2838 tg3_power_down_phy(tp
, do_low_power
);
2840 tg3_frob_aux_power(tp
);
2842 /* Workaround for unstable PLL clock */
2843 if ((GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_AX
) ||
2844 (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_BX
)) {
2845 u32 val
= tr32(0x7d00);
2847 val
&= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2849 if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)) {
2852 err
= tg3_nvram_lock(tp
);
2853 tg3_halt_cpu(tp
, RX_CPU_BASE
);
2855 tg3_nvram_unlock(tp
);
2859 tg3_write_sig_post_reset(tp
, RESET_KIND_SHUTDOWN
);
2864 static void tg3_power_down(struct tg3
*tp
)
2866 tg3_power_down_prepare(tp
);
2868 pci_wake_from_d3(tp
->pdev
, tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
);
2869 pci_set_power_state(tp
->pdev
, PCI_D3hot
);
2872 static void tg3_aux_stat_to_speed_duplex(struct tg3
*tp
, u32 val
, u16
*speed
, u8
*duplex
)
2874 switch (val
& MII_TG3_AUX_STAT_SPDMASK
) {
2875 case MII_TG3_AUX_STAT_10HALF
:
2877 *duplex
= DUPLEX_HALF
;
2880 case MII_TG3_AUX_STAT_10FULL
:
2882 *duplex
= DUPLEX_FULL
;
2885 case MII_TG3_AUX_STAT_100HALF
:
2887 *duplex
= DUPLEX_HALF
;
2890 case MII_TG3_AUX_STAT_100FULL
:
2892 *duplex
= DUPLEX_FULL
;
2895 case MII_TG3_AUX_STAT_1000HALF
:
2896 *speed
= SPEED_1000
;
2897 *duplex
= DUPLEX_HALF
;
2900 case MII_TG3_AUX_STAT_1000FULL
:
2901 *speed
= SPEED_1000
;
2902 *duplex
= DUPLEX_FULL
;
2906 if (tp
->phy_flags
& TG3_PHYFLG_IS_FET
) {
2907 *speed
= (val
& MII_TG3_AUX_STAT_100
) ? SPEED_100
:
2909 *duplex
= (val
& MII_TG3_AUX_STAT_FULL
) ? DUPLEX_FULL
:
2913 *speed
= SPEED_INVALID
;
2914 *duplex
= DUPLEX_INVALID
;
2919 static void tg3_phy_copper_begin(struct tg3
*tp
)
2924 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
) {
2925 /* Entering low power mode. Disable gigabit and
2926 * 100baseT advertisements.
2928 tg3_writephy(tp
, MII_TG3_CTRL
, 0);
2930 new_adv
= (ADVERTISE_10HALF
| ADVERTISE_10FULL
|
2931 ADVERTISE_CSMA
| ADVERTISE_PAUSE_CAP
);
2932 if (tp
->tg3_flags
& TG3_FLAG_WOL_SPEED_100MB
)
2933 new_adv
|= (ADVERTISE_100HALF
| ADVERTISE_100FULL
);
2935 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
2936 } else if (tp
->link_config
.speed
== SPEED_INVALID
) {
2937 if (tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
)
2938 tp
->link_config
.advertising
&=
2939 ~(ADVERTISED_1000baseT_Half
|
2940 ADVERTISED_1000baseT_Full
);
2942 new_adv
= ADVERTISE_CSMA
;
2943 if (tp
->link_config
.advertising
& ADVERTISED_10baseT_Half
)
2944 new_adv
|= ADVERTISE_10HALF
;
2945 if (tp
->link_config
.advertising
& ADVERTISED_10baseT_Full
)
2946 new_adv
|= ADVERTISE_10FULL
;
2947 if (tp
->link_config
.advertising
& ADVERTISED_100baseT_Half
)
2948 new_adv
|= ADVERTISE_100HALF
;
2949 if (tp
->link_config
.advertising
& ADVERTISED_100baseT_Full
)
2950 new_adv
|= ADVERTISE_100FULL
;
2952 new_adv
|= tg3_advert_flowctrl_1000T(tp
->link_config
.flowctrl
);
2954 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
2956 if (tp
->link_config
.advertising
&
2957 (ADVERTISED_1000baseT_Half
| ADVERTISED_1000baseT_Full
)) {
2959 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Half
)
2960 new_adv
|= MII_TG3_CTRL_ADV_1000_HALF
;
2961 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Full
)
2962 new_adv
|= MII_TG3_CTRL_ADV_1000_FULL
;
2963 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
) &&
2964 (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
2965 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
))
2966 new_adv
|= (MII_TG3_CTRL_AS_MASTER
|
2967 MII_TG3_CTRL_ENABLE_AS_MASTER
);
2968 tg3_writephy(tp
, MII_TG3_CTRL
, new_adv
);
2970 tg3_writephy(tp
, MII_TG3_CTRL
, 0);
2973 new_adv
= tg3_advert_flowctrl_1000T(tp
->link_config
.flowctrl
);
2974 new_adv
|= ADVERTISE_CSMA
;
2976 /* Asking for a specific link mode. */
2977 if (tp
->link_config
.speed
== SPEED_1000
) {
2978 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
2980 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
2981 new_adv
= MII_TG3_CTRL_ADV_1000_FULL
;
2983 new_adv
= MII_TG3_CTRL_ADV_1000_HALF
;
2984 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
2985 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
)
2986 new_adv
|= (MII_TG3_CTRL_AS_MASTER
|
2987 MII_TG3_CTRL_ENABLE_AS_MASTER
);
2989 if (tp
->link_config
.speed
== SPEED_100
) {
2990 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
2991 new_adv
|= ADVERTISE_100FULL
;
2993 new_adv
|= ADVERTISE_100HALF
;
2995 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
2996 new_adv
|= ADVERTISE_10FULL
;
2998 new_adv
|= ADVERTISE_10HALF
;
3000 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
3005 tg3_writephy(tp
, MII_TG3_CTRL
, new_adv
);
3008 if (tp
->phy_flags
& TG3_PHYFLG_EEE_CAP
) {
3011 tw32(TG3_CPMU_EEE_MODE
,
3012 tr32(TG3_CPMU_EEE_MODE
) & ~TG3_CPMU_EEEMD_LPI_ENABLE
);
3014 /* Enable SM_DSP clock and tx 6dB coding. */
3015 val
= MII_TG3_AUXCTL_SHDWSEL_AUXCTL
|
3016 MII_TG3_AUXCTL_ACTL_SMDSP_ENA
|
3017 MII_TG3_AUXCTL_ACTL_TX_6DB
;
3018 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, val
);
3020 switch (GET_ASIC_REV(tp
->pci_chip_rev_id
)) {
3022 case ASIC_REV_57765
:
3023 if (!tg3_phydsp_read(tp
, MII_TG3_DSP_CH34TP2
, &val
))
3024 tg3_phydsp_write(tp
, MII_TG3_DSP_CH34TP2
, val
|
3025 MII_TG3_DSP_CH34TP2_HIBW01
);
3028 val
= MII_TG3_DSP_TAP26_ALNOKO
|
3029 MII_TG3_DSP_TAP26_RMRXSTO
|
3030 MII_TG3_DSP_TAP26_OPCSINPT
;
3031 tg3_phydsp_write(tp
, MII_TG3_DSP_TAP26
, val
);
3035 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) {
3036 /* Advertise 100-BaseTX EEE ability */
3037 if (tp
->link_config
.advertising
&
3038 ADVERTISED_100baseT_Full
)
3039 val
|= MDIO_AN_EEE_ADV_100TX
;
3040 /* Advertise 1000-BaseT EEE ability */
3041 if (tp
->link_config
.advertising
&
3042 ADVERTISED_1000baseT_Full
)
3043 val
|= MDIO_AN_EEE_ADV_1000T
;
3045 tg3_phy_cl45_write(tp
, MDIO_MMD_AN
, MDIO_AN_EEE_ADV
, val
);
3047 /* Turn off SM_DSP clock. */
3048 val
= MII_TG3_AUXCTL_SHDWSEL_AUXCTL
|
3049 MII_TG3_AUXCTL_ACTL_TX_6DB
;
3050 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, val
);
3053 if (tp
->link_config
.autoneg
== AUTONEG_DISABLE
&&
3054 tp
->link_config
.speed
!= SPEED_INVALID
) {
3055 u32 bmcr
, orig_bmcr
;
3057 tp
->link_config
.active_speed
= tp
->link_config
.speed
;
3058 tp
->link_config
.active_duplex
= tp
->link_config
.duplex
;
3061 switch (tp
->link_config
.speed
) {
3067 bmcr
|= BMCR_SPEED100
;
3071 bmcr
|= TG3_BMCR_SPEED1000
;
3075 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
3076 bmcr
|= BMCR_FULLDPLX
;
3078 if (!tg3_readphy(tp
, MII_BMCR
, &orig_bmcr
) &&
3079 (bmcr
!= orig_bmcr
)) {
3080 tg3_writephy(tp
, MII_BMCR
, BMCR_LOOPBACK
);
3081 for (i
= 0; i
< 1500; i
++) {
3085 if (tg3_readphy(tp
, MII_BMSR
, &tmp
) ||
3086 tg3_readphy(tp
, MII_BMSR
, &tmp
))
3088 if (!(tmp
& BMSR_LSTATUS
)) {
3093 tg3_writephy(tp
, MII_BMCR
, bmcr
);
3097 tg3_writephy(tp
, MII_BMCR
,
3098 BMCR_ANENABLE
| BMCR_ANRESTART
);
3102 static int tg3_init_5401phy_dsp(struct tg3
*tp
)
3106 /* Turn off tap power management. */
3107 /* Set Extended packet length bit */
3108 err
= tg3_phy_auxctl_write(tp
, MII_TG3_AUXCTL_SHDWSEL_AUXCTL
, 0x4c20);
3110 err
|= tg3_phydsp_write(tp
, 0x0012, 0x1804);
3111 err
|= tg3_phydsp_write(tp
, 0x0013, 0x1204);
3112 err
|= tg3_phydsp_write(tp
, 0x8006, 0x0132);
3113 err
|= tg3_phydsp_write(tp
, 0x8006, 0x0232);
3114 err
|= tg3_phydsp_write(tp
, 0x201f, 0x0a20);
3121 static int tg3_copper_is_advertising_all(struct tg3
*tp
, u32 mask
)
3123 u32 adv_reg
, all_mask
= 0;
3125 if (mask
& ADVERTISED_10baseT_Half
)
3126 all_mask
|= ADVERTISE_10HALF
;
3127 if (mask
& ADVERTISED_10baseT_Full
)
3128 all_mask
|= ADVERTISE_10FULL
;
3129 if (mask
& ADVERTISED_100baseT_Half
)
3130 all_mask
|= ADVERTISE_100HALF
;
3131 if (mask
& ADVERTISED_100baseT_Full
)
3132 all_mask
|= ADVERTISE_100FULL
;
3134 if (tg3_readphy(tp
, MII_ADVERTISE
, &adv_reg
))
3137 if ((adv_reg
& all_mask
) != all_mask
)
3139 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
)) {
3143 if (mask
& ADVERTISED_1000baseT_Half
)
3144 all_mask
|= ADVERTISE_1000HALF
;
3145 if (mask
& ADVERTISED_1000baseT_Full
)
3146 all_mask
|= ADVERTISE_1000FULL
;
3148 if (tg3_readphy(tp
, MII_TG3_CTRL
, &tg3_ctrl
))
3151 if ((tg3_ctrl
& all_mask
) != all_mask
)
3157 static int tg3_adv_1000T_flowctrl_ok(struct tg3
*tp
, u32
*lcladv
, u32
*rmtadv
)
3161 if (tg3_readphy(tp
, MII_ADVERTISE
, lcladv
))
3164 curadv
= *lcladv
& (ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
3165 reqadv
= tg3_advert_flowctrl_1000T(tp
->link_config
.flowctrl
);
3167 if (tp
->link_config
.active_duplex
== DUPLEX_FULL
) {
3168 if (curadv
!= reqadv
)
3171 if (tp
->tg3_flags
& TG3_FLAG_PAUSE_AUTONEG
)
3172 tg3_readphy(tp
, MII_LPA
, rmtadv
);
3174 /* Reprogram the advertisement register, even if it
3175 * does not affect the current link. If the link
3176 * gets renegotiated in the future, we can save an
3177 * additional renegotiation cycle by advertising
3178 * it correctly in the first place.
3180 if (curadv
!= reqadv
) {
3181 *lcladv
&= ~(ADVERTISE_PAUSE_CAP
|
3182 ADVERTISE_PAUSE_ASYM
);
3183 tg3_writephy(tp
, MII_ADVERTISE
, *lcladv
| reqadv
);
3190 static int tg3_setup_copper_phy(struct tg3
*tp
, int force_reset
)
3192 int current_link_up
;
3194 u32 lcl_adv
, rmt_adv
;
3202 (MAC_STATUS_SYNC_CHANGED
|
3203 MAC_STATUS_CFG_CHANGED
|
3204 MAC_STATUS_MI_COMPLETION
|
3205 MAC_STATUS_LNKSTATE_CHANGED
));
3208 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
3210 (tp
->mi_mode
& ~MAC_MI_MODE_AUTO_POLL
));
3214 tg3_phy_auxctl_write(tp
, MII_TG3_AUXCTL_SHDWSEL_PWRCTL
, 0);
3216 /* Some third-party PHYs need to be reset on link going
3219 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
3220 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
3221 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) &&
3222 netif_carrier_ok(tp
->dev
)) {
3223 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3224 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
3225 !(bmsr
& BMSR_LSTATUS
))
3231 if ((tp
->phy_id
& TG3_PHY_ID_MASK
) == TG3_PHY_ID_BCM5401
) {
3232 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3233 if (tg3_readphy(tp
, MII_BMSR
, &bmsr
) ||
3234 !(tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
))
3237 if (!(bmsr
& BMSR_LSTATUS
)) {
3238 err
= tg3_init_5401phy_dsp(tp
);
3242 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3243 for (i
= 0; i
< 1000; i
++) {
3245 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
3246 (bmsr
& BMSR_LSTATUS
)) {
3252 if ((tp
->phy_id
& TG3_PHY_ID_REV_MASK
) ==
3253 TG3_PHY_REV_BCM5401_B0
&&
3254 !(bmsr
& BMSR_LSTATUS
) &&
3255 tp
->link_config
.active_speed
== SPEED_1000
) {
3256 err
= tg3_phy_reset(tp
);
3258 err
= tg3_init_5401phy_dsp(tp
);
3263 } else if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
3264 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
) {
3265 /* 5701 {A0,B0} CRC bug workaround */
3266 tg3_writephy(tp
, 0x15, 0x0a75);
3267 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, 0x8c68);
3268 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, 0x8d68);
3269 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, 0x8c68);
3272 /* Clear pending interrupts... */
3273 tg3_readphy(tp
, MII_TG3_ISTAT
, &val
);
3274 tg3_readphy(tp
, MII_TG3_ISTAT
, &val
);
3276 if (tp
->phy_flags
& TG3_PHYFLG_USE_MI_INTERRUPT
)
3277 tg3_writephy(tp
, MII_TG3_IMASK
, ~MII_TG3_INT_LINKCHG
);
3278 else if (!(tp
->phy_flags
& TG3_PHYFLG_IS_FET
))
3279 tg3_writephy(tp
, MII_TG3_IMASK
, ~0);
3281 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
3282 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
3283 if (tp
->led_ctrl
== LED_CTRL_MODE_PHY_1
)
3284 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
3285 MII_TG3_EXT_CTRL_LNK3_LED_MODE
);
3287 tg3_writephy(tp
, MII_TG3_EXT_CTRL
, 0);
3290 current_link_up
= 0;
3291 current_speed
= SPEED_INVALID
;
3292 current_duplex
= DUPLEX_INVALID
;
3294 if (tp
->phy_flags
& TG3_PHYFLG_CAPACITIVE_COUPLING
) {
3295 err
= tg3_phy_auxctl_read(tp
,
3296 MII_TG3_AUXCTL_SHDWSEL_MISCTEST
,
3298 if (!err
&& !(val
& (1 << 10))) {
3299 tg3_phy_auxctl_write(tp
,
3300 MII_TG3_AUXCTL_SHDWSEL_MISCTEST
,
3307 for (i
= 0; i
< 100; i
++) {
3308 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3309 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
3310 (bmsr
& BMSR_LSTATUS
))
3315 if (bmsr
& BMSR_LSTATUS
) {
3318 tg3_readphy(tp
, MII_TG3_AUX_STAT
, &aux_stat
);
3319 for (i
= 0; i
< 2000; i
++) {
3321 if (!tg3_readphy(tp
, MII_TG3_AUX_STAT
, &aux_stat
) &&
3326 tg3_aux_stat_to_speed_duplex(tp
, aux_stat
,
3331 for (i
= 0; i
< 200; i
++) {
3332 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
3333 if (tg3_readphy(tp
, MII_BMCR
, &bmcr
))
3335 if (bmcr
&& bmcr
!= 0x7fff)
3343 tp
->link_config
.active_speed
= current_speed
;
3344 tp
->link_config
.active_duplex
= current_duplex
;
3346 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) {
3347 if ((bmcr
& BMCR_ANENABLE
) &&
3348 tg3_copper_is_advertising_all(tp
,
3349 tp
->link_config
.advertising
)) {
3350 if (tg3_adv_1000T_flowctrl_ok(tp
, &lcl_adv
,
3352 current_link_up
= 1;
3355 if (!(bmcr
& BMCR_ANENABLE
) &&
3356 tp
->link_config
.speed
== current_speed
&&
3357 tp
->link_config
.duplex
== current_duplex
&&
3358 tp
->link_config
.flowctrl
==
3359 tp
->link_config
.active_flowctrl
) {
3360 current_link_up
= 1;
3364 if (current_link_up
== 1 &&
3365 tp
->link_config
.active_duplex
== DUPLEX_FULL
)
3366 tg3_setup_flow_control(tp
, lcl_adv
, rmt_adv
);
3370 if (current_link_up
== 0 || (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)) {
3371 tg3_phy_copper_begin(tp
);
3373 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3374 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
3375 (bmsr
& BMSR_LSTATUS
))
3376 current_link_up
= 1;
3379 tp
->mac_mode
&= ~MAC_MODE_PORT_MODE_MASK
;
3380 if (current_link_up
== 1) {
3381 if (tp
->link_config
.active_speed
== SPEED_100
||
3382 tp
->link_config
.active_speed
== SPEED_10
)
3383 tp
->mac_mode
|= MAC_MODE_PORT_MODE_MII
;
3385 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
3386 } else if (tp
->phy_flags
& TG3_PHYFLG_IS_FET
)
3387 tp
->mac_mode
|= MAC_MODE_PORT_MODE_MII
;
3389 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
3391 tp
->mac_mode
&= ~MAC_MODE_HALF_DUPLEX
;
3392 if (tp
->link_config
.active_duplex
== DUPLEX_HALF
)
3393 tp
->mac_mode
|= MAC_MODE_HALF_DUPLEX
;
3395 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) {
3396 if (current_link_up
== 1 &&
3397 tg3_5700_link_polarity(tp
, tp
->link_config
.active_speed
))
3398 tp
->mac_mode
|= MAC_MODE_LINK_POLARITY
;
3400 tp
->mac_mode
&= ~MAC_MODE_LINK_POLARITY
;
3403 /* ??? Without this setting Netgear GA302T PHY does not
3404 * ??? send/receive packets...
3406 if ((tp
->phy_id
& TG3_PHY_ID_MASK
) == TG3_PHY_ID_BCM5411
&&
3407 tp
->pci_chip_rev_id
== CHIPREV_ID_5700_ALTIMA
) {
3408 tp
->mi_mode
|= MAC_MI_MODE_AUTO_POLL
;
3409 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
3413 tw32_f(MAC_MODE
, tp
->mac_mode
);
3416 tg3_phy_eee_adjust(tp
, current_link_up
);
3418 if (tp
->tg3_flags
& TG3_FLAG_USE_LINKCHG_REG
) {
3419 /* Polled via timer. */
3420 tw32_f(MAC_EVENT
, 0);
3422 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
3426 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
&&
3427 current_link_up
== 1 &&
3428 tp
->link_config
.active_speed
== SPEED_1000
&&
3429 ((tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) ||
3430 (tp
->tg3_flags
& TG3_FLAG_PCI_HIGH_SPEED
))) {
3433 (MAC_STATUS_SYNC_CHANGED
|
3434 MAC_STATUS_CFG_CHANGED
));
3437 NIC_SRAM_FIRMWARE_MBOX
,
3438 NIC_SRAM_FIRMWARE_MBOX_MAGIC2
);
3441 /* Prevent send BD corruption. */
3442 if (tp
->tg3_flags3
& TG3_FLG3_CLKREQ_BUG
) {
3443 u16 oldlnkctl
, newlnkctl
;
3445 pci_read_config_word(tp
->pdev
,
3446 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
3448 if (tp
->link_config
.active_speed
== SPEED_100
||
3449 tp
->link_config
.active_speed
== SPEED_10
)
3450 newlnkctl
= oldlnkctl
& ~PCI_EXP_LNKCTL_CLKREQ_EN
;
3452 newlnkctl
= oldlnkctl
| PCI_EXP_LNKCTL_CLKREQ_EN
;
3453 if (newlnkctl
!= oldlnkctl
)
3454 pci_write_config_word(tp
->pdev
,
3455 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
3459 if (current_link_up
!= netif_carrier_ok(tp
->dev
)) {
3460 if (current_link_up
)
3461 netif_carrier_on(tp
->dev
);
3463 netif_carrier_off(tp
->dev
);
3464 tg3_link_report(tp
);
3470 struct tg3_fiber_aneginfo
{
3472 #define ANEG_STATE_UNKNOWN 0
3473 #define ANEG_STATE_AN_ENABLE 1
3474 #define ANEG_STATE_RESTART_INIT 2
3475 #define ANEG_STATE_RESTART 3
3476 #define ANEG_STATE_DISABLE_LINK_OK 4
3477 #define ANEG_STATE_ABILITY_DETECT_INIT 5
3478 #define ANEG_STATE_ABILITY_DETECT 6
3479 #define ANEG_STATE_ACK_DETECT_INIT 7
3480 #define ANEG_STATE_ACK_DETECT 8
3481 #define ANEG_STATE_COMPLETE_ACK_INIT 9
3482 #define ANEG_STATE_COMPLETE_ACK 10
3483 #define ANEG_STATE_IDLE_DETECT_INIT 11
3484 #define ANEG_STATE_IDLE_DETECT 12
3485 #define ANEG_STATE_LINK_OK 13
3486 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3487 #define ANEG_STATE_NEXT_PAGE_WAIT 15
3490 #define MR_AN_ENABLE 0x00000001
3491 #define MR_RESTART_AN 0x00000002
3492 #define MR_AN_COMPLETE 0x00000004
3493 #define MR_PAGE_RX 0x00000008
3494 #define MR_NP_LOADED 0x00000010
3495 #define MR_TOGGLE_TX 0x00000020
3496 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
3497 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
3498 #define MR_LP_ADV_SYM_PAUSE 0x00000100
3499 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
3500 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3501 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3502 #define MR_LP_ADV_NEXT_PAGE 0x00001000
3503 #define MR_TOGGLE_RX 0x00002000
3504 #define MR_NP_RX 0x00004000
3506 #define MR_LINK_OK 0x80000000
3508 unsigned long link_time
, cur_time
;
3510 u32 ability_match_cfg
;
3511 int ability_match_count
;
3513 char ability_match
, idle_match
, ack_match
;
3515 u32 txconfig
, rxconfig
;
3516 #define ANEG_CFG_NP 0x00000080
3517 #define ANEG_CFG_ACK 0x00000040
3518 #define ANEG_CFG_RF2 0x00000020
3519 #define ANEG_CFG_RF1 0x00000010
3520 #define ANEG_CFG_PS2 0x00000001
3521 #define ANEG_CFG_PS1 0x00008000
3522 #define ANEG_CFG_HD 0x00004000
3523 #define ANEG_CFG_FD 0x00002000
3524 #define ANEG_CFG_INVAL 0x00001f06
3529 #define ANEG_TIMER_ENAB 2
3530 #define ANEG_FAILED -1
3532 #define ANEG_STATE_SETTLE_TIME 10000
3534 static int tg3_fiber_aneg_smachine(struct tg3
*tp
,
3535 struct tg3_fiber_aneginfo
*ap
)
3538 unsigned long delta
;
3542 if (ap
->state
== ANEG_STATE_UNKNOWN
) {
3546 ap
->ability_match_cfg
= 0;
3547 ap
->ability_match_count
= 0;
3548 ap
->ability_match
= 0;
3554 if (tr32(MAC_STATUS
) & MAC_STATUS_RCVD_CFG
) {
3555 rx_cfg_reg
= tr32(MAC_RX_AUTO_NEG
);
3557 if (rx_cfg_reg
!= ap
->ability_match_cfg
) {
3558 ap
->ability_match_cfg
= rx_cfg_reg
;
3559 ap
->ability_match
= 0;
3560 ap
->ability_match_count
= 0;
3562 if (++ap
->ability_match_count
> 1) {
3563 ap
->ability_match
= 1;
3564 ap
->ability_match_cfg
= rx_cfg_reg
;
3567 if (rx_cfg_reg
& ANEG_CFG_ACK
)
3575 ap
->ability_match_cfg
= 0;
3576 ap
->ability_match_count
= 0;
3577 ap
->ability_match
= 0;
3583 ap
->rxconfig
= rx_cfg_reg
;
3586 switch (ap
->state
) {
3587 case ANEG_STATE_UNKNOWN
:
3588 if (ap
->flags
& (MR_AN_ENABLE
| MR_RESTART_AN
))
3589 ap
->state
= ANEG_STATE_AN_ENABLE
;
3592 case ANEG_STATE_AN_ENABLE
:
3593 ap
->flags
&= ~(MR_AN_COMPLETE
| MR_PAGE_RX
);
3594 if (ap
->flags
& MR_AN_ENABLE
) {
3597 ap
->ability_match_cfg
= 0;
3598 ap
->ability_match_count
= 0;
3599 ap
->ability_match
= 0;
3603 ap
->state
= ANEG_STATE_RESTART_INIT
;
3605 ap
->state
= ANEG_STATE_DISABLE_LINK_OK
;
3609 case ANEG_STATE_RESTART_INIT
:
3610 ap
->link_time
= ap
->cur_time
;
3611 ap
->flags
&= ~(MR_NP_LOADED
);
3613 tw32(MAC_TX_AUTO_NEG
, 0);
3614 tp
->mac_mode
|= MAC_MODE_SEND_CONFIGS
;
3615 tw32_f(MAC_MODE
, tp
->mac_mode
);
3618 ret
= ANEG_TIMER_ENAB
;
3619 ap
->state
= ANEG_STATE_RESTART
;
3622 case ANEG_STATE_RESTART
:
3623 delta
= ap
->cur_time
- ap
->link_time
;
3624 if (delta
> ANEG_STATE_SETTLE_TIME
)
3625 ap
->state
= ANEG_STATE_ABILITY_DETECT_INIT
;
3627 ret
= ANEG_TIMER_ENAB
;
3630 case ANEG_STATE_DISABLE_LINK_OK
:
3634 case ANEG_STATE_ABILITY_DETECT_INIT
:
3635 ap
->flags
&= ~(MR_TOGGLE_TX
);
3636 ap
->txconfig
= ANEG_CFG_FD
;
3637 flowctrl
= tg3_advert_flowctrl_1000X(tp
->link_config
.flowctrl
);
3638 if (flowctrl
& ADVERTISE_1000XPAUSE
)
3639 ap
->txconfig
|= ANEG_CFG_PS1
;
3640 if (flowctrl
& ADVERTISE_1000XPSE_ASYM
)
3641 ap
->txconfig
|= ANEG_CFG_PS2
;
3642 tw32(MAC_TX_AUTO_NEG
, ap
->txconfig
);
3643 tp
->mac_mode
|= MAC_MODE_SEND_CONFIGS
;
3644 tw32_f(MAC_MODE
, tp
->mac_mode
);
3647 ap
->state
= ANEG_STATE_ABILITY_DETECT
;
3650 case ANEG_STATE_ABILITY_DETECT
:
3651 if (ap
->ability_match
!= 0 && ap
->rxconfig
!= 0)
3652 ap
->state
= ANEG_STATE_ACK_DETECT_INIT
;
3655 case ANEG_STATE_ACK_DETECT_INIT
:
3656 ap
->txconfig
|= ANEG_CFG_ACK
;
3657 tw32(MAC_TX_AUTO_NEG
, ap
->txconfig
);
3658 tp
->mac_mode
|= MAC_MODE_SEND_CONFIGS
;
3659 tw32_f(MAC_MODE
, tp
->mac_mode
);
3662 ap
->state
= ANEG_STATE_ACK_DETECT
;
3665 case ANEG_STATE_ACK_DETECT
:
3666 if (ap
->ack_match
!= 0) {
3667 if ((ap
->rxconfig
& ~ANEG_CFG_ACK
) ==
3668 (ap
->ability_match_cfg
& ~ANEG_CFG_ACK
)) {
3669 ap
->state
= ANEG_STATE_COMPLETE_ACK_INIT
;
3671 ap
->state
= ANEG_STATE_AN_ENABLE
;
3673 } else if (ap
->ability_match
!= 0 &&
3674 ap
->rxconfig
== 0) {
3675 ap
->state
= ANEG_STATE_AN_ENABLE
;
3679 case ANEG_STATE_COMPLETE_ACK_INIT
:
3680 if (ap
->rxconfig
& ANEG_CFG_INVAL
) {
3684 ap
->flags
&= ~(MR_LP_ADV_FULL_DUPLEX
|
3685 MR_LP_ADV_HALF_DUPLEX
|
3686 MR_LP_ADV_SYM_PAUSE
|
3687 MR_LP_ADV_ASYM_PAUSE
|
3688 MR_LP_ADV_REMOTE_FAULT1
|
3689 MR_LP_ADV_REMOTE_FAULT2
|
3690 MR_LP_ADV_NEXT_PAGE
|
3693 if (ap
->rxconfig
& ANEG_CFG_FD
)
3694 ap
->flags
|= MR_LP_ADV_FULL_DUPLEX
;
3695 if (ap
->rxconfig
& ANEG_CFG_HD
)
3696 ap
->flags
|= MR_LP_ADV_HALF_DUPLEX
;
3697 if (ap
->rxconfig
& ANEG_CFG_PS1
)
3698 ap
->flags
|= MR_LP_ADV_SYM_PAUSE
;
3699 if (ap
->rxconfig
& ANEG_CFG_PS2
)
3700 ap
->flags
|= MR_LP_ADV_ASYM_PAUSE
;
3701 if (ap
->rxconfig
& ANEG_CFG_RF1
)
3702 ap
->flags
|= MR_LP_ADV_REMOTE_FAULT1
;
3703 if (ap
->rxconfig
& ANEG_CFG_RF2
)
3704 ap
->flags
|= MR_LP_ADV_REMOTE_FAULT2
;
3705 if (ap
->rxconfig
& ANEG_CFG_NP
)
3706 ap
->flags
|= MR_LP_ADV_NEXT_PAGE
;
3708 ap
->link_time
= ap
->cur_time
;
3710 ap
->flags
^= (MR_TOGGLE_TX
);
3711 if (ap
->rxconfig
& 0x0008)
3712 ap
->flags
|= MR_TOGGLE_RX
;
3713 if (ap
->rxconfig
& ANEG_CFG_NP
)
3714 ap
->flags
|= MR_NP_RX
;
3715 ap
->flags
|= MR_PAGE_RX
;
3717 ap
->state
= ANEG_STATE_COMPLETE_ACK
;
3718 ret
= ANEG_TIMER_ENAB
;
3721 case ANEG_STATE_COMPLETE_ACK
:
3722 if (ap
->ability_match
!= 0 &&
3723 ap
->rxconfig
== 0) {
3724 ap
->state
= ANEG_STATE_AN_ENABLE
;
3727 delta
= ap
->cur_time
- ap
->link_time
;
3728 if (delta
> ANEG_STATE_SETTLE_TIME
) {
3729 if (!(ap
->flags
& (MR_LP_ADV_NEXT_PAGE
))) {
3730 ap
->state
= ANEG_STATE_IDLE_DETECT_INIT
;
3732 if ((ap
->txconfig
& ANEG_CFG_NP
) == 0 &&
3733 !(ap
->flags
& MR_NP_RX
)) {
3734 ap
->state
= ANEG_STATE_IDLE_DETECT_INIT
;
3742 case ANEG_STATE_IDLE_DETECT_INIT
:
3743 ap
->link_time
= ap
->cur_time
;
3744 tp
->mac_mode
&= ~MAC_MODE_SEND_CONFIGS
;
3745 tw32_f(MAC_MODE
, tp
->mac_mode
);
3748 ap
->state
= ANEG_STATE_IDLE_DETECT
;
3749 ret
= ANEG_TIMER_ENAB
;
3752 case ANEG_STATE_IDLE_DETECT
:
3753 if (ap
->ability_match
!= 0 &&
3754 ap
->rxconfig
== 0) {
3755 ap
->state
= ANEG_STATE_AN_ENABLE
;
3758 delta
= ap
->cur_time
- ap
->link_time
;
3759 if (delta
> ANEG_STATE_SETTLE_TIME
) {
3760 /* XXX another gem from the Broadcom driver :( */
3761 ap
->state
= ANEG_STATE_LINK_OK
;
3765 case ANEG_STATE_LINK_OK
:
3766 ap
->flags
|= (MR_AN_COMPLETE
| MR_LINK_OK
);
3770 case ANEG_STATE_NEXT_PAGE_WAIT_INIT
:
3771 /* ??? unimplemented */
3774 case ANEG_STATE_NEXT_PAGE_WAIT
:
3775 /* ??? unimplemented */
3786 static int fiber_autoneg(struct tg3
*tp
, u32
*txflags
, u32
*rxflags
)
3789 struct tg3_fiber_aneginfo aninfo
;
3790 int status
= ANEG_FAILED
;
3794 tw32_f(MAC_TX_AUTO_NEG
, 0);
3796 tmp
= tp
->mac_mode
& ~MAC_MODE_PORT_MODE_MASK
;
3797 tw32_f(MAC_MODE
, tmp
| MAC_MODE_PORT_MODE_GMII
);
3800 tw32_f(MAC_MODE
, tp
->mac_mode
| MAC_MODE_SEND_CONFIGS
);
3803 memset(&aninfo
, 0, sizeof(aninfo
));
3804 aninfo
.flags
|= MR_AN_ENABLE
;
3805 aninfo
.state
= ANEG_STATE_UNKNOWN
;
3806 aninfo
.cur_time
= 0;
3808 while (++tick
< 195000) {
3809 status
= tg3_fiber_aneg_smachine(tp
, &aninfo
);
3810 if (status
== ANEG_DONE
|| status
== ANEG_FAILED
)
3816 tp
->mac_mode
&= ~MAC_MODE_SEND_CONFIGS
;
3817 tw32_f(MAC_MODE
, tp
->mac_mode
);
3820 *txflags
= aninfo
.txconfig
;
3821 *rxflags
= aninfo
.flags
;
3823 if (status
== ANEG_DONE
&&
3824 (aninfo
.flags
& (MR_AN_COMPLETE
| MR_LINK_OK
|
3825 MR_LP_ADV_FULL_DUPLEX
)))
3831 static void tg3_init_bcm8002(struct tg3
*tp
)
3833 u32 mac_status
= tr32(MAC_STATUS
);
3836 /* Reset when initting first time or we have a link. */
3837 if ((tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
) &&
3838 !(mac_status
& MAC_STATUS_PCS_SYNCED
))
3841 /* Set PLL lock range. */
3842 tg3_writephy(tp
, 0x16, 0x8007);
3845 tg3_writephy(tp
, MII_BMCR
, BMCR_RESET
);
3847 /* Wait for reset to complete. */
3848 /* XXX schedule_timeout() ... */
3849 for (i
= 0; i
< 500; i
++)
3852 /* Config mode; select PMA/Ch 1 regs. */
3853 tg3_writephy(tp
, 0x10, 0x8411);
3855 /* Enable auto-lock and comdet, select txclk for tx. */
3856 tg3_writephy(tp
, 0x11, 0x0a10);
3858 tg3_writephy(tp
, 0x18, 0x00a0);
3859 tg3_writephy(tp
, 0x16, 0x41ff);
3861 /* Assert and deassert POR. */
3862 tg3_writephy(tp
, 0x13, 0x0400);
3864 tg3_writephy(tp
, 0x13, 0x0000);
3866 tg3_writephy(tp
, 0x11, 0x0a50);
3868 tg3_writephy(tp
, 0x11, 0x0a10);
3870 /* Wait for signal to stabilize */
3871 /* XXX schedule_timeout() ... */
3872 for (i
= 0; i
< 15000; i
++)
3875 /* Deselect the channel register so we can read the PHYID
3878 tg3_writephy(tp
, 0x10, 0x8011);
3881 static int tg3_setup_fiber_hw_autoneg(struct tg3
*tp
, u32 mac_status
)
3884 u32 sg_dig_ctrl
, sg_dig_status
;
3885 u32 serdes_cfg
, expected_sg_dig_ctrl
;
3886 int workaround
, port_a
;
3887 int current_link_up
;
3890 expected_sg_dig_ctrl
= 0;
3893 current_link_up
= 0;
3895 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5704_A0
&&
3896 tp
->pci_chip_rev_id
!= CHIPREV_ID_5704_A1
) {
3898 if (tr32(TG3PCI_DUAL_MAC_CTRL
) & DUAL_MAC_CTRL_ID
)
3901 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3902 /* preserve bits 20-23 for voltage regulator */
3903 serdes_cfg
= tr32(MAC_SERDES_CFG
) & 0x00f06fff;
3906 sg_dig_ctrl
= tr32(SG_DIG_CTRL
);
3908 if (tp
->link_config
.autoneg
!= AUTONEG_ENABLE
) {
3909 if (sg_dig_ctrl
& SG_DIG_USING_HW_AUTONEG
) {
3911 u32 val
= serdes_cfg
;
3917 tw32_f(MAC_SERDES_CFG
, val
);
3920 tw32_f(SG_DIG_CTRL
, SG_DIG_COMMON_SETUP
);
3922 if (mac_status
& MAC_STATUS_PCS_SYNCED
) {
3923 tg3_setup_flow_control(tp
, 0, 0);
3924 current_link_up
= 1;
3929 /* Want auto-negotiation. */
3930 expected_sg_dig_ctrl
= SG_DIG_USING_HW_AUTONEG
| SG_DIG_COMMON_SETUP
;
3932 flowctrl
= tg3_advert_flowctrl_1000X(tp
->link_config
.flowctrl
);
3933 if (flowctrl
& ADVERTISE_1000XPAUSE
)
3934 expected_sg_dig_ctrl
|= SG_DIG_PAUSE_CAP
;
3935 if (flowctrl
& ADVERTISE_1000XPSE_ASYM
)
3936 expected_sg_dig_ctrl
|= SG_DIG_ASYM_PAUSE
;
3938 if (sg_dig_ctrl
!= expected_sg_dig_ctrl
) {
3939 if ((tp
->phy_flags
& TG3_PHYFLG_PARALLEL_DETECT
) &&
3940 tp
->serdes_counter
&&
3941 ((mac_status
& (MAC_STATUS_PCS_SYNCED
|
3942 MAC_STATUS_RCVD_CFG
)) ==
3943 MAC_STATUS_PCS_SYNCED
)) {
3944 tp
->serdes_counter
--;
3945 current_link_up
= 1;
3950 tw32_f(MAC_SERDES_CFG
, serdes_cfg
| 0xc011000);
3951 tw32_f(SG_DIG_CTRL
, expected_sg_dig_ctrl
| SG_DIG_SOFT_RESET
);
3953 tw32_f(SG_DIG_CTRL
, expected_sg_dig_ctrl
);
3955 tp
->serdes_counter
= SERDES_AN_TIMEOUT_5704S
;
3956 tp
->phy_flags
&= ~TG3_PHYFLG_PARALLEL_DETECT
;
3957 } else if (mac_status
& (MAC_STATUS_PCS_SYNCED
|
3958 MAC_STATUS_SIGNAL_DET
)) {
3959 sg_dig_status
= tr32(SG_DIG_STATUS
);
3960 mac_status
= tr32(MAC_STATUS
);
3962 if ((sg_dig_status
& SG_DIG_AUTONEG_COMPLETE
) &&
3963 (mac_status
& MAC_STATUS_PCS_SYNCED
)) {
3964 u32 local_adv
= 0, remote_adv
= 0;
3966 if (sg_dig_ctrl
& SG_DIG_PAUSE_CAP
)
3967 local_adv
|= ADVERTISE_1000XPAUSE
;
3968 if (sg_dig_ctrl
& SG_DIG_ASYM_PAUSE
)
3969 local_adv
|= ADVERTISE_1000XPSE_ASYM
;
3971 if (sg_dig_status
& SG_DIG_PARTNER_PAUSE_CAPABLE
)
3972 remote_adv
|= LPA_1000XPAUSE
;
3973 if (sg_dig_status
& SG_DIG_PARTNER_ASYM_PAUSE
)
3974 remote_adv
|= LPA_1000XPAUSE_ASYM
;
3976 tg3_setup_flow_control(tp
, local_adv
, remote_adv
);
3977 current_link_up
= 1;
3978 tp
->serdes_counter
= 0;
3979 tp
->phy_flags
&= ~TG3_PHYFLG_PARALLEL_DETECT
;
3980 } else if (!(sg_dig_status
& SG_DIG_AUTONEG_COMPLETE
)) {
3981 if (tp
->serdes_counter
)
3982 tp
->serdes_counter
--;
3985 u32 val
= serdes_cfg
;
3992 tw32_f(MAC_SERDES_CFG
, val
);
3995 tw32_f(SG_DIG_CTRL
, SG_DIG_COMMON_SETUP
);
3998 /* Link parallel detection - link is up */
3999 /* only if we have PCS_SYNC and not */
4000 /* receiving config code words */
4001 mac_status
= tr32(MAC_STATUS
);
4002 if ((mac_status
& MAC_STATUS_PCS_SYNCED
) &&
4003 !(mac_status
& MAC_STATUS_RCVD_CFG
)) {
4004 tg3_setup_flow_control(tp
, 0, 0);
4005 current_link_up
= 1;
4007 TG3_PHYFLG_PARALLEL_DETECT
;
4008 tp
->serdes_counter
=
4009 SERDES_PARALLEL_DET_TIMEOUT
;
4011 goto restart_autoneg
;
4015 tp
->serdes_counter
= SERDES_AN_TIMEOUT_5704S
;
4016 tp
->phy_flags
&= ~TG3_PHYFLG_PARALLEL_DETECT
;
4020 return current_link_up
;
4023 static int tg3_setup_fiber_by_hand(struct tg3
*tp
, u32 mac_status
)
4025 int current_link_up
= 0;
4027 if (!(mac_status
& MAC_STATUS_PCS_SYNCED
))
4030 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) {
4031 u32 txflags
, rxflags
;
4034 if (fiber_autoneg(tp
, &txflags
, &rxflags
)) {
4035 u32 local_adv
= 0, remote_adv
= 0;
4037 if (txflags
& ANEG_CFG_PS1
)
4038 local_adv
|= ADVERTISE_1000XPAUSE
;
4039 if (txflags
& ANEG_CFG_PS2
)
4040 local_adv
|= ADVERTISE_1000XPSE_ASYM
;
4042 if (rxflags
& MR_LP_ADV_SYM_PAUSE
)
4043 remote_adv
|= LPA_1000XPAUSE
;
4044 if (rxflags
& MR_LP_ADV_ASYM_PAUSE
)
4045 remote_adv
|= LPA_1000XPAUSE_ASYM
;
4047 tg3_setup_flow_control(tp
, local_adv
, remote_adv
);
4049 current_link_up
= 1;
4051 for (i
= 0; i
< 30; i
++) {
4054 (MAC_STATUS_SYNC_CHANGED
|
4055 MAC_STATUS_CFG_CHANGED
));
4057 if ((tr32(MAC_STATUS
) &
4058 (MAC_STATUS_SYNC_CHANGED
|
4059 MAC_STATUS_CFG_CHANGED
)) == 0)
4063 mac_status
= tr32(MAC_STATUS
);
4064 if (current_link_up
== 0 &&
4065 (mac_status
& MAC_STATUS_PCS_SYNCED
) &&
4066 !(mac_status
& MAC_STATUS_RCVD_CFG
))
4067 current_link_up
= 1;
4069 tg3_setup_flow_control(tp
, 0, 0);
4071 /* Forcing 1000FD link up. */
4072 current_link_up
= 1;
4074 tw32_f(MAC_MODE
, (tp
->mac_mode
| MAC_MODE_SEND_CONFIGS
));
4077 tw32_f(MAC_MODE
, tp
->mac_mode
);
4082 return current_link_up
;
4085 static int tg3_setup_fiber_phy(struct tg3
*tp
, int force_reset
)
4088 u16 orig_active_speed
;
4089 u8 orig_active_duplex
;
4091 int current_link_up
;
4094 orig_pause_cfg
= tp
->link_config
.active_flowctrl
;
4095 orig_active_speed
= tp
->link_config
.active_speed
;
4096 orig_active_duplex
= tp
->link_config
.active_duplex
;
4098 if (!(tp
->tg3_flags2
& TG3_FLG2_HW_AUTONEG
) &&
4099 netif_carrier_ok(tp
->dev
) &&
4100 (tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
)) {
4101 mac_status
= tr32(MAC_STATUS
);
4102 mac_status
&= (MAC_STATUS_PCS_SYNCED
|
4103 MAC_STATUS_SIGNAL_DET
|
4104 MAC_STATUS_CFG_CHANGED
|
4105 MAC_STATUS_RCVD_CFG
);
4106 if (mac_status
== (MAC_STATUS_PCS_SYNCED
|
4107 MAC_STATUS_SIGNAL_DET
)) {
4108 tw32_f(MAC_STATUS
, (MAC_STATUS_SYNC_CHANGED
|
4109 MAC_STATUS_CFG_CHANGED
));
4114 tw32_f(MAC_TX_AUTO_NEG
, 0);
4116 tp
->mac_mode
&= ~(MAC_MODE_PORT_MODE_MASK
| MAC_MODE_HALF_DUPLEX
);
4117 tp
->mac_mode
|= MAC_MODE_PORT_MODE_TBI
;
4118 tw32_f(MAC_MODE
, tp
->mac_mode
);
4121 if (tp
->phy_id
== TG3_PHY_ID_BCM8002
)
4122 tg3_init_bcm8002(tp
);
4124 /* Enable link change event even when serdes polling. */
4125 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
4128 current_link_up
= 0;
4129 mac_status
= tr32(MAC_STATUS
);
4131 if (tp
->tg3_flags2
& TG3_FLG2_HW_AUTONEG
)
4132 current_link_up
= tg3_setup_fiber_hw_autoneg(tp
, mac_status
);
4134 current_link_up
= tg3_setup_fiber_by_hand(tp
, mac_status
);
4136 tp
->napi
[0].hw_status
->status
=
4137 (SD_STATUS_UPDATED
|
4138 (tp
->napi
[0].hw_status
->status
& ~SD_STATUS_LINK_CHG
));
4140 for (i
= 0; i
< 100; i
++) {
4141 tw32_f(MAC_STATUS
, (MAC_STATUS_SYNC_CHANGED
|
4142 MAC_STATUS_CFG_CHANGED
));
4144 if ((tr32(MAC_STATUS
) & (MAC_STATUS_SYNC_CHANGED
|
4145 MAC_STATUS_CFG_CHANGED
|
4146 MAC_STATUS_LNKSTATE_CHANGED
)) == 0)
4150 mac_status
= tr32(MAC_STATUS
);
4151 if ((mac_status
& MAC_STATUS_PCS_SYNCED
) == 0) {
4152 current_link_up
= 0;
4153 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
&&
4154 tp
->serdes_counter
== 0) {
4155 tw32_f(MAC_MODE
, (tp
->mac_mode
|
4156 MAC_MODE_SEND_CONFIGS
));
4158 tw32_f(MAC_MODE
, tp
->mac_mode
);
4162 if (current_link_up
== 1) {
4163 tp
->link_config
.active_speed
= SPEED_1000
;
4164 tp
->link_config
.active_duplex
= DUPLEX_FULL
;
4165 tw32(MAC_LED_CTRL
, (tp
->led_ctrl
|
4166 LED_CTRL_LNKLED_OVERRIDE
|
4167 LED_CTRL_1000MBPS_ON
));
4169 tp
->link_config
.active_speed
= SPEED_INVALID
;
4170 tp
->link_config
.active_duplex
= DUPLEX_INVALID
;
4171 tw32(MAC_LED_CTRL
, (tp
->led_ctrl
|
4172 LED_CTRL_LNKLED_OVERRIDE
|
4173 LED_CTRL_TRAFFIC_OVERRIDE
));
4176 if (current_link_up
!= netif_carrier_ok(tp
->dev
)) {
4177 if (current_link_up
)
4178 netif_carrier_on(tp
->dev
);
4180 netif_carrier_off(tp
->dev
);
4181 tg3_link_report(tp
);
4183 u32 now_pause_cfg
= tp
->link_config
.active_flowctrl
;
4184 if (orig_pause_cfg
!= now_pause_cfg
||
4185 orig_active_speed
!= tp
->link_config
.active_speed
||
4186 orig_active_duplex
!= tp
->link_config
.active_duplex
)
4187 tg3_link_report(tp
);
4193 static int tg3_setup_fiber_mii_phy(struct tg3
*tp
, int force_reset
)
4195 int current_link_up
, err
= 0;
4199 u32 local_adv
, remote_adv
;
4201 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
4202 tw32_f(MAC_MODE
, tp
->mac_mode
);
4208 (MAC_STATUS_SYNC_CHANGED
|
4209 MAC_STATUS_CFG_CHANGED
|
4210 MAC_STATUS_MI_COMPLETION
|
4211 MAC_STATUS_LNKSTATE_CHANGED
));
4217 current_link_up
= 0;
4218 current_speed
= SPEED_INVALID
;
4219 current_duplex
= DUPLEX_INVALID
;
4221 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
4222 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
4223 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
) {
4224 if (tr32(MAC_TX_STATUS
) & TX_STATUS_LINK_UP
)
4225 bmsr
|= BMSR_LSTATUS
;
4227 bmsr
&= ~BMSR_LSTATUS
;
4230 err
|= tg3_readphy(tp
, MII_BMCR
, &bmcr
);
4232 if ((tp
->link_config
.autoneg
== AUTONEG_ENABLE
) && !force_reset
&&
4233 (tp
->phy_flags
& TG3_PHYFLG_PARALLEL_DETECT
)) {
4234 /* do nothing, just check for link up at the end */
4235 } else if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) {
4238 err
|= tg3_readphy(tp
, MII_ADVERTISE
, &adv
);
4239 new_adv
= adv
& ~(ADVERTISE_1000XFULL
| ADVERTISE_1000XHALF
|
4240 ADVERTISE_1000XPAUSE
|
4241 ADVERTISE_1000XPSE_ASYM
|
4244 new_adv
|= tg3_advert_flowctrl_1000X(tp
->link_config
.flowctrl
);
4246 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Half
)
4247 new_adv
|= ADVERTISE_1000XHALF
;
4248 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Full
)
4249 new_adv
|= ADVERTISE_1000XFULL
;
4251 if ((new_adv
!= adv
) || !(bmcr
& BMCR_ANENABLE
)) {
4252 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
4253 bmcr
|= BMCR_ANENABLE
| BMCR_ANRESTART
;
4254 tg3_writephy(tp
, MII_BMCR
, bmcr
);
4256 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
4257 tp
->serdes_counter
= SERDES_AN_TIMEOUT_5714S
;
4258 tp
->phy_flags
&= ~TG3_PHYFLG_PARALLEL_DETECT
;
4265 bmcr
&= ~BMCR_SPEED1000
;
4266 new_bmcr
= bmcr
& ~(BMCR_ANENABLE
| BMCR_FULLDPLX
);
4268 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
4269 new_bmcr
|= BMCR_FULLDPLX
;
4271 if (new_bmcr
!= bmcr
) {
4272 /* BMCR_SPEED1000 is a reserved bit that needs
4273 * to be set on write.
4275 new_bmcr
|= BMCR_SPEED1000
;
4277 /* Force a linkdown */
4278 if (netif_carrier_ok(tp
->dev
)) {
4281 err
|= tg3_readphy(tp
, MII_ADVERTISE
, &adv
);
4282 adv
&= ~(ADVERTISE_1000XFULL
|
4283 ADVERTISE_1000XHALF
|
4285 tg3_writephy(tp
, MII_ADVERTISE
, adv
);
4286 tg3_writephy(tp
, MII_BMCR
, bmcr
|
4290 netif_carrier_off(tp
->dev
);
4292 tg3_writephy(tp
, MII_BMCR
, new_bmcr
);
4294 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
4295 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
4296 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
4298 if (tr32(MAC_TX_STATUS
) & TX_STATUS_LINK_UP
)
4299 bmsr
|= BMSR_LSTATUS
;
4301 bmsr
&= ~BMSR_LSTATUS
;
4303 tp
->phy_flags
&= ~TG3_PHYFLG_PARALLEL_DETECT
;
4307 if (bmsr
& BMSR_LSTATUS
) {
4308 current_speed
= SPEED_1000
;
4309 current_link_up
= 1;
4310 if (bmcr
& BMCR_FULLDPLX
)
4311 current_duplex
= DUPLEX_FULL
;
4313 current_duplex
= DUPLEX_HALF
;
4318 if (bmcr
& BMCR_ANENABLE
) {
4321 err
|= tg3_readphy(tp
, MII_ADVERTISE
, &local_adv
);
4322 err
|= tg3_readphy(tp
, MII_LPA
, &remote_adv
);
4323 common
= local_adv
& remote_adv
;
4324 if (common
& (ADVERTISE_1000XHALF
|
4325 ADVERTISE_1000XFULL
)) {
4326 if (common
& ADVERTISE_1000XFULL
)
4327 current_duplex
= DUPLEX_FULL
;
4329 current_duplex
= DUPLEX_HALF
;
4330 } else if (!(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
4331 /* Link is up via parallel detect */
4333 current_link_up
= 0;
4338 if (current_link_up
== 1 && current_duplex
== DUPLEX_FULL
)
4339 tg3_setup_flow_control(tp
, local_adv
, remote_adv
);
4341 tp
->mac_mode
&= ~MAC_MODE_HALF_DUPLEX
;
4342 if (tp
->link_config
.active_duplex
== DUPLEX_HALF
)
4343 tp
->mac_mode
|= MAC_MODE_HALF_DUPLEX
;
4345 tw32_f(MAC_MODE
, tp
->mac_mode
);
4348 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
4350 tp
->link_config
.active_speed
= current_speed
;
4351 tp
->link_config
.active_duplex
= current_duplex
;
4353 if (current_link_up
!= netif_carrier_ok(tp
->dev
)) {
4354 if (current_link_up
)
4355 netif_carrier_on(tp
->dev
);
4357 netif_carrier_off(tp
->dev
);
4358 tp
->phy_flags
&= ~TG3_PHYFLG_PARALLEL_DETECT
;
4360 tg3_link_report(tp
);
4365 static void tg3_serdes_parallel_detect(struct tg3
*tp
)
4367 if (tp
->serdes_counter
) {
4368 /* Give autoneg time to complete. */
4369 tp
->serdes_counter
--;
4373 if (!netif_carrier_ok(tp
->dev
) &&
4374 (tp
->link_config
.autoneg
== AUTONEG_ENABLE
)) {
4377 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
4378 if (bmcr
& BMCR_ANENABLE
) {
4381 /* Select shadow register 0x1f */
4382 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, 0x7c00);
4383 tg3_readphy(tp
, MII_TG3_MISC_SHDW
, &phy1
);
4385 /* Select expansion interrupt status register */
4386 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
4387 MII_TG3_DSP_EXP1_INT_STAT
);
4388 tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &phy2
);
4389 tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &phy2
);
4391 if ((phy1
& 0x10) && !(phy2
& 0x20)) {
4392 /* We have signal detect and not receiving
4393 * config code words, link is up by parallel
4397 bmcr
&= ~BMCR_ANENABLE
;
4398 bmcr
|= BMCR_SPEED1000
| BMCR_FULLDPLX
;
4399 tg3_writephy(tp
, MII_BMCR
, bmcr
);
4400 tp
->phy_flags
|= TG3_PHYFLG_PARALLEL_DETECT
;
4403 } else if (netif_carrier_ok(tp
->dev
) &&
4404 (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) &&
4405 (tp
->phy_flags
& TG3_PHYFLG_PARALLEL_DETECT
)) {
4408 /* Select expansion interrupt status register */
4409 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
4410 MII_TG3_DSP_EXP1_INT_STAT
);
4411 tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &phy2
);
4415 /* Config code words received, turn on autoneg. */
4416 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
4417 tg3_writephy(tp
, MII_BMCR
, bmcr
| BMCR_ANENABLE
);
4419 tp
->phy_flags
&= ~TG3_PHYFLG_PARALLEL_DETECT
;
4425 static int tg3_setup_phy(struct tg3
*tp
, int force_reset
)
4430 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
)
4431 err
= tg3_setup_fiber_phy(tp
, force_reset
);
4432 else if (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
)
4433 err
= tg3_setup_fiber_mii_phy(tp
, force_reset
);
4435 err
= tg3_setup_copper_phy(tp
, force_reset
);
4437 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
) {
4440 val
= tr32(TG3_CPMU_CLCK_STAT
) & CPMU_CLCK_STAT_MAC_CLCK_MASK
;
4441 if (val
== CPMU_CLCK_STAT_MAC_CLCK_62_5
)
4443 else if (val
== CPMU_CLCK_STAT_MAC_CLCK_6_25
)
4448 val
= tr32(GRC_MISC_CFG
) & ~GRC_MISC_CFG_PRESCALAR_MASK
;
4449 val
|= (scale
<< GRC_MISC_CFG_PRESCALAR_SHIFT
);
4450 tw32(GRC_MISC_CFG
, val
);
4453 val
= (2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
4454 (6 << TX_LENGTHS_IPG_SHIFT
);
4455 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5720
)
4456 val
|= tr32(MAC_TX_LENGTHS
) &
4457 (TX_LENGTHS_JMB_FRM_LEN_MSK
|
4458 TX_LENGTHS_CNT_DWN_VAL_MSK
);
4460 if (tp
->link_config
.active_speed
== SPEED_1000
&&
4461 tp
->link_config
.active_duplex
== DUPLEX_HALF
)
4462 tw32(MAC_TX_LENGTHS
, val
|
4463 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT
));
4465 tw32(MAC_TX_LENGTHS
, val
|
4466 (32 << TX_LENGTHS_SLOT_TIME_SHIFT
));
4468 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
4469 if (netif_carrier_ok(tp
->dev
)) {
4470 tw32(HOSTCC_STAT_COAL_TICKS
,
4471 tp
->coal
.stats_block_coalesce_usecs
);
4473 tw32(HOSTCC_STAT_COAL_TICKS
, 0);
4477 if (tp
->tg3_flags
& TG3_FLAG_ASPM_WORKAROUND
) {
4478 val
= tr32(PCIE_PWR_MGMT_THRESH
);
4479 if (!netif_carrier_ok(tp
->dev
))
4480 val
= (val
& ~PCIE_PWR_MGMT_L1_THRESH_MSK
) |
4483 val
|= PCIE_PWR_MGMT_L1_THRESH_MSK
;
4484 tw32(PCIE_PWR_MGMT_THRESH
, val
);
4490 static inline int tg3_irq_sync(struct tg3
*tp
)
4492 return tp
->irq_sync
;
4495 static inline void tg3_rd32_loop(struct tg3
*tp
, u32
*dst
, u32 off
, u32 len
)
4499 dst
= (u32
*)((u8
*)dst
+ off
);
4500 for (i
= 0; i
< len
; i
+= sizeof(u32
))
4501 *dst
++ = tr32(off
+ i
);
4504 static void tg3_dump_legacy_regs(struct tg3
*tp
, u32
*regs
)
4506 tg3_rd32_loop(tp
, regs
, TG3PCI_VENDOR
, 0xb0);
4507 tg3_rd32_loop(tp
, regs
, MAILBOX_INTERRUPT_0
, 0x200);
4508 tg3_rd32_loop(tp
, regs
, MAC_MODE
, 0x4f0);
4509 tg3_rd32_loop(tp
, regs
, SNDDATAI_MODE
, 0xe0);
4510 tg3_rd32_loop(tp
, regs
, SNDDATAC_MODE
, 0x04);
4511 tg3_rd32_loop(tp
, regs
, SNDBDS_MODE
, 0x80);
4512 tg3_rd32_loop(tp
, regs
, SNDBDI_MODE
, 0x48);
4513 tg3_rd32_loop(tp
, regs
, SNDBDC_MODE
, 0x04);
4514 tg3_rd32_loop(tp
, regs
, RCVLPC_MODE
, 0x20);
4515 tg3_rd32_loop(tp
, regs
, RCVLPC_SELLST_BASE
, 0x15c);
4516 tg3_rd32_loop(tp
, regs
, RCVDBDI_MODE
, 0x0c);
4517 tg3_rd32_loop(tp
, regs
, RCVDBDI_JUMBO_BD
, 0x3c);
4518 tg3_rd32_loop(tp
, regs
, RCVDBDI_BD_PROD_IDX_0
, 0x44);
4519 tg3_rd32_loop(tp
, regs
, RCVDCC_MODE
, 0x04);
4520 tg3_rd32_loop(tp
, regs
, RCVBDI_MODE
, 0x20);
4521 tg3_rd32_loop(tp
, regs
, RCVCC_MODE
, 0x14);
4522 tg3_rd32_loop(tp
, regs
, RCVLSC_MODE
, 0x08);
4523 tg3_rd32_loop(tp
, regs
, MBFREE_MODE
, 0x08);
4524 tg3_rd32_loop(tp
, regs
, HOSTCC_MODE
, 0x100);
4526 if (tp
->tg3_flags
& TG3_FLAG_SUPPORT_MSIX
)
4527 tg3_rd32_loop(tp
, regs
, HOSTCC_RXCOL_TICKS_VEC1
, 0x180);
4529 tg3_rd32_loop(tp
, regs
, MEMARB_MODE
, 0x10);
4530 tg3_rd32_loop(tp
, regs
, BUFMGR_MODE
, 0x58);
4531 tg3_rd32_loop(tp
, regs
, RDMAC_MODE
, 0x08);
4532 tg3_rd32_loop(tp
, regs
, WDMAC_MODE
, 0x08);
4533 tg3_rd32_loop(tp
, regs
, RX_CPU_MODE
, 0x04);
4534 tg3_rd32_loop(tp
, regs
, RX_CPU_STATE
, 0x04);
4535 tg3_rd32_loop(tp
, regs
, RX_CPU_PGMCTR
, 0x04);
4536 tg3_rd32_loop(tp
, regs
, RX_CPU_HWBKPT
, 0x04);
4538 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
4539 tg3_rd32_loop(tp
, regs
, TX_CPU_MODE
, 0x04);
4540 tg3_rd32_loop(tp
, regs
, TX_CPU_STATE
, 0x04);
4541 tg3_rd32_loop(tp
, regs
, TX_CPU_PGMCTR
, 0x04);
4544 tg3_rd32_loop(tp
, regs
, GRCMBOX_INTERRUPT_0
, 0x110);
4545 tg3_rd32_loop(tp
, regs
, FTQ_RESET
, 0x120);
4546 tg3_rd32_loop(tp
, regs
, MSGINT_MODE
, 0x0c);
4547 tg3_rd32_loop(tp
, regs
, DMAC_MODE
, 0x04);
4548 tg3_rd32_loop(tp
, regs
, GRC_MODE
, 0x4c);
4550 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
)
4551 tg3_rd32_loop(tp
, regs
, NVRAM_CMD
, 0x24);
4554 static void tg3_dump_state(struct tg3
*tp
)
4559 regs
= kzalloc(TG3_REG_BLK_SIZE
, GFP_ATOMIC
);
4561 netdev_err(tp
->dev
, "Failed allocating register dump buffer\n");
4565 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
4566 /* Read up to but not including private PCI registers */
4567 for (i
= 0; i
< TG3_PCIE_TLDLPL_PORT
; i
+= sizeof(u32
))
4568 regs
[i
/ sizeof(u32
)] = tr32(i
);
4570 tg3_dump_legacy_regs(tp
, regs
);
4572 for (i
= 0; i
< TG3_REG_BLK_SIZE
/ sizeof(u32
); i
+= 4) {
4573 if (!regs
[i
+ 0] && !regs
[i
+ 1] &&
4574 !regs
[i
+ 2] && !regs
[i
+ 3])
4577 netdev_err(tp
->dev
, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
4579 regs
[i
+ 0], regs
[i
+ 1], regs
[i
+ 2], regs
[i
+ 3]);
4584 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
4585 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
4587 /* SW status block */
4589 "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
4591 tnapi
->hw_status
->status
,
4592 tnapi
->hw_status
->status_tag
,
4593 tnapi
->hw_status
->rx_jumbo_consumer
,
4594 tnapi
->hw_status
->rx_consumer
,
4595 tnapi
->hw_status
->rx_mini_consumer
,
4596 tnapi
->hw_status
->idx
[0].rx_producer
,
4597 tnapi
->hw_status
->idx
[0].tx_consumer
);
4600 "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
4602 tnapi
->last_tag
, tnapi
->last_irq_tag
,
4603 tnapi
->tx_prod
, tnapi
->tx_cons
, tnapi
->tx_pending
,
4605 tnapi
->prodring
.rx_std_prod_idx
,
4606 tnapi
->prodring
.rx_std_cons_idx
,
4607 tnapi
->prodring
.rx_jmb_prod_idx
,
4608 tnapi
->prodring
.rx_jmb_cons_idx
);
4612 /* This is called whenever we suspect that the system chipset is re-
4613 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4614 * is bogus tx completions. We try to recover by setting the
4615 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4618 static void tg3_tx_recover(struct tg3
*tp
)
4620 BUG_ON((tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
) ||
4621 tp
->write32_tx_mbox
== tg3_write_indirect_mbox
);
4623 netdev_warn(tp
->dev
,
4624 "The system may be re-ordering memory-mapped I/O "
4625 "cycles to the network device, attempting to recover. "
4626 "Please report the problem to the driver maintainer "
4627 "and include system chipset information.\n");
4629 spin_lock(&tp
->lock
);
4630 tp
->tg3_flags
|= TG3_FLAG_TX_RECOVERY_PENDING
;
4631 spin_unlock(&tp
->lock
);
4634 static inline u32
tg3_tx_avail(struct tg3_napi
*tnapi
)
4636 /* Tell compiler to fetch tx indices from memory. */
4638 return tnapi
->tx_pending
-
4639 ((tnapi
->tx_prod
- tnapi
->tx_cons
) & (TG3_TX_RING_SIZE
- 1));
4642 /* Tigon3 never reports partial packet sends. So we do not
4643 * need special logic to handle SKBs that have not had all
4644 * of their frags sent yet, like SunGEM does.
4646 static void tg3_tx(struct tg3_napi
*tnapi
)
4648 struct tg3
*tp
= tnapi
->tp
;
4649 u32 hw_idx
= tnapi
->hw_status
->idx
[0].tx_consumer
;
4650 u32 sw_idx
= tnapi
->tx_cons
;
4651 struct netdev_queue
*txq
;
4652 int index
= tnapi
- tp
->napi
;
4654 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)
4657 txq
= netdev_get_tx_queue(tp
->dev
, index
);
4659 while (sw_idx
!= hw_idx
) {
4660 struct ring_info
*ri
= &tnapi
->tx_buffers
[sw_idx
];
4661 struct sk_buff
*skb
= ri
->skb
;
4664 if (unlikely(skb
== NULL
)) {
4669 pci_unmap_single(tp
->pdev
,
4670 dma_unmap_addr(ri
, mapping
),
4676 sw_idx
= NEXT_TX(sw_idx
);
4678 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
4679 ri
= &tnapi
->tx_buffers
[sw_idx
];
4680 if (unlikely(ri
->skb
!= NULL
|| sw_idx
== hw_idx
))
4683 pci_unmap_page(tp
->pdev
,
4684 dma_unmap_addr(ri
, mapping
),
4685 skb_shinfo(skb
)->frags
[i
].size
,
4687 sw_idx
= NEXT_TX(sw_idx
);
4692 if (unlikely(tx_bug
)) {
4698 tnapi
->tx_cons
= sw_idx
;
4700 /* Need to make the tx_cons update visible to tg3_start_xmit()
4701 * before checking for netif_queue_stopped(). Without the
4702 * memory barrier, there is a small possibility that tg3_start_xmit()
4703 * will miss it and cause the queue to be stopped forever.
4707 if (unlikely(netif_tx_queue_stopped(txq
) &&
4708 (tg3_tx_avail(tnapi
) > TG3_TX_WAKEUP_THRESH(tnapi
)))) {
4709 __netif_tx_lock(txq
, smp_processor_id());
4710 if (netif_tx_queue_stopped(txq
) &&
4711 (tg3_tx_avail(tnapi
) > TG3_TX_WAKEUP_THRESH(tnapi
)))
4712 netif_tx_wake_queue(txq
);
4713 __netif_tx_unlock(txq
);
4717 static void tg3_rx_skb_free(struct tg3
*tp
, struct ring_info
*ri
, u32 map_sz
)
4722 pci_unmap_single(tp
->pdev
, dma_unmap_addr(ri
, mapping
),
4723 map_sz
, PCI_DMA_FROMDEVICE
);
4724 dev_kfree_skb_any(ri
->skb
);
4728 /* Returns size of skb allocated or < 0 on error.
4730 * We only need to fill in the address because the other members
4731 * of the RX descriptor are invariant, see tg3_init_rings.
4733 * Note the purposeful assymetry of cpu vs. chip accesses. For
4734 * posting buffers we only dirty the first cache line of the RX
4735 * descriptor (containing the address). Whereas for the RX status
4736 * buffers the cpu only reads the last cacheline of the RX descriptor
4737 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4739 static int tg3_alloc_rx_skb(struct tg3
*tp
, struct tg3_rx_prodring_set
*tpr
,
4740 u32 opaque_key
, u32 dest_idx_unmasked
)
4742 struct tg3_rx_buffer_desc
*desc
;
4743 struct ring_info
*map
;
4744 struct sk_buff
*skb
;
4746 int skb_size
, dest_idx
;
4748 switch (opaque_key
) {
4749 case RXD_OPAQUE_RING_STD
:
4750 dest_idx
= dest_idx_unmasked
& tp
->rx_std_ring_mask
;
4751 desc
= &tpr
->rx_std
[dest_idx
];
4752 map
= &tpr
->rx_std_buffers
[dest_idx
];
4753 skb_size
= tp
->rx_pkt_map_sz
;
4756 case RXD_OPAQUE_RING_JUMBO
:
4757 dest_idx
= dest_idx_unmasked
& tp
->rx_jmb_ring_mask
;
4758 desc
= &tpr
->rx_jmb
[dest_idx
].std
;
4759 map
= &tpr
->rx_jmb_buffers
[dest_idx
];
4760 skb_size
= TG3_RX_JMB_MAP_SZ
;
4767 /* Do not overwrite any of the map or rp information
4768 * until we are sure we can commit to a new buffer.
4770 * Callers depend upon this behavior and assume that
4771 * we leave everything unchanged if we fail.
4773 skb
= netdev_alloc_skb(tp
->dev
, skb_size
+ tp
->rx_offset
);
4777 skb_reserve(skb
, tp
->rx_offset
);
4779 mapping
= pci_map_single(tp
->pdev
, skb
->data
, skb_size
,
4780 PCI_DMA_FROMDEVICE
);
4781 if (pci_dma_mapping_error(tp
->pdev
, mapping
)) {
4787 dma_unmap_addr_set(map
, mapping
, mapping
);
4789 desc
->addr_hi
= ((u64
)mapping
>> 32);
4790 desc
->addr_lo
= ((u64
)mapping
& 0xffffffff);
4795 /* We only need to move over in the address because the other
4796 * members of the RX descriptor are invariant. See notes above
4797 * tg3_alloc_rx_skb for full details.
4799 static void tg3_recycle_rx(struct tg3_napi
*tnapi
,
4800 struct tg3_rx_prodring_set
*dpr
,
4801 u32 opaque_key
, int src_idx
,
4802 u32 dest_idx_unmasked
)
4804 struct tg3
*tp
= tnapi
->tp
;
4805 struct tg3_rx_buffer_desc
*src_desc
, *dest_desc
;
4806 struct ring_info
*src_map
, *dest_map
;
4807 struct tg3_rx_prodring_set
*spr
= &tp
->napi
[0].prodring
;
4810 switch (opaque_key
) {
4811 case RXD_OPAQUE_RING_STD
:
4812 dest_idx
= dest_idx_unmasked
& tp
->rx_std_ring_mask
;
4813 dest_desc
= &dpr
->rx_std
[dest_idx
];
4814 dest_map
= &dpr
->rx_std_buffers
[dest_idx
];
4815 src_desc
= &spr
->rx_std
[src_idx
];
4816 src_map
= &spr
->rx_std_buffers
[src_idx
];
4819 case RXD_OPAQUE_RING_JUMBO
:
4820 dest_idx
= dest_idx_unmasked
& tp
->rx_jmb_ring_mask
;
4821 dest_desc
= &dpr
->rx_jmb
[dest_idx
].std
;
4822 dest_map
= &dpr
->rx_jmb_buffers
[dest_idx
];
4823 src_desc
= &spr
->rx_jmb
[src_idx
].std
;
4824 src_map
= &spr
->rx_jmb_buffers
[src_idx
];
4831 dest_map
->skb
= src_map
->skb
;
4832 dma_unmap_addr_set(dest_map
, mapping
,
4833 dma_unmap_addr(src_map
, mapping
));
4834 dest_desc
->addr_hi
= src_desc
->addr_hi
;
4835 dest_desc
->addr_lo
= src_desc
->addr_lo
;
4837 /* Ensure that the update to the skb happens after the physical
4838 * addresses have been transferred to the new BD location.
4842 src_map
->skb
= NULL
;
4845 /* The RX ring scheme is composed of multiple rings which post fresh
4846 * buffers to the chip, and one special ring the chip uses to report
4847 * status back to the host.
4849 * The special ring reports the status of received packets to the
4850 * host. The chip does not write into the original descriptor the
4851 * RX buffer was obtained from. The chip simply takes the original
4852 * descriptor as provided by the host, updates the status and length
4853 * field, then writes this into the next status ring entry.
4855 * Each ring the host uses to post buffers to the chip is described
4856 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4857 * it is first placed into the on-chip ram. When the packet's length
4858 * is known, it walks down the TG3_BDINFO entries to select the ring.
4859 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4860 * which is within the range of the new packet's length is chosen.
4862 * The "separate ring for rx status" scheme may sound queer, but it makes
4863 * sense from a cache coherency perspective. If only the host writes
4864 * to the buffer post rings, and only the chip writes to the rx status
4865 * rings, then cache lines never move beyond shared-modified state.
4866 * If both the host and chip were to write into the same ring, cache line
4867 * eviction could occur since both entities want it in an exclusive state.
4869 static int tg3_rx(struct tg3_napi
*tnapi
, int budget
)
4871 struct tg3
*tp
= tnapi
->tp
;
4872 u32 work_mask
, rx_std_posted
= 0;
4873 u32 std_prod_idx
, jmb_prod_idx
;
4874 u32 sw_idx
= tnapi
->rx_rcb_ptr
;
4877 struct tg3_rx_prodring_set
*tpr
= &tnapi
->prodring
;
4879 hw_idx
= *(tnapi
->rx_rcb_prod_idx
);
4881 * We need to order the read of hw_idx and the read of
4882 * the opaque cookie.
4887 std_prod_idx
= tpr
->rx_std_prod_idx
;
4888 jmb_prod_idx
= tpr
->rx_jmb_prod_idx
;
4889 while (sw_idx
!= hw_idx
&& budget
> 0) {
4890 struct ring_info
*ri
;
4891 struct tg3_rx_buffer_desc
*desc
= &tnapi
->rx_rcb
[sw_idx
];
4893 struct sk_buff
*skb
;
4894 dma_addr_t dma_addr
;
4895 u32 opaque_key
, desc_idx
, *post_ptr
;
4897 desc_idx
= desc
->opaque
& RXD_OPAQUE_INDEX_MASK
;
4898 opaque_key
= desc
->opaque
& RXD_OPAQUE_RING_MASK
;
4899 if (opaque_key
== RXD_OPAQUE_RING_STD
) {
4900 ri
= &tp
->napi
[0].prodring
.rx_std_buffers
[desc_idx
];
4901 dma_addr
= dma_unmap_addr(ri
, mapping
);
4903 post_ptr
= &std_prod_idx
;
4905 } else if (opaque_key
== RXD_OPAQUE_RING_JUMBO
) {
4906 ri
= &tp
->napi
[0].prodring
.rx_jmb_buffers
[desc_idx
];
4907 dma_addr
= dma_unmap_addr(ri
, mapping
);
4909 post_ptr
= &jmb_prod_idx
;
4911 goto next_pkt_nopost
;
4913 work_mask
|= opaque_key
;
4915 if ((desc
->err_vlan
& RXD_ERR_MASK
) != 0 &&
4916 (desc
->err_vlan
!= RXD_ERR_ODD_NIBBLE_RCVD_MII
)) {
4918 tg3_recycle_rx(tnapi
, tpr
, opaque_key
,
4919 desc_idx
, *post_ptr
);
4921 /* Other statistics kept track of by card. */
4926 len
= ((desc
->idx_len
& RXD_LEN_MASK
) >> RXD_LEN_SHIFT
) -
4929 if (len
> TG3_RX_COPY_THRESH(tp
)) {
4932 skb_size
= tg3_alloc_rx_skb(tp
, tpr
, opaque_key
,
4937 pci_unmap_single(tp
->pdev
, dma_addr
, skb_size
,
4938 PCI_DMA_FROMDEVICE
);
4940 /* Ensure that the update to the skb happens
4941 * after the usage of the old DMA mapping.
4949 struct sk_buff
*copy_skb
;
4951 tg3_recycle_rx(tnapi
, tpr
, opaque_key
,
4952 desc_idx
, *post_ptr
);
4954 copy_skb
= netdev_alloc_skb(tp
->dev
, len
+
4956 if (copy_skb
== NULL
)
4957 goto drop_it_no_recycle
;
4959 skb_reserve(copy_skb
, TG3_RAW_IP_ALIGN
);
4960 skb_put(copy_skb
, len
);
4961 pci_dma_sync_single_for_cpu(tp
->pdev
, dma_addr
, len
, PCI_DMA_FROMDEVICE
);
4962 skb_copy_from_linear_data(skb
, copy_skb
->data
, len
);
4963 pci_dma_sync_single_for_device(tp
->pdev
, dma_addr
, len
, PCI_DMA_FROMDEVICE
);
4965 /* We'll reuse the original ring buffer. */
4969 if ((tp
->dev
->features
& NETIF_F_RXCSUM
) &&
4970 (desc
->type_flags
& RXD_FLAG_TCPUDP_CSUM
) &&
4971 (((desc
->ip_tcp_csum
& RXD_TCPCSUM_MASK
)
4972 >> RXD_TCPCSUM_SHIFT
) == 0xffff))
4973 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
4975 skb_checksum_none_assert(skb
);
4977 skb
->protocol
= eth_type_trans(skb
, tp
->dev
);
4979 if (len
> (tp
->dev
->mtu
+ ETH_HLEN
) &&
4980 skb
->protocol
!= htons(ETH_P_8021Q
)) {
4982 goto drop_it_no_recycle
;
4985 if (desc
->type_flags
& RXD_FLAG_VLAN
&&
4986 !(tp
->rx_mode
& RX_MODE_KEEP_VLAN_TAG
))
4987 __vlan_hwaccel_put_tag(skb
,
4988 desc
->err_vlan
& RXD_VLAN_MASK
);
4990 napi_gro_receive(&tnapi
->napi
, skb
);
4998 if (unlikely(rx_std_posted
>= tp
->rx_std_max_post
)) {
4999 tpr
->rx_std_prod_idx
= std_prod_idx
&
5000 tp
->rx_std_ring_mask
;
5001 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG
,
5002 tpr
->rx_std_prod_idx
);
5003 work_mask
&= ~RXD_OPAQUE_RING_STD
;
5008 sw_idx
&= tp
->rx_ret_ring_mask
;
5010 /* Refresh hw_idx to see if there is new work */
5011 if (sw_idx
== hw_idx
) {
5012 hw_idx
= *(tnapi
->rx_rcb_prod_idx
);
5017 /* ACK the status ring. */
5018 tnapi
->rx_rcb_ptr
= sw_idx
;
5019 tw32_rx_mbox(tnapi
->consmbox
, sw_idx
);
5021 /* Refill RX ring(s). */
5022 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_RSS
)) {
5023 if (work_mask
& RXD_OPAQUE_RING_STD
) {
5024 tpr
->rx_std_prod_idx
= std_prod_idx
&
5025 tp
->rx_std_ring_mask
;
5026 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG
,
5027 tpr
->rx_std_prod_idx
);
5029 if (work_mask
& RXD_OPAQUE_RING_JUMBO
) {
5030 tpr
->rx_jmb_prod_idx
= jmb_prod_idx
&
5031 tp
->rx_jmb_ring_mask
;
5032 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG
,
5033 tpr
->rx_jmb_prod_idx
);
5036 } else if (work_mask
) {
5037 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
5038 * updated before the producer indices can be updated.
5042 tpr
->rx_std_prod_idx
= std_prod_idx
& tp
->rx_std_ring_mask
;
5043 tpr
->rx_jmb_prod_idx
= jmb_prod_idx
& tp
->rx_jmb_ring_mask
;
5045 if (tnapi
!= &tp
->napi
[1])
5046 napi_schedule(&tp
->napi
[1].napi
);
5052 static void tg3_poll_link(struct tg3
*tp
)
5054 /* handle link change and other phy events */
5055 if (!(tp
->tg3_flags
&
5056 (TG3_FLAG_USE_LINKCHG_REG
|
5057 TG3_FLAG_POLL_SERDES
))) {
5058 struct tg3_hw_status
*sblk
= tp
->napi
[0].hw_status
;
5060 if (sblk
->status
& SD_STATUS_LINK_CHG
) {
5061 sblk
->status
= SD_STATUS_UPDATED
|
5062 (sblk
->status
& ~SD_STATUS_LINK_CHG
);
5063 spin_lock(&tp
->lock
);
5064 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
5066 (MAC_STATUS_SYNC_CHANGED
|
5067 MAC_STATUS_CFG_CHANGED
|
5068 MAC_STATUS_MI_COMPLETION
|
5069 MAC_STATUS_LNKSTATE_CHANGED
));
5072 tg3_setup_phy(tp
, 0);
5073 spin_unlock(&tp
->lock
);
5078 static int tg3_rx_prodring_xfer(struct tg3
*tp
,
5079 struct tg3_rx_prodring_set
*dpr
,
5080 struct tg3_rx_prodring_set
*spr
)
5082 u32 si
, di
, cpycnt
, src_prod_idx
;
5086 src_prod_idx
= spr
->rx_std_prod_idx
;
5088 /* Make sure updates to the rx_std_buffers[] entries and the
5089 * standard producer index are seen in the correct order.
5093 if (spr
->rx_std_cons_idx
== src_prod_idx
)
5096 if (spr
->rx_std_cons_idx
< src_prod_idx
)
5097 cpycnt
= src_prod_idx
- spr
->rx_std_cons_idx
;
5099 cpycnt
= tp
->rx_std_ring_mask
+ 1 -
5100 spr
->rx_std_cons_idx
;
5102 cpycnt
= min(cpycnt
,
5103 tp
->rx_std_ring_mask
+ 1 - dpr
->rx_std_prod_idx
);
5105 si
= spr
->rx_std_cons_idx
;
5106 di
= dpr
->rx_std_prod_idx
;
5108 for (i
= di
; i
< di
+ cpycnt
; i
++) {
5109 if (dpr
->rx_std_buffers
[i
].skb
) {
5119 /* Ensure that updates to the rx_std_buffers ring and the
5120 * shadowed hardware producer ring from tg3_recycle_skb() are
5121 * ordered correctly WRT the skb check above.
5125 memcpy(&dpr
->rx_std_buffers
[di
],
5126 &spr
->rx_std_buffers
[si
],
5127 cpycnt
* sizeof(struct ring_info
));
5129 for (i
= 0; i
< cpycnt
; i
++, di
++, si
++) {
5130 struct tg3_rx_buffer_desc
*sbd
, *dbd
;
5131 sbd
= &spr
->rx_std
[si
];
5132 dbd
= &dpr
->rx_std
[di
];
5133 dbd
->addr_hi
= sbd
->addr_hi
;
5134 dbd
->addr_lo
= sbd
->addr_lo
;
5137 spr
->rx_std_cons_idx
= (spr
->rx_std_cons_idx
+ cpycnt
) &
5138 tp
->rx_std_ring_mask
;
5139 dpr
->rx_std_prod_idx
= (dpr
->rx_std_prod_idx
+ cpycnt
) &
5140 tp
->rx_std_ring_mask
;
5144 src_prod_idx
= spr
->rx_jmb_prod_idx
;
5146 /* Make sure updates to the rx_jmb_buffers[] entries and
5147 * the jumbo producer index are seen in the correct order.
5151 if (spr
->rx_jmb_cons_idx
== src_prod_idx
)
5154 if (spr
->rx_jmb_cons_idx
< src_prod_idx
)
5155 cpycnt
= src_prod_idx
- spr
->rx_jmb_cons_idx
;
5157 cpycnt
= tp
->rx_jmb_ring_mask
+ 1 -
5158 spr
->rx_jmb_cons_idx
;
5160 cpycnt
= min(cpycnt
,
5161 tp
->rx_jmb_ring_mask
+ 1 - dpr
->rx_jmb_prod_idx
);
5163 si
= spr
->rx_jmb_cons_idx
;
5164 di
= dpr
->rx_jmb_prod_idx
;
5166 for (i
= di
; i
< di
+ cpycnt
; i
++) {
5167 if (dpr
->rx_jmb_buffers
[i
].skb
) {
5177 /* Ensure that updates to the rx_jmb_buffers ring and the
5178 * shadowed hardware producer ring from tg3_recycle_skb() are
5179 * ordered correctly WRT the skb check above.
5183 memcpy(&dpr
->rx_jmb_buffers
[di
],
5184 &spr
->rx_jmb_buffers
[si
],
5185 cpycnt
* sizeof(struct ring_info
));
5187 for (i
= 0; i
< cpycnt
; i
++, di
++, si
++) {
5188 struct tg3_rx_buffer_desc
*sbd
, *dbd
;
5189 sbd
= &spr
->rx_jmb
[si
].std
;
5190 dbd
= &dpr
->rx_jmb
[di
].std
;
5191 dbd
->addr_hi
= sbd
->addr_hi
;
5192 dbd
->addr_lo
= sbd
->addr_lo
;
5195 spr
->rx_jmb_cons_idx
= (spr
->rx_jmb_cons_idx
+ cpycnt
) &
5196 tp
->rx_jmb_ring_mask
;
5197 dpr
->rx_jmb_prod_idx
= (dpr
->rx_jmb_prod_idx
+ cpycnt
) &
5198 tp
->rx_jmb_ring_mask
;
5204 static int tg3_poll_work(struct tg3_napi
*tnapi
, int work_done
, int budget
)
5206 struct tg3
*tp
= tnapi
->tp
;
5208 /* run TX completion thread */
5209 if (tnapi
->hw_status
->idx
[0].tx_consumer
!= tnapi
->tx_cons
) {
5211 if (unlikely(tp
->tg3_flags
& TG3_FLAG_TX_RECOVERY_PENDING
))
5215 /* run RX thread, within the bounds set by NAPI.
5216 * All RX "locking" is done by ensuring outside
5217 * code synchronizes with tg3->napi.poll()
5219 if (*(tnapi
->rx_rcb_prod_idx
) != tnapi
->rx_rcb_ptr
)
5220 work_done
+= tg3_rx(tnapi
, budget
- work_done
);
5222 if ((tp
->tg3_flags3
& TG3_FLG3_ENABLE_RSS
) && tnapi
== &tp
->napi
[1]) {
5223 struct tg3_rx_prodring_set
*dpr
= &tp
->napi
[0].prodring
;
5225 u32 std_prod_idx
= dpr
->rx_std_prod_idx
;
5226 u32 jmb_prod_idx
= dpr
->rx_jmb_prod_idx
;
5228 for (i
= 1; i
< tp
->irq_cnt
; i
++)
5229 err
|= tg3_rx_prodring_xfer(tp
, dpr
,
5230 &tp
->napi
[i
].prodring
);
5234 if (std_prod_idx
!= dpr
->rx_std_prod_idx
)
5235 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG
,
5236 dpr
->rx_std_prod_idx
);
5238 if (jmb_prod_idx
!= dpr
->rx_jmb_prod_idx
)
5239 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG
,
5240 dpr
->rx_jmb_prod_idx
);
5245 tw32_f(HOSTCC_MODE
, tp
->coal_now
);
5251 static int tg3_poll_msix(struct napi_struct
*napi
, int budget
)
5253 struct tg3_napi
*tnapi
= container_of(napi
, struct tg3_napi
, napi
);
5254 struct tg3
*tp
= tnapi
->tp
;
5256 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
5259 work_done
= tg3_poll_work(tnapi
, work_done
, budget
);
5261 if (unlikely(tp
->tg3_flags
& TG3_FLAG_TX_RECOVERY_PENDING
))
5264 if (unlikely(work_done
>= budget
))
5267 /* tp->last_tag is used in tg3_int_reenable() below
5268 * to tell the hw how much work has been processed,
5269 * so we must read it before checking for more work.
5271 tnapi
->last_tag
= sblk
->status_tag
;
5272 tnapi
->last_irq_tag
= tnapi
->last_tag
;
5275 /* check for RX/TX work to do */
5276 if (likely(sblk
->idx
[0].tx_consumer
== tnapi
->tx_cons
&&
5277 *(tnapi
->rx_rcb_prod_idx
) == tnapi
->rx_rcb_ptr
)) {
5278 napi_complete(napi
);
5279 /* Reenable interrupts. */
5280 tw32_mailbox(tnapi
->int_mbox
, tnapi
->last_tag
<< 24);
5289 /* work_done is guaranteed to be less than budget. */
5290 napi_complete(napi
);
5291 schedule_work(&tp
->reset_task
);
5295 static void tg3_process_error(struct tg3
*tp
)
5298 bool real_error
= false;
5300 if (tp
->tg3_flags
& TG3_FLAG_ERROR_PROCESSED
)
5303 /* Check Flow Attention register */
5304 val
= tr32(HOSTCC_FLOW_ATTN
);
5305 if (val
& ~HOSTCC_FLOW_ATTN_MBUF_LWM
) {
5306 netdev_err(tp
->dev
, "FLOW Attention error. Resetting chip.\n");
5310 if (tr32(MSGINT_STATUS
) & ~MSGINT_STATUS_MSI_REQ
) {
5311 netdev_err(tp
->dev
, "MSI Status error. Resetting chip.\n");
5315 if (tr32(RDMAC_STATUS
) || tr32(WDMAC_STATUS
)) {
5316 netdev_err(tp
->dev
, "DMA Status error. Resetting chip.\n");
5325 tp
->tg3_flags
|= TG3_FLAG_ERROR_PROCESSED
;
5326 schedule_work(&tp
->reset_task
);
5329 static int tg3_poll(struct napi_struct
*napi
, int budget
)
5331 struct tg3_napi
*tnapi
= container_of(napi
, struct tg3_napi
, napi
);
5332 struct tg3
*tp
= tnapi
->tp
;
5334 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
5337 if (sblk
->status
& SD_STATUS_ERROR
)
5338 tg3_process_error(tp
);
5342 work_done
= tg3_poll_work(tnapi
, work_done
, budget
);
5344 if (unlikely(tp
->tg3_flags
& TG3_FLAG_TX_RECOVERY_PENDING
))
5347 if (unlikely(work_done
>= budget
))
5350 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) {
5351 /* tp->last_tag is used in tg3_int_reenable() below
5352 * to tell the hw how much work has been processed,
5353 * so we must read it before checking for more work.
5355 tnapi
->last_tag
= sblk
->status_tag
;
5356 tnapi
->last_irq_tag
= tnapi
->last_tag
;
5359 sblk
->status
&= ~SD_STATUS_UPDATED
;
5361 if (likely(!tg3_has_work(tnapi
))) {
5362 napi_complete(napi
);
5363 tg3_int_reenable(tnapi
);
5371 /* work_done is guaranteed to be less than budget. */
5372 napi_complete(napi
);
5373 schedule_work(&tp
->reset_task
);
5377 static void tg3_napi_disable(struct tg3
*tp
)
5381 for (i
= tp
->irq_cnt
- 1; i
>= 0; i
--)
5382 napi_disable(&tp
->napi
[i
].napi
);
5385 static void tg3_napi_enable(struct tg3
*tp
)
5389 for (i
= 0; i
< tp
->irq_cnt
; i
++)
5390 napi_enable(&tp
->napi
[i
].napi
);
5393 static void tg3_napi_init(struct tg3
*tp
)
5397 netif_napi_add(tp
->dev
, &tp
->napi
[0].napi
, tg3_poll
, 64);
5398 for (i
= 1; i
< tp
->irq_cnt
; i
++)
5399 netif_napi_add(tp
->dev
, &tp
->napi
[i
].napi
, tg3_poll_msix
, 64);
5402 static void tg3_napi_fini(struct tg3
*tp
)
5406 for (i
= 0; i
< tp
->irq_cnt
; i
++)
5407 netif_napi_del(&tp
->napi
[i
].napi
);
5410 static inline void tg3_netif_stop(struct tg3
*tp
)
5412 tp
->dev
->trans_start
= jiffies
; /* prevent tx timeout */
5413 tg3_napi_disable(tp
);
5414 netif_tx_disable(tp
->dev
);
5417 static inline void tg3_netif_start(struct tg3
*tp
)
5419 /* NOTE: unconditional netif_tx_wake_all_queues is only
5420 * appropriate so long as all callers are assured to
5421 * have free tx slots (such as after tg3_init_hw)
5423 netif_tx_wake_all_queues(tp
->dev
);
5425 tg3_napi_enable(tp
);
5426 tp
->napi
[0].hw_status
->status
|= SD_STATUS_UPDATED
;
5427 tg3_enable_ints(tp
);
5430 static void tg3_irq_quiesce(struct tg3
*tp
)
5434 BUG_ON(tp
->irq_sync
);
5439 for (i
= 0; i
< tp
->irq_cnt
; i
++)
5440 synchronize_irq(tp
->napi
[i
].irq_vec
);
5443 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5444 * If irq_sync is non-zero, then the IRQ handler must be synchronized
5445 * with as well. Most of the time, this is not necessary except when
5446 * shutting down the device.
5448 static inline void tg3_full_lock(struct tg3
*tp
, int irq_sync
)
5450 spin_lock_bh(&tp
->lock
);
5452 tg3_irq_quiesce(tp
);
5455 static inline void tg3_full_unlock(struct tg3
*tp
)
5457 spin_unlock_bh(&tp
->lock
);
5460 /* One-shot MSI handler - Chip automatically disables interrupt
5461 * after sending MSI so driver doesn't have to do it.
5463 static irqreturn_t
tg3_msi_1shot(int irq
, void *dev_id
)
5465 struct tg3_napi
*tnapi
= dev_id
;
5466 struct tg3
*tp
= tnapi
->tp
;
5468 prefetch(tnapi
->hw_status
);
5470 prefetch(&tnapi
->rx_rcb
[tnapi
->rx_rcb_ptr
]);
5472 if (likely(!tg3_irq_sync(tp
)))
5473 napi_schedule(&tnapi
->napi
);
5478 /* MSI ISR - No need to check for interrupt sharing and no need to
5479 * flush status block and interrupt mailbox. PCI ordering rules
5480 * guarantee that MSI will arrive after the status block.
5482 static irqreturn_t
tg3_msi(int irq
, void *dev_id
)
5484 struct tg3_napi
*tnapi
= dev_id
;
5485 struct tg3
*tp
= tnapi
->tp
;
5487 prefetch(tnapi
->hw_status
);
5489 prefetch(&tnapi
->rx_rcb
[tnapi
->rx_rcb_ptr
]);
5491 * Writing any value to intr-mbox-0 clears PCI INTA# and
5492 * chip-internal interrupt pending events.
5493 * Writing non-zero to intr-mbox-0 additional tells the
5494 * NIC to stop sending us irqs, engaging "in-intr-handler"
5497 tw32_mailbox(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0x00000001);
5498 if (likely(!tg3_irq_sync(tp
)))
5499 napi_schedule(&tnapi
->napi
);
5501 return IRQ_RETVAL(1);
5504 static irqreturn_t
tg3_interrupt(int irq
, void *dev_id
)
5506 struct tg3_napi
*tnapi
= dev_id
;
5507 struct tg3
*tp
= tnapi
->tp
;
5508 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
5509 unsigned int handled
= 1;
5511 /* In INTx mode, it is possible for the interrupt to arrive at
5512 * the CPU before the status block posted prior to the interrupt.
5513 * Reading the PCI State register will confirm whether the
5514 * interrupt is ours and will flush the status block.
5516 if (unlikely(!(sblk
->status
& SD_STATUS_UPDATED
))) {
5517 if ((tp
->tg3_flags
& TG3_FLAG_CHIP_RESETTING
) ||
5518 (tr32(TG3PCI_PCISTATE
) & PCISTATE_INT_NOT_ACTIVE
)) {
5525 * Writing any value to intr-mbox-0 clears PCI INTA# and
5526 * chip-internal interrupt pending events.
5527 * Writing non-zero to intr-mbox-0 additional tells the
5528 * NIC to stop sending us irqs, engaging "in-intr-handler"
5531 * Flush the mailbox to de-assert the IRQ immediately to prevent
5532 * spurious interrupts. The flush impacts performance but
5533 * excessive spurious interrupts can be worse in some cases.
5535 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0x00000001);
5536 if (tg3_irq_sync(tp
))
5538 sblk
->status
&= ~SD_STATUS_UPDATED
;
5539 if (likely(tg3_has_work(tnapi
))) {
5540 prefetch(&tnapi
->rx_rcb
[tnapi
->rx_rcb_ptr
]);
5541 napi_schedule(&tnapi
->napi
);
5543 /* No work, shared interrupt perhaps? re-enable
5544 * interrupts, and flush that PCI write
5546 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
,
5550 return IRQ_RETVAL(handled
);
5553 static irqreturn_t
tg3_interrupt_tagged(int irq
, void *dev_id
)
5555 struct tg3_napi
*tnapi
= dev_id
;
5556 struct tg3
*tp
= tnapi
->tp
;
5557 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
5558 unsigned int handled
= 1;
5560 /* In INTx mode, it is possible for the interrupt to arrive at
5561 * the CPU before the status block posted prior to the interrupt.
5562 * Reading the PCI State register will confirm whether the
5563 * interrupt is ours and will flush the status block.
5565 if (unlikely(sblk
->status_tag
== tnapi
->last_irq_tag
)) {
5566 if ((tp
->tg3_flags
& TG3_FLAG_CHIP_RESETTING
) ||
5567 (tr32(TG3PCI_PCISTATE
) & PCISTATE_INT_NOT_ACTIVE
)) {
5574 * writing any value to intr-mbox-0 clears PCI INTA# and
5575 * chip-internal interrupt pending events.
5576 * writing non-zero to intr-mbox-0 additional tells the
5577 * NIC to stop sending us irqs, engaging "in-intr-handler"
5580 * Flush the mailbox to de-assert the IRQ immediately to prevent
5581 * spurious interrupts. The flush impacts performance but
5582 * excessive spurious interrupts can be worse in some cases.
5584 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0x00000001);
5587 * In a shared interrupt configuration, sometimes other devices'
5588 * interrupts will scream. We record the current status tag here
5589 * so that the above check can report that the screaming interrupts
5590 * are unhandled. Eventually they will be silenced.
5592 tnapi
->last_irq_tag
= sblk
->status_tag
;
5594 if (tg3_irq_sync(tp
))
5597 prefetch(&tnapi
->rx_rcb
[tnapi
->rx_rcb_ptr
]);
5599 napi_schedule(&tnapi
->napi
);
5602 return IRQ_RETVAL(handled
);
5605 /* ISR for interrupt test */
5606 static irqreturn_t
tg3_test_isr(int irq
, void *dev_id
)
5608 struct tg3_napi
*tnapi
= dev_id
;
5609 struct tg3
*tp
= tnapi
->tp
;
5610 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
5612 if ((sblk
->status
& SD_STATUS_UPDATED
) ||
5613 !(tr32(TG3PCI_PCISTATE
) & PCISTATE_INT_NOT_ACTIVE
)) {
5614 tg3_disable_ints(tp
);
5615 return IRQ_RETVAL(1);
5617 return IRQ_RETVAL(0);
5620 static int tg3_init_hw(struct tg3
*, int);
5621 static int tg3_halt(struct tg3
*, int, int);
5623 /* Restart hardware after configuration changes, self-test, etc.
5624 * Invoked with tp->lock held.
5626 static int tg3_restart_hw(struct tg3
*tp
, int reset_phy
)
5627 __releases(tp
->lock
)
5628 __acquires(tp
->lock
)
5632 err
= tg3_init_hw(tp
, reset_phy
);
5635 "Failed to re-initialize device, aborting\n");
5636 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
5637 tg3_full_unlock(tp
);
5638 del_timer_sync(&tp
->timer
);
5640 tg3_napi_enable(tp
);
5642 tg3_full_lock(tp
, 0);
5647 #ifdef CONFIG_NET_POLL_CONTROLLER
5648 static void tg3_poll_controller(struct net_device
*dev
)
5651 struct tg3
*tp
= netdev_priv(dev
);
5653 for (i
= 0; i
< tp
->irq_cnt
; i
++)
5654 tg3_interrupt(tp
->napi
[i
].irq_vec
, &tp
->napi
[i
]);
5658 static void tg3_reset_task(struct work_struct
*work
)
5660 struct tg3
*tp
= container_of(work
, struct tg3
, reset_task
);
5662 unsigned int restart_timer
;
5664 tg3_full_lock(tp
, 0);
5666 if (!netif_running(tp
->dev
)) {
5667 tg3_full_unlock(tp
);
5671 tg3_full_unlock(tp
);
5677 tg3_full_lock(tp
, 1);
5679 restart_timer
= tp
->tg3_flags2
& TG3_FLG2_RESTART_TIMER
;
5680 tp
->tg3_flags2
&= ~TG3_FLG2_RESTART_TIMER
;
5682 if (tp
->tg3_flags
& TG3_FLAG_TX_RECOVERY_PENDING
) {
5683 tp
->write32_tx_mbox
= tg3_write32_tx_mbox
;
5684 tp
->write32_rx_mbox
= tg3_write_flush_reg32
;
5685 tp
->tg3_flags
|= TG3_FLAG_MBOX_WRITE_REORDER
;
5686 tp
->tg3_flags
&= ~TG3_FLAG_TX_RECOVERY_PENDING
;
5689 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 0);
5690 err
= tg3_init_hw(tp
, 1);
5694 tg3_netif_start(tp
);
5697 mod_timer(&tp
->timer
, jiffies
+ 1);
5700 tg3_full_unlock(tp
);
5706 static void tg3_tx_timeout(struct net_device
*dev
)
5708 struct tg3
*tp
= netdev_priv(dev
);
5710 if (netif_msg_tx_err(tp
)) {
5711 netdev_err(dev
, "transmit timed out, resetting\n");
5715 schedule_work(&tp
->reset_task
);
5718 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5719 static inline int tg3_4g_overflow_test(dma_addr_t mapping
, int len
)
5721 u32 base
= (u32
) mapping
& 0xffffffff;
5723 return (base
> 0xffffdcc0) && (base
+ len
+ 8 < base
);
5726 /* Test for DMA addresses > 40-bit */
5727 static inline int tg3_40bit_overflow_test(struct tg3
*tp
, dma_addr_t mapping
,
5730 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5731 if (tp
->tg3_flags
& TG3_FLAG_40BIT_DMA_BUG
)
5732 return ((u64
) mapping
+ len
) > DMA_BIT_MASK(40);
5739 static void tg3_set_txd(struct tg3_napi
*, int, dma_addr_t
, int, u32
, u32
);
5741 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5742 static int tigon3_dma_hwbug_workaround(struct tg3_napi
*tnapi
,
5743 struct sk_buff
*skb
, u32 last_plus_one
,
5744 u32
*start
, u32 base_flags
, u32 mss
)
5746 struct tg3
*tp
= tnapi
->tp
;
5747 struct sk_buff
*new_skb
;
5748 dma_addr_t new_addr
= 0;
5752 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
)
5753 new_skb
= skb_copy(skb
, GFP_ATOMIC
);
5755 int more_headroom
= 4 - ((unsigned long)skb
->data
& 3);
5757 new_skb
= skb_copy_expand(skb
,
5758 skb_headroom(skb
) + more_headroom
,
5759 skb_tailroom(skb
), GFP_ATOMIC
);
5765 /* New SKB is guaranteed to be linear. */
5767 new_addr
= pci_map_single(tp
->pdev
, new_skb
->data
, new_skb
->len
,
5769 /* Make sure the mapping succeeded */
5770 if (pci_dma_mapping_error(tp
->pdev
, new_addr
)) {
5772 dev_kfree_skb(new_skb
);
5775 /* Make sure new skb does not cross any 4G boundaries.
5776 * Drop the packet if it does.
5778 } else if ((tp
->tg3_flags3
& TG3_FLG3_4G_DMA_BNDRY_BUG
) &&
5779 tg3_4g_overflow_test(new_addr
, new_skb
->len
)) {
5780 pci_unmap_single(tp
->pdev
, new_addr
, new_skb
->len
,
5783 dev_kfree_skb(new_skb
);
5786 tg3_set_txd(tnapi
, entry
, new_addr
, new_skb
->len
,
5787 base_flags
, 1 | (mss
<< 1));
5788 *start
= NEXT_TX(entry
);
5792 /* Now clean up the sw ring entries. */
5794 while (entry
!= last_plus_one
) {
5798 len
= skb_headlen(skb
);
5800 len
= skb_shinfo(skb
)->frags
[i
-1].size
;
5802 pci_unmap_single(tp
->pdev
,
5803 dma_unmap_addr(&tnapi
->tx_buffers
[entry
],
5805 len
, PCI_DMA_TODEVICE
);
5807 tnapi
->tx_buffers
[entry
].skb
= new_skb
;
5808 dma_unmap_addr_set(&tnapi
->tx_buffers
[entry
], mapping
,
5811 tnapi
->tx_buffers
[entry
].skb
= NULL
;
5813 entry
= NEXT_TX(entry
);
5822 static void tg3_set_txd(struct tg3_napi
*tnapi
, int entry
,
5823 dma_addr_t mapping
, int len
, u32 flags
,
5826 struct tg3_tx_buffer_desc
*txd
= &tnapi
->tx_ring
[entry
];
5827 int is_end
= (mss_and_is_end
& 0x1);
5828 u32 mss
= (mss_and_is_end
>> 1);
5832 flags
|= TXD_FLAG_END
;
5833 if (flags
& TXD_FLAG_VLAN
) {
5834 vlan_tag
= flags
>> 16;
5837 vlan_tag
|= (mss
<< TXD_MSS_SHIFT
);
5839 txd
->addr_hi
= ((u64
) mapping
>> 32);
5840 txd
->addr_lo
= ((u64
) mapping
& 0xffffffff);
5841 txd
->len_flags
= (len
<< TXD_LEN_SHIFT
) | flags
;
5842 txd
->vlan_tag
= vlan_tag
<< TXD_VLAN_TAG_SHIFT
;
5845 /* hard_start_xmit for devices that don't have any bugs and
5846 * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5848 static netdev_tx_t
tg3_start_xmit(struct sk_buff
*skb
,
5849 struct net_device
*dev
)
5851 struct tg3
*tp
= netdev_priv(dev
);
5852 u32 len
, entry
, base_flags
, mss
;
5854 struct tg3_napi
*tnapi
;
5855 struct netdev_queue
*txq
;
5856 unsigned int i
, last
;
5858 txq
= netdev_get_tx_queue(dev
, skb_get_queue_mapping(skb
));
5859 tnapi
= &tp
->napi
[skb_get_queue_mapping(skb
)];
5860 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)
5863 /* We are running in BH disabled context with netif_tx_lock
5864 * and TX reclaim runs via tp->napi.poll inside of a software
5865 * interrupt. Furthermore, IRQ processing runs lockless so we have
5866 * no IRQ context deadlocks to worry about either. Rejoice!
5868 if (unlikely(tg3_tx_avail(tnapi
) <= (skb_shinfo(skb
)->nr_frags
+ 1))) {
5869 if (!netif_tx_queue_stopped(txq
)) {
5870 netif_tx_stop_queue(txq
);
5872 /* This is a hard error, log it. */
5874 "BUG! Tx Ring full when queue awake!\n");
5876 return NETDEV_TX_BUSY
;
5879 entry
= tnapi
->tx_prod
;
5881 mss
= skb_shinfo(skb
)->gso_size
;
5883 int tcp_opt_len
, ip_tcp_len
;
5886 if (skb_header_cloned(skb
) &&
5887 pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
)) {
5892 if (skb_is_gso_v6(skb
)) {
5893 hdrlen
= skb_headlen(skb
) - ETH_HLEN
;
5895 struct iphdr
*iph
= ip_hdr(skb
);
5897 tcp_opt_len
= tcp_optlen(skb
);
5898 ip_tcp_len
= ip_hdrlen(skb
) + sizeof(struct tcphdr
);
5901 iph
->tot_len
= htons(mss
+ ip_tcp_len
+ tcp_opt_len
);
5902 hdrlen
= ip_tcp_len
+ tcp_opt_len
;
5905 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO_3
) {
5906 mss
|= (hdrlen
& 0xc) << 12;
5908 base_flags
|= 0x00000010;
5909 base_flags
|= (hdrlen
& 0x3e0) << 5;
5913 base_flags
|= (TXD_FLAG_CPU_PRE_DMA
|
5914 TXD_FLAG_CPU_POST_DMA
);
5916 tcp_hdr(skb
)->check
= 0;
5918 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
5919 base_flags
|= TXD_FLAG_TCPUDP_CSUM
;
5922 if (vlan_tx_tag_present(skb
))
5923 base_flags
|= (TXD_FLAG_VLAN
|
5924 (vlan_tx_tag_get(skb
) << 16));
5926 len
= skb_headlen(skb
);
5928 /* Queue skb data, a.k.a. the main skb fragment. */
5929 mapping
= pci_map_single(tp
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
5930 if (pci_dma_mapping_error(tp
->pdev
, mapping
)) {
5935 tnapi
->tx_buffers
[entry
].skb
= skb
;
5936 dma_unmap_addr_set(&tnapi
->tx_buffers
[entry
], mapping
, mapping
);
5938 if ((tp
->tg3_flags3
& TG3_FLG3_USE_JUMBO_BDFLAG
) &&
5939 !mss
&& skb
->len
> VLAN_ETH_FRAME_LEN
)
5940 base_flags
|= TXD_FLAG_JMB_PKT
;
5942 tg3_set_txd(tnapi
, entry
, mapping
, len
, base_flags
,
5943 (skb_shinfo(skb
)->nr_frags
== 0) | (mss
<< 1));
5945 entry
= NEXT_TX(entry
);
5947 /* Now loop through additional data fragments, and queue them. */
5948 if (skb_shinfo(skb
)->nr_frags
> 0) {
5949 last
= skb_shinfo(skb
)->nr_frags
- 1;
5950 for (i
= 0; i
<= last
; i
++) {
5951 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
5954 mapping
= pci_map_page(tp
->pdev
,
5957 len
, PCI_DMA_TODEVICE
);
5958 if (pci_dma_mapping_error(tp
->pdev
, mapping
))
5961 tnapi
->tx_buffers
[entry
].skb
= NULL
;
5962 dma_unmap_addr_set(&tnapi
->tx_buffers
[entry
], mapping
,
5965 tg3_set_txd(tnapi
, entry
, mapping
, len
,
5966 base_flags
, (i
== last
) | (mss
<< 1));
5968 entry
= NEXT_TX(entry
);
5972 /* Packets are ready, update Tx producer idx local and on card. */
5973 tw32_tx_mbox(tnapi
->prodmbox
, entry
);
5975 tnapi
->tx_prod
= entry
;
5976 if (unlikely(tg3_tx_avail(tnapi
) <= (MAX_SKB_FRAGS
+ 1))) {
5977 netif_tx_stop_queue(txq
);
5979 /* netif_tx_stop_queue() must be done before checking
5980 * checking tx index in tg3_tx_avail() below, because in
5981 * tg3_tx(), we update tx index before checking for
5982 * netif_tx_queue_stopped().
5985 if (tg3_tx_avail(tnapi
) > TG3_TX_WAKEUP_THRESH(tnapi
))
5986 netif_tx_wake_queue(txq
);
5992 return NETDEV_TX_OK
;
5996 entry
= tnapi
->tx_prod
;
5997 tnapi
->tx_buffers
[entry
].skb
= NULL
;
5998 pci_unmap_single(tp
->pdev
,
5999 dma_unmap_addr(&tnapi
->tx_buffers
[entry
], mapping
),
6002 for (i
= 0; i
<= last
; i
++) {
6003 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
6004 entry
= NEXT_TX(entry
);
6006 pci_unmap_page(tp
->pdev
,
6007 dma_unmap_addr(&tnapi
->tx_buffers
[entry
],
6009 frag
->size
, PCI_DMA_TODEVICE
);
6013 return NETDEV_TX_OK
;
6016 static netdev_tx_t
tg3_start_xmit_dma_bug(struct sk_buff
*,
6017 struct net_device
*);
6019 /* Use GSO to workaround a rare TSO bug that may be triggered when the
6020 * TSO header is greater than 80 bytes.
6022 static int tg3_tso_bug(struct tg3
*tp
, struct sk_buff
*skb
)
6024 struct sk_buff
*segs
, *nskb
;
6025 u32 frag_cnt_est
= skb_shinfo(skb
)->gso_segs
* 3;
6027 /* Estimate the number of fragments in the worst case */
6028 if (unlikely(tg3_tx_avail(&tp
->napi
[0]) <= frag_cnt_est
)) {
6029 netif_stop_queue(tp
->dev
);
6031 /* netif_tx_stop_queue() must be done before checking
6032 * checking tx index in tg3_tx_avail() below, because in
6033 * tg3_tx(), we update tx index before checking for
6034 * netif_tx_queue_stopped().
6037 if (tg3_tx_avail(&tp
->napi
[0]) <= frag_cnt_est
)
6038 return NETDEV_TX_BUSY
;
6040 netif_wake_queue(tp
->dev
);
6043 segs
= skb_gso_segment(skb
, tp
->dev
->features
& ~NETIF_F_TSO
);
6045 goto tg3_tso_bug_end
;
6051 tg3_start_xmit_dma_bug(nskb
, tp
->dev
);
6057 return NETDEV_TX_OK
;
6060 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
6061 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
6063 static netdev_tx_t
tg3_start_xmit_dma_bug(struct sk_buff
*skb
,
6064 struct net_device
*dev
)
6066 struct tg3
*tp
= netdev_priv(dev
);
6067 u32 len
, entry
, base_flags
, mss
;
6068 int would_hit_hwbug
;
6070 struct tg3_napi
*tnapi
;
6071 struct netdev_queue
*txq
;
6072 unsigned int i
, last
;
6074 txq
= netdev_get_tx_queue(dev
, skb_get_queue_mapping(skb
));
6075 tnapi
= &tp
->napi
[skb_get_queue_mapping(skb
)];
6076 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)
6079 /* We are running in BH disabled context with netif_tx_lock
6080 * and TX reclaim runs via tp->napi.poll inside of a software
6081 * interrupt. Furthermore, IRQ processing runs lockless so we have
6082 * no IRQ context deadlocks to worry about either. Rejoice!
6084 if (unlikely(tg3_tx_avail(tnapi
) <= (skb_shinfo(skb
)->nr_frags
+ 1))) {
6085 if (!netif_tx_queue_stopped(txq
)) {
6086 netif_tx_stop_queue(txq
);
6088 /* This is a hard error, log it. */
6090 "BUG! Tx Ring full when queue awake!\n");
6092 return NETDEV_TX_BUSY
;
6095 entry
= tnapi
->tx_prod
;
6097 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
6098 base_flags
|= TXD_FLAG_TCPUDP_CSUM
;
6100 mss
= skb_shinfo(skb
)->gso_size
;
6103 u32 tcp_opt_len
, hdr_len
;
6105 if (skb_header_cloned(skb
) &&
6106 pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
)) {
6112 tcp_opt_len
= tcp_optlen(skb
);
6114 if (skb_is_gso_v6(skb
)) {
6115 hdr_len
= skb_headlen(skb
) - ETH_HLEN
;
6119 ip_tcp_len
= ip_hdrlen(skb
) + sizeof(struct tcphdr
);
6120 hdr_len
= ip_tcp_len
+ tcp_opt_len
;
6123 iph
->tot_len
= htons(mss
+ hdr_len
);
6126 if (unlikely((ETH_HLEN
+ hdr_len
) > 80) &&
6127 (tp
->tg3_flags2
& TG3_FLG2_TSO_BUG
))
6128 return tg3_tso_bug(tp
, skb
);
6130 base_flags
|= (TXD_FLAG_CPU_PRE_DMA
|
6131 TXD_FLAG_CPU_POST_DMA
);
6133 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
) {
6134 tcp_hdr(skb
)->check
= 0;
6135 base_flags
&= ~TXD_FLAG_TCPUDP_CSUM
;
6137 tcp_hdr(skb
)->check
= ~csum_tcpudp_magic(iph
->saddr
,
6142 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO_3
) {
6143 mss
|= (hdr_len
& 0xc) << 12;
6145 base_flags
|= 0x00000010;
6146 base_flags
|= (hdr_len
& 0x3e0) << 5;
6147 } else if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO_2
)
6148 mss
|= hdr_len
<< 9;
6149 else if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO_1
) ||
6150 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
6151 if (tcp_opt_len
|| iph
->ihl
> 5) {
6154 tsflags
= (iph
->ihl
- 5) + (tcp_opt_len
>> 2);
6155 mss
|= (tsflags
<< 11);
6158 if (tcp_opt_len
|| iph
->ihl
> 5) {
6161 tsflags
= (iph
->ihl
- 5) + (tcp_opt_len
>> 2);
6162 base_flags
|= tsflags
<< 12;
6167 if (vlan_tx_tag_present(skb
))
6168 base_flags
|= (TXD_FLAG_VLAN
|
6169 (vlan_tx_tag_get(skb
) << 16));
6171 if ((tp
->tg3_flags3
& TG3_FLG3_USE_JUMBO_BDFLAG
) &&
6172 !mss
&& skb
->len
> VLAN_ETH_FRAME_LEN
)
6173 base_flags
|= TXD_FLAG_JMB_PKT
;
6175 len
= skb_headlen(skb
);
6177 mapping
= pci_map_single(tp
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
6178 if (pci_dma_mapping_error(tp
->pdev
, mapping
)) {
6183 tnapi
->tx_buffers
[entry
].skb
= skb
;
6184 dma_unmap_addr_set(&tnapi
->tx_buffers
[entry
], mapping
, mapping
);
6186 would_hit_hwbug
= 0;
6188 if ((tp
->tg3_flags3
& TG3_FLG3_SHORT_DMA_BUG
) && len
<= 8)
6189 would_hit_hwbug
= 1;
6191 if ((tp
->tg3_flags3
& TG3_FLG3_4G_DMA_BNDRY_BUG
) &&
6192 tg3_4g_overflow_test(mapping
, len
))
6193 would_hit_hwbug
= 1;
6195 if ((tp
->tg3_flags3
& TG3_FLG3_40BIT_DMA_LIMIT_BUG
) &&
6196 tg3_40bit_overflow_test(tp
, mapping
, len
))
6197 would_hit_hwbug
= 1;
6199 if (tp
->tg3_flags3
& TG3_FLG3_5701_DMA_BUG
)
6200 would_hit_hwbug
= 1;
6202 tg3_set_txd(tnapi
, entry
, mapping
, len
, base_flags
,
6203 (skb_shinfo(skb
)->nr_frags
== 0) | (mss
<< 1));
6205 entry
= NEXT_TX(entry
);
6207 /* Now loop through additional data fragments, and queue them. */
6208 if (skb_shinfo(skb
)->nr_frags
> 0) {
6209 last
= skb_shinfo(skb
)->nr_frags
- 1;
6210 for (i
= 0; i
<= last
; i
++) {
6211 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
6214 mapping
= pci_map_page(tp
->pdev
,
6217 len
, PCI_DMA_TODEVICE
);
6219 tnapi
->tx_buffers
[entry
].skb
= NULL
;
6220 dma_unmap_addr_set(&tnapi
->tx_buffers
[entry
], mapping
,
6222 if (pci_dma_mapping_error(tp
->pdev
, mapping
))
6225 if ((tp
->tg3_flags3
& TG3_FLG3_SHORT_DMA_BUG
) &&
6227 would_hit_hwbug
= 1;
6229 if ((tp
->tg3_flags3
& TG3_FLG3_4G_DMA_BNDRY_BUG
) &&
6230 tg3_4g_overflow_test(mapping
, len
))
6231 would_hit_hwbug
= 1;
6233 if ((tp
->tg3_flags3
& TG3_FLG3_40BIT_DMA_LIMIT_BUG
) &&
6234 tg3_40bit_overflow_test(tp
, mapping
, len
))
6235 would_hit_hwbug
= 1;
6237 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
6238 tg3_set_txd(tnapi
, entry
, mapping
, len
,
6239 base_flags
, (i
== last
)|(mss
<< 1));
6241 tg3_set_txd(tnapi
, entry
, mapping
, len
,
6242 base_flags
, (i
== last
));
6244 entry
= NEXT_TX(entry
);
6248 if (would_hit_hwbug
) {
6249 u32 last_plus_one
= entry
;
6252 start
= entry
- 1 - skb_shinfo(skb
)->nr_frags
;
6253 start
&= (TG3_TX_RING_SIZE
- 1);
6255 /* If the workaround fails due to memory/mapping
6256 * failure, silently drop this packet.
6258 if (tigon3_dma_hwbug_workaround(tnapi
, skb
, last_plus_one
,
6259 &start
, base_flags
, mss
))
6265 /* Packets are ready, update Tx producer idx local and on card. */
6266 tw32_tx_mbox(tnapi
->prodmbox
, entry
);
6268 tnapi
->tx_prod
= entry
;
6269 if (unlikely(tg3_tx_avail(tnapi
) <= (MAX_SKB_FRAGS
+ 1))) {
6270 netif_tx_stop_queue(txq
);
6272 /* netif_tx_stop_queue() must be done before checking
6273 * checking tx index in tg3_tx_avail() below, because in
6274 * tg3_tx(), we update tx index before checking for
6275 * netif_tx_queue_stopped().
6278 if (tg3_tx_avail(tnapi
) > TG3_TX_WAKEUP_THRESH(tnapi
))
6279 netif_tx_wake_queue(txq
);
6285 return NETDEV_TX_OK
;
6289 entry
= tnapi
->tx_prod
;
6290 tnapi
->tx_buffers
[entry
].skb
= NULL
;
6291 pci_unmap_single(tp
->pdev
,
6292 dma_unmap_addr(&tnapi
->tx_buffers
[entry
], mapping
),
6295 for (i
= 0; i
<= last
; i
++) {
6296 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
6297 entry
= NEXT_TX(entry
);
6299 pci_unmap_page(tp
->pdev
,
6300 dma_unmap_addr(&tnapi
->tx_buffers
[entry
],
6302 frag
->size
, PCI_DMA_TODEVICE
);
6306 return NETDEV_TX_OK
;
6309 static u32
tg3_fix_features(struct net_device
*dev
, u32 features
)
6311 struct tg3
*tp
= netdev_priv(dev
);
6313 if (dev
->mtu
> ETH_DATA_LEN
&& (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
6314 features
&= ~NETIF_F_ALL_TSO
;
6319 static inline void tg3_set_mtu(struct net_device
*dev
, struct tg3
*tp
,
6324 if (new_mtu
> ETH_DATA_LEN
) {
6325 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) {
6326 netdev_update_features(dev
);
6327 tp
->tg3_flags2
&= ~TG3_FLG2_TSO_CAPABLE
;
6329 tp
->tg3_flags
|= TG3_FLAG_JUMBO_RING_ENABLE
;
6332 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) {
6333 tp
->tg3_flags2
|= TG3_FLG2_TSO_CAPABLE
;
6334 netdev_update_features(dev
);
6336 tp
->tg3_flags
&= ~TG3_FLAG_JUMBO_RING_ENABLE
;
6340 static int tg3_change_mtu(struct net_device
*dev
, int new_mtu
)
6342 struct tg3
*tp
= netdev_priv(dev
);
6345 if (new_mtu
< TG3_MIN_MTU
|| new_mtu
> TG3_MAX_MTU(tp
))
6348 if (!netif_running(dev
)) {
6349 /* We'll just catch it later when the
6352 tg3_set_mtu(dev
, tp
, new_mtu
);
6360 tg3_full_lock(tp
, 1);
6362 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
6364 tg3_set_mtu(dev
, tp
, new_mtu
);
6366 err
= tg3_restart_hw(tp
, 0);
6369 tg3_netif_start(tp
);
6371 tg3_full_unlock(tp
);
6379 static void tg3_rx_prodring_free(struct tg3
*tp
,
6380 struct tg3_rx_prodring_set
*tpr
)
6384 if (tpr
!= &tp
->napi
[0].prodring
) {
6385 for (i
= tpr
->rx_std_cons_idx
; i
!= tpr
->rx_std_prod_idx
;
6386 i
= (i
+ 1) & tp
->rx_std_ring_mask
)
6387 tg3_rx_skb_free(tp
, &tpr
->rx_std_buffers
[i
],
6390 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) {
6391 for (i
= tpr
->rx_jmb_cons_idx
;
6392 i
!= tpr
->rx_jmb_prod_idx
;
6393 i
= (i
+ 1) & tp
->rx_jmb_ring_mask
) {
6394 tg3_rx_skb_free(tp
, &tpr
->rx_jmb_buffers
[i
],
6402 for (i
= 0; i
<= tp
->rx_std_ring_mask
; i
++)
6403 tg3_rx_skb_free(tp
, &tpr
->rx_std_buffers
[i
],
6406 if ((tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) &&
6407 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
6408 for (i
= 0; i
<= tp
->rx_jmb_ring_mask
; i
++)
6409 tg3_rx_skb_free(tp
, &tpr
->rx_jmb_buffers
[i
],
6414 /* Initialize rx rings for packet processing.
6416 * The chip has been shut down and the driver detached from
6417 * the networking, so no interrupts or new tx packets will
6418 * end up in the driver. tp->{tx,}lock are held and thus
6421 static int tg3_rx_prodring_alloc(struct tg3
*tp
,
6422 struct tg3_rx_prodring_set
*tpr
)
6424 u32 i
, rx_pkt_dma_sz
;
6426 tpr
->rx_std_cons_idx
= 0;
6427 tpr
->rx_std_prod_idx
= 0;
6428 tpr
->rx_jmb_cons_idx
= 0;
6429 tpr
->rx_jmb_prod_idx
= 0;
6431 if (tpr
!= &tp
->napi
[0].prodring
) {
6432 memset(&tpr
->rx_std_buffers
[0], 0,
6433 TG3_RX_STD_BUFF_RING_SIZE(tp
));
6434 if (tpr
->rx_jmb_buffers
)
6435 memset(&tpr
->rx_jmb_buffers
[0], 0,
6436 TG3_RX_JMB_BUFF_RING_SIZE(tp
));
6440 /* Zero out all descriptors. */
6441 memset(tpr
->rx_std
, 0, TG3_RX_STD_RING_BYTES(tp
));
6443 rx_pkt_dma_sz
= TG3_RX_STD_DMA_SZ
;
6444 if ((tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) &&
6445 tp
->dev
->mtu
> ETH_DATA_LEN
)
6446 rx_pkt_dma_sz
= TG3_RX_JMB_DMA_SZ
;
6447 tp
->rx_pkt_map_sz
= TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz
);
6449 /* Initialize invariants of the rings, we only set this
6450 * stuff once. This works because the card does not
6451 * write into the rx buffer posting rings.
6453 for (i
= 0; i
<= tp
->rx_std_ring_mask
; i
++) {
6454 struct tg3_rx_buffer_desc
*rxd
;
6456 rxd
= &tpr
->rx_std
[i
];
6457 rxd
->idx_len
= rx_pkt_dma_sz
<< RXD_LEN_SHIFT
;
6458 rxd
->type_flags
= (RXD_FLAG_END
<< RXD_FLAGS_SHIFT
);
6459 rxd
->opaque
= (RXD_OPAQUE_RING_STD
|
6460 (i
<< RXD_OPAQUE_INDEX_SHIFT
));
6463 /* Now allocate fresh SKBs for each rx ring. */
6464 for (i
= 0; i
< tp
->rx_pending
; i
++) {
6465 if (tg3_alloc_rx_skb(tp
, tpr
, RXD_OPAQUE_RING_STD
, i
) < 0) {
6466 netdev_warn(tp
->dev
,
6467 "Using a smaller RX standard ring. Only "
6468 "%d out of %d buffers were allocated "
6469 "successfully\n", i
, tp
->rx_pending
);
6477 if (!(tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) ||
6478 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
6481 memset(tpr
->rx_jmb
, 0, TG3_RX_JMB_RING_BYTES(tp
));
6483 if (!(tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
))
6486 for (i
= 0; i
<= tp
->rx_jmb_ring_mask
; i
++) {
6487 struct tg3_rx_buffer_desc
*rxd
;
6489 rxd
= &tpr
->rx_jmb
[i
].std
;
6490 rxd
->idx_len
= TG3_RX_JMB_DMA_SZ
<< RXD_LEN_SHIFT
;
6491 rxd
->type_flags
= (RXD_FLAG_END
<< RXD_FLAGS_SHIFT
) |
6493 rxd
->opaque
= (RXD_OPAQUE_RING_JUMBO
|
6494 (i
<< RXD_OPAQUE_INDEX_SHIFT
));
6497 for (i
= 0; i
< tp
->rx_jumbo_pending
; i
++) {
6498 if (tg3_alloc_rx_skb(tp
, tpr
, RXD_OPAQUE_RING_JUMBO
, i
) < 0) {
6499 netdev_warn(tp
->dev
,
6500 "Using a smaller RX jumbo ring. Only %d "
6501 "out of %d buffers were allocated "
6502 "successfully\n", i
, tp
->rx_jumbo_pending
);
6505 tp
->rx_jumbo_pending
= i
;
6514 tg3_rx_prodring_free(tp
, tpr
);
6518 static void tg3_rx_prodring_fini(struct tg3
*tp
,
6519 struct tg3_rx_prodring_set
*tpr
)
6521 kfree(tpr
->rx_std_buffers
);
6522 tpr
->rx_std_buffers
= NULL
;
6523 kfree(tpr
->rx_jmb_buffers
);
6524 tpr
->rx_jmb_buffers
= NULL
;
6526 dma_free_coherent(&tp
->pdev
->dev
, TG3_RX_STD_RING_BYTES(tp
),
6527 tpr
->rx_std
, tpr
->rx_std_mapping
);
6531 dma_free_coherent(&tp
->pdev
->dev
, TG3_RX_JMB_RING_BYTES(tp
),
6532 tpr
->rx_jmb
, tpr
->rx_jmb_mapping
);
6537 static int tg3_rx_prodring_init(struct tg3
*tp
,
6538 struct tg3_rx_prodring_set
*tpr
)
6540 tpr
->rx_std_buffers
= kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp
),
6542 if (!tpr
->rx_std_buffers
)
6545 tpr
->rx_std
= dma_alloc_coherent(&tp
->pdev
->dev
,
6546 TG3_RX_STD_RING_BYTES(tp
),
6547 &tpr
->rx_std_mapping
,
6552 if ((tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) &&
6553 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
6554 tpr
->rx_jmb_buffers
= kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp
),
6556 if (!tpr
->rx_jmb_buffers
)
6559 tpr
->rx_jmb
= dma_alloc_coherent(&tp
->pdev
->dev
,
6560 TG3_RX_JMB_RING_BYTES(tp
),
6561 &tpr
->rx_jmb_mapping
,
6570 tg3_rx_prodring_fini(tp
, tpr
);
6574 /* Free up pending packets in all rx/tx rings.
6576 * The chip has been shut down and the driver detached from
6577 * the networking, so no interrupts or new tx packets will
6578 * end up in the driver. tp->{tx,}lock is not held and we are not
6579 * in an interrupt context and thus may sleep.
6581 static void tg3_free_rings(struct tg3
*tp
)
6585 for (j
= 0; j
< tp
->irq_cnt
; j
++) {
6586 struct tg3_napi
*tnapi
= &tp
->napi
[j
];
6588 tg3_rx_prodring_free(tp
, &tnapi
->prodring
);
6590 if (!tnapi
->tx_buffers
)
6593 for (i
= 0; i
< TG3_TX_RING_SIZE
; ) {
6594 struct ring_info
*txp
;
6595 struct sk_buff
*skb
;
6598 txp
= &tnapi
->tx_buffers
[i
];
6606 pci_unmap_single(tp
->pdev
,
6607 dma_unmap_addr(txp
, mapping
),
6614 for (k
= 0; k
< skb_shinfo(skb
)->nr_frags
; k
++) {
6615 txp
= &tnapi
->tx_buffers
[i
& (TG3_TX_RING_SIZE
- 1)];
6616 pci_unmap_page(tp
->pdev
,
6617 dma_unmap_addr(txp
, mapping
),
6618 skb_shinfo(skb
)->frags
[k
].size
,
6623 dev_kfree_skb_any(skb
);
6628 /* Initialize tx/rx rings for packet processing.
6630 * The chip has been shut down and the driver detached from
6631 * the networking, so no interrupts or new tx packets will
6632 * end up in the driver. tp->{tx,}lock are held and thus
6635 static int tg3_init_rings(struct tg3
*tp
)
6639 /* Free up all the SKBs. */
6642 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
6643 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
6645 tnapi
->last_tag
= 0;
6646 tnapi
->last_irq_tag
= 0;
6647 tnapi
->hw_status
->status
= 0;
6648 tnapi
->hw_status
->status_tag
= 0;
6649 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
6654 memset(tnapi
->tx_ring
, 0, TG3_TX_RING_BYTES
);
6656 tnapi
->rx_rcb_ptr
= 0;
6658 memset(tnapi
->rx_rcb
, 0, TG3_RX_RCB_RING_BYTES(tp
));
6660 if (tg3_rx_prodring_alloc(tp
, &tnapi
->prodring
)) {
6670 * Must not be invoked with interrupt sources disabled and
6671 * the hardware shutdown down.
6673 static void tg3_free_consistent(struct tg3
*tp
)
6677 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
6678 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
6680 if (tnapi
->tx_ring
) {
6681 dma_free_coherent(&tp
->pdev
->dev
, TG3_TX_RING_BYTES
,
6682 tnapi
->tx_ring
, tnapi
->tx_desc_mapping
);
6683 tnapi
->tx_ring
= NULL
;
6686 kfree(tnapi
->tx_buffers
);
6687 tnapi
->tx_buffers
= NULL
;
6689 if (tnapi
->rx_rcb
) {
6690 dma_free_coherent(&tp
->pdev
->dev
,
6691 TG3_RX_RCB_RING_BYTES(tp
),
6693 tnapi
->rx_rcb_mapping
);
6694 tnapi
->rx_rcb
= NULL
;
6697 tg3_rx_prodring_fini(tp
, &tnapi
->prodring
);
6699 if (tnapi
->hw_status
) {
6700 dma_free_coherent(&tp
->pdev
->dev
, TG3_HW_STATUS_SIZE
,
6702 tnapi
->status_mapping
);
6703 tnapi
->hw_status
= NULL
;
6708 dma_free_coherent(&tp
->pdev
->dev
, sizeof(struct tg3_hw_stats
),
6709 tp
->hw_stats
, tp
->stats_mapping
);
6710 tp
->hw_stats
= NULL
;
6715 * Must not be invoked with interrupt sources disabled and
6716 * the hardware shutdown down. Can sleep.
6718 static int tg3_alloc_consistent(struct tg3
*tp
)
6722 tp
->hw_stats
= dma_alloc_coherent(&tp
->pdev
->dev
,
6723 sizeof(struct tg3_hw_stats
),
6729 memset(tp
->hw_stats
, 0, sizeof(struct tg3_hw_stats
));
6731 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
6732 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
6733 struct tg3_hw_status
*sblk
;
6735 tnapi
->hw_status
= dma_alloc_coherent(&tp
->pdev
->dev
,
6737 &tnapi
->status_mapping
,
6739 if (!tnapi
->hw_status
)
6742 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
6743 sblk
= tnapi
->hw_status
;
6745 if (tg3_rx_prodring_init(tp
, &tnapi
->prodring
))
6748 /* If multivector TSS is enabled, vector 0 does not handle
6749 * tx interrupts. Don't allocate any resources for it.
6751 if ((!i
&& !(tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)) ||
6752 (i
&& (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
))) {
6753 tnapi
->tx_buffers
= kzalloc(sizeof(struct ring_info
) *
6756 if (!tnapi
->tx_buffers
)
6759 tnapi
->tx_ring
= dma_alloc_coherent(&tp
->pdev
->dev
,
6761 &tnapi
->tx_desc_mapping
,
6763 if (!tnapi
->tx_ring
)
6768 * When RSS is enabled, the status block format changes
6769 * slightly. The "rx_jumbo_consumer", "reserved",
6770 * and "rx_mini_consumer" members get mapped to the
6771 * other three rx return ring producer indexes.
6775 tnapi
->rx_rcb_prod_idx
= &sblk
->idx
[0].rx_producer
;
6778 tnapi
->rx_rcb_prod_idx
= &sblk
->rx_jumbo_consumer
;
6781 tnapi
->rx_rcb_prod_idx
= &sblk
->reserved
;
6784 tnapi
->rx_rcb_prod_idx
= &sblk
->rx_mini_consumer
;
6789 * If multivector RSS is enabled, vector 0 does not handle
6790 * rx or tx interrupts. Don't allocate any resources for it.
6792 if (!i
&& (tp
->tg3_flags3
& TG3_FLG3_ENABLE_RSS
))
6795 tnapi
->rx_rcb
= dma_alloc_coherent(&tp
->pdev
->dev
,
6796 TG3_RX_RCB_RING_BYTES(tp
),
6797 &tnapi
->rx_rcb_mapping
,
6802 memset(tnapi
->rx_rcb
, 0, TG3_RX_RCB_RING_BYTES(tp
));
6808 tg3_free_consistent(tp
);
6812 #define MAX_WAIT_CNT 1000
6814 /* To stop a block, clear the enable bit and poll till it
6815 * clears. tp->lock is held.
6817 static int tg3_stop_block(struct tg3
*tp
, unsigned long ofs
, u32 enable_bit
, int silent
)
6822 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
6829 /* We can't enable/disable these bits of the
6830 * 5705/5750, just say success.
6843 for (i
= 0; i
< MAX_WAIT_CNT
; i
++) {
6846 if ((val
& enable_bit
) == 0)
6850 if (i
== MAX_WAIT_CNT
&& !silent
) {
6851 dev_err(&tp
->pdev
->dev
,
6852 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6860 /* tp->lock is held. */
6861 static int tg3_abort_hw(struct tg3
*tp
, int silent
)
6865 tg3_disable_ints(tp
);
6867 tp
->rx_mode
&= ~RX_MODE_ENABLE
;
6868 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
6871 err
= tg3_stop_block(tp
, RCVBDI_MODE
, RCVBDI_MODE_ENABLE
, silent
);
6872 err
|= tg3_stop_block(tp
, RCVLPC_MODE
, RCVLPC_MODE_ENABLE
, silent
);
6873 err
|= tg3_stop_block(tp
, RCVLSC_MODE
, RCVLSC_MODE_ENABLE
, silent
);
6874 err
|= tg3_stop_block(tp
, RCVDBDI_MODE
, RCVDBDI_MODE_ENABLE
, silent
);
6875 err
|= tg3_stop_block(tp
, RCVDCC_MODE
, RCVDCC_MODE_ENABLE
, silent
);
6876 err
|= tg3_stop_block(tp
, RCVCC_MODE
, RCVCC_MODE_ENABLE
, silent
);
6878 err
|= tg3_stop_block(tp
, SNDBDS_MODE
, SNDBDS_MODE_ENABLE
, silent
);
6879 err
|= tg3_stop_block(tp
, SNDBDI_MODE
, SNDBDI_MODE_ENABLE
, silent
);
6880 err
|= tg3_stop_block(tp
, SNDDATAI_MODE
, SNDDATAI_MODE_ENABLE
, silent
);
6881 err
|= tg3_stop_block(tp
, RDMAC_MODE
, RDMAC_MODE_ENABLE
, silent
);
6882 err
|= tg3_stop_block(tp
, SNDDATAC_MODE
, SNDDATAC_MODE_ENABLE
, silent
);
6883 err
|= tg3_stop_block(tp
, DMAC_MODE
, DMAC_MODE_ENABLE
, silent
);
6884 err
|= tg3_stop_block(tp
, SNDBDC_MODE
, SNDBDC_MODE_ENABLE
, silent
);
6886 tp
->mac_mode
&= ~MAC_MODE_TDE_ENABLE
;
6887 tw32_f(MAC_MODE
, tp
->mac_mode
);
6890 tp
->tx_mode
&= ~TX_MODE_ENABLE
;
6891 tw32_f(MAC_TX_MODE
, tp
->tx_mode
);
6893 for (i
= 0; i
< MAX_WAIT_CNT
; i
++) {
6895 if (!(tr32(MAC_TX_MODE
) & TX_MODE_ENABLE
))
6898 if (i
>= MAX_WAIT_CNT
) {
6899 dev_err(&tp
->pdev
->dev
,
6900 "%s timed out, TX_MODE_ENABLE will not clear "
6901 "MAC_TX_MODE=%08x\n", __func__
, tr32(MAC_TX_MODE
));
6905 err
|= tg3_stop_block(tp
, HOSTCC_MODE
, HOSTCC_MODE_ENABLE
, silent
);
6906 err
|= tg3_stop_block(tp
, WDMAC_MODE
, WDMAC_MODE_ENABLE
, silent
);
6907 err
|= tg3_stop_block(tp
, MBFREE_MODE
, MBFREE_MODE_ENABLE
, silent
);
6909 tw32(FTQ_RESET
, 0xffffffff);
6910 tw32(FTQ_RESET
, 0x00000000);
6912 err
|= tg3_stop_block(tp
, BUFMGR_MODE
, BUFMGR_MODE_ENABLE
, silent
);
6913 err
|= tg3_stop_block(tp
, MEMARB_MODE
, MEMARB_MODE_ENABLE
, silent
);
6915 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
6916 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
6917 if (tnapi
->hw_status
)
6918 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
6921 memset(tp
->hw_stats
, 0, sizeof(struct tg3_hw_stats
));
6926 static void tg3_ape_send_event(struct tg3
*tp
, u32 event
)
6931 /* NCSI does not support APE events */
6932 if (tp
->tg3_flags3
& TG3_FLG3_APE_HAS_NCSI
)
6935 apedata
= tg3_ape_read32(tp
, TG3_APE_SEG_SIG
);
6936 if (apedata
!= APE_SEG_SIG_MAGIC
)
6939 apedata
= tg3_ape_read32(tp
, TG3_APE_FW_STATUS
);
6940 if (!(apedata
& APE_FW_STATUS_READY
))
6943 /* Wait for up to 1 millisecond for APE to service previous event. */
6944 for (i
= 0; i
< 10; i
++) {
6945 if (tg3_ape_lock(tp
, TG3_APE_LOCK_MEM
))
6948 apedata
= tg3_ape_read32(tp
, TG3_APE_EVENT_STATUS
);
6950 if (!(apedata
& APE_EVENT_STATUS_EVENT_PENDING
))
6951 tg3_ape_write32(tp
, TG3_APE_EVENT_STATUS
,
6952 event
| APE_EVENT_STATUS_EVENT_PENDING
);
6954 tg3_ape_unlock(tp
, TG3_APE_LOCK_MEM
);
6956 if (!(apedata
& APE_EVENT_STATUS_EVENT_PENDING
))
6962 if (!(apedata
& APE_EVENT_STATUS_EVENT_PENDING
))
6963 tg3_ape_write32(tp
, TG3_APE_EVENT
, APE_EVENT_1
);
6966 static void tg3_ape_driver_state_change(struct tg3
*tp
, int kind
)
6971 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
))
6975 case RESET_KIND_INIT
:
6976 tg3_ape_write32(tp
, TG3_APE_HOST_SEG_SIG
,
6977 APE_HOST_SEG_SIG_MAGIC
);
6978 tg3_ape_write32(tp
, TG3_APE_HOST_SEG_LEN
,
6979 APE_HOST_SEG_LEN_MAGIC
);
6980 apedata
= tg3_ape_read32(tp
, TG3_APE_HOST_INIT_COUNT
);
6981 tg3_ape_write32(tp
, TG3_APE_HOST_INIT_COUNT
, ++apedata
);
6982 tg3_ape_write32(tp
, TG3_APE_HOST_DRIVER_ID
,
6983 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM
, TG3_MIN_NUM
));
6984 tg3_ape_write32(tp
, TG3_APE_HOST_BEHAVIOR
,
6985 APE_HOST_BEHAV_NO_PHYLOCK
);
6986 tg3_ape_write32(tp
, TG3_APE_HOST_DRVR_STATE
,
6987 TG3_APE_HOST_DRVR_STATE_START
);
6989 event
= APE_EVENT_STATUS_STATE_START
;
6991 case RESET_KIND_SHUTDOWN
:
6992 /* With the interface we are currently using,
6993 * APE does not track driver state. Wiping
6994 * out the HOST SEGMENT SIGNATURE forces
6995 * the APE to assume OS absent status.
6997 tg3_ape_write32(tp
, TG3_APE_HOST_SEG_SIG
, 0x0);
6999 if (device_may_wakeup(&tp
->pdev
->dev
) &&
7000 (tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
)) {
7001 tg3_ape_write32(tp
, TG3_APE_HOST_WOL_SPEED
,
7002 TG3_APE_HOST_WOL_SPEED_AUTO
);
7003 apedata
= TG3_APE_HOST_DRVR_STATE_WOL
;
7005 apedata
= TG3_APE_HOST_DRVR_STATE_UNLOAD
;
7007 tg3_ape_write32(tp
, TG3_APE_HOST_DRVR_STATE
, apedata
);
7009 event
= APE_EVENT_STATUS_STATE_UNLOAD
;
7011 case RESET_KIND_SUSPEND
:
7012 event
= APE_EVENT_STATUS_STATE_SUSPEND
;
7018 event
|= APE_EVENT_STATUS_DRIVER_EVNT
| APE_EVENT_STATUS_STATE_CHNGE
;
7020 tg3_ape_send_event(tp
, event
);
7023 /* tp->lock is held. */
7024 static void tg3_write_sig_pre_reset(struct tg3
*tp
, int kind
)
7026 tg3_write_mem(tp
, NIC_SRAM_FIRMWARE_MBOX
,
7027 NIC_SRAM_FIRMWARE_MBOX_MAGIC1
);
7029 if (tp
->tg3_flags2
& TG3_FLG2_ASF_NEW_HANDSHAKE
) {
7031 case RESET_KIND_INIT
:
7032 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
7036 case RESET_KIND_SHUTDOWN
:
7037 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
7041 case RESET_KIND_SUSPEND
:
7042 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
7051 if (kind
== RESET_KIND_INIT
||
7052 kind
== RESET_KIND_SUSPEND
)
7053 tg3_ape_driver_state_change(tp
, kind
);
7056 /* tp->lock is held. */
7057 static void tg3_write_sig_post_reset(struct tg3
*tp
, int kind
)
7059 if (tp
->tg3_flags2
& TG3_FLG2_ASF_NEW_HANDSHAKE
) {
7061 case RESET_KIND_INIT
:
7062 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
7063 DRV_STATE_START_DONE
);
7066 case RESET_KIND_SHUTDOWN
:
7067 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
7068 DRV_STATE_UNLOAD_DONE
);
7076 if (kind
== RESET_KIND_SHUTDOWN
)
7077 tg3_ape_driver_state_change(tp
, kind
);
7080 /* tp->lock is held. */
7081 static void tg3_write_sig_legacy(struct tg3
*tp
, int kind
)
7083 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) {
7085 case RESET_KIND_INIT
:
7086 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
7090 case RESET_KIND_SHUTDOWN
:
7091 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
7095 case RESET_KIND_SUSPEND
:
7096 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
7106 static int tg3_poll_fw(struct tg3
*tp
)
7111 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
7112 /* Wait up to 20ms for init done. */
7113 for (i
= 0; i
< 200; i
++) {
7114 if (tr32(VCPU_STATUS
) & VCPU_STATUS_INIT_DONE
)
7121 /* Wait for firmware initialization to complete. */
7122 for (i
= 0; i
< 100000; i
++) {
7123 tg3_read_mem(tp
, NIC_SRAM_FIRMWARE_MBOX
, &val
);
7124 if (val
== ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1
)
7129 /* Chip might not be fitted with firmware. Some Sun onboard
7130 * parts are configured like that. So don't signal the timeout
7131 * of the above loop as an error, but do report the lack of
7132 * running firmware once.
7135 !(tp
->tg3_flags2
& TG3_FLG2_NO_FWARE_REPORTED
)) {
7136 tp
->tg3_flags2
|= TG3_FLG2_NO_FWARE_REPORTED
;
7138 netdev_info(tp
->dev
, "No firmware running\n");
7141 if (tp
->pci_chip_rev_id
== CHIPREV_ID_57765_A0
) {
7142 /* The 57765 A0 needs a little more
7143 * time to do some important work.
7151 /* Save PCI command register before chip reset */
7152 static void tg3_save_pci_state(struct tg3
*tp
)
7154 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &tp
->pci_cmd
);
7157 /* Restore PCI state after chip reset */
7158 static void tg3_restore_pci_state(struct tg3
*tp
)
7162 /* Re-enable indirect register accesses. */
7163 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
7164 tp
->misc_host_ctrl
);
7166 /* Set MAX PCI retry to zero. */
7167 val
= (PCISTATE_ROM_ENABLE
| PCISTATE_ROM_RETRY_ENABLE
);
7168 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
&&
7169 (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
))
7170 val
|= PCISTATE_RETRY_SAME_DMA
;
7171 /* Allow reads and writes to the APE register and memory space. */
7172 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
7173 val
|= PCISTATE_ALLOW_APE_CTLSPC_WR
|
7174 PCISTATE_ALLOW_APE_SHMEM_WR
|
7175 PCISTATE_ALLOW_APE_PSPACE_WR
;
7176 pci_write_config_dword(tp
->pdev
, TG3PCI_PCISTATE
, val
);
7178 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, tp
->pci_cmd
);
7180 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5785
) {
7181 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)
7182 pcie_set_readrq(tp
->pdev
, tp
->pcie_readrq
);
7184 pci_write_config_byte(tp
->pdev
, PCI_CACHE_LINE_SIZE
,
7185 tp
->pci_cacheline_sz
);
7186 pci_write_config_byte(tp
->pdev
, PCI_LATENCY_TIMER
,
7191 /* Make sure PCI-X relaxed ordering bit is clear. */
7192 if (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) {
7195 pci_read_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
7197 pcix_cmd
&= ~PCI_X_CMD_ERO
;
7198 pci_write_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
7202 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) {
7204 /* Chip reset on 5780 will reset MSI enable bit,
7205 * so need to restore it.
7207 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
7210 pci_read_config_word(tp
->pdev
,
7211 tp
->msi_cap
+ PCI_MSI_FLAGS
,
7213 pci_write_config_word(tp
->pdev
,
7214 tp
->msi_cap
+ PCI_MSI_FLAGS
,
7215 ctrl
| PCI_MSI_FLAGS_ENABLE
);
7216 val
= tr32(MSGINT_MODE
);
7217 tw32(MSGINT_MODE
, val
| MSGINT_MODE_ENABLE
);
7222 static void tg3_stop_fw(struct tg3
*);
7224 /* tp->lock is held. */
7225 static int tg3_chip_reset(struct tg3
*tp
)
7228 void (*write_op
)(struct tg3
*, u32
, u32
);
7233 tg3_ape_lock(tp
, TG3_APE_LOCK_GRC
);
7235 /* No matching tg3_nvram_unlock() after this because
7236 * chip reset below will undo the nvram lock.
7238 tp
->nvram_lock_cnt
= 0;
7240 /* GRC_MISC_CFG core clock reset will clear the memory
7241 * enable bit in PCI register 4 and the MSI enable bit
7242 * on some chips, so we save relevant registers here.
7244 tg3_save_pci_state(tp
);
7246 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
||
7247 (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
))
7248 tw32(GRC_FASTBOOT_PC
, 0);
7251 * We must avoid the readl() that normally takes place.
7252 * It locks machines, causes machine checks, and other
7253 * fun things. So, temporarily disable the 5701
7254 * hardware workaround, while we do the reset.
7256 write_op
= tp
->write32
;
7257 if (write_op
== tg3_write_flush_reg32
)
7258 tp
->write32
= tg3_write32
;
7260 /* Prevent the irq handler from reading or writing PCI registers
7261 * during chip reset when the memory enable bit in the PCI command
7262 * register may be cleared. The chip does not generate interrupt
7263 * at this time, but the irq handler may still be called due to irq
7264 * sharing or irqpoll.
7266 tp
->tg3_flags
|= TG3_FLAG_CHIP_RESETTING
;
7267 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
7268 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
7269 if (tnapi
->hw_status
) {
7270 tnapi
->hw_status
->status
= 0;
7271 tnapi
->hw_status
->status_tag
= 0;
7273 tnapi
->last_tag
= 0;
7274 tnapi
->last_irq_tag
= 0;
7278 for (i
= 0; i
< tp
->irq_cnt
; i
++)
7279 synchronize_irq(tp
->napi
[i
].irq_vec
);
7281 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
) {
7282 val
= tr32(TG3_PCIE_LNKCTL
) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN
;
7283 tw32(TG3_PCIE_LNKCTL
, val
| TG3_PCIE_LNKCTL_L1_PLL_PD_DIS
);
7287 val
= GRC_MISC_CFG_CORECLK_RESET
;
7289 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
7290 /* Force PCIe 1.0a mode */
7291 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5785
&&
7292 !(tp
->tg3_flags3
& TG3_FLG3_57765_PLUS
) &&
7293 tr32(TG3_PCIE_PHY_TSTCTL
) ==
7294 (TG3_PCIE_PHY_TSTCTL_PCIE10
| TG3_PCIE_PHY_TSTCTL_PSCRAM
))
7295 tw32(TG3_PCIE_PHY_TSTCTL
, TG3_PCIE_PHY_TSTCTL_PSCRAM
);
7297 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
) {
7298 tw32(GRC_MISC_CFG
, (1 << 29));
7303 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
7304 tw32(VCPU_STATUS
, tr32(VCPU_STATUS
) | VCPU_STATUS_DRV_RESET
);
7305 tw32(GRC_VCPU_EXT_CTRL
,
7306 tr32(GRC_VCPU_EXT_CTRL
) & ~GRC_VCPU_EXT_CTRL_HALT_CPU
);
7309 /* Manage gphy power for all CPMU absent PCIe devices. */
7310 if ((tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
7311 !(tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
))
7312 val
|= GRC_MISC_CFG_KEEP_GPHY_POWER
;
7314 tw32(GRC_MISC_CFG
, val
);
7316 /* restore 5701 hardware bug workaround write method */
7317 tp
->write32
= write_op
;
7319 /* Unfortunately, we have to delay before the PCI read back.
7320 * Some 575X chips even will not respond to a PCI cfg access
7321 * when the reset command is given to the chip.
7323 * How do these hardware designers expect things to work
7324 * properly if the PCI write is posted for a long period
7325 * of time? It is always necessary to have some method by
7326 * which a register read back can occur to push the write
7327 * out which does the reset.
7329 * For most tg3 variants the trick below was working.
7334 /* Flush PCI posted writes. The normal MMIO registers
7335 * are inaccessible at this time so this is the only
7336 * way to make this reliably (actually, this is no longer
7337 * the case, see above). I tried to use indirect
7338 * register read/write but this upset some 5701 variants.
7340 pci_read_config_dword(tp
->pdev
, PCI_COMMAND
, &val
);
7344 if ((tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) && tp
->pcie_cap
) {
7347 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5750_A0
) {
7351 /* Wait for link training to complete. */
7352 for (i
= 0; i
< 5000; i
++)
7355 pci_read_config_dword(tp
->pdev
, 0xc4, &cfg_val
);
7356 pci_write_config_dword(tp
->pdev
, 0xc4,
7357 cfg_val
| (1 << 15));
7360 /* Clear the "no snoop" and "relaxed ordering" bits. */
7361 pci_read_config_word(tp
->pdev
,
7362 tp
->pcie_cap
+ PCI_EXP_DEVCTL
,
7364 val16
&= ~(PCI_EXP_DEVCTL_RELAX_EN
|
7365 PCI_EXP_DEVCTL_NOSNOOP_EN
);
7367 * Older PCIe devices only support the 128 byte
7368 * MPS setting. Enforce the restriction.
7370 if (!(tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
))
7371 val16
&= ~PCI_EXP_DEVCTL_PAYLOAD
;
7372 pci_write_config_word(tp
->pdev
,
7373 tp
->pcie_cap
+ PCI_EXP_DEVCTL
,
7376 pcie_set_readrq(tp
->pdev
, tp
->pcie_readrq
);
7378 /* Clear error status */
7379 pci_write_config_word(tp
->pdev
,
7380 tp
->pcie_cap
+ PCI_EXP_DEVSTA
,
7381 PCI_EXP_DEVSTA_CED
|
7382 PCI_EXP_DEVSTA_NFED
|
7383 PCI_EXP_DEVSTA_FED
|
7384 PCI_EXP_DEVSTA_URD
);
7387 tg3_restore_pci_state(tp
);
7389 tp
->tg3_flags
&= ~(TG3_FLAG_CHIP_RESETTING
|
7390 TG3_FLAG_ERROR_PROCESSED
);
7393 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)
7394 val
= tr32(MEMARB_MODE
);
7395 tw32(MEMARB_MODE
, val
| MEMARB_MODE_ENABLE
);
7397 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5750_A3
) {
7399 tw32(0x5000, 0x400);
7402 tw32(GRC_MODE
, tp
->grc_mode
);
7404 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A0
) {
7407 tw32(0xc4, val
| (1 << 15));
7410 if ((tp
->nic_sram_data_cfg
& NIC_SRAM_DATA_CFG_MINI_PCI
) != 0 &&
7411 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
7412 tp
->pci_clock_ctrl
|= CLOCK_CTRL_CLKRUN_OENABLE
;
7413 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A0
)
7414 tp
->pci_clock_ctrl
|= CLOCK_CTRL_FORCE_CLKRUN
;
7415 tw32(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
);
7418 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
7419 tp
->mac_mode
= MAC_MODE_APE_TX_EN
|
7420 MAC_MODE_APE_RX_EN
|
7421 MAC_MODE_TDE_ENABLE
;
7423 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) {
7424 tp
->mac_mode
|= MAC_MODE_PORT_MODE_TBI
;
7426 } else if (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
) {
7427 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
7432 tw32_f(MAC_MODE
, val
);
7435 tg3_ape_unlock(tp
, TG3_APE_LOCK_GRC
);
7437 err
= tg3_poll_fw(tp
);
7443 if ((tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) &&
7444 tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
&&
7445 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5785
&&
7446 !(tp
->tg3_flags3
& TG3_FLG3_57765_PLUS
)) {
7449 tw32(0x7c00, val
| (1 << 25));
7452 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5720
) {
7453 val
= tr32(TG3_CPMU_CLCK_ORIDE
);
7454 tw32(TG3_CPMU_CLCK_ORIDE
, val
& ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN
);
7457 /* Reprobe ASF enable state. */
7458 tp
->tg3_flags
&= ~TG3_FLAG_ENABLE_ASF
;
7459 tp
->tg3_flags2
&= ~TG3_FLG2_ASF_NEW_HANDSHAKE
;
7460 tg3_read_mem(tp
, NIC_SRAM_DATA_SIG
, &val
);
7461 if (val
== NIC_SRAM_DATA_SIG_MAGIC
) {
7464 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG
, &nic_cfg
);
7465 if (nic_cfg
& NIC_SRAM_DATA_CFG_ASF_ENABLE
) {
7466 tp
->tg3_flags
|= TG3_FLAG_ENABLE_ASF
;
7467 tp
->last_event_jiffies
= jiffies
;
7468 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
7469 tp
->tg3_flags2
|= TG3_FLG2_ASF_NEW_HANDSHAKE
;
7476 /* tp->lock is held. */
7477 static void tg3_stop_fw(struct tg3
*tp
)
7479 if ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) &&
7480 !(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)) {
7481 /* Wait for RX cpu to ACK the previous event. */
7482 tg3_wait_for_event_ack(tp
);
7484 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_MBOX
, FWCMD_NICDRV_PAUSE_FW
);
7486 tg3_generate_fw_event(tp
);
7488 /* Wait for RX cpu to ACK this event. */
7489 tg3_wait_for_event_ack(tp
);
7493 /* tp->lock is held. */
7494 static int tg3_halt(struct tg3
*tp
, int kind
, int silent
)
7500 tg3_write_sig_pre_reset(tp
, kind
);
7502 tg3_abort_hw(tp
, silent
);
7503 err
= tg3_chip_reset(tp
);
7505 __tg3_set_mac_addr(tp
, 0);
7507 tg3_write_sig_legacy(tp
, kind
);
7508 tg3_write_sig_post_reset(tp
, kind
);
7516 #define RX_CPU_SCRATCH_BASE 0x30000
7517 #define RX_CPU_SCRATCH_SIZE 0x04000
7518 #define TX_CPU_SCRATCH_BASE 0x34000
7519 #define TX_CPU_SCRATCH_SIZE 0x04000
7521 /* tp->lock is held. */
7522 static int tg3_halt_cpu(struct tg3
*tp
, u32 offset
)
7526 BUG_ON(offset
== TX_CPU_BASE
&&
7527 (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
));
7529 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
7530 u32 val
= tr32(GRC_VCPU_EXT_CTRL
);
7532 tw32(GRC_VCPU_EXT_CTRL
, val
| GRC_VCPU_EXT_CTRL_HALT_CPU
);
7535 if (offset
== RX_CPU_BASE
) {
7536 for (i
= 0; i
< 10000; i
++) {
7537 tw32(offset
+ CPU_STATE
, 0xffffffff);
7538 tw32(offset
+ CPU_MODE
, CPU_MODE_HALT
);
7539 if (tr32(offset
+ CPU_MODE
) & CPU_MODE_HALT
)
7543 tw32(offset
+ CPU_STATE
, 0xffffffff);
7544 tw32_f(offset
+ CPU_MODE
, CPU_MODE_HALT
);
7547 for (i
= 0; i
< 10000; i
++) {
7548 tw32(offset
+ CPU_STATE
, 0xffffffff);
7549 tw32(offset
+ CPU_MODE
, CPU_MODE_HALT
);
7550 if (tr32(offset
+ CPU_MODE
) & CPU_MODE_HALT
)
7556 netdev_err(tp
->dev
, "%s timed out, %s CPU\n",
7557 __func__
, offset
== RX_CPU_BASE
? "RX" : "TX");
7561 /* Clear firmware's nvram arbitration. */
7562 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
)
7563 tw32(NVRAM_SWARB
, SWARB_REQ_CLR0
);
7568 unsigned int fw_base
;
7569 unsigned int fw_len
;
7570 const __be32
*fw_data
;
7573 /* tp->lock is held. */
7574 static int tg3_load_firmware_cpu(struct tg3
*tp
, u32 cpu_base
, u32 cpu_scratch_base
,
7575 int cpu_scratch_size
, struct fw_info
*info
)
7577 int err
, lock_err
, i
;
7578 void (*write_op
)(struct tg3
*, u32
, u32
);
7580 if (cpu_base
== TX_CPU_BASE
&&
7581 (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
7583 "%s: Trying to load TX cpu firmware which is 5705\n",
7588 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
7589 write_op
= tg3_write_mem
;
7591 write_op
= tg3_write_indirect_reg32
;
7593 /* It is possible that bootcode is still loading at this point.
7594 * Get the nvram lock first before halting the cpu.
7596 lock_err
= tg3_nvram_lock(tp
);
7597 err
= tg3_halt_cpu(tp
, cpu_base
);
7599 tg3_nvram_unlock(tp
);
7603 for (i
= 0; i
< cpu_scratch_size
; i
+= sizeof(u32
))
7604 write_op(tp
, cpu_scratch_base
+ i
, 0);
7605 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
7606 tw32(cpu_base
+ CPU_MODE
, tr32(cpu_base
+CPU_MODE
)|CPU_MODE_HALT
);
7607 for (i
= 0; i
< (info
->fw_len
/ sizeof(u32
)); i
++)
7608 write_op(tp
, (cpu_scratch_base
+
7609 (info
->fw_base
& 0xffff) +
7611 be32_to_cpu(info
->fw_data
[i
]));
7619 /* tp->lock is held. */
7620 static int tg3_load_5701_a0_firmware_fix(struct tg3
*tp
)
7622 struct fw_info info
;
7623 const __be32
*fw_data
;
7626 fw_data
= (void *)tp
->fw
->data
;
7628 /* Firmware blob starts with version numbers, followed by
7629 start address and length. We are setting complete length.
7630 length = end_address_of_bss - start_address_of_text.
7631 Remainder is the blob to be loaded contiguously
7632 from start address. */
7634 info
.fw_base
= be32_to_cpu(fw_data
[1]);
7635 info
.fw_len
= tp
->fw
->size
- 12;
7636 info
.fw_data
= &fw_data
[3];
7638 err
= tg3_load_firmware_cpu(tp
, RX_CPU_BASE
,
7639 RX_CPU_SCRATCH_BASE
, RX_CPU_SCRATCH_SIZE
,
7644 err
= tg3_load_firmware_cpu(tp
, TX_CPU_BASE
,
7645 TX_CPU_SCRATCH_BASE
, TX_CPU_SCRATCH_SIZE
,
7650 /* Now startup only the RX cpu. */
7651 tw32(RX_CPU_BASE
+ CPU_STATE
, 0xffffffff);
7652 tw32_f(RX_CPU_BASE
+ CPU_PC
, info
.fw_base
);
7654 for (i
= 0; i
< 5; i
++) {
7655 if (tr32(RX_CPU_BASE
+ CPU_PC
) == info
.fw_base
)
7657 tw32(RX_CPU_BASE
+ CPU_STATE
, 0xffffffff);
7658 tw32(RX_CPU_BASE
+ CPU_MODE
, CPU_MODE_HALT
);
7659 tw32_f(RX_CPU_BASE
+ CPU_PC
, info
.fw_base
);
7663 netdev_err(tp
->dev
, "%s fails to set RX CPU PC, is %08x "
7664 "should be %08x\n", __func__
,
7665 tr32(RX_CPU_BASE
+ CPU_PC
), info
.fw_base
);
7668 tw32(RX_CPU_BASE
+ CPU_STATE
, 0xffffffff);
7669 tw32_f(RX_CPU_BASE
+ CPU_MODE
, 0x00000000);
7674 /* 5705 needs a special version of the TSO firmware. */
7676 /* tp->lock is held. */
7677 static int tg3_load_tso_firmware(struct tg3
*tp
)
7679 struct fw_info info
;
7680 const __be32
*fw_data
;
7681 unsigned long cpu_base
, cpu_scratch_base
, cpu_scratch_size
;
7684 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
7687 fw_data
= (void *)tp
->fw
->data
;
7689 /* Firmware blob starts with version numbers, followed by
7690 start address and length. We are setting complete length.
7691 length = end_address_of_bss - start_address_of_text.
7692 Remainder is the blob to be loaded contiguously
7693 from start address. */
7695 info
.fw_base
= be32_to_cpu(fw_data
[1]);
7696 cpu_scratch_size
= tp
->fw_len
;
7697 info
.fw_len
= tp
->fw
->size
- 12;
7698 info
.fw_data
= &fw_data
[3];
7700 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
7701 cpu_base
= RX_CPU_BASE
;
7702 cpu_scratch_base
= NIC_SRAM_MBUF_POOL_BASE5705
;
7704 cpu_base
= TX_CPU_BASE
;
7705 cpu_scratch_base
= TX_CPU_SCRATCH_BASE
;
7706 cpu_scratch_size
= TX_CPU_SCRATCH_SIZE
;
7709 err
= tg3_load_firmware_cpu(tp
, cpu_base
,
7710 cpu_scratch_base
, cpu_scratch_size
,
7715 /* Now startup the cpu. */
7716 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
7717 tw32_f(cpu_base
+ CPU_PC
, info
.fw_base
);
7719 for (i
= 0; i
< 5; i
++) {
7720 if (tr32(cpu_base
+ CPU_PC
) == info
.fw_base
)
7722 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
7723 tw32(cpu_base
+ CPU_MODE
, CPU_MODE_HALT
);
7724 tw32_f(cpu_base
+ CPU_PC
, info
.fw_base
);
7729 "%s fails to set CPU PC, is %08x should be %08x\n",
7730 __func__
, tr32(cpu_base
+ CPU_PC
), info
.fw_base
);
7733 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
7734 tw32_f(cpu_base
+ CPU_MODE
, 0x00000000);
7739 static int tg3_set_mac_addr(struct net_device
*dev
, void *p
)
7741 struct tg3
*tp
= netdev_priv(dev
);
7742 struct sockaddr
*addr
= p
;
7743 int err
= 0, skip_mac_1
= 0;
7745 if (!is_valid_ether_addr(addr
->sa_data
))
7748 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
7750 if (!netif_running(dev
))
7753 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) {
7754 u32 addr0_high
, addr0_low
, addr1_high
, addr1_low
;
7756 addr0_high
= tr32(MAC_ADDR_0_HIGH
);
7757 addr0_low
= tr32(MAC_ADDR_0_LOW
);
7758 addr1_high
= tr32(MAC_ADDR_1_HIGH
);
7759 addr1_low
= tr32(MAC_ADDR_1_LOW
);
7761 /* Skip MAC addr 1 if ASF is using it. */
7762 if ((addr0_high
!= addr1_high
|| addr0_low
!= addr1_low
) &&
7763 !(addr1_high
== 0 && addr1_low
== 0))
7766 spin_lock_bh(&tp
->lock
);
7767 __tg3_set_mac_addr(tp
, skip_mac_1
);
7768 spin_unlock_bh(&tp
->lock
);
7773 /* tp->lock is held. */
7774 static void tg3_set_bdinfo(struct tg3
*tp
, u32 bdinfo_addr
,
7775 dma_addr_t mapping
, u32 maxlen_flags
,
7779 (bdinfo_addr
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_HIGH
),
7780 ((u64
) mapping
>> 32));
7782 (bdinfo_addr
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_LOW
),
7783 ((u64
) mapping
& 0xffffffff));
7785 (bdinfo_addr
+ TG3_BDINFO_MAXLEN_FLAGS
),
7788 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
7790 (bdinfo_addr
+ TG3_BDINFO_NIC_ADDR
),
7794 static void __tg3_set_rx_mode(struct net_device
*);
7795 static void __tg3_set_coalesce(struct tg3
*tp
, struct ethtool_coalesce
*ec
)
7799 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)) {
7800 tw32(HOSTCC_TXCOL_TICKS
, ec
->tx_coalesce_usecs
);
7801 tw32(HOSTCC_TXMAX_FRAMES
, ec
->tx_max_coalesced_frames
);
7802 tw32(HOSTCC_TXCOAL_MAXF_INT
, ec
->tx_max_coalesced_frames_irq
);
7804 tw32(HOSTCC_TXCOL_TICKS
, 0);
7805 tw32(HOSTCC_TXMAX_FRAMES
, 0);
7806 tw32(HOSTCC_TXCOAL_MAXF_INT
, 0);
7809 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_RSS
)) {
7810 tw32(HOSTCC_RXCOL_TICKS
, ec
->rx_coalesce_usecs
);
7811 tw32(HOSTCC_RXMAX_FRAMES
, ec
->rx_max_coalesced_frames
);
7812 tw32(HOSTCC_RXCOAL_MAXF_INT
, ec
->rx_max_coalesced_frames_irq
);
7814 tw32(HOSTCC_RXCOL_TICKS
, 0);
7815 tw32(HOSTCC_RXMAX_FRAMES
, 0);
7816 tw32(HOSTCC_RXCOAL_MAXF_INT
, 0);
7819 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
7820 u32 val
= ec
->stats_block_coalesce_usecs
;
7822 tw32(HOSTCC_RXCOAL_TICK_INT
, ec
->rx_coalesce_usecs_irq
);
7823 tw32(HOSTCC_TXCOAL_TICK_INT
, ec
->tx_coalesce_usecs_irq
);
7825 if (!netif_carrier_ok(tp
->dev
))
7828 tw32(HOSTCC_STAT_COAL_TICKS
, val
);
7831 for (i
= 0; i
< tp
->irq_cnt
- 1; i
++) {
7834 reg
= HOSTCC_RXCOL_TICKS_VEC1
+ i
* 0x18;
7835 tw32(reg
, ec
->rx_coalesce_usecs
);
7836 reg
= HOSTCC_RXMAX_FRAMES_VEC1
+ i
* 0x18;
7837 tw32(reg
, ec
->rx_max_coalesced_frames
);
7838 reg
= HOSTCC_RXCOAL_MAXF_INT_VEC1
+ i
* 0x18;
7839 tw32(reg
, ec
->rx_max_coalesced_frames_irq
);
7841 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
) {
7842 reg
= HOSTCC_TXCOL_TICKS_VEC1
+ i
* 0x18;
7843 tw32(reg
, ec
->tx_coalesce_usecs
);
7844 reg
= HOSTCC_TXMAX_FRAMES_VEC1
+ i
* 0x18;
7845 tw32(reg
, ec
->tx_max_coalesced_frames
);
7846 reg
= HOSTCC_TXCOAL_MAXF_INT_VEC1
+ i
* 0x18;
7847 tw32(reg
, ec
->tx_max_coalesced_frames_irq
);
7851 for (; i
< tp
->irq_max
- 1; i
++) {
7852 tw32(HOSTCC_RXCOL_TICKS_VEC1
+ i
* 0x18, 0);
7853 tw32(HOSTCC_RXMAX_FRAMES_VEC1
+ i
* 0x18, 0);
7854 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1
+ i
* 0x18, 0);
7856 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
) {
7857 tw32(HOSTCC_TXCOL_TICKS_VEC1
+ i
* 0x18, 0);
7858 tw32(HOSTCC_TXMAX_FRAMES_VEC1
+ i
* 0x18, 0);
7859 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1
+ i
* 0x18, 0);
7864 /* tp->lock is held. */
7865 static void tg3_rings_reset(struct tg3
*tp
)
7868 u32 stblk
, txrcb
, rxrcb
, limit
;
7869 struct tg3_napi
*tnapi
= &tp
->napi
[0];
7871 /* Disable all transmit rings but the first. */
7872 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
7873 limit
= NIC_SRAM_SEND_RCB
+ TG3_BDINFO_SIZE
* 16;
7874 else if (tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
)
7875 limit
= NIC_SRAM_SEND_RCB
+ TG3_BDINFO_SIZE
* 4;
7876 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
7877 limit
= NIC_SRAM_SEND_RCB
+ TG3_BDINFO_SIZE
* 2;
7879 limit
= NIC_SRAM_SEND_RCB
+ TG3_BDINFO_SIZE
;
7881 for (txrcb
= NIC_SRAM_SEND_RCB
+ TG3_BDINFO_SIZE
;
7882 txrcb
< limit
; txrcb
+= TG3_BDINFO_SIZE
)
7883 tg3_write_mem(tp
, txrcb
+ TG3_BDINFO_MAXLEN_FLAGS
,
7884 BDINFO_FLAGS_DISABLED
);
7887 /* Disable all receive return rings but the first. */
7888 if (tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
)
7889 limit
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
* 17;
7890 else if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
7891 limit
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
* 16;
7892 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
||
7893 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
7894 limit
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
* 4;
7896 limit
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
;
7898 for (rxrcb
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
;
7899 rxrcb
< limit
; rxrcb
+= TG3_BDINFO_SIZE
)
7900 tg3_write_mem(tp
, rxrcb
+ TG3_BDINFO_MAXLEN_FLAGS
,
7901 BDINFO_FLAGS_DISABLED
);
7903 /* Disable interrupts */
7904 tw32_mailbox_f(tp
->napi
[0].int_mbox
, 1);
7906 /* Zero mailbox registers. */
7907 if (tp
->tg3_flags
& TG3_FLAG_SUPPORT_MSIX
) {
7908 for (i
= 1; i
< tp
->irq_max
; i
++) {
7909 tp
->napi
[i
].tx_prod
= 0;
7910 tp
->napi
[i
].tx_cons
= 0;
7911 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)
7912 tw32_mailbox(tp
->napi
[i
].prodmbox
, 0);
7913 tw32_rx_mbox(tp
->napi
[i
].consmbox
, 0);
7914 tw32_mailbox_f(tp
->napi
[i
].int_mbox
, 1);
7916 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
))
7917 tw32_mailbox(tp
->napi
[0].prodmbox
, 0);
7919 tp
->napi
[0].tx_prod
= 0;
7920 tp
->napi
[0].tx_cons
= 0;
7921 tw32_mailbox(tp
->napi
[0].prodmbox
, 0);
7922 tw32_rx_mbox(tp
->napi
[0].consmbox
, 0);
7925 /* Make sure the NIC-based send BD rings are disabled. */
7926 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
7927 u32 mbox
= MAILBOX_SNDNIC_PROD_IDX_0
+ TG3_64BIT_REG_LOW
;
7928 for (i
= 0; i
< 16; i
++)
7929 tw32_tx_mbox(mbox
+ i
* 8, 0);
7932 txrcb
= NIC_SRAM_SEND_RCB
;
7933 rxrcb
= NIC_SRAM_RCV_RET_RCB
;
7935 /* Clear status block in ram. */
7936 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
7938 /* Set status block DMA address */
7939 tw32(HOSTCC_STATUS_BLK_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
7940 ((u64
) tnapi
->status_mapping
>> 32));
7941 tw32(HOSTCC_STATUS_BLK_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
7942 ((u64
) tnapi
->status_mapping
& 0xffffffff));
7944 if (tnapi
->tx_ring
) {
7945 tg3_set_bdinfo(tp
, txrcb
, tnapi
->tx_desc_mapping
,
7946 (TG3_TX_RING_SIZE
<<
7947 BDINFO_FLAGS_MAXLEN_SHIFT
),
7948 NIC_SRAM_TX_BUFFER_DESC
);
7949 txrcb
+= TG3_BDINFO_SIZE
;
7952 if (tnapi
->rx_rcb
) {
7953 tg3_set_bdinfo(tp
, rxrcb
, tnapi
->rx_rcb_mapping
,
7954 (tp
->rx_ret_ring_mask
+ 1) <<
7955 BDINFO_FLAGS_MAXLEN_SHIFT
, 0);
7956 rxrcb
+= TG3_BDINFO_SIZE
;
7959 stblk
= HOSTCC_STATBLCK_RING1
;
7961 for (i
= 1, tnapi
++; i
< tp
->irq_cnt
; i
++, tnapi
++) {
7962 u64 mapping
= (u64
)tnapi
->status_mapping
;
7963 tw32(stblk
+ TG3_64BIT_REG_HIGH
, mapping
>> 32);
7964 tw32(stblk
+ TG3_64BIT_REG_LOW
, mapping
& 0xffffffff);
7966 /* Clear status block in ram. */
7967 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
7969 if (tnapi
->tx_ring
) {
7970 tg3_set_bdinfo(tp
, txrcb
, tnapi
->tx_desc_mapping
,
7971 (TG3_TX_RING_SIZE
<<
7972 BDINFO_FLAGS_MAXLEN_SHIFT
),
7973 NIC_SRAM_TX_BUFFER_DESC
);
7974 txrcb
+= TG3_BDINFO_SIZE
;
7977 tg3_set_bdinfo(tp
, rxrcb
, tnapi
->rx_rcb_mapping
,
7978 ((tp
->rx_ret_ring_mask
+ 1) <<
7979 BDINFO_FLAGS_MAXLEN_SHIFT
), 0);
7982 rxrcb
+= TG3_BDINFO_SIZE
;
7986 static void tg3_setup_rxbd_thresholds(struct tg3
*tp
)
7988 u32 val
, bdcache_maxcnt
, host_rep_thresh
, nic_rep_thresh
;
7990 if (!(tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) ||
7991 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) ||
7992 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
||
7993 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
)
7994 bdcache_maxcnt
= TG3_SRAM_RX_STD_BDCACHE_SIZE_5700
;
7995 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
||
7996 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5787
)
7997 bdcache_maxcnt
= TG3_SRAM_RX_STD_BDCACHE_SIZE_5755
;
7999 bdcache_maxcnt
= TG3_SRAM_RX_STD_BDCACHE_SIZE_5906
;
8001 nic_rep_thresh
= min(bdcache_maxcnt
/ 2, tp
->rx_std_max_post
);
8002 host_rep_thresh
= max_t(u32
, tp
->rx_pending
/ 8, 1);
8004 val
= min(nic_rep_thresh
, host_rep_thresh
);
8005 tw32(RCVBDI_STD_THRESH
, val
);
8007 if (tp
->tg3_flags3
& TG3_FLG3_57765_PLUS
)
8008 tw32(STD_REPLENISH_LWM
, bdcache_maxcnt
);
8010 if (!(tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) ||
8011 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
8014 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
8015 bdcache_maxcnt
= TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700
;
8017 bdcache_maxcnt
= TG3_SRAM_RX_JMB_BDCACHE_SIZE_5717
;
8019 host_rep_thresh
= max_t(u32
, tp
->rx_jumbo_pending
/ 8, 1);
8021 val
= min(bdcache_maxcnt
/ 2, host_rep_thresh
);
8022 tw32(RCVBDI_JUMBO_THRESH
, val
);
8024 if (tp
->tg3_flags3
& TG3_FLG3_57765_PLUS
)
8025 tw32(JMB_REPLENISH_LWM
, bdcache_maxcnt
);
8028 /* tp->lock is held. */
8029 static int tg3_reset_hw(struct tg3
*tp
, int reset_phy
)
8031 u32 val
, rdmac_mode
;
8033 struct tg3_rx_prodring_set
*tpr
= &tp
->napi
[0].prodring
;
8035 tg3_disable_ints(tp
);
8039 tg3_write_sig_pre_reset(tp
, RESET_KIND_INIT
);
8041 if (tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
)
8042 tg3_abort_hw(tp
, 1);
8044 /* Enable MAC control of LPI */
8045 if (tp
->phy_flags
& TG3_PHYFLG_EEE_CAP
) {
8046 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL
,
8047 TG3_CPMU_EEE_LNKIDL_PCIE_NL0
|
8048 TG3_CPMU_EEE_LNKIDL_UART_IDL
);
8050 tw32_f(TG3_CPMU_EEE_CTRL
,
8051 TG3_CPMU_EEE_CTRL_EXIT_20_1_US
);
8053 val
= TG3_CPMU_EEEMD_ERLY_L1_XIT_DET
|
8054 TG3_CPMU_EEEMD_LPI_IN_TX
|
8055 TG3_CPMU_EEEMD_LPI_IN_RX
|
8056 TG3_CPMU_EEEMD_EEE_ENABLE
;
8058 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5717
)
8059 val
|= TG3_CPMU_EEEMD_SND_IDX_DET_EN
;
8061 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
8062 val
|= TG3_CPMU_EEEMD_APE_TX_DET_EN
;
8064 tw32_f(TG3_CPMU_EEE_MODE
, val
);
8066 tw32_f(TG3_CPMU_EEE_DBTMR1
,
8067 TG3_CPMU_DBTMR1_PCIEXIT_2047US
|
8068 TG3_CPMU_DBTMR1_LNKIDLE_2047US
);
8070 tw32_f(TG3_CPMU_EEE_DBTMR2
,
8071 TG3_CPMU_DBTMR2_APE_TX_2047US
|
8072 TG3_CPMU_DBTMR2_TXIDXEQ_2047US
);
8078 err
= tg3_chip_reset(tp
);
8082 tg3_write_sig_legacy(tp
, RESET_KIND_INIT
);
8084 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
) {
8085 val
= tr32(TG3_CPMU_CTRL
);
8086 val
&= ~(CPMU_CTRL_LINK_AWARE_MODE
| CPMU_CTRL_LINK_IDLE_MODE
);
8087 tw32(TG3_CPMU_CTRL
, val
);
8089 val
= tr32(TG3_CPMU_LSPD_10MB_CLK
);
8090 val
&= ~CPMU_LSPD_10MB_MACCLK_MASK
;
8091 val
|= CPMU_LSPD_10MB_MACCLK_6_25
;
8092 tw32(TG3_CPMU_LSPD_10MB_CLK
, val
);
8094 val
= tr32(TG3_CPMU_LNK_AWARE_PWRMD
);
8095 val
&= ~CPMU_LNK_AWARE_MACCLK_MASK
;
8096 val
|= CPMU_LNK_AWARE_MACCLK_6_25
;
8097 tw32(TG3_CPMU_LNK_AWARE_PWRMD
, val
);
8099 val
= tr32(TG3_CPMU_HST_ACC
);
8100 val
&= ~CPMU_HST_ACC_MACCLK_MASK
;
8101 val
|= CPMU_HST_ACC_MACCLK_6_25
;
8102 tw32(TG3_CPMU_HST_ACC
, val
);
8105 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
) {
8106 val
= tr32(PCIE_PWR_MGMT_THRESH
) & ~PCIE_PWR_MGMT_L1_THRESH_MSK
;
8107 val
|= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN
|
8108 PCIE_PWR_MGMT_L1_THRESH_4MS
;
8109 tw32(PCIE_PWR_MGMT_THRESH
, val
);
8111 val
= tr32(TG3_PCIE_EIDLE_DELAY
) & ~TG3_PCIE_EIDLE_DELAY_MASK
;
8112 tw32(TG3_PCIE_EIDLE_DELAY
, val
| TG3_PCIE_EIDLE_DELAY_13_CLKS
);
8114 tw32(TG3_CORR_ERR_STAT
, TG3_CORR_ERR_STAT_CLEAR
);
8116 val
= tr32(TG3_PCIE_LNKCTL
) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN
;
8117 tw32(TG3_PCIE_LNKCTL
, val
| TG3_PCIE_LNKCTL_L1_PLL_PD_DIS
);
8120 if (tp
->tg3_flags3
& TG3_FLG3_L1PLLPD_EN
) {
8121 u32 grc_mode
= tr32(GRC_MODE
);
8123 /* Access the lower 1K of PL PCIE block registers. */
8124 val
= grc_mode
& ~GRC_MODE_PCIE_PORT_MASK
;
8125 tw32(GRC_MODE
, val
| GRC_MODE_PCIE_PL_SEL
);
8127 val
= tr32(TG3_PCIE_TLDLPL_PORT
+ TG3_PCIE_PL_LO_PHYCTL1
);
8128 tw32(TG3_PCIE_TLDLPL_PORT
+ TG3_PCIE_PL_LO_PHYCTL1
,
8129 val
| TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN
);
8131 tw32(GRC_MODE
, grc_mode
);
8134 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
) {
8135 if (tp
->pci_chip_rev_id
== CHIPREV_ID_57765_A0
) {
8136 u32 grc_mode
= tr32(GRC_MODE
);
8138 /* Access the lower 1K of PL PCIE block registers. */
8139 val
= grc_mode
& ~GRC_MODE_PCIE_PORT_MASK
;
8140 tw32(GRC_MODE
, val
| GRC_MODE_PCIE_PL_SEL
);
8142 val
= tr32(TG3_PCIE_TLDLPL_PORT
+
8143 TG3_PCIE_PL_LO_PHYCTL5
);
8144 tw32(TG3_PCIE_TLDLPL_PORT
+ TG3_PCIE_PL_LO_PHYCTL5
,
8145 val
| TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ
);
8147 tw32(GRC_MODE
, grc_mode
);
8150 val
= tr32(TG3_CPMU_LSPD_10MB_CLK
);
8151 val
&= ~CPMU_LSPD_10MB_MACCLK_MASK
;
8152 val
|= CPMU_LSPD_10MB_MACCLK_6_25
;
8153 tw32(TG3_CPMU_LSPD_10MB_CLK
, val
);
8156 /* This works around an issue with Athlon chipsets on
8157 * B3 tigon3 silicon. This bit has no effect on any
8158 * other revision. But do not set this on PCI Express
8159 * chips and don't even touch the clocks if the CPMU is present.
8161 if (!(tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
)) {
8162 if (!(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
))
8163 tp
->pci_clock_ctrl
|= CLOCK_CTRL_DELAY_PCI_GRANT
;
8164 tw32_f(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
);
8167 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
&&
8168 (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
)) {
8169 val
= tr32(TG3PCI_PCISTATE
);
8170 val
|= PCISTATE_RETRY_SAME_DMA
;
8171 tw32(TG3PCI_PCISTATE
, val
);
8174 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
8175 /* Allow reads and writes to the
8176 * APE register and memory space.
8178 val
= tr32(TG3PCI_PCISTATE
);
8179 val
|= PCISTATE_ALLOW_APE_CTLSPC_WR
|
8180 PCISTATE_ALLOW_APE_SHMEM_WR
|
8181 PCISTATE_ALLOW_APE_PSPACE_WR
;
8182 tw32(TG3PCI_PCISTATE
, val
);
8185 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5704_BX
) {
8186 /* Enable some hw fixes. */
8187 val
= tr32(TG3PCI_MSI_DATA
);
8188 val
|= (1 << 26) | (1 << 28) | (1 << 29);
8189 tw32(TG3PCI_MSI_DATA
, val
);
8192 /* Descriptor ring init may make accesses to the
8193 * NIC SRAM area to setup the TX descriptors, so we
8194 * can only do this after the hardware has been
8195 * successfully reset.
8197 err
= tg3_init_rings(tp
);
8201 if (tp
->tg3_flags3
& TG3_FLG3_57765_PLUS
) {
8202 val
= tr32(TG3PCI_DMA_RW_CTRL
) &
8203 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT
;
8204 if (tp
->pci_chip_rev_id
== CHIPREV_ID_57765_A0
)
8205 val
&= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK
;
8206 tw32(TG3PCI_DMA_RW_CTRL
, val
| tp
->dma_rwctrl
);
8207 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5784
&&
8208 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5761
) {
8209 /* This value is determined during the probe time DMA
8210 * engine test, tg3_test_dma.
8212 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
8215 tp
->grc_mode
&= ~(GRC_MODE_HOST_SENDBDS
|
8216 GRC_MODE_4X_NIC_SEND_RINGS
|
8217 GRC_MODE_NO_TX_PHDR_CSUM
|
8218 GRC_MODE_NO_RX_PHDR_CSUM
);
8219 tp
->grc_mode
|= GRC_MODE_HOST_SENDBDS
;
8221 /* Pseudo-header checksum is done by hardware logic and not
8222 * the offload processers, so make the chip do the pseudo-
8223 * header checksums on receive. For transmit it is more
8224 * convenient to do the pseudo-header checksum in software
8225 * as Linux does that on transmit for us in all cases.
8227 tp
->grc_mode
|= GRC_MODE_NO_TX_PHDR_CSUM
;
8231 (GRC_MODE_IRQ_ON_MAC_ATTN
| GRC_MODE_HOST_STACKUP
));
8233 /* Setup the timer prescalar register. Clock is always 66Mhz. */
8234 val
= tr32(GRC_MISC_CFG
);
8236 val
|= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT
);
8237 tw32(GRC_MISC_CFG
, val
);
8239 /* Initialize MBUF/DESC pool. */
8240 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) {
8242 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5705
) {
8243 tw32(BUFMGR_MB_POOL_ADDR
, NIC_SRAM_MBUF_POOL_BASE
);
8244 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
)
8245 tw32(BUFMGR_MB_POOL_SIZE
, NIC_SRAM_MBUF_POOL_SIZE64
);
8247 tw32(BUFMGR_MB_POOL_SIZE
, NIC_SRAM_MBUF_POOL_SIZE96
);
8248 tw32(BUFMGR_DMA_DESC_POOL_ADDR
, NIC_SRAM_DMA_DESC_POOL_BASE
);
8249 tw32(BUFMGR_DMA_DESC_POOL_SIZE
, NIC_SRAM_DMA_DESC_POOL_SIZE
);
8250 } else if (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) {
8253 fw_len
= tp
->fw_len
;
8254 fw_len
= (fw_len
+ (0x80 - 1)) & ~(0x80 - 1);
8255 tw32(BUFMGR_MB_POOL_ADDR
,
8256 NIC_SRAM_MBUF_POOL_BASE5705
+ fw_len
);
8257 tw32(BUFMGR_MB_POOL_SIZE
,
8258 NIC_SRAM_MBUF_POOL_SIZE5705
- fw_len
- 0xa00);
8261 if (tp
->dev
->mtu
<= ETH_DATA_LEN
) {
8262 tw32(BUFMGR_MB_RDMA_LOW_WATER
,
8263 tp
->bufmgr_config
.mbuf_read_dma_low_water
);
8264 tw32(BUFMGR_MB_MACRX_LOW_WATER
,
8265 tp
->bufmgr_config
.mbuf_mac_rx_low_water
);
8266 tw32(BUFMGR_MB_HIGH_WATER
,
8267 tp
->bufmgr_config
.mbuf_high_water
);
8269 tw32(BUFMGR_MB_RDMA_LOW_WATER
,
8270 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
);
8271 tw32(BUFMGR_MB_MACRX_LOW_WATER
,
8272 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
);
8273 tw32(BUFMGR_MB_HIGH_WATER
,
8274 tp
->bufmgr_config
.mbuf_high_water_jumbo
);
8276 tw32(BUFMGR_DMA_LOW_WATER
,
8277 tp
->bufmgr_config
.dma_low_water
);
8278 tw32(BUFMGR_DMA_HIGH_WATER
,
8279 tp
->bufmgr_config
.dma_high_water
);
8281 val
= BUFMGR_MODE_ENABLE
| BUFMGR_MODE_ATTN_ENABLE
;
8282 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
)
8283 val
|= BUFMGR_MODE_NO_TX_UNDERRUN
;
8284 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
8285 tp
->pci_chip_rev_id
== CHIPREV_ID_5719_A0
||
8286 tp
->pci_chip_rev_id
== CHIPREV_ID_5720_A0
)
8287 val
|= BUFMGR_MODE_MBLOW_ATTN_ENAB
;
8288 tw32(BUFMGR_MODE
, val
);
8289 for (i
= 0; i
< 2000; i
++) {
8290 if (tr32(BUFMGR_MODE
) & BUFMGR_MODE_ENABLE
)
8295 netdev_err(tp
->dev
, "%s cannot enable BUFMGR\n", __func__
);
8299 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5906_A1
)
8300 tw32(ISO_PKT_TX
, (tr32(ISO_PKT_TX
) & ~0x3) | 0x2);
8302 tg3_setup_rxbd_thresholds(tp
);
8304 /* Initialize TG3_BDINFO's at:
8305 * RCVDBDI_STD_BD: standard eth size rx ring
8306 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
8307 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
8310 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
8311 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
8312 * ring attribute flags
8313 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
8315 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
8316 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
8318 * The size of each ring is fixed in the firmware, but the location is
8321 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
8322 ((u64
) tpr
->rx_std_mapping
>> 32));
8323 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
8324 ((u64
) tpr
->rx_std_mapping
& 0xffffffff));
8325 if (!(tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
))
8326 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_NIC_ADDR
,
8327 NIC_SRAM_RX_BUFFER_DESC
);
8329 /* Disable the mini ring */
8330 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
8331 tw32(RCVDBDI_MINI_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
8332 BDINFO_FLAGS_DISABLED
);
8334 /* Program the jumbo buffer descriptor ring control
8335 * blocks on those devices that have them.
8337 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
||
8338 ((tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) &&
8339 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))) {
8341 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
) {
8342 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
8343 ((u64
) tpr
->rx_jmb_mapping
>> 32));
8344 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
8345 ((u64
) tpr
->rx_jmb_mapping
& 0xffffffff));
8346 val
= TG3_RX_JMB_RING_SIZE(tp
) <<
8347 BDINFO_FLAGS_MAXLEN_SHIFT
;
8348 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
8349 val
| BDINFO_FLAGS_USE_EXT_RECV
);
8350 if (!(tp
->tg3_flags3
& TG3_FLG3_USE_JUMBO_BDFLAG
) ||
8351 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
8352 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_NIC_ADDR
,
8353 NIC_SRAM_RX_JUMBO_BUFFER_DESC
);
8355 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
8356 BDINFO_FLAGS_DISABLED
);
8359 if (tp
->tg3_flags3
& TG3_FLG3_57765_PLUS
) {
8360 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
8361 val
= TG3_RX_STD_MAX_SIZE_5700
;
8363 val
= TG3_RX_STD_MAX_SIZE_5717
;
8364 val
<<= BDINFO_FLAGS_MAXLEN_SHIFT
;
8365 val
|= (TG3_RX_STD_DMA_SZ
<< 2);
8367 val
= TG3_RX_STD_DMA_SZ
<< BDINFO_FLAGS_MAXLEN_SHIFT
;
8369 val
= TG3_RX_STD_MAX_SIZE_5700
<< BDINFO_FLAGS_MAXLEN_SHIFT
;
8371 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_MAXLEN_FLAGS
, val
);
8373 tpr
->rx_std_prod_idx
= tp
->rx_pending
;
8374 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG
, tpr
->rx_std_prod_idx
);
8376 tpr
->rx_jmb_prod_idx
= (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
) ?
8377 tp
->rx_jumbo_pending
: 0;
8378 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG
, tpr
->rx_jmb_prod_idx
);
8380 tg3_rings_reset(tp
);
8382 /* Initialize MAC address and backoff seed. */
8383 __tg3_set_mac_addr(tp
, 0);
8385 /* MTU + ethernet header + FCS + optional VLAN tag */
8386 tw32(MAC_RX_MTU_SIZE
,
8387 tp
->dev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
+ VLAN_HLEN
);
8389 /* The slot time is changed by tg3_setup_phy if we
8390 * run at gigabit with half duplex.
8392 val
= (2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
8393 (6 << TX_LENGTHS_IPG_SHIFT
) |
8394 (32 << TX_LENGTHS_SLOT_TIME_SHIFT
);
8396 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5720
)
8397 val
|= tr32(MAC_TX_LENGTHS
) &
8398 (TX_LENGTHS_JMB_FRM_LEN_MSK
|
8399 TX_LENGTHS_CNT_DWN_VAL_MSK
);
8401 tw32(MAC_TX_LENGTHS
, val
);
8403 /* Receive rules. */
8404 tw32(MAC_RCV_RULE_CFG
, RCV_RULE_CFG_DEFAULT_CLASS
);
8405 tw32(RCVLPC_CONFIG
, 0x0181);
8407 /* Calculate RDMAC_MODE setting early, we need it to determine
8408 * the RCVLPC_STATE_ENABLE mask.
8410 rdmac_mode
= (RDMAC_MODE_ENABLE
| RDMAC_MODE_TGTABORT_ENAB
|
8411 RDMAC_MODE_MSTABORT_ENAB
| RDMAC_MODE_PARITYERR_ENAB
|
8412 RDMAC_MODE_ADDROFLOW_ENAB
| RDMAC_MODE_FIFOOFLOW_ENAB
|
8413 RDMAC_MODE_FIFOURUN_ENAB
| RDMAC_MODE_FIFOOREAD_ENAB
|
8414 RDMAC_MODE_LNGREAD_ENAB
);
8416 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
)
8417 rdmac_mode
|= RDMAC_MODE_MULT_DMA_RD_DIS
;
8419 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
8420 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
8421 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
8422 rdmac_mode
|= RDMAC_MODE_BD_SBD_CRPT_ENAB
|
8423 RDMAC_MODE_MBUF_RBD_CRPT_ENAB
|
8424 RDMAC_MODE_MBUF_SBD_CRPT_ENAB
;
8426 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
8427 tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A0
) {
8428 if (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
&&
8429 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
8430 rdmac_mode
|= RDMAC_MODE_FIFO_SIZE_128
;
8431 } else if (!(tr32(TG3PCI_PCISTATE
) & PCISTATE_BUS_SPEED_HIGH
) &&
8432 !(tp
->tg3_flags2
& TG3_FLG2_IS_5788
)) {
8433 rdmac_mode
|= RDMAC_MODE_FIFO_LONG_BURST
;
8437 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)
8438 rdmac_mode
|= RDMAC_MODE_FIFO_LONG_BURST
;
8440 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
8441 rdmac_mode
|= RDMAC_MODE_IPV4_LSO_EN
;
8443 if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO_3
) ||
8444 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
8445 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
8446 rdmac_mode
|= RDMAC_MODE_IPV6_LSO_EN
;
8448 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5720
)
8449 rdmac_mode
|= tr32(RDMAC_MODE
) & RDMAC_MODE_H2BNC_VLAN_DET
;
8451 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
8452 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
8453 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
8454 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
||
8455 (tp
->tg3_flags3
& TG3_FLG3_57765_PLUS
)) {
8456 val
= tr32(TG3_RDMA_RSRVCTRL_REG
);
8457 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
||
8458 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5720
) {
8459 val
&= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK
|
8460 TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK
|
8461 TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK
);
8462 val
|= TG3_RDMA_RSRVCTRL_TXMRGN_320B
|
8463 TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K
|
8464 TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K
;
8466 tw32(TG3_RDMA_RSRVCTRL_REG
,
8467 val
| TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX
);
8470 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
||
8471 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5720
) {
8472 val
= tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL
);
8473 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL
, val
|
8474 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K
|
8475 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K
);
8478 /* Receive/send statistics. */
8479 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) {
8480 val
= tr32(RCVLPC_STATS_ENABLE
);
8481 val
&= ~RCVLPC_STATSENAB_DACK_FIX
;
8482 tw32(RCVLPC_STATS_ENABLE
, val
);
8483 } else if ((rdmac_mode
& RDMAC_MODE_FIFO_SIZE_128
) &&
8484 (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
)) {
8485 val
= tr32(RCVLPC_STATS_ENABLE
);
8486 val
&= ~RCVLPC_STATSENAB_LNGBRST_RFIX
;
8487 tw32(RCVLPC_STATS_ENABLE
, val
);
8489 tw32(RCVLPC_STATS_ENABLE
, 0xffffff);
8491 tw32(RCVLPC_STATSCTRL
, RCVLPC_STATSCTRL_ENABLE
);
8492 tw32(SNDDATAI_STATSENAB
, 0xffffff);
8493 tw32(SNDDATAI_STATSCTRL
,
8494 (SNDDATAI_SCTRL_ENABLE
|
8495 SNDDATAI_SCTRL_FASTUPD
));
8497 /* Setup host coalescing engine. */
8498 tw32(HOSTCC_MODE
, 0);
8499 for (i
= 0; i
< 2000; i
++) {
8500 if (!(tr32(HOSTCC_MODE
) & HOSTCC_MODE_ENABLE
))
8505 __tg3_set_coalesce(tp
, &tp
->coal
);
8507 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
8508 /* Status/statistics block address. See tg3_timer,
8509 * the tg3_periodic_fetch_stats call there, and
8510 * tg3_get_stats to see how this works for 5705/5750 chips.
8512 tw32(HOSTCC_STATS_BLK_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
8513 ((u64
) tp
->stats_mapping
>> 32));
8514 tw32(HOSTCC_STATS_BLK_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
8515 ((u64
) tp
->stats_mapping
& 0xffffffff));
8516 tw32(HOSTCC_STATS_BLK_NIC_ADDR
, NIC_SRAM_STATS_BLK
);
8518 tw32(HOSTCC_STATUS_BLK_NIC_ADDR
, NIC_SRAM_STATUS_BLK
);
8520 /* Clear statistics and status block memory areas */
8521 for (i
= NIC_SRAM_STATS_BLK
;
8522 i
< NIC_SRAM_STATUS_BLK
+ TG3_HW_STATUS_SIZE
;
8524 tg3_write_mem(tp
, i
, 0);
8529 tw32(HOSTCC_MODE
, HOSTCC_MODE_ENABLE
| tp
->coalesce_mode
);
8531 tw32(RCVCC_MODE
, RCVCC_MODE_ENABLE
| RCVCC_MODE_ATTN_ENABLE
);
8532 tw32(RCVLPC_MODE
, RCVLPC_MODE_ENABLE
);
8533 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
8534 tw32(RCVLSC_MODE
, RCVLSC_MODE_ENABLE
| RCVLSC_MODE_ATTN_ENABLE
);
8536 if (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
) {
8537 tp
->phy_flags
&= ~TG3_PHYFLG_PARALLEL_DETECT
;
8538 /* reset to prevent losing 1st rx packet intermittently */
8539 tw32_f(MAC_RX_MODE
, RX_MODE_RESET
);
8543 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
8544 tp
->mac_mode
= MAC_MODE_APE_TX_EN
| MAC_MODE_APE_RX_EN
;
8547 tp
->mac_mode
|= MAC_MODE_TXSTAT_ENABLE
| MAC_MODE_RXSTAT_ENABLE
|
8548 MAC_MODE_TDE_ENABLE
| MAC_MODE_RDE_ENABLE
| MAC_MODE_FHDE_ENABLE
;
8549 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
8550 !(tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) &&
8551 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
)
8552 tp
->mac_mode
|= MAC_MODE_LINK_POLARITY
;
8553 tw32_f(MAC_MODE
, tp
->mac_mode
| MAC_MODE_RXSTAT_CLEAR
| MAC_MODE_TXSTAT_CLEAR
);
8556 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8557 * If TG3_FLG2_IS_NIC is zero, we should read the
8558 * register to preserve the GPIO settings for LOMs. The GPIOs,
8559 * whether used as inputs or outputs, are set by boot code after
8562 if (!(tp
->tg3_flags2
& TG3_FLG2_IS_NIC
)) {
8565 gpio_mask
= GRC_LCLCTRL_GPIO_OE0
| GRC_LCLCTRL_GPIO_OE1
|
8566 GRC_LCLCTRL_GPIO_OE2
| GRC_LCLCTRL_GPIO_OUTPUT0
|
8567 GRC_LCLCTRL_GPIO_OUTPUT1
| GRC_LCLCTRL_GPIO_OUTPUT2
;
8569 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
)
8570 gpio_mask
|= GRC_LCLCTRL_GPIO_OE3
|
8571 GRC_LCLCTRL_GPIO_OUTPUT3
;
8573 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
)
8574 gpio_mask
|= GRC_LCLCTRL_GPIO_UART_SEL
;
8576 tp
->grc_local_ctrl
&= ~gpio_mask
;
8577 tp
->grc_local_ctrl
|= tr32(GRC_LOCAL_CTRL
) & gpio_mask
;
8579 /* GPIO1 must be driven high for eeprom write protect */
8580 if (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
)
8581 tp
->grc_local_ctrl
|= (GRC_LCLCTRL_GPIO_OE1
|
8582 GRC_LCLCTRL_GPIO_OUTPUT1
);
8584 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
);
8587 if ((tp
->tg3_flags2
& TG3_FLG2_USING_MSIX
) &&
8589 val
= tr32(MSGINT_MODE
);
8590 val
|= MSGINT_MODE_MULTIVEC_EN
| MSGINT_MODE_ENABLE
;
8591 tw32(MSGINT_MODE
, val
);
8594 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
8595 tw32_f(DMAC_MODE
, DMAC_MODE_ENABLE
);
8599 val
= (WDMAC_MODE_ENABLE
| WDMAC_MODE_TGTABORT_ENAB
|
8600 WDMAC_MODE_MSTABORT_ENAB
| WDMAC_MODE_PARITYERR_ENAB
|
8601 WDMAC_MODE_ADDROFLOW_ENAB
| WDMAC_MODE_FIFOOFLOW_ENAB
|
8602 WDMAC_MODE_FIFOURUN_ENAB
| WDMAC_MODE_FIFOOREAD_ENAB
|
8603 WDMAC_MODE_LNGREAD_ENAB
);
8605 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
8606 tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A0
) {
8607 if ((tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) &&
8608 (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A1
||
8609 tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A2
)) {
8611 } else if (!(tr32(TG3PCI_PCISTATE
) & PCISTATE_BUS_SPEED_HIGH
) &&
8612 !(tp
->tg3_flags2
& TG3_FLG2_IS_5788
)) {
8613 val
|= WDMAC_MODE_RX_ACCEL
;
8617 /* Enable host coalescing bug fix */
8618 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
8619 val
|= WDMAC_MODE_STATUS_TAG_FIX
;
8621 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
8622 val
|= WDMAC_MODE_BURST_ALL_DATA
;
8624 tw32_f(WDMAC_MODE
, val
);
8627 if (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) {
8630 pci_read_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
8632 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
) {
8633 pcix_cmd
&= ~PCI_X_CMD_MAX_READ
;
8634 pcix_cmd
|= PCI_X_CMD_READ_2K
;
8635 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
8636 pcix_cmd
&= ~(PCI_X_CMD_MAX_SPLIT
| PCI_X_CMD_MAX_READ
);
8637 pcix_cmd
|= PCI_X_CMD_READ_2K
;
8639 pci_write_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
8643 tw32_f(RDMAC_MODE
, rdmac_mode
);
8646 tw32(RCVDCC_MODE
, RCVDCC_MODE_ENABLE
| RCVDCC_MODE_ATTN_ENABLE
);
8647 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
8648 tw32(MBFREE_MODE
, MBFREE_MODE_ENABLE
);
8650 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
)
8652 SNDDATAC_MODE_ENABLE
| SNDDATAC_MODE_CDELAY
);
8654 tw32(SNDDATAC_MODE
, SNDDATAC_MODE_ENABLE
);
8656 tw32(SNDBDC_MODE
, SNDBDC_MODE_ENABLE
| SNDBDC_MODE_ATTN_ENABLE
);
8657 tw32(RCVBDI_MODE
, RCVBDI_MODE_ENABLE
| RCVBDI_MODE_RCB_ATTN_ENAB
);
8658 val
= RCVDBDI_MODE_ENABLE
| RCVDBDI_MODE_INV_RING_SZ
;
8659 if (tp
->tg3_flags3
& TG3_FLG3_LRG_PROD_RING_CAP
)
8660 val
|= RCVDBDI_MODE_LRG_RING_SZ
;
8661 tw32(RCVDBDI_MODE
, val
);
8662 tw32(SNDDATAI_MODE
, SNDDATAI_MODE_ENABLE
);
8663 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
8664 tw32(SNDDATAI_MODE
, SNDDATAI_MODE_ENABLE
| 0x8);
8665 val
= SNDBDI_MODE_ENABLE
| SNDBDI_MODE_ATTN_ENABLE
;
8666 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)
8667 val
|= SNDBDI_MODE_MULTI_TXQ_EN
;
8668 tw32(SNDBDI_MODE
, val
);
8669 tw32(SNDBDS_MODE
, SNDBDS_MODE_ENABLE
| SNDBDS_MODE_ATTN_ENABLE
);
8671 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
) {
8672 err
= tg3_load_5701_a0_firmware_fix(tp
);
8677 if (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) {
8678 err
= tg3_load_tso_firmware(tp
);
8683 tp
->tx_mode
= TX_MODE_ENABLE
;
8685 if ((tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) ||
8686 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
8687 tp
->tx_mode
|= TX_MODE_MBUF_LOCKUP_FIX
;
8689 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5720
) {
8690 val
= TX_MODE_JMB_FRM_LEN
| TX_MODE_CNT_DN_MODE
;
8691 tp
->tx_mode
&= ~val
;
8692 tp
->tx_mode
|= tr32(MAC_TX_MODE
) & val
;
8695 tw32_f(MAC_TX_MODE
, tp
->tx_mode
);
8698 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_RSS
) {
8699 u32 reg
= MAC_RSS_INDIR_TBL_0
;
8700 u8
*ent
= (u8
*)&val
;
8702 /* Setup the indirection table */
8703 for (i
= 0; i
< TG3_RSS_INDIR_TBL_SIZE
; i
++) {
8704 int idx
= i
% sizeof(val
);
8706 ent
[idx
] = i
% (tp
->irq_cnt
- 1);
8707 if (idx
== sizeof(val
) - 1) {
8713 /* Setup the "secret" hash key. */
8714 tw32(MAC_RSS_HASH_KEY_0
, 0x5f865437);
8715 tw32(MAC_RSS_HASH_KEY_1
, 0xe4ac62cc);
8716 tw32(MAC_RSS_HASH_KEY_2
, 0x50103a45);
8717 tw32(MAC_RSS_HASH_KEY_3
, 0x36621985);
8718 tw32(MAC_RSS_HASH_KEY_4
, 0xbf14c0e8);
8719 tw32(MAC_RSS_HASH_KEY_5
, 0x1bc27a1e);
8720 tw32(MAC_RSS_HASH_KEY_6
, 0x84f4b556);
8721 tw32(MAC_RSS_HASH_KEY_7
, 0x094ea6fe);
8722 tw32(MAC_RSS_HASH_KEY_8
, 0x7dda01e7);
8723 tw32(MAC_RSS_HASH_KEY_9
, 0xc04d7481);
8726 tp
->rx_mode
= RX_MODE_ENABLE
;
8727 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
8728 tp
->rx_mode
|= RX_MODE_IPV6_CSUM_ENABLE
;
8730 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_RSS
)
8731 tp
->rx_mode
|= RX_MODE_RSS_ENABLE
|
8732 RX_MODE_RSS_ITBL_HASH_BITS_7
|
8733 RX_MODE_RSS_IPV6_HASH_EN
|
8734 RX_MODE_RSS_TCP_IPV6_HASH_EN
|
8735 RX_MODE_RSS_IPV4_HASH_EN
|
8736 RX_MODE_RSS_TCP_IPV4_HASH_EN
;
8738 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
8741 tw32(MAC_LED_CTRL
, tp
->led_ctrl
);
8743 tw32(MAC_MI_STAT
, MAC_MI_STAT_LNKSTAT_ATTN_ENAB
);
8744 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) {
8745 tw32_f(MAC_RX_MODE
, RX_MODE_RESET
);
8748 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
8751 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) {
8752 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) &&
8753 !(tp
->phy_flags
& TG3_PHYFLG_SERDES_PREEMPHASIS
)) {
8754 /* Set drive transmission level to 1.2V */
8755 /* only if the signal pre-emphasis bit is not set */
8756 val
= tr32(MAC_SERDES_CFG
);
8759 tw32(MAC_SERDES_CFG
, val
);
8761 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5703_A1
)
8762 tw32(MAC_SERDES_CFG
, 0x616000);
8765 /* Prevent chip from dropping frames when flow control
8768 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
8772 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME
, val
);
8774 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
&&
8775 (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
)) {
8776 /* Use hardware link auto-negotiation */
8777 tp
->tg3_flags2
|= TG3_FLG2_HW_AUTONEG
;
8780 if ((tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
) &&
8781 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
)) {
8784 tmp
= tr32(SERDES_RX_CTRL
);
8785 tw32(SERDES_RX_CTRL
, tmp
| SERDES_RX_SIG_DETECT
);
8786 tp
->grc_local_ctrl
&= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT
;
8787 tp
->grc_local_ctrl
|= GRC_LCLCTRL_USE_SIG_DETECT
;
8788 tw32(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
);
8791 if (!(tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
)) {
8792 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
) {
8793 tp
->phy_flags
&= ~TG3_PHYFLG_IS_LOW_POWER
;
8794 tp
->link_config
.speed
= tp
->link_config
.orig_speed
;
8795 tp
->link_config
.duplex
= tp
->link_config
.orig_duplex
;
8796 tp
->link_config
.autoneg
= tp
->link_config
.orig_autoneg
;
8799 err
= tg3_setup_phy(tp
, 0);
8803 if (!(tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) &&
8804 !(tp
->phy_flags
& TG3_PHYFLG_IS_FET
)) {
8807 /* Clear CRC stats. */
8808 if (!tg3_readphy(tp
, MII_TG3_TEST1
, &tmp
)) {
8809 tg3_writephy(tp
, MII_TG3_TEST1
,
8810 tmp
| MII_TG3_TEST1_CRC_EN
);
8811 tg3_readphy(tp
, MII_TG3_RXR_COUNTERS
, &tmp
);
8816 __tg3_set_rx_mode(tp
->dev
);
8818 /* Initialize receive rules. */
8819 tw32(MAC_RCV_RULE_0
, 0xc2000000 & RCV_RULE_DISABLE_MASK
);
8820 tw32(MAC_RCV_VALUE_0
, 0xffffffff & RCV_RULE_DISABLE_MASK
);
8821 tw32(MAC_RCV_RULE_1
, 0x86000004 & RCV_RULE_DISABLE_MASK
);
8822 tw32(MAC_RCV_VALUE_1
, 0xffffffff & RCV_RULE_DISABLE_MASK
);
8824 if ((tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
8825 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
8829 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)
8833 tw32(MAC_RCV_RULE_15
, 0); tw32(MAC_RCV_VALUE_15
, 0);
8835 tw32(MAC_RCV_RULE_14
, 0); tw32(MAC_RCV_VALUE_14
, 0);
8837 tw32(MAC_RCV_RULE_13
, 0); tw32(MAC_RCV_VALUE_13
, 0);
8839 tw32(MAC_RCV_RULE_12
, 0); tw32(MAC_RCV_VALUE_12
, 0);
8841 tw32(MAC_RCV_RULE_11
, 0); tw32(MAC_RCV_VALUE_11
, 0);
8843 tw32(MAC_RCV_RULE_10
, 0); tw32(MAC_RCV_VALUE_10
, 0);
8845 tw32(MAC_RCV_RULE_9
, 0); tw32(MAC_RCV_VALUE_9
, 0);
8847 tw32(MAC_RCV_RULE_8
, 0); tw32(MAC_RCV_VALUE_8
, 0);
8849 tw32(MAC_RCV_RULE_7
, 0); tw32(MAC_RCV_VALUE_7
, 0);
8851 tw32(MAC_RCV_RULE_6
, 0); tw32(MAC_RCV_VALUE_6
, 0);
8853 tw32(MAC_RCV_RULE_5
, 0); tw32(MAC_RCV_VALUE_5
, 0);
8855 tw32(MAC_RCV_RULE_4
, 0); tw32(MAC_RCV_VALUE_4
, 0);
8857 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
8859 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
8867 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
8868 /* Write our heartbeat update interval to APE. */
8869 tg3_ape_write32(tp
, TG3_APE_HOST_HEARTBEAT_INT_MS
,
8870 APE_HOST_HEARTBEAT_INT_DISABLE
);
8872 tg3_write_sig_post_reset(tp
, RESET_KIND_INIT
);
8877 /* Called at device open time to get the chip ready for
8878 * packet processing. Invoked with tp->lock held.
8880 static int tg3_init_hw(struct tg3
*tp
, int reset_phy
)
8882 tg3_switch_clocks(tp
);
8884 tw32(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
8886 return tg3_reset_hw(tp
, reset_phy
);
8889 #define TG3_STAT_ADD32(PSTAT, REG) \
8890 do { u32 __val = tr32(REG); \
8891 (PSTAT)->low += __val; \
8892 if ((PSTAT)->low < __val) \
8893 (PSTAT)->high += 1; \
8896 static void tg3_periodic_fetch_stats(struct tg3
*tp
)
8898 struct tg3_hw_stats
*sp
= tp
->hw_stats
;
8900 if (!netif_carrier_ok(tp
->dev
))
8903 TG3_STAT_ADD32(&sp
->tx_octets
, MAC_TX_STATS_OCTETS
);
8904 TG3_STAT_ADD32(&sp
->tx_collisions
, MAC_TX_STATS_COLLISIONS
);
8905 TG3_STAT_ADD32(&sp
->tx_xon_sent
, MAC_TX_STATS_XON_SENT
);
8906 TG3_STAT_ADD32(&sp
->tx_xoff_sent
, MAC_TX_STATS_XOFF_SENT
);
8907 TG3_STAT_ADD32(&sp
->tx_mac_errors
, MAC_TX_STATS_MAC_ERRORS
);
8908 TG3_STAT_ADD32(&sp
->tx_single_collisions
, MAC_TX_STATS_SINGLE_COLLISIONS
);
8909 TG3_STAT_ADD32(&sp
->tx_mult_collisions
, MAC_TX_STATS_MULT_COLLISIONS
);
8910 TG3_STAT_ADD32(&sp
->tx_deferred
, MAC_TX_STATS_DEFERRED
);
8911 TG3_STAT_ADD32(&sp
->tx_excessive_collisions
, MAC_TX_STATS_EXCESSIVE_COL
);
8912 TG3_STAT_ADD32(&sp
->tx_late_collisions
, MAC_TX_STATS_LATE_COL
);
8913 TG3_STAT_ADD32(&sp
->tx_ucast_packets
, MAC_TX_STATS_UCAST
);
8914 TG3_STAT_ADD32(&sp
->tx_mcast_packets
, MAC_TX_STATS_MCAST
);
8915 TG3_STAT_ADD32(&sp
->tx_bcast_packets
, MAC_TX_STATS_BCAST
);
8917 TG3_STAT_ADD32(&sp
->rx_octets
, MAC_RX_STATS_OCTETS
);
8918 TG3_STAT_ADD32(&sp
->rx_fragments
, MAC_RX_STATS_FRAGMENTS
);
8919 TG3_STAT_ADD32(&sp
->rx_ucast_packets
, MAC_RX_STATS_UCAST
);
8920 TG3_STAT_ADD32(&sp
->rx_mcast_packets
, MAC_RX_STATS_MCAST
);
8921 TG3_STAT_ADD32(&sp
->rx_bcast_packets
, MAC_RX_STATS_BCAST
);
8922 TG3_STAT_ADD32(&sp
->rx_fcs_errors
, MAC_RX_STATS_FCS_ERRORS
);
8923 TG3_STAT_ADD32(&sp
->rx_align_errors
, MAC_RX_STATS_ALIGN_ERRORS
);
8924 TG3_STAT_ADD32(&sp
->rx_xon_pause_rcvd
, MAC_RX_STATS_XON_PAUSE_RECVD
);
8925 TG3_STAT_ADD32(&sp
->rx_xoff_pause_rcvd
, MAC_RX_STATS_XOFF_PAUSE_RECVD
);
8926 TG3_STAT_ADD32(&sp
->rx_mac_ctrl_rcvd
, MAC_RX_STATS_MAC_CTRL_RECVD
);
8927 TG3_STAT_ADD32(&sp
->rx_xoff_entered
, MAC_RX_STATS_XOFF_ENTERED
);
8928 TG3_STAT_ADD32(&sp
->rx_frame_too_long_errors
, MAC_RX_STATS_FRAME_TOO_LONG
);
8929 TG3_STAT_ADD32(&sp
->rx_jabbers
, MAC_RX_STATS_JABBERS
);
8930 TG3_STAT_ADD32(&sp
->rx_undersize_packets
, MAC_RX_STATS_UNDERSIZE
);
8932 TG3_STAT_ADD32(&sp
->rxbds_empty
, RCVLPC_NO_RCV_BD_CNT
);
8933 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5717
) {
8934 TG3_STAT_ADD32(&sp
->rx_discards
, RCVLPC_IN_DISCARDS_CNT
);
8936 u32 val
= tr32(HOSTCC_FLOW_ATTN
);
8937 val
= (val
& HOSTCC_FLOW_ATTN_MBUF_LWM
) ? 1 : 0;
8939 tw32(HOSTCC_FLOW_ATTN
, HOSTCC_FLOW_ATTN_MBUF_LWM
);
8940 sp
->rx_discards
.low
+= val
;
8941 if (sp
->rx_discards
.low
< val
)
8942 sp
->rx_discards
.high
+= 1;
8944 sp
->mbuf_lwm_thresh_hit
= sp
->rx_discards
;
8946 TG3_STAT_ADD32(&sp
->rx_errors
, RCVLPC_IN_ERRORS_CNT
);
8949 static void tg3_timer(unsigned long __opaque
)
8951 struct tg3
*tp
= (struct tg3
*) __opaque
;
8956 spin_lock(&tp
->lock
);
8958 if (!(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)) {
8959 /* All of this garbage is because when using non-tagged
8960 * IRQ status the mailbox/status_block protocol the chip
8961 * uses with the cpu is race prone.
8963 if (tp
->napi
[0].hw_status
->status
& SD_STATUS_UPDATED
) {
8964 tw32(GRC_LOCAL_CTRL
,
8965 tp
->grc_local_ctrl
| GRC_LCLCTRL_SETINT
);
8967 tw32(HOSTCC_MODE
, tp
->coalesce_mode
|
8968 HOSTCC_MODE_ENABLE
| HOSTCC_MODE_NOW
);
8971 if (!(tr32(WDMAC_MODE
) & WDMAC_MODE_ENABLE
)) {
8972 tp
->tg3_flags2
|= TG3_FLG2_RESTART_TIMER
;
8973 spin_unlock(&tp
->lock
);
8974 schedule_work(&tp
->reset_task
);
8979 /* This part only runs once per second. */
8980 if (!--tp
->timer_counter
) {
8981 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
8982 tg3_periodic_fetch_stats(tp
);
8984 if (tp
->setlpicnt
&& !--tp
->setlpicnt
) {
8985 u32 val
= tr32(TG3_CPMU_EEE_MODE
);
8986 tw32(TG3_CPMU_EEE_MODE
,
8987 val
| TG3_CPMU_EEEMD_LPI_ENABLE
);
8990 if (tp
->tg3_flags
& TG3_FLAG_USE_LINKCHG_REG
) {
8994 mac_stat
= tr32(MAC_STATUS
);
8997 if (tp
->phy_flags
& TG3_PHYFLG_USE_MI_INTERRUPT
) {
8998 if (mac_stat
& MAC_STATUS_MI_INTERRUPT
)
9000 } else if (mac_stat
& MAC_STATUS_LNKSTATE_CHANGED
)
9004 tg3_setup_phy(tp
, 0);
9005 } else if (tp
->tg3_flags
& TG3_FLAG_POLL_SERDES
) {
9006 u32 mac_stat
= tr32(MAC_STATUS
);
9009 if (netif_carrier_ok(tp
->dev
) &&
9010 (mac_stat
& MAC_STATUS_LNKSTATE_CHANGED
)) {
9013 if (!netif_carrier_ok(tp
->dev
) &&
9014 (mac_stat
& (MAC_STATUS_PCS_SYNCED
|
9015 MAC_STATUS_SIGNAL_DET
))) {
9019 if (!tp
->serdes_counter
) {
9022 ~MAC_MODE_PORT_MODE_MASK
));
9024 tw32_f(MAC_MODE
, tp
->mac_mode
);
9027 tg3_setup_phy(tp
, 0);
9029 } else if ((tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
) &&
9030 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
9031 tg3_serdes_parallel_detect(tp
);
9034 tp
->timer_counter
= tp
->timer_multiplier
;
9037 /* Heartbeat is only sent once every 2 seconds.
9039 * The heartbeat is to tell the ASF firmware that the host
9040 * driver is still alive. In the event that the OS crashes,
9041 * ASF needs to reset the hardware to free up the FIFO space
9042 * that may be filled with rx packets destined for the host.
9043 * If the FIFO is full, ASF will no longer function properly.
9045 * Unintended resets have been reported on real time kernels
9046 * where the timer doesn't run on time. Netpoll will also have
9049 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
9050 * to check the ring condition when the heartbeat is expiring
9051 * before doing the reset. This will prevent most unintended
9054 if (!--tp
->asf_counter
) {
9055 if ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) &&
9056 !(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)) {
9057 tg3_wait_for_event_ack(tp
);
9059 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_MBOX
,
9060 FWCMD_NICDRV_ALIVE3
);
9061 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_LEN_MBOX
, 4);
9062 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
,
9063 TG3_FW_UPDATE_TIMEOUT_SEC
);
9065 tg3_generate_fw_event(tp
);
9067 tp
->asf_counter
= tp
->asf_multiplier
;
9070 spin_unlock(&tp
->lock
);
9073 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
9074 add_timer(&tp
->timer
);
9077 static int tg3_request_irq(struct tg3
*tp
, int irq_num
)
9080 unsigned long flags
;
9082 struct tg3_napi
*tnapi
= &tp
->napi
[irq_num
];
9084 if (tp
->irq_cnt
== 1)
9085 name
= tp
->dev
->name
;
9087 name
= &tnapi
->irq_lbl
[0];
9088 snprintf(name
, IFNAMSIZ
, "%s-%d", tp
->dev
->name
, irq_num
);
9089 name
[IFNAMSIZ
-1] = 0;
9092 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI_OR_MSIX
) {
9094 if (tp
->tg3_flags2
& TG3_FLG2_1SHOT_MSI
)
9099 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)
9100 fn
= tg3_interrupt_tagged
;
9101 flags
= IRQF_SHARED
;
9104 return request_irq(tnapi
->irq_vec
, fn
, flags
, name
, tnapi
);
9107 static int tg3_test_interrupt(struct tg3
*tp
)
9109 struct tg3_napi
*tnapi
= &tp
->napi
[0];
9110 struct net_device
*dev
= tp
->dev
;
9111 int err
, i
, intr_ok
= 0;
9114 if (!netif_running(dev
))
9117 tg3_disable_ints(tp
);
9119 free_irq(tnapi
->irq_vec
, tnapi
);
9122 * Turn off MSI one shot mode. Otherwise this test has no
9123 * observable way to know whether the interrupt was delivered.
9125 if ((tp
->tg3_flags3
& TG3_FLG3_57765_PLUS
) &&
9126 (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
)) {
9127 val
= tr32(MSGINT_MODE
) | MSGINT_MODE_ONE_SHOT_DISABLE
;
9128 tw32(MSGINT_MODE
, val
);
9131 err
= request_irq(tnapi
->irq_vec
, tg3_test_isr
,
9132 IRQF_SHARED
| IRQF_SAMPLE_RANDOM
, dev
->name
, tnapi
);
9136 tnapi
->hw_status
->status
&= ~SD_STATUS_UPDATED
;
9137 tg3_enable_ints(tp
);
9139 tw32_f(HOSTCC_MODE
, tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
|
9142 for (i
= 0; i
< 5; i
++) {
9143 u32 int_mbox
, misc_host_ctrl
;
9145 int_mbox
= tr32_mailbox(tnapi
->int_mbox
);
9146 misc_host_ctrl
= tr32(TG3PCI_MISC_HOST_CTRL
);
9148 if ((int_mbox
!= 0) ||
9149 (misc_host_ctrl
& MISC_HOST_CTRL_MASK_PCI_INT
)) {
9157 tg3_disable_ints(tp
);
9159 free_irq(tnapi
->irq_vec
, tnapi
);
9161 err
= tg3_request_irq(tp
, 0);
9167 /* Reenable MSI one shot mode. */
9168 if ((tp
->tg3_flags3
& TG3_FLG3_57765_PLUS
) &&
9169 (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
)) {
9170 val
= tr32(MSGINT_MODE
) & ~MSGINT_MODE_ONE_SHOT_DISABLE
;
9171 tw32(MSGINT_MODE
, val
);
9179 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
9180 * successfully restored
9182 static int tg3_test_msi(struct tg3
*tp
)
9187 if (!(tp
->tg3_flags2
& TG3_FLG2_USING_MSI
))
9190 /* Turn off SERR reporting in case MSI terminates with Master
9193 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
9194 pci_write_config_word(tp
->pdev
, PCI_COMMAND
,
9195 pci_cmd
& ~PCI_COMMAND_SERR
);
9197 err
= tg3_test_interrupt(tp
);
9199 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
9204 /* other failures */
9208 /* MSI test failed, go back to INTx mode */
9209 netdev_warn(tp
->dev
, "No interrupt was generated using MSI. Switching "
9210 "to INTx mode. Please report this failure to the PCI "
9211 "maintainer and include system chipset information\n");
9213 free_irq(tp
->napi
[0].irq_vec
, &tp
->napi
[0]);
9215 pci_disable_msi(tp
->pdev
);
9217 tp
->tg3_flags2
&= ~TG3_FLG2_USING_MSI
;
9218 tp
->napi
[0].irq_vec
= tp
->pdev
->irq
;
9220 err
= tg3_request_irq(tp
, 0);
9224 /* Need to reset the chip because the MSI cycle may have terminated
9225 * with Master Abort.
9227 tg3_full_lock(tp
, 1);
9229 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
9230 err
= tg3_init_hw(tp
, 1);
9232 tg3_full_unlock(tp
);
9235 free_irq(tp
->napi
[0].irq_vec
, &tp
->napi
[0]);
9240 static int tg3_request_firmware(struct tg3
*tp
)
9242 const __be32
*fw_data
;
9244 if (request_firmware(&tp
->fw
, tp
->fw_needed
, &tp
->pdev
->dev
)) {
9245 netdev_err(tp
->dev
, "Failed to load firmware \"%s\"\n",
9250 fw_data
= (void *)tp
->fw
->data
;
9252 /* Firmware blob starts with version numbers, followed by
9253 * start address and _full_ length including BSS sections
9254 * (which must be longer than the actual data, of course
9257 tp
->fw_len
= be32_to_cpu(fw_data
[2]); /* includes bss */
9258 if (tp
->fw_len
< (tp
->fw
->size
- 12)) {
9259 netdev_err(tp
->dev
, "bogus length %d in \"%s\"\n",
9260 tp
->fw_len
, tp
->fw_needed
);
9261 release_firmware(tp
->fw
);
9266 /* We no longer need firmware; we have it. */
9267 tp
->fw_needed
= NULL
;
9271 static bool tg3_enable_msix(struct tg3
*tp
)
9273 int i
, rc
, cpus
= num_online_cpus();
9274 struct msix_entry msix_ent
[tp
->irq_max
];
9277 /* Just fallback to the simpler MSI mode. */
9281 * We want as many rx rings enabled as there are cpus.
9282 * The first MSIX vector only deals with link interrupts, etc,
9283 * so we add one to the number of vectors we are requesting.
9285 tp
->irq_cnt
= min_t(unsigned, cpus
+ 1, tp
->irq_max
);
9287 for (i
= 0; i
< tp
->irq_max
; i
++) {
9288 msix_ent
[i
].entry
= i
;
9289 msix_ent
[i
].vector
= 0;
9292 rc
= pci_enable_msix(tp
->pdev
, msix_ent
, tp
->irq_cnt
);
9295 } else if (rc
!= 0) {
9296 if (pci_enable_msix(tp
->pdev
, msix_ent
, rc
))
9298 netdev_notice(tp
->dev
, "Requested %d MSI-X vectors, received %d\n",
9303 for (i
= 0; i
< tp
->irq_max
; i
++)
9304 tp
->napi
[i
].irq_vec
= msix_ent
[i
].vector
;
9306 netif_set_real_num_tx_queues(tp
->dev
, 1);
9307 rc
= tp
->irq_cnt
> 1 ? tp
->irq_cnt
- 1 : 1;
9308 if (netif_set_real_num_rx_queues(tp
->dev
, rc
)) {
9309 pci_disable_msix(tp
->pdev
);
9313 if (tp
->irq_cnt
> 1) {
9314 tp
->tg3_flags3
|= TG3_FLG3_ENABLE_RSS
;
9316 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
||
9317 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5720
) {
9318 tp
->tg3_flags3
|= TG3_FLG3_ENABLE_TSS
;
9319 netif_set_real_num_tx_queues(tp
->dev
, tp
->irq_cnt
- 1);
9326 static void tg3_ints_init(struct tg3
*tp
)
9328 if ((tp
->tg3_flags
& TG3_FLAG_SUPPORT_MSI_OR_MSIX
) &&
9329 !(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)) {
9330 /* All MSI supporting chips should support tagged
9331 * status. Assert that this is the case.
9333 netdev_warn(tp
->dev
,
9334 "MSI without TAGGED_STATUS? Not using MSI\n");
9338 if ((tp
->tg3_flags
& TG3_FLAG_SUPPORT_MSIX
) && tg3_enable_msix(tp
))
9339 tp
->tg3_flags2
|= TG3_FLG2_USING_MSIX
;
9340 else if ((tp
->tg3_flags
& TG3_FLAG_SUPPORT_MSI
) &&
9341 pci_enable_msi(tp
->pdev
) == 0)
9342 tp
->tg3_flags2
|= TG3_FLG2_USING_MSI
;
9344 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI_OR_MSIX
) {
9345 u32 msi_mode
= tr32(MSGINT_MODE
);
9346 if ((tp
->tg3_flags2
& TG3_FLG2_USING_MSIX
) &&
9348 msi_mode
|= MSGINT_MODE_MULTIVEC_EN
;
9349 tw32(MSGINT_MODE
, msi_mode
| MSGINT_MODE_ENABLE
);
9352 if (!(tp
->tg3_flags2
& TG3_FLG2_USING_MSIX
)) {
9354 tp
->napi
[0].irq_vec
= tp
->pdev
->irq
;
9355 netif_set_real_num_tx_queues(tp
->dev
, 1);
9356 netif_set_real_num_rx_queues(tp
->dev
, 1);
9360 static void tg3_ints_fini(struct tg3
*tp
)
9362 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSIX
)
9363 pci_disable_msix(tp
->pdev
);
9364 else if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
)
9365 pci_disable_msi(tp
->pdev
);
9366 tp
->tg3_flags2
&= ~TG3_FLG2_USING_MSI_OR_MSIX
;
9367 tp
->tg3_flags3
&= ~(TG3_FLG3_ENABLE_RSS
| TG3_FLG3_ENABLE_TSS
);
9370 static int tg3_open(struct net_device
*dev
)
9372 struct tg3
*tp
= netdev_priv(dev
);
9375 if (tp
->fw_needed
) {
9376 err
= tg3_request_firmware(tp
);
9377 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
) {
9381 netdev_warn(tp
->dev
, "TSO capability disabled\n");
9382 tp
->tg3_flags2
&= ~TG3_FLG2_TSO_CAPABLE
;
9383 } else if (!(tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
)) {
9384 netdev_notice(tp
->dev
, "TSO capability restored\n");
9385 tp
->tg3_flags2
|= TG3_FLG2_TSO_CAPABLE
;
9389 netif_carrier_off(tp
->dev
);
9391 err
= tg3_power_up(tp
);
9395 tg3_full_lock(tp
, 0);
9397 tg3_disable_ints(tp
);
9398 tp
->tg3_flags
&= ~TG3_FLAG_INIT_COMPLETE
;
9400 tg3_full_unlock(tp
);
9403 * Setup interrupts first so we know how
9404 * many NAPI resources to allocate
9408 /* The placement of this call is tied
9409 * to the setup and use of Host TX descriptors.
9411 err
= tg3_alloc_consistent(tp
);
9417 tg3_napi_enable(tp
);
9419 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
9420 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
9421 err
= tg3_request_irq(tp
, i
);
9423 for (i
--; i
>= 0; i
--)
9424 free_irq(tnapi
->irq_vec
, tnapi
);
9432 tg3_full_lock(tp
, 0);
9434 err
= tg3_init_hw(tp
, 1);
9436 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
9439 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)
9440 tp
->timer_offset
= HZ
;
9442 tp
->timer_offset
= HZ
/ 10;
9444 BUG_ON(tp
->timer_offset
> HZ
);
9445 tp
->timer_counter
= tp
->timer_multiplier
=
9446 (HZ
/ tp
->timer_offset
);
9447 tp
->asf_counter
= tp
->asf_multiplier
=
9448 ((HZ
/ tp
->timer_offset
) * 2);
9450 init_timer(&tp
->timer
);
9451 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
9452 tp
->timer
.data
= (unsigned long) tp
;
9453 tp
->timer
.function
= tg3_timer
;
9456 tg3_full_unlock(tp
);
9461 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
9462 err
= tg3_test_msi(tp
);
9465 tg3_full_lock(tp
, 0);
9466 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
9468 tg3_full_unlock(tp
);
9473 if (!(tp
->tg3_flags3
& TG3_FLG3_57765_PLUS
) &&
9474 (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
)) {
9475 u32 val
= tr32(PCIE_TRANSACTION_CFG
);
9477 tw32(PCIE_TRANSACTION_CFG
,
9478 val
| PCIE_TRANS_CFG_1SHOT_MSI
);
9484 tg3_full_lock(tp
, 0);
9486 add_timer(&tp
->timer
);
9487 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
9488 tg3_enable_ints(tp
);
9490 tg3_full_unlock(tp
);
9492 netif_tx_start_all_queues(dev
);
9497 for (i
= tp
->irq_cnt
- 1; i
>= 0; i
--) {
9498 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
9499 free_irq(tnapi
->irq_vec
, tnapi
);
9503 tg3_napi_disable(tp
);
9505 tg3_free_consistent(tp
);
9512 static struct rtnl_link_stats64
*tg3_get_stats64(struct net_device
*,
9513 struct rtnl_link_stats64
*);
9514 static struct tg3_ethtool_stats
*tg3_get_estats(struct tg3
*);
9516 static int tg3_close(struct net_device
*dev
)
9519 struct tg3
*tp
= netdev_priv(dev
);
9521 tg3_napi_disable(tp
);
9522 cancel_work_sync(&tp
->reset_task
);
9524 netif_tx_stop_all_queues(dev
);
9526 del_timer_sync(&tp
->timer
);
9530 tg3_full_lock(tp
, 1);
9532 tg3_disable_ints(tp
);
9534 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
9536 tp
->tg3_flags
&= ~TG3_FLAG_INIT_COMPLETE
;
9538 tg3_full_unlock(tp
);
9540 for (i
= tp
->irq_cnt
- 1; i
>= 0; i
--) {
9541 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
9542 free_irq(tnapi
->irq_vec
, tnapi
);
9547 tg3_get_stats64(tp
->dev
, &tp
->net_stats_prev
);
9549 memcpy(&tp
->estats_prev
, tg3_get_estats(tp
),
9550 sizeof(tp
->estats_prev
));
9554 tg3_free_consistent(tp
);
9558 netif_carrier_off(tp
->dev
);
9563 static inline u64
get_stat64(tg3_stat64_t
*val
)
9565 return ((u64
)val
->high
<< 32) | ((u64
)val
->low
);
9568 static u64
calc_crc_errors(struct tg3
*tp
)
9570 struct tg3_hw_stats
*hw_stats
= tp
->hw_stats
;
9572 if (!(tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) &&
9573 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
9574 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)) {
9577 spin_lock_bh(&tp
->lock
);
9578 if (!tg3_readphy(tp
, MII_TG3_TEST1
, &val
)) {
9579 tg3_writephy(tp
, MII_TG3_TEST1
,
9580 val
| MII_TG3_TEST1_CRC_EN
);
9581 tg3_readphy(tp
, MII_TG3_RXR_COUNTERS
, &val
);
9584 spin_unlock_bh(&tp
->lock
);
9586 tp
->phy_crc_errors
+= val
;
9588 return tp
->phy_crc_errors
;
9591 return get_stat64(&hw_stats
->rx_fcs_errors
);
9594 #define ESTAT_ADD(member) \
9595 estats->member = old_estats->member + \
9596 get_stat64(&hw_stats->member)
9598 static struct tg3_ethtool_stats
*tg3_get_estats(struct tg3
*tp
)
9600 struct tg3_ethtool_stats
*estats
= &tp
->estats
;
9601 struct tg3_ethtool_stats
*old_estats
= &tp
->estats_prev
;
9602 struct tg3_hw_stats
*hw_stats
= tp
->hw_stats
;
9607 ESTAT_ADD(rx_octets
);
9608 ESTAT_ADD(rx_fragments
);
9609 ESTAT_ADD(rx_ucast_packets
);
9610 ESTAT_ADD(rx_mcast_packets
);
9611 ESTAT_ADD(rx_bcast_packets
);
9612 ESTAT_ADD(rx_fcs_errors
);
9613 ESTAT_ADD(rx_align_errors
);
9614 ESTAT_ADD(rx_xon_pause_rcvd
);
9615 ESTAT_ADD(rx_xoff_pause_rcvd
);
9616 ESTAT_ADD(rx_mac_ctrl_rcvd
);
9617 ESTAT_ADD(rx_xoff_entered
);
9618 ESTAT_ADD(rx_frame_too_long_errors
);
9619 ESTAT_ADD(rx_jabbers
);
9620 ESTAT_ADD(rx_undersize_packets
);
9621 ESTAT_ADD(rx_in_length_errors
);
9622 ESTAT_ADD(rx_out_length_errors
);
9623 ESTAT_ADD(rx_64_or_less_octet_packets
);
9624 ESTAT_ADD(rx_65_to_127_octet_packets
);
9625 ESTAT_ADD(rx_128_to_255_octet_packets
);
9626 ESTAT_ADD(rx_256_to_511_octet_packets
);
9627 ESTAT_ADD(rx_512_to_1023_octet_packets
);
9628 ESTAT_ADD(rx_1024_to_1522_octet_packets
);
9629 ESTAT_ADD(rx_1523_to_2047_octet_packets
);
9630 ESTAT_ADD(rx_2048_to_4095_octet_packets
);
9631 ESTAT_ADD(rx_4096_to_8191_octet_packets
);
9632 ESTAT_ADD(rx_8192_to_9022_octet_packets
);
9634 ESTAT_ADD(tx_octets
);
9635 ESTAT_ADD(tx_collisions
);
9636 ESTAT_ADD(tx_xon_sent
);
9637 ESTAT_ADD(tx_xoff_sent
);
9638 ESTAT_ADD(tx_flow_control
);
9639 ESTAT_ADD(tx_mac_errors
);
9640 ESTAT_ADD(tx_single_collisions
);
9641 ESTAT_ADD(tx_mult_collisions
);
9642 ESTAT_ADD(tx_deferred
);
9643 ESTAT_ADD(tx_excessive_collisions
);
9644 ESTAT_ADD(tx_late_collisions
);
9645 ESTAT_ADD(tx_collide_2times
);
9646 ESTAT_ADD(tx_collide_3times
);
9647 ESTAT_ADD(tx_collide_4times
);
9648 ESTAT_ADD(tx_collide_5times
);
9649 ESTAT_ADD(tx_collide_6times
);
9650 ESTAT_ADD(tx_collide_7times
);
9651 ESTAT_ADD(tx_collide_8times
);
9652 ESTAT_ADD(tx_collide_9times
);
9653 ESTAT_ADD(tx_collide_10times
);
9654 ESTAT_ADD(tx_collide_11times
);
9655 ESTAT_ADD(tx_collide_12times
);
9656 ESTAT_ADD(tx_collide_13times
);
9657 ESTAT_ADD(tx_collide_14times
);
9658 ESTAT_ADD(tx_collide_15times
);
9659 ESTAT_ADD(tx_ucast_packets
);
9660 ESTAT_ADD(tx_mcast_packets
);
9661 ESTAT_ADD(tx_bcast_packets
);
9662 ESTAT_ADD(tx_carrier_sense_errors
);
9663 ESTAT_ADD(tx_discards
);
9664 ESTAT_ADD(tx_errors
);
9666 ESTAT_ADD(dma_writeq_full
);
9667 ESTAT_ADD(dma_write_prioq_full
);
9668 ESTAT_ADD(rxbds_empty
);
9669 ESTAT_ADD(rx_discards
);
9670 ESTAT_ADD(rx_errors
);
9671 ESTAT_ADD(rx_threshold_hit
);
9673 ESTAT_ADD(dma_readq_full
);
9674 ESTAT_ADD(dma_read_prioq_full
);
9675 ESTAT_ADD(tx_comp_queue_full
);
9677 ESTAT_ADD(ring_set_send_prod_index
);
9678 ESTAT_ADD(ring_status_update
);
9679 ESTAT_ADD(nic_irqs
);
9680 ESTAT_ADD(nic_avoided_irqs
);
9681 ESTAT_ADD(nic_tx_threshold_hit
);
9686 static struct rtnl_link_stats64
*tg3_get_stats64(struct net_device
*dev
,
9687 struct rtnl_link_stats64
*stats
)
9689 struct tg3
*tp
= netdev_priv(dev
);
9690 struct rtnl_link_stats64
*old_stats
= &tp
->net_stats_prev
;
9691 struct tg3_hw_stats
*hw_stats
= tp
->hw_stats
;
9696 stats
->rx_packets
= old_stats
->rx_packets
+
9697 get_stat64(&hw_stats
->rx_ucast_packets
) +
9698 get_stat64(&hw_stats
->rx_mcast_packets
) +
9699 get_stat64(&hw_stats
->rx_bcast_packets
);
9701 stats
->tx_packets
= old_stats
->tx_packets
+
9702 get_stat64(&hw_stats
->tx_ucast_packets
) +
9703 get_stat64(&hw_stats
->tx_mcast_packets
) +
9704 get_stat64(&hw_stats
->tx_bcast_packets
);
9706 stats
->rx_bytes
= old_stats
->rx_bytes
+
9707 get_stat64(&hw_stats
->rx_octets
);
9708 stats
->tx_bytes
= old_stats
->tx_bytes
+
9709 get_stat64(&hw_stats
->tx_octets
);
9711 stats
->rx_errors
= old_stats
->rx_errors
+
9712 get_stat64(&hw_stats
->rx_errors
);
9713 stats
->tx_errors
= old_stats
->tx_errors
+
9714 get_stat64(&hw_stats
->tx_errors
) +
9715 get_stat64(&hw_stats
->tx_mac_errors
) +
9716 get_stat64(&hw_stats
->tx_carrier_sense_errors
) +
9717 get_stat64(&hw_stats
->tx_discards
);
9719 stats
->multicast
= old_stats
->multicast
+
9720 get_stat64(&hw_stats
->rx_mcast_packets
);
9721 stats
->collisions
= old_stats
->collisions
+
9722 get_stat64(&hw_stats
->tx_collisions
);
9724 stats
->rx_length_errors
= old_stats
->rx_length_errors
+
9725 get_stat64(&hw_stats
->rx_frame_too_long_errors
) +
9726 get_stat64(&hw_stats
->rx_undersize_packets
);
9728 stats
->rx_over_errors
= old_stats
->rx_over_errors
+
9729 get_stat64(&hw_stats
->rxbds_empty
);
9730 stats
->rx_frame_errors
= old_stats
->rx_frame_errors
+
9731 get_stat64(&hw_stats
->rx_align_errors
);
9732 stats
->tx_aborted_errors
= old_stats
->tx_aborted_errors
+
9733 get_stat64(&hw_stats
->tx_discards
);
9734 stats
->tx_carrier_errors
= old_stats
->tx_carrier_errors
+
9735 get_stat64(&hw_stats
->tx_carrier_sense_errors
);
9737 stats
->rx_crc_errors
= old_stats
->rx_crc_errors
+
9738 calc_crc_errors(tp
);
9740 stats
->rx_missed_errors
= old_stats
->rx_missed_errors
+
9741 get_stat64(&hw_stats
->rx_discards
);
9743 stats
->rx_dropped
= tp
->rx_dropped
;
9748 static inline u32
calc_crc(unsigned char *buf
, int len
)
9756 for (j
= 0; j
< len
; j
++) {
9759 for (k
= 0; k
< 8; k
++) {
9772 static void tg3_set_multi(struct tg3
*tp
, unsigned int accept_all
)
9774 /* accept or reject all multicast frames */
9775 tw32(MAC_HASH_REG_0
, accept_all
? 0xffffffff : 0);
9776 tw32(MAC_HASH_REG_1
, accept_all
? 0xffffffff : 0);
9777 tw32(MAC_HASH_REG_2
, accept_all
? 0xffffffff : 0);
9778 tw32(MAC_HASH_REG_3
, accept_all
? 0xffffffff : 0);
9781 static void __tg3_set_rx_mode(struct net_device
*dev
)
9783 struct tg3
*tp
= netdev_priv(dev
);
9786 rx_mode
= tp
->rx_mode
& ~(RX_MODE_PROMISC
|
9787 RX_MODE_KEEP_VLAN_TAG
);
9789 #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
9790 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9793 if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
9794 rx_mode
|= RX_MODE_KEEP_VLAN_TAG
;
9797 if (dev
->flags
& IFF_PROMISC
) {
9798 /* Promiscuous mode. */
9799 rx_mode
|= RX_MODE_PROMISC
;
9800 } else if (dev
->flags
& IFF_ALLMULTI
) {
9801 /* Accept all multicast. */
9802 tg3_set_multi(tp
, 1);
9803 } else if (netdev_mc_empty(dev
)) {
9804 /* Reject all multicast. */
9805 tg3_set_multi(tp
, 0);
9807 /* Accept one or more multicast(s). */
9808 struct netdev_hw_addr
*ha
;
9809 u32 mc_filter
[4] = { 0, };
9814 netdev_for_each_mc_addr(ha
, dev
) {
9815 crc
= calc_crc(ha
->addr
, ETH_ALEN
);
9817 regidx
= (bit
& 0x60) >> 5;
9819 mc_filter
[regidx
] |= (1 << bit
);
9822 tw32(MAC_HASH_REG_0
, mc_filter
[0]);
9823 tw32(MAC_HASH_REG_1
, mc_filter
[1]);
9824 tw32(MAC_HASH_REG_2
, mc_filter
[2]);
9825 tw32(MAC_HASH_REG_3
, mc_filter
[3]);
9828 if (rx_mode
!= tp
->rx_mode
) {
9829 tp
->rx_mode
= rx_mode
;
9830 tw32_f(MAC_RX_MODE
, rx_mode
);
9835 static void tg3_set_rx_mode(struct net_device
*dev
)
9837 struct tg3
*tp
= netdev_priv(dev
);
9839 if (!netif_running(dev
))
9842 tg3_full_lock(tp
, 0);
9843 __tg3_set_rx_mode(dev
);
9844 tg3_full_unlock(tp
);
9847 static int tg3_get_regs_len(struct net_device
*dev
)
9849 return TG3_REG_BLK_SIZE
;
9852 static void tg3_get_regs(struct net_device
*dev
,
9853 struct ethtool_regs
*regs
, void *_p
)
9855 struct tg3
*tp
= netdev_priv(dev
);
9859 memset(_p
, 0, TG3_REG_BLK_SIZE
);
9861 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)
9864 tg3_full_lock(tp
, 0);
9866 tg3_dump_legacy_regs(tp
, (u32
*)_p
);
9868 tg3_full_unlock(tp
);
9871 static int tg3_get_eeprom_len(struct net_device
*dev
)
9873 struct tg3
*tp
= netdev_priv(dev
);
9875 return tp
->nvram_size
;
9878 static int tg3_get_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
, u8
*data
)
9880 struct tg3
*tp
= netdev_priv(dev
);
9883 u32 i
, offset
, len
, b_offset
, b_count
;
9886 if (tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
)
9889 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)
9892 offset
= eeprom
->offset
;
9896 eeprom
->magic
= TG3_EEPROM_MAGIC
;
9899 /* adjustments to start on required 4 byte boundary */
9900 b_offset
= offset
& 3;
9901 b_count
= 4 - b_offset
;
9902 if (b_count
> len
) {
9903 /* i.e. offset=1 len=2 */
9906 ret
= tg3_nvram_read_be32(tp
, offset
-b_offset
, &val
);
9909 memcpy(data
, ((char *)&val
) + b_offset
, b_count
);
9912 eeprom
->len
+= b_count
;
9915 /* read bytes up to the last 4 byte boundary */
9916 pd
= &data
[eeprom
->len
];
9917 for (i
= 0; i
< (len
- (len
& 3)); i
+= 4) {
9918 ret
= tg3_nvram_read_be32(tp
, offset
+ i
, &val
);
9923 memcpy(pd
+ i
, &val
, 4);
9928 /* read last bytes not ending on 4 byte boundary */
9929 pd
= &data
[eeprom
->len
];
9931 b_offset
= offset
+ len
- b_count
;
9932 ret
= tg3_nvram_read_be32(tp
, b_offset
, &val
);
9935 memcpy(pd
, &val
, b_count
);
9936 eeprom
->len
+= b_count
;
9941 static int tg3_nvram_write_block(struct tg3
*tp
, u32 offset
, u32 len
, u8
*buf
);
9943 static int tg3_set_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
, u8
*data
)
9945 struct tg3
*tp
= netdev_priv(dev
);
9947 u32 offset
, len
, b_offset
, odd_len
;
9951 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)
9954 if ((tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) ||
9955 eeprom
->magic
!= TG3_EEPROM_MAGIC
)
9958 offset
= eeprom
->offset
;
9961 if ((b_offset
= (offset
& 3))) {
9962 /* adjustments to start on required 4 byte boundary */
9963 ret
= tg3_nvram_read_be32(tp
, offset
-b_offset
, &start
);
9974 /* adjustments to end on required 4 byte boundary */
9976 len
= (len
+ 3) & ~3;
9977 ret
= tg3_nvram_read_be32(tp
, offset
+len
-4, &end
);
9983 if (b_offset
|| odd_len
) {
9984 buf
= kmalloc(len
, GFP_KERNEL
);
9988 memcpy(buf
, &start
, 4);
9990 memcpy(buf
+len
-4, &end
, 4);
9991 memcpy(buf
+ b_offset
, data
, eeprom
->len
);
9994 ret
= tg3_nvram_write_block(tp
, offset
, len
, buf
);
10002 static int tg3_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
10004 struct tg3
*tp
= netdev_priv(dev
);
10006 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
10007 struct phy_device
*phydev
;
10008 if (!(tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
))
10010 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
10011 return phy_ethtool_gset(phydev
, cmd
);
10014 cmd
->supported
= (SUPPORTED_Autoneg
);
10016 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
))
10017 cmd
->supported
|= (SUPPORTED_1000baseT_Half
|
10018 SUPPORTED_1000baseT_Full
);
10020 if (!(tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
)) {
10021 cmd
->supported
|= (SUPPORTED_100baseT_Half
|
10022 SUPPORTED_100baseT_Full
|
10023 SUPPORTED_10baseT_Half
|
10024 SUPPORTED_10baseT_Full
|
10026 cmd
->port
= PORT_TP
;
10028 cmd
->supported
|= SUPPORTED_FIBRE
;
10029 cmd
->port
= PORT_FIBRE
;
10032 cmd
->advertising
= tp
->link_config
.advertising
;
10033 if (netif_running(dev
)) {
10034 cmd
->speed
= tp
->link_config
.active_speed
;
10035 cmd
->duplex
= tp
->link_config
.active_duplex
;
10037 cmd
->speed
= SPEED_INVALID
;
10038 cmd
->duplex
= DUPLEX_INVALID
;
10040 cmd
->phy_address
= tp
->phy_addr
;
10041 cmd
->transceiver
= XCVR_INTERNAL
;
10042 cmd
->autoneg
= tp
->link_config
.autoneg
;
10048 static int tg3_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
10050 struct tg3
*tp
= netdev_priv(dev
);
10052 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
10053 struct phy_device
*phydev
;
10054 if (!(tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
))
10056 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
10057 return phy_ethtool_sset(phydev
, cmd
);
10060 if (cmd
->autoneg
!= AUTONEG_ENABLE
&&
10061 cmd
->autoneg
!= AUTONEG_DISABLE
)
10064 if (cmd
->autoneg
== AUTONEG_DISABLE
&&
10065 cmd
->duplex
!= DUPLEX_FULL
&&
10066 cmd
->duplex
!= DUPLEX_HALF
)
10069 if (cmd
->autoneg
== AUTONEG_ENABLE
) {
10070 u32 mask
= ADVERTISED_Autoneg
|
10072 ADVERTISED_Asym_Pause
;
10074 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
))
10075 mask
|= ADVERTISED_1000baseT_Half
|
10076 ADVERTISED_1000baseT_Full
;
10078 if (!(tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
))
10079 mask
|= ADVERTISED_100baseT_Half
|
10080 ADVERTISED_100baseT_Full
|
10081 ADVERTISED_10baseT_Half
|
10082 ADVERTISED_10baseT_Full
|
10085 mask
|= ADVERTISED_FIBRE
;
10087 if (cmd
->advertising
& ~mask
)
10090 mask
&= (ADVERTISED_1000baseT_Half
|
10091 ADVERTISED_1000baseT_Full
|
10092 ADVERTISED_100baseT_Half
|
10093 ADVERTISED_100baseT_Full
|
10094 ADVERTISED_10baseT_Half
|
10095 ADVERTISED_10baseT_Full
);
10097 cmd
->advertising
&= mask
;
10099 if (tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
) {
10100 if (cmd
->speed
!= SPEED_1000
)
10103 if (cmd
->duplex
!= DUPLEX_FULL
)
10106 if (cmd
->speed
!= SPEED_100
&&
10107 cmd
->speed
!= SPEED_10
)
10112 tg3_full_lock(tp
, 0);
10114 tp
->link_config
.autoneg
= cmd
->autoneg
;
10115 if (cmd
->autoneg
== AUTONEG_ENABLE
) {
10116 tp
->link_config
.advertising
= (cmd
->advertising
|
10117 ADVERTISED_Autoneg
);
10118 tp
->link_config
.speed
= SPEED_INVALID
;
10119 tp
->link_config
.duplex
= DUPLEX_INVALID
;
10121 tp
->link_config
.advertising
= 0;
10122 tp
->link_config
.speed
= cmd
->speed
;
10123 tp
->link_config
.duplex
= cmd
->duplex
;
10126 tp
->link_config
.orig_speed
= tp
->link_config
.speed
;
10127 tp
->link_config
.orig_duplex
= tp
->link_config
.duplex
;
10128 tp
->link_config
.orig_autoneg
= tp
->link_config
.autoneg
;
10130 if (netif_running(dev
))
10131 tg3_setup_phy(tp
, 1);
10133 tg3_full_unlock(tp
);
10138 static void tg3_get_drvinfo(struct net_device
*dev
, struct ethtool_drvinfo
*info
)
10140 struct tg3
*tp
= netdev_priv(dev
);
10142 strcpy(info
->driver
, DRV_MODULE_NAME
);
10143 strcpy(info
->version
, DRV_MODULE_VERSION
);
10144 strcpy(info
->fw_version
, tp
->fw_ver
);
10145 strcpy(info
->bus_info
, pci_name(tp
->pdev
));
10148 static void tg3_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
10150 struct tg3
*tp
= netdev_priv(dev
);
10152 if ((tp
->tg3_flags
& TG3_FLAG_WOL_CAP
) &&
10153 device_can_wakeup(&tp
->pdev
->dev
))
10154 wol
->supported
= WAKE_MAGIC
;
10156 wol
->supported
= 0;
10158 if ((tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
) &&
10159 device_can_wakeup(&tp
->pdev
->dev
))
10160 wol
->wolopts
= WAKE_MAGIC
;
10161 memset(&wol
->sopass
, 0, sizeof(wol
->sopass
));
10164 static int tg3_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
10166 struct tg3
*tp
= netdev_priv(dev
);
10167 struct device
*dp
= &tp
->pdev
->dev
;
10169 if (wol
->wolopts
& ~WAKE_MAGIC
)
10171 if ((wol
->wolopts
& WAKE_MAGIC
) &&
10172 !((tp
->tg3_flags
& TG3_FLAG_WOL_CAP
) && device_can_wakeup(dp
)))
10175 device_set_wakeup_enable(dp
, wol
->wolopts
& WAKE_MAGIC
);
10177 spin_lock_bh(&tp
->lock
);
10178 if (device_may_wakeup(dp
))
10179 tp
->tg3_flags
|= TG3_FLAG_WOL_ENABLE
;
10181 tp
->tg3_flags
&= ~TG3_FLAG_WOL_ENABLE
;
10182 spin_unlock_bh(&tp
->lock
);
10188 static u32
tg3_get_msglevel(struct net_device
*dev
)
10190 struct tg3
*tp
= netdev_priv(dev
);
10191 return tp
->msg_enable
;
10194 static void tg3_set_msglevel(struct net_device
*dev
, u32 value
)
10196 struct tg3
*tp
= netdev_priv(dev
);
10197 tp
->msg_enable
= value
;
10200 static int tg3_nway_reset(struct net_device
*dev
)
10202 struct tg3
*tp
= netdev_priv(dev
);
10205 if (!netif_running(dev
))
10208 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
)
10211 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
10212 if (!(tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
))
10214 r
= phy_start_aneg(tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
]);
10218 spin_lock_bh(&tp
->lock
);
10220 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
10221 if (!tg3_readphy(tp
, MII_BMCR
, &bmcr
) &&
10222 ((bmcr
& BMCR_ANENABLE
) ||
10223 (tp
->phy_flags
& TG3_PHYFLG_PARALLEL_DETECT
))) {
10224 tg3_writephy(tp
, MII_BMCR
, bmcr
| BMCR_ANRESTART
|
10228 spin_unlock_bh(&tp
->lock
);
10234 static void tg3_get_ringparam(struct net_device
*dev
, struct ethtool_ringparam
*ering
)
10236 struct tg3
*tp
= netdev_priv(dev
);
10238 ering
->rx_max_pending
= tp
->rx_std_ring_mask
;
10239 ering
->rx_mini_max_pending
= 0;
10240 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
)
10241 ering
->rx_jumbo_max_pending
= tp
->rx_jmb_ring_mask
;
10243 ering
->rx_jumbo_max_pending
= 0;
10245 ering
->tx_max_pending
= TG3_TX_RING_SIZE
- 1;
10247 ering
->rx_pending
= tp
->rx_pending
;
10248 ering
->rx_mini_pending
= 0;
10249 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
)
10250 ering
->rx_jumbo_pending
= tp
->rx_jumbo_pending
;
10252 ering
->rx_jumbo_pending
= 0;
10254 ering
->tx_pending
= tp
->napi
[0].tx_pending
;
10257 static int tg3_set_ringparam(struct net_device
*dev
, struct ethtool_ringparam
*ering
)
10259 struct tg3
*tp
= netdev_priv(dev
);
10260 int i
, irq_sync
= 0, err
= 0;
10262 if ((ering
->rx_pending
> tp
->rx_std_ring_mask
) ||
10263 (ering
->rx_jumbo_pending
> tp
->rx_jmb_ring_mask
) ||
10264 (ering
->tx_pending
> TG3_TX_RING_SIZE
- 1) ||
10265 (ering
->tx_pending
<= MAX_SKB_FRAGS
) ||
10266 ((tp
->tg3_flags2
& TG3_FLG2_TSO_BUG
) &&
10267 (ering
->tx_pending
<= (MAX_SKB_FRAGS
* 3))))
10270 if (netif_running(dev
)) {
10272 tg3_netif_stop(tp
);
10276 tg3_full_lock(tp
, irq_sync
);
10278 tp
->rx_pending
= ering
->rx_pending
;
10280 if ((tp
->tg3_flags2
& TG3_FLG2_MAX_RXPEND_64
) &&
10281 tp
->rx_pending
> 63)
10282 tp
->rx_pending
= 63;
10283 tp
->rx_jumbo_pending
= ering
->rx_jumbo_pending
;
10285 for (i
= 0; i
< tp
->irq_max
; i
++)
10286 tp
->napi
[i
].tx_pending
= ering
->tx_pending
;
10288 if (netif_running(dev
)) {
10289 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
10290 err
= tg3_restart_hw(tp
, 1);
10292 tg3_netif_start(tp
);
10295 tg3_full_unlock(tp
);
10297 if (irq_sync
&& !err
)
10303 static void tg3_get_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
*epause
)
10305 struct tg3
*tp
= netdev_priv(dev
);
10307 epause
->autoneg
= (tp
->tg3_flags
& TG3_FLAG_PAUSE_AUTONEG
) != 0;
10309 if (tp
->link_config
.active_flowctrl
& FLOW_CTRL_RX
)
10310 epause
->rx_pause
= 1;
10312 epause
->rx_pause
= 0;
10314 if (tp
->link_config
.active_flowctrl
& FLOW_CTRL_TX
)
10315 epause
->tx_pause
= 1;
10317 epause
->tx_pause
= 0;
10320 static int tg3_set_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
*epause
)
10322 struct tg3
*tp
= netdev_priv(dev
);
10325 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
10327 struct phy_device
*phydev
;
10329 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
10331 if (!(phydev
->supported
& SUPPORTED_Pause
) ||
10332 (!(phydev
->supported
& SUPPORTED_Asym_Pause
) &&
10333 (epause
->rx_pause
!= epause
->tx_pause
)))
10336 tp
->link_config
.flowctrl
= 0;
10337 if (epause
->rx_pause
) {
10338 tp
->link_config
.flowctrl
|= FLOW_CTRL_RX
;
10340 if (epause
->tx_pause
) {
10341 tp
->link_config
.flowctrl
|= FLOW_CTRL_TX
;
10342 newadv
= ADVERTISED_Pause
;
10344 newadv
= ADVERTISED_Pause
|
10345 ADVERTISED_Asym_Pause
;
10346 } else if (epause
->tx_pause
) {
10347 tp
->link_config
.flowctrl
|= FLOW_CTRL_TX
;
10348 newadv
= ADVERTISED_Asym_Pause
;
10352 if (epause
->autoneg
)
10353 tp
->tg3_flags
|= TG3_FLAG_PAUSE_AUTONEG
;
10355 tp
->tg3_flags
&= ~TG3_FLAG_PAUSE_AUTONEG
;
10357 if (tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
) {
10358 u32 oldadv
= phydev
->advertising
&
10359 (ADVERTISED_Pause
| ADVERTISED_Asym_Pause
);
10360 if (oldadv
!= newadv
) {
10361 phydev
->advertising
&=
10362 ~(ADVERTISED_Pause
|
10363 ADVERTISED_Asym_Pause
);
10364 phydev
->advertising
|= newadv
;
10365 if (phydev
->autoneg
) {
10367 * Always renegotiate the link to
10368 * inform our link partner of our
10369 * flow control settings, even if the
10370 * flow control is forced. Let
10371 * tg3_adjust_link() do the final
10372 * flow control setup.
10374 return phy_start_aneg(phydev
);
10378 if (!epause
->autoneg
)
10379 tg3_setup_flow_control(tp
, 0, 0);
10381 tp
->link_config
.orig_advertising
&=
10382 ~(ADVERTISED_Pause
|
10383 ADVERTISED_Asym_Pause
);
10384 tp
->link_config
.orig_advertising
|= newadv
;
10389 if (netif_running(dev
)) {
10390 tg3_netif_stop(tp
);
10394 tg3_full_lock(tp
, irq_sync
);
10396 if (epause
->autoneg
)
10397 tp
->tg3_flags
|= TG3_FLAG_PAUSE_AUTONEG
;
10399 tp
->tg3_flags
&= ~TG3_FLAG_PAUSE_AUTONEG
;
10400 if (epause
->rx_pause
)
10401 tp
->link_config
.flowctrl
|= FLOW_CTRL_RX
;
10403 tp
->link_config
.flowctrl
&= ~FLOW_CTRL_RX
;
10404 if (epause
->tx_pause
)
10405 tp
->link_config
.flowctrl
|= FLOW_CTRL_TX
;
10407 tp
->link_config
.flowctrl
&= ~FLOW_CTRL_TX
;
10409 if (netif_running(dev
)) {
10410 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
10411 err
= tg3_restart_hw(tp
, 1);
10413 tg3_netif_start(tp
);
10416 tg3_full_unlock(tp
);
10422 static int tg3_get_sset_count(struct net_device
*dev
, int sset
)
10426 return TG3_NUM_TEST
;
10428 return TG3_NUM_STATS
;
10430 return -EOPNOTSUPP
;
10434 static void tg3_get_strings(struct net_device
*dev
, u32 stringset
, u8
*buf
)
10436 switch (stringset
) {
10438 memcpy(buf
, ðtool_stats_keys
, sizeof(ethtool_stats_keys
));
10441 memcpy(buf
, ðtool_test_keys
, sizeof(ethtool_test_keys
));
10444 WARN_ON(1); /* we need a WARN() */
10449 static int tg3_set_phys_id(struct net_device
*dev
,
10450 enum ethtool_phys_id_state state
)
10452 struct tg3
*tp
= netdev_priv(dev
);
10454 if (!netif_running(tp
->dev
))
10458 case ETHTOOL_ID_ACTIVE
:
10459 return 1; /* cycle on/off once per second */
10461 case ETHTOOL_ID_ON
:
10462 tw32(MAC_LED_CTRL
, LED_CTRL_LNKLED_OVERRIDE
|
10463 LED_CTRL_1000MBPS_ON
|
10464 LED_CTRL_100MBPS_ON
|
10465 LED_CTRL_10MBPS_ON
|
10466 LED_CTRL_TRAFFIC_OVERRIDE
|
10467 LED_CTRL_TRAFFIC_BLINK
|
10468 LED_CTRL_TRAFFIC_LED
);
10471 case ETHTOOL_ID_OFF
:
10472 tw32(MAC_LED_CTRL
, LED_CTRL_LNKLED_OVERRIDE
|
10473 LED_CTRL_TRAFFIC_OVERRIDE
);
10476 case ETHTOOL_ID_INACTIVE
:
10477 tw32(MAC_LED_CTRL
, tp
->led_ctrl
);
10484 static void tg3_get_ethtool_stats(struct net_device
*dev
,
10485 struct ethtool_stats
*estats
, u64
*tmp_stats
)
10487 struct tg3
*tp
= netdev_priv(dev
);
10488 memcpy(tmp_stats
, tg3_get_estats(tp
), sizeof(tp
->estats
));
10491 static __be32
* tg3_vpd_readblock(struct tg3
*tp
)
10495 u32 offset
= 0, len
= 0;
10498 if ((tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) ||
10499 tg3_nvram_read(tp
, 0, &magic
))
10502 if (magic
== TG3_EEPROM_MAGIC
) {
10503 for (offset
= TG3_NVM_DIR_START
;
10504 offset
< TG3_NVM_DIR_END
;
10505 offset
+= TG3_NVM_DIRENT_SIZE
) {
10506 if (tg3_nvram_read(tp
, offset
, &val
))
10509 if ((val
>> TG3_NVM_DIRTYPE_SHIFT
) ==
10510 TG3_NVM_DIRTYPE_EXTVPD
)
10514 if (offset
!= TG3_NVM_DIR_END
) {
10515 len
= (val
& TG3_NVM_DIRTYPE_LENMSK
) * 4;
10516 if (tg3_nvram_read(tp
, offset
+ 4, &offset
))
10519 offset
= tg3_nvram_logical_addr(tp
, offset
);
10523 if (!offset
|| !len
) {
10524 offset
= TG3_NVM_VPD_OFF
;
10525 len
= TG3_NVM_VPD_LEN
;
10528 buf
= kmalloc(len
, GFP_KERNEL
);
10532 if (magic
== TG3_EEPROM_MAGIC
) {
10533 for (i
= 0; i
< len
; i
+= 4) {
10534 /* The data is in little-endian format in NVRAM.
10535 * Use the big-endian read routines to preserve
10536 * the byte order as it exists in NVRAM.
10538 if (tg3_nvram_read_be32(tp
, offset
+ i
, &buf
[i
/4]))
10544 unsigned int pos
= 0;
10546 ptr
= (u8
*)&buf
[0];
10547 for (i
= 0; pos
< len
&& i
< 3; i
++, pos
+= cnt
, ptr
+= cnt
) {
10548 cnt
= pci_read_vpd(tp
->pdev
, pos
,
10550 if (cnt
== -ETIMEDOUT
|| cnt
== -EINTR
)
10566 #define NVRAM_TEST_SIZE 0x100
10567 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
10568 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
10569 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
10570 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10571 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10573 static int tg3_test_nvram(struct tg3
*tp
)
10577 int i
, j
, k
, err
= 0, size
;
10579 if (tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
)
10582 if (tg3_nvram_read(tp
, 0, &magic
) != 0)
10585 if (magic
== TG3_EEPROM_MAGIC
)
10586 size
= NVRAM_TEST_SIZE
;
10587 else if ((magic
& TG3_EEPROM_MAGIC_FW_MSK
) == TG3_EEPROM_MAGIC_FW
) {
10588 if ((magic
& TG3_EEPROM_SB_FORMAT_MASK
) ==
10589 TG3_EEPROM_SB_FORMAT_1
) {
10590 switch (magic
& TG3_EEPROM_SB_REVISION_MASK
) {
10591 case TG3_EEPROM_SB_REVISION_0
:
10592 size
= NVRAM_SELFBOOT_FORMAT1_0_SIZE
;
10594 case TG3_EEPROM_SB_REVISION_2
:
10595 size
= NVRAM_SELFBOOT_FORMAT1_2_SIZE
;
10597 case TG3_EEPROM_SB_REVISION_3
:
10598 size
= NVRAM_SELFBOOT_FORMAT1_3_SIZE
;
10605 } else if ((magic
& TG3_EEPROM_MAGIC_HW_MSK
) == TG3_EEPROM_MAGIC_HW
)
10606 size
= NVRAM_SELFBOOT_HW_SIZE
;
10610 buf
= kmalloc(size
, GFP_KERNEL
);
10615 for (i
= 0, j
= 0; i
< size
; i
+= 4, j
++) {
10616 err
= tg3_nvram_read_be32(tp
, i
, &buf
[j
]);
10623 /* Selfboot format */
10624 magic
= be32_to_cpu(buf
[0]);
10625 if ((magic
& TG3_EEPROM_MAGIC_FW_MSK
) ==
10626 TG3_EEPROM_MAGIC_FW
) {
10627 u8
*buf8
= (u8
*) buf
, csum8
= 0;
10629 if ((magic
& TG3_EEPROM_SB_REVISION_MASK
) ==
10630 TG3_EEPROM_SB_REVISION_2
) {
10631 /* For rev 2, the csum doesn't include the MBA. */
10632 for (i
= 0; i
< TG3_EEPROM_SB_F1R2_MBA_OFF
; i
++)
10634 for (i
= TG3_EEPROM_SB_F1R2_MBA_OFF
+ 4; i
< size
; i
++)
10637 for (i
= 0; i
< size
; i
++)
10650 if ((magic
& TG3_EEPROM_MAGIC_HW_MSK
) ==
10651 TG3_EEPROM_MAGIC_HW
) {
10652 u8 data
[NVRAM_SELFBOOT_DATA_SIZE
];
10653 u8 parity
[NVRAM_SELFBOOT_DATA_SIZE
];
10654 u8
*buf8
= (u8
*) buf
;
10656 /* Separate the parity bits and the data bytes. */
10657 for (i
= 0, j
= 0, k
= 0; i
< NVRAM_SELFBOOT_HW_SIZE
; i
++) {
10658 if ((i
== 0) || (i
== 8)) {
10662 for (l
= 0, msk
= 0x80; l
< 7; l
++, msk
>>= 1)
10663 parity
[k
++] = buf8
[i
] & msk
;
10665 } else if (i
== 16) {
10669 for (l
= 0, msk
= 0x20; l
< 6; l
++, msk
>>= 1)
10670 parity
[k
++] = buf8
[i
] & msk
;
10673 for (l
= 0, msk
= 0x80; l
< 8; l
++, msk
>>= 1)
10674 parity
[k
++] = buf8
[i
] & msk
;
10677 data
[j
++] = buf8
[i
];
10681 for (i
= 0; i
< NVRAM_SELFBOOT_DATA_SIZE
; i
++) {
10682 u8 hw8
= hweight8(data
[i
]);
10684 if ((hw8
& 0x1) && parity
[i
])
10686 else if (!(hw8
& 0x1) && !parity
[i
])
10695 /* Bootstrap checksum at offset 0x10 */
10696 csum
= calc_crc((unsigned char *) buf
, 0x10);
10697 if (csum
!= le32_to_cpu(buf
[0x10/4]))
10700 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10701 csum
= calc_crc((unsigned char *) &buf
[0x74/4], 0x88);
10702 if (csum
!= le32_to_cpu(buf
[0xfc/4]))
10707 buf
= tg3_vpd_readblock(tp
);
10711 i
= pci_vpd_find_tag((u8
*)buf
, 0, TG3_NVM_VPD_LEN
,
10712 PCI_VPD_LRDT_RO_DATA
);
10714 j
= pci_vpd_lrdt_size(&((u8
*)buf
)[i
]);
10718 if (i
+ PCI_VPD_LRDT_TAG_SIZE
+ j
> TG3_NVM_VPD_LEN
)
10721 i
+= PCI_VPD_LRDT_TAG_SIZE
;
10722 j
= pci_vpd_find_info_keyword((u8
*)buf
, i
, j
,
10723 PCI_VPD_RO_KEYWORD_CHKSUM
);
10727 j
+= PCI_VPD_INFO_FLD_HDR_SIZE
;
10729 for (i
= 0; i
<= j
; i
++)
10730 csum8
+= ((u8
*)buf
)[i
];
10744 #define TG3_SERDES_TIMEOUT_SEC 2
10745 #define TG3_COPPER_TIMEOUT_SEC 6
10747 static int tg3_test_link(struct tg3
*tp
)
10751 if (!netif_running(tp
->dev
))
10754 if (tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
)
10755 max
= TG3_SERDES_TIMEOUT_SEC
;
10757 max
= TG3_COPPER_TIMEOUT_SEC
;
10759 for (i
= 0; i
< max
; i
++) {
10760 if (netif_carrier_ok(tp
->dev
))
10763 if (msleep_interruptible(1000))
10770 /* Only test the commonly used registers */
10771 static int tg3_test_registers(struct tg3
*tp
)
10773 int i
, is_5705
, is_5750
;
10774 u32 offset
, read_mask
, write_mask
, val
, save_val
, read_val
;
10778 #define TG3_FL_5705 0x1
10779 #define TG3_FL_NOT_5705 0x2
10780 #define TG3_FL_NOT_5788 0x4
10781 #define TG3_FL_NOT_5750 0x8
10785 /* MAC Control Registers */
10786 { MAC_MODE
, TG3_FL_NOT_5705
,
10787 0x00000000, 0x00ef6f8c },
10788 { MAC_MODE
, TG3_FL_5705
,
10789 0x00000000, 0x01ef6b8c },
10790 { MAC_STATUS
, TG3_FL_NOT_5705
,
10791 0x03800107, 0x00000000 },
10792 { MAC_STATUS
, TG3_FL_5705
,
10793 0x03800100, 0x00000000 },
10794 { MAC_ADDR_0_HIGH
, 0x0000,
10795 0x00000000, 0x0000ffff },
10796 { MAC_ADDR_0_LOW
, 0x0000,
10797 0x00000000, 0xffffffff },
10798 { MAC_RX_MTU_SIZE
, 0x0000,
10799 0x00000000, 0x0000ffff },
10800 { MAC_TX_MODE
, 0x0000,
10801 0x00000000, 0x00000070 },
10802 { MAC_TX_LENGTHS
, 0x0000,
10803 0x00000000, 0x00003fff },
10804 { MAC_RX_MODE
, TG3_FL_NOT_5705
,
10805 0x00000000, 0x000007fc },
10806 { MAC_RX_MODE
, TG3_FL_5705
,
10807 0x00000000, 0x000007dc },
10808 { MAC_HASH_REG_0
, 0x0000,
10809 0x00000000, 0xffffffff },
10810 { MAC_HASH_REG_1
, 0x0000,
10811 0x00000000, 0xffffffff },
10812 { MAC_HASH_REG_2
, 0x0000,
10813 0x00000000, 0xffffffff },
10814 { MAC_HASH_REG_3
, 0x0000,
10815 0x00000000, 0xffffffff },
10817 /* Receive Data and Receive BD Initiator Control Registers. */
10818 { RCVDBDI_JUMBO_BD
+0, TG3_FL_NOT_5705
,
10819 0x00000000, 0xffffffff },
10820 { RCVDBDI_JUMBO_BD
+4, TG3_FL_NOT_5705
,
10821 0x00000000, 0xffffffff },
10822 { RCVDBDI_JUMBO_BD
+8, TG3_FL_NOT_5705
,
10823 0x00000000, 0x00000003 },
10824 { RCVDBDI_JUMBO_BD
+0xc, TG3_FL_NOT_5705
,
10825 0x00000000, 0xffffffff },
10826 { RCVDBDI_STD_BD
+0, 0x0000,
10827 0x00000000, 0xffffffff },
10828 { RCVDBDI_STD_BD
+4, 0x0000,
10829 0x00000000, 0xffffffff },
10830 { RCVDBDI_STD_BD
+8, 0x0000,
10831 0x00000000, 0xffff0002 },
10832 { RCVDBDI_STD_BD
+0xc, 0x0000,
10833 0x00000000, 0xffffffff },
10835 /* Receive BD Initiator Control Registers. */
10836 { RCVBDI_STD_THRESH
, TG3_FL_NOT_5705
,
10837 0x00000000, 0xffffffff },
10838 { RCVBDI_STD_THRESH
, TG3_FL_5705
,
10839 0x00000000, 0x000003ff },
10840 { RCVBDI_JUMBO_THRESH
, TG3_FL_NOT_5705
,
10841 0x00000000, 0xffffffff },
10843 /* Host Coalescing Control Registers. */
10844 { HOSTCC_MODE
, TG3_FL_NOT_5705
,
10845 0x00000000, 0x00000004 },
10846 { HOSTCC_MODE
, TG3_FL_5705
,
10847 0x00000000, 0x000000f6 },
10848 { HOSTCC_RXCOL_TICKS
, TG3_FL_NOT_5705
,
10849 0x00000000, 0xffffffff },
10850 { HOSTCC_RXCOL_TICKS
, TG3_FL_5705
,
10851 0x00000000, 0x000003ff },
10852 { HOSTCC_TXCOL_TICKS
, TG3_FL_NOT_5705
,
10853 0x00000000, 0xffffffff },
10854 { HOSTCC_TXCOL_TICKS
, TG3_FL_5705
,
10855 0x00000000, 0x000003ff },
10856 { HOSTCC_RXMAX_FRAMES
, TG3_FL_NOT_5705
,
10857 0x00000000, 0xffffffff },
10858 { HOSTCC_RXMAX_FRAMES
, TG3_FL_5705
| TG3_FL_NOT_5788
,
10859 0x00000000, 0x000000ff },
10860 { HOSTCC_TXMAX_FRAMES
, TG3_FL_NOT_5705
,
10861 0x00000000, 0xffffffff },
10862 { HOSTCC_TXMAX_FRAMES
, TG3_FL_5705
| TG3_FL_NOT_5788
,
10863 0x00000000, 0x000000ff },
10864 { HOSTCC_RXCOAL_TICK_INT
, TG3_FL_NOT_5705
,
10865 0x00000000, 0xffffffff },
10866 { HOSTCC_TXCOAL_TICK_INT
, TG3_FL_NOT_5705
,
10867 0x00000000, 0xffffffff },
10868 { HOSTCC_RXCOAL_MAXF_INT
, TG3_FL_NOT_5705
,
10869 0x00000000, 0xffffffff },
10870 { HOSTCC_RXCOAL_MAXF_INT
, TG3_FL_5705
| TG3_FL_NOT_5788
,
10871 0x00000000, 0x000000ff },
10872 { HOSTCC_TXCOAL_MAXF_INT
, TG3_FL_NOT_5705
,
10873 0x00000000, 0xffffffff },
10874 { HOSTCC_TXCOAL_MAXF_INT
, TG3_FL_5705
| TG3_FL_NOT_5788
,
10875 0x00000000, 0x000000ff },
10876 { HOSTCC_STAT_COAL_TICKS
, TG3_FL_NOT_5705
,
10877 0x00000000, 0xffffffff },
10878 { HOSTCC_STATS_BLK_HOST_ADDR
, TG3_FL_NOT_5705
,
10879 0x00000000, 0xffffffff },
10880 { HOSTCC_STATS_BLK_HOST_ADDR
+4, TG3_FL_NOT_5705
,
10881 0x00000000, 0xffffffff },
10882 { HOSTCC_STATUS_BLK_HOST_ADDR
, 0x0000,
10883 0x00000000, 0xffffffff },
10884 { HOSTCC_STATUS_BLK_HOST_ADDR
+4, 0x0000,
10885 0x00000000, 0xffffffff },
10886 { HOSTCC_STATS_BLK_NIC_ADDR
, 0x0000,
10887 0xffffffff, 0x00000000 },
10888 { HOSTCC_STATUS_BLK_NIC_ADDR
, 0x0000,
10889 0xffffffff, 0x00000000 },
10891 /* Buffer Manager Control Registers. */
10892 { BUFMGR_MB_POOL_ADDR
, TG3_FL_NOT_5750
,
10893 0x00000000, 0x007fff80 },
10894 { BUFMGR_MB_POOL_SIZE
, TG3_FL_NOT_5750
,
10895 0x00000000, 0x007fffff },
10896 { BUFMGR_MB_RDMA_LOW_WATER
, 0x0000,
10897 0x00000000, 0x0000003f },
10898 { BUFMGR_MB_MACRX_LOW_WATER
, 0x0000,
10899 0x00000000, 0x000001ff },
10900 { BUFMGR_MB_HIGH_WATER
, 0x0000,
10901 0x00000000, 0x000001ff },
10902 { BUFMGR_DMA_DESC_POOL_ADDR
, TG3_FL_NOT_5705
,
10903 0xffffffff, 0x00000000 },
10904 { BUFMGR_DMA_DESC_POOL_SIZE
, TG3_FL_NOT_5705
,
10905 0xffffffff, 0x00000000 },
10907 /* Mailbox Registers */
10908 { GRCMBOX_RCVSTD_PROD_IDX
+4, 0x0000,
10909 0x00000000, 0x000001ff },
10910 { GRCMBOX_RCVJUMBO_PROD_IDX
+4, TG3_FL_NOT_5705
,
10911 0x00000000, 0x000001ff },
10912 { GRCMBOX_RCVRET_CON_IDX_0
+4, 0x0000,
10913 0x00000000, 0x000007ff },
10914 { GRCMBOX_SNDHOST_PROD_IDX_0
+4, 0x0000,
10915 0x00000000, 0x000001ff },
10917 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10920 is_5705
= is_5750
= 0;
10921 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
10923 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
10927 for (i
= 0; reg_tbl
[i
].offset
!= 0xffff; i
++) {
10928 if (is_5705
&& (reg_tbl
[i
].flags
& TG3_FL_NOT_5705
))
10931 if (!is_5705
&& (reg_tbl
[i
].flags
& TG3_FL_5705
))
10934 if ((tp
->tg3_flags2
& TG3_FLG2_IS_5788
) &&
10935 (reg_tbl
[i
].flags
& TG3_FL_NOT_5788
))
10938 if (is_5750
&& (reg_tbl
[i
].flags
& TG3_FL_NOT_5750
))
10941 offset
= (u32
) reg_tbl
[i
].offset
;
10942 read_mask
= reg_tbl
[i
].read_mask
;
10943 write_mask
= reg_tbl
[i
].write_mask
;
10945 /* Save the original register content */
10946 save_val
= tr32(offset
);
10948 /* Determine the read-only value. */
10949 read_val
= save_val
& read_mask
;
10951 /* Write zero to the register, then make sure the read-only bits
10952 * are not changed and the read/write bits are all zeros.
10956 val
= tr32(offset
);
10958 /* Test the read-only and read/write bits. */
10959 if (((val
& read_mask
) != read_val
) || (val
& write_mask
))
10962 /* Write ones to all the bits defined by RdMask and WrMask, then
10963 * make sure the read-only bits are not changed and the
10964 * read/write bits are all ones.
10966 tw32(offset
, read_mask
| write_mask
);
10968 val
= tr32(offset
);
10970 /* Test the read-only bits. */
10971 if ((val
& read_mask
) != read_val
)
10974 /* Test the read/write bits. */
10975 if ((val
& write_mask
) != write_mask
)
10978 tw32(offset
, save_val
);
10984 if (netif_msg_hw(tp
))
10985 netdev_err(tp
->dev
,
10986 "Register test failed at offset %x\n", offset
);
10987 tw32(offset
, save_val
);
10991 static int tg3_do_mem_test(struct tg3
*tp
, u32 offset
, u32 len
)
10993 static const u32 test_pattern
[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10997 for (i
= 0; i
< ARRAY_SIZE(test_pattern
); i
++) {
10998 for (j
= 0; j
< len
; j
+= 4) {
11001 tg3_write_mem(tp
, offset
+ j
, test_pattern
[i
]);
11002 tg3_read_mem(tp
, offset
+ j
, &val
);
11003 if (val
!= test_pattern
[i
])
11010 static int tg3_test_memory(struct tg3
*tp
)
11012 static struct mem_entry
{
11015 } mem_tbl_570x
[] = {
11016 { 0x00000000, 0x00b50},
11017 { 0x00002000, 0x1c000},
11018 { 0xffffffff, 0x00000}
11019 }, mem_tbl_5705
[] = {
11020 { 0x00000100, 0x0000c},
11021 { 0x00000200, 0x00008},
11022 { 0x00004000, 0x00800},
11023 { 0x00006000, 0x01000},
11024 { 0x00008000, 0x02000},
11025 { 0x00010000, 0x0e000},
11026 { 0xffffffff, 0x00000}
11027 }, mem_tbl_5755
[] = {
11028 { 0x00000200, 0x00008},
11029 { 0x00004000, 0x00800},
11030 { 0x00006000, 0x00800},
11031 { 0x00008000, 0x02000},
11032 { 0x00010000, 0x0c000},
11033 { 0xffffffff, 0x00000}
11034 }, mem_tbl_5906
[] = {
11035 { 0x00000200, 0x00008},
11036 { 0x00004000, 0x00400},
11037 { 0x00006000, 0x00400},
11038 { 0x00008000, 0x01000},
11039 { 0x00010000, 0x01000},
11040 { 0xffffffff, 0x00000}
11041 }, mem_tbl_5717
[] = {
11042 { 0x00000200, 0x00008},
11043 { 0x00010000, 0x0a000},
11044 { 0x00020000, 0x13c00},
11045 { 0xffffffff, 0x00000}
11046 }, mem_tbl_57765
[] = {
11047 { 0x00000200, 0x00008},
11048 { 0x00004000, 0x00800},
11049 { 0x00006000, 0x09800},
11050 { 0x00010000, 0x0a000},
11051 { 0xffffffff, 0x00000}
11053 struct mem_entry
*mem_tbl
;
11057 if (tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
)
11058 mem_tbl
= mem_tbl_5717
;
11059 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
11060 mem_tbl
= mem_tbl_57765
;
11061 else if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
11062 mem_tbl
= mem_tbl_5755
;
11063 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
11064 mem_tbl
= mem_tbl_5906
;
11065 else if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
11066 mem_tbl
= mem_tbl_5705
;
11068 mem_tbl
= mem_tbl_570x
;
11070 for (i
= 0; mem_tbl
[i
].offset
!= 0xffffffff; i
++) {
11071 err
= tg3_do_mem_test(tp
, mem_tbl
[i
].offset
, mem_tbl
[i
].len
);
11079 #define TG3_MAC_LOOPBACK 0
11080 #define TG3_PHY_LOOPBACK 1
11082 static int tg3_run_loopback(struct tg3
*tp
, u32 pktsz
, int loopback_mode
)
11084 u32 mac_mode
, rx_start_idx
, rx_idx
, tx_idx
, opaque_key
;
11085 u32 desc_idx
, coal_now
;
11086 struct sk_buff
*skb
, *rx_skb
;
11089 int num_pkts
, tx_len
, rx_len
, i
, err
;
11090 struct tg3_rx_buffer_desc
*desc
;
11091 struct tg3_napi
*tnapi
, *rnapi
;
11092 struct tg3_rx_prodring_set
*tpr
= &tp
->napi
[0].prodring
;
11094 tnapi
= &tp
->napi
[0];
11095 rnapi
= &tp
->napi
[0];
11096 if (tp
->irq_cnt
> 1) {
11097 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_RSS
)
11098 rnapi
= &tp
->napi
[1];
11099 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)
11100 tnapi
= &tp
->napi
[1];
11102 coal_now
= tnapi
->coal_now
| rnapi
->coal_now
;
11104 if (loopback_mode
== TG3_MAC_LOOPBACK
) {
11105 /* HW errata - mac loopback fails in some cases on 5780.
11106 * Normal traffic and PHY loopback are not affected by
11107 * errata. Also, the MAC loopback test is deprecated for
11108 * all newer ASIC revisions.
11110 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5780
||
11111 (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
))
11114 mac_mode
= tp
->mac_mode
&
11115 ~(MAC_MODE_PORT_MODE_MASK
| MAC_MODE_HALF_DUPLEX
);
11116 mac_mode
|= MAC_MODE_PORT_INT_LPBACK
;
11117 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
11118 mac_mode
|= MAC_MODE_LINK_POLARITY
;
11119 if (tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
)
11120 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
11122 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
11123 tw32(MAC_MODE
, mac_mode
);
11124 } else if (loopback_mode
== TG3_PHY_LOOPBACK
) {
11127 if (tp
->phy_flags
& TG3_PHYFLG_IS_FET
) {
11128 tg3_phy_fet_toggle_apd(tp
, false);
11129 val
= BMCR_LOOPBACK
| BMCR_FULLDPLX
| BMCR_SPEED100
;
11131 val
= BMCR_LOOPBACK
| BMCR_FULLDPLX
| BMCR_SPEED1000
;
11133 tg3_phy_toggle_automdix(tp
, 0);
11135 tg3_writephy(tp
, MII_BMCR
, val
);
11138 mac_mode
= tp
->mac_mode
&
11139 ~(MAC_MODE_PORT_MODE_MASK
| MAC_MODE_HALF_DUPLEX
);
11140 if (tp
->phy_flags
& TG3_PHYFLG_IS_FET
) {
11141 tg3_writephy(tp
, MII_TG3_FET_PTEST
,
11142 MII_TG3_FET_PTEST_FRC_TX_LINK
|
11143 MII_TG3_FET_PTEST_FRC_TX_LOCK
);
11144 /* The write needs to be flushed for the AC131 */
11145 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
11146 tg3_readphy(tp
, MII_TG3_FET_PTEST
, &val
);
11147 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
11149 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
11151 /* reset to prevent losing 1st rx packet intermittently */
11152 if (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
) {
11153 tw32_f(MAC_RX_MODE
, RX_MODE_RESET
);
11155 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
11157 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) {
11158 u32 masked_phy_id
= tp
->phy_id
& TG3_PHY_ID_MASK
;
11159 if (masked_phy_id
== TG3_PHY_ID_BCM5401
)
11160 mac_mode
&= ~MAC_MODE_LINK_POLARITY
;
11161 else if (masked_phy_id
== TG3_PHY_ID_BCM5411
)
11162 mac_mode
|= MAC_MODE_LINK_POLARITY
;
11163 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
11164 MII_TG3_EXT_CTRL_LNK3_LED_MODE
);
11166 tw32(MAC_MODE
, mac_mode
);
11168 /* Wait for link */
11169 for (i
= 0; i
< 100; i
++) {
11170 if (tr32(MAC_TX_STATUS
) & TX_STATUS_LINK_UP
)
11181 skb
= netdev_alloc_skb(tp
->dev
, tx_len
);
11185 tx_data
= skb_put(skb
, tx_len
);
11186 memcpy(tx_data
, tp
->dev
->dev_addr
, 6);
11187 memset(tx_data
+ 6, 0x0, 8);
11189 tw32(MAC_RX_MTU_SIZE
, tx_len
+ ETH_FCS_LEN
);
11191 for (i
= 14; i
< tx_len
; i
++)
11192 tx_data
[i
] = (u8
) (i
& 0xff);
11194 map
= pci_map_single(tp
->pdev
, skb
->data
, tx_len
, PCI_DMA_TODEVICE
);
11195 if (pci_dma_mapping_error(tp
->pdev
, map
)) {
11196 dev_kfree_skb(skb
);
11200 tw32_f(HOSTCC_MODE
, tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
|
11205 rx_start_idx
= rnapi
->hw_status
->idx
[0].rx_producer
;
11209 tg3_set_txd(tnapi
, tnapi
->tx_prod
, map
, tx_len
, 0, 1);
11214 tw32_tx_mbox(tnapi
->prodmbox
, tnapi
->tx_prod
);
11215 tr32_mailbox(tnapi
->prodmbox
);
11219 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
11220 for (i
= 0; i
< 35; i
++) {
11221 tw32_f(HOSTCC_MODE
, tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
|
11226 tx_idx
= tnapi
->hw_status
->idx
[0].tx_consumer
;
11227 rx_idx
= rnapi
->hw_status
->idx
[0].rx_producer
;
11228 if ((tx_idx
== tnapi
->tx_prod
) &&
11229 (rx_idx
== (rx_start_idx
+ num_pkts
)))
11233 pci_unmap_single(tp
->pdev
, map
, tx_len
, PCI_DMA_TODEVICE
);
11234 dev_kfree_skb(skb
);
11236 if (tx_idx
!= tnapi
->tx_prod
)
11239 if (rx_idx
!= rx_start_idx
+ num_pkts
)
11242 desc
= &rnapi
->rx_rcb
[rx_start_idx
];
11243 desc_idx
= desc
->opaque
& RXD_OPAQUE_INDEX_MASK
;
11244 opaque_key
= desc
->opaque
& RXD_OPAQUE_RING_MASK
;
11246 if ((desc
->err_vlan
& RXD_ERR_MASK
) != 0 &&
11247 (desc
->err_vlan
!= RXD_ERR_ODD_NIBBLE_RCVD_MII
))
11250 rx_len
= ((desc
->idx_len
& RXD_LEN_MASK
) >> RXD_LEN_SHIFT
) - 4;
11251 if (rx_len
!= tx_len
)
11254 if (pktsz
<= TG3_RX_STD_DMA_SZ
- ETH_FCS_LEN
) {
11255 if (opaque_key
!= RXD_OPAQUE_RING_STD
)
11258 rx_skb
= tpr
->rx_std_buffers
[desc_idx
].skb
;
11259 map
= dma_unmap_addr(&tpr
->rx_std_buffers
[desc_idx
], mapping
);
11261 if (opaque_key
!= RXD_OPAQUE_RING_JUMBO
)
11264 rx_skb
= tpr
->rx_jmb_buffers
[desc_idx
].skb
;
11265 map
= dma_unmap_addr(&tpr
->rx_jmb_buffers
[desc_idx
], mapping
);
11268 pci_dma_sync_single_for_cpu(tp
->pdev
, map
, rx_len
, PCI_DMA_FROMDEVICE
);
11270 for (i
= 14; i
< tx_len
; i
++) {
11271 if (*(rx_skb
->data
+ i
) != (u8
) (i
& 0xff))
11276 /* tg3_free_rings will unmap and free the rx_skb */
11281 #define TG3_MAC_LOOPBACK_FAILED 1
11282 #define TG3_PHY_LOOPBACK_FAILED 2
11283 #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
11284 TG3_PHY_LOOPBACK_FAILED)
11286 static int tg3_test_loopback(struct tg3
*tp
)
11289 u32 eee_cap
, cpmuctrl
= 0;
11291 if (!netif_running(tp
->dev
))
11292 return TG3_LOOPBACK_FAILED
;
11294 eee_cap
= tp
->phy_flags
& TG3_PHYFLG_EEE_CAP
;
11295 tp
->phy_flags
&= ~TG3_PHYFLG_EEE_CAP
;
11297 err
= tg3_reset_hw(tp
, 1);
11299 err
= TG3_LOOPBACK_FAILED
;
11303 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_RSS
) {
11306 /* Reroute all rx packets to the 1st queue */
11307 for (i
= MAC_RSS_INDIR_TBL_0
;
11308 i
< MAC_RSS_INDIR_TBL_0
+ TG3_RSS_INDIR_TBL_SIZE
; i
+= 4)
11312 /* Turn off gphy autopowerdown. */
11313 if (tp
->phy_flags
& TG3_PHYFLG_ENABLE_APD
)
11314 tg3_phy_toggle_apd(tp
, false);
11316 if (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) {
11320 tw32(TG3_CPMU_MUTEX_REQ
, CPMU_MUTEX_REQ_DRIVER
);
11322 /* Wait for up to 40 microseconds to acquire lock. */
11323 for (i
= 0; i
< 4; i
++) {
11324 status
= tr32(TG3_CPMU_MUTEX_GNT
);
11325 if (status
== CPMU_MUTEX_GNT_DRIVER
)
11330 if (status
!= CPMU_MUTEX_GNT_DRIVER
) {
11331 err
= TG3_LOOPBACK_FAILED
;
11335 /* Turn off link-based power management. */
11336 cpmuctrl
= tr32(TG3_CPMU_CTRL
);
11337 tw32(TG3_CPMU_CTRL
,
11338 cpmuctrl
& ~(CPMU_CTRL_LINK_SPEED_MODE
|
11339 CPMU_CTRL_LINK_AWARE_MODE
));
11342 if (tg3_run_loopback(tp
, ETH_FRAME_LEN
, TG3_MAC_LOOPBACK
))
11343 err
|= TG3_MAC_LOOPBACK_FAILED
;
11345 if ((tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
) &&
11346 tg3_run_loopback(tp
, 9000 + ETH_HLEN
, TG3_MAC_LOOPBACK
))
11347 err
|= (TG3_MAC_LOOPBACK_FAILED
<< 2);
11349 if (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) {
11350 tw32(TG3_CPMU_CTRL
, cpmuctrl
);
11352 /* Release the mutex */
11353 tw32(TG3_CPMU_MUTEX_GNT
, CPMU_MUTEX_GNT_DRIVER
);
11356 if (!(tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) &&
11357 !(tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
)) {
11358 if (tg3_run_loopback(tp
, ETH_FRAME_LEN
, TG3_PHY_LOOPBACK
))
11359 err
|= TG3_PHY_LOOPBACK_FAILED
;
11360 if ((tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
) &&
11361 tg3_run_loopback(tp
, 9000 + ETH_HLEN
, TG3_PHY_LOOPBACK
))
11362 err
|= (TG3_PHY_LOOPBACK_FAILED
<< 2);
11365 /* Re-enable gphy autopowerdown. */
11366 if (tp
->phy_flags
& TG3_PHYFLG_ENABLE_APD
)
11367 tg3_phy_toggle_apd(tp
, true);
11370 tp
->phy_flags
|= eee_cap
;
11375 static void tg3_self_test(struct net_device
*dev
, struct ethtool_test
*etest
,
11378 struct tg3
*tp
= netdev_priv(dev
);
11380 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)
11383 memset(data
, 0, sizeof(u64
) * TG3_NUM_TEST
);
11385 if (tg3_test_nvram(tp
) != 0) {
11386 etest
->flags
|= ETH_TEST_FL_FAILED
;
11389 if (tg3_test_link(tp
) != 0) {
11390 etest
->flags
|= ETH_TEST_FL_FAILED
;
11393 if (etest
->flags
& ETH_TEST_FL_OFFLINE
) {
11394 int err
, err2
= 0, irq_sync
= 0;
11396 if (netif_running(dev
)) {
11398 tg3_netif_stop(tp
);
11402 tg3_full_lock(tp
, irq_sync
);
11404 tg3_halt(tp
, RESET_KIND_SUSPEND
, 1);
11405 err
= tg3_nvram_lock(tp
);
11406 tg3_halt_cpu(tp
, RX_CPU_BASE
);
11407 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
11408 tg3_halt_cpu(tp
, TX_CPU_BASE
);
11410 tg3_nvram_unlock(tp
);
11412 if (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
)
11415 if (tg3_test_registers(tp
) != 0) {
11416 etest
->flags
|= ETH_TEST_FL_FAILED
;
11419 if (tg3_test_memory(tp
) != 0) {
11420 etest
->flags
|= ETH_TEST_FL_FAILED
;
11423 if ((data
[4] = tg3_test_loopback(tp
)) != 0)
11424 etest
->flags
|= ETH_TEST_FL_FAILED
;
11426 tg3_full_unlock(tp
);
11428 if (tg3_test_interrupt(tp
) != 0) {
11429 etest
->flags
|= ETH_TEST_FL_FAILED
;
11433 tg3_full_lock(tp
, 0);
11435 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
11436 if (netif_running(dev
)) {
11437 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
11438 err2
= tg3_restart_hw(tp
, 1);
11440 tg3_netif_start(tp
);
11443 tg3_full_unlock(tp
);
11445 if (irq_sync
&& !err2
)
11448 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)
11449 tg3_power_down(tp
);
11453 static int tg3_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
11455 struct mii_ioctl_data
*data
= if_mii(ifr
);
11456 struct tg3
*tp
= netdev_priv(dev
);
11459 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
11460 struct phy_device
*phydev
;
11461 if (!(tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
))
11463 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
11464 return phy_mii_ioctl(phydev
, ifr
, cmd
);
11469 data
->phy_id
= tp
->phy_addr
;
11472 case SIOCGMIIREG
: {
11475 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
)
11476 break; /* We have no PHY */
11478 if (!netif_running(dev
))
11481 spin_lock_bh(&tp
->lock
);
11482 err
= tg3_readphy(tp
, data
->reg_num
& 0x1f, &mii_regval
);
11483 spin_unlock_bh(&tp
->lock
);
11485 data
->val_out
= mii_regval
;
11491 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
)
11492 break; /* We have no PHY */
11494 if (!netif_running(dev
))
11497 spin_lock_bh(&tp
->lock
);
11498 err
= tg3_writephy(tp
, data
->reg_num
& 0x1f, data
->val_in
);
11499 spin_unlock_bh(&tp
->lock
);
11507 return -EOPNOTSUPP
;
11510 static int tg3_get_coalesce(struct net_device
*dev
, struct ethtool_coalesce
*ec
)
11512 struct tg3
*tp
= netdev_priv(dev
);
11514 memcpy(ec
, &tp
->coal
, sizeof(*ec
));
11518 static int tg3_set_coalesce(struct net_device
*dev
, struct ethtool_coalesce
*ec
)
11520 struct tg3
*tp
= netdev_priv(dev
);
11521 u32 max_rxcoal_tick_int
= 0, max_txcoal_tick_int
= 0;
11522 u32 max_stat_coal_ticks
= 0, min_stat_coal_ticks
= 0;
11524 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
11525 max_rxcoal_tick_int
= MAX_RXCOAL_TICK_INT
;
11526 max_txcoal_tick_int
= MAX_TXCOAL_TICK_INT
;
11527 max_stat_coal_ticks
= MAX_STAT_COAL_TICKS
;
11528 min_stat_coal_ticks
= MIN_STAT_COAL_TICKS
;
11531 if ((ec
->rx_coalesce_usecs
> MAX_RXCOL_TICKS
) ||
11532 (ec
->tx_coalesce_usecs
> MAX_TXCOL_TICKS
) ||
11533 (ec
->rx_max_coalesced_frames
> MAX_RXMAX_FRAMES
) ||
11534 (ec
->tx_max_coalesced_frames
> MAX_TXMAX_FRAMES
) ||
11535 (ec
->rx_coalesce_usecs_irq
> max_rxcoal_tick_int
) ||
11536 (ec
->tx_coalesce_usecs_irq
> max_txcoal_tick_int
) ||
11537 (ec
->rx_max_coalesced_frames_irq
> MAX_RXCOAL_MAXF_INT
) ||
11538 (ec
->tx_max_coalesced_frames_irq
> MAX_TXCOAL_MAXF_INT
) ||
11539 (ec
->stats_block_coalesce_usecs
> max_stat_coal_ticks
) ||
11540 (ec
->stats_block_coalesce_usecs
< min_stat_coal_ticks
))
11543 /* No rx interrupts will be generated if both are zero */
11544 if ((ec
->rx_coalesce_usecs
== 0) &&
11545 (ec
->rx_max_coalesced_frames
== 0))
11548 /* No tx interrupts will be generated if both are zero */
11549 if ((ec
->tx_coalesce_usecs
== 0) &&
11550 (ec
->tx_max_coalesced_frames
== 0))
11553 /* Only copy relevant parameters, ignore all others. */
11554 tp
->coal
.rx_coalesce_usecs
= ec
->rx_coalesce_usecs
;
11555 tp
->coal
.tx_coalesce_usecs
= ec
->tx_coalesce_usecs
;
11556 tp
->coal
.rx_max_coalesced_frames
= ec
->rx_max_coalesced_frames
;
11557 tp
->coal
.tx_max_coalesced_frames
= ec
->tx_max_coalesced_frames
;
11558 tp
->coal
.rx_coalesce_usecs_irq
= ec
->rx_coalesce_usecs_irq
;
11559 tp
->coal
.tx_coalesce_usecs_irq
= ec
->tx_coalesce_usecs_irq
;
11560 tp
->coal
.rx_max_coalesced_frames_irq
= ec
->rx_max_coalesced_frames_irq
;
11561 tp
->coal
.tx_max_coalesced_frames_irq
= ec
->tx_max_coalesced_frames_irq
;
11562 tp
->coal
.stats_block_coalesce_usecs
= ec
->stats_block_coalesce_usecs
;
11564 if (netif_running(dev
)) {
11565 tg3_full_lock(tp
, 0);
11566 __tg3_set_coalesce(tp
, &tp
->coal
);
11567 tg3_full_unlock(tp
);
11572 static const struct ethtool_ops tg3_ethtool_ops
= {
11573 .get_settings
= tg3_get_settings
,
11574 .set_settings
= tg3_set_settings
,
11575 .get_drvinfo
= tg3_get_drvinfo
,
11576 .get_regs_len
= tg3_get_regs_len
,
11577 .get_regs
= tg3_get_regs
,
11578 .get_wol
= tg3_get_wol
,
11579 .set_wol
= tg3_set_wol
,
11580 .get_msglevel
= tg3_get_msglevel
,
11581 .set_msglevel
= tg3_set_msglevel
,
11582 .nway_reset
= tg3_nway_reset
,
11583 .get_link
= ethtool_op_get_link
,
11584 .get_eeprom_len
= tg3_get_eeprom_len
,
11585 .get_eeprom
= tg3_get_eeprom
,
11586 .set_eeprom
= tg3_set_eeprom
,
11587 .get_ringparam
= tg3_get_ringparam
,
11588 .set_ringparam
= tg3_set_ringparam
,
11589 .get_pauseparam
= tg3_get_pauseparam
,
11590 .set_pauseparam
= tg3_set_pauseparam
,
11591 .self_test
= tg3_self_test
,
11592 .get_strings
= tg3_get_strings
,
11593 .set_phys_id
= tg3_set_phys_id
,
11594 .get_ethtool_stats
= tg3_get_ethtool_stats
,
11595 .get_coalesce
= tg3_get_coalesce
,
11596 .set_coalesce
= tg3_set_coalesce
,
11597 .get_sset_count
= tg3_get_sset_count
,
11600 static void __devinit
tg3_get_eeprom_size(struct tg3
*tp
)
11602 u32 cursize
, val
, magic
;
11604 tp
->nvram_size
= EEPROM_CHIP_SIZE
;
11606 if (tg3_nvram_read(tp
, 0, &magic
) != 0)
11609 if ((magic
!= TG3_EEPROM_MAGIC
) &&
11610 ((magic
& TG3_EEPROM_MAGIC_FW_MSK
) != TG3_EEPROM_MAGIC_FW
) &&
11611 ((magic
& TG3_EEPROM_MAGIC_HW_MSK
) != TG3_EEPROM_MAGIC_HW
))
11615 * Size the chip by reading offsets at increasing powers of two.
11616 * When we encounter our validation signature, we know the addressing
11617 * has wrapped around, and thus have our chip size.
11621 while (cursize
< tp
->nvram_size
) {
11622 if (tg3_nvram_read(tp
, cursize
, &val
) != 0)
11631 tp
->nvram_size
= cursize
;
11634 static void __devinit
tg3_get_nvram_size(struct tg3
*tp
)
11638 if ((tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) ||
11639 tg3_nvram_read(tp
, 0, &val
) != 0)
11642 /* Selfboot format */
11643 if (val
!= TG3_EEPROM_MAGIC
) {
11644 tg3_get_eeprom_size(tp
);
11648 if (tg3_nvram_read(tp
, 0xf0, &val
) == 0) {
11650 /* This is confusing. We want to operate on the
11651 * 16-bit value at offset 0xf2. The tg3_nvram_read()
11652 * call will read from NVRAM and byteswap the data
11653 * according to the byteswapping settings for all
11654 * other register accesses. This ensures the data we
11655 * want will always reside in the lower 16-bits.
11656 * However, the data in NVRAM is in LE format, which
11657 * means the data from the NVRAM read will always be
11658 * opposite the endianness of the CPU. The 16-bit
11659 * byteswap then brings the data to CPU endianness.
11661 tp
->nvram_size
= swab16((u16
)(val
& 0x0000ffff)) * 1024;
11665 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
11668 static void __devinit
tg3_get_nvram_info(struct tg3
*tp
)
11672 nvcfg1
= tr32(NVRAM_CFG1
);
11673 if (nvcfg1
& NVRAM_CFG1_FLASHIF_ENAB
) {
11674 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11676 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
11677 tw32(NVRAM_CFG1
, nvcfg1
);
11680 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
) ||
11681 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
11682 switch (nvcfg1
& NVRAM_CFG1_VENDOR_MASK
) {
11683 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED
:
11684 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11685 tp
->nvram_pagesize
= ATMEL_AT45DB0X1B_PAGE_SIZE
;
11686 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11688 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED
:
11689 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11690 tp
->nvram_pagesize
= ATMEL_AT25F512_PAGE_SIZE
;
11692 case FLASH_VENDOR_ATMEL_EEPROM
:
11693 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11694 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
11695 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11697 case FLASH_VENDOR_ST
:
11698 tp
->nvram_jedecnum
= JEDEC_ST
;
11699 tp
->nvram_pagesize
= ST_M45PEX0_PAGE_SIZE
;
11700 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11702 case FLASH_VENDOR_SAIFUN
:
11703 tp
->nvram_jedecnum
= JEDEC_SAIFUN
;
11704 tp
->nvram_pagesize
= SAIFUN_SA25F0XX_PAGE_SIZE
;
11706 case FLASH_VENDOR_SST_SMALL
:
11707 case FLASH_VENDOR_SST_LARGE
:
11708 tp
->nvram_jedecnum
= JEDEC_SST
;
11709 tp
->nvram_pagesize
= SST_25VF0X0_PAGE_SIZE
;
11713 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11714 tp
->nvram_pagesize
= ATMEL_AT45DB0X1B_PAGE_SIZE
;
11715 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11719 static void __devinit
tg3_nvram_get_pagesize(struct tg3
*tp
, u32 nvmcfg1
)
11721 switch (nvmcfg1
& NVRAM_CFG1_5752PAGE_SIZE_MASK
) {
11722 case FLASH_5752PAGE_SIZE_256
:
11723 tp
->nvram_pagesize
= 256;
11725 case FLASH_5752PAGE_SIZE_512
:
11726 tp
->nvram_pagesize
= 512;
11728 case FLASH_5752PAGE_SIZE_1K
:
11729 tp
->nvram_pagesize
= 1024;
11731 case FLASH_5752PAGE_SIZE_2K
:
11732 tp
->nvram_pagesize
= 2048;
11734 case FLASH_5752PAGE_SIZE_4K
:
11735 tp
->nvram_pagesize
= 4096;
11737 case FLASH_5752PAGE_SIZE_264
:
11738 tp
->nvram_pagesize
= 264;
11740 case FLASH_5752PAGE_SIZE_528
:
11741 tp
->nvram_pagesize
= 528;
11746 static void __devinit
tg3_get_5752_nvram_info(struct tg3
*tp
)
11750 nvcfg1
= tr32(NVRAM_CFG1
);
11752 /* NVRAM protection for TPM */
11753 if (nvcfg1
& (1 << 27))
11754 tp
->tg3_flags3
|= TG3_FLG3_PROTECTED_NVRAM
;
11756 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11757 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ
:
11758 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ
:
11759 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11760 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11762 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
11763 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11764 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11765 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11767 case FLASH_5752VENDOR_ST_M45PE10
:
11768 case FLASH_5752VENDOR_ST_M45PE20
:
11769 case FLASH_5752VENDOR_ST_M45PE40
:
11770 tp
->nvram_jedecnum
= JEDEC_ST
;
11771 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11772 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11776 if (tp
->tg3_flags2
& TG3_FLG2_FLASH
) {
11777 tg3_nvram_get_pagesize(tp
, nvcfg1
);
11779 /* For eeprom, set pagesize to maximum eeprom size */
11780 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
11782 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
11783 tw32(NVRAM_CFG1
, nvcfg1
);
11787 static void __devinit
tg3_get_5755_nvram_info(struct tg3
*tp
)
11789 u32 nvcfg1
, protect
= 0;
11791 nvcfg1
= tr32(NVRAM_CFG1
);
11793 /* NVRAM protection for TPM */
11794 if (nvcfg1
& (1 << 27)) {
11795 tp
->tg3_flags3
|= TG3_FLG3_PROTECTED_NVRAM
;
11799 nvcfg1
&= NVRAM_CFG1_5752VENDOR_MASK
;
11801 case FLASH_5755VENDOR_ATMEL_FLASH_1
:
11802 case FLASH_5755VENDOR_ATMEL_FLASH_2
:
11803 case FLASH_5755VENDOR_ATMEL_FLASH_3
:
11804 case FLASH_5755VENDOR_ATMEL_FLASH_5
:
11805 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11806 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11807 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11808 tp
->nvram_pagesize
= 264;
11809 if (nvcfg1
== FLASH_5755VENDOR_ATMEL_FLASH_1
||
11810 nvcfg1
== FLASH_5755VENDOR_ATMEL_FLASH_5
)
11811 tp
->nvram_size
= (protect
? 0x3e200 :
11812 TG3_NVRAM_SIZE_512KB
);
11813 else if (nvcfg1
== FLASH_5755VENDOR_ATMEL_FLASH_2
)
11814 tp
->nvram_size
= (protect
? 0x1f200 :
11815 TG3_NVRAM_SIZE_256KB
);
11817 tp
->nvram_size
= (protect
? 0x1f200 :
11818 TG3_NVRAM_SIZE_128KB
);
11820 case FLASH_5752VENDOR_ST_M45PE10
:
11821 case FLASH_5752VENDOR_ST_M45PE20
:
11822 case FLASH_5752VENDOR_ST_M45PE40
:
11823 tp
->nvram_jedecnum
= JEDEC_ST
;
11824 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11825 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11826 tp
->nvram_pagesize
= 256;
11827 if (nvcfg1
== FLASH_5752VENDOR_ST_M45PE10
)
11828 tp
->nvram_size
= (protect
?
11829 TG3_NVRAM_SIZE_64KB
:
11830 TG3_NVRAM_SIZE_128KB
);
11831 else if (nvcfg1
== FLASH_5752VENDOR_ST_M45PE20
)
11832 tp
->nvram_size
= (protect
?
11833 TG3_NVRAM_SIZE_64KB
:
11834 TG3_NVRAM_SIZE_256KB
);
11836 tp
->nvram_size
= (protect
?
11837 TG3_NVRAM_SIZE_128KB
:
11838 TG3_NVRAM_SIZE_512KB
);
11843 static void __devinit
tg3_get_5787_nvram_info(struct tg3
*tp
)
11847 nvcfg1
= tr32(NVRAM_CFG1
);
11849 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11850 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ
:
11851 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ
:
11852 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ
:
11853 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ
:
11854 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11855 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11856 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
11858 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
11859 tw32(NVRAM_CFG1
, nvcfg1
);
11861 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
11862 case FLASH_5755VENDOR_ATMEL_FLASH_1
:
11863 case FLASH_5755VENDOR_ATMEL_FLASH_2
:
11864 case FLASH_5755VENDOR_ATMEL_FLASH_3
:
11865 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11866 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11867 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11868 tp
->nvram_pagesize
= 264;
11870 case FLASH_5752VENDOR_ST_M45PE10
:
11871 case FLASH_5752VENDOR_ST_M45PE20
:
11872 case FLASH_5752VENDOR_ST_M45PE40
:
11873 tp
->nvram_jedecnum
= JEDEC_ST
;
11874 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11875 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11876 tp
->nvram_pagesize
= 256;
11881 static void __devinit
tg3_get_5761_nvram_info(struct tg3
*tp
)
11883 u32 nvcfg1
, protect
= 0;
11885 nvcfg1
= tr32(NVRAM_CFG1
);
11887 /* NVRAM protection for TPM */
11888 if (nvcfg1
& (1 << 27)) {
11889 tp
->tg3_flags3
|= TG3_FLG3_PROTECTED_NVRAM
;
11893 nvcfg1
&= NVRAM_CFG1_5752VENDOR_MASK
;
11895 case FLASH_5761VENDOR_ATMEL_ADB021D
:
11896 case FLASH_5761VENDOR_ATMEL_ADB041D
:
11897 case FLASH_5761VENDOR_ATMEL_ADB081D
:
11898 case FLASH_5761VENDOR_ATMEL_ADB161D
:
11899 case FLASH_5761VENDOR_ATMEL_MDB021D
:
11900 case FLASH_5761VENDOR_ATMEL_MDB041D
:
11901 case FLASH_5761VENDOR_ATMEL_MDB081D
:
11902 case FLASH_5761VENDOR_ATMEL_MDB161D
:
11903 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11904 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11905 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11906 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
11907 tp
->nvram_pagesize
= 256;
11909 case FLASH_5761VENDOR_ST_A_M45PE20
:
11910 case FLASH_5761VENDOR_ST_A_M45PE40
:
11911 case FLASH_5761VENDOR_ST_A_M45PE80
:
11912 case FLASH_5761VENDOR_ST_A_M45PE16
:
11913 case FLASH_5761VENDOR_ST_M_M45PE20
:
11914 case FLASH_5761VENDOR_ST_M_M45PE40
:
11915 case FLASH_5761VENDOR_ST_M_M45PE80
:
11916 case FLASH_5761VENDOR_ST_M_M45PE16
:
11917 tp
->nvram_jedecnum
= JEDEC_ST
;
11918 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11919 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11920 tp
->nvram_pagesize
= 256;
11925 tp
->nvram_size
= tr32(NVRAM_ADDR_LOCKOUT
);
11928 case FLASH_5761VENDOR_ATMEL_ADB161D
:
11929 case FLASH_5761VENDOR_ATMEL_MDB161D
:
11930 case FLASH_5761VENDOR_ST_A_M45PE16
:
11931 case FLASH_5761VENDOR_ST_M_M45PE16
:
11932 tp
->nvram_size
= TG3_NVRAM_SIZE_2MB
;
11934 case FLASH_5761VENDOR_ATMEL_ADB081D
:
11935 case FLASH_5761VENDOR_ATMEL_MDB081D
:
11936 case FLASH_5761VENDOR_ST_A_M45PE80
:
11937 case FLASH_5761VENDOR_ST_M_M45PE80
:
11938 tp
->nvram_size
= TG3_NVRAM_SIZE_1MB
;
11940 case FLASH_5761VENDOR_ATMEL_ADB041D
:
11941 case FLASH_5761VENDOR_ATMEL_MDB041D
:
11942 case FLASH_5761VENDOR_ST_A_M45PE40
:
11943 case FLASH_5761VENDOR_ST_M_M45PE40
:
11944 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
11946 case FLASH_5761VENDOR_ATMEL_ADB021D
:
11947 case FLASH_5761VENDOR_ATMEL_MDB021D
:
11948 case FLASH_5761VENDOR_ST_A_M45PE20
:
11949 case FLASH_5761VENDOR_ST_M_M45PE20
:
11950 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
11956 static void __devinit
tg3_get_5906_nvram_info(struct tg3
*tp
)
11958 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11959 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11960 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
11963 static void __devinit
tg3_get_57780_nvram_info(struct tg3
*tp
)
11967 nvcfg1
= tr32(NVRAM_CFG1
);
11969 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11970 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ
:
11971 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ
:
11972 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11973 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11974 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
11976 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
11977 tw32(NVRAM_CFG1
, nvcfg1
);
11979 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
11980 case FLASH_57780VENDOR_ATMEL_AT45DB011D
:
11981 case FLASH_57780VENDOR_ATMEL_AT45DB011B
:
11982 case FLASH_57780VENDOR_ATMEL_AT45DB021D
:
11983 case FLASH_57780VENDOR_ATMEL_AT45DB021B
:
11984 case FLASH_57780VENDOR_ATMEL_AT45DB041D
:
11985 case FLASH_57780VENDOR_ATMEL_AT45DB041B
:
11986 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11987 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11988 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11990 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11991 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
11992 case FLASH_57780VENDOR_ATMEL_AT45DB011D
:
11993 case FLASH_57780VENDOR_ATMEL_AT45DB011B
:
11994 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
11996 case FLASH_57780VENDOR_ATMEL_AT45DB021D
:
11997 case FLASH_57780VENDOR_ATMEL_AT45DB021B
:
11998 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
12000 case FLASH_57780VENDOR_ATMEL_AT45DB041D
:
12001 case FLASH_57780VENDOR_ATMEL_AT45DB041B
:
12002 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
12006 case FLASH_5752VENDOR_ST_M45PE10
:
12007 case FLASH_5752VENDOR_ST_M45PE20
:
12008 case FLASH_5752VENDOR_ST_M45PE40
:
12009 tp
->nvram_jedecnum
= JEDEC_ST
;
12010 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
12011 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
12013 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
12014 case FLASH_5752VENDOR_ST_M45PE10
:
12015 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
12017 case FLASH_5752VENDOR_ST_M45PE20
:
12018 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
12020 case FLASH_5752VENDOR_ST_M45PE40
:
12021 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
12026 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM
;
12030 tg3_nvram_get_pagesize(tp
, nvcfg1
);
12031 if (tp
->nvram_pagesize
!= 264 && tp
->nvram_pagesize
!= 528)
12032 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
12036 static void __devinit
tg3_get_5717_nvram_info(struct tg3
*tp
)
12040 nvcfg1
= tr32(NVRAM_CFG1
);
12042 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
12043 case FLASH_5717VENDOR_ATMEL_EEPROM
:
12044 case FLASH_5717VENDOR_MICRO_EEPROM
:
12045 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
12046 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
12047 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
12049 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
12050 tw32(NVRAM_CFG1
, nvcfg1
);
12052 case FLASH_5717VENDOR_ATMEL_MDB011D
:
12053 case FLASH_5717VENDOR_ATMEL_ADB011B
:
12054 case FLASH_5717VENDOR_ATMEL_ADB011D
:
12055 case FLASH_5717VENDOR_ATMEL_MDB021D
:
12056 case FLASH_5717VENDOR_ATMEL_ADB021B
:
12057 case FLASH_5717VENDOR_ATMEL_ADB021D
:
12058 case FLASH_5717VENDOR_ATMEL_45USPT
:
12059 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
12060 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
12061 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
12063 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
12064 case FLASH_5717VENDOR_ATMEL_MDB021D
:
12065 /* Detect size with tg3_nvram_get_size() */
12067 case FLASH_5717VENDOR_ATMEL_ADB021B
:
12068 case FLASH_5717VENDOR_ATMEL_ADB021D
:
12069 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
12072 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
12076 case FLASH_5717VENDOR_ST_M_M25PE10
:
12077 case FLASH_5717VENDOR_ST_A_M25PE10
:
12078 case FLASH_5717VENDOR_ST_M_M45PE10
:
12079 case FLASH_5717VENDOR_ST_A_M45PE10
:
12080 case FLASH_5717VENDOR_ST_M_M25PE20
:
12081 case FLASH_5717VENDOR_ST_A_M25PE20
:
12082 case FLASH_5717VENDOR_ST_M_M45PE20
:
12083 case FLASH_5717VENDOR_ST_A_M45PE20
:
12084 case FLASH_5717VENDOR_ST_25USPT
:
12085 case FLASH_5717VENDOR_ST_45USPT
:
12086 tp
->nvram_jedecnum
= JEDEC_ST
;
12087 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
12088 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
12090 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
12091 case FLASH_5717VENDOR_ST_M_M25PE20
:
12092 case FLASH_5717VENDOR_ST_M_M45PE20
:
12093 /* Detect size with tg3_nvram_get_size() */
12095 case FLASH_5717VENDOR_ST_A_M25PE20
:
12096 case FLASH_5717VENDOR_ST_A_M45PE20
:
12097 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
12100 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
12105 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM
;
12109 tg3_nvram_get_pagesize(tp
, nvcfg1
);
12110 if (tp
->nvram_pagesize
!= 264 && tp
->nvram_pagesize
!= 528)
12111 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
12114 static void __devinit
tg3_get_5720_nvram_info(struct tg3
*tp
)
12116 u32 nvcfg1
, nvmpinstrp
;
12118 nvcfg1
= tr32(NVRAM_CFG1
);
12119 nvmpinstrp
= nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
;
12121 switch (nvmpinstrp
) {
12122 case FLASH_5720_EEPROM_HD
:
12123 case FLASH_5720_EEPROM_LD
:
12124 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
12125 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
12127 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
12128 tw32(NVRAM_CFG1
, nvcfg1
);
12129 if (nvmpinstrp
== FLASH_5720_EEPROM_HD
)
12130 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
12132 tp
->nvram_pagesize
= ATMEL_AT24C02_CHIP_SIZE
;
12134 case FLASH_5720VENDOR_M_ATMEL_DB011D
:
12135 case FLASH_5720VENDOR_A_ATMEL_DB011B
:
12136 case FLASH_5720VENDOR_A_ATMEL_DB011D
:
12137 case FLASH_5720VENDOR_M_ATMEL_DB021D
:
12138 case FLASH_5720VENDOR_A_ATMEL_DB021B
:
12139 case FLASH_5720VENDOR_A_ATMEL_DB021D
:
12140 case FLASH_5720VENDOR_M_ATMEL_DB041D
:
12141 case FLASH_5720VENDOR_A_ATMEL_DB041B
:
12142 case FLASH_5720VENDOR_A_ATMEL_DB041D
:
12143 case FLASH_5720VENDOR_M_ATMEL_DB081D
:
12144 case FLASH_5720VENDOR_A_ATMEL_DB081D
:
12145 case FLASH_5720VENDOR_ATMEL_45USPT
:
12146 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
12147 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
12148 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
12150 switch (nvmpinstrp
) {
12151 case FLASH_5720VENDOR_M_ATMEL_DB021D
:
12152 case FLASH_5720VENDOR_A_ATMEL_DB021B
:
12153 case FLASH_5720VENDOR_A_ATMEL_DB021D
:
12154 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
12156 case FLASH_5720VENDOR_M_ATMEL_DB041D
:
12157 case FLASH_5720VENDOR_A_ATMEL_DB041B
:
12158 case FLASH_5720VENDOR_A_ATMEL_DB041D
:
12159 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
12161 case FLASH_5720VENDOR_M_ATMEL_DB081D
:
12162 case FLASH_5720VENDOR_A_ATMEL_DB081D
:
12163 tp
->nvram_size
= TG3_NVRAM_SIZE_1MB
;
12166 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
12170 case FLASH_5720VENDOR_M_ST_M25PE10
:
12171 case FLASH_5720VENDOR_M_ST_M45PE10
:
12172 case FLASH_5720VENDOR_A_ST_M25PE10
:
12173 case FLASH_5720VENDOR_A_ST_M45PE10
:
12174 case FLASH_5720VENDOR_M_ST_M25PE20
:
12175 case FLASH_5720VENDOR_M_ST_M45PE20
:
12176 case FLASH_5720VENDOR_A_ST_M25PE20
:
12177 case FLASH_5720VENDOR_A_ST_M45PE20
:
12178 case FLASH_5720VENDOR_M_ST_M25PE40
:
12179 case FLASH_5720VENDOR_M_ST_M45PE40
:
12180 case FLASH_5720VENDOR_A_ST_M25PE40
:
12181 case FLASH_5720VENDOR_A_ST_M45PE40
:
12182 case FLASH_5720VENDOR_M_ST_M25PE80
:
12183 case FLASH_5720VENDOR_M_ST_M45PE80
:
12184 case FLASH_5720VENDOR_A_ST_M25PE80
:
12185 case FLASH_5720VENDOR_A_ST_M45PE80
:
12186 case FLASH_5720VENDOR_ST_25USPT
:
12187 case FLASH_5720VENDOR_ST_45USPT
:
12188 tp
->nvram_jedecnum
= JEDEC_ST
;
12189 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
12190 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
12192 switch (nvmpinstrp
) {
12193 case FLASH_5720VENDOR_M_ST_M25PE20
:
12194 case FLASH_5720VENDOR_M_ST_M45PE20
:
12195 case FLASH_5720VENDOR_A_ST_M25PE20
:
12196 case FLASH_5720VENDOR_A_ST_M45PE20
:
12197 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
12199 case FLASH_5720VENDOR_M_ST_M25PE40
:
12200 case FLASH_5720VENDOR_M_ST_M45PE40
:
12201 case FLASH_5720VENDOR_A_ST_M25PE40
:
12202 case FLASH_5720VENDOR_A_ST_M45PE40
:
12203 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
12205 case FLASH_5720VENDOR_M_ST_M25PE80
:
12206 case FLASH_5720VENDOR_M_ST_M45PE80
:
12207 case FLASH_5720VENDOR_A_ST_M25PE80
:
12208 case FLASH_5720VENDOR_A_ST_M45PE80
:
12209 tp
->nvram_size
= TG3_NVRAM_SIZE_1MB
;
12212 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
12217 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM
;
12221 tg3_nvram_get_pagesize(tp
, nvcfg1
);
12222 if (tp
->nvram_pagesize
!= 264 && tp
->nvram_pagesize
!= 528)
12223 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
12226 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
12227 static void __devinit
tg3_nvram_init(struct tg3
*tp
)
12229 tw32_f(GRC_EEPROM_ADDR
,
12230 (EEPROM_ADDR_FSM_RESET
|
12231 (EEPROM_DEFAULT_CLOCK_PERIOD
<<
12232 EEPROM_ADDR_CLKPERD_SHIFT
)));
12236 /* Enable seeprom accesses. */
12237 tw32_f(GRC_LOCAL_CTRL
,
12238 tr32(GRC_LOCAL_CTRL
) | GRC_LCLCTRL_AUTO_SEEPROM
);
12241 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
12242 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
) {
12243 tp
->tg3_flags
|= TG3_FLAG_NVRAM
;
12245 if (tg3_nvram_lock(tp
)) {
12246 netdev_warn(tp
->dev
,
12247 "Cannot get nvram lock, %s failed\n",
12251 tg3_enable_nvram_access(tp
);
12253 tp
->nvram_size
= 0;
12255 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
)
12256 tg3_get_5752_nvram_info(tp
);
12257 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
)
12258 tg3_get_5755_nvram_info(tp
);
12259 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5787
||
12260 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
12261 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
12262 tg3_get_5787_nvram_info(tp
);
12263 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
)
12264 tg3_get_5761_nvram_info(tp
);
12265 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
12266 tg3_get_5906_nvram_info(tp
);
12267 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
||
12268 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
12269 tg3_get_57780_nvram_info(tp
);
12270 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
12271 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
)
12272 tg3_get_5717_nvram_info(tp
);
12273 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5720
)
12274 tg3_get_5720_nvram_info(tp
);
12276 tg3_get_nvram_info(tp
);
12278 if (tp
->nvram_size
== 0)
12279 tg3_get_nvram_size(tp
);
12281 tg3_disable_nvram_access(tp
);
12282 tg3_nvram_unlock(tp
);
12285 tp
->tg3_flags
&= ~(TG3_FLAG_NVRAM
| TG3_FLAG_NVRAM_BUFFERED
);
12287 tg3_get_eeprom_size(tp
);
12291 static int tg3_nvram_write_block_using_eeprom(struct tg3
*tp
,
12292 u32 offset
, u32 len
, u8
*buf
)
12297 for (i
= 0; i
< len
; i
+= 4) {
12303 memcpy(&data
, buf
+ i
, 4);
12306 * The SEEPROM interface expects the data to always be opposite
12307 * the native endian format. We accomplish this by reversing
12308 * all the operations that would have been performed on the
12309 * data from a call to tg3_nvram_read_be32().
12311 tw32(GRC_EEPROM_DATA
, swab32(be32_to_cpu(data
)));
12313 val
= tr32(GRC_EEPROM_ADDR
);
12314 tw32(GRC_EEPROM_ADDR
, val
| EEPROM_ADDR_COMPLETE
);
12316 val
&= ~(EEPROM_ADDR_ADDR_MASK
| EEPROM_ADDR_DEVID_MASK
|
12318 tw32(GRC_EEPROM_ADDR
, val
|
12319 (0 << EEPROM_ADDR_DEVID_SHIFT
) |
12320 (addr
& EEPROM_ADDR_ADDR_MASK
) |
12321 EEPROM_ADDR_START
|
12322 EEPROM_ADDR_WRITE
);
12324 for (j
= 0; j
< 1000; j
++) {
12325 val
= tr32(GRC_EEPROM_ADDR
);
12327 if (val
& EEPROM_ADDR_COMPLETE
)
12331 if (!(val
& EEPROM_ADDR_COMPLETE
)) {
12340 /* offset and length are dword aligned */
12341 static int tg3_nvram_write_block_unbuffered(struct tg3
*tp
, u32 offset
, u32 len
,
12345 u32 pagesize
= tp
->nvram_pagesize
;
12346 u32 pagemask
= pagesize
- 1;
12350 tmp
= kmalloc(pagesize
, GFP_KERNEL
);
12356 u32 phy_addr
, page_off
, size
;
12358 phy_addr
= offset
& ~pagemask
;
12360 for (j
= 0; j
< pagesize
; j
+= 4) {
12361 ret
= tg3_nvram_read_be32(tp
, phy_addr
+ j
,
12362 (__be32
*) (tmp
+ j
));
12369 page_off
= offset
& pagemask
;
12376 memcpy(tmp
+ page_off
, buf
, size
);
12378 offset
= offset
+ (pagesize
- page_off
);
12380 tg3_enable_nvram_access(tp
);
12383 * Before we can erase the flash page, we need
12384 * to issue a special "write enable" command.
12386 nvram_cmd
= NVRAM_CMD_WREN
| NVRAM_CMD_GO
| NVRAM_CMD_DONE
;
12388 if (tg3_nvram_exec_cmd(tp
, nvram_cmd
))
12391 /* Erase the target page */
12392 tw32(NVRAM_ADDR
, phy_addr
);
12394 nvram_cmd
= NVRAM_CMD_GO
| NVRAM_CMD_DONE
| NVRAM_CMD_WR
|
12395 NVRAM_CMD_FIRST
| NVRAM_CMD_LAST
| NVRAM_CMD_ERASE
;
12397 if (tg3_nvram_exec_cmd(tp
, nvram_cmd
))
12400 /* Issue another write enable to start the write. */
12401 nvram_cmd
= NVRAM_CMD_WREN
| NVRAM_CMD_GO
| NVRAM_CMD_DONE
;
12403 if (tg3_nvram_exec_cmd(tp
, nvram_cmd
))
12406 for (j
= 0; j
< pagesize
; j
+= 4) {
12409 data
= *((__be32
*) (tmp
+ j
));
12411 tw32(NVRAM_WRDATA
, be32_to_cpu(data
));
12413 tw32(NVRAM_ADDR
, phy_addr
+ j
);
12415 nvram_cmd
= NVRAM_CMD_GO
| NVRAM_CMD_DONE
|
12419 nvram_cmd
|= NVRAM_CMD_FIRST
;
12420 else if (j
== (pagesize
- 4))
12421 nvram_cmd
|= NVRAM_CMD_LAST
;
12423 if ((ret
= tg3_nvram_exec_cmd(tp
, nvram_cmd
)))
12430 nvram_cmd
= NVRAM_CMD_WRDI
| NVRAM_CMD_GO
| NVRAM_CMD_DONE
;
12431 tg3_nvram_exec_cmd(tp
, nvram_cmd
);
12438 /* offset and length are dword aligned */
12439 static int tg3_nvram_write_block_buffered(struct tg3
*tp
, u32 offset
, u32 len
,
12444 for (i
= 0; i
< len
; i
+= 4, offset
+= 4) {
12445 u32 page_off
, phy_addr
, nvram_cmd
;
12448 memcpy(&data
, buf
+ i
, 4);
12449 tw32(NVRAM_WRDATA
, be32_to_cpu(data
));
12451 page_off
= offset
% tp
->nvram_pagesize
;
12453 phy_addr
= tg3_nvram_phys_addr(tp
, offset
);
12455 tw32(NVRAM_ADDR
, phy_addr
);
12457 nvram_cmd
= NVRAM_CMD_GO
| NVRAM_CMD_DONE
| NVRAM_CMD_WR
;
12459 if (page_off
== 0 || i
== 0)
12460 nvram_cmd
|= NVRAM_CMD_FIRST
;
12461 if (page_off
== (tp
->nvram_pagesize
- 4))
12462 nvram_cmd
|= NVRAM_CMD_LAST
;
12464 if (i
== (len
- 4))
12465 nvram_cmd
|= NVRAM_CMD_LAST
;
12467 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5752
&&
12468 !(tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) &&
12469 (tp
->nvram_jedecnum
== JEDEC_ST
) &&
12470 (nvram_cmd
& NVRAM_CMD_FIRST
)) {
12472 if ((ret
= tg3_nvram_exec_cmd(tp
,
12473 NVRAM_CMD_WREN
| NVRAM_CMD_GO
|
12478 if (!(tp
->tg3_flags2
& TG3_FLG2_FLASH
)) {
12479 /* We always do complete word writes to eeprom. */
12480 nvram_cmd
|= (NVRAM_CMD_FIRST
| NVRAM_CMD_LAST
);
12483 if ((ret
= tg3_nvram_exec_cmd(tp
, nvram_cmd
)))
12489 /* offset and length are dword aligned */
12490 static int tg3_nvram_write_block(struct tg3
*tp
, u32 offset
, u32 len
, u8
*buf
)
12494 if (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
) {
12495 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
&
12496 ~GRC_LCLCTRL_GPIO_OUTPUT1
);
12500 if (!(tp
->tg3_flags
& TG3_FLAG_NVRAM
)) {
12501 ret
= tg3_nvram_write_block_using_eeprom(tp
, offset
, len
, buf
);
12505 ret
= tg3_nvram_lock(tp
);
12509 tg3_enable_nvram_access(tp
);
12510 if ((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
12511 !(tp
->tg3_flags3
& TG3_FLG3_PROTECTED_NVRAM
))
12512 tw32(NVRAM_WRITE1
, 0x406);
12514 grc_mode
= tr32(GRC_MODE
);
12515 tw32(GRC_MODE
, grc_mode
| GRC_MODE_NVRAM_WR_ENABLE
);
12517 if ((tp
->tg3_flags
& TG3_FLAG_NVRAM_BUFFERED
) ||
12518 !(tp
->tg3_flags2
& TG3_FLG2_FLASH
)) {
12520 ret
= tg3_nvram_write_block_buffered(tp
, offset
, len
,
12523 ret
= tg3_nvram_write_block_unbuffered(tp
, offset
, len
,
12527 grc_mode
= tr32(GRC_MODE
);
12528 tw32(GRC_MODE
, grc_mode
& ~GRC_MODE_NVRAM_WR_ENABLE
);
12530 tg3_disable_nvram_access(tp
);
12531 tg3_nvram_unlock(tp
);
12534 if (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
) {
12535 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
);
12542 struct subsys_tbl_ent
{
12543 u16 subsys_vendor
, subsys_devid
;
12547 static struct subsys_tbl_ent subsys_id_to_phy_id
[] __devinitdata
= {
12548 /* Broadcom boards. */
12549 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
12550 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6
, TG3_PHY_ID_BCM5401
},
12551 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
12552 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5
, TG3_PHY_ID_BCM5701
},
12553 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
12554 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6
, TG3_PHY_ID_BCM8002
},
12555 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
12556 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9
, 0 },
12557 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
12558 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1
, TG3_PHY_ID_BCM5701
},
12559 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
12560 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8
, TG3_PHY_ID_BCM5701
},
12561 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
12562 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7
, 0 },
12563 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
12564 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10
, TG3_PHY_ID_BCM5701
},
12565 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
12566 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12
, TG3_PHY_ID_BCM5701
},
12567 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
12568 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1
, TG3_PHY_ID_BCM5703
},
12569 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
12570 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2
, TG3_PHY_ID_BCM5703
},
12573 { TG3PCI_SUBVENDOR_ID_3COM
,
12574 TG3PCI_SUBDEVICE_ID_3COM_3C996T
, TG3_PHY_ID_BCM5401
},
12575 { TG3PCI_SUBVENDOR_ID_3COM
,
12576 TG3PCI_SUBDEVICE_ID_3COM_3C996BT
, TG3_PHY_ID_BCM5701
},
12577 { TG3PCI_SUBVENDOR_ID_3COM
,
12578 TG3PCI_SUBDEVICE_ID_3COM_3C996SX
, 0 },
12579 { TG3PCI_SUBVENDOR_ID_3COM
,
12580 TG3PCI_SUBDEVICE_ID_3COM_3C1000T
, TG3_PHY_ID_BCM5701
},
12581 { TG3PCI_SUBVENDOR_ID_3COM
,
12582 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01
, TG3_PHY_ID_BCM5701
},
12585 { TG3PCI_SUBVENDOR_ID_DELL
,
12586 TG3PCI_SUBDEVICE_ID_DELL_VIPER
, TG3_PHY_ID_BCM5401
},
12587 { TG3PCI_SUBVENDOR_ID_DELL
,
12588 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR
, TG3_PHY_ID_BCM5401
},
12589 { TG3PCI_SUBVENDOR_ID_DELL
,
12590 TG3PCI_SUBDEVICE_ID_DELL_MERLOT
, TG3_PHY_ID_BCM5411
},
12591 { TG3PCI_SUBVENDOR_ID_DELL
,
12592 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT
, TG3_PHY_ID_BCM5411
},
12594 /* Compaq boards. */
12595 { TG3PCI_SUBVENDOR_ID_COMPAQ
,
12596 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE
, TG3_PHY_ID_BCM5701
},
12597 { TG3PCI_SUBVENDOR_ID_COMPAQ
,
12598 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2
, TG3_PHY_ID_BCM5701
},
12599 { TG3PCI_SUBVENDOR_ID_COMPAQ
,
12600 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING
, 0 },
12601 { TG3PCI_SUBVENDOR_ID_COMPAQ
,
12602 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780
, TG3_PHY_ID_BCM5701
},
12603 { TG3PCI_SUBVENDOR_ID_COMPAQ
,
12604 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2
, TG3_PHY_ID_BCM5701
},
12607 { TG3PCI_SUBVENDOR_ID_IBM
,
12608 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2
, 0 }
12611 static struct subsys_tbl_ent
* __devinit
tg3_lookup_by_subsys(struct tg3
*tp
)
12615 for (i
= 0; i
< ARRAY_SIZE(subsys_id_to_phy_id
); i
++) {
12616 if ((subsys_id_to_phy_id
[i
].subsys_vendor
==
12617 tp
->pdev
->subsystem_vendor
) &&
12618 (subsys_id_to_phy_id
[i
].subsys_devid
==
12619 tp
->pdev
->subsystem_device
))
12620 return &subsys_id_to_phy_id
[i
];
12625 static void __devinit
tg3_get_eeprom_hw_cfg(struct tg3
*tp
)
12630 /* On some early chips the SRAM cannot be accessed in D3hot state,
12631 * so need make sure we're in D0.
12633 pci_read_config_word(tp
->pdev
, tp
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
12634 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
12635 pci_write_config_word(tp
->pdev
, tp
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
12638 /* Make sure register accesses (indirect or otherwise)
12639 * will function correctly.
12641 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
12642 tp
->misc_host_ctrl
);
12644 /* The memory arbiter has to be enabled in order for SRAM accesses
12645 * to succeed. Normally on powerup the tg3 chip firmware will make
12646 * sure it is enabled, but other entities such as system netboot
12647 * code might disable it.
12649 val
= tr32(MEMARB_MODE
);
12650 tw32(MEMARB_MODE
, val
| MEMARB_MODE_ENABLE
);
12652 tp
->phy_id
= TG3_PHY_ID_INVALID
;
12653 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
12655 /* Assume an onboard device and WOL capable by default. */
12656 tp
->tg3_flags
|= TG3_FLAG_EEPROM_WRITE_PROT
| TG3_FLAG_WOL_CAP
;
12658 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
12659 if (!(tr32(PCIE_TRANSACTION_CFG
) & PCIE_TRANS_CFG_LOM
)) {
12660 tp
->tg3_flags
&= ~TG3_FLAG_EEPROM_WRITE_PROT
;
12661 tp
->tg3_flags2
|= TG3_FLG2_IS_NIC
;
12663 val
= tr32(VCPU_CFGSHDW
);
12664 if (val
& VCPU_CFGSHDW_ASPM_DBNC
)
12665 tp
->tg3_flags
|= TG3_FLAG_ASPM_WORKAROUND
;
12666 if ((val
& VCPU_CFGSHDW_WOL_ENABLE
) &&
12667 (val
& VCPU_CFGSHDW_WOL_MAGPKT
))
12668 tp
->tg3_flags
|= TG3_FLAG_WOL_ENABLE
;
12672 tg3_read_mem(tp
, NIC_SRAM_DATA_SIG
, &val
);
12673 if (val
== NIC_SRAM_DATA_SIG_MAGIC
) {
12674 u32 nic_cfg
, led_cfg
;
12675 u32 nic_phy_id
, ver
, cfg2
= 0, cfg4
= 0, eeprom_phy_id
;
12676 int eeprom_phy_serdes
= 0;
12678 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG
, &nic_cfg
);
12679 tp
->nic_sram_data_cfg
= nic_cfg
;
12681 tg3_read_mem(tp
, NIC_SRAM_DATA_VER
, &ver
);
12682 ver
>>= NIC_SRAM_DATA_VER_SHIFT
;
12683 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
) &&
12684 (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
) &&
12685 (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5703
) &&
12686 (ver
> 0) && (ver
< 0x100))
12687 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG_2
, &cfg2
);
12689 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
12690 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG_4
, &cfg4
);
12692 if ((nic_cfg
& NIC_SRAM_DATA_CFG_PHY_TYPE_MASK
) ==
12693 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER
)
12694 eeprom_phy_serdes
= 1;
12696 tg3_read_mem(tp
, NIC_SRAM_DATA_PHY_ID
, &nic_phy_id
);
12697 if (nic_phy_id
!= 0) {
12698 u32 id1
= nic_phy_id
& NIC_SRAM_DATA_PHY_ID1_MASK
;
12699 u32 id2
= nic_phy_id
& NIC_SRAM_DATA_PHY_ID2_MASK
;
12701 eeprom_phy_id
= (id1
>> 16) << 10;
12702 eeprom_phy_id
|= (id2
& 0xfc00) << 16;
12703 eeprom_phy_id
|= (id2
& 0x03ff) << 0;
12707 tp
->phy_id
= eeprom_phy_id
;
12708 if (eeprom_phy_serdes
) {
12709 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
12710 tp
->phy_flags
|= TG3_PHYFLG_PHY_SERDES
;
12712 tp
->phy_flags
|= TG3_PHYFLG_MII_SERDES
;
12715 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
12716 led_cfg
= cfg2
& (NIC_SRAM_DATA_CFG_LED_MODE_MASK
|
12717 SHASTA_EXT_LED_MODE_MASK
);
12719 led_cfg
= nic_cfg
& NIC_SRAM_DATA_CFG_LED_MODE_MASK
;
12723 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1
:
12724 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
12727 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2
:
12728 tp
->led_ctrl
= LED_CTRL_MODE_PHY_2
;
12731 case NIC_SRAM_DATA_CFG_LED_MODE_MAC
:
12732 tp
->led_ctrl
= LED_CTRL_MODE_MAC
;
12734 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12735 * read on some older 5700/5701 bootcode.
12737 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
12739 GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
12741 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
12745 case SHASTA_EXT_LED_SHARED
:
12746 tp
->led_ctrl
= LED_CTRL_MODE_SHARED
;
12747 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
&&
12748 tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A1
)
12749 tp
->led_ctrl
|= (LED_CTRL_MODE_PHY_1
|
12750 LED_CTRL_MODE_PHY_2
);
12753 case SHASTA_EXT_LED_MAC
:
12754 tp
->led_ctrl
= LED_CTRL_MODE_SHASTA_MAC
;
12757 case SHASTA_EXT_LED_COMBO
:
12758 tp
->led_ctrl
= LED_CTRL_MODE_COMBO
;
12759 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
)
12760 tp
->led_ctrl
|= (LED_CTRL_MODE_PHY_1
|
12761 LED_CTRL_MODE_PHY_2
);
12766 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
12767 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) &&
12768 tp
->pdev
->subsystem_vendor
== PCI_VENDOR_ID_DELL
)
12769 tp
->led_ctrl
= LED_CTRL_MODE_PHY_2
;
12771 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
)
12772 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
12774 if (nic_cfg
& NIC_SRAM_DATA_CFG_EEPROM_WP
) {
12775 tp
->tg3_flags
|= TG3_FLAG_EEPROM_WRITE_PROT
;
12776 if ((tp
->pdev
->subsystem_vendor
==
12777 PCI_VENDOR_ID_ARIMA
) &&
12778 (tp
->pdev
->subsystem_device
== 0x205a ||
12779 tp
->pdev
->subsystem_device
== 0x2063))
12780 tp
->tg3_flags
&= ~TG3_FLAG_EEPROM_WRITE_PROT
;
12782 tp
->tg3_flags
&= ~TG3_FLAG_EEPROM_WRITE_PROT
;
12783 tp
->tg3_flags2
|= TG3_FLG2_IS_NIC
;
12786 if (nic_cfg
& NIC_SRAM_DATA_CFG_ASF_ENABLE
) {
12787 tp
->tg3_flags
|= TG3_FLAG_ENABLE_ASF
;
12788 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
12789 tp
->tg3_flags2
|= TG3_FLG2_ASF_NEW_HANDSHAKE
;
12792 if ((nic_cfg
& NIC_SRAM_DATA_CFG_APE_ENABLE
) &&
12793 (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
))
12794 tp
->tg3_flags3
|= TG3_FLG3_ENABLE_APE
;
12796 if (tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
&&
12797 !(nic_cfg
& NIC_SRAM_DATA_CFG_FIBER_WOL
))
12798 tp
->tg3_flags
&= ~TG3_FLAG_WOL_CAP
;
12800 if ((tp
->tg3_flags
& TG3_FLAG_WOL_CAP
) &&
12801 (nic_cfg
& NIC_SRAM_DATA_CFG_WOL_ENABLE
))
12802 tp
->tg3_flags
|= TG3_FLAG_WOL_ENABLE
;
12804 if (cfg2
& (1 << 17))
12805 tp
->phy_flags
|= TG3_PHYFLG_CAPACITIVE_COUPLING
;
12807 /* serdes signal pre-emphasis in register 0x590 set by */
12808 /* bootcode if bit 18 is set */
12809 if (cfg2
& (1 << 18))
12810 tp
->phy_flags
|= TG3_PHYFLG_SERDES_PREEMPHASIS
;
12812 if (((tp
->tg3_flags3
& TG3_FLG3_57765_PLUS
) ||
12813 ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
12814 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
))) &&
12815 (cfg2
& NIC_SRAM_DATA_CFG_2_APD_EN
))
12816 tp
->phy_flags
|= TG3_PHYFLG_ENABLE_APD
;
12818 if ((tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) &&
12819 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5785
&&
12820 !(tp
->tg3_flags3
& TG3_FLG3_57765_PLUS
)) {
12823 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG_3
, &cfg3
);
12824 if (cfg3
& NIC_SRAM_ASPM_DEBOUNCE
)
12825 tp
->tg3_flags
|= TG3_FLAG_ASPM_WORKAROUND
;
12828 if (cfg4
& NIC_SRAM_RGMII_INBAND_DISABLE
)
12829 tp
->tg3_flags3
|= TG3_FLG3_RGMII_INBAND_DISABLE
;
12830 if (cfg4
& NIC_SRAM_RGMII_EXT_IBND_RX_EN
)
12831 tp
->tg3_flags3
|= TG3_FLG3_RGMII_EXT_IBND_RX_EN
;
12832 if (cfg4
& NIC_SRAM_RGMII_EXT_IBND_TX_EN
)
12833 tp
->tg3_flags3
|= TG3_FLG3_RGMII_EXT_IBND_TX_EN
;
12836 if (tp
->tg3_flags
& TG3_FLAG_WOL_CAP
)
12837 device_set_wakeup_enable(&tp
->pdev
->dev
,
12838 tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
);
12840 device_set_wakeup_capable(&tp
->pdev
->dev
, false);
12843 static int __devinit
tg3_issue_otp_command(struct tg3
*tp
, u32 cmd
)
12848 tw32(OTP_CTRL
, cmd
| OTP_CTRL_OTP_CMD_START
);
12849 tw32(OTP_CTRL
, cmd
);
12851 /* Wait for up to 1 ms for command to execute. */
12852 for (i
= 0; i
< 100; i
++) {
12853 val
= tr32(OTP_STATUS
);
12854 if (val
& OTP_STATUS_CMD_DONE
)
12859 return (val
& OTP_STATUS_CMD_DONE
) ? 0 : -EBUSY
;
12862 /* Read the gphy configuration from the OTP region of the chip. The gphy
12863 * configuration is a 32-bit value that straddles the alignment boundary.
12864 * We do two 32-bit reads and then shift and merge the results.
12866 static u32 __devinit
tg3_read_otp_phycfg(struct tg3
*tp
)
12868 u32 bhalf_otp
, thalf_otp
;
12870 tw32(OTP_MODE
, OTP_MODE_OTP_THRU_GRC
);
12872 if (tg3_issue_otp_command(tp
, OTP_CTRL_OTP_CMD_INIT
))
12875 tw32(OTP_ADDRESS
, OTP_ADDRESS_MAGIC1
);
12877 if (tg3_issue_otp_command(tp
, OTP_CTRL_OTP_CMD_READ
))
12880 thalf_otp
= tr32(OTP_READ_DATA
);
12882 tw32(OTP_ADDRESS
, OTP_ADDRESS_MAGIC2
);
12884 if (tg3_issue_otp_command(tp
, OTP_CTRL_OTP_CMD_READ
))
12887 bhalf_otp
= tr32(OTP_READ_DATA
);
12889 return ((thalf_otp
& 0x0000ffff) << 16) | (bhalf_otp
>> 16);
12892 static void __devinit
tg3_phy_init_link_config(struct tg3
*tp
)
12894 u32 adv
= ADVERTISED_Autoneg
|
12897 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
))
12898 adv
|= ADVERTISED_1000baseT_Half
|
12899 ADVERTISED_1000baseT_Full
;
12901 if (!(tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
))
12902 adv
|= ADVERTISED_100baseT_Half
|
12903 ADVERTISED_100baseT_Full
|
12904 ADVERTISED_10baseT_Half
|
12905 ADVERTISED_10baseT_Full
|
12908 adv
|= ADVERTISED_FIBRE
;
12910 tp
->link_config
.advertising
= adv
;
12911 tp
->link_config
.speed
= SPEED_INVALID
;
12912 tp
->link_config
.duplex
= DUPLEX_INVALID
;
12913 tp
->link_config
.autoneg
= AUTONEG_ENABLE
;
12914 tp
->link_config
.active_speed
= SPEED_INVALID
;
12915 tp
->link_config
.active_duplex
= DUPLEX_INVALID
;
12916 tp
->link_config
.orig_speed
= SPEED_INVALID
;
12917 tp
->link_config
.orig_duplex
= DUPLEX_INVALID
;
12918 tp
->link_config
.orig_autoneg
= AUTONEG_INVALID
;
12921 static int __devinit
tg3_phy_probe(struct tg3
*tp
)
12923 u32 hw_phy_id_1
, hw_phy_id_2
;
12924 u32 hw_phy_id
, hw_phy_id_masked
;
12927 /* flow control autonegotiation is default behavior */
12928 tp
->tg3_flags
|= TG3_FLAG_PAUSE_AUTONEG
;
12929 tp
->link_config
.flowctrl
= FLOW_CTRL_TX
| FLOW_CTRL_RX
;
12931 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
)
12932 return tg3_phy_init(tp
);
12934 /* Reading the PHY ID register can conflict with ASF
12935 * firmware access to the PHY hardware.
12938 if ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) ||
12939 (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)) {
12940 hw_phy_id
= hw_phy_id_masked
= TG3_PHY_ID_INVALID
;
12942 /* Now read the physical PHY_ID from the chip and verify
12943 * that it is sane. If it doesn't look good, we fall back
12944 * to either the hard-coded table based PHY_ID and failing
12945 * that the value found in the eeprom area.
12947 err
|= tg3_readphy(tp
, MII_PHYSID1
, &hw_phy_id_1
);
12948 err
|= tg3_readphy(tp
, MII_PHYSID2
, &hw_phy_id_2
);
12950 hw_phy_id
= (hw_phy_id_1
& 0xffff) << 10;
12951 hw_phy_id
|= (hw_phy_id_2
& 0xfc00) << 16;
12952 hw_phy_id
|= (hw_phy_id_2
& 0x03ff) << 0;
12954 hw_phy_id_masked
= hw_phy_id
& TG3_PHY_ID_MASK
;
12957 if (!err
&& TG3_KNOWN_PHY_ID(hw_phy_id_masked
)) {
12958 tp
->phy_id
= hw_phy_id
;
12959 if (hw_phy_id_masked
== TG3_PHY_ID_BCM8002
)
12960 tp
->phy_flags
|= TG3_PHYFLG_PHY_SERDES
;
12962 tp
->phy_flags
&= ~TG3_PHYFLG_PHY_SERDES
;
12964 if (tp
->phy_id
!= TG3_PHY_ID_INVALID
) {
12965 /* Do nothing, phy ID already set up in
12966 * tg3_get_eeprom_hw_cfg().
12969 struct subsys_tbl_ent
*p
;
12971 /* No eeprom signature? Try the hardcoded
12972 * subsys device table.
12974 p
= tg3_lookup_by_subsys(tp
);
12978 tp
->phy_id
= p
->phy_id
;
12980 tp
->phy_id
== TG3_PHY_ID_BCM8002
)
12981 tp
->phy_flags
|= TG3_PHYFLG_PHY_SERDES
;
12985 if (!(tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
) &&
12986 ((tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5718
&&
12987 tp
->pci_chip_rev_id
!= CHIPREV_ID_5717_A0
) ||
12988 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
&&
12989 tp
->pci_chip_rev_id
!= CHIPREV_ID_57765_A0
)))
12990 tp
->phy_flags
|= TG3_PHYFLG_EEE_CAP
;
12992 tg3_phy_init_link_config(tp
);
12994 if (!(tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
) &&
12995 !(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) &&
12996 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)) {
12997 u32 bmsr
, adv_reg
, tg3_ctrl
, mask
;
12999 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
13000 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
13001 (bmsr
& BMSR_LSTATUS
))
13002 goto skip_phy_reset
;
13004 err
= tg3_phy_reset(tp
);
13008 adv_reg
= (ADVERTISE_10HALF
| ADVERTISE_10FULL
|
13009 ADVERTISE_100HALF
| ADVERTISE_100FULL
|
13010 ADVERTISE_CSMA
| ADVERTISE_PAUSE_CAP
);
13012 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
)) {
13013 tg3_ctrl
= (MII_TG3_CTRL_ADV_1000_HALF
|
13014 MII_TG3_CTRL_ADV_1000_FULL
);
13015 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
13016 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
)
13017 tg3_ctrl
|= (MII_TG3_CTRL_AS_MASTER
|
13018 MII_TG3_CTRL_ENABLE_AS_MASTER
);
13021 mask
= (ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
13022 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
|
13023 ADVERTISED_1000baseT_Half
| ADVERTISED_1000baseT_Full
);
13024 if (!tg3_copper_is_advertising_all(tp
, mask
)) {
13025 tg3_writephy(tp
, MII_ADVERTISE
, adv_reg
);
13027 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
))
13028 tg3_writephy(tp
, MII_TG3_CTRL
, tg3_ctrl
);
13030 tg3_writephy(tp
, MII_BMCR
,
13031 BMCR_ANENABLE
| BMCR_ANRESTART
);
13033 tg3_phy_set_wirespeed(tp
);
13035 tg3_writephy(tp
, MII_ADVERTISE
, adv_reg
);
13036 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
))
13037 tg3_writephy(tp
, MII_TG3_CTRL
, tg3_ctrl
);
13041 if ((tp
->phy_id
& TG3_PHY_ID_MASK
) == TG3_PHY_ID_BCM5401
) {
13042 err
= tg3_init_5401phy_dsp(tp
);
13046 err
= tg3_init_5401phy_dsp(tp
);
13052 static void __devinit
tg3_read_vpd(struct tg3
*tp
)
13055 unsigned int block_end
, rosize
, len
;
13058 vpd_data
= (u8
*)tg3_vpd_readblock(tp
);
13062 i
= pci_vpd_find_tag(vpd_data
, 0, TG3_NVM_VPD_LEN
,
13063 PCI_VPD_LRDT_RO_DATA
);
13065 goto out_not_found
;
13067 rosize
= pci_vpd_lrdt_size(&vpd_data
[i
]);
13068 block_end
= i
+ PCI_VPD_LRDT_TAG_SIZE
+ rosize
;
13069 i
+= PCI_VPD_LRDT_TAG_SIZE
;
13071 if (block_end
> TG3_NVM_VPD_LEN
)
13072 goto out_not_found
;
13074 j
= pci_vpd_find_info_keyword(vpd_data
, i
, rosize
,
13075 PCI_VPD_RO_KEYWORD_MFR_ID
);
13077 len
= pci_vpd_info_field_size(&vpd_data
[j
]);
13079 j
+= PCI_VPD_INFO_FLD_HDR_SIZE
;
13080 if (j
+ len
> block_end
|| len
!= 4 ||
13081 memcmp(&vpd_data
[j
], "1028", 4))
13084 j
= pci_vpd_find_info_keyword(vpd_data
, i
, rosize
,
13085 PCI_VPD_RO_KEYWORD_VENDOR0
);
13089 len
= pci_vpd_info_field_size(&vpd_data
[j
]);
13091 j
+= PCI_VPD_INFO_FLD_HDR_SIZE
;
13092 if (j
+ len
> block_end
)
13095 memcpy(tp
->fw_ver
, &vpd_data
[j
], len
);
13096 strncat(tp
->fw_ver
, " bc ", TG3_NVM_VPD_LEN
- len
- 1);
13100 i
= pci_vpd_find_info_keyword(vpd_data
, i
, rosize
,
13101 PCI_VPD_RO_KEYWORD_PARTNO
);
13103 goto out_not_found
;
13105 len
= pci_vpd_info_field_size(&vpd_data
[i
]);
13107 i
+= PCI_VPD_INFO_FLD_HDR_SIZE
;
13108 if (len
> TG3_BPN_SIZE
||
13109 (len
+ i
) > TG3_NVM_VPD_LEN
)
13110 goto out_not_found
;
13112 memcpy(tp
->board_part_number
, &vpd_data
[i
], len
);
13116 if (tp
->board_part_number
[0])
13120 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
) {
13121 if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5717
)
13122 strcpy(tp
->board_part_number
, "BCM5717");
13123 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5718
)
13124 strcpy(tp
->board_part_number
, "BCM5718");
13127 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
) {
13128 if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57780
)
13129 strcpy(tp
->board_part_number
, "BCM57780");
13130 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57760
)
13131 strcpy(tp
->board_part_number
, "BCM57760");
13132 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57790
)
13133 strcpy(tp
->board_part_number
, "BCM57790");
13134 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57788
)
13135 strcpy(tp
->board_part_number
, "BCM57788");
13138 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
) {
13139 if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57761
)
13140 strcpy(tp
->board_part_number
, "BCM57761");
13141 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57765
)
13142 strcpy(tp
->board_part_number
, "BCM57765");
13143 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57781
)
13144 strcpy(tp
->board_part_number
, "BCM57781");
13145 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57785
)
13146 strcpy(tp
->board_part_number
, "BCM57785");
13147 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57791
)
13148 strcpy(tp
->board_part_number
, "BCM57791");
13149 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57795
)
13150 strcpy(tp
->board_part_number
, "BCM57795");
13153 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
13154 strcpy(tp
->board_part_number
, "BCM95906");
13157 strcpy(tp
->board_part_number
, "none");
13161 static int __devinit
tg3_fw_img_is_valid(struct tg3
*tp
, u32 offset
)
13165 if (tg3_nvram_read(tp
, offset
, &val
) ||
13166 (val
& 0xfc000000) != 0x0c000000 ||
13167 tg3_nvram_read(tp
, offset
+ 4, &val
) ||
13174 static void __devinit
tg3_read_bc_ver(struct tg3
*tp
)
13176 u32 val
, offset
, start
, ver_offset
;
13178 bool newver
= false;
13180 if (tg3_nvram_read(tp
, 0xc, &offset
) ||
13181 tg3_nvram_read(tp
, 0x4, &start
))
13184 offset
= tg3_nvram_logical_addr(tp
, offset
);
13186 if (tg3_nvram_read(tp
, offset
, &val
))
13189 if ((val
& 0xfc000000) == 0x0c000000) {
13190 if (tg3_nvram_read(tp
, offset
+ 4, &val
))
13197 dst_off
= strlen(tp
->fw_ver
);
13200 if (TG3_VER_SIZE
- dst_off
< 16 ||
13201 tg3_nvram_read(tp
, offset
+ 8, &ver_offset
))
13204 offset
= offset
+ ver_offset
- start
;
13205 for (i
= 0; i
< 16; i
+= 4) {
13207 if (tg3_nvram_read_be32(tp
, offset
+ i
, &v
))
13210 memcpy(tp
->fw_ver
+ dst_off
+ i
, &v
, sizeof(v
));
13215 if (tg3_nvram_read(tp
, TG3_NVM_PTREV_BCVER
, &ver_offset
))
13218 major
= (ver_offset
& TG3_NVM_BCVER_MAJMSK
) >>
13219 TG3_NVM_BCVER_MAJSFT
;
13220 minor
= ver_offset
& TG3_NVM_BCVER_MINMSK
;
13221 snprintf(&tp
->fw_ver
[dst_off
], TG3_VER_SIZE
- dst_off
,
13222 "v%d.%02d", major
, minor
);
13226 static void __devinit
tg3_read_hwsb_ver(struct tg3
*tp
)
13228 u32 val
, major
, minor
;
13230 /* Use native endian representation */
13231 if (tg3_nvram_read(tp
, TG3_NVM_HWSB_CFG1
, &val
))
13234 major
= (val
& TG3_NVM_HWSB_CFG1_MAJMSK
) >>
13235 TG3_NVM_HWSB_CFG1_MAJSFT
;
13236 minor
= (val
& TG3_NVM_HWSB_CFG1_MINMSK
) >>
13237 TG3_NVM_HWSB_CFG1_MINSFT
;
13239 snprintf(&tp
->fw_ver
[0], 32, "sb v%d.%02d", major
, minor
);
13242 static void __devinit
tg3_read_sb_ver(struct tg3
*tp
, u32 val
)
13244 u32 offset
, major
, minor
, build
;
13246 strncat(tp
->fw_ver
, "sb", TG3_VER_SIZE
- strlen(tp
->fw_ver
) - 1);
13248 if ((val
& TG3_EEPROM_SB_FORMAT_MASK
) != TG3_EEPROM_SB_FORMAT_1
)
13251 switch (val
& TG3_EEPROM_SB_REVISION_MASK
) {
13252 case TG3_EEPROM_SB_REVISION_0
:
13253 offset
= TG3_EEPROM_SB_F1R0_EDH_OFF
;
13255 case TG3_EEPROM_SB_REVISION_2
:
13256 offset
= TG3_EEPROM_SB_F1R2_EDH_OFF
;
13258 case TG3_EEPROM_SB_REVISION_3
:
13259 offset
= TG3_EEPROM_SB_F1R3_EDH_OFF
;
13261 case TG3_EEPROM_SB_REVISION_4
:
13262 offset
= TG3_EEPROM_SB_F1R4_EDH_OFF
;
13264 case TG3_EEPROM_SB_REVISION_5
:
13265 offset
= TG3_EEPROM_SB_F1R5_EDH_OFF
;
13267 case TG3_EEPROM_SB_REVISION_6
:
13268 offset
= TG3_EEPROM_SB_F1R6_EDH_OFF
;
13274 if (tg3_nvram_read(tp
, offset
, &val
))
13277 build
= (val
& TG3_EEPROM_SB_EDH_BLD_MASK
) >>
13278 TG3_EEPROM_SB_EDH_BLD_SHFT
;
13279 major
= (val
& TG3_EEPROM_SB_EDH_MAJ_MASK
) >>
13280 TG3_EEPROM_SB_EDH_MAJ_SHFT
;
13281 minor
= val
& TG3_EEPROM_SB_EDH_MIN_MASK
;
13283 if (minor
> 99 || build
> 26)
13286 offset
= strlen(tp
->fw_ver
);
13287 snprintf(&tp
->fw_ver
[offset
], TG3_VER_SIZE
- offset
,
13288 " v%d.%02d", major
, minor
);
13291 offset
= strlen(tp
->fw_ver
);
13292 if (offset
< TG3_VER_SIZE
- 1)
13293 tp
->fw_ver
[offset
] = 'a' + build
- 1;
13297 static void __devinit
tg3_read_mgmtfw_ver(struct tg3
*tp
)
13299 u32 val
, offset
, start
;
13302 for (offset
= TG3_NVM_DIR_START
;
13303 offset
< TG3_NVM_DIR_END
;
13304 offset
+= TG3_NVM_DIRENT_SIZE
) {
13305 if (tg3_nvram_read(tp
, offset
, &val
))
13308 if ((val
>> TG3_NVM_DIRTYPE_SHIFT
) == TG3_NVM_DIRTYPE_ASFINI
)
13312 if (offset
== TG3_NVM_DIR_END
)
13315 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
13316 start
= 0x08000000;
13317 else if (tg3_nvram_read(tp
, offset
- 4, &start
))
13320 if (tg3_nvram_read(tp
, offset
+ 4, &offset
) ||
13321 !tg3_fw_img_is_valid(tp
, offset
) ||
13322 tg3_nvram_read(tp
, offset
+ 8, &val
))
13325 offset
+= val
- start
;
13327 vlen
= strlen(tp
->fw_ver
);
13329 tp
->fw_ver
[vlen
++] = ',';
13330 tp
->fw_ver
[vlen
++] = ' ';
13332 for (i
= 0; i
< 4; i
++) {
13334 if (tg3_nvram_read_be32(tp
, offset
, &v
))
13337 offset
+= sizeof(v
);
13339 if (vlen
> TG3_VER_SIZE
- sizeof(v
)) {
13340 memcpy(&tp
->fw_ver
[vlen
], &v
, TG3_VER_SIZE
- vlen
);
13344 memcpy(&tp
->fw_ver
[vlen
], &v
, sizeof(v
));
13349 static void __devinit
tg3_read_dash_ver(struct tg3
*tp
)
13355 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) ||
13356 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
13359 apedata
= tg3_ape_read32(tp
, TG3_APE_SEG_SIG
);
13360 if (apedata
!= APE_SEG_SIG_MAGIC
)
13363 apedata
= tg3_ape_read32(tp
, TG3_APE_FW_STATUS
);
13364 if (!(apedata
& APE_FW_STATUS_READY
))
13367 apedata
= tg3_ape_read32(tp
, TG3_APE_FW_VERSION
);
13369 if (tg3_ape_read32(tp
, TG3_APE_FW_FEATURES
) & TG3_APE_FW_FEATURE_NCSI
) {
13370 tp
->tg3_flags3
|= TG3_FLG3_APE_HAS_NCSI
;
13376 vlen
= strlen(tp
->fw_ver
);
13378 snprintf(&tp
->fw_ver
[vlen
], TG3_VER_SIZE
- vlen
, " %s v%d.%d.%d.%d",
13380 (apedata
& APE_FW_VERSION_MAJMSK
) >> APE_FW_VERSION_MAJSFT
,
13381 (apedata
& APE_FW_VERSION_MINMSK
) >> APE_FW_VERSION_MINSFT
,
13382 (apedata
& APE_FW_VERSION_REVMSK
) >> APE_FW_VERSION_REVSFT
,
13383 (apedata
& APE_FW_VERSION_BLDMSK
));
13386 static void __devinit
tg3_read_fw_ver(struct tg3
*tp
)
13389 bool vpd_vers
= false;
13391 if (tp
->fw_ver
[0] != 0)
13394 if (tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) {
13395 strcat(tp
->fw_ver
, "sb");
13399 if (tg3_nvram_read(tp
, 0, &val
))
13402 if (val
== TG3_EEPROM_MAGIC
)
13403 tg3_read_bc_ver(tp
);
13404 else if ((val
& TG3_EEPROM_MAGIC_FW_MSK
) == TG3_EEPROM_MAGIC_FW
)
13405 tg3_read_sb_ver(tp
, val
);
13406 else if ((val
& TG3_EEPROM_MAGIC_HW_MSK
) == TG3_EEPROM_MAGIC_HW
)
13407 tg3_read_hwsb_ver(tp
);
13411 if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) ||
13412 (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) || vpd_vers
)
13415 tg3_read_mgmtfw_ver(tp
);
13418 tp
->fw_ver
[TG3_VER_SIZE
- 1] = 0;
13421 static struct pci_dev
* __devinit
tg3_find_peer(struct tg3
*);
13423 static inline u32
tg3_rx_ret_ring_size(struct tg3
*tp
)
13425 if (tp
->tg3_flags3
& TG3_FLG3_LRG_PROD_RING_CAP
)
13426 return TG3_RX_RET_MAX_SIZE_5717
;
13427 else if ((tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) &&
13428 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
13429 return TG3_RX_RET_MAX_SIZE_5700
;
13431 return TG3_RX_RET_MAX_SIZE_5705
;
13434 static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets
) = {
13435 { PCI_DEVICE(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_FE_GATE_700C
) },
13436 { PCI_DEVICE(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8131_BRIDGE
) },
13437 { PCI_DEVICE(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8385_0
) },
13441 static int __devinit
tg3_get_invariants(struct tg3
*tp
)
13444 u32 pci_state_reg
, grc_misc_cfg
;
13449 /* Force memory write invalidate off. If we leave it on,
13450 * then on 5700_BX chips we have to enable a workaround.
13451 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
13452 * to match the cacheline size. The Broadcom driver have this
13453 * workaround but turns MWI off all the times so never uses
13454 * it. This seems to suggest that the workaround is insufficient.
13456 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
13457 pci_cmd
&= ~PCI_COMMAND_INVALIDATE
;
13458 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
13460 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
13461 * has the register indirect write enable bit set before
13462 * we try to access any of the MMIO registers. It is also
13463 * critical that the PCI-X hw workaround situation is decided
13464 * before that as well.
13466 pci_read_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
13469 tp
->pci_chip_rev_id
= (misc_ctrl_reg
>>
13470 MISC_HOST_CTRL_CHIPREV_SHIFT
);
13471 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_USE_PROD_ID_REG
) {
13472 u32 prod_id_asic_rev
;
13474 if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5717
||
13475 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5718
||
13476 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5719
||
13477 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5720
)
13478 pci_read_config_dword(tp
->pdev
,
13479 TG3PCI_GEN2_PRODID_ASICREV
,
13480 &prod_id_asic_rev
);
13481 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57781
||
13482 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57785
||
13483 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57761
||
13484 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57765
||
13485 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57791
||
13486 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57795
)
13487 pci_read_config_dword(tp
->pdev
,
13488 TG3PCI_GEN15_PRODID_ASICREV
,
13489 &prod_id_asic_rev
);
13491 pci_read_config_dword(tp
->pdev
, TG3PCI_PRODID_ASICREV
,
13492 &prod_id_asic_rev
);
13494 tp
->pci_chip_rev_id
= prod_id_asic_rev
;
13497 /* Wrong chip ID in 5752 A0. This code can be removed later
13498 * as A0 is not in production.
13500 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5752_A0_HW
)
13501 tp
->pci_chip_rev_id
= CHIPREV_ID_5752_A0
;
13503 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
13504 * we need to disable memory and use config. cycles
13505 * only to access all registers. The 5702/03 chips
13506 * can mistakenly decode the special cycles from the
13507 * ICH chipsets as memory write cycles, causing corruption
13508 * of register and memory space. Only certain ICH bridges
13509 * will drive special cycles with non-zero data during the
13510 * address phase which can fall within the 5703's address
13511 * range. This is not an ICH bug as the PCI spec allows
13512 * non-zero address during special cycles. However, only
13513 * these ICH bridges are known to drive non-zero addresses
13514 * during special cycles.
13516 * Since special cycles do not cross PCI bridges, we only
13517 * enable this workaround if the 5703 is on the secondary
13518 * bus of these ICH bridges.
13520 if ((tp
->pci_chip_rev_id
== CHIPREV_ID_5703_A1
) ||
13521 (tp
->pci_chip_rev_id
== CHIPREV_ID_5703_A2
)) {
13522 static struct tg3_dev_id
{
13526 } ich_chipsets
[] = {
13527 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AA_8
,
13529 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AB_8
,
13531 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_11
,
13533 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_6
,
13537 struct tg3_dev_id
*pci_id
= &ich_chipsets
[0];
13538 struct pci_dev
*bridge
= NULL
;
13540 while (pci_id
->vendor
!= 0) {
13541 bridge
= pci_get_device(pci_id
->vendor
, pci_id
->device
,
13547 if (pci_id
->rev
!= PCI_ANY_ID
) {
13548 if (bridge
->revision
> pci_id
->rev
)
13551 if (bridge
->subordinate
&&
13552 (bridge
->subordinate
->number
==
13553 tp
->pdev
->bus
->number
)) {
13555 tp
->tg3_flags2
|= TG3_FLG2_ICH_WORKAROUND
;
13556 pci_dev_put(bridge
);
13562 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)) {
13563 static struct tg3_dev_id
{
13566 } bridge_chipsets
[] = {
13567 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_0
},
13568 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_1
},
13571 struct tg3_dev_id
*pci_id
= &bridge_chipsets
[0];
13572 struct pci_dev
*bridge
= NULL
;
13574 while (pci_id
->vendor
!= 0) {
13575 bridge
= pci_get_device(pci_id
->vendor
,
13582 if (bridge
->subordinate
&&
13583 (bridge
->subordinate
->number
<=
13584 tp
->pdev
->bus
->number
) &&
13585 (bridge
->subordinate
->subordinate
>=
13586 tp
->pdev
->bus
->number
)) {
13587 tp
->tg3_flags3
|= TG3_FLG3_5701_DMA_BUG
;
13588 pci_dev_put(bridge
);
13594 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
13595 * DMA addresses > 40-bit. This bridge may have other additional
13596 * 57xx devices behind it in some 4-port NIC designs for example.
13597 * Any tg3 device found behind the bridge will also need the 40-bit
13600 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5780
||
13601 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
) {
13602 tp
->tg3_flags2
|= TG3_FLG2_5780_CLASS
;
13603 tp
->tg3_flags
|= TG3_FLAG_40BIT_DMA_BUG
;
13604 tp
->msi_cap
= pci_find_capability(tp
->pdev
, PCI_CAP_ID_MSI
);
13606 struct pci_dev
*bridge
= NULL
;
13609 bridge
= pci_get_device(PCI_VENDOR_ID_SERVERWORKS
,
13610 PCI_DEVICE_ID_SERVERWORKS_EPB
,
13612 if (bridge
&& bridge
->subordinate
&&
13613 (bridge
->subordinate
->number
<=
13614 tp
->pdev
->bus
->number
) &&
13615 (bridge
->subordinate
->subordinate
>=
13616 tp
->pdev
->bus
->number
)) {
13617 tp
->tg3_flags
|= TG3_FLAG_40BIT_DMA_BUG
;
13618 pci_dev_put(bridge
);
13624 /* Initialize misc host control in PCI block. */
13625 tp
->misc_host_ctrl
|= (misc_ctrl_reg
&
13626 MISC_HOST_CTRL_CHIPREV
);
13627 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
13628 tp
->misc_host_ctrl
);
13630 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
13631 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
||
13632 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
13633 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5720
)
13634 tp
->pdev_peer
= tg3_find_peer(tp
);
13636 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
13637 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
||
13638 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5720
)
13639 tp
->tg3_flags3
|= TG3_FLG3_5717_PLUS
;
13641 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
||
13642 (tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
))
13643 tp
->tg3_flags3
|= TG3_FLG3_57765_PLUS
;
13645 /* Intentionally exclude ASIC_REV_5906 */
13646 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
||
13647 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5787
||
13648 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
13649 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
13650 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
13651 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
||
13652 (tp
->tg3_flags3
& TG3_FLG3_57765_PLUS
))
13653 tp
->tg3_flags3
|= TG3_FLG3_5755_PLUS
;
13655 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
||
13656 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
||
13657 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
||
13658 (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) ||
13659 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
13660 tp
->tg3_flags2
|= TG3_FLG2_5750_PLUS
;
13663 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) ||
13664 (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
))
13665 tp
->tg3_flags2
|= TG3_FLG2_5705_PLUS
;
13667 /* 5700 B0 chips do not support checksumming correctly due
13668 * to hardware bugs.
13670 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5700_B0
) {
13671 u32 features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_RXCSUM
;
13673 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
13674 features
|= NETIF_F_IPV6_CSUM
;
13675 tp
->dev
->features
|= features
;
13676 tp
->dev
->hw_features
|= features
;
13677 tp
->dev
->vlan_features
|= features
;
13680 /* Determine TSO capabilities */
13681 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
)
13682 ; /* Do nothing. HW bug. */
13683 else if (tp
->tg3_flags3
& TG3_FLG3_57765_PLUS
)
13684 tp
->tg3_flags2
|= TG3_FLG2_HW_TSO_3
;
13685 else if ((tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) ||
13686 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
13687 tp
->tg3_flags2
|= TG3_FLG2_HW_TSO_2
;
13688 else if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) {
13689 tp
->tg3_flags2
|= TG3_FLG2_HW_TSO_1
| TG3_FLG2_TSO_BUG
;
13690 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
&&
13691 tp
->pci_chip_rev_id
>= CHIPREV_ID_5750_C2
)
13692 tp
->tg3_flags2
&= ~TG3_FLG2_TSO_BUG
;
13693 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
13694 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
&&
13695 tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A0
) {
13696 tp
->tg3_flags2
|= TG3_FLG2_TSO_BUG
;
13697 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
)
13698 tp
->fw_needed
= FIRMWARE_TG3TSO5
;
13700 tp
->fw_needed
= FIRMWARE_TG3TSO
;
13705 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) {
13706 tp
->tg3_flags
|= TG3_FLAG_SUPPORT_MSI
;
13707 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_AX
||
13708 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_BX
||
13709 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
&&
13710 tp
->pci_chip_rev_id
<= CHIPREV_ID_5714_A2
&&
13711 tp
->pdev_peer
== tp
->pdev
))
13712 tp
->tg3_flags
&= ~TG3_FLAG_SUPPORT_MSI
;
13714 if ((tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) ||
13715 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
13716 tp
->tg3_flags2
|= TG3_FLG2_1SHOT_MSI
;
13719 if (tp
->tg3_flags3
& TG3_FLG3_57765_PLUS
) {
13720 tp
->tg3_flags
|= TG3_FLAG_SUPPORT_MSIX
;
13721 tp
->irq_max
= TG3_IRQ_MAX_VECS
;
13725 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
13726 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
||
13727 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
13728 tp
->tg3_flags3
|= TG3_FLG3_SHORT_DMA_BUG
;
13729 else if (!(tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)) {
13730 tp
->tg3_flags3
|= TG3_FLG3_4G_DMA_BNDRY_BUG
;
13731 tp
->tg3_flags3
|= TG3_FLG3_40BIT_DMA_LIMIT_BUG
;
13734 if (tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
)
13735 tp
->tg3_flags3
|= TG3_FLG3_LRG_PROD_RING_CAP
;
13737 if ((tp
->tg3_flags3
& TG3_FLG3_57765_PLUS
) &&
13738 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5719
)
13739 tp
->tg3_flags3
|= TG3_FLG3_USE_JUMBO_BDFLAG
;
13741 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) ||
13742 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) ||
13743 (tp
->tg3_flags3
& TG3_FLG3_USE_JUMBO_BDFLAG
))
13744 tp
->tg3_flags
|= TG3_FLAG_JUMBO_CAPABLE
;
13746 pci_read_config_dword(tp
->pdev
, TG3PCI_PCISTATE
,
13749 tp
->pcie_cap
= pci_find_capability(tp
->pdev
, PCI_CAP_ID_EXP
);
13750 if (tp
->pcie_cap
!= 0) {
13753 tp
->tg3_flags2
|= TG3_FLG2_PCI_EXPRESS
;
13755 tp
->pcie_readrq
= 4096;
13756 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
||
13757 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5720
)
13758 tp
->pcie_readrq
= 2048;
13760 pcie_set_readrq(tp
->pdev
, tp
->pcie_readrq
);
13762 pci_read_config_word(tp
->pdev
,
13763 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
13765 if (lnkctl
& PCI_EXP_LNKCTL_CLKREQ_EN
) {
13766 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
13767 tp
->tg3_flags2
&= ~TG3_FLG2_HW_TSO_2
;
13768 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
13769 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
13770 tp
->pci_chip_rev_id
== CHIPREV_ID_57780_A0
||
13771 tp
->pci_chip_rev_id
== CHIPREV_ID_57780_A1
)
13772 tp
->tg3_flags3
|= TG3_FLG3_CLKREQ_BUG
;
13773 } else if (tp
->pci_chip_rev_id
== CHIPREV_ID_5717_A0
) {
13774 tp
->tg3_flags3
|= TG3_FLG3_L1PLLPD_EN
;
13776 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
) {
13777 tp
->tg3_flags2
|= TG3_FLG2_PCI_EXPRESS
;
13778 } else if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) ||
13779 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
13780 tp
->pcix_cap
= pci_find_capability(tp
->pdev
, PCI_CAP_ID_PCIX
);
13781 if (!tp
->pcix_cap
) {
13782 dev_err(&tp
->pdev
->dev
,
13783 "Cannot find PCI-X capability, aborting\n");
13787 if (!(pci_state_reg
& PCISTATE_CONV_PCI_MODE
))
13788 tp
->tg3_flags
|= TG3_FLAG_PCIX_MODE
;
13791 /* If we have an AMD 762 or VIA K8T800 chipset, write
13792 * reordering to the mailbox registers done by the host
13793 * controller can cause major troubles. We read back from
13794 * every mailbox register write to force the writes to be
13795 * posted to the chip in order.
13797 if (pci_dev_present(tg3_write_reorder_chipsets
) &&
13798 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
))
13799 tp
->tg3_flags
|= TG3_FLAG_MBOX_WRITE_REORDER
;
13801 pci_read_config_byte(tp
->pdev
, PCI_CACHE_LINE_SIZE
,
13802 &tp
->pci_cacheline_sz
);
13803 pci_read_config_byte(tp
->pdev
, PCI_LATENCY_TIMER
,
13804 &tp
->pci_lat_timer
);
13805 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
&&
13806 tp
->pci_lat_timer
< 64) {
13807 tp
->pci_lat_timer
= 64;
13808 pci_write_config_byte(tp
->pdev
, PCI_LATENCY_TIMER
,
13809 tp
->pci_lat_timer
);
13812 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5700_BX
) {
13813 /* 5700 BX chips need to have their TX producer index
13814 * mailboxes written twice to workaround a bug.
13816 tp
->tg3_flags
|= TG3_FLAG_TXD_MBOX_HWBUG
;
13818 /* If we are in PCI-X mode, enable register write workaround.
13820 * The workaround is to use indirect register accesses
13821 * for all chip writes not to mailbox registers.
13823 if (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) {
13826 tp
->tg3_flags
|= TG3_FLAG_PCIX_TARGET_HWBUG
;
13828 /* The chip can have it's power management PCI config
13829 * space registers clobbered due to this bug.
13830 * So explicitly force the chip into D0 here.
13832 pci_read_config_dword(tp
->pdev
,
13833 tp
->pm_cap
+ PCI_PM_CTRL
,
13835 pm_reg
&= ~PCI_PM_CTRL_STATE_MASK
;
13836 pm_reg
|= PCI_PM_CTRL_PME_ENABLE
| 0 /* D0 */;
13837 pci_write_config_dword(tp
->pdev
,
13838 tp
->pm_cap
+ PCI_PM_CTRL
,
13841 /* Also, force SERR#/PERR# in PCI command. */
13842 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
13843 pci_cmd
|= PCI_COMMAND_PARITY
| PCI_COMMAND_SERR
;
13844 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
13848 if ((pci_state_reg
& PCISTATE_BUS_SPEED_HIGH
) != 0)
13849 tp
->tg3_flags
|= TG3_FLAG_PCI_HIGH_SPEED
;
13850 if ((pci_state_reg
& PCISTATE_BUS_32BIT
) != 0)
13851 tp
->tg3_flags
|= TG3_FLAG_PCI_32BIT
;
13853 /* Chip-specific fixup from Broadcom driver */
13854 if ((tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
) &&
13855 (!(pci_state_reg
& PCISTATE_RETRY_SAME_DMA
))) {
13856 pci_state_reg
|= PCISTATE_RETRY_SAME_DMA
;
13857 pci_write_config_dword(tp
->pdev
, TG3PCI_PCISTATE
, pci_state_reg
);
13860 /* Default fast path register access methods */
13861 tp
->read32
= tg3_read32
;
13862 tp
->write32
= tg3_write32
;
13863 tp
->read32_mbox
= tg3_read32
;
13864 tp
->write32_mbox
= tg3_write32
;
13865 tp
->write32_tx_mbox
= tg3_write32
;
13866 tp
->write32_rx_mbox
= tg3_write32
;
13868 /* Various workaround register access methods */
13869 if (tp
->tg3_flags
& TG3_FLAG_PCIX_TARGET_HWBUG
)
13870 tp
->write32
= tg3_write_indirect_reg32
;
13871 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
||
13872 ((tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) &&
13873 tp
->pci_chip_rev_id
== CHIPREV_ID_5750_A0
)) {
13875 * Back to back register writes can cause problems on these
13876 * chips, the workaround is to read back all reg writes
13877 * except those to mailbox regs.
13879 * See tg3_write_indirect_reg32().
13881 tp
->write32
= tg3_write_flush_reg32
;
13884 if ((tp
->tg3_flags
& TG3_FLAG_TXD_MBOX_HWBUG
) ||
13885 (tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
)) {
13886 tp
->write32_tx_mbox
= tg3_write32_tx_mbox
;
13887 if (tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
)
13888 tp
->write32_rx_mbox
= tg3_write_flush_reg32
;
13891 if (tp
->tg3_flags2
& TG3_FLG2_ICH_WORKAROUND
) {
13892 tp
->read32
= tg3_read_indirect_reg32
;
13893 tp
->write32
= tg3_write_indirect_reg32
;
13894 tp
->read32_mbox
= tg3_read_indirect_mbox
;
13895 tp
->write32_mbox
= tg3_write_indirect_mbox
;
13896 tp
->write32_tx_mbox
= tg3_write_indirect_mbox
;
13897 tp
->write32_rx_mbox
= tg3_write_indirect_mbox
;
13902 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
13903 pci_cmd
&= ~PCI_COMMAND_MEMORY
;
13904 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
13906 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
13907 tp
->read32_mbox
= tg3_read32_mbox_5906
;
13908 tp
->write32_mbox
= tg3_write32_mbox_5906
;
13909 tp
->write32_tx_mbox
= tg3_write32_mbox_5906
;
13910 tp
->write32_rx_mbox
= tg3_write32_mbox_5906
;
13913 if (tp
->write32
== tg3_write_indirect_reg32
||
13914 ((tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) &&
13915 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
13916 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)))
13917 tp
->tg3_flags
|= TG3_FLAG_SRAM_USE_CONFIG
;
13919 /* Get eeprom hw config before calling tg3_set_power_state().
13920 * In particular, the TG3_FLG2_IS_NIC flag must be
13921 * determined before calling tg3_set_power_state() so that
13922 * we know whether or not to switch out of Vaux power.
13923 * When the flag is set, it means that GPIO1 is used for eeprom
13924 * write protect and also implies that it is a LOM where GPIOs
13925 * are not used to switch power.
13927 tg3_get_eeprom_hw_cfg(tp
);
13929 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
13930 /* Allow reads and writes to the
13931 * APE register and memory space.
13933 pci_state_reg
|= PCISTATE_ALLOW_APE_CTLSPC_WR
|
13934 PCISTATE_ALLOW_APE_SHMEM_WR
|
13935 PCISTATE_ALLOW_APE_PSPACE_WR
;
13936 pci_write_config_dword(tp
->pdev
, TG3PCI_PCISTATE
,
13940 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
13941 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
13942 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
13943 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
||
13944 (tp
->tg3_flags3
& TG3_FLG3_57765_PLUS
))
13945 tp
->tg3_flags
|= TG3_FLAG_CPMU_PRESENT
;
13947 /* Set up tp->grc_local_ctrl before calling tg_power_up().
13948 * GPIO1 driven high will bring 5700's external PHY out of reset.
13949 * It is also used as eeprom write protect on LOMs.
13951 tp
->grc_local_ctrl
= GRC_LCLCTRL_INT_ON_ATTN
| GRC_LCLCTRL_AUTO_SEEPROM
;
13952 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) ||
13953 (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
))
13954 tp
->grc_local_ctrl
|= (GRC_LCLCTRL_GPIO_OE1
|
13955 GRC_LCLCTRL_GPIO_OUTPUT1
);
13956 /* Unused GPIO3 must be driven as output on 5752 because there
13957 * are no pull-up resistors on unused GPIO pins.
13959 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
)
13960 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE3
;
13962 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
||
13963 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
||
13964 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
13965 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_UART_SEL
;
13967 if (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5761
||
13968 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5761S
) {
13969 /* Turn off the debug UART. */
13970 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_UART_SEL
;
13971 if (tp
->tg3_flags2
& TG3_FLG2_IS_NIC
)
13972 /* Keep VMain power. */
13973 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE0
|
13974 GRC_LCLCTRL_GPIO_OUTPUT0
;
13977 /* Force the chip into D0. */
13978 err
= tg3_power_up(tp
);
13980 dev_err(&tp
->pdev
->dev
, "Transition to D0 failed\n");
13984 /* Derive initial jumbo mode from MTU assigned in
13985 * ether_setup() via the alloc_etherdev() call
13987 if (tp
->dev
->mtu
> ETH_DATA_LEN
&&
13988 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
13989 tp
->tg3_flags
|= TG3_FLAG_JUMBO_RING_ENABLE
;
13991 /* Determine WakeOnLan speed to use. */
13992 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
13993 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
13994 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
||
13995 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B2
) {
13996 tp
->tg3_flags
&= ~(TG3_FLAG_WOL_SPEED_100MB
);
13998 tp
->tg3_flags
|= TG3_FLAG_WOL_SPEED_100MB
;
14001 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
14002 tp
->phy_flags
|= TG3_PHYFLG_IS_FET
;
14004 /* A few boards don't want Ethernet@WireSpeed phy feature */
14005 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) ||
14006 ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) &&
14007 (tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A0
) &&
14008 (tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A1
)) ||
14009 (tp
->phy_flags
& TG3_PHYFLG_IS_FET
) ||
14010 (tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
))
14011 tp
->phy_flags
|= TG3_PHYFLG_NO_ETH_WIRE_SPEED
;
14013 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5703_AX
||
14014 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5704_AX
)
14015 tp
->phy_flags
|= TG3_PHYFLG_ADC_BUG
;
14016 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
)
14017 tp
->phy_flags
|= TG3_PHYFLG_5704_A0_BUG
;
14019 if ((tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
14020 !(tp
->phy_flags
& TG3_PHYFLG_IS_FET
) &&
14021 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5785
&&
14022 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_57780
&&
14023 !(tp
->tg3_flags3
& TG3_FLG3_57765_PLUS
)) {
14024 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
||
14025 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5787
||
14026 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
14027 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
) {
14028 if (tp
->pdev
->device
!= PCI_DEVICE_ID_TIGON3_5756
&&
14029 tp
->pdev
->device
!= PCI_DEVICE_ID_TIGON3_5722
)
14030 tp
->phy_flags
|= TG3_PHYFLG_JITTER_BUG
;
14031 if (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5755M
)
14032 tp
->phy_flags
|= TG3_PHYFLG_ADJUST_TRIM
;
14034 tp
->phy_flags
|= TG3_PHYFLG_BER_BUG
;
14037 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
14038 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
) {
14039 tp
->phy_otp
= tg3_read_otp_phycfg(tp
);
14040 if (tp
->phy_otp
== 0)
14041 tp
->phy_otp
= TG3_OTP_DEFAULT
;
14044 if (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
)
14045 tp
->mi_mode
= MAC_MI_MODE_500KHZ_CONST
;
14047 tp
->mi_mode
= MAC_MI_MODE_BASE
;
14049 tp
->coalesce_mode
= 0;
14050 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5700_AX
&&
14051 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5700_BX
)
14052 tp
->coalesce_mode
|= HOSTCC_MODE_32BYTE
;
14054 /* Set these bits to enable statistics workaround. */
14055 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
14056 tp
->pci_chip_rev_id
== CHIPREV_ID_5719_A0
||
14057 tp
->pci_chip_rev_id
== CHIPREV_ID_5720_A0
) {
14058 tp
->coalesce_mode
|= HOSTCC_MODE_ATTN
;
14059 tp
->grc_mode
|= GRC_MODE_IRQ_ON_FLOW_ATTN
;
14062 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
14063 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
14064 tp
->tg3_flags3
|= TG3_FLG3_USE_PHYLIB
;
14066 err
= tg3_mdio_init(tp
);
14070 /* Initialize data/descriptor byte/word swapping. */
14071 val
= tr32(GRC_MODE
);
14072 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5720
)
14073 val
&= (GRC_MODE_BYTE_SWAP_B2HRX_DATA
|
14074 GRC_MODE_WORD_SWAP_B2HRX_DATA
|
14075 GRC_MODE_B2HRX_ENABLE
|
14076 GRC_MODE_HTX2B_ENABLE
|
14077 GRC_MODE_HOST_STACKUP
);
14079 val
&= GRC_MODE_HOST_STACKUP
;
14081 tw32(GRC_MODE
, val
| tp
->grc_mode
);
14083 tg3_switch_clocks(tp
);
14085 /* Clear this out for sanity. */
14086 tw32(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
14088 pci_read_config_dword(tp
->pdev
, TG3PCI_PCISTATE
,
14090 if ((pci_state_reg
& PCISTATE_CONV_PCI_MODE
) == 0 &&
14091 (tp
->tg3_flags
& TG3_FLAG_PCIX_TARGET_HWBUG
) == 0) {
14092 u32 chiprevid
= GET_CHIP_REV_ID(tp
->misc_host_ctrl
);
14094 if (chiprevid
== CHIPREV_ID_5701_A0
||
14095 chiprevid
== CHIPREV_ID_5701_B0
||
14096 chiprevid
== CHIPREV_ID_5701_B2
||
14097 chiprevid
== CHIPREV_ID_5701_B5
) {
14098 void __iomem
*sram_base
;
14100 /* Write some dummy words into the SRAM status block
14101 * area, see if it reads back correctly. If the return
14102 * value is bad, force enable the PCIX workaround.
14104 sram_base
= tp
->regs
+ NIC_SRAM_WIN_BASE
+ NIC_SRAM_STATS_BLK
;
14106 writel(0x00000000, sram_base
);
14107 writel(0x00000000, sram_base
+ 4);
14108 writel(0xffffffff, sram_base
+ 4);
14109 if (readl(sram_base
) != 0x00000000)
14110 tp
->tg3_flags
|= TG3_FLAG_PCIX_TARGET_HWBUG
;
14115 tg3_nvram_init(tp
);
14117 grc_misc_cfg
= tr32(GRC_MISC_CFG
);
14118 grc_misc_cfg
&= GRC_MISC_CFG_BOARD_ID_MASK
;
14120 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
14121 (grc_misc_cfg
== GRC_MISC_CFG_BOARD_ID_5788
||
14122 grc_misc_cfg
== GRC_MISC_CFG_BOARD_ID_5788M
))
14123 tp
->tg3_flags2
|= TG3_FLG2_IS_5788
;
14125 if (!(tp
->tg3_flags2
& TG3_FLG2_IS_5788
) &&
14126 (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
))
14127 tp
->tg3_flags
|= TG3_FLAG_TAGGED_STATUS
;
14128 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) {
14129 tp
->coalesce_mode
|= (HOSTCC_MODE_CLRTICK_RXBD
|
14130 HOSTCC_MODE_CLRTICK_TXBD
);
14132 tp
->misc_host_ctrl
|= MISC_HOST_CTRL_TAGGED_STATUS
;
14133 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
14134 tp
->misc_host_ctrl
);
14137 /* Preserve the APE MAC_MODE bits */
14138 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
14139 tp
->mac_mode
= MAC_MODE_APE_TX_EN
| MAC_MODE_APE_RX_EN
;
14141 tp
->mac_mode
= TG3_DEF_MAC_MODE
;
14143 /* these are limited to 10/100 only */
14144 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
&&
14145 (grc_misc_cfg
== 0x8000 || grc_misc_cfg
== 0x4000)) ||
14146 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
14147 tp
->pdev
->vendor
== PCI_VENDOR_ID_BROADCOM
&&
14148 (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5901
||
14149 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5901_2
||
14150 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5705F
)) ||
14151 (tp
->pdev
->vendor
== PCI_VENDOR_ID_BROADCOM
&&
14152 (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5751F
||
14153 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5753F
||
14154 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5787F
)) ||
14155 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57790
||
14156 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57791
||
14157 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57795
||
14158 (tp
->phy_flags
& TG3_PHYFLG_IS_FET
))
14159 tp
->phy_flags
|= TG3_PHYFLG_10_100_ONLY
;
14161 err
= tg3_phy_probe(tp
);
14163 dev_err(&tp
->pdev
->dev
, "phy probe failed, err %d\n", err
);
14164 /* ... but do not return immediately ... */
14169 tg3_read_fw_ver(tp
);
14171 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) {
14172 tp
->phy_flags
&= ~TG3_PHYFLG_USE_MI_INTERRUPT
;
14174 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
)
14175 tp
->phy_flags
|= TG3_PHYFLG_USE_MI_INTERRUPT
;
14177 tp
->phy_flags
&= ~TG3_PHYFLG_USE_MI_INTERRUPT
;
14180 /* 5700 {AX,BX} chips have a broken status block link
14181 * change bit implementation, so we must use the
14182 * status register in those cases.
14184 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
)
14185 tp
->tg3_flags
|= TG3_FLAG_USE_LINKCHG_REG
;
14187 tp
->tg3_flags
&= ~TG3_FLAG_USE_LINKCHG_REG
;
14189 /* The led_ctrl is set during tg3_phy_probe, here we might
14190 * have to force the link status polling mechanism based
14191 * upon subsystem IDs.
14193 if (tp
->pdev
->subsystem_vendor
== PCI_VENDOR_ID_DELL
&&
14194 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
&&
14195 !(tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
)) {
14196 tp
->phy_flags
|= TG3_PHYFLG_USE_MI_INTERRUPT
;
14197 tp
->tg3_flags
|= TG3_FLAG_USE_LINKCHG_REG
;
14200 /* For all SERDES we poll the MAC status register. */
14201 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
)
14202 tp
->tg3_flags
|= TG3_FLAG_POLL_SERDES
;
14204 tp
->tg3_flags
&= ~TG3_FLAG_POLL_SERDES
;
14206 tp
->rx_offset
= NET_IP_ALIGN
;
14207 tp
->rx_copy_thresh
= TG3_RX_COPY_THRESHOLD
;
14208 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
&&
14209 (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) != 0) {
14211 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
14212 tp
->rx_copy_thresh
= ~(u16
)0;
14216 tp
->rx_std_ring_mask
= TG3_RX_STD_RING_SIZE(tp
) - 1;
14217 tp
->rx_jmb_ring_mask
= TG3_RX_JMB_RING_SIZE(tp
) - 1;
14218 tp
->rx_ret_ring_mask
= tg3_rx_ret_ring_size(tp
) - 1;
14220 tp
->rx_std_max_post
= tp
->rx_std_ring_mask
+ 1;
14222 /* Increment the rx prod index on the rx std ring by at most
14223 * 8 for these chips to workaround hw errata.
14225 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
||
14226 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
||
14227 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
)
14228 tp
->rx_std_max_post
= 8;
14230 if (tp
->tg3_flags
& TG3_FLAG_ASPM_WORKAROUND
)
14231 tp
->pwrmgmt_thresh
= tr32(PCIE_PWR_MGMT_THRESH
) &
14232 PCIE_PWR_MGMT_L1_THRESH_MSK
;
14237 #ifdef CONFIG_SPARC
14238 static int __devinit
tg3_get_macaddr_sparc(struct tg3
*tp
)
14240 struct net_device
*dev
= tp
->dev
;
14241 struct pci_dev
*pdev
= tp
->pdev
;
14242 struct device_node
*dp
= pci_device_to_OF_node(pdev
);
14243 const unsigned char *addr
;
14246 addr
= of_get_property(dp
, "local-mac-address", &len
);
14247 if (addr
&& len
== 6) {
14248 memcpy(dev
->dev_addr
, addr
, 6);
14249 memcpy(dev
->perm_addr
, dev
->dev_addr
, 6);
14255 static int __devinit
tg3_get_default_macaddr_sparc(struct tg3
*tp
)
14257 struct net_device
*dev
= tp
->dev
;
14259 memcpy(dev
->dev_addr
, idprom
->id_ethaddr
, 6);
14260 memcpy(dev
->perm_addr
, idprom
->id_ethaddr
, 6);
14265 static int __devinit
tg3_get_device_address(struct tg3
*tp
)
14267 struct net_device
*dev
= tp
->dev
;
14268 u32 hi
, lo
, mac_offset
;
14271 #ifdef CONFIG_SPARC
14272 if (!tg3_get_macaddr_sparc(tp
))
14277 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) ||
14278 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
14279 if (tr32(TG3PCI_DUAL_MAC_CTRL
) & DUAL_MAC_CTRL_ID
)
14281 if (tg3_nvram_lock(tp
))
14282 tw32_f(NVRAM_CMD
, NVRAM_CMD_RESET
);
14284 tg3_nvram_unlock(tp
);
14285 } else if (tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
) {
14286 if (PCI_FUNC(tp
->pdev
->devfn
) & 1)
14288 if (PCI_FUNC(tp
->pdev
->devfn
) > 1)
14289 mac_offset
+= 0x18c;
14290 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
14293 /* First try to get it from MAC address mailbox. */
14294 tg3_read_mem(tp
, NIC_SRAM_MAC_ADDR_HIGH_MBOX
, &hi
);
14295 if ((hi
>> 16) == 0x484b) {
14296 dev
->dev_addr
[0] = (hi
>> 8) & 0xff;
14297 dev
->dev_addr
[1] = (hi
>> 0) & 0xff;
14299 tg3_read_mem(tp
, NIC_SRAM_MAC_ADDR_LOW_MBOX
, &lo
);
14300 dev
->dev_addr
[2] = (lo
>> 24) & 0xff;
14301 dev
->dev_addr
[3] = (lo
>> 16) & 0xff;
14302 dev
->dev_addr
[4] = (lo
>> 8) & 0xff;
14303 dev
->dev_addr
[5] = (lo
>> 0) & 0xff;
14305 /* Some old bootcode may report a 0 MAC address in SRAM */
14306 addr_ok
= is_valid_ether_addr(&dev
->dev_addr
[0]);
14309 /* Next, try NVRAM. */
14310 if (!(tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) &&
14311 !tg3_nvram_read_be32(tp
, mac_offset
+ 0, &hi
) &&
14312 !tg3_nvram_read_be32(tp
, mac_offset
+ 4, &lo
)) {
14313 memcpy(&dev
->dev_addr
[0], ((char *)&hi
) + 2, 2);
14314 memcpy(&dev
->dev_addr
[2], (char *)&lo
, sizeof(lo
));
14316 /* Finally just fetch it out of the MAC control regs. */
14318 hi
= tr32(MAC_ADDR_0_HIGH
);
14319 lo
= tr32(MAC_ADDR_0_LOW
);
14321 dev
->dev_addr
[5] = lo
& 0xff;
14322 dev
->dev_addr
[4] = (lo
>> 8) & 0xff;
14323 dev
->dev_addr
[3] = (lo
>> 16) & 0xff;
14324 dev
->dev_addr
[2] = (lo
>> 24) & 0xff;
14325 dev
->dev_addr
[1] = hi
& 0xff;
14326 dev
->dev_addr
[0] = (hi
>> 8) & 0xff;
14330 if (!is_valid_ether_addr(&dev
->dev_addr
[0])) {
14331 #ifdef CONFIG_SPARC
14332 if (!tg3_get_default_macaddr_sparc(tp
))
14337 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
14341 #define BOUNDARY_SINGLE_CACHELINE 1
14342 #define BOUNDARY_MULTI_CACHELINE 2
14344 static u32 __devinit
tg3_calc_dma_bndry(struct tg3
*tp
, u32 val
)
14346 int cacheline_size
;
14350 pci_read_config_byte(tp
->pdev
, PCI_CACHE_LINE_SIZE
, &byte
);
14352 cacheline_size
= 1024;
14354 cacheline_size
= (int) byte
* 4;
14356 /* On 5703 and later chips, the boundary bits have no
14359 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
14360 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
&&
14361 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
))
14364 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
14365 goal
= BOUNDARY_MULTI_CACHELINE
;
14367 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
14368 goal
= BOUNDARY_SINGLE_CACHELINE
;
14374 if (tp
->tg3_flags3
& TG3_FLG3_57765_PLUS
) {
14375 val
= goal
? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT
;
14382 /* PCI controllers on most RISC systems tend to disconnect
14383 * when a device tries to burst across a cache-line boundary.
14384 * Therefore, letting tg3 do so just wastes PCI bandwidth.
14386 * Unfortunately, for PCI-E there are only limited
14387 * write-side controls for this, and thus for reads
14388 * we will still get the disconnects. We'll also waste
14389 * these PCI cycles for both read and write for chips
14390 * other than 5700 and 5701 which do not implement the
14393 if ((tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) &&
14394 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)) {
14395 switch (cacheline_size
) {
14400 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
14401 val
|= (DMA_RWCTRL_READ_BNDRY_128_PCIX
|
14402 DMA_RWCTRL_WRITE_BNDRY_128_PCIX
);
14404 val
|= (DMA_RWCTRL_READ_BNDRY_384_PCIX
|
14405 DMA_RWCTRL_WRITE_BNDRY_384_PCIX
);
14410 val
|= (DMA_RWCTRL_READ_BNDRY_256_PCIX
|
14411 DMA_RWCTRL_WRITE_BNDRY_256_PCIX
);
14415 val
|= (DMA_RWCTRL_READ_BNDRY_384_PCIX
|
14416 DMA_RWCTRL_WRITE_BNDRY_384_PCIX
);
14419 } else if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
14420 switch (cacheline_size
) {
14424 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
14425 val
&= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE
;
14426 val
|= DMA_RWCTRL_WRITE_BNDRY_64_PCIE
;
14432 val
&= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE
;
14433 val
|= DMA_RWCTRL_WRITE_BNDRY_128_PCIE
;
14437 switch (cacheline_size
) {
14439 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
14440 val
|= (DMA_RWCTRL_READ_BNDRY_16
|
14441 DMA_RWCTRL_WRITE_BNDRY_16
);
14446 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
14447 val
|= (DMA_RWCTRL_READ_BNDRY_32
|
14448 DMA_RWCTRL_WRITE_BNDRY_32
);
14453 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
14454 val
|= (DMA_RWCTRL_READ_BNDRY_64
|
14455 DMA_RWCTRL_WRITE_BNDRY_64
);
14460 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
14461 val
|= (DMA_RWCTRL_READ_BNDRY_128
|
14462 DMA_RWCTRL_WRITE_BNDRY_128
);
14467 val
|= (DMA_RWCTRL_READ_BNDRY_256
|
14468 DMA_RWCTRL_WRITE_BNDRY_256
);
14471 val
|= (DMA_RWCTRL_READ_BNDRY_512
|
14472 DMA_RWCTRL_WRITE_BNDRY_512
);
14476 val
|= (DMA_RWCTRL_READ_BNDRY_1024
|
14477 DMA_RWCTRL_WRITE_BNDRY_1024
);
14486 static int __devinit
tg3_do_test_dma(struct tg3
*tp
, u32
*buf
, dma_addr_t buf_dma
, int size
, int to_device
)
14488 struct tg3_internal_buffer_desc test_desc
;
14489 u32 sram_dma_descs
;
14492 sram_dma_descs
= NIC_SRAM_DMA_DESC_POOL_BASE
;
14494 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ
, 0);
14495 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ
, 0);
14496 tw32(RDMAC_STATUS
, 0);
14497 tw32(WDMAC_STATUS
, 0);
14499 tw32(BUFMGR_MODE
, 0);
14500 tw32(FTQ_RESET
, 0);
14502 test_desc
.addr_hi
= ((u64
) buf_dma
) >> 32;
14503 test_desc
.addr_lo
= buf_dma
& 0xffffffff;
14504 test_desc
.nic_mbuf
= 0x00002100;
14505 test_desc
.len
= size
;
14508 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
14509 * the *second* time the tg3 driver was getting loaded after an
14512 * Broadcom tells me:
14513 * ...the DMA engine is connected to the GRC block and a DMA
14514 * reset may affect the GRC block in some unpredictable way...
14515 * The behavior of resets to individual blocks has not been tested.
14517 * Broadcom noted the GRC reset will also reset all sub-components.
14520 test_desc
.cqid_sqid
= (13 << 8) | 2;
14522 tw32_f(RDMAC_MODE
, RDMAC_MODE_ENABLE
);
14525 test_desc
.cqid_sqid
= (16 << 8) | 7;
14527 tw32_f(WDMAC_MODE
, WDMAC_MODE_ENABLE
);
14530 test_desc
.flags
= 0x00000005;
14532 for (i
= 0; i
< (sizeof(test_desc
) / sizeof(u32
)); i
++) {
14535 val
= *(((u32
*)&test_desc
) + i
);
14536 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
,
14537 sram_dma_descs
+ (i
* sizeof(u32
)));
14538 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_DATA
, val
);
14540 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, 0);
14543 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ
, sram_dma_descs
);
14545 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ
, sram_dma_descs
);
14548 for (i
= 0; i
< 40; i
++) {
14552 val
= tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ
);
14554 val
= tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ
);
14555 if ((val
& 0xffff) == sram_dma_descs
) {
14566 #define TEST_BUFFER_SIZE 0x2000
14568 static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets
) = {
14569 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_UNI_N_PCI15
) },
14573 static int __devinit
tg3_test_dma(struct tg3
*tp
)
14575 dma_addr_t buf_dma
;
14576 u32
*buf
, saved_dma_rwctrl
;
14579 buf
= dma_alloc_coherent(&tp
->pdev
->dev
, TEST_BUFFER_SIZE
,
14580 &buf_dma
, GFP_KERNEL
);
14586 tp
->dma_rwctrl
= ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT
) |
14587 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT
));
14589 tp
->dma_rwctrl
= tg3_calc_dma_bndry(tp
, tp
->dma_rwctrl
);
14591 if (tp
->tg3_flags3
& TG3_FLG3_57765_PLUS
)
14594 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
14595 /* DMA read watermark not used on PCIE */
14596 tp
->dma_rwctrl
|= 0x00180000;
14597 } else if (!(tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
)) {
14598 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
||
14599 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
)
14600 tp
->dma_rwctrl
|= 0x003f0000;
14602 tp
->dma_rwctrl
|= 0x003f000f;
14604 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
14605 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
14606 u32 ccval
= (tr32(TG3PCI_CLOCK_CTRL
) & 0x1f);
14607 u32 read_water
= 0x7;
14609 /* If the 5704 is behind the EPB bridge, we can
14610 * do the less restrictive ONE_DMA workaround for
14611 * better performance.
14613 if ((tp
->tg3_flags
& TG3_FLAG_40BIT_DMA_BUG
) &&
14614 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
)
14615 tp
->dma_rwctrl
|= 0x8000;
14616 else if (ccval
== 0x6 || ccval
== 0x7)
14617 tp
->dma_rwctrl
|= DMA_RWCTRL_ONE_DMA
;
14619 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
)
14621 /* Set bit 23 to enable PCIX hw bug fix */
14623 (read_water
<< DMA_RWCTRL_READ_WATER_SHIFT
) |
14624 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT
) |
14626 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5780
) {
14627 /* 5780 always in PCIX mode */
14628 tp
->dma_rwctrl
|= 0x00144000;
14629 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
) {
14630 /* 5714 always in PCIX mode */
14631 tp
->dma_rwctrl
|= 0x00148000;
14633 tp
->dma_rwctrl
|= 0x001b000f;
14637 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
14638 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
)
14639 tp
->dma_rwctrl
&= 0xfffffff0;
14641 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
14642 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
14643 /* Remove this if it causes problems for some boards. */
14644 tp
->dma_rwctrl
|= DMA_RWCTRL_USE_MEM_READ_MULT
;
14646 /* On 5700/5701 chips, we need to set this bit.
14647 * Otherwise the chip will issue cacheline transactions
14648 * to streamable DMA memory with not all the byte
14649 * enables turned on. This is an error on several
14650 * RISC PCI controllers, in particular sparc64.
14652 * On 5703/5704 chips, this bit has been reassigned
14653 * a different meaning. In particular, it is used
14654 * on those chips to enable a PCI-X workaround.
14656 tp
->dma_rwctrl
|= DMA_RWCTRL_ASSERT_ALL_BE
;
14659 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
14662 /* Unneeded, already done by tg3_get_invariants. */
14663 tg3_switch_clocks(tp
);
14666 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
14667 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
)
14670 /* It is best to perform DMA test with maximum write burst size
14671 * to expose the 5700/5701 write DMA bug.
14673 saved_dma_rwctrl
= tp
->dma_rwctrl
;
14674 tp
->dma_rwctrl
&= ~DMA_RWCTRL_WRITE_BNDRY_MASK
;
14675 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
14680 for (i
= 0; i
< TEST_BUFFER_SIZE
/ sizeof(u32
); i
++)
14683 /* Send the buffer to the chip. */
14684 ret
= tg3_do_test_dma(tp
, buf
, buf_dma
, TEST_BUFFER_SIZE
, 1);
14686 dev_err(&tp
->pdev
->dev
,
14687 "%s: Buffer write failed. err = %d\n",
14693 /* validate data reached card RAM correctly. */
14694 for (i
= 0; i
< TEST_BUFFER_SIZE
/ sizeof(u32
); i
++) {
14696 tg3_read_mem(tp
, 0x2100 + (i
*4), &val
);
14697 if (le32_to_cpu(val
) != p
[i
]) {
14698 dev_err(&tp
->pdev
->dev
,
14699 "%s: Buffer corrupted on device! "
14700 "(%d != %d)\n", __func__
, val
, i
);
14701 /* ret = -ENODEV here? */
14706 /* Now read it back. */
14707 ret
= tg3_do_test_dma(tp
, buf
, buf_dma
, TEST_BUFFER_SIZE
, 0);
14709 dev_err(&tp
->pdev
->dev
, "%s: Buffer read failed. "
14710 "err = %d\n", __func__
, ret
);
14715 for (i
= 0; i
< TEST_BUFFER_SIZE
/ sizeof(u32
); i
++) {
14719 if ((tp
->dma_rwctrl
& DMA_RWCTRL_WRITE_BNDRY_MASK
) !=
14720 DMA_RWCTRL_WRITE_BNDRY_16
) {
14721 tp
->dma_rwctrl
&= ~DMA_RWCTRL_WRITE_BNDRY_MASK
;
14722 tp
->dma_rwctrl
|= DMA_RWCTRL_WRITE_BNDRY_16
;
14723 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
14726 dev_err(&tp
->pdev
->dev
,
14727 "%s: Buffer corrupted on read back! "
14728 "(%d != %d)\n", __func__
, p
[i
], i
);
14734 if (i
== (TEST_BUFFER_SIZE
/ sizeof(u32
))) {
14740 if ((tp
->dma_rwctrl
& DMA_RWCTRL_WRITE_BNDRY_MASK
) !=
14741 DMA_RWCTRL_WRITE_BNDRY_16
) {
14743 /* DMA test passed without adjusting DMA boundary,
14744 * now look for chipsets that are known to expose the
14745 * DMA bug without failing the test.
14747 if (pci_dev_present(tg3_dma_wait_state_chipsets
)) {
14748 tp
->dma_rwctrl
&= ~DMA_RWCTRL_WRITE_BNDRY_MASK
;
14749 tp
->dma_rwctrl
|= DMA_RWCTRL_WRITE_BNDRY_16
;
14751 /* Safe to use the calculated DMA boundary. */
14752 tp
->dma_rwctrl
= saved_dma_rwctrl
;
14755 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
14759 dma_free_coherent(&tp
->pdev
->dev
, TEST_BUFFER_SIZE
, buf
, buf_dma
);
14764 static void __devinit
tg3_init_bufmgr_config(struct tg3
*tp
)
14766 if (tp
->tg3_flags3
& TG3_FLG3_57765_PLUS
) {
14767 tp
->bufmgr_config
.mbuf_read_dma_low_water
=
14768 DEFAULT_MB_RDMA_LOW_WATER_5705
;
14769 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
14770 DEFAULT_MB_MACRX_LOW_WATER_57765
;
14771 tp
->bufmgr_config
.mbuf_high_water
=
14772 DEFAULT_MB_HIGH_WATER_57765
;
14774 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
=
14775 DEFAULT_MB_RDMA_LOW_WATER_5705
;
14776 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
=
14777 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765
;
14778 tp
->bufmgr_config
.mbuf_high_water_jumbo
=
14779 DEFAULT_MB_HIGH_WATER_JUMBO_57765
;
14780 } else if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
14781 tp
->bufmgr_config
.mbuf_read_dma_low_water
=
14782 DEFAULT_MB_RDMA_LOW_WATER_5705
;
14783 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
14784 DEFAULT_MB_MACRX_LOW_WATER_5705
;
14785 tp
->bufmgr_config
.mbuf_high_water
=
14786 DEFAULT_MB_HIGH_WATER_5705
;
14787 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
14788 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
14789 DEFAULT_MB_MACRX_LOW_WATER_5906
;
14790 tp
->bufmgr_config
.mbuf_high_water
=
14791 DEFAULT_MB_HIGH_WATER_5906
;
14794 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
=
14795 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780
;
14796 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
=
14797 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780
;
14798 tp
->bufmgr_config
.mbuf_high_water_jumbo
=
14799 DEFAULT_MB_HIGH_WATER_JUMBO_5780
;
14801 tp
->bufmgr_config
.mbuf_read_dma_low_water
=
14802 DEFAULT_MB_RDMA_LOW_WATER
;
14803 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
14804 DEFAULT_MB_MACRX_LOW_WATER
;
14805 tp
->bufmgr_config
.mbuf_high_water
=
14806 DEFAULT_MB_HIGH_WATER
;
14808 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
=
14809 DEFAULT_MB_RDMA_LOW_WATER_JUMBO
;
14810 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
=
14811 DEFAULT_MB_MACRX_LOW_WATER_JUMBO
;
14812 tp
->bufmgr_config
.mbuf_high_water_jumbo
=
14813 DEFAULT_MB_HIGH_WATER_JUMBO
;
14816 tp
->bufmgr_config
.dma_low_water
= DEFAULT_DMA_LOW_WATER
;
14817 tp
->bufmgr_config
.dma_high_water
= DEFAULT_DMA_HIGH_WATER
;
14820 static char * __devinit
tg3_phy_string(struct tg3
*tp
)
14822 switch (tp
->phy_id
& TG3_PHY_ID_MASK
) {
14823 case TG3_PHY_ID_BCM5400
: return "5400";
14824 case TG3_PHY_ID_BCM5401
: return "5401";
14825 case TG3_PHY_ID_BCM5411
: return "5411";
14826 case TG3_PHY_ID_BCM5701
: return "5701";
14827 case TG3_PHY_ID_BCM5703
: return "5703";
14828 case TG3_PHY_ID_BCM5704
: return "5704";
14829 case TG3_PHY_ID_BCM5705
: return "5705";
14830 case TG3_PHY_ID_BCM5750
: return "5750";
14831 case TG3_PHY_ID_BCM5752
: return "5752";
14832 case TG3_PHY_ID_BCM5714
: return "5714";
14833 case TG3_PHY_ID_BCM5780
: return "5780";
14834 case TG3_PHY_ID_BCM5755
: return "5755";
14835 case TG3_PHY_ID_BCM5787
: return "5787";
14836 case TG3_PHY_ID_BCM5784
: return "5784";
14837 case TG3_PHY_ID_BCM5756
: return "5722/5756";
14838 case TG3_PHY_ID_BCM5906
: return "5906";
14839 case TG3_PHY_ID_BCM5761
: return "5761";
14840 case TG3_PHY_ID_BCM5718C
: return "5718C";
14841 case TG3_PHY_ID_BCM5718S
: return "5718S";
14842 case TG3_PHY_ID_BCM57765
: return "57765";
14843 case TG3_PHY_ID_BCM5719C
: return "5719C";
14844 case TG3_PHY_ID_BCM5720C
: return "5720C";
14845 case TG3_PHY_ID_BCM8002
: return "8002/serdes";
14846 case 0: return "serdes";
14847 default: return "unknown";
14851 static char * __devinit
tg3_bus_string(struct tg3
*tp
, char *str
)
14853 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
14854 strcpy(str
, "PCI Express");
14856 } else if (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) {
14857 u32 clock_ctrl
= tr32(TG3PCI_CLOCK_CTRL
) & 0x1f;
14859 strcpy(str
, "PCIX:");
14861 if ((clock_ctrl
== 7) ||
14862 ((tr32(GRC_MISC_CFG
) & GRC_MISC_CFG_BOARD_ID_MASK
) ==
14863 GRC_MISC_CFG_BOARD_ID_5704CIOBE
))
14864 strcat(str
, "133MHz");
14865 else if (clock_ctrl
== 0)
14866 strcat(str
, "33MHz");
14867 else if (clock_ctrl
== 2)
14868 strcat(str
, "50MHz");
14869 else if (clock_ctrl
== 4)
14870 strcat(str
, "66MHz");
14871 else if (clock_ctrl
== 6)
14872 strcat(str
, "100MHz");
14874 strcpy(str
, "PCI:");
14875 if (tp
->tg3_flags
& TG3_FLAG_PCI_HIGH_SPEED
)
14876 strcat(str
, "66MHz");
14878 strcat(str
, "33MHz");
14880 if (tp
->tg3_flags
& TG3_FLAG_PCI_32BIT
)
14881 strcat(str
, ":32-bit");
14883 strcat(str
, ":64-bit");
14887 static struct pci_dev
* __devinit
tg3_find_peer(struct tg3
*tp
)
14889 struct pci_dev
*peer
;
14890 unsigned int func
, devnr
= tp
->pdev
->devfn
& ~7;
14892 for (func
= 0; func
< 8; func
++) {
14893 peer
= pci_get_slot(tp
->pdev
->bus
, devnr
| func
);
14894 if (peer
&& peer
!= tp
->pdev
)
14898 /* 5704 can be configured in single-port mode, set peer to
14899 * tp->pdev in that case.
14907 * We don't need to keep the refcount elevated; there's no way
14908 * to remove one half of this device without removing the other
14915 static void __devinit
tg3_init_coal(struct tg3
*tp
)
14917 struct ethtool_coalesce
*ec
= &tp
->coal
;
14919 memset(ec
, 0, sizeof(*ec
));
14920 ec
->cmd
= ETHTOOL_GCOALESCE
;
14921 ec
->rx_coalesce_usecs
= LOW_RXCOL_TICKS
;
14922 ec
->tx_coalesce_usecs
= LOW_TXCOL_TICKS
;
14923 ec
->rx_max_coalesced_frames
= LOW_RXMAX_FRAMES
;
14924 ec
->tx_max_coalesced_frames
= LOW_TXMAX_FRAMES
;
14925 ec
->rx_coalesce_usecs_irq
= DEFAULT_RXCOAL_TICK_INT
;
14926 ec
->tx_coalesce_usecs_irq
= DEFAULT_TXCOAL_TICK_INT
;
14927 ec
->rx_max_coalesced_frames_irq
= DEFAULT_RXCOAL_MAXF_INT
;
14928 ec
->tx_max_coalesced_frames_irq
= DEFAULT_TXCOAL_MAXF_INT
;
14929 ec
->stats_block_coalesce_usecs
= DEFAULT_STAT_COAL_TICKS
;
14931 if (tp
->coalesce_mode
& (HOSTCC_MODE_CLRTICK_RXBD
|
14932 HOSTCC_MODE_CLRTICK_TXBD
)) {
14933 ec
->rx_coalesce_usecs
= LOW_RXCOL_TICKS_CLRTCKS
;
14934 ec
->rx_coalesce_usecs_irq
= DEFAULT_RXCOAL_TICK_INT_CLRTCKS
;
14935 ec
->tx_coalesce_usecs
= LOW_TXCOL_TICKS_CLRTCKS
;
14936 ec
->tx_coalesce_usecs_irq
= DEFAULT_TXCOAL_TICK_INT_CLRTCKS
;
14939 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
14940 ec
->rx_coalesce_usecs_irq
= 0;
14941 ec
->tx_coalesce_usecs_irq
= 0;
14942 ec
->stats_block_coalesce_usecs
= 0;
14946 static const struct net_device_ops tg3_netdev_ops
= {
14947 .ndo_open
= tg3_open
,
14948 .ndo_stop
= tg3_close
,
14949 .ndo_start_xmit
= tg3_start_xmit
,
14950 .ndo_get_stats64
= tg3_get_stats64
,
14951 .ndo_validate_addr
= eth_validate_addr
,
14952 .ndo_set_multicast_list
= tg3_set_rx_mode
,
14953 .ndo_set_mac_address
= tg3_set_mac_addr
,
14954 .ndo_do_ioctl
= tg3_ioctl
,
14955 .ndo_tx_timeout
= tg3_tx_timeout
,
14956 .ndo_change_mtu
= tg3_change_mtu
,
14957 .ndo_fix_features
= tg3_fix_features
,
14958 #ifdef CONFIG_NET_POLL_CONTROLLER
14959 .ndo_poll_controller
= tg3_poll_controller
,
14963 static const struct net_device_ops tg3_netdev_ops_dma_bug
= {
14964 .ndo_open
= tg3_open
,
14965 .ndo_stop
= tg3_close
,
14966 .ndo_start_xmit
= tg3_start_xmit_dma_bug
,
14967 .ndo_get_stats64
= tg3_get_stats64
,
14968 .ndo_validate_addr
= eth_validate_addr
,
14969 .ndo_set_multicast_list
= tg3_set_rx_mode
,
14970 .ndo_set_mac_address
= tg3_set_mac_addr
,
14971 .ndo_do_ioctl
= tg3_ioctl
,
14972 .ndo_tx_timeout
= tg3_tx_timeout
,
14973 .ndo_change_mtu
= tg3_change_mtu
,
14974 #ifdef CONFIG_NET_POLL_CONTROLLER
14975 .ndo_poll_controller
= tg3_poll_controller
,
14979 static int __devinit
tg3_init_one(struct pci_dev
*pdev
,
14980 const struct pci_device_id
*ent
)
14982 struct net_device
*dev
;
14984 int i
, err
, pm_cap
;
14985 u32 sndmbx
, rcvmbx
, intmbx
;
14987 u64 dma_mask
, persist_dma_mask
;
14988 u32 hw_features
= 0;
14990 printk_once(KERN_INFO
"%s\n", version
);
14992 err
= pci_enable_device(pdev
);
14994 dev_err(&pdev
->dev
, "Cannot enable PCI device, aborting\n");
14998 err
= pci_request_regions(pdev
, DRV_MODULE_NAME
);
15000 dev_err(&pdev
->dev
, "Cannot obtain PCI resources, aborting\n");
15001 goto err_out_disable_pdev
;
15004 pci_set_master(pdev
);
15006 /* Find power-management capability. */
15007 pm_cap
= pci_find_capability(pdev
, PCI_CAP_ID_PM
);
15009 dev_err(&pdev
->dev
,
15010 "Cannot find Power Management capability, aborting\n");
15012 goto err_out_free_res
;
15015 dev
= alloc_etherdev_mq(sizeof(*tp
), TG3_IRQ_MAX_VECS
);
15017 dev_err(&pdev
->dev
, "Etherdev alloc failed, aborting\n");
15019 goto err_out_free_res
;
15022 SET_NETDEV_DEV(dev
, &pdev
->dev
);
15024 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
15026 tp
= netdev_priv(dev
);
15029 tp
->pm_cap
= pm_cap
;
15030 tp
->rx_mode
= TG3_DEF_RX_MODE
;
15031 tp
->tx_mode
= TG3_DEF_TX_MODE
;
15034 tp
->msg_enable
= tg3_debug
;
15036 tp
->msg_enable
= TG3_DEF_MSG_ENABLE
;
15038 /* The word/byte swap controls here control register access byte
15039 * swapping. DMA data byte swapping is controlled in the GRC_MODE
15042 tp
->misc_host_ctrl
=
15043 MISC_HOST_CTRL_MASK_PCI_INT
|
15044 MISC_HOST_CTRL_WORD_SWAP
|
15045 MISC_HOST_CTRL_INDIR_ACCESS
|
15046 MISC_HOST_CTRL_PCISTATE_RW
;
15048 /* The NONFRM (non-frame) byte/word swap controls take effect
15049 * on descriptor entries, anything which isn't packet data.
15051 * The StrongARM chips on the board (one for tx, one for rx)
15052 * are running in big-endian mode.
15054 tp
->grc_mode
= (GRC_MODE_WSWAP_DATA
| GRC_MODE_BSWAP_DATA
|
15055 GRC_MODE_WSWAP_NONFRM_DATA
);
15056 #ifdef __BIG_ENDIAN
15057 tp
->grc_mode
|= GRC_MODE_BSWAP_NONFRM_DATA
;
15059 spin_lock_init(&tp
->lock
);
15060 spin_lock_init(&tp
->indirect_lock
);
15061 INIT_WORK(&tp
->reset_task
, tg3_reset_task
);
15063 tp
->regs
= pci_ioremap_bar(pdev
, BAR_0
);
15065 dev_err(&pdev
->dev
, "Cannot map device registers, aborting\n");
15067 goto err_out_free_dev
;
15070 tp
->rx_pending
= TG3_DEF_RX_RING_PENDING
;
15071 tp
->rx_jumbo_pending
= TG3_DEF_RX_JUMBO_RING_PENDING
;
15073 dev
->ethtool_ops
= &tg3_ethtool_ops
;
15074 dev
->watchdog_timeo
= TG3_TX_TIMEOUT
;
15075 dev
->irq
= pdev
->irq
;
15077 err
= tg3_get_invariants(tp
);
15079 dev_err(&pdev
->dev
,
15080 "Problem fetching invariants of chip, aborting\n");
15081 goto err_out_iounmap
;
15084 if ((tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) &&
15085 !(tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
))
15086 dev
->netdev_ops
= &tg3_netdev_ops
;
15088 dev
->netdev_ops
= &tg3_netdev_ops_dma_bug
;
15091 /* The EPB bridge inside 5714, 5715, and 5780 and any
15092 * device behind the EPB cannot support DMA addresses > 40-bit.
15093 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
15094 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
15095 * do DMA address check in tg3_start_xmit().
15097 if (tp
->tg3_flags2
& TG3_FLG2_IS_5788
)
15098 persist_dma_mask
= dma_mask
= DMA_BIT_MASK(32);
15099 else if (tp
->tg3_flags
& TG3_FLAG_40BIT_DMA_BUG
) {
15100 persist_dma_mask
= dma_mask
= DMA_BIT_MASK(40);
15101 #ifdef CONFIG_HIGHMEM
15102 dma_mask
= DMA_BIT_MASK(64);
15105 persist_dma_mask
= dma_mask
= DMA_BIT_MASK(64);
15107 /* Configure DMA attributes. */
15108 if (dma_mask
> DMA_BIT_MASK(32)) {
15109 err
= pci_set_dma_mask(pdev
, dma_mask
);
15111 dev
->features
|= NETIF_F_HIGHDMA
;
15112 err
= pci_set_consistent_dma_mask(pdev
,
15115 dev_err(&pdev
->dev
, "Unable to obtain 64 bit "
15116 "DMA for consistent allocations\n");
15117 goto err_out_iounmap
;
15121 if (err
|| dma_mask
== DMA_BIT_MASK(32)) {
15122 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
15124 dev_err(&pdev
->dev
,
15125 "No usable DMA configuration, aborting\n");
15126 goto err_out_iounmap
;
15130 tg3_init_bufmgr_config(tp
);
15132 /* Selectively allow TSO based on operating conditions */
15133 if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO
) ||
15134 (tp
->fw_needed
&& !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)))
15135 tp
->tg3_flags2
|= TG3_FLG2_TSO_CAPABLE
;
15137 tp
->tg3_flags2
&= ~(TG3_FLG2_TSO_CAPABLE
| TG3_FLG2_TSO_BUG
);
15138 tp
->fw_needed
= NULL
;
15141 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
)
15142 tp
->fw_needed
= FIRMWARE_TG3
;
15144 /* TSO is on by default on chips that support hardware TSO.
15145 * Firmware TSO on older chips gives lower performance, so it
15146 * is off by default, but can be enabled using ethtool.
15148 if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO
) &&
15149 (dev
->features
& NETIF_F_IP_CSUM
))
15150 hw_features
|= NETIF_F_TSO
;
15151 if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO_2
) ||
15152 (tp
->tg3_flags2
& TG3_FLG2_HW_TSO_3
)) {
15153 if (dev
->features
& NETIF_F_IPV6_CSUM
)
15154 hw_features
|= NETIF_F_TSO6
;
15155 if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO_3
) ||
15156 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
15157 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
15158 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
) ||
15159 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
15160 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
15161 hw_features
|= NETIF_F_TSO_ECN
;
15164 dev
->hw_features
|= hw_features
;
15165 dev
->features
|= hw_features
;
15166 dev
->vlan_features
|= hw_features
;
15168 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A1
&&
15169 !(tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) &&
15170 !(tr32(TG3PCI_PCISTATE
) & PCISTATE_BUS_SPEED_HIGH
)) {
15171 tp
->tg3_flags2
|= TG3_FLG2_MAX_RXPEND_64
;
15172 tp
->rx_pending
= 63;
15175 err
= tg3_get_device_address(tp
);
15177 dev_err(&pdev
->dev
,
15178 "Could not obtain valid ethernet address, aborting\n");
15179 goto err_out_iounmap
;
15182 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
15183 tp
->aperegs
= pci_ioremap_bar(pdev
, BAR_2
);
15184 if (!tp
->aperegs
) {
15185 dev_err(&pdev
->dev
,
15186 "Cannot map APE registers, aborting\n");
15188 goto err_out_iounmap
;
15191 tg3_ape_lock_init(tp
);
15193 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)
15194 tg3_read_dash_ver(tp
);
15198 * Reset chip in case UNDI or EFI driver did not shutdown
15199 * DMA self test will enable WDMAC and we'll see (spurious)
15200 * pending DMA on the PCI bus at that point.
15202 if ((tr32(HOSTCC_MODE
) & HOSTCC_MODE_ENABLE
) ||
15203 (tr32(WDMAC_MODE
) & WDMAC_MODE_ENABLE
)) {
15204 tw32(MEMARB_MODE
, MEMARB_MODE_ENABLE
);
15205 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
15208 err
= tg3_test_dma(tp
);
15210 dev_err(&pdev
->dev
, "DMA engine test failed, aborting\n");
15211 goto err_out_apeunmap
;
15214 intmbx
= MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
;
15215 rcvmbx
= MAILBOX_RCVRET_CON_IDX_0
+ TG3_64BIT_REG_LOW
;
15216 sndmbx
= MAILBOX_SNDHOST_PROD_IDX_0
+ TG3_64BIT_REG_LOW
;
15217 for (i
= 0; i
< tp
->irq_max
; i
++) {
15218 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
15221 tnapi
->tx_pending
= TG3_DEF_TX_RING_PENDING
;
15223 tnapi
->int_mbox
= intmbx
;
15229 tnapi
->consmbox
= rcvmbx
;
15230 tnapi
->prodmbox
= sndmbx
;
15233 tnapi
->coal_now
= HOSTCC_MODE_COAL_VEC1_NOW
<< (i
- 1);
15235 tnapi
->coal_now
= HOSTCC_MODE_NOW
;
15237 if (!(tp
->tg3_flags
& TG3_FLAG_SUPPORT_MSIX
))
15241 * If we support MSIX, we'll be using RSS. If we're using
15242 * RSS, the first vector only handles link interrupts and the
15243 * remaining vectors handle rx and tx interrupts. Reuse the
15244 * mailbox values for the next iteration. The values we setup
15245 * above are still useful for the single vectored mode.
15260 pci_set_drvdata(pdev
, dev
);
15262 err
= register_netdev(dev
);
15264 dev_err(&pdev
->dev
, "Cannot register net device, aborting\n");
15265 goto err_out_apeunmap
;
15268 netdev_info(dev
, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
15269 tp
->board_part_number
,
15270 tp
->pci_chip_rev_id
,
15271 tg3_bus_string(tp
, str
),
15274 if (tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
) {
15275 struct phy_device
*phydev
;
15276 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
15278 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
15279 phydev
->drv
->name
, dev_name(&phydev
->dev
));
15283 if (tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
)
15284 ethtype
= "10/100Base-TX";
15285 else if (tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
)
15286 ethtype
= "1000Base-SX";
15288 ethtype
= "10/100/1000Base-T";
15290 netdev_info(dev
, "attached PHY is %s (%s Ethernet) "
15291 "(WireSpeed[%d])\n", tg3_phy_string(tp
), ethtype
,
15292 (tp
->phy_flags
& TG3_PHYFLG_NO_ETH_WIRE_SPEED
) == 0);
15295 netdev_info(dev
, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
15296 (dev
->features
& NETIF_F_RXCSUM
) != 0,
15297 (tp
->tg3_flags
& TG3_FLAG_USE_LINKCHG_REG
) != 0,
15298 (tp
->phy_flags
& TG3_PHYFLG_USE_MI_INTERRUPT
) != 0,
15299 (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) != 0,
15300 (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) != 0);
15301 netdev_info(dev
, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
15303 pdev
->dma_mask
== DMA_BIT_MASK(32) ? 32 :
15304 ((u64
)pdev
->dma_mask
) == DMA_BIT_MASK(40) ? 40 : 64);
15310 iounmap(tp
->aperegs
);
15311 tp
->aperegs
= NULL
;
15324 pci_release_regions(pdev
);
15326 err_out_disable_pdev
:
15327 pci_disable_device(pdev
);
15328 pci_set_drvdata(pdev
, NULL
);
15332 static void __devexit
tg3_remove_one(struct pci_dev
*pdev
)
15334 struct net_device
*dev
= pci_get_drvdata(pdev
);
15337 struct tg3
*tp
= netdev_priv(dev
);
15340 release_firmware(tp
->fw
);
15342 cancel_work_sync(&tp
->reset_task
);
15344 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
15349 unregister_netdev(dev
);
15351 iounmap(tp
->aperegs
);
15352 tp
->aperegs
= NULL
;
15359 pci_release_regions(pdev
);
15360 pci_disable_device(pdev
);
15361 pci_set_drvdata(pdev
, NULL
);
15365 #ifdef CONFIG_PM_SLEEP
15366 static int tg3_suspend(struct device
*device
)
15368 struct pci_dev
*pdev
= to_pci_dev(device
);
15369 struct net_device
*dev
= pci_get_drvdata(pdev
);
15370 struct tg3
*tp
= netdev_priv(dev
);
15373 if (!netif_running(dev
))
15376 flush_work_sync(&tp
->reset_task
);
15378 tg3_netif_stop(tp
);
15380 del_timer_sync(&tp
->timer
);
15382 tg3_full_lock(tp
, 1);
15383 tg3_disable_ints(tp
);
15384 tg3_full_unlock(tp
);
15386 netif_device_detach(dev
);
15388 tg3_full_lock(tp
, 0);
15389 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
15390 tp
->tg3_flags
&= ~TG3_FLAG_INIT_COMPLETE
;
15391 tg3_full_unlock(tp
);
15393 err
= tg3_power_down_prepare(tp
);
15397 tg3_full_lock(tp
, 0);
15399 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
15400 err2
= tg3_restart_hw(tp
, 1);
15404 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
15405 add_timer(&tp
->timer
);
15407 netif_device_attach(dev
);
15408 tg3_netif_start(tp
);
15411 tg3_full_unlock(tp
);
15420 static int tg3_resume(struct device
*device
)
15422 struct pci_dev
*pdev
= to_pci_dev(device
);
15423 struct net_device
*dev
= pci_get_drvdata(pdev
);
15424 struct tg3
*tp
= netdev_priv(dev
);
15427 if (!netif_running(dev
))
15430 netif_device_attach(dev
);
15432 tg3_full_lock(tp
, 0);
15434 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
15435 err
= tg3_restart_hw(tp
, 1);
15439 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
15440 add_timer(&tp
->timer
);
15442 tg3_netif_start(tp
);
15445 tg3_full_unlock(tp
);
15453 static SIMPLE_DEV_PM_OPS(tg3_pm_ops
, tg3_suspend
, tg3_resume
);
15454 #define TG3_PM_OPS (&tg3_pm_ops)
15458 #define TG3_PM_OPS NULL
15460 #endif /* CONFIG_PM_SLEEP */
15462 static struct pci_driver tg3_driver
= {
15463 .name
= DRV_MODULE_NAME
,
15464 .id_table
= tg3_pci_tbl
,
15465 .probe
= tg3_init_one
,
15466 .remove
= __devexit_p(tg3_remove_one
),
15467 .driver
.pm
= TG3_PM_OPS
,
15470 static int __init
tg3_init(void)
15472 return pci_register_driver(&tg3_driver
);
15475 static void __exit
tg3_cleanup(void)
15477 pci_unregister_driver(&tg3_driver
);
15480 module_init(tg3_init
);
15481 module_exit(tg3_cleanup
);