projects / deliverable / linux.git / blob
? search:


939574c571f7d300fc0017f74603f396c052aff8
[deliverable/linux.git] / drivers / net / tg3.c
1 /*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2009 Broadcom Corporation.
8 *
9 * Firmware is:
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
16 */
17
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/compiler.h>
24 #include <linux/slab.h>
25 #include <linux/delay.h>
26 #include <linux/in.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/phy.h>
36 #include <linux/brcmphy.h>
37 #include <linux/if_vlan.h>
38 #include <linux/ip.h>
39 #include <linux/tcp.h>
40 #include <linux/workqueue.h>
41 #include <linux/prefetch.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/firmware.h>
44
45 #include <net/checksum.h>
46 #include <net/ip.h>
47
48 #include <asm/system.h>
49 #include <asm/io.h>
50 #include <asm/byteorder.h>
51 #include <asm/uaccess.h>
52
53 #ifdef CONFIG_SPARC
54 #include <asm/idprom.h>
55 #include <asm/prom.h>
56 #endif
57
58 #define BAR_0 0
59 #define BAR_2 2
60
61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62 #define TG3_VLAN_TAG_USED 1
63 #else
64 #define TG3_VLAN_TAG_USED 0
65 #endif
66
67 #include "tg3.h"
68
69 #define DRV_MODULE_NAME "tg3"
70 #define PFX DRV_MODULE_NAME ": "
71 #define DRV_MODULE_VERSION "3.100"
72 #define DRV_MODULE_RELDATE "August 25, 2009"
73
74 #define TG3_DEF_MAC_MODE 0
75 #define TG3_DEF_RX_MODE 0
76 #define TG3_DEF_TX_MODE 0
77 #define TG3_DEF_MSG_ENABLE \
78 (NETIF_MSG_DRV | \
79 NETIF_MSG_PROBE | \
80 NETIF_MSG_LINK | \
81 NETIF_MSG_TIMER | \
82 NETIF_MSG_IFDOWN | \
83 NETIF_MSG_IFUP | \
84 NETIF_MSG_RX_ERR | \
85 NETIF_MSG_TX_ERR)
86
87 /* length of time before we decide the hardware is borked,
88 * and dev->tx_timeout() should be called to fix the problem
89 */
90 #define TG3_TX_TIMEOUT (5 * HZ)
91
92 /* hardware minimum and maximum for a single frame's data payload */
93 #define TG3_MIN_MTU 60
94 #define TG3_MAX_MTU(tp) \
95 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
96
97 /* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place
99 * them in the NIC onboard memory.
100 */
101 #define TG3_RX_RING_SIZE 512
102 #define TG3_DEF_RX_RING_PENDING 200
103 #define TG3_RX_JUMBO_RING_SIZE 256
104 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
105
106 /* Do not place this n-ring entries value into the tp struct itself,
107 * we really want to expose these constants to GCC so that modulo et
108 * al. operations are done with shifts and masks instead of with
109 * hw multiply/modulo instructions. Another solution would be to
110 * replace things like '% foo' with '& (foo - 1)'.
111 */
112 #define TG3_RX_RCB_RING_SIZE(tp) \
113 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
114
115 #define TG3_TX_RING_SIZE 512
116 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
117
118 #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
119 TG3_RX_RING_SIZE)
120 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
121 TG3_RX_JUMBO_RING_SIZE)
122 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
123 TG3_RX_RCB_RING_SIZE(tp))
124 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
125 TG3_TX_RING_SIZE)
126 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
127
128 #define TG3_DMA_BYTE_ENAB 64
129
130 #define TG3_RX_STD_DMA_SZ 1536
131 #define TG3_RX_JMB_DMA_SZ 9046
132
133 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
134
135 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
136 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
137
138 /* minimum number of free TX descriptors required to wake up TX process */
139 #define TG3_TX_WAKEUP_THRESH(tp) ((tp)->tx_pending / 4)
140
141 #define TG3_RAW_IP_ALIGN 2
142
143 /* number of ETHTOOL_GSTATS u64's */
144 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
145
146 #define TG3_NUM_TEST 6
147
148 #define FIRMWARE_TG3 "tigon/tg3.bin"
149 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
150 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
151
152 static char version[] __devinitdata =
153 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
154
155 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
156 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
157 MODULE_LICENSE("GPL");
158 MODULE_VERSION(DRV_MODULE_VERSION);
159 MODULE_FIRMWARE(FIRMWARE_TG3);
160 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
161 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
162
163
164 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
165 module_param(tg3_debug, int, 0);
166 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
167
168 static struct pci_device_id tg3_pci_tbl[] = {
169 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
170 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
171 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
235 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
236 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
237 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
238 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
239 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
240 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
241 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
242 {}
243 };
244
245 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
246
247 static const struct {
248 const char string[ETH_GSTRING_LEN];
249 } ethtool_stats_keys[TG3_NUM_STATS] = {
250 { "rx_octets" },
251 { "rx_fragments" },
252 { "rx_ucast_packets" },
253 { "rx_mcast_packets" },
254 { "rx_bcast_packets" },
255 { "rx_fcs_errors" },
256 { "rx_align_errors" },
257 { "rx_xon_pause_rcvd" },
258 { "rx_xoff_pause_rcvd" },
259 { "rx_mac_ctrl_rcvd" },
260 { "rx_xoff_entered" },
261 { "rx_frame_too_long_errors" },
262 { "rx_jabbers" },
263 { "rx_undersize_packets" },
264 { "rx_in_length_errors" },
265 { "rx_out_length_errors" },
266 { "rx_64_or_less_octet_packets" },
267 { "rx_65_to_127_octet_packets" },
268 { "rx_128_to_255_octet_packets" },
269 { "rx_256_to_511_octet_packets" },
270 { "rx_512_to_1023_octet_packets" },
271 { "rx_1024_to_1522_octet_packets" },
272 { "rx_1523_to_2047_octet_packets" },
273 { "rx_2048_to_4095_octet_packets" },
274 { "rx_4096_to_8191_octet_packets" },
275 { "rx_8192_to_9022_octet_packets" },
276
277 { "tx_octets" },
278 { "tx_collisions" },
279
280 { "tx_xon_sent" },
281 { "tx_xoff_sent" },
282 { "tx_flow_control" },
283 { "tx_mac_errors" },
284 { "tx_single_collisions" },
285 { "tx_mult_collisions" },
286 { "tx_deferred" },
287 { "tx_excessive_collisions" },
288 { "tx_late_collisions" },
289 { "tx_collide_2times" },
290 { "tx_collide_3times" },
291 { "tx_collide_4times" },
292 { "tx_collide_5times" },
293 { "tx_collide_6times" },
294 { "tx_collide_7times" },
295 { "tx_collide_8times" },
296 { "tx_collide_9times" },
297 { "tx_collide_10times" },
298 { "tx_collide_11times" },
299 { "tx_collide_12times" },
300 { "tx_collide_13times" },
301 { "tx_collide_14times" },
302 { "tx_collide_15times" },
303 { "tx_ucast_packets" },
304 { "tx_mcast_packets" },
305 { "tx_bcast_packets" },
306 { "tx_carrier_sense_errors" },
307 { "tx_discards" },
308 { "tx_errors" },
309
310 { "dma_writeq_full" },
311 { "dma_write_prioq_full" },
312 { "rxbds_empty" },
313 { "rx_discards" },
314 { "rx_errors" },
315 { "rx_threshold_hit" },
316
317 { "dma_readq_full" },
318 { "dma_read_prioq_full" },
319 { "tx_comp_queue_full" },
320
321 { "ring_set_send_prod_index" },
322 { "ring_status_update" },
323 { "nic_irqs" },
324 { "nic_avoided_irqs" },
325 { "nic_tx_threshold_hit" }
326 };
327
328 static const struct {
329 const char string[ETH_GSTRING_LEN];
330 } ethtool_test_keys[TG3_NUM_TEST] = {
331 { "nvram test (online) " },
332 { "link test (online) " },
333 { "register test (offline)" },
334 { "memory test (offline)" },
335 { "loopback test (offline)" },
336 { "interrupt test (offline)" },
337 };
338
339 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
340 {
341 writel(val, tp->regs + off);
342 }
343
344 static u32 tg3_read32(struct tg3 *tp, u32 off)
345 {
346 return (readl(tp->regs + off));
347 }
348
349 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
350 {
351 writel(val, tp->aperegs + off);
352 }
353
354 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
355 {
356 return (readl(tp->aperegs + off));
357 }
358
359 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
360 {
361 unsigned long flags;
362
363 spin_lock_irqsave(&tp->indirect_lock, flags);
364 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
365 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
366 spin_unlock_irqrestore(&tp->indirect_lock, flags);
367 }
368
369 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
370 {
371 writel(val, tp->regs + off);
372 readl(tp->regs + off);
373 }
374
375 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
376 {
377 unsigned long flags;
378 u32 val;
379
380 spin_lock_irqsave(&tp->indirect_lock, flags);
381 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
382 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
383 spin_unlock_irqrestore(&tp->indirect_lock, flags);
384 return val;
385 }
386
387 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
388 {
389 unsigned long flags;
390
391 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
392 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
393 TG3_64BIT_REG_LOW, val);
394 return;
395 }
396 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
397 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
398 TG3_64BIT_REG_LOW, val);
399 return;
400 }
401
402 spin_lock_irqsave(&tp->indirect_lock, flags);
403 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
404 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
405 spin_unlock_irqrestore(&tp->indirect_lock, flags);
406
407 /* In indirect mode when disabling interrupts, we also need
408 * to clear the interrupt bit in the GRC local ctrl register.
409 */
410 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
411 (val == 0x1)) {
412 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
413 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
414 }
415 }
416
417 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
418 {
419 unsigned long flags;
420 u32 val;
421
422 spin_lock_irqsave(&tp->indirect_lock, flags);
423 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
424 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
425 spin_unlock_irqrestore(&tp->indirect_lock, flags);
426 return val;
427 }
428
429 /* usec_wait specifies the wait time in usec when writing to certain registers
430 * where it is unsafe to read back the register without some delay.
431 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
432 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
433 */
434 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
435 {
436 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
437 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
438 /* Non-posted methods */
439 tp->write32(tp, off, val);
440 else {
441 /* Posted method */
442 tg3_write32(tp, off, val);
443 if (usec_wait)
444 udelay(usec_wait);
445 tp->read32(tp, off);
446 }
447 /* Wait again after the read for the posted method to guarantee that
448 * the wait time is met.
449 */
450 if (usec_wait)
451 udelay(usec_wait);
452 }
453
454 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
455 {
456 tp->write32_mbox(tp, off, val);
457 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
458 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
459 tp->read32_mbox(tp, off);
460 }
461
462 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
463 {
464 void __iomem *mbox = tp->regs + off;
465 writel(val, mbox);
466 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
467 writel(val, mbox);
468 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
469 readl(mbox);
470 }
471
472 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
473 {
474 return (readl(tp->regs + off + GRCMBOX_BASE));
475 }
476
477 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
478 {
479 writel(val, tp->regs + off + GRCMBOX_BASE);
480 }
481
482 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
483 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
484 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
485 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
486 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
487
488 #define tw32(reg,val) tp->write32(tp, reg, val)
489 #define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
490 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
491 #define tr32(reg) tp->read32(tp, reg)
492
493 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
494 {
495 unsigned long flags;
496
497 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
498 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
499 return;
500
501 spin_lock_irqsave(&tp->indirect_lock, flags);
502 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
503 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
504 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
505
506 /* Always leave this as zero. */
507 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
508 } else {
509 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
510 tw32_f(TG3PCI_MEM_WIN_DATA, val);
511
512 /* Always leave this as zero. */
513 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
514 }
515 spin_unlock_irqrestore(&tp->indirect_lock, flags);
516 }
517
518 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
519 {
520 unsigned long flags;
521
522 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
523 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
524 *val = 0;
525 return;
526 }
527
528 spin_lock_irqsave(&tp->indirect_lock, flags);
529 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
530 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
531 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
532
533 /* Always leave this as zero. */
534 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
535 } else {
536 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
537 *val = tr32(TG3PCI_MEM_WIN_DATA);
538
539 /* Always leave this as zero. */
540 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
541 }
542 spin_unlock_irqrestore(&tp->indirect_lock, flags);
543 }
544
545 static void tg3_ape_lock_init(struct tg3 *tp)
546 {
547 int i;
548
549 /* Make sure the driver hasn't any stale locks. */
550 for (i = 0; i < 8; i++)
551 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
552 APE_LOCK_GRANT_DRIVER);
553 }
554
555 static int tg3_ape_lock(struct tg3 *tp, int locknum)
556 {
557 int i, off;
558 int ret = 0;
559 u32 status;
560
561 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
562 return 0;
563
564 switch (locknum) {
565 case TG3_APE_LOCK_GRC:
566 case TG3_APE_LOCK_MEM:
567 break;
568 default:
569 return -EINVAL;
570 }
571
572 off = 4 * locknum;
573
574 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
575
576 /* Wait for up to 1 millisecond to acquire lock. */
577 for (i = 0; i < 100; i++) {
578 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
579 if (status == APE_LOCK_GRANT_DRIVER)
580 break;
581 udelay(10);
582 }
583
584 if (status != APE_LOCK_GRANT_DRIVER) {
585 /* Revoke the lock request. */
586 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
587 APE_LOCK_GRANT_DRIVER);
588
589 ret = -EBUSY;
590 }
591
592 return ret;
593 }
594
595 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
596 {
597 int off;
598
599 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
600 return;
601
602 switch (locknum) {
603 case TG3_APE_LOCK_GRC:
604 case TG3_APE_LOCK_MEM:
605 break;
606 default:
607 return;
608 }
609
610 off = 4 * locknum;
611 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
612 }
613
614 static void tg3_disable_ints(struct tg3 *tp)
615 {
616 tw32(TG3PCI_MISC_HOST_CTRL,
617 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
618 tw32_mailbox_f(tp->napi[0].int_mbox, 0x00000001);
619 }
620
621 static inline void tg3_cond_int(struct tg3 *tp)
622 {
623 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
624 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
625 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
626 else
627 tw32(HOSTCC_MODE, tp->coalesce_mode |
628 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
629 }
630
631 static void tg3_enable_ints(struct tg3 *tp)
632 {
633 struct tg3_napi *tnapi = &tp->napi[0];
634 tp->irq_sync = 0;
635 wmb();
636
637 tw32(TG3PCI_MISC_HOST_CTRL,
638 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
639 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
640 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
641 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
642 tg3_cond_int(tp);
643 }
644
645 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
646 {
647 struct tg3 *tp = tnapi->tp;
648 struct tg3_hw_status *sblk = tnapi->hw_status;
649 unsigned int work_exists = 0;
650
651 /* check for phy events */
652 if (!(tp->tg3_flags &
653 (TG3_FLAG_USE_LINKCHG_REG |
654 TG3_FLAG_POLL_SERDES))) {
655 if (sblk->status & SD_STATUS_LINK_CHG)
656 work_exists = 1;
657 }
658 /* check for RX/TX work to do */
659 if (sblk->idx[0].tx_consumer != tp->tx_cons ||
660 sblk->idx[0].rx_producer != tnapi->rx_rcb_ptr)
661 work_exists = 1;
662
663 return work_exists;
664 }
665
666 /* tg3_int_reenable
667 * similar to tg3_enable_ints, but it accurately determines whether there
668 * is new work pending and can return without flushing the PIO write
669 * which reenables interrupts
670 */
671 static void tg3_int_reenable(struct tg3_napi *tnapi)
672 {
673 struct tg3 *tp = tnapi->tp;
674
675 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
676 mmiowb();
677
678 /* When doing tagged status, this work check is unnecessary.
679 * The last_tag we write above tells the chip which piece of
680 * work we've completed.
681 */
682 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
683 tg3_has_work(tnapi))
684 tw32(HOSTCC_MODE, tp->coalesce_mode |
685 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
686 }
687
688 static inline void tg3_netif_stop(struct tg3 *tp)
689 {
690 tp->dev->trans_start = jiffies; /* prevent tx timeout */
691 napi_disable(&tp->napi[0].napi);
692 netif_tx_disable(tp->dev);
693 }
694
695 static inline void tg3_netif_start(struct tg3 *tp)
696 {
697 struct tg3_napi *tnapi = &tp->napi[0];
698 netif_wake_queue(tp->dev);
699 /* NOTE: unconditional netif_wake_queue is only appropriate
700 * so long as all callers are assured to have free tx slots
701 * (such as after tg3_init_hw)
702 */
703 napi_enable(&tnapi->napi);
704 tnapi->hw_status->status |= SD_STATUS_UPDATED;
705 tg3_enable_ints(tp);
706 }
707
708 static void tg3_switch_clocks(struct tg3 *tp)
709 {
710 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
711 u32 orig_clock_ctrl;
712
713 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
714 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
715 return;
716
717 orig_clock_ctrl = clock_ctrl;
718 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
719 CLOCK_CTRL_CLKRUN_OENABLE |
720 0x1f);
721 tp->pci_clock_ctrl = clock_ctrl;
722
723 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
724 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
725 tw32_wait_f(TG3PCI_CLOCK_CTRL,
726 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
727 }
728 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
729 tw32_wait_f(TG3PCI_CLOCK_CTRL,
730 clock_ctrl |
731 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
732 40);
733 tw32_wait_f(TG3PCI_CLOCK_CTRL,
734 clock_ctrl | (CLOCK_CTRL_ALTCLK),
735 40);
736 }
737 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
738 }
739
740 #define PHY_BUSY_LOOPS 5000
741
742 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
743 {
744 u32 frame_val;
745 unsigned int loops;
746 int ret;
747
748 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
749 tw32_f(MAC_MI_MODE,
750 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
751 udelay(80);
752 }
753
754 *val = 0x0;
755
756 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
757 MI_COM_PHY_ADDR_MASK);
758 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
759 MI_COM_REG_ADDR_MASK);
760 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
761
762 tw32_f(MAC_MI_COM, frame_val);
763
764 loops = PHY_BUSY_LOOPS;
765 while (loops != 0) {
766 udelay(10);
767 frame_val = tr32(MAC_MI_COM);
768
769 if ((frame_val & MI_COM_BUSY) == 0) {
770 udelay(5);
771 frame_val = tr32(MAC_MI_COM);
772 break;
773 }
774 loops -= 1;
775 }
776
777 ret = -EBUSY;
778 if (loops != 0) {
779 *val = frame_val & MI_COM_DATA_MASK;
780 ret = 0;
781 }
782
783 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
784 tw32_f(MAC_MI_MODE, tp->mi_mode);
785 udelay(80);
786 }
787
788 return ret;
789 }
790
791 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
792 {
793 u32 frame_val;
794 unsigned int loops;
795 int ret;
796
797 if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
798 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
799 return 0;
800
801 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
802 tw32_f(MAC_MI_MODE,
803 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
804 udelay(80);
805 }
806
807 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
808 MI_COM_PHY_ADDR_MASK);
809 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
810 MI_COM_REG_ADDR_MASK);
811 frame_val |= (val & MI_COM_DATA_MASK);
812 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
813
814 tw32_f(MAC_MI_COM, frame_val);
815
816 loops = PHY_BUSY_LOOPS;
817 while (loops != 0) {
818 udelay(10);
819 frame_val = tr32(MAC_MI_COM);
820 if ((frame_val & MI_COM_BUSY) == 0) {
821 udelay(5);
822 frame_val = tr32(MAC_MI_COM);
823 break;
824 }
825 loops -= 1;
826 }
827
828 ret = -EBUSY;
829 if (loops != 0)
830 ret = 0;
831
832 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
833 tw32_f(MAC_MI_MODE, tp->mi_mode);
834 udelay(80);
835 }
836
837 return ret;
838 }
839
840 static int tg3_bmcr_reset(struct tg3 *tp)
841 {
842 u32 phy_control;
843 int limit, err;
844
845 /* OK, reset it, and poll the BMCR_RESET bit until it
846 * clears or we time out.
847 */
848 phy_control = BMCR_RESET;
849 err = tg3_writephy(tp, MII_BMCR, phy_control);
850 if (err != 0)
851 return -EBUSY;
852
853 limit = 5000;
854 while (limit--) {
855 err = tg3_readphy(tp, MII_BMCR, &phy_control);
856 if (err != 0)
857 return -EBUSY;
858
859 if ((phy_control & BMCR_RESET) == 0) {
860 udelay(40);
861 break;
862 }
863 udelay(10);
864 }
865 if (limit < 0)
866 return -EBUSY;
867
868 return 0;
869 }
870
871 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
872 {
873 struct tg3 *tp = bp->priv;
874 u32 val;
875
876 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
877 return -EAGAIN;
878
879 if (tg3_readphy(tp, reg, &val))
880 return -EIO;
881
882 return val;
883 }
884
885 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
886 {
887 struct tg3 *tp = bp->priv;
888
889 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
890 return -EAGAIN;
891
892 if (tg3_writephy(tp, reg, val))
893 return -EIO;
894
895 return 0;
896 }
897
898 static int tg3_mdio_reset(struct mii_bus *bp)
899 {
900 return 0;
901 }
902
903 static void tg3_mdio_config_5785(struct tg3 *tp)
904 {
905 u32 val;
906 struct phy_device *phydev;
907
908 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
909 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
910 case TG3_PHY_ID_BCM50610:
911 val = MAC_PHYCFG2_50610_LED_MODES;
912 break;
913 case TG3_PHY_ID_BCMAC131:
914 val = MAC_PHYCFG2_AC131_LED_MODES;
915 break;
916 case TG3_PHY_ID_RTL8211C:
917 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
918 break;
919 case TG3_PHY_ID_RTL8201E:
920 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
921 break;
922 default:
923 return;
924 }
925
926 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
927 tw32(MAC_PHYCFG2, val);
928
929 val = tr32(MAC_PHYCFG1);
930 val &= ~(MAC_PHYCFG1_RGMII_INT |
931 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
932 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
933 tw32(MAC_PHYCFG1, val);
934
935 return;
936 }
937
938 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
939 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
940 MAC_PHYCFG2_FMODE_MASK_MASK |
941 MAC_PHYCFG2_GMODE_MASK_MASK |
942 MAC_PHYCFG2_ACT_MASK_MASK |
943 MAC_PHYCFG2_QUAL_MASK_MASK |
944 MAC_PHYCFG2_INBAND_ENABLE;
945
946 tw32(MAC_PHYCFG2, val);
947
948 val = tr32(MAC_PHYCFG1);
949 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
950 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
951 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
952 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
953 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
954 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
955 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
956 }
957 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
958 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
959 tw32(MAC_PHYCFG1, val);
960
961 val = tr32(MAC_EXT_RGMII_MODE);
962 val &= ~(MAC_RGMII_MODE_RX_INT_B |
963 MAC_RGMII_MODE_RX_QUALITY |
964 MAC_RGMII_MODE_RX_ACTIVITY |
965 MAC_RGMII_MODE_RX_ENG_DET |
966 MAC_RGMII_MODE_TX_ENABLE |
967 MAC_RGMII_MODE_TX_LOWPWR |
968 MAC_RGMII_MODE_TX_RESET);
969 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
970 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
971 val |= MAC_RGMII_MODE_RX_INT_B |
972 MAC_RGMII_MODE_RX_QUALITY |
973 MAC_RGMII_MODE_RX_ACTIVITY |
974 MAC_RGMII_MODE_RX_ENG_DET;
975 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
976 val |= MAC_RGMII_MODE_TX_ENABLE |
977 MAC_RGMII_MODE_TX_LOWPWR |
978 MAC_RGMII_MODE_TX_RESET;
979 }
980 tw32(MAC_EXT_RGMII_MODE, val);
981 }
982
983 static void tg3_mdio_start(struct tg3 *tp)
984 {
985 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
986 mutex_lock(&tp->mdio_bus->mdio_lock);
987 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
988 mutex_unlock(&tp->mdio_bus->mdio_lock);
989 }
990
991 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
992 tw32_f(MAC_MI_MODE, tp->mi_mode);
993 udelay(80);
994
995 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
996 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
997 tg3_mdio_config_5785(tp);
998 }
999
1000 static void tg3_mdio_stop(struct tg3 *tp)
1001 {
1002 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1003 mutex_lock(&tp->mdio_bus->mdio_lock);
1004 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_PAUSED;
1005 mutex_unlock(&tp->mdio_bus->mdio_lock);
1006 }
1007 }
1008
1009 static int tg3_mdio_init(struct tg3 *tp)
1010 {
1011 int i;
1012 u32 reg;
1013 struct phy_device *phydev;
1014
1015 tg3_mdio_start(tp);
1016
1017 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1018 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1019 return 0;
1020
1021 tp->mdio_bus = mdiobus_alloc();
1022 if (tp->mdio_bus == NULL)
1023 return -ENOMEM;
1024
1025 tp->mdio_bus->name = "tg3 mdio bus";
1026 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1027 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1028 tp->mdio_bus->priv = tp;
1029 tp->mdio_bus->parent = &tp->pdev->dev;
1030 tp->mdio_bus->read = &tg3_mdio_read;
1031 tp->mdio_bus->write = &tg3_mdio_write;
1032 tp->mdio_bus->reset = &tg3_mdio_reset;
1033 tp->mdio_bus->phy_mask = ~(1 << PHY_ADDR);
1034 tp->mdio_bus->irq = &tp->mdio_irq[0];
1035
1036 for (i = 0; i < PHY_MAX_ADDR; i++)
1037 tp->mdio_bus->irq[i] = PHY_POLL;
1038
1039 /* The bus registration will look for all the PHYs on the mdio bus.
1040 * Unfortunately, it does not ensure the PHY is powered up before
1041 * accessing the PHY ID registers. A chip reset is the
1042 * quickest way to bring the device back to an operational state..
1043 */
1044 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1045 tg3_bmcr_reset(tp);
1046
1047 i = mdiobus_register(tp->mdio_bus);
1048 if (i) {
1049 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1050 tp->dev->name, i);
1051 mdiobus_free(tp->mdio_bus);
1052 return i;
1053 }
1054
1055 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1056
1057 if (!phydev || !phydev->drv) {
1058 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1059 mdiobus_unregister(tp->mdio_bus);
1060 mdiobus_free(tp->mdio_bus);
1061 return -ENODEV;
1062 }
1063
1064 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1065 case TG3_PHY_ID_BCM57780:
1066 phydev->interface = PHY_INTERFACE_MODE_GMII;
1067 break;
1068 case TG3_PHY_ID_BCM50610:
1069 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1070 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1071 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1072 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1073 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1074 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1075 /* fallthru */
1076 case TG3_PHY_ID_RTL8211C:
1077 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1078 break;
1079 case TG3_PHY_ID_RTL8201E:
1080 case TG3_PHY_ID_BCMAC131:
1081 phydev->interface = PHY_INTERFACE_MODE_MII;
1082 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
1083 break;
1084 }
1085
1086 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1087
1088 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1089 tg3_mdio_config_5785(tp);
1090
1091 return 0;
1092 }
1093
1094 static void tg3_mdio_fini(struct tg3 *tp)
1095 {
1096 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1097 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1098 mdiobus_unregister(tp->mdio_bus);
1099 mdiobus_free(tp->mdio_bus);
1100 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
1101 }
1102 }
1103
1104 /* tp->lock is held. */
1105 static inline void tg3_generate_fw_event(struct tg3 *tp)
1106 {
1107 u32 val;
1108
1109 val = tr32(GRC_RX_CPU_EVENT);
1110 val |= GRC_RX_CPU_DRIVER_EVENT;
1111 tw32_f(GRC_RX_CPU_EVENT, val);
1112
1113 tp->last_event_jiffies = jiffies;
1114 }
1115
1116 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1117
1118 /* tp->lock is held. */
1119 static void tg3_wait_for_event_ack(struct tg3 *tp)
1120 {
1121 int i;
1122 unsigned int delay_cnt;
1123 long time_remain;
1124
1125 /* If enough time has passed, no wait is necessary. */
1126 time_remain = (long)(tp->last_event_jiffies + 1 +
1127 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1128 (long)jiffies;
1129 if (time_remain < 0)
1130 return;
1131
1132 /* Check if we can shorten the wait time. */
1133 delay_cnt = jiffies_to_usecs(time_remain);
1134 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1135 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1136 delay_cnt = (delay_cnt >> 3) + 1;
1137
1138 for (i = 0; i < delay_cnt; i++) {
1139 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1140 break;
1141 udelay(8);
1142 }
1143 }
1144
1145 /* tp->lock is held. */
1146 static void tg3_ump_link_report(struct tg3 *tp)
1147 {
1148 u32 reg;
1149 u32 val;
1150
1151 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1152 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1153 return;
1154
1155 tg3_wait_for_event_ack(tp);
1156
1157 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1158
1159 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1160
1161 val = 0;
1162 if (!tg3_readphy(tp, MII_BMCR, &reg))
1163 val = reg << 16;
1164 if (!tg3_readphy(tp, MII_BMSR, &reg))
1165 val |= (reg & 0xffff);
1166 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1167
1168 val = 0;
1169 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1170 val = reg << 16;
1171 if (!tg3_readphy(tp, MII_LPA, &reg))
1172 val |= (reg & 0xffff);
1173 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1174
1175 val = 0;
1176 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1177 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1178 val = reg << 16;
1179 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1180 val |= (reg & 0xffff);
1181 }
1182 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1183
1184 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1185 val = reg << 16;
1186 else
1187 val = 0;
1188 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1189
1190 tg3_generate_fw_event(tp);
1191 }
1192
1193 static void tg3_link_report(struct tg3 *tp)
1194 {
1195 if (!netif_carrier_ok(tp->dev)) {
1196 if (netif_msg_link(tp))
1197 printk(KERN_INFO PFX "%s: Link is down.\n",
1198 tp->dev->name);
1199 tg3_ump_link_report(tp);
1200 } else if (netif_msg_link(tp)) {
1201 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1202 tp->dev->name,
1203 (tp->link_config.active_speed == SPEED_1000 ?
1204 1000 :
1205 (tp->link_config.active_speed == SPEED_100 ?
1206 100 : 10)),
1207 (tp->link_config.active_duplex == DUPLEX_FULL ?
1208 "full" : "half"));
1209
1210 printk(KERN_INFO PFX
1211 "%s: Flow control is %s for TX and %s for RX.\n",
1212 tp->dev->name,
1213 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1214 "on" : "off",
1215 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1216 "on" : "off");
1217 tg3_ump_link_report(tp);
1218 }
1219 }
1220
1221 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1222 {
1223 u16 miireg;
1224
1225 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1226 miireg = ADVERTISE_PAUSE_CAP;
1227 else if (flow_ctrl & FLOW_CTRL_TX)
1228 miireg = ADVERTISE_PAUSE_ASYM;
1229 else if (flow_ctrl & FLOW_CTRL_RX)
1230 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1231 else
1232 miireg = 0;
1233
1234 return miireg;
1235 }
1236
1237 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1238 {
1239 u16 miireg;
1240
1241 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1242 miireg = ADVERTISE_1000XPAUSE;
1243 else if (flow_ctrl & FLOW_CTRL_TX)
1244 miireg = ADVERTISE_1000XPSE_ASYM;
1245 else if (flow_ctrl & FLOW_CTRL_RX)
1246 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1247 else
1248 miireg = 0;
1249
1250 return miireg;
1251 }
1252
1253 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1254 {
1255 u8 cap = 0;
1256
1257 if (lcladv & ADVERTISE_1000XPAUSE) {
1258 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1259 if (rmtadv & LPA_1000XPAUSE)
1260 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1261 else if (rmtadv & LPA_1000XPAUSE_ASYM)
1262 cap = FLOW_CTRL_RX;
1263 } else {
1264 if (rmtadv & LPA_1000XPAUSE)
1265 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1266 }
1267 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1268 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1269 cap = FLOW_CTRL_TX;
1270 }
1271
1272 return cap;
1273 }
1274
1275 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1276 {
1277 u8 autoneg;
1278 u8 flowctrl = 0;
1279 u32 old_rx_mode = tp->rx_mode;
1280 u32 old_tx_mode = tp->tx_mode;
1281
1282 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1283 autoneg = tp->mdio_bus->phy_map[PHY_ADDR]->autoneg;
1284 else
1285 autoneg = tp->link_config.autoneg;
1286
1287 if (autoneg == AUTONEG_ENABLE &&
1288 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1289 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1290 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1291 else
1292 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1293 } else
1294 flowctrl = tp->link_config.flowctrl;
1295
1296 tp->link_config.active_flowctrl = flowctrl;
1297
1298 if (flowctrl & FLOW_CTRL_RX)
1299 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1300 else
1301 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1302
1303 if (old_rx_mode != tp->rx_mode)
1304 tw32_f(MAC_RX_MODE, tp->rx_mode);
1305
1306 if (flowctrl & FLOW_CTRL_TX)
1307 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1308 else
1309 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1310
1311 if (old_tx_mode != tp->tx_mode)
1312 tw32_f(MAC_TX_MODE, tp->tx_mode);
1313 }
1314
1315 static void tg3_adjust_link(struct net_device *dev)
1316 {
1317 u8 oldflowctrl, linkmesg = 0;
1318 u32 mac_mode, lcl_adv, rmt_adv;
1319 struct tg3 *tp = netdev_priv(dev);
1320 struct phy_device *phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1321
1322 spin_lock(&tp->lock);
1323
1324 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1325 MAC_MODE_HALF_DUPLEX);
1326
1327 oldflowctrl = tp->link_config.active_flowctrl;
1328
1329 if (phydev->link) {
1330 lcl_adv = 0;
1331 rmt_adv = 0;
1332
1333 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1334 mac_mode |= MAC_MODE_PORT_MODE_MII;
1335 else
1336 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1337
1338 if (phydev->duplex == DUPLEX_HALF)
1339 mac_mode |= MAC_MODE_HALF_DUPLEX;
1340 else {
1341 lcl_adv = tg3_advert_flowctrl_1000T(
1342 tp->link_config.flowctrl);
1343
1344 if (phydev->pause)
1345 rmt_adv = LPA_PAUSE_CAP;
1346 if (phydev->asym_pause)
1347 rmt_adv |= LPA_PAUSE_ASYM;
1348 }
1349
1350 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1351 } else
1352 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1353
1354 if (mac_mode != tp->mac_mode) {
1355 tp->mac_mode = mac_mode;
1356 tw32_f(MAC_MODE, tp->mac_mode);
1357 udelay(40);
1358 }
1359
1360 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1361 if (phydev->speed == SPEED_10)
1362 tw32(MAC_MI_STAT,
1363 MAC_MI_STAT_10MBPS_MODE |
1364 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1365 else
1366 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1367 }
1368
1369 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1370 tw32(MAC_TX_LENGTHS,
1371 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1372 (6 << TX_LENGTHS_IPG_SHIFT) |
1373 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1374 else
1375 tw32(MAC_TX_LENGTHS,
1376 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1377 (6 << TX_LENGTHS_IPG_SHIFT) |
1378 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1379
1380 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1381 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1382 phydev->speed != tp->link_config.active_speed ||
1383 phydev->duplex != tp->link_config.active_duplex ||
1384 oldflowctrl != tp->link_config.active_flowctrl)
1385 linkmesg = 1;
1386
1387 tp->link_config.active_speed = phydev->speed;
1388 tp->link_config.active_duplex = phydev->duplex;
1389
1390 spin_unlock(&tp->lock);
1391
1392 if (linkmesg)
1393 tg3_link_report(tp);
1394 }
1395
1396 static int tg3_phy_init(struct tg3 *tp)
1397 {
1398 struct phy_device *phydev;
1399
1400 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1401 return 0;
1402
1403 /* Bring the PHY back to a known state. */
1404 tg3_bmcr_reset(tp);
1405
1406 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1407
1408 /* Attach the MAC to the PHY. */
1409 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1410 phydev->dev_flags, phydev->interface);
1411 if (IS_ERR(phydev)) {
1412 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1413 return PTR_ERR(phydev);
1414 }
1415
1416 /* Mask with MAC supported features. */
1417 switch (phydev->interface) {
1418 case PHY_INTERFACE_MODE_GMII:
1419 case PHY_INTERFACE_MODE_RGMII:
1420 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1421 phydev->supported &= (PHY_GBIT_FEATURES |
1422 SUPPORTED_Pause |
1423 SUPPORTED_Asym_Pause);
1424 break;
1425 }
1426 /* fallthru */
1427 case PHY_INTERFACE_MODE_MII:
1428 phydev->supported &= (PHY_BASIC_FEATURES |
1429 SUPPORTED_Pause |
1430 SUPPORTED_Asym_Pause);
1431 break;
1432 default:
1433 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1434 return -EINVAL;
1435 }
1436
1437 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1438
1439 phydev->advertising = phydev->supported;
1440
1441 return 0;
1442 }
1443
1444 static void tg3_phy_start(struct tg3 *tp)
1445 {
1446 struct phy_device *phydev;
1447
1448 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1449 return;
1450
1451 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1452
1453 if (tp->link_config.phy_is_low_power) {
1454 tp->link_config.phy_is_low_power = 0;
1455 phydev->speed = tp->link_config.orig_speed;
1456 phydev->duplex = tp->link_config.orig_duplex;
1457 phydev->autoneg = tp->link_config.orig_autoneg;
1458 phydev->advertising = tp->link_config.orig_advertising;
1459 }
1460
1461 phy_start(phydev);
1462
1463 phy_start_aneg(phydev);
1464 }
1465
1466 static void tg3_phy_stop(struct tg3 *tp)
1467 {
1468 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1469 return;
1470
1471 phy_stop(tp->mdio_bus->phy_map[PHY_ADDR]);
1472 }
1473
1474 static void tg3_phy_fini(struct tg3 *tp)
1475 {
1476 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1477 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1478 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1479 }
1480 }
1481
1482 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1483 {
1484 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1485 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1486 }
1487
1488 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1489 {
1490 u32 phytest;
1491
1492 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1493 u32 phy;
1494
1495 tg3_writephy(tp, MII_TG3_FET_TEST,
1496 phytest | MII_TG3_FET_SHADOW_EN);
1497 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1498 if (enable)
1499 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1500 else
1501 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1502 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1503 }
1504 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1505 }
1506 }
1507
1508 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1509 {
1510 u32 reg;
1511
1512 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1513 return;
1514
1515 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1516 tg3_phy_fet_toggle_apd(tp, enable);
1517 return;
1518 }
1519
1520 reg = MII_TG3_MISC_SHDW_WREN |
1521 MII_TG3_MISC_SHDW_SCR5_SEL |
1522 MII_TG3_MISC_SHDW_SCR5_LPED |
1523 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1524 MII_TG3_MISC_SHDW_SCR5_SDTL |
1525 MII_TG3_MISC_SHDW_SCR5_C125OE;
1526 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1527 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1528
1529 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1530
1531
1532 reg = MII_TG3_MISC_SHDW_WREN |
1533 MII_TG3_MISC_SHDW_APD_SEL |
1534 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1535 if (enable)
1536 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1537
1538 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1539 }
1540
1541 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1542 {
1543 u32 phy;
1544
1545 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1546 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1547 return;
1548
1549 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1550 u32 ephy;
1551
1552 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1553 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1554
1555 tg3_writephy(tp, MII_TG3_FET_TEST,
1556 ephy | MII_TG3_FET_SHADOW_EN);
1557 if (!tg3_readphy(tp, reg, &phy)) {
1558 if (enable)
1559 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1560 else
1561 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1562 tg3_writephy(tp, reg, phy);
1563 }
1564 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1565 }
1566 } else {
1567 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1568 MII_TG3_AUXCTL_SHDWSEL_MISC;
1569 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1570 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1571 if (enable)
1572 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1573 else
1574 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1575 phy |= MII_TG3_AUXCTL_MISC_WREN;
1576 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1577 }
1578 }
1579 }
1580
1581 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1582 {
1583 u32 val;
1584
1585 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1586 return;
1587
1588 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1589 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1590 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1591 (val | (1 << 15) | (1 << 4)));
1592 }
1593
1594 static void tg3_phy_apply_otp(struct tg3 *tp)
1595 {
1596 u32 otp, phy;
1597
1598 if (!tp->phy_otp)
1599 return;
1600
1601 otp = tp->phy_otp;
1602
1603 /* Enable SM_DSP clock and tx 6dB coding. */
1604 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1605 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1606 MII_TG3_AUXCTL_ACTL_TX_6DB;
1607 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1608
1609 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1610 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1611 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1612
1613 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1614 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1615 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1616
1617 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1618 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1619 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1620
1621 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1622 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1623
1624 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1625 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1626
1627 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1628 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1629 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1630
1631 /* Turn off SM_DSP clock. */
1632 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1633 MII_TG3_AUXCTL_ACTL_TX_6DB;
1634 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1635 }
1636
1637 static int tg3_wait_macro_done(struct tg3 *tp)
1638 {
1639 int limit = 100;
1640
1641 while (limit--) {
1642 u32 tmp32;
1643
1644 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1645 if ((tmp32 & 0x1000) == 0)
1646 break;
1647 }
1648 }
1649 if (limit < 0)
1650 return -EBUSY;
1651
1652 return 0;
1653 }
1654
1655 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1656 {
1657 static const u32 test_pat[4][6] = {
1658 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1659 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1660 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1661 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1662 };
1663 int chan;
1664
1665 for (chan = 0; chan < 4; chan++) {
1666 int i;
1667
1668 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1669 (chan * 0x2000) | 0x0200);
1670 tg3_writephy(tp, 0x16, 0x0002);
1671
1672 for (i = 0; i < 6; i++)
1673 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1674 test_pat[chan][i]);
1675
1676 tg3_writephy(tp, 0x16, 0x0202);
1677 if (tg3_wait_macro_done(tp)) {
1678 *resetp = 1;
1679 return -EBUSY;
1680 }
1681
1682 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1683 (chan * 0x2000) | 0x0200);
1684 tg3_writephy(tp, 0x16, 0x0082);
1685 if (tg3_wait_macro_done(tp)) {
1686 *resetp = 1;
1687 return -EBUSY;
1688 }
1689
1690 tg3_writephy(tp, 0x16, 0x0802);
1691 if (tg3_wait_macro_done(tp)) {
1692 *resetp = 1;
1693 return -EBUSY;
1694 }
1695
1696 for (i = 0; i < 6; i += 2) {
1697 u32 low, high;
1698
1699 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1700 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1701 tg3_wait_macro_done(tp)) {
1702 *resetp = 1;
1703 return -EBUSY;
1704 }
1705 low &= 0x7fff;
1706 high &= 0x000f;
1707 if (low != test_pat[chan][i] ||
1708 high != test_pat[chan][i+1]) {
1709 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1710 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1711 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1712
1713 return -EBUSY;
1714 }
1715 }
1716 }
1717
1718 return 0;
1719 }
1720
1721 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1722 {
1723 int chan;
1724
1725 for (chan = 0; chan < 4; chan++) {
1726 int i;
1727
1728 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1729 (chan * 0x2000) | 0x0200);
1730 tg3_writephy(tp, 0x16, 0x0002);
1731 for (i = 0; i < 6; i++)
1732 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1733 tg3_writephy(tp, 0x16, 0x0202);
1734 if (tg3_wait_macro_done(tp))
1735 return -EBUSY;
1736 }
1737
1738 return 0;
1739 }
1740
1741 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1742 {
1743 u32 reg32, phy9_orig;
1744 int retries, do_phy_reset, err;
1745
1746 retries = 10;
1747 do_phy_reset = 1;
1748 do {
1749 if (do_phy_reset) {
1750 err = tg3_bmcr_reset(tp);
1751 if (err)
1752 return err;
1753 do_phy_reset = 0;
1754 }
1755
1756 /* Disable transmitter and interrupt. */
1757 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1758 continue;
1759
1760 reg32 |= 0x3000;
1761 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1762
1763 /* Set full-duplex, 1000 mbps. */
1764 tg3_writephy(tp, MII_BMCR,
1765 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1766
1767 /* Set to master mode. */
1768 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1769 continue;
1770
1771 tg3_writephy(tp, MII_TG3_CTRL,
1772 (MII_TG3_CTRL_AS_MASTER |
1773 MII_TG3_CTRL_ENABLE_AS_MASTER));
1774
1775 /* Enable SM_DSP_CLOCK and 6dB. */
1776 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1777
1778 /* Block the PHY control access. */
1779 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1780 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1781
1782 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1783 if (!err)
1784 break;
1785 } while (--retries);
1786
1787 err = tg3_phy_reset_chanpat(tp);
1788 if (err)
1789 return err;
1790
1791 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1792 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1793
1794 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1795 tg3_writephy(tp, 0x16, 0x0000);
1796
1797 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1798 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1799 /* Set Extended packet length bit for jumbo frames */
1800 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1801 }
1802 else {
1803 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1804 }
1805
1806 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1807
1808 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1809 reg32 &= ~0x3000;
1810 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1811 } else if (!err)
1812 err = -EBUSY;
1813
1814 return err;
1815 }
1816
1817 /* This will reset the tigon3 PHY if there is no valid
1818 * link unless the FORCE argument is non-zero.
1819 */
1820 static int tg3_phy_reset(struct tg3 *tp)
1821 {
1822 u32 cpmuctrl;
1823 u32 phy_status;
1824 int err;
1825
1826 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1827 u32 val;
1828
1829 val = tr32(GRC_MISC_CFG);
1830 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1831 udelay(40);
1832 }
1833 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1834 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1835 if (err != 0)
1836 return -EBUSY;
1837
1838 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1839 netif_carrier_off(tp->dev);
1840 tg3_link_report(tp);
1841 }
1842
1843 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1844 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1845 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1846 err = tg3_phy_reset_5703_4_5(tp);
1847 if (err)
1848 return err;
1849 goto out;
1850 }
1851
1852 cpmuctrl = 0;
1853 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1854 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1855 cpmuctrl = tr32(TG3_CPMU_CTRL);
1856 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1857 tw32(TG3_CPMU_CTRL,
1858 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1859 }
1860
1861 err = tg3_bmcr_reset(tp);
1862 if (err)
1863 return err;
1864
1865 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1866 u32 phy;
1867
1868 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1869 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1870
1871 tw32(TG3_CPMU_CTRL, cpmuctrl);
1872 }
1873
1874 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1875 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1876 u32 val;
1877
1878 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1879 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1880 CPMU_LSPD_1000MB_MACCLK_12_5) {
1881 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1882 udelay(40);
1883 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1884 }
1885 }
1886
1887 tg3_phy_apply_otp(tp);
1888
1889 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1890 tg3_phy_toggle_apd(tp, true);
1891 else
1892 tg3_phy_toggle_apd(tp, false);
1893
1894 out:
1895 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1896 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1897 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1898 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1899 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1900 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1901 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1902 }
1903 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1904 tg3_writephy(tp, 0x1c, 0x8d68);
1905 tg3_writephy(tp, 0x1c, 0x8d68);
1906 }
1907 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1908 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1909 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1910 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1911 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1912 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1913 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1914 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1915 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1916 }
1917 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1918 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1919 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1920 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1921 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1922 tg3_writephy(tp, MII_TG3_TEST1,
1923 MII_TG3_TEST1_TRIM_EN | 0x4);
1924 } else
1925 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1926 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1927 }
1928 /* Set Extended packet length bit (bit 14) on all chips that */
1929 /* support jumbo frames */
1930 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1931 /* Cannot do read-modify-write on 5401 */
1932 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1933 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1934 u32 phy_reg;
1935
1936 /* Set bit 14 with read-modify-write to preserve other bits */
1937 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1938 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1939 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1940 }
1941
1942 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1943 * jumbo frames transmission.
1944 */
1945 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1946 u32 phy_reg;
1947
1948 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1949 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1950 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1951 }
1952
1953 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1954 /* adjust output voltage */
1955 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
1956 }
1957
1958 tg3_phy_toggle_automdix(tp, 1);
1959 tg3_phy_set_wirespeed(tp);
1960 return 0;
1961 }
1962
1963 static void tg3_frob_aux_power(struct tg3 *tp)
1964 {
1965 struct tg3 *tp_peer = tp;
1966
1967 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1968 return;
1969
1970 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1971 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1972 struct net_device *dev_peer;
1973
1974 dev_peer = pci_get_drvdata(tp->pdev_peer);
1975 /* remove_one() may have been run on the peer. */
1976 if (!dev_peer)
1977 tp_peer = tp;
1978 else
1979 tp_peer = netdev_priv(dev_peer);
1980 }
1981
1982 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1983 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1984 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1985 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1986 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1987 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1988 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1989 (GRC_LCLCTRL_GPIO_OE0 |
1990 GRC_LCLCTRL_GPIO_OE1 |
1991 GRC_LCLCTRL_GPIO_OE2 |
1992 GRC_LCLCTRL_GPIO_OUTPUT0 |
1993 GRC_LCLCTRL_GPIO_OUTPUT1),
1994 100);
1995 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
1996 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
1997 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
1998 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
1999 GRC_LCLCTRL_GPIO_OE1 |
2000 GRC_LCLCTRL_GPIO_OE2 |
2001 GRC_LCLCTRL_GPIO_OUTPUT0 |
2002 GRC_LCLCTRL_GPIO_OUTPUT1 |
2003 tp->grc_local_ctrl;
2004 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2005
2006 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2007 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2008
2009 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2010 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2011 } else {
2012 u32 no_gpio2;
2013 u32 grc_local_ctrl = 0;
2014
2015 if (tp_peer != tp &&
2016 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2017 return;
2018
2019 /* Workaround to prevent overdrawing Amps. */
2020 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2021 ASIC_REV_5714) {
2022 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2023 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2024 grc_local_ctrl, 100);
2025 }
2026
2027 /* On 5753 and variants, GPIO2 cannot be used. */
2028 no_gpio2 = tp->nic_sram_data_cfg &
2029 NIC_SRAM_DATA_CFG_NO_GPIO2;
2030
2031 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2032 GRC_LCLCTRL_GPIO_OE1 |
2033 GRC_LCLCTRL_GPIO_OE2 |
2034 GRC_LCLCTRL_GPIO_OUTPUT1 |
2035 GRC_LCLCTRL_GPIO_OUTPUT2;
2036 if (no_gpio2) {
2037 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2038 GRC_LCLCTRL_GPIO_OUTPUT2);
2039 }
2040 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2041 grc_local_ctrl, 100);
2042
2043 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2044
2045 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2046 grc_local_ctrl, 100);
2047
2048 if (!no_gpio2) {
2049 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2050 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2051 grc_local_ctrl, 100);
2052 }
2053 }
2054 } else {
2055 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2056 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2057 if (tp_peer != tp &&
2058 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2059 return;
2060
2061 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2062 (GRC_LCLCTRL_GPIO_OE1 |
2063 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2064
2065 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2066 GRC_LCLCTRL_GPIO_OE1, 100);
2067
2068 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2069 (GRC_LCLCTRL_GPIO_OE1 |
2070 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2071 }
2072 }
2073 }
2074
2075 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2076 {
2077 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2078 return 1;
2079 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2080 if (speed != SPEED_10)
2081 return 1;
2082 } else if (speed == SPEED_10)
2083 return 1;
2084
2085 return 0;
2086 }
2087
2088 static int tg3_setup_phy(struct tg3 *, int);
2089
2090 #define RESET_KIND_SHUTDOWN 0
2091 #define RESET_KIND_INIT 1
2092 #define RESET_KIND_SUSPEND 2
2093
2094 static void tg3_write_sig_post_reset(struct tg3 *, int);
2095 static int tg3_halt_cpu(struct tg3 *, u32);
2096
2097 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2098 {
2099 u32 val;
2100
2101 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2102 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2103 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2104 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2105
2106 sg_dig_ctrl |=
2107 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2108 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2109 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2110 }
2111 return;
2112 }
2113
2114 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2115 tg3_bmcr_reset(tp);
2116 val = tr32(GRC_MISC_CFG);
2117 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2118 udelay(40);
2119 return;
2120 } else if (do_low_power) {
2121 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2122 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2123
2124 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2125 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2126 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2127 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2128 MII_TG3_AUXCTL_PCTL_VREG_11V);
2129 }
2130
2131 /* The PHY should not be powered down on some chips because
2132 * of bugs.
2133 */
2134 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2135 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2136 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2137 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2138 return;
2139
2140 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2141 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2142 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2143 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2144 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2145 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2146 }
2147
2148 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2149 }
2150
2151 /* tp->lock is held. */
2152 static int tg3_nvram_lock(struct tg3 *tp)
2153 {
2154 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2155 int i;
2156
2157 if (tp->nvram_lock_cnt == 0) {
2158 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2159 for (i = 0; i < 8000; i++) {
2160 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2161 break;
2162 udelay(20);
2163 }
2164 if (i == 8000) {
2165 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2166 return -ENODEV;
2167 }
2168 }
2169 tp->nvram_lock_cnt++;
2170 }
2171 return 0;
2172 }
2173
2174 /* tp->lock is held. */
2175 static void tg3_nvram_unlock(struct tg3 *tp)
2176 {
2177 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2178 if (tp->nvram_lock_cnt > 0)
2179 tp->nvram_lock_cnt--;
2180 if (tp->nvram_lock_cnt == 0)
2181 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2182 }
2183 }
2184
2185 /* tp->lock is held. */
2186 static void tg3_enable_nvram_access(struct tg3 *tp)
2187 {
2188 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2189 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2190 u32 nvaccess = tr32(NVRAM_ACCESS);
2191
2192 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2193 }
2194 }
2195
2196 /* tp->lock is held. */
2197 static void tg3_disable_nvram_access(struct tg3 *tp)
2198 {
2199 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2200 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2201 u32 nvaccess = tr32(NVRAM_ACCESS);
2202
2203 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2204 }
2205 }
2206
2207 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2208 u32 offset, u32 *val)
2209 {
2210 u32 tmp;
2211 int i;
2212
2213 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2214 return -EINVAL;
2215
2216 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2217 EEPROM_ADDR_DEVID_MASK |
2218 EEPROM_ADDR_READ);
2219 tw32(GRC_EEPROM_ADDR,
2220 tmp |
2221 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2222 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2223 EEPROM_ADDR_ADDR_MASK) |
2224 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2225
2226 for (i = 0; i < 1000; i++) {
2227 tmp = tr32(GRC_EEPROM_ADDR);
2228
2229 if (tmp & EEPROM_ADDR_COMPLETE)
2230 break;
2231 msleep(1);
2232 }
2233 if (!(tmp & EEPROM_ADDR_COMPLETE))
2234 return -EBUSY;
2235
2236 tmp = tr32(GRC_EEPROM_DATA);
2237
2238 /*
2239 * The data will always be opposite the native endian
2240 * format. Perform a blind byteswap to compensate.
2241 */
2242 *val = swab32(tmp);
2243
2244 return 0;
2245 }
2246
2247 #define NVRAM_CMD_TIMEOUT 10000
2248
2249 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2250 {
2251 int i;
2252
2253 tw32(NVRAM_CMD, nvram_cmd);
2254 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2255 udelay(10);
2256 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2257 udelay(10);
2258 break;
2259 }
2260 }
2261
2262 if (i == NVRAM_CMD_TIMEOUT)
2263 return -EBUSY;
2264
2265 return 0;
2266 }
2267
2268 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2269 {
2270 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2271 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2272 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2273 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2274 (tp->nvram_jedecnum == JEDEC_ATMEL))
2275
2276 addr = ((addr / tp->nvram_pagesize) <<
2277 ATMEL_AT45DB0X1B_PAGE_POS) +
2278 (addr % tp->nvram_pagesize);
2279
2280 return addr;
2281 }
2282
2283 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2284 {
2285 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2286 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2287 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2288 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2289 (tp->nvram_jedecnum == JEDEC_ATMEL))
2290
2291 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2292 tp->nvram_pagesize) +
2293 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2294
2295 return addr;
2296 }
2297
2298 /* NOTE: Data read in from NVRAM is byteswapped according to
2299 * the byteswapping settings for all other register accesses.
2300 * tg3 devices are BE devices, so on a BE machine, the data
2301 * returned will be exactly as it is seen in NVRAM. On a LE
2302 * machine, the 32-bit value will be byteswapped.
2303 */
2304 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2305 {
2306 int ret;
2307
2308 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2309 return tg3_nvram_read_using_eeprom(tp, offset, val);
2310
2311 offset = tg3_nvram_phys_addr(tp, offset);
2312
2313 if (offset > NVRAM_ADDR_MSK)
2314 return -EINVAL;
2315
2316 ret = tg3_nvram_lock(tp);
2317 if (ret)
2318 return ret;
2319
2320 tg3_enable_nvram_access(tp);
2321
2322 tw32(NVRAM_ADDR, offset);
2323 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2324 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2325
2326 if (ret == 0)
2327 *val = tr32(NVRAM_RDDATA);
2328
2329 tg3_disable_nvram_access(tp);
2330
2331 tg3_nvram_unlock(tp);
2332
2333 return ret;
2334 }
2335
2336 /* Ensures NVRAM data is in bytestream format. */
2337 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2338 {
2339 u32 v;
2340 int res = tg3_nvram_read(tp, offset, &v);
2341 if (!res)
2342 *val = cpu_to_be32(v);
2343 return res;
2344 }
2345
2346 /* tp->lock is held. */
2347 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2348 {
2349 u32 addr_high, addr_low;
2350 int i;
2351
2352 addr_high = ((tp->dev->dev_addr[0] << 8) |
2353 tp->dev->dev_addr[1]);
2354 addr_low = ((tp->dev->dev_addr[2] << 24) |
2355 (tp->dev->dev_addr[3] << 16) |
2356 (tp->dev->dev_addr[4] << 8) |
2357 (tp->dev->dev_addr[5] << 0));
2358 for (i = 0; i < 4; i++) {
2359 if (i == 1 && skip_mac_1)
2360 continue;
2361 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2362 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2363 }
2364
2365 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2366 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2367 for (i = 0; i < 12; i++) {
2368 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2369 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2370 }
2371 }
2372
2373 addr_high = (tp->dev->dev_addr[0] +
2374 tp->dev->dev_addr[1] +
2375 tp->dev->dev_addr[2] +
2376 tp->dev->dev_addr[3] +
2377 tp->dev->dev_addr[4] +
2378 tp->dev->dev_addr[5]) &
2379 TX_BACKOFF_SEED_MASK;
2380 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2381 }
2382
2383 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2384 {
2385 u32 misc_host_ctrl;
2386 bool device_should_wake, do_low_power;
2387
2388 /* Make sure register accesses (indirect or otherwise)
2389 * will function correctly.
2390 */
2391 pci_write_config_dword(tp->pdev,
2392 TG3PCI_MISC_HOST_CTRL,
2393 tp->misc_host_ctrl);
2394
2395 switch (state) {
2396 case PCI_D0:
2397 pci_enable_wake(tp->pdev, state, false);
2398 pci_set_power_state(tp->pdev, PCI_D0);
2399
2400 /* Switch out of Vaux if it is a NIC */
2401 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2402 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2403
2404 return 0;
2405
2406 case PCI_D1:
2407 case PCI_D2:
2408 case PCI_D3hot:
2409 break;
2410
2411 default:
2412 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2413 tp->dev->name, state);
2414 return -EINVAL;
2415 }
2416
2417 /* Restore the CLKREQ setting. */
2418 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2419 u16 lnkctl;
2420
2421 pci_read_config_word(tp->pdev,
2422 tp->pcie_cap + PCI_EXP_LNKCTL,
2423 &lnkctl);
2424 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2425 pci_write_config_word(tp->pdev,
2426 tp->pcie_cap + PCI_EXP_LNKCTL,
2427 lnkctl);
2428 }
2429
2430 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2431 tw32(TG3PCI_MISC_HOST_CTRL,
2432 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2433
2434 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2435 device_may_wakeup(&tp->pdev->dev) &&
2436 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2437
2438 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2439 do_low_power = false;
2440 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2441 !tp->link_config.phy_is_low_power) {
2442 struct phy_device *phydev;
2443 u32 phyid, advertising;
2444
2445 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
2446
2447 tp->link_config.phy_is_low_power = 1;
2448
2449 tp->link_config.orig_speed = phydev->speed;
2450 tp->link_config.orig_duplex = phydev->duplex;
2451 tp->link_config.orig_autoneg = phydev->autoneg;
2452 tp->link_config.orig_advertising = phydev->advertising;
2453
2454 advertising = ADVERTISED_TP |
2455 ADVERTISED_Pause |
2456 ADVERTISED_Autoneg |
2457 ADVERTISED_10baseT_Half;
2458
2459 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2460 device_should_wake) {
2461 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2462 advertising |=
2463 ADVERTISED_100baseT_Half |
2464 ADVERTISED_100baseT_Full |
2465 ADVERTISED_10baseT_Full;
2466 else
2467 advertising |= ADVERTISED_10baseT_Full;
2468 }
2469
2470 phydev->advertising = advertising;
2471
2472 phy_start_aneg(phydev);
2473
2474 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2475 if (phyid != TG3_PHY_ID_BCMAC131) {
2476 phyid &= TG3_PHY_OUI_MASK;
2477 if (phyid == TG3_PHY_OUI_1 ||
2478 phyid == TG3_PHY_OUI_2 ||
2479 phyid == TG3_PHY_OUI_3)
2480 do_low_power = true;
2481 }
2482 }
2483 } else {
2484 do_low_power = true;
2485
2486 if (tp->link_config.phy_is_low_power == 0) {
2487 tp->link_config.phy_is_low_power = 1;
2488 tp->link_config.orig_speed = tp->link_config.speed;
2489 tp->link_config.orig_duplex = tp->link_config.duplex;
2490 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2491 }
2492
2493 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2494 tp->link_config.speed = SPEED_10;
2495 tp->link_config.duplex = DUPLEX_HALF;
2496 tp->link_config.autoneg = AUTONEG_ENABLE;
2497 tg3_setup_phy(tp, 0);
2498 }
2499 }
2500
2501 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2502 u32 val;
2503
2504 val = tr32(GRC_VCPU_EXT_CTRL);
2505 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2506 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2507 int i;
2508 u32 val;
2509
2510 for (i = 0; i < 200; i++) {
2511 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2512 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2513 break;
2514 msleep(1);
2515 }
2516 }
2517 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2518 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2519 WOL_DRV_STATE_SHUTDOWN |
2520 WOL_DRV_WOL |
2521 WOL_SET_MAGIC_PKT);
2522
2523 if (device_should_wake) {
2524 u32 mac_mode;
2525
2526 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2527 if (do_low_power) {
2528 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2529 udelay(40);
2530 }
2531
2532 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2533 mac_mode = MAC_MODE_PORT_MODE_GMII;
2534 else
2535 mac_mode = MAC_MODE_PORT_MODE_MII;
2536
2537 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2538 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2539 ASIC_REV_5700) {
2540 u32 speed = (tp->tg3_flags &
2541 TG3_FLAG_WOL_SPEED_100MB) ?
2542 SPEED_100 : SPEED_10;
2543 if (tg3_5700_link_polarity(tp, speed))
2544 mac_mode |= MAC_MODE_LINK_POLARITY;
2545 else
2546 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2547 }
2548 } else {
2549 mac_mode = MAC_MODE_PORT_MODE_TBI;
2550 }
2551
2552 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2553 tw32(MAC_LED_CTRL, tp->led_ctrl);
2554
2555 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2556 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2557 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2558 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2559 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2560 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2561
2562 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2563 mac_mode |= tp->mac_mode &
2564 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2565 if (mac_mode & MAC_MODE_APE_TX_EN)
2566 mac_mode |= MAC_MODE_TDE_ENABLE;
2567 }
2568
2569 tw32_f(MAC_MODE, mac_mode);
2570 udelay(100);
2571
2572 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2573 udelay(10);
2574 }
2575
2576 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2577 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2578 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2579 u32 base_val;
2580
2581 base_val = tp->pci_clock_ctrl;
2582 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2583 CLOCK_CTRL_TXCLK_DISABLE);
2584
2585 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2586 CLOCK_CTRL_PWRDOWN_PLL133, 40);
2587 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2588 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2589 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2590 /* do nothing */
2591 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2592 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2593 u32 newbits1, newbits2;
2594
2595 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2596 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2597 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2598 CLOCK_CTRL_TXCLK_DISABLE |
2599 CLOCK_CTRL_ALTCLK);
2600 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2601 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2602 newbits1 = CLOCK_CTRL_625_CORE;
2603 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2604 } else {
2605 newbits1 = CLOCK_CTRL_ALTCLK;
2606 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2607 }
2608
2609 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2610 40);
2611
2612 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2613 40);
2614
2615 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2616 u32 newbits3;
2617
2618 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2619 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2620 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2621 CLOCK_CTRL_TXCLK_DISABLE |
2622 CLOCK_CTRL_44MHZ_CORE);
2623 } else {
2624 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2625 }
2626
2627 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2628 tp->pci_clock_ctrl | newbits3, 40);
2629 }
2630 }
2631
2632 if (!(device_should_wake) &&
2633 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2634 tg3_power_down_phy(tp, do_low_power);
2635
2636 tg3_frob_aux_power(tp);
2637
2638 /* Workaround for unstable PLL clock */
2639 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2640 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2641 u32 val = tr32(0x7d00);
2642
2643 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2644 tw32(0x7d00, val);
2645 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2646 int err;
2647
2648 err = tg3_nvram_lock(tp);
2649 tg3_halt_cpu(tp, RX_CPU_BASE);
2650 if (!err)
2651 tg3_nvram_unlock(tp);
2652 }
2653 }
2654
2655 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2656
2657 if (device_should_wake)
2658 pci_enable_wake(tp->pdev, state, true);
2659
2660 /* Finally, set the new power state. */
2661 pci_set_power_state(tp->pdev, state);
2662
2663 return 0;
2664 }
2665
2666 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2667 {
2668 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2669 case MII_TG3_AUX_STAT_10HALF:
2670 *speed = SPEED_10;
2671 *duplex = DUPLEX_HALF;
2672 break;
2673
2674 case MII_TG3_AUX_STAT_10FULL:
2675 *speed = SPEED_10;
2676 *duplex = DUPLEX_FULL;
2677 break;
2678
2679 case MII_TG3_AUX_STAT_100HALF:
2680 *speed = SPEED_100;
2681 *duplex = DUPLEX_HALF;
2682 break;
2683
2684 case MII_TG3_AUX_STAT_100FULL:
2685 *speed = SPEED_100;
2686 *duplex = DUPLEX_FULL;
2687 break;
2688
2689 case MII_TG3_AUX_STAT_1000HALF:
2690 *speed = SPEED_1000;
2691 *duplex = DUPLEX_HALF;
2692 break;
2693
2694 case MII_TG3_AUX_STAT_1000FULL:
2695 *speed = SPEED_1000;
2696 *duplex = DUPLEX_FULL;
2697 break;
2698
2699 default:
2700 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2701 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2702 SPEED_10;
2703 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2704 DUPLEX_HALF;
2705 break;
2706 }
2707 *speed = SPEED_INVALID;
2708 *duplex = DUPLEX_INVALID;
2709 break;
2710 }
2711 }
2712
2713 static void tg3_phy_copper_begin(struct tg3 *tp)
2714 {
2715 u32 new_adv;
2716 int i;
2717
2718 if (tp->link_config.phy_is_low_power) {
2719 /* Entering low power mode. Disable gigabit and
2720 * 100baseT advertisements.
2721 */
2722 tg3_writephy(tp, MII_TG3_CTRL, 0);
2723
2724 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2725 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2726 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2727 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2728
2729 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2730 } else if (tp->link_config.speed == SPEED_INVALID) {
2731 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2732 tp->link_config.advertising &=
2733 ~(ADVERTISED_1000baseT_Half |
2734 ADVERTISED_1000baseT_Full);
2735
2736 new_adv = ADVERTISE_CSMA;
2737 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2738 new_adv |= ADVERTISE_10HALF;
2739 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2740 new_adv |= ADVERTISE_10FULL;
2741 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2742 new_adv |= ADVERTISE_100HALF;
2743 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2744 new_adv |= ADVERTISE_100FULL;
2745
2746 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2747
2748 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2749
2750 if (tp->link_config.advertising &
2751 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2752 new_adv = 0;
2753 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2754 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2755 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2756 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2757 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2758 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2759 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2760 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2761 MII_TG3_CTRL_ENABLE_AS_MASTER);
2762 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2763 } else {
2764 tg3_writephy(tp, MII_TG3_CTRL, 0);
2765 }
2766 } else {
2767 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2768 new_adv |= ADVERTISE_CSMA;
2769
2770 /* Asking for a specific link mode. */
2771 if (tp->link_config.speed == SPEED_1000) {
2772 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2773
2774 if (tp->link_config.duplex == DUPLEX_FULL)
2775 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2776 else
2777 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2778 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2779 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2780 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2781 MII_TG3_CTRL_ENABLE_AS_MASTER);
2782 } else {
2783 if (tp->link_config.speed == SPEED_100) {
2784 if (tp->link_config.duplex == DUPLEX_FULL)
2785 new_adv |= ADVERTISE_100FULL;
2786 else
2787 new_adv |= ADVERTISE_100HALF;
2788 } else {
2789 if (tp->link_config.duplex == DUPLEX_FULL)
2790 new_adv |= ADVERTISE_10FULL;
2791 else
2792 new_adv |= ADVERTISE_10HALF;
2793 }
2794 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2795
2796 new_adv = 0;
2797 }
2798
2799 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2800 }
2801
2802 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2803 tp->link_config.speed != SPEED_INVALID) {
2804 u32 bmcr, orig_bmcr;
2805
2806 tp->link_config.active_speed = tp->link_config.speed;
2807 tp->link_config.active_duplex = tp->link_config.duplex;
2808
2809 bmcr = 0;
2810 switch (tp->link_config.speed) {
2811 default:
2812 case SPEED_10:
2813 break;
2814
2815 case SPEED_100:
2816 bmcr |= BMCR_SPEED100;
2817 break;
2818
2819 case SPEED_1000:
2820 bmcr |= TG3_BMCR_SPEED1000;
2821 break;
2822 }
2823
2824 if (tp->link_config.duplex == DUPLEX_FULL)
2825 bmcr |= BMCR_FULLDPLX;
2826
2827 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2828 (bmcr != orig_bmcr)) {
2829 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2830 for (i = 0; i < 1500; i++) {
2831 u32 tmp;
2832
2833 udelay(10);
2834 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2835 tg3_readphy(tp, MII_BMSR, &tmp))
2836 continue;
2837 if (!(tmp & BMSR_LSTATUS)) {
2838 udelay(40);
2839 break;
2840 }
2841 }
2842 tg3_writephy(tp, MII_BMCR, bmcr);
2843 udelay(40);
2844 }
2845 } else {
2846 tg3_writephy(tp, MII_BMCR,
2847 BMCR_ANENABLE | BMCR_ANRESTART);
2848 }
2849 }
2850
2851 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2852 {
2853 int err;
2854
2855 /* Turn off tap power management. */
2856 /* Set Extended packet length bit */
2857 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2858
2859 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2860 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2861
2862 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2863 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2864
2865 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2866 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2867
2868 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2869 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2870
2871 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2872 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2873
2874 udelay(40);
2875
2876 return err;
2877 }
2878
2879 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2880 {
2881 u32 adv_reg, all_mask = 0;
2882
2883 if (mask & ADVERTISED_10baseT_Half)
2884 all_mask |= ADVERTISE_10HALF;
2885 if (mask & ADVERTISED_10baseT_Full)
2886 all_mask |= ADVERTISE_10FULL;
2887 if (mask & ADVERTISED_100baseT_Half)
2888 all_mask |= ADVERTISE_100HALF;
2889 if (mask & ADVERTISED_100baseT_Full)
2890 all_mask |= ADVERTISE_100FULL;
2891
2892 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2893 return 0;
2894
2895 if ((adv_reg & all_mask) != all_mask)
2896 return 0;
2897 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2898 u32 tg3_ctrl;
2899
2900 all_mask = 0;
2901 if (mask & ADVERTISED_1000baseT_Half)
2902 all_mask |= ADVERTISE_1000HALF;
2903 if (mask & ADVERTISED_1000baseT_Full)
2904 all_mask |= ADVERTISE_1000FULL;
2905
2906 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2907 return 0;
2908
2909 if ((tg3_ctrl & all_mask) != all_mask)
2910 return 0;
2911 }
2912 return 1;
2913 }
2914
2915 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2916 {
2917 u32 curadv, reqadv;
2918
2919 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2920 return 1;
2921
2922 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2923 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2924
2925 if (tp->link_config.active_duplex == DUPLEX_FULL) {
2926 if (curadv != reqadv)
2927 return 0;
2928
2929 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2930 tg3_readphy(tp, MII_LPA, rmtadv);
2931 } else {
2932 /* Reprogram the advertisement register, even if it
2933 * does not affect the current link. If the link
2934 * gets renegotiated in the future, we can save an
2935 * additional renegotiation cycle by advertising
2936 * it correctly in the first place.
2937 */
2938 if (curadv != reqadv) {
2939 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2940 ADVERTISE_PAUSE_ASYM);
2941 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2942 }
2943 }
2944
2945 return 1;
2946 }
2947
2948 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2949 {
2950 int current_link_up;
2951 u32 bmsr, dummy;
2952 u32 lcl_adv, rmt_adv;
2953 u16 current_speed;
2954 u8 current_duplex;
2955 int i, err;
2956
2957 tw32(MAC_EVENT, 0);
2958
2959 tw32_f(MAC_STATUS,
2960 (MAC_STATUS_SYNC_CHANGED |
2961 MAC_STATUS_CFG_CHANGED |
2962 MAC_STATUS_MI_COMPLETION |
2963 MAC_STATUS_LNKSTATE_CHANGED));
2964 udelay(40);
2965
2966 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
2967 tw32_f(MAC_MI_MODE,
2968 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
2969 udelay(80);
2970 }
2971
2972 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
2973
2974 /* Some third-party PHYs need to be reset on link going
2975 * down.
2976 */
2977 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2978 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2979 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2980 netif_carrier_ok(tp->dev)) {
2981 tg3_readphy(tp, MII_BMSR, &bmsr);
2982 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2983 !(bmsr & BMSR_LSTATUS))
2984 force_reset = 1;
2985 }
2986 if (force_reset)
2987 tg3_phy_reset(tp);
2988
2989 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
2990 tg3_readphy(tp, MII_BMSR, &bmsr);
2991 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
2992 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
2993 bmsr = 0;
2994
2995 if (!(bmsr & BMSR_LSTATUS)) {
2996 err = tg3_init_5401phy_dsp(tp);
2997 if (err)
2998 return err;
2999
3000 tg3_readphy(tp, MII_BMSR, &bmsr);
3001 for (i = 0; i < 1000; i++) {
3002 udelay(10);
3003 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3004 (bmsr & BMSR_LSTATUS)) {
3005 udelay(40);
3006 break;
3007 }
3008 }
3009
3010 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3011 !(bmsr & BMSR_LSTATUS) &&
3012 tp->link_config.active_speed == SPEED_1000) {
3013 err = tg3_phy_reset(tp);
3014 if (!err)
3015 err = tg3_init_5401phy_dsp(tp);
3016 if (err)
3017 return err;
3018 }
3019 }
3020 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3021 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3022 /* 5701 {A0,B0} CRC bug workaround */
3023 tg3_writephy(tp, 0x15, 0x0a75);
3024 tg3_writephy(tp, 0x1c, 0x8c68);
3025 tg3_writephy(tp, 0x1c, 0x8d68);
3026 tg3_writephy(tp, 0x1c, 0x8c68);
3027 }
3028
3029 /* Clear pending interrupts... */
3030 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3031 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3032
3033 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3034 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3035 else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
3036 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3037
3038 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3039 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3040 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3041 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3042 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3043 else
3044 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3045 }
3046
3047 current_link_up = 0;
3048 current_speed = SPEED_INVALID;
3049 current_duplex = DUPLEX_INVALID;
3050
3051 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3052 u32 val;
3053
3054 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3055 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3056 if (!(val & (1 << 10))) {
3057 val |= (1 << 10);
3058 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3059 goto relink;
3060 }
3061 }
3062
3063 bmsr = 0;
3064 for (i = 0; i < 100; i++) {
3065 tg3_readphy(tp, MII_BMSR, &bmsr);
3066 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3067 (bmsr & BMSR_LSTATUS))
3068 break;
3069 udelay(40);
3070 }
3071
3072 if (bmsr & BMSR_LSTATUS) {
3073 u32 aux_stat, bmcr;
3074
3075 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3076 for (i = 0; i < 2000; i++) {
3077 udelay(10);
3078 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3079 aux_stat)
3080 break;
3081 }
3082
3083 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3084 &current_speed,
3085 &current_duplex);
3086
3087 bmcr = 0;
3088 for (i = 0; i < 200; i++) {
3089 tg3_readphy(tp, MII_BMCR, &bmcr);
3090 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3091 continue;
3092 if (bmcr && bmcr != 0x7fff)
3093 break;
3094 udelay(10);
3095 }
3096
3097 lcl_adv = 0;
3098 rmt_adv = 0;
3099
3100 tp->link_config.active_speed = current_speed;
3101 tp->link_config.active_duplex = current_duplex;
3102
3103 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3104 if ((bmcr & BMCR_ANENABLE) &&
3105 tg3_copper_is_advertising_all(tp,
3106 tp->link_config.advertising)) {
3107 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3108 &rmt_adv))
3109 current_link_up = 1;
3110 }
3111 } else {
3112 if (!(bmcr & BMCR_ANENABLE) &&
3113 tp->link_config.speed == current_speed &&
3114 tp->link_config.duplex == current_duplex &&
3115 tp->link_config.flowctrl ==
3116 tp->link_config.active_flowctrl) {
3117 current_link_up = 1;
3118 }
3119 }
3120
3121 if (current_link_up == 1 &&
3122 tp->link_config.active_duplex == DUPLEX_FULL)
3123 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3124 }
3125
3126 relink:
3127 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3128 u32 tmp;
3129
3130 tg3_phy_copper_begin(tp);
3131
3132 tg3_readphy(tp, MII_BMSR, &tmp);
3133 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3134 (tmp & BMSR_LSTATUS))
3135 current_link_up = 1;
3136 }
3137
3138 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3139 if (current_link_up == 1) {
3140 if (tp->link_config.active_speed == SPEED_100 ||
3141 tp->link_config.active_speed == SPEED_10)
3142 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3143 else
3144 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3145 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3146 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3147 else
3148 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3149
3150 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3151 if (tp->link_config.active_duplex == DUPLEX_HALF)
3152 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3153
3154 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3155 if (current_link_up == 1 &&
3156 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3157 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3158 else
3159 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3160 }
3161
3162 /* ??? Without this setting Netgear GA302T PHY does not
3163 * ??? send/receive packets...
3164 */
3165 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3166 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3167 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3168 tw32_f(MAC_MI_MODE, tp->mi_mode);
3169 udelay(80);
3170 }
3171
3172 tw32_f(MAC_MODE, tp->mac_mode);
3173 udelay(40);
3174
3175 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3176 /* Polled via timer. */
3177 tw32_f(MAC_EVENT, 0);
3178 } else {
3179 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3180 }
3181 udelay(40);
3182
3183 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3184 current_link_up == 1 &&
3185 tp->link_config.active_speed == SPEED_1000 &&
3186 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3187 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3188 udelay(120);
3189 tw32_f(MAC_STATUS,
3190 (MAC_STATUS_SYNC_CHANGED |
3191 MAC_STATUS_CFG_CHANGED));
3192 udelay(40);
3193 tg3_write_mem(tp,
3194 NIC_SRAM_FIRMWARE_MBOX,
3195 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3196 }
3197
3198 /* Prevent send BD corruption. */
3199 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3200 u16 oldlnkctl, newlnkctl;
3201
3202 pci_read_config_word(tp->pdev,
3203 tp->pcie_cap + PCI_EXP_LNKCTL,
3204 &oldlnkctl);
3205 if (tp->link_config.active_speed == SPEED_100 ||
3206 tp->link_config.active_speed == SPEED_10)
3207 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3208 else
3209 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3210 if (newlnkctl != oldlnkctl)
3211 pci_write_config_word(tp->pdev,
3212 tp->pcie_cap + PCI_EXP_LNKCTL,
3213 newlnkctl);
3214 } else if (tp->tg3_flags3 & TG3_FLG3_TOGGLE_10_100_L1PLLPD) {
3215 u32 newreg, oldreg = tr32(TG3_PCIE_LNKCTL);
3216 if (tp->link_config.active_speed == SPEED_100 ||
3217 tp->link_config.active_speed == SPEED_10)
3218 newreg = oldreg & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
3219 else
3220 newreg = oldreg | TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
3221 if (newreg != oldreg)
3222 tw32(TG3_PCIE_LNKCTL, newreg);
3223 }
3224
3225 if (current_link_up != netif_carrier_ok(tp->dev)) {
3226 if (current_link_up)
3227 netif_carrier_on(tp->dev);
3228 else
3229 netif_carrier_off(tp->dev);
3230 tg3_link_report(tp);
3231 }
3232
3233 return 0;
3234 }
3235
3236 struct tg3_fiber_aneginfo {
3237 int state;
3238 #define ANEG_STATE_UNKNOWN 0
3239 #define ANEG_STATE_AN_ENABLE 1
3240 #define ANEG_STATE_RESTART_INIT 2
3241 #define ANEG_STATE_RESTART 3
3242 #define ANEG_STATE_DISABLE_LINK_OK 4
3243 #define ANEG_STATE_ABILITY_DETECT_INIT 5
3244 #define ANEG_STATE_ABILITY_DETECT 6
3245 #define ANEG_STATE_ACK_DETECT_INIT 7
3246 #define ANEG_STATE_ACK_DETECT 8
3247 #define ANEG_STATE_COMPLETE_ACK_INIT 9
3248 #define ANEG_STATE_COMPLETE_ACK 10
3249 #define ANEG_STATE_IDLE_DETECT_INIT 11
3250 #define ANEG_STATE_IDLE_DETECT 12
3251 #define ANEG_STATE_LINK_OK 13
3252 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3253 #define ANEG_STATE_NEXT_PAGE_WAIT 15
3254
3255 u32 flags;
3256 #define MR_AN_ENABLE 0x00000001
3257 #define MR_RESTART_AN 0x00000002
3258 #define MR_AN_COMPLETE 0x00000004
3259 #define MR_PAGE_RX 0x00000008
3260 #define MR_NP_LOADED 0x00000010
3261 #define MR_TOGGLE_TX 0x00000020
3262 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
3263 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
3264 #define MR_LP_ADV_SYM_PAUSE 0x00000100
3265 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
3266 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3267 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3268 #define MR_LP_ADV_NEXT_PAGE 0x00001000
3269 #define MR_TOGGLE_RX 0x00002000
3270 #define MR_NP_RX 0x00004000
3271
3272 #define MR_LINK_OK 0x80000000
3273
3274 unsigned long link_time, cur_time;
3275
3276 u32 ability_match_cfg;
3277 int ability_match_count;
3278
3279 char ability_match, idle_match, ack_match;
3280
3281 u32 txconfig, rxconfig;
3282 #define ANEG_CFG_NP 0x00000080
3283 #define ANEG_CFG_ACK 0x00000040
3284 #define ANEG_CFG_RF2 0x00000020
3285 #define ANEG_CFG_RF1 0x00000010
3286 #define ANEG_CFG_PS2 0x00000001
3287 #define ANEG_CFG_PS1 0x00008000
3288 #define ANEG_CFG_HD 0x00004000
3289 #define ANEG_CFG_FD 0x00002000
3290 #define ANEG_CFG_INVAL 0x00001f06
3291
3292 };
3293 #define ANEG_OK 0
3294 #define ANEG_DONE 1
3295 #define ANEG_TIMER_ENAB 2
3296 #define ANEG_FAILED -1
3297
3298 #define ANEG_STATE_SETTLE_TIME 10000
3299
3300 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3301 struct tg3_fiber_aneginfo *ap)
3302 {
3303 u16 flowctrl;
3304 unsigned long delta;
3305 u32 rx_cfg_reg;
3306 int ret;
3307
3308 if (ap->state == ANEG_STATE_UNKNOWN) {
3309 ap->rxconfig = 0;
3310 ap->link_time = 0;
3311 ap->cur_time = 0;
3312 ap->ability_match_cfg = 0;
3313 ap->ability_match_count = 0;
3314 ap->ability_match = 0;
3315 ap->idle_match = 0;
3316 ap->ack_match = 0;
3317 }
3318 ap->cur_time++;
3319
3320 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3321 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3322
3323 if (rx_cfg_reg != ap->ability_match_cfg) {
3324 ap->ability_match_cfg = rx_cfg_reg;
3325 ap->ability_match = 0;
3326 ap->ability_match_count = 0;
3327 } else {
3328 if (++ap->ability_match_count > 1) {
3329 ap->ability_match = 1;
3330 ap->ability_match_cfg = rx_cfg_reg;
3331 }
3332 }
3333 if (rx_cfg_reg & ANEG_CFG_ACK)
3334 ap->ack_match = 1;
3335 else
3336 ap->ack_match = 0;
3337
3338 ap->idle_match = 0;
3339 } else {
3340 ap->idle_match = 1;
3341 ap->ability_match_cfg = 0;
3342 ap->ability_match_count = 0;
3343 ap->ability_match = 0;
3344 ap->ack_match = 0;
3345
3346 rx_cfg_reg = 0;
3347 }
3348
3349 ap->rxconfig = rx_cfg_reg;
3350 ret = ANEG_OK;
3351
3352 switch(ap->state) {
3353 case ANEG_STATE_UNKNOWN:
3354 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3355 ap->state = ANEG_STATE_AN_ENABLE;
3356
3357 /* fallthru */
3358 case ANEG_STATE_AN_ENABLE:
3359 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3360 if (ap->flags & MR_AN_ENABLE) {
3361 ap->link_time = 0;
3362 ap->cur_time = 0;
3363 ap->ability_match_cfg = 0;
3364 ap->ability_match_count = 0;
3365 ap->ability_match = 0;
3366 ap->idle_match = 0;
3367 ap->ack_match = 0;
3368
3369 ap->state = ANEG_STATE_RESTART_INIT;
3370 } else {
3371 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3372 }
3373 break;
3374
3375 case ANEG_STATE_RESTART_INIT:
3376 ap->link_time = ap->cur_time;
3377 ap->flags &= ~(MR_NP_LOADED);
3378 ap->txconfig = 0;
3379 tw32(MAC_TX_AUTO_NEG, 0);
3380 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3381 tw32_f(MAC_MODE, tp->mac_mode);
3382 udelay(40);
3383
3384 ret = ANEG_TIMER_ENAB;
3385 ap->state = ANEG_STATE_RESTART;
3386
3387 /* fallthru */
3388 case ANEG_STATE_RESTART:
3389 delta = ap->cur_time - ap->link_time;
3390 if (delta > ANEG_STATE_SETTLE_TIME) {
3391 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3392 } else {
3393 ret = ANEG_TIMER_ENAB;
3394 }
3395 break;
3396
3397 case ANEG_STATE_DISABLE_LINK_OK:
3398 ret = ANEG_DONE;
3399 break;
3400
3401 case ANEG_STATE_ABILITY_DETECT_INIT:
3402 ap->flags &= ~(MR_TOGGLE_TX);
3403 ap->txconfig = ANEG_CFG_FD;
3404 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3405 if (flowctrl & ADVERTISE_1000XPAUSE)
3406 ap->txconfig |= ANEG_CFG_PS1;
3407 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3408 ap->txconfig |= ANEG_CFG_PS2;
3409 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3410 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3411 tw32_f(MAC_MODE, tp->mac_mode);
3412 udelay(40);
3413
3414 ap->state = ANEG_STATE_ABILITY_DETECT;
3415 break;
3416
3417 case ANEG_STATE_ABILITY_DETECT:
3418 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3419 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3420 }
3421 break;
3422
3423 case ANEG_STATE_ACK_DETECT_INIT:
3424 ap->txconfig |= ANEG_CFG_ACK;
3425 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3426 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3427 tw32_f(MAC_MODE, tp->mac_mode);
3428 udelay(40);
3429
3430 ap->state = ANEG_STATE_ACK_DETECT;
3431
3432 /* fallthru */
3433 case ANEG_STATE_ACK_DETECT:
3434 if (ap->ack_match != 0) {
3435 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3436 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3437 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3438 } else {
3439 ap->state = ANEG_STATE_AN_ENABLE;
3440 }
3441 } else if (ap->ability_match != 0 &&
3442 ap->rxconfig == 0) {
3443 ap->state = ANEG_STATE_AN_ENABLE;
3444 }
3445 break;
3446
3447 case ANEG_STATE_COMPLETE_ACK_INIT:
3448 if (ap->rxconfig & ANEG_CFG_INVAL) {
3449 ret = ANEG_FAILED;
3450 break;
3451 }
3452 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3453 MR_LP_ADV_HALF_DUPLEX |
3454 MR_LP_ADV_SYM_PAUSE |
3455 MR_LP_ADV_ASYM_PAUSE |
3456 MR_LP_ADV_REMOTE_FAULT1 |
3457 MR_LP_ADV_REMOTE_FAULT2 |
3458 MR_LP_ADV_NEXT_PAGE |
3459 MR_TOGGLE_RX |
3460 MR_NP_RX);
3461 if (ap->rxconfig & ANEG_CFG_FD)
3462 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3463 if (ap->rxconfig & ANEG_CFG_HD)
3464 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3465 if (ap->rxconfig & ANEG_CFG_PS1)
3466 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3467 if (ap->rxconfig & ANEG_CFG_PS2)
3468 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3469 if (ap->rxconfig & ANEG_CFG_RF1)
3470 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3471 if (ap->rxconfig & ANEG_CFG_RF2)
3472 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3473 if (ap->rxconfig & ANEG_CFG_NP)
3474 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3475
3476 ap->link_time = ap->cur_time;
3477
3478 ap->flags ^= (MR_TOGGLE_TX);
3479 if (ap->rxconfig & 0x0008)
3480 ap->flags |= MR_TOGGLE_RX;
3481 if (ap->rxconfig & ANEG_CFG_NP)
3482 ap->flags |= MR_NP_RX;
3483 ap->flags |= MR_PAGE_RX;
3484
3485 ap->state = ANEG_STATE_COMPLETE_ACK;
3486 ret = ANEG_TIMER_ENAB;
3487 break;
3488
3489 case ANEG_STATE_COMPLETE_ACK:
3490 if (ap->ability_match != 0 &&
3491 ap->rxconfig == 0) {
3492 ap->state = ANEG_STATE_AN_ENABLE;
3493 break;
3494 }
3495 delta = ap->cur_time - ap->link_time;
3496 if (delta > ANEG_STATE_SETTLE_TIME) {
3497 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3498 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3499 } else {
3500 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3501 !(ap->flags & MR_NP_RX)) {
3502 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3503 } else {
3504 ret = ANEG_FAILED;
3505 }
3506 }
3507 }
3508 break;
3509
3510 case ANEG_STATE_IDLE_DETECT_INIT:
3511 ap->link_time = ap->cur_time;
3512 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3513 tw32_f(MAC_MODE, tp->mac_mode);
3514 udelay(40);
3515
3516 ap->state = ANEG_STATE_IDLE_DETECT;
3517 ret = ANEG_TIMER_ENAB;
3518 break;
3519
3520 case ANEG_STATE_IDLE_DETECT:
3521 if (ap->ability_match != 0 &&
3522 ap->rxconfig == 0) {
3523 ap->state = ANEG_STATE_AN_ENABLE;
3524 break;
3525 }
3526 delta = ap->cur_time - ap->link_time;
3527 if (delta > ANEG_STATE_SETTLE_TIME) {
3528 /* XXX another gem from the Broadcom driver :( */
3529 ap->state = ANEG_STATE_LINK_OK;
3530 }
3531 break;
3532
3533 case ANEG_STATE_LINK_OK:
3534 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3535 ret = ANEG_DONE;
3536 break;
3537
3538 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3539 /* ??? unimplemented */
3540 break;
3541
3542 case ANEG_STATE_NEXT_PAGE_WAIT:
3543 /* ??? unimplemented */
3544 break;
3545
3546 default:
3547 ret = ANEG_FAILED;
3548 break;
3549 }
3550
3551 return ret;
3552 }
3553
3554 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3555 {
3556 int res = 0;
3557 struct tg3_fiber_aneginfo aninfo;
3558 int status = ANEG_FAILED;
3559 unsigned int tick;
3560 u32 tmp;
3561
3562 tw32_f(MAC_TX_AUTO_NEG, 0);
3563
3564 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3565 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3566 udelay(40);
3567
3568 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3569 udelay(40);
3570
3571 memset(&aninfo, 0, sizeof(aninfo));
3572 aninfo.flags |= MR_AN_ENABLE;
3573 aninfo.state = ANEG_STATE_UNKNOWN;
3574 aninfo.cur_time = 0;
3575 tick = 0;
3576 while (++tick < 195000) {
3577 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3578 if (status == ANEG_DONE || status == ANEG_FAILED)
3579 break;
3580
3581 udelay(1);
3582 }
3583
3584 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3585 tw32_f(MAC_MODE, tp->mac_mode);
3586 udelay(40);
3587
3588 *txflags = aninfo.txconfig;
3589 *rxflags = aninfo.flags;
3590
3591 if (status == ANEG_DONE &&
3592 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3593 MR_LP_ADV_FULL_DUPLEX)))
3594 res = 1;
3595
3596 return res;
3597 }
3598
3599 static void tg3_init_bcm8002(struct tg3 *tp)
3600 {
3601 u32 mac_status = tr32(MAC_STATUS);
3602 int i;
3603
3604 /* Reset when initting first time or we have a link. */
3605 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3606 !(mac_status & MAC_STATUS_PCS_SYNCED))
3607 return;
3608
3609 /* Set PLL lock range. */
3610 tg3_writephy(tp, 0x16, 0x8007);
3611
3612 /* SW reset */
3613 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3614
3615 /* Wait for reset to complete. */
3616 /* XXX schedule_timeout() ... */
3617 for (i = 0; i < 500; i++)
3618 udelay(10);
3619
3620 /* Config mode; select PMA/Ch 1 regs. */
3621 tg3_writephy(tp, 0x10, 0x8411);
3622
3623 /* Enable auto-lock and comdet, select txclk for tx. */
3624 tg3_writephy(tp, 0x11, 0x0a10);
3625
3626 tg3_writephy(tp, 0x18, 0x00a0);
3627 tg3_writephy(tp, 0x16, 0x41ff);
3628
3629 /* Assert and deassert POR. */
3630 tg3_writephy(tp, 0x13, 0x0400);
3631 udelay(40);
3632 tg3_writephy(tp, 0x13, 0x0000);
3633
3634 tg3_writephy(tp, 0x11, 0x0a50);
3635 udelay(40);
3636 tg3_writephy(tp, 0x11, 0x0a10);
3637
3638 /* Wait for signal to stabilize */
3639 /* XXX schedule_timeout() ... */
3640 for (i = 0; i < 15000; i++)
3641 udelay(10);
3642
3643 /* Deselect the channel register so we can read the PHYID
3644 * later.
3645 */
3646 tg3_writephy(tp, 0x10, 0x8011);
3647 }
3648
3649 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3650 {
3651 u16 flowctrl;
3652 u32 sg_dig_ctrl, sg_dig_status;
3653 u32 serdes_cfg, expected_sg_dig_ctrl;
3654 int workaround, port_a;
3655 int current_link_up;
3656
3657 serdes_cfg = 0;
3658 expected_sg_dig_ctrl = 0;
3659 workaround = 0;
3660 port_a = 1;
3661 current_link_up = 0;
3662
3663 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3664 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3665 workaround = 1;
3666 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3667 port_a = 0;
3668
3669 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3670 /* preserve bits 20-23 for voltage regulator */
3671 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3672 }
3673
3674 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3675
3676 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3677 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3678 if (workaround) {
3679 u32 val = serdes_cfg;
3680
3681 if (port_a)
3682 val |= 0xc010000;
3683 else
3684 val |= 0x4010000;
3685 tw32_f(MAC_SERDES_CFG, val);
3686 }
3687
3688 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3689 }
3690 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3691 tg3_setup_flow_control(tp, 0, 0);
3692 current_link_up = 1;
3693 }
3694 goto out;
3695 }
3696
3697 /* Want auto-negotiation. */
3698 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3699
3700 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3701 if (flowctrl & ADVERTISE_1000XPAUSE)
3702 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3703 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3704 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3705
3706 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3707 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3708 tp->serdes_counter &&
3709 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3710 MAC_STATUS_RCVD_CFG)) ==
3711 MAC_STATUS_PCS_SYNCED)) {
3712 tp->serdes_counter--;
3713 current_link_up = 1;
3714 goto out;
3715 }
3716 restart_autoneg:
3717 if (workaround)
3718 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3719 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3720 udelay(5);
3721 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3722
3723 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3724 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3725 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3726 MAC_STATUS_SIGNAL_DET)) {
3727 sg_dig_status = tr32(SG_DIG_STATUS);
3728 mac_status = tr32(MAC_STATUS);
3729
3730 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3731 (mac_status & MAC_STATUS_PCS_SYNCED)) {
3732 u32 local_adv = 0, remote_adv = 0;
3733
3734 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3735 local_adv |= ADVERTISE_1000XPAUSE;
3736 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3737 local_adv |= ADVERTISE_1000XPSE_ASYM;
3738
3739 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3740 remote_adv |= LPA_1000XPAUSE;
3741 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3742 remote_adv |= LPA_1000XPAUSE_ASYM;
3743
3744 tg3_setup_flow_control(tp, local_adv, remote_adv);
3745 current_link_up = 1;
3746 tp->serdes_counter = 0;
3747 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3748 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3749 if (tp->serdes_counter)
3750 tp->serdes_counter--;
3751 else {
3752 if (workaround) {
3753 u32 val = serdes_cfg;
3754
3755 if (port_a)
3756 val |= 0xc010000;
3757 else
3758 val |= 0x4010000;
3759
3760 tw32_f(MAC_SERDES_CFG, val);
3761 }
3762
3763 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3764 udelay(40);
3765
3766 /* Link parallel detection - link is up */
3767 /* only if we have PCS_SYNC and not */
3768 /* receiving config code words */
3769 mac_status = tr32(MAC_STATUS);
3770 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3771 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3772 tg3_setup_flow_control(tp, 0, 0);
3773 current_link_up = 1;
3774 tp->tg3_flags2 |=
3775 TG3_FLG2_PARALLEL_DETECT;
3776 tp->serdes_counter =
3777 SERDES_PARALLEL_DET_TIMEOUT;
3778 } else
3779 goto restart_autoneg;
3780 }
3781 }
3782 } else {
3783 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3784 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3785 }
3786
3787 out:
3788 return current_link_up;
3789 }
3790
3791 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3792 {
3793 int current_link_up = 0;
3794
3795 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3796 goto out;
3797
3798 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3799 u32 txflags, rxflags;
3800 int i;
3801
3802 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3803 u32 local_adv = 0, remote_adv = 0;
3804
3805 if (txflags & ANEG_CFG_PS1)
3806 local_adv |= ADVERTISE_1000XPAUSE;
3807 if (txflags & ANEG_CFG_PS2)
3808 local_adv |= ADVERTISE_1000XPSE_ASYM;
3809
3810 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3811 remote_adv |= LPA_1000XPAUSE;
3812 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3813 remote_adv |= LPA_1000XPAUSE_ASYM;
3814
3815 tg3_setup_flow_control(tp, local_adv, remote_adv);
3816
3817 current_link_up = 1;
3818 }
3819 for (i = 0; i < 30; i++) {
3820 udelay(20);
3821 tw32_f(MAC_STATUS,
3822 (MAC_STATUS_SYNC_CHANGED |
3823 MAC_STATUS_CFG_CHANGED));
3824 udelay(40);
3825 if ((tr32(MAC_STATUS) &
3826 (MAC_STATUS_SYNC_CHANGED |
3827 MAC_STATUS_CFG_CHANGED)) == 0)
3828 break;
3829 }
3830
3831 mac_status = tr32(MAC_STATUS);
3832 if (current_link_up == 0 &&
3833 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3834 !(mac_status & MAC_STATUS_RCVD_CFG))
3835 current_link_up = 1;
3836 } else {
3837 tg3_setup_flow_control(tp, 0, 0);
3838
3839 /* Forcing 1000FD link up. */
3840 current_link_up = 1;
3841
3842 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3843 udelay(40);
3844
3845 tw32_f(MAC_MODE, tp->mac_mode);
3846 udelay(40);
3847 }
3848
3849 out:
3850 return current_link_up;
3851 }
3852
3853 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3854 {
3855 u32 orig_pause_cfg;
3856 u16 orig_active_speed;
3857 u8 orig_active_duplex;
3858 u32 mac_status;
3859 int current_link_up;
3860 int i;
3861
3862 orig_pause_cfg = tp->link_config.active_flowctrl;
3863 orig_active_speed = tp->link_config.active_speed;
3864 orig_active_duplex = tp->link_config.active_duplex;
3865
3866 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3867 netif_carrier_ok(tp->dev) &&
3868 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3869 mac_status = tr32(MAC_STATUS);
3870 mac_status &= (MAC_STATUS_PCS_SYNCED |
3871 MAC_STATUS_SIGNAL_DET |
3872 MAC_STATUS_CFG_CHANGED |
3873 MAC_STATUS_RCVD_CFG);
3874 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3875 MAC_STATUS_SIGNAL_DET)) {
3876 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3877 MAC_STATUS_CFG_CHANGED));
3878 return 0;
3879 }
3880 }
3881
3882 tw32_f(MAC_TX_AUTO_NEG, 0);
3883
3884 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3885 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3886 tw32_f(MAC_MODE, tp->mac_mode);
3887 udelay(40);
3888
3889 if (tp->phy_id == PHY_ID_BCM8002)
3890 tg3_init_bcm8002(tp);
3891
3892 /* Enable link change event even when serdes polling. */
3893 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3894 udelay(40);
3895
3896 current_link_up = 0;
3897 mac_status = tr32(MAC_STATUS);
3898
3899 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3900 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3901 else
3902 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3903
3904 tp->napi[0].hw_status->status =
3905 (SD_STATUS_UPDATED |
3906 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
3907
3908 for (i = 0; i < 100; i++) {
3909 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3910 MAC_STATUS_CFG_CHANGED));
3911 udelay(5);
3912 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3913 MAC_STATUS_CFG_CHANGED |
3914 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3915 break;
3916 }
3917
3918 mac_status = tr32(MAC_STATUS);
3919 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3920 current_link_up = 0;
3921 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3922 tp->serdes_counter == 0) {
3923 tw32_f(MAC_MODE, (tp->mac_mode |
3924 MAC_MODE_SEND_CONFIGS));
3925 udelay(1);
3926 tw32_f(MAC_MODE, tp->mac_mode);
3927 }
3928 }
3929
3930 if (current_link_up == 1) {
3931 tp->link_config.active_speed = SPEED_1000;
3932 tp->link_config.active_duplex = DUPLEX_FULL;
3933 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3934 LED_CTRL_LNKLED_OVERRIDE |
3935 LED_CTRL_1000MBPS_ON));
3936 } else {
3937 tp->link_config.active_speed = SPEED_INVALID;
3938 tp->link_config.active_duplex = DUPLEX_INVALID;
3939 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3940 LED_CTRL_LNKLED_OVERRIDE |
3941 LED_CTRL_TRAFFIC_OVERRIDE));
3942 }
3943
3944 if (current_link_up != netif_carrier_ok(tp->dev)) {
3945 if (current_link_up)
3946 netif_carrier_on(tp->dev);
3947 else
3948 netif_carrier_off(tp->dev);
3949 tg3_link_report(tp);
3950 } else {
3951 u32 now_pause_cfg = tp->link_config.active_flowctrl;
3952 if (orig_pause_cfg != now_pause_cfg ||
3953 orig_active_speed != tp->link_config.active_speed ||
3954 orig_active_duplex != tp->link_config.active_duplex)
3955 tg3_link_report(tp);
3956 }
3957
3958 return 0;
3959 }
3960
3961 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
3962 {
3963 int current_link_up, err = 0;
3964 u32 bmsr, bmcr;
3965 u16 current_speed;
3966 u8 current_duplex;
3967 u32 local_adv, remote_adv;
3968
3969 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3970 tw32_f(MAC_MODE, tp->mac_mode);
3971 udelay(40);
3972
3973 tw32(MAC_EVENT, 0);
3974
3975 tw32_f(MAC_STATUS,
3976 (MAC_STATUS_SYNC_CHANGED |
3977 MAC_STATUS_CFG_CHANGED |
3978 MAC_STATUS_MI_COMPLETION |
3979 MAC_STATUS_LNKSTATE_CHANGED));
3980 udelay(40);
3981
3982 if (force_reset)
3983 tg3_phy_reset(tp);
3984
3985 current_link_up = 0;
3986 current_speed = SPEED_INVALID;
3987 current_duplex = DUPLEX_INVALID;
3988
3989 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3990 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3991 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
3992 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3993 bmsr |= BMSR_LSTATUS;
3994 else
3995 bmsr &= ~BMSR_LSTATUS;
3996 }
3997
3998 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
3999
4000 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4001 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4002 /* do nothing, just check for link up at the end */
4003 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4004 u32 adv, new_adv;
4005
4006 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4007 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4008 ADVERTISE_1000XPAUSE |
4009 ADVERTISE_1000XPSE_ASYM |
4010 ADVERTISE_SLCT);
4011
4012 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4013
4014 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4015 new_adv |= ADVERTISE_1000XHALF;
4016 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4017 new_adv |= ADVERTISE_1000XFULL;
4018
4019 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4020 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4021 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4022 tg3_writephy(tp, MII_BMCR, bmcr);
4023
4024 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4025 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4026 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4027
4028 return err;
4029 }
4030 } else {
4031 u32 new_bmcr;
4032
4033 bmcr &= ~BMCR_SPEED1000;
4034 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4035
4036 if (tp->link_config.duplex == DUPLEX_FULL)
4037 new_bmcr |= BMCR_FULLDPLX;
4038
4039 if (new_bmcr != bmcr) {
4040 /* BMCR_SPEED1000 is a reserved bit that needs
4041 * to be set on write.
4042 */
4043 new_bmcr |= BMCR_SPEED1000;
4044
4045 /* Force a linkdown */
4046 if (netif_carrier_ok(tp->dev)) {
4047 u32 adv;
4048
4049 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4050 adv &= ~(ADVERTISE_1000XFULL |
4051 ADVERTISE_1000XHALF |
4052 ADVERTISE_SLCT);
4053 tg3_writephy(tp, MII_ADVERTISE, adv);
4054 tg3_writephy(tp, MII_BMCR, bmcr |
4055 BMCR_ANRESTART |
4056 BMCR_ANENABLE);
4057 udelay(10);
4058 netif_carrier_off(tp->dev);
4059 }
4060 tg3_writephy(tp, MII_BMCR, new_bmcr);
4061 bmcr = new_bmcr;
4062 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4063 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4064 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4065 ASIC_REV_5714) {
4066 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4067 bmsr |= BMSR_LSTATUS;
4068 else
4069 bmsr &= ~BMSR_LSTATUS;
4070 }
4071 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4072 }
4073 }
4074
4075 if (bmsr & BMSR_LSTATUS) {
4076 current_speed = SPEED_1000;
4077 current_link_up = 1;
4078 if (bmcr & BMCR_FULLDPLX)
4079 current_duplex = DUPLEX_FULL;
4080 else
4081 current_duplex = DUPLEX_HALF;
4082
4083 local_adv = 0;
4084 remote_adv = 0;
4085
4086 if (bmcr & BMCR_ANENABLE) {
4087 u32 common;
4088
4089 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4090 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4091 common = local_adv & remote_adv;
4092 if (common & (ADVERTISE_1000XHALF |
4093 ADVERTISE_1000XFULL)) {
4094 if (common & ADVERTISE_1000XFULL)
4095 current_duplex = DUPLEX_FULL;
4096 else
4097 current_duplex = DUPLEX_HALF;
4098 }
4099 else
4100 current_link_up = 0;
4101 }
4102 }
4103
4104 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4105 tg3_setup_flow_control(tp, local_adv, remote_adv);
4106
4107 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4108 if (tp->link_config.active_duplex == DUPLEX_HALF)
4109 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4110
4111 tw32_f(MAC_MODE, tp->mac_mode);
4112 udelay(40);
4113
4114 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4115
4116 tp->link_config.active_speed = current_speed;
4117 tp->link_config.active_duplex = current_duplex;
4118
4119 if (current_link_up != netif_carrier_ok(tp->dev)) {
4120 if (current_link_up)
4121 netif_carrier_on(tp->dev);
4122 else {
4123 netif_carrier_off(tp->dev);
4124 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4125 }
4126 tg3_link_report(tp);
4127 }
4128 return err;
4129 }
4130
4131 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4132 {
4133 if (tp->serdes_counter) {
4134 /* Give autoneg time to complete. */
4135 tp->serdes_counter--;
4136 return;
4137 }
4138 if (!netif_carrier_ok(tp->dev) &&
4139 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4140 u32 bmcr;
4141
4142 tg3_readphy(tp, MII_BMCR, &bmcr);
4143 if (bmcr & BMCR_ANENABLE) {
4144 u32 phy1, phy2;
4145
4146 /* Select shadow register 0x1f */
4147 tg3_writephy(tp, 0x1c, 0x7c00);
4148 tg3_readphy(tp, 0x1c, &phy1);
4149
4150 /* Select expansion interrupt status register */
4151 tg3_writephy(tp, 0x17, 0x0f01);
4152 tg3_readphy(tp, 0x15, &phy2);
4153 tg3_readphy(tp, 0x15, &phy2);
4154
4155 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4156 /* We have signal detect and not receiving
4157 * config code words, link is up by parallel
4158 * detection.
4159 */
4160
4161 bmcr &= ~BMCR_ANENABLE;
4162 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4163 tg3_writephy(tp, MII_BMCR, bmcr);
4164 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4165 }
4166 }
4167 }
4168 else if (netif_carrier_ok(tp->dev) &&
4169 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4170 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4171 u32 phy2;
4172
4173 /* Select expansion interrupt status register */
4174 tg3_writephy(tp, 0x17, 0x0f01);
4175 tg3_readphy(tp, 0x15, &phy2);
4176 if (phy2 & 0x20) {
4177 u32 bmcr;
4178
4179 /* Config code words received, turn on autoneg. */
4180 tg3_readphy(tp, MII_BMCR, &bmcr);
4181 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4182
4183 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4184
4185 }
4186 }
4187 }
4188
4189 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4190 {
4191 int err;
4192
4193 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4194 err = tg3_setup_fiber_phy(tp, force_reset);
4195 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4196 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4197 } else {
4198 err = tg3_setup_copper_phy(tp, force_reset);
4199 }
4200
4201 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4202 u32 val, scale;
4203
4204 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4205 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4206 scale = 65;
4207 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4208 scale = 6;
4209 else
4210 scale = 12;
4211
4212 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4213 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4214 tw32(GRC_MISC_CFG, val);
4215 }
4216
4217 if (tp->link_config.active_speed == SPEED_1000 &&
4218 tp->link_config.active_duplex == DUPLEX_HALF)
4219 tw32(MAC_TX_LENGTHS,
4220 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4221 (6 << TX_LENGTHS_IPG_SHIFT) |
4222 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4223 else
4224 tw32(MAC_TX_LENGTHS,
4225 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4226 (6 << TX_LENGTHS_IPG_SHIFT) |
4227 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4228
4229 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4230 if (netif_carrier_ok(tp->dev)) {
4231 tw32(HOSTCC_STAT_COAL_TICKS,
4232 tp->coal.stats_block_coalesce_usecs);
4233 } else {
4234 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4235 }
4236 }
4237
4238 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4239 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4240 if (!netif_carrier_ok(tp->dev))
4241 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4242 tp->pwrmgmt_thresh;
4243 else
4244 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4245 tw32(PCIE_PWR_MGMT_THRESH, val);
4246 }
4247
4248 return err;
4249 }
4250
4251 /* This is called whenever we suspect that the system chipset is re-
4252 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4253 * is bogus tx completions. We try to recover by setting the
4254 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4255 * in the workqueue.
4256 */
4257 static void tg3_tx_recover(struct tg3 *tp)
4258 {
4259 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4260 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4261
4262 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4263 "mapped I/O cycles to the network device, attempting to "
4264 "recover. Please report the problem to the driver maintainer "
4265 "and include system chipset information.\n", tp->dev->name);
4266
4267 spin_lock(&tp->lock);
4268 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4269 spin_unlock(&tp->lock);
4270 }
4271
4272 static inline u32 tg3_tx_avail(struct tg3 *tp)
4273 {
4274 smp_mb();
4275 return (tp->tx_pending -
4276 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
4277 }
4278
4279 /* Tigon3 never reports partial packet sends. So we do not
4280 * need special logic to handle SKBs that have not had all
4281 * of their frags sent yet, like SunGEM does.
4282 */
4283 static void tg3_tx(struct tg3_napi *tnapi)
4284 {
4285 struct tg3 *tp = tnapi->tp;
4286 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4287 u32 sw_idx = tp->tx_cons;
4288
4289 while (sw_idx != hw_idx) {
4290 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
4291 struct sk_buff *skb = ri->skb;
4292 int i, tx_bug = 0;
4293
4294 if (unlikely(skb == NULL)) {
4295 tg3_tx_recover(tp);
4296 return;
4297 }
4298
4299 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
4300
4301 ri->skb = NULL;
4302
4303 sw_idx = NEXT_TX(sw_idx);
4304
4305 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4306 ri = &tp->tx_buffers[sw_idx];
4307 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4308 tx_bug = 1;
4309 sw_idx = NEXT_TX(sw_idx);
4310 }
4311
4312 dev_kfree_skb(skb);
4313
4314 if (unlikely(tx_bug)) {
4315 tg3_tx_recover(tp);
4316 return;
4317 }
4318 }
4319
4320 tp->tx_cons = sw_idx;
4321
4322 /* Need to make the tx_cons update visible to tg3_start_xmit()
4323 * before checking for netif_queue_stopped(). Without the
4324 * memory barrier, there is a small possibility that tg3_start_xmit()
4325 * will miss it and cause the queue to be stopped forever.
4326 */
4327 smp_mb();
4328
4329 if (unlikely(netif_queue_stopped(tp->dev) &&
4330 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
4331 netif_tx_lock(tp->dev);
4332 if (netif_queue_stopped(tp->dev) &&
4333 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
4334 netif_wake_queue(tp->dev);
4335 netif_tx_unlock(tp->dev);
4336 }
4337 }
4338
4339 /* Returns size of skb allocated or < 0 on error.
4340 *
4341 * We only need to fill in the address because the other members
4342 * of the RX descriptor are invariant, see tg3_init_rings.
4343 *
4344 * Note the purposeful assymetry of cpu vs. chip accesses. For
4345 * posting buffers we only dirty the first cache line of the RX
4346 * descriptor (containing the address). Whereas for the RX status
4347 * buffers the cpu only reads the last cacheline of the RX descriptor
4348 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4349 */
4350 static int tg3_alloc_rx_skb(struct tg3_napi *tnapi, u32 opaque_key,
4351 int src_idx, u32 dest_idx_unmasked)
4352 {
4353 struct tg3 *tp = tnapi->tp;
4354 struct tg3_rx_buffer_desc *desc;
4355 struct ring_info *map, *src_map;
4356 struct sk_buff *skb;
4357 dma_addr_t mapping;
4358 int skb_size, dest_idx;
4359 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4360
4361 src_map = NULL;
4362 switch (opaque_key) {
4363 case RXD_OPAQUE_RING_STD:
4364 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4365 desc = &tpr->rx_std[dest_idx];
4366 map = &tpr->rx_std_buffers[dest_idx];
4367 if (src_idx >= 0)
4368 src_map = &tpr->rx_std_buffers[src_idx];
4369 skb_size = tp->rx_pkt_map_sz;
4370 break;
4371
4372 case RXD_OPAQUE_RING_JUMBO:
4373 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4374 desc = &tpr->rx_jmb[dest_idx].std;
4375 map = &tpr->rx_jmb_buffers[dest_idx];
4376 if (src_idx >= 0)
4377 src_map = &tpr->rx_jmb_buffers[src_idx];
4378 skb_size = TG3_RX_JMB_MAP_SZ;
4379 break;
4380
4381 default:
4382 return -EINVAL;
4383 }
4384
4385 /* Do not overwrite any of the map or rp information
4386 * until we are sure we can commit to a new buffer.
4387 *
4388 * Callers depend upon this behavior and assume that
4389 * we leave everything unchanged if we fail.
4390 */
4391 skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4392 if (skb == NULL)
4393 return -ENOMEM;
4394
4395 skb_reserve(skb, tp->rx_offset);
4396
4397 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4398 PCI_DMA_FROMDEVICE);
4399
4400 map->skb = skb;
4401 pci_unmap_addr_set(map, mapping, mapping);
4402
4403 if (src_map != NULL)
4404 src_map->skb = NULL;
4405
4406 desc->addr_hi = ((u64)mapping >> 32);
4407 desc->addr_lo = ((u64)mapping & 0xffffffff);
4408
4409 return skb_size;
4410 }
4411
4412 /* We only need to move over in the address because the other
4413 * members of the RX descriptor are invariant. See notes above
4414 * tg3_alloc_rx_skb for full details.
4415 */
4416 static void tg3_recycle_rx(struct tg3_napi *tnapi, u32 opaque_key,
4417 int src_idx, u32 dest_idx_unmasked)
4418 {
4419 struct tg3 *tp = tnapi->tp;
4420 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4421 struct ring_info *src_map, *dest_map;
4422 int dest_idx;
4423 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4424
4425 switch (opaque_key) {
4426 case RXD_OPAQUE_RING_STD:
4427 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4428 dest_desc = &tpr->rx_std[dest_idx];
4429 dest_map = &tpr->rx_std_buffers[dest_idx];
4430 src_desc = &tpr->rx_std[src_idx];
4431 src_map = &tpr->rx_std_buffers[src_idx];
4432 break;
4433
4434 case RXD_OPAQUE_RING_JUMBO:
4435 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4436 dest_desc = &tpr->rx_jmb[dest_idx].std;
4437 dest_map = &tpr->rx_jmb_buffers[dest_idx];
4438 src_desc = &tpr->rx_jmb[src_idx].std;
4439 src_map = &tpr->rx_jmb_buffers[src_idx];
4440 break;
4441
4442 default:
4443 return;
4444 }
4445
4446 dest_map->skb = src_map->skb;
4447 pci_unmap_addr_set(dest_map, mapping,
4448 pci_unmap_addr(src_map, mapping));
4449 dest_desc->addr_hi = src_desc->addr_hi;
4450 dest_desc->addr_lo = src_desc->addr_lo;
4451
4452 src_map->skb = NULL;
4453 }
4454
4455 /* The RX ring scheme is composed of multiple rings which post fresh
4456 * buffers to the chip, and one special ring the chip uses to report
4457 * status back to the host.
4458 *
4459 * The special ring reports the status of received packets to the
4460 * host. The chip does not write into the original descriptor the
4461 * RX buffer was obtained from. The chip simply takes the original
4462 * descriptor as provided by the host, updates the status and length
4463 * field, then writes this into the next status ring entry.
4464 *
4465 * Each ring the host uses to post buffers to the chip is described
4466 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4467 * it is first placed into the on-chip ram. When the packet's length
4468 * is known, it walks down the TG3_BDINFO entries to select the ring.
4469 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4470 * which is within the range of the new packet's length is chosen.
4471 *
4472 * The "separate ring for rx status" scheme may sound queer, but it makes
4473 * sense from a cache coherency perspective. If only the host writes
4474 * to the buffer post rings, and only the chip writes to the rx status
4475 * rings, then cache lines never move beyond shared-modified state.
4476 * If both the host and chip were to write into the same ring, cache line
4477 * eviction could occur since both entities want it in an exclusive state.
4478 */
4479 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4480 {
4481 struct tg3 *tp = tnapi->tp;
4482 u32 work_mask, rx_std_posted = 0;
4483 u32 sw_idx = tnapi->rx_rcb_ptr;
4484 u16 hw_idx;
4485 int received;
4486 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4487
4488 hw_idx = tnapi->hw_status->idx[0].rx_producer;
4489 /*
4490 * We need to order the read of hw_idx and the read of
4491 * the opaque cookie.
4492 */
4493 rmb();
4494 work_mask = 0;
4495 received = 0;
4496 while (sw_idx != hw_idx && budget > 0) {
4497 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4498 unsigned int len;
4499 struct sk_buff *skb;
4500 dma_addr_t dma_addr;
4501 u32 opaque_key, desc_idx, *post_ptr;
4502
4503 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4504 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4505 if (opaque_key == RXD_OPAQUE_RING_STD) {
4506 struct ring_info *ri = &tpr->rx_std_buffers[desc_idx];
4507 dma_addr = pci_unmap_addr(ri, mapping);
4508 skb = ri->skb;
4509 post_ptr = &tpr->rx_std_ptr;
4510 rx_std_posted++;
4511 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4512 struct ring_info *ri = &tpr->rx_jmb_buffers[desc_idx];
4513 dma_addr = pci_unmap_addr(ri, mapping);
4514 skb = ri->skb;
4515 post_ptr = &tpr->rx_jmb_ptr;
4516 } else
4517 goto next_pkt_nopost;
4518
4519 work_mask |= opaque_key;
4520
4521 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4522 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4523 drop_it:
4524 tg3_recycle_rx(tnapi, opaque_key,
4525 desc_idx, *post_ptr);
4526 drop_it_no_recycle:
4527 /* Other statistics kept track of by card. */
4528 tp->net_stats.rx_dropped++;
4529 goto next_pkt;
4530 }
4531
4532 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4533 ETH_FCS_LEN;
4534
4535 if (len > RX_COPY_THRESHOLD
4536 && tp->rx_offset == NET_IP_ALIGN
4537 /* rx_offset will likely not equal NET_IP_ALIGN
4538 * if this is a 5701 card running in PCI-X mode
4539 * [see tg3_get_invariants()]
4540 */
4541 ) {
4542 int skb_size;
4543
4544 skb_size = tg3_alloc_rx_skb(tnapi, opaque_key,
4545 desc_idx, *post_ptr);
4546 if (skb_size < 0)
4547 goto drop_it;
4548
4549 pci_unmap_single(tp->pdev, dma_addr, skb_size,
4550 PCI_DMA_FROMDEVICE);
4551
4552 skb_put(skb, len);
4553 } else {
4554 struct sk_buff *copy_skb;
4555
4556 tg3_recycle_rx(tnapi, opaque_key,
4557 desc_idx, *post_ptr);
4558
4559 copy_skb = netdev_alloc_skb(tp->dev,
4560 len + TG3_RAW_IP_ALIGN);
4561 if (copy_skb == NULL)
4562 goto drop_it_no_recycle;
4563
4564 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4565 skb_put(copy_skb, len);
4566 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4567 skb_copy_from_linear_data(skb, copy_skb->data, len);
4568 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4569
4570 /* We'll reuse the original ring buffer. */
4571 skb = copy_skb;
4572 }
4573
4574 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4575 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4576 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4577 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4578 skb->ip_summed = CHECKSUM_UNNECESSARY;
4579 else
4580 skb->ip_summed = CHECKSUM_NONE;
4581
4582 skb->protocol = eth_type_trans(skb, tp->dev);
4583
4584 if (len > (tp->dev->mtu + ETH_HLEN) &&
4585 skb->protocol != htons(ETH_P_8021Q)) {
4586 dev_kfree_skb(skb);
4587 goto next_pkt;
4588 }
4589
4590 #if TG3_VLAN_TAG_USED
4591 if (tp->vlgrp != NULL &&
4592 desc->type_flags & RXD_FLAG_VLAN) {
4593 vlan_gro_receive(&tnapi->napi, tp->vlgrp,
4594 desc->err_vlan & RXD_VLAN_MASK, skb);
4595 } else
4596 #endif
4597 napi_gro_receive(&tnapi->napi, skb);
4598
4599 received++;
4600 budget--;
4601
4602 next_pkt:
4603 (*post_ptr)++;
4604
4605 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4606 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4607
4608 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4609 TG3_64BIT_REG_LOW, idx);
4610 work_mask &= ~RXD_OPAQUE_RING_STD;
4611 rx_std_posted = 0;
4612 }
4613 next_pkt_nopost:
4614 sw_idx++;
4615 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4616
4617 /* Refresh hw_idx to see if there is new work */
4618 if (sw_idx == hw_idx) {
4619 hw_idx = tnapi->hw_status->idx[0].rx_producer;
4620 rmb();
4621 }
4622 }
4623
4624 /* ACK the status ring. */
4625 tnapi->rx_rcb_ptr = sw_idx;
4626 tw32_rx_mbox(tnapi->consmbox, sw_idx);
4627
4628 /* Refill RX ring(s). */
4629 if (work_mask & RXD_OPAQUE_RING_STD) {
4630 sw_idx = tpr->rx_std_ptr % TG3_RX_RING_SIZE;
4631 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4632 sw_idx);
4633 }
4634 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4635 sw_idx = tpr->rx_jmb_ptr % TG3_RX_JUMBO_RING_SIZE;
4636 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4637 sw_idx);
4638 }
4639 mmiowb();
4640
4641 return received;
4642 }
4643
4644 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4645 {
4646 struct tg3 *tp = tnapi->tp;
4647 struct tg3_hw_status *sblk = tnapi->hw_status;
4648
4649 /* handle link change and other phy events */
4650 if (!(tp->tg3_flags &
4651 (TG3_FLAG_USE_LINKCHG_REG |
4652 TG3_FLAG_POLL_SERDES))) {
4653 if (sblk->status & SD_STATUS_LINK_CHG) {
4654 sblk->status = SD_STATUS_UPDATED |
4655 (sblk->status & ~SD_STATUS_LINK_CHG);
4656 spin_lock(&tp->lock);
4657 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4658 tw32_f(MAC_STATUS,
4659 (MAC_STATUS_SYNC_CHANGED |
4660 MAC_STATUS_CFG_CHANGED |
4661 MAC_STATUS_MI_COMPLETION |
4662 MAC_STATUS_LNKSTATE_CHANGED));
4663 udelay(40);
4664 } else
4665 tg3_setup_phy(tp, 0);
4666 spin_unlock(&tp->lock);
4667 }
4668 }
4669
4670 /* run TX completion thread */
4671 if (sblk->idx[0].tx_consumer != tp->tx_cons) {
4672 tg3_tx(tnapi);
4673 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4674 return work_done;
4675 }
4676
4677 /* run RX thread, within the bounds set by NAPI.
4678 * All RX "locking" is done by ensuring outside
4679 * code synchronizes with tg3->napi.poll()
4680 */
4681 if (sblk->idx[0].rx_producer != tnapi->rx_rcb_ptr)
4682 work_done += tg3_rx(tnapi, budget - work_done);
4683
4684 return work_done;
4685 }
4686
4687 static int tg3_poll(struct napi_struct *napi, int budget)
4688 {
4689 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4690 struct tg3 *tp = tnapi->tp;
4691 int work_done = 0;
4692 struct tg3_hw_status *sblk = tnapi->hw_status;
4693
4694 while (1) {
4695 work_done = tg3_poll_work(tnapi, work_done, budget);
4696
4697 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4698 goto tx_recovery;
4699
4700 if (unlikely(work_done >= budget))
4701 break;
4702
4703 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4704 /* tp->last_tag is used in tg3_int_reenable() below
4705 * to tell the hw how much work has been processed,
4706 * so we must read it before checking for more work.
4707 */
4708 tnapi->last_tag = sblk->status_tag;
4709 tnapi->last_irq_tag = tnapi->last_tag;
4710 rmb();
4711 } else
4712 sblk->status &= ~SD_STATUS_UPDATED;
4713
4714 if (likely(!tg3_has_work(tnapi))) {
4715 napi_complete(napi);
4716 tg3_int_reenable(tnapi);
4717 break;
4718 }
4719 }
4720
4721 return work_done;
4722
4723 tx_recovery:
4724 /* work_done is guaranteed to be less than budget. */
4725 napi_complete(napi);
4726 schedule_work(&tp->reset_task);
4727 return work_done;
4728 }
4729
4730 static void tg3_irq_quiesce(struct tg3 *tp)
4731 {
4732 BUG_ON(tp->irq_sync);
4733
4734 tp->irq_sync = 1;
4735 smp_mb();
4736
4737 synchronize_irq(tp->pdev->irq);
4738 }
4739
4740 static inline int tg3_irq_sync(struct tg3 *tp)
4741 {
4742 return tp->irq_sync;
4743 }
4744
4745 /* Fully shutdown all tg3 driver activity elsewhere in the system.
4746 * If irq_sync is non-zero, then the IRQ handler must be synchronized
4747 * with as well. Most of the time, this is not necessary except when
4748 * shutting down the device.
4749 */
4750 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4751 {
4752 spin_lock_bh(&tp->lock);
4753 if (irq_sync)
4754 tg3_irq_quiesce(tp);
4755 }
4756
4757 static inline void tg3_full_unlock(struct tg3 *tp)
4758 {
4759 spin_unlock_bh(&tp->lock);
4760 }
4761
4762 /* One-shot MSI handler - Chip automatically disables interrupt
4763 * after sending MSI so driver doesn't have to do it.
4764 */
4765 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
4766 {
4767 struct tg3_napi *tnapi = dev_id;
4768 struct tg3 *tp = tnapi->tp;
4769
4770 prefetch(tnapi->hw_status);
4771 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4772
4773 if (likely(!tg3_irq_sync(tp)))
4774 napi_schedule(&tnapi->napi);
4775
4776 return IRQ_HANDLED;
4777 }
4778
4779 /* MSI ISR - No need to check for interrupt sharing and no need to
4780 * flush status block and interrupt mailbox. PCI ordering rules
4781 * guarantee that MSI will arrive after the status block.
4782 */
4783 static irqreturn_t tg3_msi(int irq, void *dev_id)
4784 {
4785 struct tg3_napi *tnapi = dev_id;
4786 struct tg3 *tp = tnapi->tp;
4787
4788 prefetch(tnapi->hw_status);
4789 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4790 /*
4791 * Writing any value to intr-mbox-0 clears PCI INTA# and
4792 * chip-internal interrupt pending events.
4793 * Writing non-zero to intr-mbox-0 additional tells the
4794 * NIC to stop sending us irqs, engaging "in-intr-handler"
4795 * event coalescing.
4796 */
4797 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4798 if (likely(!tg3_irq_sync(tp)))
4799 napi_schedule(&tnapi->napi);
4800
4801 return IRQ_RETVAL(1);
4802 }
4803
4804 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
4805 {
4806 struct tg3_napi *tnapi = dev_id;
4807 struct tg3 *tp = tnapi->tp;
4808 struct tg3_hw_status *sblk = tnapi->hw_status;
4809 unsigned int handled = 1;
4810
4811 /* In INTx mode, it is possible for the interrupt to arrive at
4812 * the CPU before the status block posted prior to the interrupt.
4813 * Reading the PCI State register will confirm whether the
4814 * interrupt is ours and will flush the status block.
4815 */
4816 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4817 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4818 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4819 handled = 0;
4820 goto out;
4821 }
4822 }
4823
4824 /*
4825 * Writing any value to intr-mbox-0 clears PCI INTA# and
4826 * chip-internal interrupt pending events.
4827 * Writing non-zero to intr-mbox-0 additional tells the
4828 * NIC to stop sending us irqs, engaging "in-intr-handler"
4829 * event coalescing.
4830 *
4831 * Flush the mailbox to de-assert the IRQ immediately to prevent
4832 * spurious interrupts. The flush impacts performance but
4833 * excessive spurious interrupts can be worse in some cases.
4834 */
4835 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4836 if (tg3_irq_sync(tp))
4837 goto out;
4838 sblk->status &= ~SD_STATUS_UPDATED;
4839 if (likely(tg3_has_work(tnapi))) {
4840 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4841 napi_schedule(&tnapi->napi);
4842 } else {
4843 /* No work, shared interrupt perhaps? re-enable
4844 * interrupts, and flush that PCI write
4845 */
4846 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4847 0x00000000);
4848 }
4849 out:
4850 return IRQ_RETVAL(handled);
4851 }
4852
4853 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
4854 {
4855 struct tg3_napi *tnapi = dev_id;
4856 struct tg3 *tp = tnapi->tp;
4857 struct tg3_hw_status *sblk = tnapi->hw_status;
4858 unsigned int handled = 1;
4859
4860 /* In INTx mode, it is possible for the interrupt to arrive at
4861 * the CPU before the status block posted prior to the interrupt.
4862 * Reading the PCI State register will confirm whether the
4863 * interrupt is ours and will flush the status block.
4864 */
4865 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
4866 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4867 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4868 handled = 0;
4869 goto out;
4870 }
4871 }
4872
4873 /*
4874 * writing any value to intr-mbox-0 clears PCI INTA# and
4875 * chip-internal interrupt pending events.
4876 * writing non-zero to intr-mbox-0 additional tells the
4877 * NIC to stop sending us irqs, engaging "in-intr-handler"
4878 * event coalescing.
4879 *
4880 * Flush the mailbox to de-assert the IRQ immediately to prevent
4881 * spurious interrupts. The flush impacts performance but
4882 * excessive spurious interrupts can be worse in some cases.
4883 */
4884 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4885
4886 /*
4887 * In a shared interrupt configuration, sometimes other devices'
4888 * interrupts will scream. We record the current status tag here
4889 * so that the above check can report that the screaming interrupts
4890 * are unhandled. Eventually they will be silenced.
4891 */
4892 tnapi->last_irq_tag = sblk->status_tag;
4893
4894 if (tg3_irq_sync(tp))
4895 goto out;
4896
4897 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4898
4899 napi_schedule(&tnapi->napi);
4900
4901 out:
4902 return IRQ_RETVAL(handled);
4903 }
4904
4905 /* ISR for interrupt test */
4906 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
4907 {
4908 struct tg3_napi *tnapi = dev_id;
4909 struct tg3 *tp = tnapi->tp;
4910 struct tg3_hw_status *sblk = tnapi->hw_status;
4911
4912 if ((sblk->status & SD_STATUS_UPDATED) ||
4913 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4914 tg3_disable_ints(tp);
4915 return IRQ_RETVAL(1);
4916 }
4917 return IRQ_RETVAL(0);
4918 }
4919
4920 static int tg3_init_hw(struct tg3 *, int);
4921 static int tg3_halt(struct tg3 *, int, int);
4922
4923 /* Restart hardware after configuration changes, self-test, etc.
4924 * Invoked with tp->lock held.
4925 */
4926 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
4927 __releases(tp->lock)
4928 __acquires(tp->lock)
4929 {
4930 int err;
4931
4932 err = tg3_init_hw(tp, reset_phy);
4933 if (err) {
4934 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4935 "aborting.\n", tp->dev->name);
4936 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4937 tg3_full_unlock(tp);
4938 del_timer_sync(&tp->timer);
4939 tp->irq_sync = 0;
4940 napi_enable(&tp->napi[0].napi);
4941 dev_close(tp->dev);
4942 tg3_full_lock(tp, 0);
4943 }
4944 return err;
4945 }
4946
4947 #ifdef CONFIG_NET_POLL_CONTROLLER
4948 static void tg3_poll_controller(struct net_device *dev)
4949 {
4950 struct tg3 *tp = netdev_priv(dev);
4951
4952 tg3_interrupt(tp->pdev->irq, dev);
4953 }
4954 #endif
4955
4956 static void tg3_reset_task(struct work_struct *work)
4957 {
4958 struct tg3 *tp = container_of(work, struct tg3, reset_task);
4959 int err;
4960 unsigned int restart_timer;
4961
4962 tg3_full_lock(tp, 0);
4963
4964 if (!netif_running(tp->dev)) {
4965 tg3_full_unlock(tp);
4966 return;
4967 }
4968
4969 tg3_full_unlock(tp);
4970
4971 tg3_phy_stop(tp);
4972
4973 tg3_netif_stop(tp);
4974
4975 tg3_full_lock(tp, 1);
4976
4977 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
4978 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
4979
4980 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
4981 tp->write32_tx_mbox = tg3_write32_tx_mbox;
4982 tp->write32_rx_mbox = tg3_write_flush_reg32;
4983 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
4984 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
4985 }
4986
4987 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
4988 err = tg3_init_hw(tp, 1);
4989 if (err)
4990 goto out;
4991
4992 tg3_netif_start(tp);
4993
4994 if (restart_timer)
4995 mod_timer(&tp->timer, jiffies + 1);
4996
4997 out:
4998 tg3_full_unlock(tp);
4999
5000 if (!err)
5001 tg3_phy_start(tp);
5002 }
5003
5004 static void tg3_dump_short_state(struct tg3 *tp)
5005 {
5006 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5007 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5008 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5009 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5010 }
5011
5012 static void tg3_tx_timeout(struct net_device *dev)
5013 {
5014 struct tg3 *tp = netdev_priv(dev);
5015
5016 if (netif_msg_tx_err(tp)) {
5017 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5018 dev->name);
5019 tg3_dump_short_state(tp);
5020 }
5021
5022 schedule_work(&tp->reset_task);
5023 }
5024
5025 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5026 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5027 {
5028 u32 base = (u32) mapping & 0xffffffff;
5029
5030 return ((base > 0xffffdcc0) &&
5031 (base + len + 8 < base));
5032 }
5033
5034 /* Test for DMA addresses > 40-bit */
5035 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5036 int len)
5037 {
5038 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5039 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5040 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5041 return 0;
5042 #else
5043 return 0;
5044 #endif
5045 }
5046
5047 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
5048
5049 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5050 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
5051 u32 last_plus_one, u32 *start,
5052 u32 base_flags, u32 mss)
5053 {
5054 struct sk_buff *new_skb;
5055 dma_addr_t new_addr = 0;
5056 u32 entry = *start;
5057 int i, ret = 0;
5058
5059 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5060 new_skb = skb_copy(skb, GFP_ATOMIC);
5061 else {
5062 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5063
5064 new_skb = skb_copy_expand(skb,
5065 skb_headroom(skb) + more_headroom,
5066 skb_tailroom(skb), GFP_ATOMIC);
5067 }
5068
5069 if (!new_skb) {
5070 ret = -1;
5071 } else {
5072 /* New SKB is guaranteed to be linear. */
5073 entry = *start;
5074 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
5075 new_addr = skb_shinfo(new_skb)->dma_head;
5076
5077 /* Make sure new skb does not cross any 4G boundaries.
5078 * Drop the packet if it does.
5079 */
5080 if (ret || tg3_4g_overflow_test(new_addr, new_skb->len)) {
5081 if (!ret)
5082 skb_dma_unmap(&tp->pdev->dev, new_skb,
5083 DMA_TO_DEVICE);
5084 ret = -1;
5085 dev_kfree_skb(new_skb);
5086 new_skb = NULL;
5087 } else {
5088 tg3_set_txd(tp, entry, new_addr, new_skb->len,
5089 base_flags, 1 | (mss << 1));
5090 *start = NEXT_TX(entry);
5091 }
5092 }
5093
5094 /* Now clean up the sw ring entries. */
5095 i = 0;
5096 while (entry != last_plus_one) {
5097 if (i == 0) {
5098 tp->tx_buffers[entry].skb = new_skb;
5099 } else {
5100 tp->tx_buffers[entry].skb = NULL;
5101 }
5102 entry = NEXT_TX(entry);
5103 i++;
5104 }
5105
5106 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5107 dev_kfree_skb(skb);
5108
5109 return ret;
5110 }
5111
5112 static void tg3_set_txd(struct tg3 *tp, int entry,
5113 dma_addr_t mapping, int len, u32 flags,
5114 u32 mss_and_is_end)
5115 {
5116 struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
5117 int is_end = (mss_and_is_end & 0x1);
5118 u32 mss = (mss_and_is_end >> 1);
5119 u32 vlan_tag = 0;
5120
5121 if (is_end)
5122 flags |= TXD_FLAG_END;
5123 if (flags & TXD_FLAG_VLAN) {
5124 vlan_tag = flags >> 16;
5125 flags &= 0xffff;
5126 }
5127 vlan_tag |= (mss << TXD_MSS_SHIFT);
5128
5129 txd->addr_hi = ((u64) mapping >> 32);
5130 txd->addr_lo = ((u64) mapping & 0xffffffff);
5131 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5132 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5133 }
5134
5135 /* hard_start_xmit for devices that don't have any bugs and
5136 * support TG3_FLG2_HW_TSO_2 only.
5137 */
5138 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
5139 {
5140 struct tg3 *tp = netdev_priv(dev);
5141 u32 len, entry, base_flags, mss;
5142 struct skb_shared_info *sp;
5143 dma_addr_t mapping;
5144
5145 len = skb_headlen(skb);
5146
5147 /* We are running in BH disabled context with netif_tx_lock
5148 * and TX reclaim runs via tp->napi.poll inside of a software
5149 * interrupt. Furthermore, IRQ processing runs lockless so we have
5150 * no IRQ context deadlocks to worry about either. Rejoice!
5151 */
5152 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
5153 if (!netif_queue_stopped(dev)) {
5154 netif_stop_queue(dev);
5155
5156 /* This is a hard error, log it. */
5157 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5158 "queue awake!\n", dev->name);
5159 }
5160 return NETDEV_TX_BUSY;
5161 }
5162
5163 entry = tp->tx_prod;
5164 base_flags = 0;
5165 mss = 0;
5166 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5167 int tcp_opt_len, ip_tcp_len;
5168
5169 if (skb_header_cloned(skb) &&
5170 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5171 dev_kfree_skb(skb);
5172 goto out_unlock;
5173 }
5174
5175 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5176 mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
5177 else {
5178 struct iphdr *iph = ip_hdr(skb);
5179
5180 tcp_opt_len = tcp_optlen(skb);
5181 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5182
5183 iph->check = 0;
5184 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5185 mss |= (ip_tcp_len + tcp_opt_len) << 9;
5186 }
5187
5188 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5189 TXD_FLAG_CPU_POST_DMA);
5190
5191 tcp_hdr(skb)->check = 0;
5192
5193 }
5194 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5195 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5196 #if TG3_VLAN_TAG_USED
5197 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5198 base_flags |= (TXD_FLAG_VLAN |
5199 (vlan_tx_tag_get(skb) << 16));
5200 #endif
5201
5202 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5203 dev_kfree_skb(skb);
5204 goto out_unlock;
5205 }
5206
5207 sp = skb_shinfo(skb);
5208
5209 mapping = sp->dma_head;
5210
5211 tp->tx_buffers[entry].skb = skb;
5212
5213 tg3_set_txd(tp, entry, mapping, len, base_flags,
5214 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5215
5216 entry = NEXT_TX(entry);
5217
5218 /* Now loop through additional data fragments, and queue them. */
5219 if (skb_shinfo(skb)->nr_frags > 0) {
5220 unsigned int i, last;
5221
5222 last = skb_shinfo(skb)->nr_frags - 1;
5223 for (i = 0; i <= last; i++) {
5224 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5225
5226 len = frag->size;
5227 mapping = sp->dma_maps[i];
5228 tp->tx_buffers[entry].skb = NULL;
5229
5230 tg3_set_txd(tp, entry, mapping, len,
5231 base_flags, (i == last) | (mss << 1));
5232
5233 entry = NEXT_TX(entry);
5234 }
5235 }
5236
5237 /* Packets are ready, update Tx producer idx local and on card. */
5238 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
5239
5240 tp->tx_prod = entry;
5241 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
5242 netif_stop_queue(dev);
5243 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
5244 netif_wake_queue(tp->dev);
5245 }
5246
5247 out_unlock:
5248 mmiowb();
5249
5250 return NETDEV_TX_OK;
5251 }
5252
5253 static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
5254
5255 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5256 * TSO header is greater than 80 bytes.
5257 */
5258 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5259 {
5260 struct sk_buff *segs, *nskb;
5261
5262 /* Estimate the number of fragments in the worst case */
5263 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
5264 netif_stop_queue(tp->dev);
5265 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
5266 return NETDEV_TX_BUSY;
5267
5268 netif_wake_queue(tp->dev);
5269 }
5270
5271 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5272 if (IS_ERR(segs))
5273 goto tg3_tso_bug_end;
5274
5275 do {
5276 nskb = segs;
5277 segs = segs->next;
5278 nskb->next = NULL;
5279 tg3_start_xmit_dma_bug(nskb, tp->dev);
5280 } while (segs);
5281
5282 tg3_tso_bug_end:
5283 dev_kfree_skb(skb);
5284
5285 return NETDEV_TX_OK;
5286 }
5287
5288 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5289 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5290 */
5291 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
5292 {
5293 struct tg3 *tp = netdev_priv(dev);
5294 u32 len, entry, base_flags, mss;
5295 struct skb_shared_info *sp;
5296 int would_hit_hwbug;
5297 dma_addr_t mapping;
5298
5299 len = skb_headlen(skb);
5300
5301 /* We are running in BH disabled context with netif_tx_lock
5302 * and TX reclaim runs via tp->napi.poll inside of a software
5303 * interrupt. Furthermore, IRQ processing runs lockless so we have
5304 * no IRQ context deadlocks to worry about either. Rejoice!
5305 */
5306 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
5307 if (!netif_queue_stopped(dev)) {
5308 netif_stop_queue(dev);
5309
5310 /* This is a hard error, log it. */
5311 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5312 "queue awake!\n", dev->name);
5313 }
5314 return NETDEV_TX_BUSY;
5315 }
5316
5317 entry = tp->tx_prod;
5318 base_flags = 0;
5319 if (skb->ip_summed == CHECKSUM_PARTIAL)
5320 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5321 mss = 0;
5322 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5323 struct iphdr *iph;
5324 int tcp_opt_len, ip_tcp_len, hdr_len;
5325
5326 if (skb_header_cloned(skb) &&
5327 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5328 dev_kfree_skb(skb);
5329 goto out_unlock;
5330 }
5331
5332 tcp_opt_len = tcp_optlen(skb);
5333 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5334
5335 hdr_len = ip_tcp_len + tcp_opt_len;
5336 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5337 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5338 return (tg3_tso_bug(tp, skb));
5339
5340 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5341 TXD_FLAG_CPU_POST_DMA);
5342
5343 iph = ip_hdr(skb);
5344 iph->check = 0;
5345 iph->tot_len = htons(mss + hdr_len);
5346 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5347 tcp_hdr(skb)->check = 0;
5348 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5349 } else
5350 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5351 iph->daddr, 0,
5352 IPPROTO_TCP,
5353 0);
5354
5355 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
5356 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
5357 if (tcp_opt_len || iph->ihl > 5) {
5358 int tsflags;
5359
5360 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5361 mss |= (tsflags << 11);
5362 }
5363 } else {
5364 if (tcp_opt_len || iph->ihl > 5) {
5365 int tsflags;
5366
5367 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5368 base_flags |= tsflags << 12;
5369 }
5370 }
5371 }
5372 #if TG3_VLAN_TAG_USED
5373 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5374 base_flags |= (TXD_FLAG_VLAN |
5375 (vlan_tx_tag_get(skb) << 16));
5376 #endif
5377
5378 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5379 dev_kfree_skb(skb);
5380 goto out_unlock;
5381 }
5382
5383 sp = skb_shinfo(skb);
5384
5385 mapping = sp->dma_head;
5386
5387 tp->tx_buffers[entry].skb = skb;
5388
5389 would_hit_hwbug = 0;
5390
5391 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5392 would_hit_hwbug = 1;
5393 else if (tg3_4g_overflow_test(mapping, len))
5394 would_hit_hwbug = 1;
5395
5396 tg3_set_txd(tp, entry, mapping, len, base_flags,
5397 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5398
5399 entry = NEXT_TX(entry);
5400
5401 /* Now loop through additional data fragments, and queue them. */
5402 if (skb_shinfo(skb)->nr_frags > 0) {
5403 unsigned int i, last;
5404
5405 last = skb_shinfo(skb)->nr_frags - 1;
5406 for (i = 0; i <= last; i++) {
5407 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5408
5409 len = frag->size;
5410 mapping = sp->dma_maps[i];
5411
5412 tp->tx_buffers[entry].skb = NULL;
5413
5414 if (tg3_4g_overflow_test(mapping, len))
5415 would_hit_hwbug = 1;
5416
5417 if (tg3_40bit_overflow_test(tp, mapping, len))
5418 would_hit_hwbug = 1;
5419
5420 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5421 tg3_set_txd(tp, entry, mapping, len,
5422 base_flags, (i == last)|(mss << 1));
5423 else
5424 tg3_set_txd(tp, entry, mapping, len,
5425 base_flags, (i == last));
5426
5427 entry = NEXT_TX(entry);
5428 }
5429 }
5430
5431 if (would_hit_hwbug) {
5432 u32 last_plus_one = entry;
5433 u32 start;
5434
5435 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5436 start &= (TG3_TX_RING_SIZE - 1);
5437
5438 /* If the workaround fails due to memory/mapping
5439 * failure, silently drop this packet.
5440 */
5441 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
5442 &start, base_flags, mss))
5443 goto out_unlock;
5444
5445 entry = start;
5446 }
5447
5448 /* Packets are ready, update Tx producer idx local and on card. */
5449 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
5450
5451 tp->tx_prod = entry;
5452 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
5453 netif_stop_queue(dev);
5454 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
5455 netif_wake_queue(tp->dev);
5456 }
5457
5458 out_unlock:
5459 mmiowb();
5460
5461 return NETDEV_TX_OK;
5462 }
5463
5464 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5465 int new_mtu)
5466 {
5467 dev->mtu = new_mtu;
5468
5469 if (new_mtu > ETH_DATA_LEN) {
5470 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5471 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5472 ethtool_op_set_tso(dev, 0);
5473 }
5474 else
5475 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5476 } else {
5477 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5478 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5479 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5480 }
5481 }
5482
5483 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5484 {
5485 struct tg3 *tp = netdev_priv(dev);
5486 int err;
5487
5488 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5489 return -EINVAL;
5490
5491 if (!netif_running(dev)) {
5492 /* We'll just catch it later when the
5493 * device is up'd.
5494 */
5495 tg3_set_mtu(dev, tp, new_mtu);
5496 return 0;
5497 }
5498
5499 tg3_phy_stop(tp);
5500
5501 tg3_netif_stop(tp);
5502
5503 tg3_full_lock(tp, 1);
5504
5505 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5506
5507 tg3_set_mtu(dev, tp, new_mtu);
5508
5509 err = tg3_restart_hw(tp, 0);
5510
5511 if (!err)
5512 tg3_netif_start(tp);
5513
5514 tg3_full_unlock(tp);
5515
5516 if (!err)
5517 tg3_phy_start(tp);
5518
5519 return err;
5520 }
5521
5522 static void tg3_rx_prodring_free(struct tg3 *tp,
5523 struct tg3_rx_prodring_set *tpr)
5524 {
5525 struct ring_info *rxp;
5526 int i;
5527
5528 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5529 rxp = &tpr->rx_std_buffers[i];
5530
5531 if (rxp->skb == NULL)
5532 continue;
5533
5534 pci_unmap_single(tp->pdev,
5535 pci_unmap_addr(rxp, mapping),
5536 tp->rx_pkt_map_sz,
5537 PCI_DMA_FROMDEVICE);
5538 dev_kfree_skb_any(rxp->skb);
5539 rxp->skb = NULL;
5540 }
5541
5542 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5543 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5544 rxp = &tpr->rx_jmb_buffers[i];
5545
5546 if (rxp->skb == NULL)
5547 continue;
5548
5549 pci_unmap_single(tp->pdev,
5550 pci_unmap_addr(rxp, mapping),
5551 TG3_RX_JMB_MAP_SZ,
5552 PCI_DMA_FROMDEVICE);
5553 dev_kfree_skb_any(rxp->skb);
5554 rxp->skb = NULL;
5555 }
5556 }
5557 }
5558
5559 /* Initialize tx/rx rings for packet processing.
5560 *
5561 * The chip has been shut down and the driver detached from
5562 * the networking, so no interrupts or new tx packets will
5563 * end up in the driver. tp->{tx,}lock are held and thus
5564 * we may not sleep.
5565 */
5566 static int tg3_rx_prodring_alloc(struct tg3 *tp,
5567 struct tg3_rx_prodring_set *tpr)
5568 {
5569 u32 i, rx_pkt_dma_sz;
5570 struct tg3_napi *tnapi = &tp->napi[0];
5571
5572 /* Zero out all descriptors. */
5573 memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
5574
5575 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
5576 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
5577 tp->dev->mtu > ETH_DATA_LEN)
5578 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
5579 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
5580
5581 /* Initialize invariants of the rings, we only set this
5582 * stuff once. This works because the card does not
5583 * write into the rx buffer posting rings.
5584 */
5585 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5586 struct tg3_rx_buffer_desc *rxd;
5587
5588 rxd = &tpr->rx_std[i];
5589 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
5590 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5591 rxd->opaque = (RXD_OPAQUE_RING_STD |
5592 (i << RXD_OPAQUE_INDEX_SHIFT));
5593 }
5594
5595 /* Now allocate fresh SKBs for each rx ring. */
5596 for (i = 0; i < tp->rx_pending; i++) {
5597 if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_STD, -1, i) < 0) {
5598 printk(KERN_WARNING PFX
5599 "%s: Using a smaller RX standard ring, "
5600 "only %d out of %d buffers were allocated "
5601 "successfully.\n",
5602 tp->dev->name, i, tp->rx_pending);
5603 if (i == 0)
5604 goto initfail;
5605 tp->rx_pending = i;
5606 break;
5607 }
5608 }
5609
5610 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
5611 goto done;
5612
5613 memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
5614
5615 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5616 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5617 struct tg3_rx_buffer_desc *rxd;
5618
5619 rxd = &tpr->rx_jmb[i].std;
5620 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
5621 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5622 RXD_FLAG_JUMBO;
5623 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5624 (i << RXD_OPAQUE_INDEX_SHIFT));
5625 }
5626
5627 for (i = 0; i < tp->rx_jumbo_pending; i++) {
5628 if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_JUMBO,
5629 -1, i) < 0) {
5630 printk(KERN_WARNING PFX
5631 "%s: Using a smaller RX jumbo ring, "
5632 "only %d out of %d buffers were "
5633 "allocated successfully.\n",
5634 tp->dev->name, i, tp->rx_jumbo_pending);
5635 if (i == 0)
5636 goto initfail;
5637 tp->rx_jumbo_pending = i;
5638 break;
5639 }
5640 }
5641 }
5642
5643 done:
5644 return 0;
5645
5646 initfail:
5647 tg3_rx_prodring_free(tp, tpr);
5648 return -ENOMEM;
5649 }
5650
5651 static void tg3_rx_prodring_fini(struct tg3 *tp,
5652 struct tg3_rx_prodring_set *tpr)
5653 {
5654 kfree(tpr->rx_std_buffers);
5655 tpr->rx_std_buffers = NULL;
5656 kfree(tpr->rx_jmb_buffers);
5657 tpr->rx_jmb_buffers = NULL;
5658 if (tpr->rx_std) {
5659 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
5660 tpr->rx_std, tpr->rx_std_mapping);
5661 tpr->rx_std = NULL;
5662 }
5663 if (tpr->rx_jmb) {
5664 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5665 tpr->rx_jmb, tpr->rx_jmb_mapping);
5666 tpr->rx_jmb = NULL;
5667 }
5668 }
5669
5670 static int tg3_rx_prodring_init(struct tg3 *tp,
5671 struct tg3_rx_prodring_set *tpr)
5672 {
5673 tpr->rx_std_buffers = kzalloc(sizeof(struct ring_info) *
5674 TG3_RX_RING_SIZE, GFP_KERNEL);
5675 if (!tpr->rx_std_buffers)
5676 return -ENOMEM;
5677
5678 tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5679 &tpr->rx_std_mapping);
5680 if (!tpr->rx_std)
5681 goto err_out;
5682
5683 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5684 tpr->rx_jmb_buffers = kzalloc(sizeof(struct ring_info) *
5685 TG3_RX_JUMBO_RING_SIZE,
5686 GFP_KERNEL);
5687 if (!tpr->rx_jmb_buffers)
5688 goto err_out;
5689
5690 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
5691 TG3_RX_JUMBO_RING_BYTES,
5692 &tpr->rx_jmb_mapping);
5693 if (!tpr->rx_jmb)
5694 goto err_out;
5695 }
5696
5697 return 0;
5698
5699 err_out:
5700 tg3_rx_prodring_fini(tp, tpr);
5701 return -ENOMEM;
5702 }
5703
5704 /* Free up pending packets in all rx/tx rings.
5705 *
5706 * The chip has been shut down and the driver detached from
5707 * the networking, so no interrupts or new tx packets will
5708 * end up in the driver. tp->{tx,}lock is not held and we are not
5709 * in an interrupt context and thus may sleep.
5710 */
5711 static void tg3_free_rings(struct tg3 *tp)
5712 {
5713 int i;
5714
5715 for (i = 0; i < TG3_TX_RING_SIZE; ) {
5716 struct tx_ring_info *txp;
5717 struct sk_buff *skb;
5718
5719 txp = &tp->tx_buffers[i];
5720 skb = txp->skb;
5721
5722 if (skb == NULL) {
5723 i++;
5724 continue;
5725 }
5726
5727 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5728
5729 txp->skb = NULL;
5730
5731 i += skb_shinfo(skb)->nr_frags + 1;
5732
5733 dev_kfree_skb_any(skb);
5734 }
5735
5736 tg3_rx_prodring_free(tp, &tp->prodring[0]);
5737 }
5738
5739 /* Initialize tx/rx rings for packet processing.
5740 *
5741 * The chip has been shut down and the driver detached from
5742 * the networking, so no interrupts or new tx packets will
5743 * end up in the driver. tp->{tx,}lock are held and thus
5744 * we may not sleep.
5745 */
5746 static int tg3_init_rings(struct tg3 *tp)
5747 {
5748 struct tg3_napi *tnapi = &tp->napi[0];
5749
5750 /* Free up all the SKBs. */
5751 tg3_free_rings(tp);
5752
5753 /* Zero out all descriptors. */
5754 memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
5755
5756 tnapi->rx_rcb_ptr = 0;
5757 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5758
5759 return tg3_rx_prodring_alloc(tp, &tp->prodring[0]);
5760 }
5761
5762 /*
5763 * Must not be invoked with interrupt sources disabled and
5764 * the hardware shutdown down.
5765 */
5766 static void tg3_free_consistent(struct tg3 *tp)
5767 {
5768 struct tg3_napi *tnapi = &tp->napi[0];
5769
5770 kfree(tp->tx_buffers);
5771 tp->tx_buffers = NULL;
5772 if (tp->tx_ring) {
5773 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5774 tp->tx_ring, tp->tx_desc_mapping);
5775 tp->tx_ring = NULL;
5776 }
5777 if (tnapi->rx_rcb) {
5778 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5779 tnapi->rx_rcb, tnapi->rx_rcb_mapping);
5780 tnapi->rx_rcb = NULL;
5781 }
5782 if (tnapi->hw_status) {
5783 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5784 tnapi->hw_status,
5785 tnapi->status_mapping);
5786 tnapi->hw_status = NULL;
5787 }
5788 if (tp->hw_stats) {
5789 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5790 tp->hw_stats, tp->stats_mapping);
5791 tp->hw_stats = NULL;
5792 }
5793 tg3_rx_prodring_fini(tp, &tp->prodring[0]);
5794 }
5795
5796 /*
5797 * Must not be invoked with interrupt sources disabled and
5798 * the hardware shutdown down. Can sleep.
5799 */
5800 static int tg3_alloc_consistent(struct tg3 *tp)
5801 {
5802 struct tg3_napi *tnapi = &tp->napi[0];
5803
5804 if (tg3_rx_prodring_init(tp, &tp->prodring[0]))
5805 return -ENOMEM;
5806
5807 tp->tx_buffers = kzalloc(sizeof(struct tx_ring_info) *
5808 TG3_TX_RING_SIZE, GFP_KERNEL);
5809 if (!tp->tx_buffers)
5810 goto err_out;
5811
5812 tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
5813 &tp->tx_desc_mapping);
5814 if (!tp->tx_ring)
5815 goto err_out;
5816
5817 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
5818 TG3_HW_STATUS_SIZE,
5819 &tnapi->status_mapping);
5820 if (!tnapi->hw_status)
5821 goto err_out;
5822
5823 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
5824
5825 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
5826 TG3_RX_RCB_RING_BYTES(tp),
5827 &tnapi->rx_rcb_mapping);
5828 if (!tnapi->rx_rcb)
5829 goto err_out;
5830
5831 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5832
5833 tp->hw_stats = pci_alloc_consistent(tp->pdev,
5834 sizeof(struct tg3_hw_stats),
5835 &tp->stats_mapping);
5836 if (!tp->hw_stats)
5837 goto err_out;
5838
5839 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5840
5841 return 0;
5842
5843 err_out:
5844 tg3_free_consistent(tp);
5845 return -ENOMEM;
5846 }
5847
5848 #define MAX_WAIT_CNT 1000
5849
5850 /* To stop a block, clear the enable bit and poll till it
5851 * clears. tp->lock is held.
5852 */
5853 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
5854 {
5855 unsigned int i;
5856 u32 val;
5857
5858 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5859 switch (ofs) {
5860 case RCVLSC_MODE:
5861 case DMAC_MODE:
5862 case MBFREE_MODE:
5863 case BUFMGR_MODE:
5864 case MEMARB_MODE:
5865 /* We can't enable/disable these bits of the
5866 * 5705/5750, just say success.
5867 */
5868 return 0;
5869
5870 default:
5871 break;
5872 }
5873 }
5874
5875 val = tr32(ofs);
5876 val &= ~enable_bit;
5877 tw32_f(ofs, val);
5878
5879 for (i = 0; i < MAX_WAIT_CNT; i++) {
5880 udelay(100);
5881 val = tr32(ofs);
5882 if ((val & enable_bit) == 0)
5883 break;
5884 }
5885
5886 if (i == MAX_WAIT_CNT && !silent) {
5887 printk(KERN_ERR PFX "tg3_stop_block timed out, "
5888 "ofs=%lx enable_bit=%x\n",
5889 ofs, enable_bit);
5890 return -ENODEV;
5891 }
5892
5893 return 0;
5894 }
5895
5896 /* tp->lock is held. */
5897 static int tg3_abort_hw(struct tg3 *tp, int silent)
5898 {
5899 int i, err;
5900 struct tg3_napi *tnapi = &tp->napi[0];
5901
5902 tg3_disable_ints(tp);
5903
5904 tp->rx_mode &= ~RX_MODE_ENABLE;
5905 tw32_f(MAC_RX_MODE, tp->rx_mode);
5906 udelay(10);
5907
5908 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
5909 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
5910 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
5911 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
5912 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
5913 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
5914
5915 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
5916 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
5917 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
5918 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
5919 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
5920 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
5921 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
5922
5923 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
5924 tw32_f(MAC_MODE, tp->mac_mode);
5925 udelay(40);
5926
5927 tp->tx_mode &= ~TX_MODE_ENABLE;
5928 tw32_f(MAC_TX_MODE, tp->tx_mode);
5929
5930 for (i = 0; i < MAX_WAIT_CNT; i++) {
5931 udelay(100);
5932 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
5933 break;
5934 }
5935 if (i >= MAX_WAIT_CNT) {
5936 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
5937 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
5938 tp->dev->name, tr32(MAC_TX_MODE));
5939 err |= -ENODEV;
5940 }
5941
5942 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
5943 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
5944 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
5945
5946 tw32(FTQ_RESET, 0xffffffff);
5947 tw32(FTQ_RESET, 0x00000000);
5948
5949 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
5950 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
5951
5952 if (tnapi->hw_status)
5953 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
5954 if (tp->hw_stats)
5955 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5956
5957 return err;
5958 }
5959
5960 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
5961 {
5962 int i;
5963 u32 apedata;
5964
5965 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
5966 if (apedata != APE_SEG_SIG_MAGIC)
5967 return;
5968
5969 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
5970 if (!(apedata & APE_FW_STATUS_READY))
5971 return;
5972
5973 /* Wait for up to 1 millisecond for APE to service previous event. */
5974 for (i = 0; i < 10; i++) {
5975 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
5976 return;
5977
5978 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
5979
5980 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5981 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
5982 event | APE_EVENT_STATUS_EVENT_PENDING);
5983
5984 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
5985
5986 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5987 break;
5988
5989 udelay(100);
5990 }
5991
5992 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5993 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
5994 }
5995
5996 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
5997 {
5998 u32 event;
5999 u32 apedata;
6000
6001 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6002 return;
6003
6004 switch (kind) {
6005 case RESET_KIND_INIT:
6006 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6007 APE_HOST_SEG_SIG_MAGIC);
6008 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6009 APE_HOST_SEG_LEN_MAGIC);
6010 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6011 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6012 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6013 APE_HOST_DRIVER_ID_MAGIC);
6014 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6015 APE_HOST_BEHAV_NO_PHYLOCK);
6016
6017 event = APE_EVENT_STATUS_STATE_START;
6018 break;
6019 case RESET_KIND_SHUTDOWN:
6020 /* With the interface we are currently using,
6021 * APE does not track driver state. Wiping
6022 * out the HOST SEGMENT SIGNATURE forces
6023 * the APE to assume OS absent status.
6024 */
6025 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6026
6027 event = APE_EVENT_STATUS_STATE_UNLOAD;
6028 break;
6029 case RESET_KIND_SUSPEND:
6030 event = APE_EVENT_STATUS_STATE_SUSPEND;
6031 break;
6032 default:
6033 return;
6034 }
6035
6036 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6037
6038 tg3_ape_send_event(tp, event);
6039 }
6040
6041 /* tp->lock is held. */
6042 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6043 {
6044 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6045 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6046
6047 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6048 switch (kind) {
6049 case RESET_KIND_INIT:
6050 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6051 DRV_STATE_START);
6052 break;
6053
6054 case RESET_KIND_SHUTDOWN:
6055 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6056 DRV_STATE_UNLOAD);
6057 break;
6058
6059 case RESET_KIND_SUSPEND:
6060 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6061 DRV_STATE_SUSPEND);
6062 break;
6063
6064 default:
6065 break;
6066 }
6067 }
6068
6069 if (kind == RESET_KIND_INIT ||
6070 kind == RESET_KIND_SUSPEND)
6071 tg3_ape_driver_state_change(tp, kind);
6072 }
6073
6074 /* tp->lock is held. */
6075 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6076 {
6077 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6078 switch (kind) {
6079 case RESET_KIND_INIT:
6080 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6081 DRV_STATE_START_DONE);
6082 break;
6083
6084 case RESET_KIND_SHUTDOWN:
6085 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6086 DRV_STATE_UNLOAD_DONE);
6087 break;
6088
6089 default:
6090 break;
6091 }
6092 }
6093
6094 if (kind == RESET_KIND_SHUTDOWN)
6095 tg3_ape_driver_state_change(tp, kind);
6096 }
6097
6098 /* tp->lock is held. */
6099 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6100 {
6101 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6102 switch (kind) {
6103 case RESET_KIND_INIT:
6104 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6105 DRV_STATE_START);
6106 break;
6107
6108 case RESET_KIND_SHUTDOWN:
6109 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6110 DRV_STATE_UNLOAD);
6111 break;
6112
6113 case RESET_KIND_SUSPEND:
6114 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6115 DRV_STATE_SUSPEND);
6116 break;
6117
6118 default:
6119 break;
6120 }
6121 }
6122 }
6123
6124 static int tg3_poll_fw(struct tg3 *tp)
6125 {
6126 int i;
6127 u32 val;
6128
6129 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6130 /* Wait up to 20ms for init done. */
6131 for (i = 0; i < 200; i++) {
6132 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6133 return 0;
6134 udelay(100);
6135 }
6136 return -ENODEV;
6137 }
6138
6139 /* Wait for firmware initialization to complete. */
6140 for (i = 0; i < 100000; i++) {
6141 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6142 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6143 break;
6144 udelay(10);
6145 }
6146
6147 /* Chip might not be fitted with firmware. Some Sun onboard
6148 * parts are configured like that. So don't signal the timeout
6149 * of the above loop as an error, but do report the lack of
6150 * running firmware once.
6151 */
6152 if (i >= 100000 &&
6153 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6154 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6155
6156 printk(KERN_INFO PFX "%s: No firmware running.\n",
6157 tp->dev->name);
6158 }
6159
6160 return 0;
6161 }
6162
6163 /* Save PCI command register before chip reset */
6164 static void tg3_save_pci_state(struct tg3 *tp)
6165 {
6166 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6167 }
6168
6169 /* Restore PCI state after chip reset */
6170 static void tg3_restore_pci_state(struct tg3 *tp)
6171 {
6172 u32 val;
6173
6174 /* Re-enable indirect register accesses. */
6175 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6176 tp->misc_host_ctrl);
6177
6178 /* Set MAX PCI retry to zero. */
6179 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6180 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6181 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6182 val |= PCISTATE_RETRY_SAME_DMA;
6183 /* Allow reads and writes to the APE register and memory space. */
6184 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6185 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6186 PCISTATE_ALLOW_APE_SHMEM_WR;
6187 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6188
6189 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6190
6191 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6192 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6193 pcie_set_readrq(tp->pdev, 4096);
6194 else {
6195 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6196 tp->pci_cacheline_sz);
6197 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6198 tp->pci_lat_timer);
6199 }
6200 }
6201
6202 /* Make sure PCI-X relaxed ordering bit is clear. */
6203 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6204 u16 pcix_cmd;
6205
6206 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6207 &pcix_cmd);
6208 pcix_cmd &= ~PCI_X_CMD_ERO;
6209 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6210 pcix_cmd);
6211 }
6212
6213 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6214
6215 /* Chip reset on 5780 will reset MSI enable bit,
6216 * so need to restore it.
6217 */
6218 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6219 u16 ctrl;
6220
6221 pci_read_config_word(tp->pdev,
6222 tp->msi_cap + PCI_MSI_FLAGS,
6223 &ctrl);
6224 pci_write_config_word(tp->pdev,
6225 tp->msi_cap + PCI_MSI_FLAGS,
6226 ctrl | PCI_MSI_FLAGS_ENABLE);
6227 val = tr32(MSGINT_MODE);
6228 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6229 }
6230 }
6231 }
6232
6233 static void tg3_stop_fw(struct tg3 *);
6234
6235 /* tp->lock is held. */
6236 static int tg3_chip_reset(struct tg3 *tp)
6237 {
6238 u32 val;
6239 void (*write_op)(struct tg3 *, u32, u32);
6240 int err;
6241
6242 tg3_nvram_lock(tp);
6243
6244 tg3_mdio_stop(tp);
6245
6246 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6247
6248 /* No matching tg3_nvram_unlock() after this because
6249 * chip reset below will undo the nvram lock.
6250 */
6251 tp->nvram_lock_cnt = 0;
6252
6253 /* GRC_MISC_CFG core clock reset will clear the memory
6254 * enable bit in PCI register 4 and the MSI enable bit
6255 * on some chips, so we save relevant registers here.
6256 */
6257 tg3_save_pci_state(tp);
6258
6259 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6260 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6261 tw32(GRC_FASTBOOT_PC, 0);
6262
6263 /*
6264 * We must avoid the readl() that normally takes place.
6265 * It locks machines, causes machine checks, and other
6266 * fun things. So, temporarily disable the 5701
6267 * hardware workaround, while we do the reset.
6268 */
6269 write_op = tp->write32;
6270 if (write_op == tg3_write_flush_reg32)
6271 tp->write32 = tg3_write32;
6272
6273 /* Prevent the irq handler from reading or writing PCI registers
6274 * during chip reset when the memory enable bit in the PCI command
6275 * register may be cleared. The chip does not generate interrupt
6276 * at this time, but the irq handler may still be called due to irq
6277 * sharing or irqpoll.
6278 */
6279 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6280 if (tp->napi[0].hw_status) {
6281 tp->napi[0].hw_status->status = 0;
6282 tp->napi[0].hw_status->status_tag = 0;
6283 }
6284 tp->napi[0].last_tag = 0;
6285 tp->napi[0].last_irq_tag = 0;
6286 smp_mb();
6287 synchronize_irq(tp->pdev->irq);
6288
6289 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6290 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6291 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6292 }
6293
6294 /* do the reset */
6295 val = GRC_MISC_CFG_CORECLK_RESET;
6296
6297 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6298 if (tr32(0x7e2c) == 0x60) {
6299 tw32(0x7e2c, 0x20);
6300 }
6301 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6302 tw32(GRC_MISC_CFG, (1 << 29));
6303 val |= (1 << 29);
6304 }
6305 }
6306
6307 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6308 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6309 tw32(GRC_VCPU_EXT_CTRL,
6310 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6311 }
6312
6313 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6314 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6315 tw32(GRC_MISC_CFG, val);
6316
6317 /* restore 5701 hardware bug workaround write method */
6318 tp->write32 = write_op;
6319
6320 /* Unfortunately, we have to delay before the PCI read back.
6321 * Some 575X chips even will not respond to a PCI cfg access
6322 * when the reset command is given to the chip.
6323 *
6324 * How do these hardware designers expect things to work
6325 * properly if the PCI write is posted for a long period
6326 * of time? It is always necessary to have some method by
6327 * which a register read back can occur to push the write
6328 * out which does the reset.
6329 *
6330 * For most tg3 variants the trick below was working.
6331 * Ho hum...
6332 */
6333 udelay(120);
6334
6335 /* Flush PCI posted writes. The normal MMIO registers
6336 * are inaccessible at this time so this is the only
6337 * way to make this reliably (actually, this is no longer
6338 * the case, see above). I tried to use indirect
6339 * register read/write but this upset some 5701 variants.
6340 */
6341 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6342
6343 udelay(120);
6344
6345 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6346 u16 val16;
6347
6348 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6349 int i;
6350 u32 cfg_val;
6351
6352 /* Wait for link training to complete. */
6353 for (i = 0; i < 5000; i++)
6354 udelay(100);
6355
6356 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6357 pci_write_config_dword(tp->pdev, 0xc4,
6358 cfg_val | (1 << 15));
6359 }
6360
6361 /* Clear the "no snoop" and "relaxed ordering" bits. */
6362 pci_read_config_word(tp->pdev,
6363 tp->pcie_cap + PCI_EXP_DEVCTL,
6364 &val16);
6365 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6366 PCI_EXP_DEVCTL_NOSNOOP_EN);
6367 /*
6368 * Older PCIe devices only support the 128 byte
6369 * MPS setting. Enforce the restriction.
6370 */
6371 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6372 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6373 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
6374 pci_write_config_word(tp->pdev,
6375 tp->pcie_cap + PCI_EXP_DEVCTL,
6376 val16);
6377
6378 pcie_set_readrq(tp->pdev, 4096);
6379
6380 /* Clear error status */
6381 pci_write_config_word(tp->pdev,
6382 tp->pcie_cap + PCI_EXP_DEVSTA,
6383 PCI_EXP_DEVSTA_CED |
6384 PCI_EXP_DEVSTA_NFED |
6385 PCI_EXP_DEVSTA_FED |
6386 PCI_EXP_DEVSTA_URD);
6387 }
6388
6389 tg3_restore_pci_state(tp);
6390
6391 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6392
6393 val = 0;
6394 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6395 val = tr32(MEMARB_MODE);
6396 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
6397
6398 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6399 tg3_stop_fw(tp);
6400 tw32(0x5000, 0x400);
6401 }
6402
6403 tw32(GRC_MODE, tp->grc_mode);
6404
6405 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
6406 val = tr32(0xc4);
6407
6408 tw32(0xc4, val | (1 << 15));
6409 }
6410
6411 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6412 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6413 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6414 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6415 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6416 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6417 }
6418
6419 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6420 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6421 tw32_f(MAC_MODE, tp->mac_mode);
6422 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6423 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6424 tw32_f(MAC_MODE, tp->mac_mode);
6425 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6426 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6427 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6428 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6429 tw32_f(MAC_MODE, tp->mac_mode);
6430 } else
6431 tw32_f(MAC_MODE, 0);
6432 udelay(40);
6433
6434 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6435
6436 err = tg3_poll_fw(tp);
6437 if (err)
6438 return err;
6439
6440 tg3_mdio_start(tp);
6441
6442 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6443 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6444 val = tr32(0x7c00);
6445
6446 tw32(0x7c00, val | (1 << 25));
6447 }
6448
6449 /* Reprobe ASF enable state. */
6450 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6451 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6452 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6453 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6454 u32 nic_cfg;
6455
6456 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6457 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6458 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
6459 tp->last_event_jiffies = jiffies;
6460 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
6461 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6462 }
6463 }
6464
6465 return 0;
6466 }
6467
6468 /* tp->lock is held. */
6469 static void tg3_stop_fw(struct tg3 *tp)
6470 {
6471 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6472 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
6473 /* Wait for RX cpu to ACK the previous event. */
6474 tg3_wait_for_event_ack(tp);
6475
6476 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
6477
6478 tg3_generate_fw_event(tp);
6479
6480 /* Wait for RX cpu to ACK this event. */
6481 tg3_wait_for_event_ack(tp);
6482 }
6483 }
6484
6485 /* tp->lock is held. */
6486 static int tg3_halt(struct tg3 *tp, int kind, int silent)
6487 {
6488 int err;
6489
6490 tg3_stop_fw(tp);
6491
6492 tg3_write_sig_pre_reset(tp, kind);
6493
6494 tg3_abort_hw(tp, silent);
6495 err = tg3_chip_reset(tp);
6496
6497 __tg3_set_mac_addr(tp, 0);
6498
6499 tg3_write_sig_legacy(tp, kind);
6500 tg3_write_sig_post_reset(tp, kind);
6501
6502 if (err)
6503 return err;
6504
6505 return 0;
6506 }
6507
6508 #define RX_CPU_SCRATCH_BASE 0x30000
6509 #define RX_CPU_SCRATCH_SIZE 0x04000
6510 #define TX_CPU_SCRATCH_BASE 0x34000
6511 #define TX_CPU_SCRATCH_SIZE 0x04000
6512
6513 /* tp->lock is held. */
6514 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6515 {
6516 int i;
6517
6518 BUG_ON(offset == TX_CPU_BASE &&
6519 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
6520
6521 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6522 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6523
6524 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6525 return 0;
6526 }
6527 if (offset == RX_CPU_BASE) {
6528 for (i = 0; i < 10000; i++) {
6529 tw32(offset + CPU_STATE, 0xffffffff);
6530 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6531 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6532 break;
6533 }
6534
6535 tw32(offset + CPU_STATE, 0xffffffff);
6536 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
6537 udelay(10);
6538 } else {
6539 for (i = 0; i < 10000; i++) {
6540 tw32(offset + CPU_STATE, 0xffffffff);
6541 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6542 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6543 break;
6544 }
6545 }
6546
6547 if (i >= 10000) {
6548 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6549 "and %s CPU\n",
6550 tp->dev->name,
6551 (offset == RX_CPU_BASE ? "RX" : "TX"));
6552 return -ENODEV;
6553 }
6554
6555 /* Clear firmware's nvram arbitration. */
6556 if (tp->tg3_flags & TG3_FLAG_NVRAM)
6557 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
6558 return 0;
6559 }
6560
6561 struct fw_info {
6562 unsigned int fw_base;
6563 unsigned int fw_len;
6564 const __be32 *fw_data;
6565 };
6566
6567 /* tp->lock is held. */
6568 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6569 int cpu_scratch_size, struct fw_info *info)
6570 {
6571 int err, lock_err, i;
6572 void (*write_op)(struct tg3 *, u32, u32);
6573
6574 if (cpu_base == TX_CPU_BASE &&
6575 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6576 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6577 "TX cpu firmware on %s which is 5705.\n",
6578 tp->dev->name);
6579 return -EINVAL;
6580 }
6581
6582 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6583 write_op = tg3_write_mem;
6584 else
6585 write_op = tg3_write_indirect_reg32;
6586
6587 /* It is possible that bootcode is still loading at this point.
6588 * Get the nvram lock first before halting the cpu.
6589 */
6590 lock_err = tg3_nvram_lock(tp);
6591 err = tg3_halt_cpu(tp, cpu_base);
6592 if (!lock_err)
6593 tg3_nvram_unlock(tp);
6594 if (err)
6595 goto out;
6596
6597 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6598 write_op(tp, cpu_scratch_base + i, 0);
6599 tw32(cpu_base + CPU_STATE, 0xffffffff);
6600 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
6601 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
6602 write_op(tp, (cpu_scratch_base +
6603 (info->fw_base & 0xffff) +
6604 (i * sizeof(u32))),
6605 be32_to_cpu(info->fw_data[i]));
6606
6607 err = 0;
6608
6609 out:
6610 return err;
6611 }
6612
6613 /* tp->lock is held. */
6614 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6615 {
6616 struct fw_info info;
6617 const __be32 *fw_data;
6618 int err, i;
6619
6620 fw_data = (void *)tp->fw->data;
6621
6622 /* Firmware blob starts with version numbers, followed by
6623 start address and length. We are setting complete length.
6624 length = end_address_of_bss - start_address_of_text.
6625 Remainder is the blob to be loaded contiguously
6626 from start address. */
6627
6628 info.fw_base = be32_to_cpu(fw_data[1]);
6629 info.fw_len = tp->fw->size - 12;
6630 info.fw_data = &fw_data[3];
6631
6632 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6633 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6634 &info);
6635 if (err)
6636 return err;
6637
6638 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6639 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6640 &info);
6641 if (err)
6642 return err;
6643
6644 /* Now startup only the RX cpu. */
6645 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6646 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6647
6648 for (i = 0; i < 5; i++) {
6649 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
6650 break;
6651 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6652 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
6653 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6654 udelay(1000);
6655 }
6656 if (i >= 5) {
6657 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6658 "to set RX CPU PC, is %08x should be %08x\n",
6659 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
6660 info.fw_base);
6661 return -ENODEV;
6662 }
6663 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6664 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
6665
6666 return 0;
6667 }
6668
6669 /* 5705 needs a special version of the TSO firmware. */
6670
6671 /* tp->lock is held. */
6672 static int tg3_load_tso_firmware(struct tg3 *tp)
6673 {
6674 struct fw_info info;
6675 const __be32 *fw_data;
6676 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6677 int err, i;
6678
6679 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6680 return 0;
6681
6682 fw_data = (void *)tp->fw->data;
6683
6684 /* Firmware blob starts with version numbers, followed by
6685 start address and length. We are setting complete length.
6686 length = end_address_of_bss - start_address_of_text.
6687 Remainder is the blob to be loaded contiguously
6688 from start address. */
6689
6690 info.fw_base = be32_to_cpu(fw_data[1]);
6691 cpu_scratch_size = tp->fw_len;
6692 info.fw_len = tp->fw->size - 12;
6693 info.fw_data = &fw_data[3];
6694
6695 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6696 cpu_base = RX_CPU_BASE;
6697 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
6698 } else {
6699 cpu_base = TX_CPU_BASE;
6700 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6701 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6702 }
6703
6704 err = tg3_load_firmware_cpu(tp, cpu_base,
6705 cpu_scratch_base, cpu_scratch_size,
6706 &info);
6707 if (err)
6708 return err;
6709
6710 /* Now startup the cpu. */
6711 tw32(cpu_base + CPU_STATE, 0xffffffff);
6712 tw32_f(cpu_base + CPU_PC, info.fw_base);
6713
6714 for (i = 0; i < 5; i++) {
6715 if (tr32(cpu_base + CPU_PC) == info.fw_base)
6716 break;
6717 tw32(cpu_base + CPU_STATE, 0xffffffff);
6718 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
6719 tw32_f(cpu_base + CPU_PC, info.fw_base);
6720 udelay(1000);
6721 }
6722 if (i >= 5) {
6723 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6724 "to set CPU PC, is %08x should be %08x\n",
6725 tp->dev->name, tr32(cpu_base + CPU_PC),
6726 info.fw_base);
6727 return -ENODEV;
6728 }
6729 tw32(cpu_base + CPU_STATE, 0xffffffff);
6730 tw32_f(cpu_base + CPU_MODE, 0x00000000);
6731 return 0;
6732 }
6733
6734
6735 static int tg3_set_mac_addr(struct net_device *dev, void *p)
6736 {
6737 struct tg3 *tp = netdev_priv(dev);
6738 struct sockaddr *addr = p;
6739 int err = 0, skip_mac_1 = 0;
6740
6741 if (!is_valid_ether_addr(addr->sa_data))
6742 return -EINVAL;
6743
6744 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6745
6746 if (!netif_running(dev))
6747 return 0;
6748
6749 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6750 u32 addr0_high, addr0_low, addr1_high, addr1_low;
6751
6752 addr0_high = tr32(MAC_ADDR_0_HIGH);
6753 addr0_low = tr32(MAC_ADDR_0_LOW);
6754 addr1_high = tr32(MAC_ADDR_1_HIGH);
6755 addr1_low = tr32(MAC_ADDR_1_LOW);
6756
6757 /* Skip MAC addr 1 if ASF is using it. */
6758 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6759 !(addr1_high == 0 && addr1_low == 0))
6760 skip_mac_1 = 1;
6761 }
6762 spin_lock_bh(&tp->lock);
6763 __tg3_set_mac_addr(tp, skip_mac_1);
6764 spin_unlock_bh(&tp->lock);
6765
6766 return err;
6767 }
6768
6769 /* tp->lock is held. */
6770 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6771 dma_addr_t mapping, u32 maxlen_flags,
6772 u32 nic_addr)
6773 {
6774 tg3_write_mem(tp,
6775 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6776 ((u64) mapping >> 32));
6777 tg3_write_mem(tp,
6778 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6779 ((u64) mapping & 0xffffffff));
6780 tg3_write_mem(tp,
6781 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6782 maxlen_flags);
6783
6784 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6785 tg3_write_mem(tp,
6786 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6787 nic_addr);
6788 }
6789
6790 static void __tg3_set_rx_mode(struct net_device *);
6791 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
6792 {
6793 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6794 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6795 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6796 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6797 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6798 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6799 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6800 }
6801 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6802 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6803 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6804 u32 val = ec->stats_block_coalesce_usecs;
6805
6806 if (!netif_carrier_ok(tp->dev))
6807 val = 0;
6808
6809 tw32(HOSTCC_STAT_COAL_TICKS, val);
6810 }
6811 }
6812
6813 /* tp->lock is held. */
6814 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6815 {
6816 u32 val, rdmac_mode;
6817 int i, err, limit;
6818 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
6819
6820 tg3_disable_ints(tp);
6821
6822 tg3_stop_fw(tp);
6823
6824 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6825
6826 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
6827 tg3_abort_hw(tp, 1);
6828 }
6829
6830 if (reset_phy &&
6831 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
6832 tg3_phy_reset(tp);
6833
6834 err = tg3_chip_reset(tp);
6835 if (err)
6836 return err;
6837
6838 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6839
6840 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
6841 val = tr32(TG3_CPMU_CTRL);
6842 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
6843 tw32(TG3_CPMU_CTRL, val);
6844
6845 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
6846 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
6847 val |= CPMU_LSPD_10MB_MACCLK_6_25;
6848 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
6849
6850 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
6851 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
6852 val |= CPMU_LNK_AWARE_MACCLK_6_25;
6853 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
6854
6855 val = tr32(TG3_CPMU_HST_ACC);
6856 val &= ~CPMU_HST_ACC_MACCLK_MASK;
6857 val |= CPMU_HST_ACC_MACCLK_6_25;
6858 tw32(TG3_CPMU_HST_ACC, val);
6859 }
6860
6861 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6862 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
6863 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
6864 PCIE_PWR_MGMT_L1_THRESH_4MS;
6865 tw32(PCIE_PWR_MGMT_THRESH, val);
6866
6867 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
6868 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
6869
6870 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
6871 }
6872
6873 if (tp->tg3_flags3 & TG3_FLG3_TOGGLE_10_100_L1PLLPD) {
6874 val = tr32(TG3_PCIE_LNKCTL);
6875 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG)
6876 val |= TG3_PCIE_LNKCTL_L1_PLL_PD_DIS;
6877 else
6878 val &= ~TG3_PCIE_LNKCTL_L1_PLL_PD_DIS;
6879 tw32(TG3_PCIE_LNKCTL, val);
6880 }
6881
6882 /* This works around an issue with Athlon chipsets on
6883 * B3 tigon3 silicon. This bit has no effect on any
6884 * other revision. But do not set this on PCI Express
6885 * chips and don't even touch the clocks if the CPMU is present.
6886 */
6887 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
6888 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6889 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6890 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6891 }
6892
6893 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6894 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6895 val = tr32(TG3PCI_PCISTATE);
6896 val |= PCISTATE_RETRY_SAME_DMA;
6897 tw32(TG3PCI_PCISTATE, val);
6898 }
6899
6900 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6901 /* Allow reads and writes to the
6902 * APE register and memory space.
6903 */
6904 val = tr32(TG3PCI_PCISTATE);
6905 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6906 PCISTATE_ALLOW_APE_SHMEM_WR;
6907 tw32(TG3PCI_PCISTATE, val);
6908 }
6909
6910 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6911 /* Enable some hw fixes. */
6912 val = tr32(TG3PCI_MSI_DATA);
6913 val |= (1 << 26) | (1 << 28) | (1 << 29);
6914 tw32(TG3PCI_MSI_DATA, val);
6915 }
6916
6917 /* Descriptor ring init may make accesses to the
6918 * NIC SRAM area to setup the TX descriptors, so we
6919 * can only do this after the hardware has been
6920 * successfully reset.
6921 */
6922 err = tg3_init_rings(tp);
6923 if (err)
6924 return err;
6925
6926 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
6927 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
6928 /* This value is determined during the probe time DMA
6929 * engine test, tg3_test_dma.
6930 */
6931 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
6932 }
6933
6934 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
6935 GRC_MODE_4X_NIC_SEND_RINGS |
6936 GRC_MODE_NO_TX_PHDR_CSUM |
6937 GRC_MODE_NO_RX_PHDR_CSUM);
6938 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
6939
6940 /* Pseudo-header checksum is done by hardware logic and not
6941 * the offload processers, so make the chip do the pseudo-
6942 * header checksums on receive. For transmit it is more
6943 * convenient to do the pseudo-header checksum in software
6944 * as Linux does that on transmit for us in all cases.
6945 */
6946 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
6947
6948 tw32(GRC_MODE,
6949 tp->grc_mode |
6950 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
6951
6952 /* Setup the timer prescalar register. Clock is always 66Mhz. */
6953 val = tr32(GRC_MISC_CFG);
6954 val &= ~0xff;
6955 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
6956 tw32(GRC_MISC_CFG, val);
6957
6958 /* Initialize MBUF/DESC pool. */
6959 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6960 /* Do nothing. */
6961 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
6962 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
6963 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
6964 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
6965 else
6966 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
6967 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
6968 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
6969 }
6970 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6971 int fw_len;
6972
6973 fw_len = tp->fw_len;
6974 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
6975 tw32(BUFMGR_MB_POOL_ADDR,
6976 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6977 tw32(BUFMGR_MB_POOL_SIZE,
6978 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6979 }
6980
6981 if (tp->dev->mtu <= ETH_DATA_LEN) {
6982 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6983 tp->bufmgr_config.mbuf_read_dma_low_water);
6984 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6985 tp->bufmgr_config.mbuf_mac_rx_low_water);
6986 tw32(BUFMGR_MB_HIGH_WATER,
6987 tp->bufmgr_config.mbuf_high_water);
6988 } else {
6989 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6990 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6991 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6992 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
6993 tw32(BUFMGR_MB_HIGH_WATER,
6994 tp->bufmgr_config.mbuf_high_water_jumbo);
6995 }
6996 tw32(BUFMGR_DMA_LOW_WATER,
6997 tp->bufmgr_config.dma_low_water);
6998 tw32(BUFMGR_DMA_HIGH_WATER,
6999 tp->bufmgr_config.dma_high_water);
7000
7001 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7002 for (i = 0; i < 2000; i++) {
7003 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7004 break;
7005 udelay(10);
7006 }
7007 if (i >= 2000) {
7008 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7009 tp->dev->name);
7010 return -ENODEV;
7011 }
7012
7013 /* Setup replenish threshold. */
7014 val = tp->rx_pending / 8;
7015 if (val == 0)
7016 val = 1;
7017 else if (val > tp->rx_std_max_post)
7018 val = tp->rx_std_max_post;
7019 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7020 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7021 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7022
7023 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7024 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7025 }
7026
7027 tw32(RCVBDI_STD_THRESH, val);
7028
7029 /* Initialize TG3_BDINFO's at:
7030 * RCVDBDI_STD_BD: standard eth size rx ring
7031 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7032 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7033 *
7034 * like so:
7035 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7036 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7037 * ring attribute flags
7038 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7039 *
7040 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7041 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7042 *
7043 * The size of each ring is fixed in the firmware, but the location is
7044 * configurable.
7045 */
7046 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7047 ((u64) tpr->rx_std_mapping >> 32));
7048 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7049 ((u64) tpr->rx_std_mapping & 0xffffffff));
7050 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7051 NIC_SRAM_RX_BUFFER_DESC);
7052
7053 /* Disable the mini ring */
7054 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7055 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7056 BDINFO_FLAGS_DISABLED);
7057
7058 /* Program the jumbo buffer descriptor ring control
7059 * blocks on those devices that have them.
7060 */
7061 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7062 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7063 /* Setup replenish threshold. */
7064 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7065
7066 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7067 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7068 ((u64) tpr->rx_jmb_mapping >> 32));
7069 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7070 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7071 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7072 (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7073 BDINFO_FLAGS_USE_EXT_RECV);
7074 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7075 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7076 } else {
7077 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7078 BDINFO_FLAGS_DISABLED);
7079 }
7080
7081 val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
7082 } else
7083 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7084
7085 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7086
7087 /* There is only one send ring on 5705/5750, no need to explicitly
7088 * disable the others.
7089 */
7090 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7091 /* Clear out send RCB ring in SRAM. */
7092 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
7093 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
7094 BDINFO_FLAGS_DISABLED);
7095 }
7096
7097 tp->tx_prod = 0;
7098 tp->tx_cons = 0;
7099 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
7100 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
7101
7102 tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
7103 tp->tx_desc_mapping,
7104 (TG3_TX_RING_SIZE <<
7105 BDINFO_FLAGS_MAXLEN_SHIFT),
7106 NIC_SRAM_TX_BUFFER_DESC);
7107
7108 /* There is only one receive return ring on 5705/5750, no need
7109 * to explicitly disable the others.
7110 */
7111 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7112 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
7113 i += TG3_BDINFO_SIZE) {
7114 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
7115 BDINFO_FLAGS_DISABLED);
7116 }
7117 }
7118
7119 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7120
7121 tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
7122 tp->napi[0].rx_rcb_mapping,
7123 (TG3_RX_RCB_RING_SIZE(tp) <<
7124 BDINFO_FLAGS_MAXLEN_SHIFT),
7125 0);
7126
7127 tpr->rx_std_ptr = tp->rx_pending;
7128 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
7129 tpr->rx_std_ptr);
7130
7131 tpr->rx_jmb_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7132 tp->rx_jumbo_pending : 0;
7133 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
7134 tpr->rx_jmb_ptr);
7135
7136 /* Initialize MAC address and backoff seed. */
7137 __tg3_set_mac_addr(tp, 0);
7138
7139 /* MTU + ethernet header + FCS + optional VLAN tag */
7140 tw32(MAC_RX_MTU_SIZE,
7141 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7142
7143 /* The slot time is changed by tg3_setup_phy if we
7144 * run at gigabit with half duplex.
7145 */
7146 tw32(MAC_TX_LENGTHS,
7147 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7148 (6 << TX_LENGTHS_IPG_SHIFT) |
7149 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7150
7151 /* Receive rules. */
7152 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7153 tw32(RCVLPC_CONFIG, 0x0181);
7154
7155 /* Calculate RDMAC_MODE setting early, we need it to determine
7156 * the RCVLPC_STATE_ENABLE mask.
7157 */
7158 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7159 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7160 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7161 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7162 RDMAC_MODE_LNGREAD_ENAB);
7163
7164 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7165 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7166 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7167 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7168 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7169 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7170
7171 /* If statement applies to 5705 and 5750 PCI devices only */
7172 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7173 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7174 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7175 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7176 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7177 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7178 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7179 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7180 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7181 }
7182 }
7183
7184 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7185 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7186
7187 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7188 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7189
7190 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7191 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7192 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
7193
7194 /* Receive/send statistics. */
7195 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7196 val = tr32(RCVLPC_STATS_ENABLE);
7197 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7198 tw32(RCVLPC_STATS_ENABLE, val);
7199 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7200 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7201 val = tr32(RCVLPC_STATS_ENABLE);
7202 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7203 tw32(RCVLPC_STATS_ENABLE, val);
7204 } else {
7205 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7206 }
7207 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7208 tw32(SNDDATAI_STATSENAB, 0xffffff);
7209 tw32(SNDDATAI_STATSCTRL,
7210 (SNDDATAI_SCTRL_ENABLE |
7211 SNDDATAI_SCTRL_FASTUPD));
7212
7213 /* Setup host coalescing engine. */
7214 tw32(HOSTCC_MODE, 0);
7215 for (i = 0; i < 2000; i++) {
7216 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7217 break;
7218 udelay(10);
7219 }
7220
7221 __tg3_set_coalesce(tp, &tp->coal);
7222
7223 /* set status block DMA address */
7224 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7225 ((u64) tp->napi[0].status_mapping >> 32));
7226 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7227 ((u64) tp->napi[0].status_mapping & 0xffffffff));
7228
7229 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7230 /* Status/statistics block address. See tg3_timer,
7231 * the tg3_periodic_fetch_stats call there, and
7232 * tg3_get_stats to see how this works for 5705/5750 chips.
7233 */
7234 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7235 ((u64) tp->stats_mapping >> 32));
7236 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7237 ((u64) tp->stats_mapping & 0xffffffff));
7238 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7239 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7240 }
7241
7242 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7243
7244 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7245 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7246 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7247 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7248
7249 /* Clear statistics/status block in chip, and status block in ram. */
7250 for (i = NIC_SRAM_STATS_BLK;
7251 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7252 i += sizeof(u32)) {
7253 tg3_write_mem(tp, i, 0);
7254 udelay(40);
7255 }
7256 memset(tp->napi[0].hw_status, 0, TG3_HW_STATUS_SIZE);
7257
7258 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7259 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7260 /* reset to prevent losing 1st rx packet intermittently */
7261 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7262 udelay(10);
7263 }
7264
7265 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7266 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7267 else
7268 tp->mac_mode = 0;
7269 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
7270 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
7271 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7272 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7273 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7274 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7275 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7276 udelay(40);
7277
7278 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
7279 * If TG3_FLG2_IS_NIC is zero, we should read the
7280 * register to preserve the GPIO settings for LOMs. The GPIOs,
7281 * whether used as inputs or outputs, are set by boot code after
7282 * reset.
7283 */
7284 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
7285 u32 gpio_mask;
7286
7287 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7288 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7289 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
7290
7291 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7292 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7293 GRC_LCLCTRL_GPIO_OUTPUT3;
7294
7295 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7296 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7297
7298 tp->grc_local_ctrl &= ~gpio_mask;
7299 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7300
7301 /* GPIO1 must be driven high for eeprom write protect */
7302 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7303 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7304 GRC_LCLCTRL_GPIO_OUTPUT1);
7305 }
7306 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7307 udelay(100);
7308
7309 tw32_mailbox_f(tp->napi[0].int_mbox, 0);
7310
7311 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7312 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7313 udelay(40);
7314 }
7315
7316 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7317 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7318 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7319 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7320 WDMAC_MODE_LNGREAD_ENAB);
7321
7322 /* If statement applies to 5705 and 5750 PCI devices only */
7323 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7324 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7325 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
7326 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
7327 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7328 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7329 /* nothing */
7330 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7331 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7332 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7333 val |= WDMAC_MODE_RX_ACCEL;
7334 }
7335 }
7336
7337 /* Enable host coalescing bug fix */
7338 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7339 val |= WDMAC_MODE_STATUS_TAG_FIX;
7340
7341 tw32_f(WDMAC_MODE, val);
7342 udelay(40);
7343
7344 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7345 u16 pcix_cmd;
7346
7347 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7348 &pcix_cmd);
7349 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
7350 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7351 pcix_cmd |= PCI_X_CMD_READ_2K;
7352 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
7353 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7354 pcix_cmd |= PCI_X_CMD_READ_2K;
7355 }
7356 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7357 pcix_cmd);
7358 }
7359
7360 tw32_f(RDMAC_MODE, rdmac_mode);
7361 udelay(40);
7362
7363 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7364 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7365 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
7366
7367 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7368 tw32(SNDDATAC_MODE,
7369 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7370 else
7371 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7372
7373 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7374 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7375 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7376 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
7377 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7378 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
7379 tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
7380 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7381
7382 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7383 err = tg3_load_5701_a0_firmware_fix(tp);
7384 if (err)
7385 return err;
7386 }
7387
7388 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7389 err = tg3_load_tso_firmware(tp);
7390 if (err)
7391 return err;
7392 }
7393
7394 tp->tx_mode = TX_MODE_ENABLE;
7395 tw32_f(MAC_TX_MODE, tp->tx_mode);
7396 udelay(100);
7397
7398 tp->rx_mode = RX_MODE_ENABLE;
7399 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7400 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7401
7402 tw32_f(MAC_RX_MODE, tp->rx_mode);
7403 udelay(10);
7404
7405 tw32(MAC_LED_CTRL, tp->led_ctrl);
7406
7407 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
7408 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7409 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7410 udelay(10);
7411 }
7412 tw32_f(MAC_RX_MODE, tp->rx_mode);
7413 udelay(10);
7414
7415 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7416 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7417 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7418 /* Set drive transmission level to 1.2V */
7419 /* only if the signal pre-emphasis bit is not set */
7420 val = tr32(MAC_SERDES_CFG);
7421 val &= 0xfffff000;
7422 val |= 0x880;
7423 tw32(MAC_SERDES_CFG, val);
7424 }
7425 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7426 tw32(MAC_SERDES_CFG, 0x616000);
7427 }
7428
7429 /* Prevent chip from dropping frames when flow control
7430 * is enabled.
7431 */
7432 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7433
7434 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7435 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7436 /* Use hardware link auto-negotiation */
7437 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7438 }
7439
7440 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7441 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7442 u32 tmp;
7443
7444 tmp = tr32(SERDES_RX_CTRL);
7445 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7446 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7447 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7448 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7449 }
7450
7451 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7452 if (tp->link_config.phy_is_low_power) {
7453 tp->link_config.phy_is_low_power = 0;
7454 tp->link_config.speed = tp->link_config.orig_speed;
7455 tp->link_config.duplex = tp->link_config.orig_duplex;
7456 tp->link_config.autoneg = tp->link_config.orig_autoneg;
7457 }
7458
7459 err = tg3_setup_phy(tp, 0);
7460 if (err)
7461 return err;
7462
7463 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7464 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
7465 u32 tmp;
7466
7467 /* Clear CRC stats. */
7468 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7469 tg3_writephy(tp, MII_TG3_TEST1,
7470 tmp | MII_TG3_TEST1_CRC_EN);
7471 tg3_readphy(tp, 0x14, &tmp);
7472 }
7473 }
7474 }
7475
7476 __tg3_set_rx_mode(tp->dev);
7477
7478 /* Initialize receive rules. */
7479 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
7480 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7481 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
7482 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7483
7484 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7485 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
7486 limit = 8;
7487 else
7488 limit = 16;
7489 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7490 limit -= 4;
7491 switch (limit) {
7492 case 16:
7493 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
7494 case 15:
7495 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
7496 case 14:
7497 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
7498 case 13:
7499 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
7500 case 12:
7501 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
7502 case 11:
7503 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
7504 case 10:
7505 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
7506 case 9:
7507 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
7508 case 8:
7509 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
7510 case 7:
7511 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
7512 case 6:
7513 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
7514 case 5:
7515 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
7516 case 4:
7517 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
7518 case 3:
7519 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
7520 case 2:
7521 case 1:
7522
7523 default:
7524 break;
7525 }
7526
7527 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7528 /* Write our heartbeat update interval to APE. */
7529 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7530 APE_HOST_HEARTBEAT_INT_DISABLE);
7531
7532 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7533
7534 return 0;
7535 }
7536
7537 /* Called at device open time to get the chip ready for
7538 * packet processing. Invoked with tp->lock held.
7539 */
7540 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
7541 {
7542 tg3_switch_clocks(tp);
7543
7544 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7545
7546 return tg3_reset_hw(tp, reset_phy);
7547 }
7548
7549 #define TG3_STAT_ADD32(PSTAT, REG) \
7550 do { u32 __val = tr32(REG); \
7551 (PSTAT)->low += __val; \
7552 if ((PSTAT)->low < __val) \
7553 (PSTAT)->high += 1; \
7554 } while (0)
7555
7556 static void tg3_periodic_fetch_stats(struct tg3 *tp)
7557 {
7558 struct tg3_hw_stats *sp = tp->hw_stats;
7559
7560 if (!netif_carrier_ok(tp->dev))
7561 return;
7562
7563 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7564 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7565 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7566 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7567 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7568 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7569 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7570 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7571 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7572 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7573 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7574 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7575 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7576
7577 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7578 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7579 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7580 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7581 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7582 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7583 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7584 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7585 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7586 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7587 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7588 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7589 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7590 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
7591
7592 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7593 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7594 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
7595 }
7596
7597 static void tg3_timer(unsigned long __opaque)
7598 {
7599 struct tg3 *tp = (struct tg3 *) __opaque;
7600
7601 if (tp->irq_sync)
7602 goto restart_timer;
7603
7604 spin_lock(&tp->lock);
7605
7606 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7607 /* All of this garbage is because when using non-tagged
7608 * IRQ status the mailbox/status_block protocol the chip
7609 * uses with the cpu is race prone.
7610 */
7611 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
7612 tw32(GRC_LOCAL_CTRL,
7613 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7614 } else {
7615 tw32(HOSTCC_MODE, tp->coalesce_mode |
7616 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
7617 }
7618
7619 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7620 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
7621 spin_unlock(&tp->lock);
7622 schedule_work(&tp->reset_task);
7623 return;
7624 }
7625 }
7626
7627 /* This part only runs once per second. */
7628 if (!--tp->timer_counter) {
7629 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7630 tg3_periodic_fetch_stats(tp);
7631
7632 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7633 u32 mac_stat;
7634 int phy_event;
7635
7636 mac_stat = tr32(MAC_STATUS);
7637
7638 phy_event = 0;
7639 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
7640 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
7641 phy_event = 1;
7642 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
7643 phy_event = 1;
7644
7645 if (phy_event)
7646 tg3_setup_phy(tp, 0);
7647 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
7648 u32 mac_stat = tr32(MAC_STATUS);
7649 int need_setup = 0;
7650
7651 if (netif_carrier_ok(tp->dev) &&
7652 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
7653 need_setup = 1;
7654 }
7655 if (! netif_carrier_ok(tp->dev) &&
7656 (mac_stat & (MAC_STATUS_PCS_SYNCED |
7657 MAC_STATUS_SIGNAL_DET))) {
7658 need_setup = 1;
7659 }
7660 if (need_setup) {
7661 if (!tp->serdes_counter) {
7662 tw32_f(MAC_MODE,
7663 (tp->mac_mode &
7664 ~MAC_MODE_PORT_MODE_MASK));
7665 udelay(40);
7666 tw32_f(MAC_MODE, tp->mac_mode);
7667 udelay(40);
7668 }
7669 tg3_setup_phy(tp, 0);
7670 }
7671 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
7672 tg3_serdes_parallel_detect(tp);
7673
7674 tp->timer_counter = tp->timer_multiplier;
7675 }
7676
7677 /* Heartbeat is only sent once every 2 seconds.
7678 *
7679 * The heartbeat is to tell the ASF firmware that the host
7680 * driver is still alive. In the event that the OS crashes,
7681 * ASF needs to reset the hardware to free up the FIFO space
7682 * that may be filled with rx packets destined for the host.
7683 * If the FIFO is full, ASF will no longer function properly.
7684 *
7685 * Unintended resets have been reported on real time kernels
7686 * where the timer doesn't run on time. Netpoll will also have
7687 * same problem.
7688 *
7689 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
7690 * to check the ring condition when the heartbeat is expiring
7691 * before doing the reset. This will prevent most unintended
7692 * resets.
7693 */
7694 if (!--tp->asf_counter) {
7695 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7696 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7697 tg3_wait_for_event_ack(tp);
7698
7699 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
7700 FWCMD_NICDRV_ALIVE3);
7701 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
7702 /* 5 seconds timeout */
7703 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
7704
7705 tg3_generate_fw_event(tp);
7706 }
7707 tp->asf_counter = tp->asf_multiplier;
7708 }
7709
7710 spin_unlock(&tp->lock);
7711
7712 restart_timer:
7713 tp->timer.expires = jiffies + tp->timer_offset;
7714 add_timer(&tp->timer);
7715 }
7716
7717 static int tg3_request_irq(struct tg3 *tp)
7718 {
7719 irq_handler_t fn;
7720 unsigned long flags;
7721 char *name = tp->dev->name;
7722
7723 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7724 fn = tg3_msi;
7725 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
7726 fn = tg3_msi_1shot;
7727 flags = IRQF_SAMPLE_RANDOM;
7728 } else {
7729 fn = tg3_interrupt;
7730 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7731 fn = tg3_interrupt_tagged;
7732 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
7733 }
7734 return request_irq(tp->pdev->irq, fn, flags, name, &tp->napi[0]);
7735 }
7736
7737 static int tg3_test_interrupt(struct tg3 *tp)
7738 {
7739 struct tg3_napi *tnapi = &tp->napi[0];
7740 struct net_device *dev = tp->dev;
7741 int err, i, intr_ok = 0;
7742
7743 if (!netif_running(dev))
7744 return -ENODEV;
7745
7746 tg3_disable_ints(tp);
7747
7748 free_irq(tp->pdev->irq, tnapi);
7749
7750 err = request_irq(tp->pdev->irq, tg3_test_isr,
7751 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
7752 if (err)
7753 return err;
7754
7755 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
7756 tg3_enable_ints(tp);
7757
7758 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
7759 HOSTCC_MODE_NOW);
7760
7761 for (i = 0; i < 5; i++) {
7762 u32 int_mbox, misc_host_ctrl;
7763
7764 int_mbox = tr32_mailbox(tnapi->int_mbox);
7765 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
7766
7767 if ((int_mbox != 0) ||
7768 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
7769 intr_ok = 1;
7770 break;
7771 }
7772
7773 msleep(10);
7774 }
7775
7776 tg3_disable_ints(tp);
7777
7778 free_irq(tp->pdev->irq, tnapi);
7779
7780 err = tg3_request_irq(tp);
7781
7782 if (err)
7783 return err;
7784
7785 if (intr_ok)
7786 return 0;
7787
7788 return -EIO;
7789 }
7790
7791 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
7792 * successfully restored
7793 */
7794 static int tg3_test_msi(struct tg3 *tp)
7795 {
7796 int err;
7797 u16 pci_cmd;
7798
7799 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
7800 return 0;
7801
7802 /* Turn off SERR reporting in case MSI terminates with Master
7803 * Abort.
7804 */
7805 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
7806 pci_write_config_word(tp->pdev, PCI_COMMAND,
7807 pci_cmd & ~PCI_COMMAND_SERR);
7808
7809 err = tg3_test_interrupt(tp);
7810
7811 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
7812
7813 if (!err)
7814 return 0;
7815
7816 /* other failures */
7817 if (err != -EIO)
7818 return err;
7819
7820 /* MSI test failed, go back to INTx mode */
7821 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
7822 "switching to INTx mode. Please report this failure to "
7823 "the PCI maintainer and include system chipset information.\n",
7824 tp->dev->name);
7825
7826 free_irq(tp->pdev->irq, &tp->napi[0]);
7827
7828 pci_disable_msi(tp->pdev);
7829
7830 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7831
7832 err = tg3_request_irq(tp);
7833 if (err)
7834 return err;
7835
7836 /* Need to reset the chip because the MSI cycle may have terminated
7837 * with Master Abort.
7838 */
7839 tg3_full_lock(tp, 1);
7840
7841 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7842 err = tg3_init_hw(tp, 1);
7843
7844 tg3_full_unlock(tp);
7845
7846 if (err)
7847 free_irq(tp->pdev->irq, &tp->napi[0]);
7848
7849 return err;
7850 }
7851
7852 static int tg3_request_firmware(struct tg3 *tp)
7853 {
7854 const __be32 *fw_data;
7855
7856 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
7857 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
7858 tp->dev->name, tp->fw_needed);
7859 return -ENOENT;
7860 }
7861
7862 fw_data = (void *)tp->fw->data;
7863
7864 /* Firmware blob starts with version numbers, followed by
7865 * start address and _full_ length including BSS sections
7866 * (which must be longer than the actual data, of course
7867 */
7868
7869 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
7870 if (tp->fw_len < (tp->fw->size - 12)) {
7871 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
7872 tp->dev->name, tp->fw_len, tp->fw_needed);
7873 release_firmware(tp->fw);
7874 tp->fw = NULL;
7875 return -EINVAL;
7876 }
7877
7878 /* We no longer need firmware; we have it. */
7879 tp->fw_needed = NULL;
7880 return 0;
7881 }
7882
7883 static void tg3_ints_init(struct tg3 *tp)
7884 {
7885 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
7886 /* All MSI supporting chips should support tagged
7887 * status. Assert that this is the case.
7888 */
7889 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7890 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7891 "Not using MSI.\n", tp->dev->name);
7892 } else if (pci_enable_msi(tp->pdev) == 0) {
7893 u32 msi_mode;
7894
7895 msi_mode = tr32(MSGINT_MODE);
7896 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7897 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7898 }
7899 }
7900 }
7901
7902 static void tg3_ints_fini(struct tg3 *tp)
7903 {
7904 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7905 pci_disable_msi(tp->pdev);
7906 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7907 }
7908 }
7909
7910 static int tg3_open(struct net_device *dev)
7911 {
7912 struct tg3 *tp = netdev_priv(dev);
7913 int err;
7914
7915 if (tp->fw_needed) {
7916 err = tg3_request_firmware(tp);
7917 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7918 if (err)
7919 return err;
7920 } else if (err) {
7921 printk(KERN_WARNING "%s: TSO capability disabled.\n",
7922 tp->dev->name);
7923 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
7924 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7925 printk(KERN_NOTICE "%s: TSO capability restored.\n",
7926 tp->dev->name);
7927 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
7928 }
7929 }
7930
7931 netif_carrier_off(tp->dev);
7932
7933 err = tg3_set_power_state(tp, PCI_D0);
7934 if (err)
7935 return err;
7936
7937 tg3_full_lock(tp, 0);
7938
7939 tg3_disable_ints(tp);
7940 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7941
7942 tg3_full_unlock(tp);
7943
7944 /* The placement of this call is tied
7945 * to the setup and use of Host TX descriptors.
7946 */
7947 err = tg3_alloc_consistent(tp);
7948 if (err)
7949 return err;
7950
7951 tg3_ints_init(tp);
7952
7953 napi_enable(&tp->napi[0].napi);
7954
7955 err = tg3_request_irq(tp);
7956
7957 if (err)
7958 goto err_out1;
7959
7960 tg3_full_lock(tp, 0);
7961
7962 err = tg3_init_hw(tp, 1);
7963 if (err) {
7964 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7965 tg3_free_rings(tp);
7966 } else {
7967 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7968 tp->timer_offset = HZ;
7969 else
7970 tp->timer_offset = HZ / 10;
7971
7972 BUG_ON(tp->timer_offset > HZ);
7973 tp->timer_counter = tp->timer_multiplier =
7974 (HZ / tp->timer_offset);
7975 tp->asf_counter = tp->asf_multiplier =
7976 ((HZ / tp->timer_offset) * 2);
7977
7978 init_timer(&tp->timer);
7979 tp->timer.expires = jiffies + tp->timer_offset;
7980 tp->timer.data = (unsigned long) tp;
7981 tp->timer.function = tg3_timer;
7982 }
7983
7984 tg3_full_unlock(tp);
7985
7986 if (err)
7987 goto err_out2;
7988
7989 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7990 err = tg3_test_msi(tp);
7991
7992 if (err) {
7993 tg3_full_lock(tp, 0);
7994 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7995 tg3_free_rings(tp);
7996 tg3_full_unlock(tp);
7997
7998 goto err_out1;
7999 }
8000
8001 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8002 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
8003 u32 val = tr32(PCIE_TRANSACTION_CFG);
8004
8005 tw32(PCIE_TRANSACTION_CFG,
8006 val | PCIE_TRANS_CFG_1SHOT_MSI);
8007 }
8008 }
8009 }
8010
8011 tg3_phy_start(tp);
8012
8013 tg3_full_lock(tp, 0);
8014
8015 add_timer(&tp->timer);
8016 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8017 tg3_enable_ints(tp);
8018
8019 tg3_full_unlock(tp);
8020
8021 netif_start_queue(dev);
8022
8023 return 0;
8024
8025 err_out2:
8026 free_irq(tp->pdev->irq, &tp->napi[0]);
8027
8028 err_out1:
8029 napi_disable(&tp->napi[0].napi);
8030 tg3_ints_fini(tp);
8031 tg3_free_consistent(tp);
8032 return err;
8033 }
8034
8035 #if 0
8036 /*static*/ void tg3_dump_state(struct tg3 *tp)
8037 {
8038 u32 val32, val32_2, val32_3, val32_4, val32_5;
8039 u16 val16;
8040 int i;
8041 struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
8042
8043 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8044 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8045 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8046 val16, val32);
8047
8048 /* MAC block */
8049 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8050 tr32(MAC_MODE), tr32(MAC_STATUS));
8051 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8052 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8053 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8054 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8055 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8056 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8057
8058 /* Send data initiator control block */
8059 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8060 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8061 printk(" SNDDATAI_STATSCTRL[%08x]\n",
8062 tr32(SNDDATAI_STATSCTRL));
8063
8064 /* Send data completion control block */
8065 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8066
8067 /* Send BD ring selector block */
8068 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8069 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8070
8071 /* Send BD initiator control block */
8072 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8073 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8074
8075 /* Send BD completion control block */
8076 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8077
8078 /* Receive list placement control block */
8079 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8080 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8081 printk(" RCVLPC_STATSCTRL[%08x]\n",
8082 tr32(RCVLPC_STATSCTRL));
8083
8084 /* Receive data and receive BD initiator control block */
8085 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8086 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8087
8088 /* Receive data completion control block */
8089 printk("DEBUG: RCVDCC_MODE[%08x]\n",
8090 tr32(RCVDCC_MODE));
8091
8092 /* Receive BD initiator control block */
8093 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8094 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8095
8096 /* Receive BD completion control block */
8097 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8098 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8099
8100 /* Receive list selector control block */
8101 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8102 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8103
8104 /* Mbuf cluster free block */
8105 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8106 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8107
8108 /* Host coalescing control block */
8109 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8110 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8111 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8112 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8113 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8114 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8115 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8116 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8117 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8118 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8119 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8120 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8121
8122 /* Memory arbiter control block */
8123 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8124 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8125
8126 /* Buffer manager control block */
8127 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8128 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8129 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8130 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8131 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8132 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8133 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8134 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8135
8136 /* Read DMA control block */
8137 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8138 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8139
8140 /* Write DMA control block */
8141 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8142 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8143
8144 /* DMA completion block */
8145 printk("DEBUG: DMAC_MODE[%08x]\n",
8146 tr32(DMAC_MODE));
8147
8148 /* GRC block */
8149 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8150 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8151 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8152 tr32(GRC_LOCAL_CTRL));
8153
8154 /* TG3_BDINFOs */
8155 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8156 tr32(RCVDBDI_JUMBO_BD + 0x0),
8157 tr32(RCVDBDI_JUMBO_BD + 0x4),
8158 tr32(RCVDBDI_JUMBO_BD + 0x8),
8159 tr32(RCVDBDI_JUMBO_BD + 0xc));
8160 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8161 tr32(RCVDBDI_STD_BD + 0x0),
8162 tr32(RCVDBDI_STD_BD + 0x4),
8163 tr32(RCVDBDI_STD_BD + 0x8),
8164 tr32(RCVDBDI_STD_BD + 0xc));
8165 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8166 tr32(RCVDBDI_MINI_BD + 0x0),
8167 tr32(RCVDBDI_MINI_BD + 0x4),
8168 tr32(RCVDBDI_MINI_BD + 0x8),
8169 tr32(RCVDBDI_MINI_BD + 0xc));
8170
8171 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8172 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8173 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8174 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8175 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8176 val32, val32_2, val32_3, val32_4);
8177
8178 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8179 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8180 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8181 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8182 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8183 val32, val32_2, val32_3, val32_4);
8184
8185 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8186 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8187 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8188 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8189 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8190 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8191 val32, val32_2, val32_3, val32_4, val32_5);
8192
8193 /* SW status block */
8194 printk(KERN_DEBUG
8195 "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8196 sblk->status,
8197 sblk->status_tag,
8198 sblk->rx_jumbo_consumer,
8199 sblk->rx_consumer,
8200 sblk->rx_mini_consumer,
8201 sblk->idx[0].rx_producer,
8202 sblk->idx[0].tx_consumer);
8203
8204 /* SW statistics block */
8205 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8206 ((u32 *)tp->hw_stats)[0],
8207 ((u32 *)tp->hw_stats)[1],
8208 ((u32 *)tp->hw_stats)[2],
8209 ((u32 *)tp->hw_stats)[3]);
8210
8211 /* Mailboxes */
8212 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
8213 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8214 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8215 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8216 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
8217
8218 /* NIC side send descriptors. */
8219 for (i = 0; i < 6; i++) {
8220 unsigned long txd;
8221
8222 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8223 + (i * sizeof(struct tg3_tx_buffer_desc));
8224 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8225 i,
8226 readl(txd + 0x0), readl(txd + 0x4),
8227 readl(txd + 0x8), readl(txd + 0xc));
8228 }
8229
8230 /* NIC side RX descriptors. */
8231 for (i = 0; i < 6; i++) {
8232 unsigned long rxd;
8233
8234 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8235 + (i * sizeof(struct tg3_rx_buffer_desc));
8236 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8237 i,
8238 readl(rxd + 0x0), readl(rxd + 0x4),
8239 readl(rxd + 0x8), readl(rxd + 0xc));
8240 rxd += (4 * sizeof(u32));
8241 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8242 i,
8243 readl(rxd + 0x0), readl(rxd + 0x4),
8244 readl(rxd + 0x8), readl(rxd + 0xc));
8245 }
8246
8247 for (i = 0; i < 6; i++) {
8248 unsigned long rxd;
8249
8250 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8251 + (i * sizeof(struct tg3_rx_buffer_desc));
8252 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8253 i,
8254 readl(rxd + 0x0), readl(rxd + 0x4),
8255 readl(rxd + 0x8), readl(rxd + 0xc));
8256 rxd += (4 * sizeof(u32));
8257 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8258 i,
8259 readl(rxd + 0x0), readl(rxd + 0x4),
8260 readl(rxd + 0x8), readl(rxd + 0xc));
8261 }
8262 }
8263 #endif
8264
8265 static struct net_device_stats *tg3_get_stats(struct net_device *);
8266 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8267
8268 static int tg3_close(struct net_device *dev)
8269 {
8270 struct tg3 *tp = netdev_priv(dev);
8271
8272 napi_disable(&tp->napi[0].napi);
8273 cancel_work_sync(&tp->reset_task);
8274
8275 netif_stop_queue(dev);
8276
8277 del_timer_sync(&tp->timer);
8278
8279 tg3_full_lock(tp, 1);
8280 #if 0
8281 tg3_dump_state(tp);
8282 #endif
8283
8284 tg3_disable_ints(tp);
8285
8286 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8287 tg3_free_rings(tp);
8288 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8289
8290 tg3_full_unlock(tp);
8291
8292 free_irq(tp->pdev->irq, &tp->napi[0]);
8293
8294 tg3_ints_fini(tp);
8295
8296 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8297 sizeof(tp->net_stats_prev));
8298 memcpy(&tp->estats_prev, tg3_get_estats(tp),
8299 sizeof(tp->estats_prev));
8300
8301 tg3_free_consistent(tp);
8302
8303 tg3_set_power_state(tp, PCI_D3hot);
8304
8305 netif_carrier_off(tp->dev);
8306
8307 return 0;
8308 }
8309
8310 static inline unsigned long get_stat64(tg3_stat64_t *val)
8311 {
8312 unsigned long ret;
8313
8314 #if (BITS_PER_LONG == 32)
8315 ret = val->low;
8316 #else
8317 ret = ((u64)val->high << 32) | ((u64)val->low);
8318 #endif
8319 return ret;
8320 }
8321
8322 static inline u64 get_estat64(tg3_stat64_t *val)
8323 {
8324 return ((u64)val->high << 32) | ((u64)val->low);
8325 }
8326
8327 static unsigned long calc_crc_errors(struct tg3 *tp)
8328 {
8329 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8330
8331 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8332 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8333 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
8334 u32 val;
8335
8336 spin_lock_bh(&tp->lock);
8337 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8338 tg3_writephy(tp, MII_TG3_TEST1,
8339 val | MII_TG3_TEST1_CRC_EN);
8340 tg3_readphy(tp, 0x14, &val);
8341 } else
8342 val = 0;
8343 spin_unlock_bh(&tp->lock);
8344
8345 tp->phy_crc_errors += val;
8346
8347 return tp->phy_crc_errors;
8348 }
8349
8350 return get_stat64(&hw_stats->rx_fcs_errors);
8351 }
8352
8353 #define ESTAT_ADD(member) \
8354 estats->member = old_estats->member + \
8355 get_estat64(&hw_stats->member)
8356
8357 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8358 {
8359 struct tg3_ethtool_stats *estats = &tp->estats;
8360 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8361 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8362
8363 if (!hw_stats)
8364 return old_estats;
8365
8366 ESTAT_ADD(rx_octets);
8367 ESTAT_ADD(rx_fragments);
8368 ESTAT_ADD(rx_ucast_packets);
8369 ESTAT_ADD(rx_mcast_packets);
8370 ESTAT_ADD(rx_bcast_packets);
8371 ESTAT_ADD(rx_fcs_errors);
8372 ESTAT_ADD(rx_align_errors);
8373 ESTAT_ADD(rx_xon_pause_rcvd);
8374 ESTAT_ADD(rx_xoff_pause_rcvd);
8375 ESTAT_ADD(rx_mac_ctrl_rcvd);
8376 ESTAT_ADD(rx_xoff_entered);
8377 ESTAT_ADD(rx_frame_too_long_errors);
8378 ESTAT_ADD(rx_jabbers);
8379 ESTAT_ADD(rx_undersize_packets);
8380 ESTAT_ADD(rx_in_length_errors);
8381 ESTAT_ADD(rx_out_length_errors);
8382 ESTAT_ADD(rx_64_or_less_octet_packets);
8383 ESTAT_ADD(rx_65_to_127_octet_packets);
8384 ESTAT_ADD(rx_128_to_255_octet_packets);
8385 ESTAT_ADD(rx_256_to_511_octet_packets);
8386 ESTAT_ADD(rx_512_to_1023_octet_packets);
8387 ESTAT_ADD(rx_1024_to_1522_octet_packets);
8388 ESTAT_ADD(rx_1523_to_2047_octet_packets);
8389 ESTAT_ADD(rx_2048_to_4095_octet_packets);
8390 ESTAT_ADD(rx_4096_to_8191_octet_packets);
8391 ESTAT_ADD(rx_8192_to_9022_octet_packets);
8392
8393 ESTAT_ADD(tx_octets);
8394 ESTAT_ADD(tx_collisions);
8395 ESTAT_ADD(tx_xon_sent);
8396 ESTAT_ADD(tx_xoff_sent);
8397 ESTAT_ADD(tx_flow_control);
8398 ESTAT_ADD(tx_mac_errors);
8399 ESTAT_ADD(tx_single_collisions);
8400 ESTAT_ADD(tx_mult_collisions);
8401 ESTAT_ADD(tx_deferred);
8402 ESTAT_ADD(tx_excessive_collisions);
8403 ESTAT_ADD(tx_late_collisions);
8404 ESTAT_ADD(tx_collide_2times);
8405 ESTAT_ADD(tx_collide_3times);
8406 ESTAT_ADD(tx_collide_4times);
8407 ESTAT_ADD(tx_collide_5times);
8408 ESTAT_ADD(tx_collide_6times);
8409 ESTAT_ADD(tx_collide_7times);
8410 ESTAT_ADD(tx_collide_8times);
8411 ESTAT_ADD(tx_collide_9times);
8412 ESTAT_ADD(tx_collide_10times);
8413 ESTAT_ADD(tx_collide_11times);
8414 ESTAT_ADD(tx_collide_12times);
8415 ESTAT_ADD(tx_collide_13times);
8416 ESTAT_ADD(tx_collide_14times);
8417 ESTAT_ADD(tx_collide_15times);
8418 ESTAT_ADD(tx_ucast_packets);
8419 ESTAT_ADD(tx_mcast_packets);
8420 ESTAT_ADD(tx_bcast_packets);
8421 ESTAT_ADD(tx_carrier_sense_errors);
8422 ESTAT_ADD(tx_discards);
8423 ESTAT_ADD(tx_errors);
8424
8425 ESTAT_ADD(dma_writeq_full);
8426 ESTAT_ADD(dma_write_prioq_full);
8427 ESTAT_ADD(rxbds_empty);
8428 ESTAT_ADD(rx_discards);
8429 ESTAT_ADD(rx_errors);
8430 ESTAT_ADD(rx_threshold_hit);
8431
8432 ESTAT_ADD(dma_readq_full);
8433 ESTAT_ADD(dma_read_prioq_full);
8434 ESTAT_ADD(tx_comp_queue_full);
8435
8436 ESTAT_ADD(ring_set_send_prod_index);
8437 ESTAT_ADD(ring_status_update);
8438 ESTAT_ADD(nic_irqs);
8439 ESTAT_ADD(nic_avoided_irqs);
8440 ESTAT_ADD(nic_tx_threshold_hit);
8441
8442 return estats;
8443 }
8444
8445 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8446 {
8447 struct tg3 *tp = netdev_priv(dev);
8448 struct net_device_stats *stats = &tp->net_stats;
8449 struct net_device_stats *old_stats = &tp->net_stats_prev;
8450 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8451
8452 if (!hw_stats)
8453 return old_stats;
8454
8455 stats->rx_packets = old_stats->rx_packets +
8456 get_stat64(&hw_stats->rx_ucast_packets) +
8457 get_stat64(&hw_stats->rx_mcast_packets) +
8458 get_stat64(&hw_stats->rx_bcast_packets);
8459
8460 stats->tx_packets = old_stats->tx_packets +
8461 get_stat64(&hw_stats->tx_ucast_packets) +
8462 get_stat64(&hw_stats->tx_mcast_packets) +
8463 get_stat64(&hw_stats->tx_bcast_packets);
8464
8465 stats->rx_bytes = old_stats->rx_bytes +
8466 get_stat64(&hw_stats->rx_octets);
8467 stats->tx_bytes = old_stats->tx_bytes +
8468 get_stat64(&hw_stats->tx_octets);
8469
8470 stats->rx_errors = old_stats->rx_errors +
8471 get_stat64(&hw_stats->rx_errors);
8472 stats->tx_errors = old_stats->tx_errors +
8473 get_stat64(&hw_stats->tx_errors) +
8474 get_stat64(&hw_stats->tx_mac_errors) +
8475 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8476 get_stat64(&hw_stats->tx_discards);
8477
8478 stats->multicast = old_stats->multicast +
8479 get_stat64(&hw_stats->rx_mcast_packets);
8480 stats->collisions = old_stats->collisions +
8481 get_stat64(&hw_stats->tx_collisions);
8482
8483 stats->rx_length_errors = old_stats->rx_length_errors +
8484 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8485 get_stat64(&hw_stats->rx_undersize_packets);
8486
8487 stats->rx_over_errors = old_stats->rx_over_errors +
8488 get_stat64(&hw_stats->rxbds_empty);
8489 stats->rx_frame_errors = old_stats->rx_frame_errors +
8490 get_stat64(&hw_stats->rx_align_errors);
8491 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8492 get_stat64(&hw_stats->tx_discards);
8493 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8494 get_stat64(&hw_stats->tx_carrier_sense_errors);
8495
8496 stats->rx_crc_errors = old_stats->rx_crc_errors +
8497 calc_crc_errors(tp);
8498
8499 stats->rx_missed_errors = old_stats->rx_missed_errors +
8500 get_stat64(&hw_stats->rx_discards);
8501
8502 return stats;
8503 }
8504
8505 static inline u32 calc_crc(unsigned char *buf, int len)
8506 {
8507 u32 reg;
8508 u32 tmp;
8509 int j, k;
8510
8511 reg = 0xffffffff;
8512
8513 for (j = 0; j < len; j++) {
8514 reg ^= buf[j];
8515
8516 for (k = 0; k < 8; k++) {
8517 tmp = reg & 0x01;
8518
8519 reg >>= 1;
8520
8521 if (tmp) {
8522 reg ^= 0xedb88320;
8523 }
8524 }
8525 }
8526
8527 return ~reg;
8528 }
8529
8530 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8531 {
8532 /* accept or reject all multicast frames */
8533 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8534 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8535 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8536 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8537 }
8538
8539 static void __tg3_set_rx_mode(struct net_device *dev)
8540 {
8541 struct tg3 *tp = netdev_priv(dev);
8542 u32 rx_mode;
8543
8544 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8545 RX_MODE_KEEP_VLAN_TAG);
8546
8547 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8548 * flag clear.
8549 */
8550 #if TG3_VLAN_TAG_USED
8551 if (!tp->vlgrp &&
8552 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8553 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8554 #else
8555 /* By definition, VLAN is disabled always in this
8556 * case.
8557 */
8558 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8559 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8560 #endif
8561
8562 if (dev->flags & IFF_PROMISC) {
8563 /* Promiscuous mode. */
8564 rx_mode |= RX_MODE_PROMISC;
8565 } else if (dev->flags & IFF_ALLMULTI) {
8566 /* Accept all multicast. */
8567 tg3_set_multi (tp, 1);
8568 } else if (dev->mc_count < 1) {
8569 /* Reject all multicast. */
8570 tg3_set_multi (tp, 0);
8571 } else {
8572 /* Accept one or more multicast(s). */
8573 struct dev_mc_list *mclist;
8574 unsigned int i;
8575 u32 mc_filter[4] = { 0, };
8576 u32 regidx;
8577 u32 bit;
8578 u32 crc;
8579
8580 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
8581 i++, mclist = mclist->next) {
8582
8583 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
8584 bit = ~crc & 0x7f;
8585 regidx = (bit & 0x60) >> 5;
8586 bit &= 0x1f;
8587 mc_filter[regidx] |= (1 << bit);
8588 }
8589
8590 tw32(MAC_HASH_REG_0, mc_filter[0]);
8591 tw32(MAC_HASH_REG_1, mc_filter[1]);
8592 tw32(MAC_HASH_REG_2, mc_filter[2]);
8593 tw32(MAC_HASH_REG_3, mc_filter[3]);
8594 }
8595
8596 if (rx_mode != tp->rx_mode) {
8597 tp->rx_mode = rx_mode;
8598 tw32_f(MAC_RX_MODE, rx_mode);
8599 udelay(10);
8600 }
8601 }
8602
8603 static void tg3_set_rx_mode(struct net_device *dev)
8604 {
8605 struct tg3 *tp = netdev_priv(dev);
8606
8607 if (!netif_running(dev))
8608 return;
8609
8610 tg3_full_lock(tp, 0);
8611 __tg3_set_rx_mode(dev);
8612 tg3_full_unlock(tp);
8613 }
8614
8615 #define TG3_REGDUMP_LEN (32 * 1024)
8616
8617 static int tg3_get_regs_len(struct net_device *dev)
8618 {
8619 return TG3_REGDUMP_LEN;
8620 }
8621
8622 static void tg3_get_regs(struct net_device *dev,
8623 struct ethtool_regs *regs, void *_p)
8624 {
8625 u32 *p = _p;
8626 struct tg3 *tp = netdev_priv(dev);
8627 u8 *orig_p = _p;
8628 int i;
8629
8630 regs->version = 0;
8631
8632 memset(p, 0, TG3_REGDUMP_LEN);
8633
8634 if (tp->link_config.phy_is_low_power)
8635 return;
8636
8637 tg3_full_lock(tp, 0);
8638
8639 #define __GET_REG32(reg) (*(p)++ = tr32(reg))
8640 #define GET_REG32_LOOP(base,len) \
8641 do { p = (u32 *)(orig_p + (base)); \
8642 for (i = 0; i < len; i += 4) \
8643 __GET_REG32((base) + i); \
8644 } while (0)
8645 #define GET_REG32_1(reg) \
8646 do { p = (u32 *)(orig_p + (reg)); \
8647 __GET_REG32((reg)); \
8648 } while (0)
8649
8650 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
8651 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
8652 GET_REG32_LOOP(MAC_MODE, 0x4f0);
8653 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
8654 GET_REG32_1(SNDDATAC_MODE);
8655 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
8656 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
8657 GET_REG32_1(SNDBDC_MODE);
8658 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
8659 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
8660 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
8661 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
8662 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
8663 GET_REG32_1(RCVDCC_MODE);
8664 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
8665 GET_REG32_LOOP(RCVCC_MODE, 0x14);
8666 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
8667 GET_REG32_1(MBFREE_MODE);
8668 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
8669 GET_REG32_LOOP(MEMARB_MODE, 0x10);
8670 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
8671 GET_REG32_LOOP(RDMAC_MODE, 0x08);
8672 GET_REG32_LOOP(WDMAC_MODE, 0x08);
8673 GET_REG32_1(RX_CPU_MODE);
8674 GET_REG32_1(RX_CPU_STATE);
8675 GET_REG32_1(RX_CPU_PGMCTR);
8676 GET_REG32_1(RX_CPU_HWBKPT);
8677 GET_REG32_1(TX_CPU_MODE);
8678 GET_REG32_1(TX_CPU_STATE);
8679 GET_REG32_1(TX_CPU_PGMCTR);
8680 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
8681 GET_REG32_LOOP(FTQ_RESET, 0x120);
8682 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
8683 GET_REG32_1(DMAC_MODE);
8684 GET_REG32_LOOP(GRC_MODE, 0x4c);
8685 if (tp->tg3_flags & TG3_FLAG_NVRAM)
8686 GET_REG32_LOOP(NVRAM_CMD, 0x24);
8687
8688 #undef __GET_REG32
8689 #undef GET_REG32_LOOP
8690 #undef GET_REG32_1
8691
8692 tg3_full_unlock(tp);
8693 }
8694
8695 static int tg3_get_eeprom_len(struct net_device *dev)
8696 {
8697 struct tg3 *tp = netdev_priv(dev);
8698
8699 return tp->nvram_size;
8700 }
8701
8702 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8703 {
8704 struct tg3 *tp = netdev_priv(dev);
8705 int ret;
8706 u8 *pd;
8707 u32 i, offset, len, b_offset, b_count;
8708 __be32 val;
8709
8710 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
8711 return -EINVAL;
8712
8713 if (tp->link_config.phy_is_low_power)
8714 return -EAGAIN;
8715
8716 offset = eeprom->offset;
8717 len = eeprom->len;
8718 eeprom->len = 0;
8719
8720 eeprom->magic = TG3_EEPROM_MAGIC;
8721
8722 if (offset & 3) {
8723 /* adjustments to start on required 4 byte boundary */
8724 b_offset = offset & 3;
8725 b_count = 4 - b_offset;
8726 if (b_count > len) {
8727 /* i.e. offset=1 len=2 */
8728 b_count = len;
8729 }
8730 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
8731 if (ret)
8732 return ret;
8733 memcpy(data, ((char*)&val) + b_offset, b_count);
8734 len -= b_count;
8735 offset += b_count;
8736 eeprom->len += b_count;
8737 }
8738
8739 /* read bytes upto the last 4 byte boundary */
8740 pd = &data[eeprom->len];
8741 for (i = 0; i < (len - (len & 3)); i += 4) {
8742 ret = tg3_nvram_read_be32(tp, offset + i, &val);
8743 if (ret) {
8744 eeprom->len += i;
8745 return ret;
8746 }
8747 memcpy(pd + i, &val, 4);
8748 }
8749 eeprom->len += i;
8750
8751 if (len & 3) {
8752 /* read last bytes not ending on 4 byte boundary */
8753 pd = &data[eeprom->len];
8754 b_count = len & 3;
8755 b_offset = offset + len - b_count;
8756 ret = tg3_nvram_read_be32(tp, b_offset, &val);
8757 if (ret)
8758 return ret;
8759 memcpy(pd, &val, b_count);
8760 eeprom->len += b_count;
8761 }
8762 return 0;
8763 }
8764
8765 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
8766
8767 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8768 {
8769 struct tg3 *tp = netdev_priv(dev);
8770 int ret;
8771 u32 offset, len, b_offset, odd_len;
8772 u8 *buf;
8773 __be32 start, end;
8774
8775 if (tp->link_config.phy_is_low_power)
8776 return -EAGAIN;
8777
8778 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
8779 eeprom->magic != TG3_EEPROM_MAGIC)
8780 return -EINVAL;
8781
8782 offset = eeprom->offset;
8783 len = eeprom->len;
8784
8785 if ((b_offset = (offset & 3))) {
8786 /* adjustments to start on required 4 byte boundary */
8787 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
8788 if (ret)
8789 return ret;
8790 len += b_offset;
8791 offset &= ~3;
8792 if (len < 4)
8793 len = 4;
8794 }
8795
8796 odd_len = 0;
8797 if (len & 3) {
8798 /* adjustments to end on required 4 byte boundary */
8799 odd_len = 1;
8800 len = (len + 3) & ~3;
8801 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
8802 if (ret)
8803 return ret;
8804 }
8805
8806 buf = data;
8807 if (b_offset || odd_len) {
8808 buf = kmalloc(len, GFP_KERNEL);
8809 if (!buf)
8810 return -ENOMEM;
8811 if (b_offset)
8812 memcpy(buf, &start, 4);
8813 if (odd_len)
8814 memcpy(buf+len-4, &end, 4);
8815 memcpy(buf + b_offset, data, eeprom->len);
8816 }
8817
8818 ret = tg3_nvram_write_block(tp, offset, len, buf);
8819
8820 if (buf != data)
8821 kfree(buf);
8822
8823 return ret;
8824 }
8825
8826 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8827 {
8828 struct tg3 *tp = netdev_priv(dev);
8829
8830 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8831 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8832 return -EAGAIN;
8833 return phy_ethtool_gset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
8834 }
8835
8836 cmd->supported = (SUPPORTED_Autoneg);
8837
8838 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8839 cmd->supported |= (SUPPORTED_1000baseT_Half |
8840 SUPPORTED_1000baseT_Full);
8841
8842 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
8843 cmd->supported |= (SUPPORTED_100baseT_Half |
8844 SUPPORTED_100baseT_Full |
8845 SUPPORTED_10baseT_Half |
8846 SUPPORTED_10baseT_Full |
8847 SUPPORTED_TP);
8848 cmd->port = PORT_TP;
8849 } else {
8850 cmd->supported |= SUPPORTED_FIBRE;
8851 cmd->port = PORT_FIBRE;
8852 }
8853
8854 cmd->advertising = tp->link_config.advertising;
8855 if (netif_running(dev)) {
8856 cmd->speed = tp->link_config.active_speed;
8857 cmd->duplex = tp->link_config.active_duplex;
8858 }
8859 cmd->phy_address = PHY_ADDR;
8860 cmd->transceiver = XCVR_INTERNAL;
8861 cmd->autoneg = tp->link_config.autoneg;
8862 cmd->maxtxpkt = 0;
8863 cmd->maxrxpkt = 0;
8864 return 0;
8865 }
8866
8867 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8868 {
8869 struct tg3 *tp = netdev_priv(dev);
8870
8871 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8872 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8873 return -EAGAIN;
8874 return phy_ethtool_sset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
8875 }
8876
8877 if (cmd->autoneg != AUTONEG_ENABLE &&
8878 cmd->autoneg != AUTONEG_DISABLE)
8879 return -EINVAL;
8880
8881 if (cmd->autoneg == AUTONEG_DISABLE &&
8882 cmd->duplex != DUPLEX_FULL &&
8883 cmd->duplex != DUPLEX_HALF)
8884 return -EINVAL;
8885
8886 if (cmd->autoneg == AUTONEG_ENABLE) {
8887 u32 mask = ADVERTISED_Autoneg |
8888 ADVERTISED_Pause |
8889 ADVERTISED_Asym_Pause;
8890
8891 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
8892 mask |= ADVERTISED_1000baseT_Half |
8893 ADVERTISED_1000baseT_Full;
8894
8895 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
8896 mask |= ADVERTISED_100baseT_Half |
8897 ADVERTISED_100baseT_Full |
8898 ADVERTISED_10baseT_Half |
8899 ADVERTISED_10baseT_Full |
8900 ADVERTISED_TP;
8901 else
8902 mask |= ADVERTISED_FIBRE;
8903
8904 if (cmd->advertising & ~mask)
8905 return -EINVAL;
8906
8907 mask &= (ADVERTISED_1000baseT_Half |
8908 ADVERTISED_1000baseT_Full |
8909 ADVERTISED_100baseT_Half |
8910 ADVERTISED_100baseT_Full |
8911 ADVERTISED_10baseT_Half |
8912 ADVERTISED_10baseT_Full);
8913
8914 cmd->advertising &= mask;
8915 } else {
8916 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
8917 if (cmd->speed != SPEED_1000)
8918 return -EINVAL;
8919
8920 if (cmd->duplex != DUPLEX_FULL)
8921 return -EINVAL;
8922 } else {
8923 if (cmd->speed != SPEED_100 &&
8924 cmd->speed != SPEED_10)
8925 return -EINVAL;
8926 }
8927 }
8928
8929 tg3_full_lock(tp, 0);
8930
8931 tp->link_config.autoneg = cmd->autoneg;
8932 if (cmd->autoneg == AUTONEG_ENABLE) {
8933 tp->link_config.advertising = (cmd->advertising |
8934 ADVERTISED_Autoneg);
8935 tp->link_config.speed = SPEED_INVALID;
8936 tp->link_config.duplex = DUPLEX_INVALID;
8937 } else {
8938 tp->link_config.advertising = 0;
8939 tp->link_config.speed = cmd->speed;
8940 tp->link_config.duplex = cmd->duplex;
8941 }
8942
8943 tp->link_config.orig_speed = tp->link_config.speed;
8944 tp->link_config.orig_duplex = tp->link_config.duplex;
8945 tp->link_config.orig_autoneg = tp->link_config.autoneg;
8946
8947 if (netif_running(dev))
8948 tg3_setup_phy(tp, 1);
8949
8950 tg3_full_unlock(tp);
8951
8952 return 0;
8953 }
8954
8955 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
8956 {
8957 struct tg3 *tp = netdev_priv(dev);
8958
8959 strcpy(info->driver, DRV_MODULE_NAME);
8960 strcpy(info->version, DRV_MODULE_VERSION);
8961 strcpy(info->fw_version, tp->fw_ver);
8962 strcpy(info->bus_info, pci_name(tp->pdev));
8963 }
8964
8965 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8966 {
8967 struct tg3 *tp = netdev_priv(dev);
8968
8969 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
8970 device_can_wakeup(&tp->pdev->dev))
8971 wol->supported = WAKE_MAGIC;
8972 else
8973 wol->supported = 0;
8974 wol->wolopts = 0;
8975 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
8976 device_can_wakeup(&tp->pdev->dev))
8977 wol->wolopts = WAKE_MAGIC;
8978 memset(&wol->sopass, 0, sizeof(wol->sopass));
8979 }
8980
8981 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8982 {
8983 struct tg3 *tp = netdev_priv(dev);
8984 struct device *dp = &tp->pdev->dev;
8985
8986 if (wol->wolopts & ~WAKE_MAGIC)
8987 return -EINVAL;
8988 if ((wol->wolopts & WAKE_MAGIC) &&
8989 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
8990 return -EINVAL;
8991
8992 spin_lock_bh(&tp->lock);
8993 if (wol->wolopts & WAKE_MAGIC) {
8994 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
8995 device_set_wakeup_enable(dp, true);
8996 } else {
8997 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
8998 device_set_wakeup_enable(dp, false);
8999 }
9000 spin_unlock_bh(&tp->lock);
9001
9002 return 0;
9003 }
9004
9005 static u32 tg3_get_msglevel(struct net_device *dev)
9006 {
9007 struct tg3 *tp = netdev_priv(dev);
9008 return tp->msg_enable;
9009 }
9010
9011 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9012 {
9013 struct tg3 *tp = netdev_priv(dev);
9014 tp->msg_enable = value;
9015 }
9016
9017 static int tg3_set_tso(struct net_device *dev, u32 value)
9018 {
9019 struct tg3 *tp = netdev_priv(dev);
9020
9021 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9022 if (value)
9023 return -EINVAL;
9024 return 0;
9025 }
9026 if ((dev->features & NETIF_F_IPV6_CSUM) &&
9027 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)) {
9028 if (value) {
9029 dev->features |= NETIF_F_TSO6;
9030 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9031 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9032 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9033 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9034 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9035 dev->features |= NETIF_F_TSO_ECN;
9036 } else
9037 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9038 }
9039 return ethtool_op_set_tso(dev, value);
9040 }
9041
9042 static int tg3_nway_reset(struct net_device *dev)
9043 {
9044 struct tg3 *tp = netdev_priv(dev);
9045 int r;
9046
9047 if (!netif_running(dev))
9048 return -EAGAIN;
9049
9050 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9051 return -EINVAL;
9052
9053 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9054 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9055 return -EAGAIN;
9056 r = phy_start_aneg(tp->mdio_bus->phy_map[PHY_ADDR]);
9057 } else {
9058 u32 bmcr;
9059
9060 spin_lock_bh(&tp->lock);
9061 r = -EINVAL;
9062 tg3_readphy(tp, MII_BMCR, &bmcr);
9063 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9064 ((bmcr & BMCR_ANENABLE) ||
9065 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9066 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9067 BMCR_ANENABLE);
9068 r = 0;
9069 }
9070 spin_unlock_bh(&tp->lock);
9071 }
9072
9073 return r;
9074 }
9075
9076 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9077 {
9078 struct tg3 *tp = netdev_priv(dev);
9079
9080 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9081 ering->rx_mini_max_pending = 0;
9082 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9083 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9084 else
9085 ering->rx_jumbo_max_pending = 0;
9086
9087 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9088
9089 ering->rx_pending = tp->rx_pending;
9090 ering->rx_mini_pending = 0;
9091 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9092 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9093 else
9094 ering->rx_jumbo_pending = 0;
9095
9096 ering->tx_pending = tp->tx_pending;
9097 }
9098
9099 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9100 {
9101 struct tg3 *tp = netdev_priv(dev);
9102 int irq_sync = 0, err = 0;
9103
9104 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9105 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9106 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9107 (ering->tx_pending <= MAX_SKB_FRAGS) ||
9108 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9109 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9110 return -EINVAL;
9111
9112 if (netif_running(dev)) {
9113 tg3_phy_stop(tp);
9114 tg3_netif_stop(tp);
9115 irq_sync = 1;
9116 }
9117
9118 tg3_full_lock(tp, irq_sync);
9119
9120 tp->rx_pending = ering->rx_pending;
9121
9122 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9123 tp->rx_pending > 63)
9124 tp->rx_pending = 63;
9125 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9126 tp->tx_pending = ering->tx_pending;
9127
9128 if (netif_running(dev)) {
9129 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9130 err = tg3_restart_hw(tp, 1);
9131 if (!err)
9132 tg3_netif_start(tp);
9133 }
9134
9135 tg3_full_unlock(tp);
9136
9137 if (irq_sync && !err)
9138 tg3_phy_start(tp);
9139
9140 return err;
9141 }
9142
9143 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9144 {
9145 struct tg3 *tp = netdev_priv(dev);
9146
9147 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9148
9149 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
9150 epause->rx_pause = 1;
9151 else
9152 epause->rx_pause = 0;
9153
9154 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
9155 epause->tx_pause = 1;
9156 else
9157 epause->tx_pause = 0;
9158 }
9159
9160 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9161 {
9162 struct tg3 *tp = netdev_priv(dev);
9163 int err = 0;
9164
9165 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9166 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9167 return -EAGAIN;
9168
9169 if (epause->autoneg) {
9170 u32 newadv;
9171 struct phy_device *phydev;
9172
9173 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
9174
9175 if (epause->rx_pause) {
9176 if (epause->tx_pause)
9177 newadv = ADVERTISED_Pause;
9178 else
9179 newadv = ADVERTISED_Pause |
9180 ADVERTISED_Asym_Pause;
9181 } else if (epause->tx_pause) {
9182 newadv = ADVERTISED_Asym_Pause;
9183 } else
9184 newadv = 0;
9185
9186 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9187 u32 oldadv = phydev->advertising &
9188 (ADVERTISED_Pause |
9189 ADVERTISED_Asym_Pause);
9190 if (oldadv != newadv) {
9191 phydev->advertising &=
9192 ~(ADVERTISED_Pause |
9193 ADVERTISED_Asym_Pause);
9194 phydev->advertising |= newadv;
9195 err = phy_start_aneg(phydev);
9196 }
9197 } else {
9198 tp->link_config.advertising &=
9199 ~(ADVERTISED_Pause |
9200 ADVERTISED_Asym_Pause);
9201 tp->link_config.advertising |= newadv;
9202 }
9203 } else {
9204 if (epause->rx_pause)
9205 tp->link_config.flowctrl |= FLOW_CTRL_RX;
9206 else
9207 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9208
9209 if (epause->tx_pause)
9210 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9211 else
9212 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9213
9214 if (netif_running(dev))
9215 tg3_setup_flow_control(tp, 0, 0);
9216 }
9217 } else {
9218 int irq_sync = 0;
9219
9220 if (netif_running(dev)) {
9221 tg3_netif_stop(tp);
9222 irq_sync = 1;
9223 }
9224
9225 tg3_full_lock(tp, irq_sync);
9226
9227 if (epause->autoneg)
9228 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9229 else
9230 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9231 if (epause->rx_pause)
9232 tp->link_config.flowctrl |= FLOW_CTRL_RX;
9233 else
9234 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9235 if (epause->tx_pause)
9236 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9237 else
9238 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9239
9240 if (netif_running(dev)) {
9241 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9242 err = tg3_restart_hw(tp, 1);
9243 if (!err)
9244 tg3_netif_start(tp);
9245 }
9246
9247 tg3_full_unlock(tp);
9248 }
9249
9250 return err;
9251 }
9252
9253 static u32 tg3_get_rx_csum(struct net_device *dev)
9254 {
9255 struct tg3 *tp = netdev_priv(dev);
9256 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9257 }
9258
9259 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9260 {
9261 struct tg3 *tp = netdev_priv(dev);
9262
9263 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9264 if (data != 0)
9265 return -EINVAL;
9266 return 0;
9267 }
9268
9269 spin_lock_bh(&tp->lock);
9270 if (data)
9271 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9272 else
9273 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
9274 spin_unlock_bh(&tp->lock);
9275
9276 return 0;
9277 }
9278
9279 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9280 {
9281 struct tg3 *tp = netdev_priv(dev);
9282
9283 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9284 if (data != 0)
9285 return -EINVAL;
9286 return 0;
9287 }
9288
9289 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9290 ethtool_op_set_tx_ipv6_csum(dev, data);
9291 else
9292 ethtool_op_set_tx_csum(dev, data);
9293
9294 return 0;
9295 }
9296
9297 static int tg3_get_sset_count (struct net_device *dev, int sset)
9298 {
9299 switch (sset) {
9300 case ETH_SS_TEST:
9301 return TG3_NUM_TEST;
9302 case ETH_SS_STATS:
9303 return TG3_NUM_STATS;
9304 default:
9305 return -EOPNOTSUPP;
9306 }
9307 }
9308
9309 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9310 {
9311 switch (stringset) {
9312 case ETH_SS_STATS:
9313 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9314 break;
9315 case ETH_SS_TEST:
9316 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9317 break;
9318 default:
9319 WARN_ON(1); /* we need a WARN() */
9320 break;
9321 }
9322 }
9323
9324 static int tg3_phys_id(struct net_device *dev, u32 data)
9325 {
9326 struct tg3 *tp = netdev_priv(dev);
9327 int i;
9328
9329 if (!netif_running(tp->dev))
9330 return -EAGAIN;
9331
9332 if (data == 0)
9333 data = UINT_MAX / 2;
9334
9335 for (i = 0; i < (data * 2); i++) {
9336 if ((i % 2) == 0)
9337 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9338 LED_CTRL_1000MBPS_ON |
9339 LED_CTRL_100MBPS_ON |
9340 LED_CTRL_10MBPS_ON |
9341 LED_CTRL_TRAFFIC_OVERRIDE |
9342 LED_CTRL_TRAFFIC_BLINK |
9343 LED_CTRL_TRAFFIC_LED);
9344
9345 else
9346 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9347 LED_CTRL_TRAFFIC_OVERRIDE);
9348
9349 if (msleep_interruptible(500))
9350 break;
9351 }
9352 tw32(MAC_LED_CTRL, tp->led_ctrl);
9353 return 0;
9354 }
9355
9356 static void tg3_get_ethtool_stats (struct net_device *dev,
9357 struct ethtool_stats *estats, u64 *tmp_stats)
9358 {
9359 struct tg3 *tp = netdev_priv(dev);
9360 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9361 }
9362
9363 #define NVRAM_TEST_SIZE 0x100
9364 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
9365 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
9366 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
9367 #define NVRAM_SELFBOOT_HW_SIZE 0x20
9368 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
9369
9370 static int tg3_test_nvram(struct tg3 *tp)
9371 {
9372 u32 csum, magic;
9373 __be32 *buf;
9374 int i, j, k, err = 0, size;
9375
9376 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9377 return 0;
9378
9379 if (tg3_nvram_read(tp, 0, &magic) != 0)
9380 return -EIO;
9381
9382 if (magic == TG3_EEPROM_MAGIC)
9383 size = NVRAM_TEST_SIZE;
9384 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
9385 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9386 TG3_EEPROM_SB_FORMAT_1) {
9387 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9388 case TG3_EEPROM_SB_REVISION_0:
9389 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9390 break;
9391 case TG3_EEPROM_SB_REVISION_2:
9392 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9393 break;
9394 case TG3_EEPROM_SB_REVISION_3:
9395 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9396 break;
9397 default:
9398 return 0;
9399 }
9400 } else
9401 return 0;
9402 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9403 size = NVRAM_SELFBOOT_HW_SIZE;
9404 else
9405 return -EIO;
9406
9407 buf = kmalloc(size, GFP_KERNEL);
9408 if (buf == NULL)
9409 return -ENOMEM;
9410
9411 err = -EIO;
9412 for (i = 0, j = 0; i < size; i += 4, j++) {
9413 err = tg3_nvram_read_be32(tp, i, &buf[j]);
9414 if (err)
9415 break;
9416 }
9417 if (i < size)
9418 goto out;
9419
9420 /* Selfboot format */
9421 magic = be32_to_cpu(buf[0]);
9422 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
9423 TG3_EEPROM_MAGIC_FW) {
9424 u8 *buf8 = (u8 *) buf, csum8 = 0;
9425
9426 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
9427 TG3_EEPROM_SB_REVISION_2) {
9428 /* For rev 2, the csum doesn't include the MBA. */
9429 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9430 csum8 += buf8[i];
9431 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9432 csum8 += buf8[i];
9433 } else {
9434 for (i = 0; i < size; i++)
9435 csum8 += buf8[i];
9436 }
9437
9438 if (csum8 == 0) {
9439 err = 0;
9440 goto out;
9441 }
9442
9443 err = -EIO;
9444 goto out;
9445 }
9446
9447 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
9448 TG3_EEPROM_MAGIC_HW) {
9449 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
9450 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
9451 u8 *buf8 = (u8 *) buf;
9452
9453 /* Separate the parity bits and the data bytes. */
9454 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9455 if ((i == 0) || (i == 8)) {
9456 int l;
9457 u8 msk;
9458
9459 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9460 parity[k++] = buf8[i] & msk;
9461 i++;
9462 }
9463 else if (i == 16) {
9464 int l;
9465 u8 msk;
9466
9467 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9468 parity[k++] = buf8[i] & msk;
9469 i++;
9470
9471 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9472 parity[k++] = buf8[i] & msk;
9473 i++;
9474 }
9475 data[j++] = buf8[i];
9476 }
9477
9478 err = -EIO;
9479 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9480 u8 hw8 = hweight8(data[i]);
9481
9482 if ((hw8 & 0x1) && parity[i])
9483 goto out;
9484 else if (!(hw8 & 0x1) && !parity[i])
9485 goto out;
9486 }
9487 err = 0;
9488 goto out;
9489 }
9490
9491 /* Bootstrap checksum at offset 0x10 */
9492 csum = calc_crc((unsigned char *) buf, 0x10);
9493 if (csum != be32_to_cpu(buf[0x10/4]))
9494 goto out;
9495
9496 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9497 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
9498 if (csum != be32_to_cpu(buf[0xfc/4]))
9499 goto out;
9500
9501 err = 0;
9502
9503 out:
9504 kfree(buf);
9505 return err;
9506 }
9507
9508 #define TG3_SERDES_TIMEOUT_SEC 2
9509 #define TG3_COPPER_TIMEOUT_SEC 6
9510
9511 static int tg3_test_link(struct tg3 *tp)
9512 {
9513 int i, max;
9514
9515 if (!netif_running(tp->dev))
9516 return -ENODEV;
9517
9518 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
9519 max = TG3_SERDES_TIMEOUT_SEC;
9520 else
9521 max = TG3_COPPER_TIMEOUT_SEC;
9522
9523 for (i = 0; i < max; i++) {
9524 if (netif_carrier_ok(tp->dev))
9525 return 0;
9526
9527 if (msleep_interruptible(1000))
9528 break;
9529 }
9530
9531 return -EIO;
9532 }
9533
9534 /* Only test the commonly used registers */
9535 static int tg3_test_registers(struct tg3 *tp)
9536 {
9537 int i, is_5705, is_5750;
9538 u32 offset, read_mask, write_mask, val, save_val, read_val;
9539 static struct {
9540 u16 offset;
9541 u16 flags;
9542 #define TG3_FL_5705 0x1
9543 #define TG3_FL_NOT_5705 0x2
9544 #define TG3_FL_NOT_5788 0x4
9545 #define TG3_FL_NOT_5750 0x8
9546 u32 read_mask;
9547 u32 write_mask;
9548 } reg_tbl[] = {
9549 /* MAC Control Registers */
9550 { MAC_MODE, TG3_FL_NOT_5705,
9551 0x00000000, 0x00ef6f8c },
9552 { MAC_MODE, TG3_FL_5705,
9553 0x00000000, 0x01ef6b8c },
9554 { MAC_STATUS, TG3_FL_NOT_5705,
9555 0x03800107, 0x00000000 },
9556 { MAC_STATUS, TG3_FL_5705,
9557 0x03800100, 0x00000000 },
9558 { MAC_ADDR_0_HIGH, 0x0000,
9559 0x00000000, 0x0000ffff },
9560 { MAC_ADDR_0_LOW, 0x0000,
9561 0x00000000, 0xffffffff },
9562 { MAC_RX_MTU_SIZE, 0x0000,
9563 0x00000000, 0x0000ffff },
9564 { MAC_TX_MODE, 0x0000,
9565 0x00000000, 0x00000070 },
9566 { MAC_TX_LENGTHS, 0x0000,
9567 0x00000000, 0x00003fff },
9568 { MAC_RX_MODE, TG3_FL_NOT_5705,
9569 0x00000000, 0x000007fc },
9570 { MAC_RX_MODE, TG3_FL_5705,
9571 0x00000000, 0x000007dc },
9572 { MAC_HASH_REG_0, 0x0000,
9573 0x00000000, 0xffffffff },
9574 { MAC_HASH_REG_1, 0x0000,
9575 0x00000000, 0xffffffff },
9576 { MAC_HASH_REG_2, 0x0000,
9577 0x00000000, 0xffffffff },
9578 { MAC_HASH_REG_3, 0x0000,
9579 0x00000000, 0xffffffff },
9580
9581 /* Receive Data and Receive BD Initiator Control Registers. */
9582 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
9583 0x00000000, 0xffffffff },
9584 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
9585 0x00000000, 0xffffffff },
9586 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
9587 0x00000000, 0x00000003 },
9588 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
9589 0x00000000, 0xffffffff },
9590 { RCVDBDI_STD_BD+0, 0x0000,
9591 0x00000000, 0xffffffff },
9592 { RCVDBDI_STD_BD+4, 0x0000,
9593 0x00000000, 0xffffffff },
9594 { RCVDBDI_STD_BD+8, 0x0000,
9595 0x00000000, 0xffff0002 },
9596 { RCVDBDI_STD_BD+0xc, 0x0000,
9597 0x00000000, 0xffffffff },
9598
9599 /* Receive BD Initiator Control Registers. */
9600 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
9601 0x00000000, 0xffffffff },
9602 { RCVBDI_STD_THRESH, TG3_FL_5705,
9603 0x00000000, 0x000003ff },
9604 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
9605 0x00000000, 0xffffffff },
9606
9607 /* Host Coalescing Control Registers. */
9608 { HOSTCC_MODE, TG3_FL_NOT_5705,
9609 0x00000000, 0x00000004 },
9610 { HOSTCC_MODE, TG3_FL_5705,
9611 0x00000000, 0x000000f6 },
9612 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
9613 0x00000000, 0xffffffff },
9614 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
9615 0x00000000, 0x000003ff },
9616 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
9617 0x00000000, 0xffffffff },
9618 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
9619 0x00000000, 0x000003ff },
9620 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
9621 0x00000000, 0xffffffff },
9622 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9623 0x00000000, 0x000000ff },
9624 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
9625 0x00000000, 0xffffffff },
9626 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9627 0x00000000, 0x000000ff },
9628 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
9629 0x00000000, 0xffffffff },
9630 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
9631 0x00000000, 0xffffffff },
9632 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9633 0x00000000, 0xffffffff },
9634 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9635 0x00000000, 0x000000ff },
9636 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9637 0x00000000, 0xffffffff },
9638 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9639 0x00000000, 0x000000ff },
9640 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
9641 0x00000000, 0xffffffff },
9642 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
9643 0x00000000, 0xffffffff },
9644 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
9645 0x00000000, 0xffffffff },
9646 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
9647 0x00000000, 0xffffffff },
9648 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
9649 0x00000000, 0xffffffff },
9650 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
9651 0xffffffff, 0x00000000 },
9652 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
9653 0xffffffff, 0x00000000 },
9654
9655 /* Buffer Manager Control Registers. */
9656 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
9657 0x00000000, 0x007fff80 },
9658 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
9659 0x00000000, 0x007fffff },
9660 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
9661 0x00000000, 0x0000003f },
9662 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
9663 0x00000000, 0x000001ff },
9664 { BUFMGR_MB_HIGH_WATER, 0x0000,
9665 0x00000000, 0x000001ff },
9666 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
9667 0xffffffff, 0x00000000 },
9668 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
9669 0xffffffff, 0x00000000 },
9670
9671 /* Mailbox Registers */
9672 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
9673 0x00000000, 0x000001ff },
9674 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
9675 0x00000000, 0x000001ff },
9676 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
9677 0x00000000, 0x000007ff },
9678 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
9679 0x00000000, 0x000001ff },
9680
9681 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
9682 };
9683
9684 is_5705 = is_5750 = 0;
9685 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
9686 is_5705 = 1;
9687 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9688 is_5750 = 1;
9689 }
9690
9691 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
9692 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
9693 continue;
9694
9695 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
9696 continue;
9697
9698 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9699 (reg_tbl[i].flags & TG3_FL_NOT_5788))
9700 continue;
9701
9702 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
9703 continue;
9704
9705 offset = (u32) reg_tbl[i].offset;
9706 read_mask = reg_tbl[i].read_mask;
9707 write_mask = reg_tbl[i].write_mask;
9708
9709 /* Save the original register content */
9710 save_val = tr32(offset);
9711
9712 /* Determine the read-only value. */
9713 read_val = save_val & read_mask;
9714
9715 /* Write zero to the register, then make sure the read-only bits
9716 * are not changed and the read/write bits are all zeros.
9717 */
9718 tw32(offset, 0);
9719
9720 val = tr32(offset);
9721
9722 /* Test the read-only and read/write bits. */
9723 if (((val & read_mask) != read_val) || (val & write_mask))
9724 goto out;
9725
9726 /* Write ones to all the bits defined by RdMask and WrMask, then
9727 * make sure the read-only bits are not changed and the
9728 * read/write bits are all ones.
9729 */
9730 tw32(offset, read_mask | write_mask);
9731
9732 val = tr32(offset);
9733
9734 /* Test the read-only bits. */
9735 if ((val & read_mask) != read_val)
9736 goto out;
9737
9738 /* Test the read/write bits. */
9739 if ((val & write_mask) != write_mask)
9740 goto out;
9741
9742 tw32(offset, save_val);
9743 }
9744
9745 return 0;
9746
9747 out:
9748 if (netif_msg_hw(tp))
9749 printk(KERN_ERR PFX "Register test failed at offset %x\n",
9750 offset);
9751 tw32(offset, save_val);
9752 return -EIO;
9753 }
9754
9755 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
9756 {
9757 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
9758 int i;
9759 u32 j;
9760
9761 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
9762 for (j = 0; j < len; j += 4) {
9763 u32 val;
9764
9765 tg3_write_mem(tp, offset + j, test_pattern[i]);
9766 tg3_read_mem(tp, offset + j, &val);
9767 if (val != test_pattern[i])
9768 return -EIO;
9769 }
9770 }
9771 return 0;
9772 }
9773
9774 static int tg3_test_memory(struct tg3 *tp)
9775 {
9776 static struct mem_entry {
9777 u32 offset;
9778 u32 len;
9779 } mem_tbl_570x[] = {
9780 { 0x00000000, 0x00b50},
9781 { 0x00002000, 0x1c000},
9782 { 0xffffffff, 0x00000}
9783 }, mem_tbl_5705[] = {
9784 { 0x00000100, 0x0000c},
9785 { 0x00000200, 0x00008},
9786 { 0x00004000, 0x00800},
9787 { 0x00006000, 0x01000},
9788 { 0x00008000, 0x02000},
9789 { 0x00010000, 0x0e000},
9790 { 0xffffffff, 0x00000}
9791 }, mem_tbl_5755[] = {
9792 { 0x00000200, 0x00008},
9793 { 0x00004000, 0x00800},
9794 { 0x00006000, 0x00800},
9795 { 0x00008000, 0x02000},
9796 { 0x00010000, 0x0c000},
9797 { 0xffffffff, 0x00000}
9798 }, mem_tbl_5906[] = {
9799 { 0x00000200, 0x00008},
9800 { 0x00004000, 0x00400},
9801 { 0x00006000, 0x00400},
9802 { 0x00008000, 0x01000},
9803 { 0x00010000, 0x01000},
9804 { 0xffffffff, 0x00000}
9805 };
9806 struct mem_entry *mem_tbl;
9807 int err = 0;
9808 int i;
9809
9810 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9811 mem_tbl = mem_tbl_5755;
9812 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9813 mem_tbl = mem_tbl_5906;
9814 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
9815 mem_tbl = mem_tbl_5705;
9816 else
9817 mem_tbl = mem_tbl_570x;
9818
9819 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
9820 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
9821 mem_tbl[i].len)) != 0)
9822 break;
9823 }
9824
9825 return err;
9826 }
9827
9828 #define TG3_MAC_LOOPBACK 0
9829 #define TG3_PHY_LOOPBACK 1
9830
9831 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
9832 {
9833 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
9834 u32 desc_idx;
9835 struct sk_buff *skb, *rx_skb;
9836 u8 *tx_data;
9837 dma_addr_t map;
9838 int num_pkts, tx_len, rx_len, i, err;
9839 struct tg3_rx_buffer_desc *desc;
9840 struct tg3_napi *tnapi, *rnapi;
9841 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
9842
9843 tnapi = &tp->napi[0];
9844 rnapi = &tp->napi[0];
9845
9846 if (loopback_mode == TG3_MAC_LOOPBACK) {
9847 /* HW errata - mac loopback fails in some cases on 5780.
9848 * Normal traffic and PHY loopback are not affected by
9849 * errata.
9850 */
9851 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
9852 return 0;
9853
9854 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
9855 MAC_MODE_PORT_INT_LPBACK;
9856 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9857 mac_mode |= MAC_MODE_LINK_POLARITY;
9858 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
9859 mac_mode |= MAC_MODE_PORT_MODE_MII;
9860 else
9861 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9862 tw32(MAC_MODE, mac_mode);
9863 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
9864 u32 val;
9865
9866 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
9867 tg3_phy_fet_toggle_apd(tp, false);
9868 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
9869 } else
9870 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
9871
9872 tg3_phy_toggle_automdix(tp, 0);
9873
9874 tg3_writephy(tp, MII_BMCR, val);
9875 udelay(40);
9876
9877 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
9878 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
9879 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9880 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
9881 mac_mode |= MAC_MODE_PORT_MODE_MII;
9882 } else
9883 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9884
9885 /* reset to prevent losing 1st rx packet intermittently */
9886 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
9887 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
9888 udelay(10);
9889 tw32_f(MAC_RX_MODE, tp->rx_mode);
9890 }
9891 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
9892 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
9893 mac_mode &= ~MAC_MODE_LINK_POLARITY;
9894 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
9895 mac_mode |= MAC_MODE_LINK_POLARITY;
9896 tg3_writephy(tp, MII_TG3_EXT_CTRL,
9897 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
9898 }
9899 tw32(MAC_MODE, mac_mode);
9900 }
9901 else
9902 return -EINVAL;
9903
9904 err = -EIO;
9905
9906 tx_len = 1514;
9907 skb = netdev_alloc_skb(tp->dev, tx_len);
9908 if (!skb)
9909 return -ENOMEM;
9910
9911 tx_data = skb_put(skb, tx_len);
9912 memcpy(tx_data, tp->dev->dev_addr, 6);
9913 memset(tx_data + 6, 0x0, 8);
9914
9915 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
9916
9917 for (i = 14; i < tx_len; i++)
9918 tx_data[i] = (u8) (i & 0xff);
9919
9920 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
9921
9922 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9923 HOSTCC_MODE_NOW);
9924
9925 udelay(10);
9926
9927 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
9928
9929 num_pkts = 0;
9930
9931 tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
9932
9933 tp->tx_prod++;
9934 num_pkts++;
9935
9936 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
9937 tp->tx_prod);
9938 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
9939
9940 udelay(10);
9941
9942 /* 250 usec to allow enough time on some 10/100 Mbps devices. */
9943 for (i = 0; i < 25; i++) {
9944 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9945 HOSTCC_MODE_NOW);
9946
9947 udelay(10);
9948
9949 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
9950 rx_idx = rnapi->hw_status->idx[0].rx_producer;
9951 if ((tx_idx == tp->tx_prod) &&
9952 (rx_idx == (rx_start_idx + num_pkts)))
9953 break;
9954 }
9955
9956 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
9957 dev_kfree_skb(skb);
9958
9959 if (tx_idx != tp->tx_prod)
9960 goto out;
9961
9962 if (rx_idx != rx_start_idx + num_pkts)
9963 goto out;
9964
9965 desc = &rnapi->rx_rcb[rx_start_idx];
9966 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
9967 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
9968 if (opaque_key != RXD_OPAQUE_RING_STD)
9969 goto out;
9970
9971 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
9972 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
9973 goto out;
9974
9975 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
9976 if (rx_len != tx_len)
9977 goto out;
9978
9979 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
9980
9981 map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
9982 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
9983
9984 for (i = 14; i < tx_len; i++) {
9985 if (*(rx_skb->data + i) != (u8) (i & 0xff))
9986 goto out;
9987 }
9988 err = 0;
9989
9990 /* tg3_free_rings will unmap and free the rx_skb */
9991 out:
9992 return err;
9993 }
9994
9995 #define TG3_MAC_LOOPBACK_FAILED 1
9996 #define TG3_PHY_LOOPBACK_FAILED 2
9997 #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
9998 TG3_PHY_LOOPBACK_FAILED)
9999
10000 static int tg3_test_loopback(struct tg3 *tp)
10001 {
10002 int err = 0;
10003 u32 cpmuctrl = 0;
10004
10005 if (!netif_running(tp->dev))
10006 return TG3_LOOPBACK_FAILED;
10007
10008 err = tg3_reset_hw(tp, 1);
10009 if (err)
10010 return TG3_LOOPBACK_FAILED;
10011
10012 /* Turn off gphy autopowerdown. */
10013 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10014 tg3_phy_toggle_apd(tp, false);
10015
10016 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10017 int i;
10018 u32 status;
10019
10020 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10021
10022 /* Wait for up to 40 microseconds to acquire lock. */
10023 for (i = 0; i < 4; i++) {
10024 status = tr32(TG3_CPMU_MUTEX_GNT);
10025 if (status == CPMU_MUTEX_GNT_DRIVER)
10026 break;
10027 udelay(10);
10028 }
10029
10030 if (status != CPMU_MUTEX_GNT_DRIVER)
10031 return TG3_LOOPBACK_FAILED;
10032
10033 /* Turn off link-based power management. */
10034 cpmuctrl = tr32(TG3_CPMU_CTRL);
10035 tw32(TG3_CPMU_CTRL,
10036 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10037 CPMU_CTRL_LINK_AWARE_MODE));
10038 }
10039
10040 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10041 err |= TG3_MAC_LOOPBACK_FAILED;
10042
10043 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10044 tw32(TG3_CPMU_CTRL, cpmuctrl);
10045
10046 /* Release the mutex */
10047 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10048 }
10049
10050 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10051 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10052 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10053 err |= TG3_PHY_LOOPBACK_FAILED;
10054 }
10055
10056 /* Re-enable gphy autopowerdown. */
10057 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10058 tg3_phy_toggle_apd(tp, true);
10059
10060 return err;
10061 }
10062
10063 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10064 u64 *data)
10065 {
10066 struct tg3 *tp = netdev_priv(dev);
10067
10068 if (tp->link_config.phy_is_low_power)
10069 tg3_set_power_state(tp, PCI_D0);
10070
10071 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10072
10073 if (tg3_test_nvram(tp) != 0) {
10074 etest->flags |= ETH_TEST_FL_FAILED;
10075 data[0] = 1;
10076 }
10077 if (tg3_test_link(tp) != 0) {
10078 etest->flags |= ETH_TEST_FL_FAILED;
10079 data[1] = 1;
10080 }
10081 if (etest->flags & ETH_TEST_FL_OFFLINE) {
10082 int err, err2 = 0, irq_sync = 0;
10083
10084 if (netif_running(dev)) {
10085 tg3_phy_stop(tp);
10086 tg3_netif_stop(tp);
10087 irq_sync = 1;
10088 }
10089
10090 tg3_full_lock(tp, irq_sync);
10091
10092 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10093 err = tg3_nvram_lock(tp);
10094 tg3_halt_cpu(tp, RX_CPU_BASE);
10095 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10096 tg3_halt_cpu(tp, TX_CPU_BASE);
10097 if (!err)
10098 tg3_nvram_unlock(tp);
10099
10100 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10101 tg3_phy_reset(tp);
10102
10103 if (tg3_test_registers(tp) != 0) {
10104 etest->flags |= ETH_TEST_FL_FAILED;
10105 data[2] = 1;
10106 }
10107 if (tg3_test_memory(tp) != 0) {
10108 etest->flags |= ETH_TEST_FL_FAILED;
10109 data[3] = 1;
10110 }
10111 if ((data[4] = tg3_test_loopback(tp)) != 0)
10112 etest->flags |= ETH_TEST_FL_FAILED;
10113
10114 tg3_full_unlock(tp);
10115
10116 if (tg3_test_interrupt(tp) != 0) {
10117 etest->flags |= ETH_TEST_FL_FAILED;
10118 data[5] = 1;
10119 }
10120
10121 tg3_full_lock(tp, 0);
10122
10123 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10124 if (netif_running(dev)) {
10125 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10126 err2 = tg3_restart_hw(tp, 1);
10127 if (!err2)
10128 tg3_netif_start(tp);
10129 }
10130
10131 tg3_full_unlock(tp);
10132
10133 if (irq_sync && !err2)
10134 tg3_phy_start(tp);
10135 }
10136 if (tp->link_config.phy_is_low_power)
10137 tg3_set_power_state(tp, PCI_D3hot);
10138
10139 }
10140
10141 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10142 {
10143 struct mii_ioctl_data *data = if_mii(ifr);
10144 struct tg3 *tp = netdev_priv(dev);
10145 int err;
10146
10147 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10148 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10149 return -EAGAIN;
10150 return phy_mii_ioctl(tp->mdio_bus->phy_map[PHY_ADDR], data, cmd);
10151 }
10152
10153 switch(cmd) {
10154 case SIOCGMIIPHY:
10155 data->phy_id = PHY_ADDR;
10156
10157 /* fallthru */
10158 case SIOCGMIIREG: {
10159 u32 mii_regval;
10160
10161 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10162 break; /* We have no PHY */
10163
10164 if (tp->link_config.phy_is_low_power)
10165 return -EAGAIN;
10166
10167 spin_lock_bh(&tp->lock);
10168 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10169 spin_unlock_bh(&tp->lock);
10170
10171 data->val_out = mii_regval;
10172
10173 return err;
10174 }
10175
10176 case SIOCSMIIREG:
10177 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10178 break; /* We have no PHY */
10179
10180 if (!capable(CAP_NET_ADMIN))
10181 return -EPERM;
10182
10183 if (tp->link_config.phy_is_low_power)
10184 return -EAGAIN;
10185
10186 spin_lock_bh(&tp->lock);
10187 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
10188 spin_unlock_bh(&tp->lock);
10189
10190 return err;
10191
10192 default:
10193 /* do nothing */
10194 break;
10195 }
10196 return -EOPNOTSUPP;
10197 }
10198
10199 #if TG3_VLAN_TAG_USED
10200 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10201 {
10202 struct tg3 *tp = netdev_priv(dev);
10203
10204 if (!netif_running(dev)) {
10205 tp->vlgrp = grp;
10206 return;
10207 }
10208
10209 tg3_netif_stop(tp);
10210
10211 tg3_full_lock(tp, 0);
10212
10213 tp->vlgrp = grp;
10214
10215 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10216 __tg3_set_rx_mode(dev);
10217
10218 tg3_netif_start(tp);
10219
10220 tg3_full_unlock(tp);
10221 }
10222 #endif
10223
10224 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10225 {
10226 struct tg3 *tp = netdev_priv(dev);
10227
10228 memcpy(ec, &tp->coal, sizeof(*ec));
10229 return 0;
10230 }
10231
10232 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10233 {
10234 struct tg3 *tp = netdev_priv(dev);
10235 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10236 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10237
10238 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10239 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10240 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10241 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10242 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10243 }
10244
10245 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10246 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10247 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10248 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10249 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10250 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10251 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10252 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10253 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10254 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10255 return -EINVAL;
10256
10257 /* No rx interrupts will be generated if both are zero */
10258 if ((ec->rx_coalesce_usecs == 0) &&
10259 (ec->rx_max_coalesced_frames == 0))
10260 return -EINVAL;
10261
10262 /* No tx interrupts will be generated if both are zero */
10263 if ((ec->tx_coalesce_usecs == 0) &&
10264 (ec->tx_max_coalesced_frames == 0))
10265 return -EINVAL;
10266
10267 /* Only copy relevant parameters, ignore all others. */
10268 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10269 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10270 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10271 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10272 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10273 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10274 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10275 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10276 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10277
10278 if (netif_running(dev)) {
10279 tg3_full_lock(tp, 0);
10280 __tg3_set_coalesce(tp, &tp->coal);
10281 tg3_full_unlock(tp);
10282 }
10283 return 0;
10284 }
10285
10286 static const struct ethtool_ops tg3_ethtool_ops = {
10287 .get_settings = tg3_get_settings,
10288 .set_settings = tg3_set_settings,
10289 .get_drvinfo = tg3_get_drvinfo,
10290 .get_regs_len = tg3_get_regs_len,
10291 .get_regs = tg3_get_regs,
10292 .get_wol = tg3_get_wol,
10293 .set_wol = tg3_set_wol,
10294 .get_msglevel = tg3_get_msglevel,
10295 .set_msglevel = tg3_set_msglevel,
10296 .nway_reset = tg3_nway_reset,
10297 .get_link = ethtool_op_get_link,
10298 .get_eeprom_len = tg3_get_eeprom_len,
10299 .get_eeprom = tg3_get_eeprom,
10300 .set_eeprom = tg3_set_eeprom,
10301 .get_ringparam = tg3_get_ringparam,
10302 .set_ringparam = tg3_set_ringparam,
10303 .get_pauseparam = tg3_get_pauseparam,
10304 .set_pauseparam = tg3_set_pauseparam,
10305 .get_rx_csum = tg3_get_rx_csum,
10306 .set_rx_csum = tg3_set_rx_csum,
10307 .set_tx_csum = tg3_set_tx_csum,
10308 .set_sg = ethtool_op_set_sg,
10309 .set_tso = tg3_set_tso,
10310 .self_test = tg3_self_test,
10311 .get_strings = tg3_get_strings,
10312 .phys_id = tg3_phys_id,
10313 .get_ethtool_stats = tg3_get_ethtool_stats,
10314 .get_coalesce = tg3_get_coalesce,
10315 .set_coalesce = tg3_set_coalesce,
10316 .get_sset_count = tg3_get_sset_count,
10317 };
10318
10319 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10320 {
10321 u32 cursize, val, magic;
10322
10323 tp->nvram_size = EEPROM_CHIP_SIZE;
10324
10325 if (tg3_nvram_read(tp, 0, &magic) != 0)
10326 return;
10327
10328 if ((magic != TG3_EEPROM_MAGIC) &&
10329 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10330 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
10331 return;
10332
10333 /*
10334 * Size the chip by reading offsets at increasing powers of two.
10335 * When we encounter our validation signature, we know the addressing
10336 * has wrapped around, and thus have our chip size.
10337 */
10338 cursize = 0x10;
10339
10340 while (cursize < tp->nvram_size) {
10341 if (tg3_nvram_read(tp, cursize, &val) != 0)
10342 return;
10343
10344 if (val == magic)
10345 break;
10346
10347 cursize <<= 1;
10348 }
10349
10350 tp->nvram_size = cursize;
10351 }
10352
10353 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10354 {
10355 u32 val;
10356
10357 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
10358 tg3_nvram_read(tp, 0, &val) != 0)
10359 return;
10360
10361 /* Selfboot format */
10362 if (val != TG3_EEPROM_MAGIC) {
10363 tg3_get_eeprom_size(tp);
10364 return;
10365 }
10366
10367 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
10368 if (val != 0) {
10369 /* This is confusing. We want to operate on the
10370 * 16-bit value at offset 0xf2. The tg3_nvram_read()
10371 * call will read from NVRAM and byteswap the data
10372 * according to the byteswapping settings for all
10373 * other register accesses. This ensures the data we
10374 * want will always reside in the lower 16-bits.
10375 * However, the data in NVRAM is in LE format, which
10376 * means the data from the NVRAM read will always be
10377 * opposite the endianness of the CPU. The 16-bit
10378 * byteswap then brings the data to CPU endianness.
10379 */
10380 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
10381 return;
10382 }
10383 }
10384 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10385 }
10386
10387 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10388 {
10389 u32 nvcfg1;
10390
10391 nvcfg1 = tr32(NVRAM_CFG1);
10392 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10393 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10394 } else {
10395 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10396 tw32(NVRAM_CFG1, nvcfg1);
10397 }
10398
10399 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
10400 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
10401 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
10402 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10403 tp->nvram_jedecnum = JEDEC_ATMEL;
10404 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10405 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10406 break;
10407 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10408 tp->nvram_jedecnum = JEDEC_ATMEL;
10409 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10410 break;
10411 case FLASH_VENDOR_ATMEL_EEPROM:
10412 tp->nvram_jedecnum = JEDEC_ATMEL;
10413 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10414 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10415 break;
10416 case FLASH_VENDOR_ST:
10417 tp->nvram_jedecnum = JEDEC_ST;
10418 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10419 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10420 break;
10421 case FLASH_VENDOR_SAIFUN:
10422 tp->nvram_jedecnum = JEDEC_SAIFUN;
10423 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10424 break;
10425 case FLASH_VENDOR_SST_SMALL:
10426 case FLASH_VENDOR_SST_LARGE:
10427 tp->nvram_jedecnum = JEDEC_SST;
10428 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10429 break;
10430 }
10431 } else {
10432 tp->nvram_jedecnum = JEDEC_ATMEL;
10433 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10434 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10435 }
10436 }
10437
10438 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10439 {
10440 u32 nvcfg1;
10441
10442 nvcfg1 = tr32(NVRAM_CFG1);
10443
10444 /* NVRAM protection for TPM */
10445 if (nvcfg1 & (1 << 27))
10446 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10447
10448 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10449 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10450 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10451 tp->nvram_jedecnum = JEDEC_ATMEL;
10452 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10453 break;
10454 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10455 tp->nvram_jedecnum = JEDEC_ATMEL;
10456 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10457 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10458 break;
10459 case FLASH_5752VENDOR_ST_M45PE10:
10460 case FLASH_5752VENDOR_ST_M45PE20:
10461 case FLASH_5752VENDOR_ST_M45PE40:
10462 tp->nvram_jedecnum = JEDEC_ST;
10463 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10464 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10465 break;
10466 }
10467
10468 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
10469 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10470 case FLASH_5752PAGE_SIZE_256:
10471 tp->nvram_pagesize = 256;
10472 break;
10473 case FLASH_5752PAGE_SIZE_512:
10474 tp->nvram_pagesize = 512;
10475 break;
10476 case FLASH_5752PAGE_SIZE_1K:
10477 tp->nvram_pagesize = 1024;
10478 break;
10479 case FLASH_5752PAGE_SIZE_2K:
10480 tp->nvram_pagesize = 2048;
10481 break;
10482 case FLASH_5752PAGE_SIZE_4K:
10483 tp->nvram_pagesize = 4096;
10484 break;
10485 case FLASH_5752PAGE_SIZE_264:
10486 tp->nvram_pagesize = 264;
10487 break;
10488 }
10489 } else {
10490 /* For eeprom, set pagesize to maximum eeprom size */
10491 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10492
10493 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10494 tw32(NVRAM_CFG1, nvcfg1);
10495 }
10496 }
10497
10498 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10499 {
10500 u32 nvcfg1, protect = 0;
10501
10502 nvcfg1 = tr32(NVRAM_CFG1);
10503
10504 /* NVRAM protection for TPM */
10505 if (nvcfg1 & (1 << 27)) {
10506 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10507 protect = 1;
10508 }
10509
10510 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10511 switch (nvcfg1) {
10512 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10513 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10514 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10515 case FLASH_5755VENDOR_ATMEL_FLASH_5:
10516 tp->nvram_jedecnum = JEDEC_ATMEL;
10517 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10518 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10519 tp->nvram_pagesize = 264;
10520 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
10521 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
10522 tp->nvram_size = (protect ? 0x3e200 :
10523 TG3_NVRAM_SIZE_512KB);
10524 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
10525 tp->nvram_size = (protect ? 0x1f200 :
10526 TG3_NVRAM_SIZE_256KB);
10527 else
10528 tp->nvram_size = (protect ? 0x1f200 :
10529 TG3_NVRAM_SIZE_128KB);
10530 break;
10531 case FLASH_5752VENDOR_ST_M45PE10:
10532 case FLASH_5752VENDOR_ST_M45PE20:
10533 case FLASH_5752VENDOR_ST_M45PE40:
10534 tp->nvram_jedecnum = JEDEC_ST;
10535 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10536 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10537 tp->nvram_pagesize = 256;
10538 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
10539 tp->nvram_size = (protect ?
10540 TG3_NVRAM_SIZE_64KB :
10541 TG3_NVRAM_SIZE_128KB);
10542 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
10543 tp->nvram_size = (protect ?
10544 TG3_NVRAM_SIZE_64KB :
10545 TG3_NVRAM_SIZE_256KB);
10546 else
10547 tp->nvram_size = (protect ?
10548 TG3_NVRAM_SIZE_128KB :
10549 TG3_NVRAM_SIZE_512KB);
10550 break;
10551 }
10552 }
10553
10554 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
10555 {
10556 u32 nvcfg1;
10557
10558 nvcfg1 = tr32(NVRAM_CFG1);
10559
10560 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10561 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
10562 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10563 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
10564 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10565 tp->nvram_jedecnum = JEDEC_ATMEL;
10566 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10567 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10568
10569 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10570 tw32(NVRAM_CFG1, nvcfg1);
10571 break;
10572 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10573 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10574 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10575 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10576 tp->nvram_jedecnum = JEDEC_ATMEL;
10577 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10578 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10579 tp->nvram_pagesize = 264;
10580 break;
10581 case FLASH_5752VENDOR_ST_M45PE10:
10582 case FLASH_5752VENDOR_ST_M45PE20:
10583 case FLASH_5752VENDOR_ST_M45PE40:
10584 tp->nvram_jedecnum = JEDEC_ST;
10585 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10586 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10587 tp->nvram_pagesize = 256;
10588 break;
10589 }
10590 }
10591
10592 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
10593 {
10594 u32 nvcfg1, protect = 0;
10595
10596 nvcfg1 = tr32(NVRAM_CFG1);
10597
10598 /* NVRAM protection for TPM */
10599 if (nvcfg1 & (1 << 27)) {
10600 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10601 protect = 1;
10602 }
10603
10604 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10605 switch (nvcfg1) {
10606 case FLASH_5761VENDOR_ATMEL_ADB021D:
10607 case FLASH_5761VENDOR_ATMEL_ADB041D:
10608 case FLASH_5761VENDOR_ATMEL_ADB081D:
10609 case FLASH_5761VENDOR_ATMEL_ADB161D:
10610 case FLASH_5761VENDOR_ATMEL_MDB021D:
10611 case FLASH_5761VENDOR_ATMEL_MDB041D:
10612 case FLASH_5761VENDOR_ATMEL_MDB081D:
10613 case FLASH_5761VENDOR_ATMEL_MDB161D:
10614 tp->nvram_jedecnum = JEDEC_ATMEL;
10615 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10616 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10617 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10618 tp->nvram_pagesize = 256;
10619 break;
10620 case FLASH_5761VENDOR_ST_A_M45PE20:
10621 case FLASH_5761VENDOR_ST_A_M45PE40:
10622 case FLASH_5761VENDOR_ST_A_M45PE80:
10623 case FLASH_5761VENDOR_ST_A_M45PE16:
10624 case FLASH_5761VENDOR_ST_M_M45PE20:
10625 case FLASH_5761VENDOR_ST_M_M45PE40:
10626 case FLASH_5761VENDOR_ST_M_M45PE80:
10627 case FLASH_5761VENDOR_ST_M_M45PE16:
10628 tp->nvram_jedecnum = JEDEC_ST;
10629 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10630 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10631 tp->nvram_pagesize = 256;
10632 break;
10633 }
10634
10635 if (protect) {
10636 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
10637 } else {
10638 switch (nvcfg1) {
10639 case FLASH_5761VENDOR_ATMEL_ADB161D:
10640 case FLASH_5761VENDOR_ATMEL_MDB161D:
10641 case FLASH_5761VENDOR_ST_A_M45PE16:
10642 case FLASH_5761VENDOR_ST_M_M45PE16:
10643 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
10644 break;
10645 case FLASH_5761VENDOR_ATMEL_ADB081D:
10646 case FLASH_5761VENDOR_ATMEL_MDB081D:
10647 case FLASH_5761VENDOR_ST_A_M45PE80:
10648 case FLASH_5761VENDOR_ST_M_M45PE80:
10649 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
10650 break;
10651 case FLASH_5761VENDOR_ATMEL_ADB041D:
10652 case FLASH_5761VENDOR_ATMEL_MDB041D:
10653 case FLASH_5761VENDOR_ST_A_M45PE40:
10654 case FLASH_5761VENDOR_ST_M_M45PE40:
10655 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10656 break;
10657 case FLASH_5761VENDOR_ATMEL_ADB021D:
10658 case FLASH_5761VENDOR_ATMEL_MDB021D:
10659 case FLASH_5761VENDOR_ST_A_M45PE20:
10660 case FLASH_5761VENDOR_ST_M_M45PE20:
10661 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10662 break;
10663 }
10664 }
10665 }
10666
10667 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
10668 {
10669 tp->nvram_jedecnum = JEDEC_ATMEL;
10670 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10671 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10672 }
10673
10674 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
10675 {
10676 u32 nvcfg1;
10677
10678 nvcfg1 = tr32(NVRAM_CFG1);
10679
10680 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10681 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10682 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10683 tp->nvram_jedecnum = JEDEC_ATMEL;
10684 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10685 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10686
10687 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10688 tw32(NVRAM_CFG1, nvcfg1);
10689 return;
10690 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10691 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10692 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10693 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10694 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10695 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10696 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10697 tp->nvram_jedecnum = JEDEC_ATMEL;
10698 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10699 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10700
10701 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10702 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10703 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10704 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10705 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10706 break;
10707 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10708 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10709 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10710 break;
10711 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10712 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10713 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10714 break;
10715 }
10716 break;
10717 case FLASH_5752VENDOR_ST_M45PE10:
10718 case FLASH_5752VENDOR_ST_M45PE20:
10719 case FLASH_5752VENDOR_ST_M45PE40:
10720 tp->nvram_jedecnum = JEDEC_ST;
10721 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10722 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10723
10724 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10725 case FLASH_5752VENDOR_ST_M45PE10:
10726 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10727 break;
10728 case FLASH_5752VENDOR_ST_M45PE20:
10729 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10730 break;
10731 case FLASH_5752VENDOR_ST_M45PE40:
10732 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10733 break;
10734 }
10735 break;
10736 default:
10737 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
10738 return;
10739 }
10740
10741 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10742 case FLASH_5752PAGE_SIZE_256:
10743 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10744 tp->nvram_pagesize = 256;
10745 break;
10746 case FLASH_5752PAGE_SIZE_512:
10747 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10748 tp->nvram_pagesize = 512;
10749 break;
10750 case FLASH_5752PAGE_SIZE_1K:
10751 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10752 tp->nvram_pagesize = 1024;
10753 break;
10754 case FLASH_5752PAGE_SIZE_2K:
10755 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10756 tp->nvram_pagesize = 2048;
10757 break;
10758 case FLASH_5752PAGE_SIZE_4K:
10759 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10760 tp->nvram_pagesize = 4096;
10761 break;
10762 case FLASH_5752PAGE_SIZE_264:
10763 tp->nvram_pagesize = 264;
10764 break;
10765 case FLASH_5752PAGE_SIZE_528:
10766 tp->nvram_pagesize = 528;
10767 break;
10768 }
10769 }
10770
10771 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
10772 static void __devinit tg3_nvram_init(struct tg3 *tp)
10773 {
10774 tw32_f(GRC_EEPROM_ADDR,
10775 (EEPROM_ADDR_FSM_RESET |
10776 (EEPROM_DEFAULT_CLOCK_PERIOD <<
10777 EEPROM_ADDR_CLKPERD_SHIFT)));
10778
10779 msleep(1);
10780
10781 /* Enable seeprom accesses. */
10782 tw32_f(GRC_LOCAL_CTRL,
10783 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
10784 udelay(100);
10785
10786 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10787 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
10788 tp->tg3_flags |= TG3_FLAG_NVRAM;
10789
10790 if (tg3_nvram_lock(tp)) {
10791 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
10792 "tg3_nvram_init failed.\n", tp->dev->name);
10793 return;
10794 }
10795 tg3_enable_nvram_access(tp);
10796
10797 tp->nvram_size = 0;
10798
10799 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10800 tg3_get_5752_nvram_info(tp);
10801 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10802 tg3_get_5755_nvram_info(tp);
10803 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10804 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
10805 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10806 tg3_get_5787_nvram_info(tp);
10807 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
10808 tg3_get_5761_nvram_info(tp);
10809 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10810 tg3_get_5906_nvram_info(tp);
10811 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
10812 tg3_get_57780_nvram_info(tp);
10813 else
10814 tg3_get_nvram_info(tp);
10815
10816 if (tp->nvram_size == 0)
10817 tg3_get_nvram_size(tp);
10818
10819 tg3_disable_nvram_access(tp);
10820 tg3_nvram_unlock(tp);
10821
10822 } else {
10823 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
10824
10825 tg3_get_eeprom_size(tp);
10826 }
10827 }
10828
10829 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
10830 u32 offset, u32 len, u8 *buf)
10831 {
10832 int i, j, rc = 0;
10833 u32 val;
10834
10835 for (i = 0; i < len; i += 4) {
10836 u32 addr;
10837 __be32 data;
10838
10839 addr = offset + i;
10840
10841 memcpy(&data, buf + i, 4);
10842
10843 /*
10844 * The SEEPROM interface expects the data to always be opposite
10845 * the native endian format. We accomplish this by reversing
10846 * all the operations that would have been performed on the
10847 * data from a call to tg3_nvram_read_be32().
10848 */
10849 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
10850
10851 val = tr32(GRC_EEPROM_ADDR);
10852 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
10853
10854 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
10855 EEPROM_ADDR_READ);
10856 tw32(GRC_EEPROM_ADDR, val |
10857 (0 << EEPROM_ADDR_DEVID_SHIFT) |
10858 (addr & EEPROM_ADDR_ADDR_MASK) |
10859 EEPROM_ADDR_START |
10860 EEPROM_ADDR_WRITE);
10861
10862 for (j = 0; j < 1000; j++) {
10863 val = tr32(GRC_EEPROM_ADDR);
10864
10865 if (val & EEPROM_ADDR_COMPLETE)
10866 break;
10867 msleep(1);
10868 }
10869 if (!(val & EEPROM_ADDR_COMPLETE)) {
10870 rc = -EBUSY;
10871 break;
10872 }
10873 }
10874
10875 return rc;
10876 }
10877
10878 /* offset and length are dword aligned */
10879 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
10880 u8 *buf)
10881 {
10882 int ret = 0;
10883 u32 pagesize = tp->nvram_pagesize;
10884 u32 pagemask = pagesize - 1;
10885 u32 nvram_cmd;
10886 u8 *tmp;
10887
10888 tmp = kmalloc(pagesize, GFP_KERNEL);
10889 if (tmp == NULL)
10890 return -ENOMEM;
10891
10892 while (len) {
10893 int j;
10894 u32 phy_addr, page_off, size;
10895
10896 phy_addr = offset & ~pagemask;
10897
10898 for (j = 0; j < pagesize; j += 4) {
10899 ret = tg3_nvram_read_be32(tp, phy_addr + j,
10900 (__be32 *) (tmp + j));
10901 if (ret)
10902 break;
10903 }
10904 if (ret)
10905 break;
10906
10907 page_off = offset & pagemask;
10908 size = pagesize;
10909 if (len < size)
10910 size = len;
10911
10912 len -= size;
10913
10914 memcpy(tmp + page_off, buf, size);
10915
10916 offset = offset + (pagesize - page_off);
10917
10918 tg3_enable_nvram_access(tp);
10919
10920 /*
10921 * Before we can erase the flash page, we need
10922 * to issue a special "write enable" command.
10923 */
10924 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10925
10926 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10927 break;
10928
10929 /* Erase the target page */
10930 tw32(NVRAM_ADDR, phy_addr);
10931
10932 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
10933 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
10934
10935 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10936 break;
10937
10938 /* Issue another write enable to start the write. */
10939 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10940
10941 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10942 break;
10943
10944 for (j = 0; j < pagesize; j += 4) {
10945 __be32 data;
10946
10947 data = *((__be32 *) (tmp + j));
10948
10949 tw32(NVRAM_WRDATA, be32_to_cpu(data));
10950
10951 tw32(NVRAM_ADDR, phy_addr + j);
10952
10953 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
10954 NVRAM_CMD_WR;
10955
10956 if (j == 0)
10957 nvram_cmd |= NVRAM_CMD_FIRST;
10958 else if (j == (pagesize - 4))
10959 nvram_cmd |= NVRAM_CMD_LAST;
10960
10961 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10962 break;
10963 }
10964 if (ret)
10965 break;
10966 }
10967
10968 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10969 tg3_nvram_exec_cmd(tp, nvram_cmd);
10970
10971 kfree(tmp);
10972
10973 return ret;
10974 }
10975
10976 /* offset and length are dword aligned */
10977 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
10978 u8 *buf)
10979 {
10980 int i, ret = 0;
10981
10982 for (i = 0; i < len; i += 4, offset += 4) {
10983 u32 page_off, phy_addr, nvram_cmd;
10984 __be32 data;
10985
10986 memcpy(&data, buf + i, 4);
10987 tw32(NVRAM_WRDATA, be32_to_cpu(data));
10988
10989 page_off = offset % tp->nvram_pagesize;
10990
10991 phy_addr = tg3_nvram_phys_addr(tp, offset);
10992
10993 tw32(NVRAM_ADDR, phy_addr);
10994
10995 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
10996
10997 if ((page_off == 0) || (i == 0))
10998 nvram_cmd |= NVRAM_CMD_FIRST;
10999 if (page_off == (tp->nvram_pagesize - 4))
11000 nvram_cmd |= NVRAM_CMD_LAST;
11001
11002 if (i == (len - 4))
11003 nvram_cmd |= NVRAM_CMD_LAST;
11004
11005 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11006 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
11007 (tp->nvram_jedecnum == JEDEC_ST) &&
11008 (nvram_cmd & NVRAM_CMD_FIRST)) {
11009
11010 if ((ret = tg3_nvram_exec_cmd(tp,
11011 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11012 NVRAM_CMD_DONE)))
11013
11014 break;
11015 }
11016 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11017 /* We always do complete word writes to eeprom. */
11018 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11019 }
11020
11021 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11022 break;
11023 }
11024 return ret;
11025 }
11026
11027 /* offset and length are dword aligned */
11028 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11029 {
11030 int ret;
11031
11032 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11033 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11034 ~GRC_LCLCTRL_GPIO_OUTPUT1);
11035 udelay(40);
11036 }
11037
11038 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11039 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11040 }
11041 else {
11042 u32 grc_mode;
11043
11044 ret = tg3_nvram_lock(tp);
11045 if (ret)
11046 return ret;
11047
11048 tg3_enable_nvram_access(tp);
11049 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11050 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
11051 tw32(NVRAM_WRITE1, 0x406);
11052
11053 grc_mode = tr32(GRC_MODE);
11054 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11055
11056 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11057 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11058
11059 ret = tg3_nvram_write_block_buffered(tp, offset, len,
11060 buf);
11061 }
11062 else {
11063 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11064 buf);
11065 }
11066
11067 grc_mode = tr32(GRC_MODE);
11068 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11069
11070 tg3_disable_nvram_access(tp);
11071 tg3_nvram_unlock(tp);
11072 }
11073
11074 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11075 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
11076 udelay(40);
11077 }
11078
11079 return ret;
11080 }
11081
11082 struct subsys_tbl_ent {
11083 u16 subsys_vendor, subsys_devid;
11084 u32 phy_id;
11085 };
11086
11087 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
11088 /* Broadcom boards. */
11089 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
11090 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
11091 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
11092 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
11093 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
11094 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
11095 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
11096 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
11097 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
11098 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
11099 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
11100
11101 /* 3com boards. */
11102 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
11103 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
11104 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
11105 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
11106 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
11107
11108 /* DELL boards. */
11109 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
11110 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
11111 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
11112 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
11113
11114 /* Compaq boards. */
11115 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
11116 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
11117 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
11118 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
11119 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
11120
11121 /* IBM boards. */
11122 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
11123 };
11124
11125 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
11126 {
11127 int i;
11128
11129 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11130 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11131 tp->pdev->subsystem_vendor) &&
11132 (subsys_id_to_phy_id[i].subsys_devid ==
11133 tp->pdev->subsystem_device))
11134 return &subsys_id_to_phy_id[i];
11135 }
11136 return NULL;
11137 }
11138
11139 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
11140 {
11141 u32 val;
11142 u16 pmcsr;
11143
11144 /* On some early chips the SRAM cannot be accessed in D3hot state,
11145 * so need make sure we're in D0.
11146 */
11147 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11148 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11149 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11150 msleep(1);
11151
11152 /* Make sure register accesses (indirect or otherwise)
11153 * will function correctly.
11154 */
11155 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11156 tp->misc_host_ctrl);
11157
11158 /* The memory arbiter has to be enabled in order for SRAM accesses
11159 * to succeed. Normally on powerup the tg3 chip firmware will make
11160 * sure it is enabled, but other entities such as system netboot
11161 * code might disable it.
11162 */
11163 val = tr32(MEMARB_MODE);
11164 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11165
11166 tp->phy_id = PHY_ID_INVALID;
11167 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11168
11169 /* Assume an onboard device and WOL capable by default. */
11170 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
11171
11172 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11173 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
11174 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11175 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11176 }
11177 val = tr32(VCPU_CFGSHDW);
11178 if (val & VCPU_CFGSHDW_ASPM_DBNC)
11179 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11180 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
11181 (val & VCPU_CFGSHDW_WOL_MAGPKT))
11182 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11183 goto done;
11184 }
11185
11186 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11187 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11188 u32 nic_cfg, led_cfg;
11189 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
11190 int eeprom_phy_serdes = 0;
11191
11192 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11193 tp->nic_sram_data_cfg = nic_cfg;
11194
11195 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11196 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11197 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11198 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11199 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11200 (ver > 0) && (ver < 0x100))
11201 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11202
11203 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11204 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11205
11206 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11207 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11208 eeprom_phy_serdes = 1;
11209
11210 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11211 if (nic_phy_id != 0) {
11212 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11213 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11214
11215 eeprom_phy_id = (id1 >> 16) << 10;
11216 eeprom_phy_id |= (id2 & 0xfc00) << 16;
11217 eeprom_phy_id |= (id2 & 0x03ff) << 0;
11218 } else
11219 eeprom_phy_id = 0;
11220
11221 tp->phy_id = eeprom_phy_id;
11222 if (eeprom_phy_serdes) {
11223 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
11224 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11225 else
11226 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11227 }
11228
11229 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11230 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11231 SHASTA_EXT_LED_MODE_MASK);
11232 else
11233 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11234
11235 switch (led_cfg) {
11236 default:
11237 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11238 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11239 break;
11240
11241 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11242 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11243 break;
11244
11245 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11246 tp->led_ctrl = LED_CTRL_MODE_MAC;
11247
11248 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11249 * read on some older 5700/5701 bootcode.
11250 */
11251 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11252 ASIC_REV_5700 ||
11253 GET_ASIC_REV(tp->pci_chip_rev_id) ==
11254 ASIC_REV_5701)
11255 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11256
11257 break;
11258
11259 case SHASTA_EXT_LED_SHARED:
11260 tp->led_ctrl = LED_CTRL_MODE_SHARED;
11261 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11262 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11263 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11264 LED_CTRL_MODE_PHY_2);
11265 break;
11266
11267 case SHASTA_EXT_LED_MAC:
11268 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11269 break;
11270
11271 case SHASTA_EXT_LED_COMBO:
11272 tp->led_ctrl = LED_CTRL_MODE_COMBO;
11273 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11274 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11275 LED_CTRL_MODE_PHY_2);
11276 break;
11277
11278 }
11279
11280 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11281 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11282 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11283 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11284
11285 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11286 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11287
11288 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
11289 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
11290 if ((tp->pdev->subsystem_vendor ==
11291 PCI_VENDOR_ID_ARIMA) &&
11292 (tp->pdev->subsystem_device == 0x205a ||
11293 tp->pdev->subsystem_device == 0x2063))
11294 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11295 } else {
11296 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11297 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11298 }
11299
11300 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11301 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
11302 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11303 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11304 }
11305
11306 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
11307 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
11308 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
11309
11310 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11311 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11312 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
11313
11314 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
11315 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
11316 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11317
11318 if (cfg2 & (1 << 17))
11319 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11320
11321 /* serdes signal pre-emphasis in register 0x590 set by */
11322 /* bootcode if bit 18 is set */
11323 if (cfg2 & (1 << 18))
11324 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
11325
11326 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11327 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
11328 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
11329 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
11330
11331 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11332 u32 cfg3;
11333
11334 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11335 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11336 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11337 }
11338
11339 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11340 tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11341 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11342 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11343 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11344 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
11345 }
11346 done:
11347 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
11348 device_set_wakeup_enable(&tp->pdev->dev,
11349 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
11350 }
11351
11352 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11353 {
11354 int i;
11355 u32 val;
11356
11357 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11358 tw32(OTP_CTRL, cmd);
11359
11360 /* Wait for up to 1 ms for command to execute. */
11361 for (i = 0; i < 100; i++) {
11362 val = tr32(OTP_STATUS);
11363 if (val & OTP_STATUS_CMD_DONE)
11364 break;
11365 udelay(10);
11366 }
11367
11368 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11369 }
11370
11371 /* Read the gphy configuration from the OTP region of the chip. The gphy
11372 * configuration is a 32-bit value that straddles the alignment boundary.
11373 * We do two 32-bit reads and then shift and merge the results.
11374 */
11375 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11376 {
11377 u32 bhalf_otp, thalf_otp;
11378
11379 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11380
11381 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
11382 return 0;
11383
11384 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
11385
11386 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11387 return 0;
11388
11389 thalf_otp = tr32(OTP_READ_DATA);
11390
11391 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
11392
11393 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11394 return 0;
11395
11396 bhalf_otp = tr32(OTP_READ_DATA);
11397
11398 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
11399 }
11400
11401 static int __devinit tg3_phy_probe(struct tg3 *tp)
11402 {
11403 u32 hw_phy_id_1, hw_phy_id_2;
11404 u32 hw_phy_id, hw_phy_id_masked;
11405 int err;
11406
11407 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11408 return tg3_phy_init(tp);
11409
11410 /* Reading the PHY ID register can conflict with ASF
11411 * firmware access to the PHY hardware.
11412 */
11413 err = 0;
11414 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11415 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
11416 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
11417 } else {
11418 /* Now read the physical PHY_ID from the chip and verify
11419 * that it is sane. If it doesn't look good, we fall back
11420 * to either the hard-coded table based PHY_ID and failing
11421 * that the value found in the eeprom area.
11422 */
11423 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11424 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11425
11426 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
11427 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11428 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
11429
11430 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11431 }
11432
11433 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11434 tp->phy_id = hw_phy_id;
11435 if (hw_phy_id_masked == PHY_ID_BCM8002)
11436 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11437 else
11438 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
11439 } else {
11440 if (tp->phy_id != PHY_ID_INVALID) {
11441 /* Do nothing, phy ID already set up in
11442 * tg3_get_eeprom_hw_cfg().
11443 */
11444 } else {
11445 struct subsys_tbl_ent *p;
11446
11447 /* No eeprom signature? Try the hardcoded
11448 * subsys device table.
11449 */
11450 p = lookup_by_subsys(tp);
11451 if (!p)
11452 return -ENODEV;
11453
11454 tp->phy_id = p->phy_id;
11455 if (!tp->phy_id ||
11456 tp->phy_id == PHY_ID_BCM8002)
11457 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11458 }
11459 }
11460
11461 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
11462 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
11463 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
11464 u32 bmsr, adv_reg, tg3_ctrl, mask;
11465
11466 tg3_readphy(tp, MII_BMSR, &bmsr);
11467 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
11468 (bmsr & BMSR_LSTATUS))
11469 goto skip_phy_reset;
11470
11471 err = tg3_phy_reset(tp);
11472 if (err)
11473 return err;
11474
11475 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
11476 ADVERTISE_100HALF | ADVERTISE_100FULL |
11477 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
11478 tg3_ctrl = 0;
11479 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
11480 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
11481 MII_TG3_CTRL_ADV_1000_FULL);
11482 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
11483 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
11484 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
11485 MII_TG3_CTRL_ENABLE_AS_MASTER);
11486 }
11487
11488 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11489 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11490 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
11491 if (!tg3_copper_is_advertising_all(tp, mask)) {
11492 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11493
11494 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11495 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11496
11497 tg3_writephy(tp, MII_BMCR,
11498 BMCR_ANENABLE | BMCR_ANRESTART);
11499 }
11500 tg3_phy_set_wirespeed(tp);
11501
11502 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11503 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11504 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11505 }
11506
11507 skip_phy_reset:
11508 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
11509 err = tg3_init_5401phy_dsp(tp);
11510 if (err)
11511 return err;
11512 }
11513
11514 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
11515 err = tg3_init_5401phy_dsp(tp);
11516 }
11517
11518 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
11519 tp->link_config.advertising =
11520 (ADVERTISED_1000baseT_Half |
11521 ADVERTISED_1000baseT_Full |
11522 ADVERTISED_Autoneg |
11523 ADVERTISED_FIBRE);
11524 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
11525 tp->link_config.advertising &=
11526 ~(ADVERTISED_1000baseT_Half |
11527 ADVERTISED_1000baseT_Full);
11528
11529 return err;
11530 }
11531
11532 static void __devinit tg3_read_partno(struct tg3 *tp)
11533 {
11534 unsigned char vpd_data[256]; /* in little-endian format */
11535 unsigned int i;
11536 u32 magic;
11537
11538 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11539 tg3_nvram_read(tp, 0x0, &magic))
11540 goto out_not_found;
11541
11542 if (magic == TG3_EEPROM_MAGIC) {
11543 for (i = 0; i < 256; i += 4) {
11544 u32 tmp;
11545
11546 /* The data is in little-endian format in NVRAM.
11547 * Use the big-endian read routines to preserve
11548 * the byte order as it exists in NVRAM.
11549 */
11550 if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp))
11551 goto out_not_found;
11552
11553 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
11554 }
11555 } else {
11556 int vpd_cap;
11557
11558 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
11559 for (i = 0; i < 256; i += 4) {
11560 u32 tmp, j = 0;
11561 __le32 v;
11562 u16 tmp16;
11563
11564 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
11565 i);
11566 while (j++ < 100) {
11567 pci_read_config_word(tp->pdev, vpd_cap +
11568 PCI_VPD_ADDR, &tmp16);
11569 if (tmp16 & 0x8000)
11570 break;
11571 msleep(1);
11572 }
11573 if (!(tmp16 & 0x8000))
11574 goto out_not_found;
11575
11576 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
11577 &tmp);
11578 v = cpu_to_le32(tmp);
11579 memcpy(&vpd_data[i], &v, sizeof(v));
11580 }
11581 }
11582
11583 /* Now parse and find the part number. */
11584 for (i = 0; i < 254; ) {
11585 unsigned char val = vpd_data[i];
11586 unsigned int block_end;
11587
11588 if (val == 0x82 || val == 0x91) {
11589 i = (i + 3 +
11590 (vpd_data[i + 1] +
11591 (vpd_data[i + 2] << 8)));
11592 continue;
11593 }
11594
11595 if (val != 0x90)
11596 goto out_not_found;
11597
11598 block_end = (i + 3 +
11599 (vpd_data[i + 1] +
11600 (vpd_data[i + 2] << 8)));
11601 i += 3;
11602
11603 if (block_end > 256)
11604 goto out_not_found;
11605
11606 while (i < (block_end - 2)) {
11607 if (vpd_data[i + 0] == 'P' &&
11608 vpd_data[i + 1] == 'N') {
11609 int partno_len = vpd_data[i + 2];
11610
11611 i += 3;
11612 if (partno_len > 24 || (partno_len + i) > 256)
11613 goto out_not_found;
11614
11615 memcpy(tp->board_part_number,
11616 &vpd_data[i], partno_len);
11617
11618 /* Success. */
11619 return;
11620 }
11621 i += 3 + vpd_data[i + 2];
11622 }
11623
11624 /* Part number not found. */
11625 goto out_not_found;
11626 }
11627
11628 out_not_found:
11629 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11630 strcpy(tp->board_part_number, "BCM95906");
11631 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11632 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
11633 strcpy(tp->board_part_number, "BCM57780");
11634 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11635 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
11636 strcpy(tp->board_part_number, "BCM57760");
11637 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11638 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
11639 strcpy(tp->board_part_number, "BCM57790");
11640 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11641 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
11642 strcpy(tp->board_part_number, "BCM57788");
11643 else
11644 strcpy(tp->board_part_number, "none");
11645 }
11646
11647 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
11648 {
11649 u32 val;
11650
11651 if (tg3_nvram_read(tp, offset, &val) ||
11652 (val & 0xfc000000) != 0x0c000000 ||
11653 tg3_nvram_read(tp, offset + 4, &val) ||
11654 val != 0)
11655 return 0;
11656
11657 return 1;
11658 }
11659
11660 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
11661 {
11662 u32 val, offset, start, ver_offset;
11663 int i;
11664 bool newver = false;
11665
11666 if (tg3_nvram_read(tp, 0xc, &offset) ||
11667 tg3_nvram_read(tp, 0x4, &start))
11668 return;
11669
11670 offset = tg3_nvram_logical_addr(tp, offset);
11671
11672 if (tg3_nvram_read(tp, offset, &val))
11673 return;
11674
11675 if ((val & 0xfc000000) == 0x0c000000) {
11676 if (tg3_nvram_read(tp, offset + 4, &val))
11677 return;
11678
11679 if (val == 0)
11680 newver = true;
11681 }
11682
11683 if (newver) {
11684 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
11685 return;
11686
11687 offset = offset + ver_offset - start;
11688 for (i = 0; i < 16; i += 4) {
11689 __be32 v;
11690 if (tg3_nvram_read_be32(tp, offset + i, &v))
11691 return;
11692
11693 memcpy(tp->fw_ver + i, &v, sizeof(v));
11694 }
11695 } else {
11696 u32 major, minor;
11697
11698 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
11699 return;
11700
11701 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
11702 TG3_NVM_BCVER_MAJSFT;
11703 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
11704 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
11705 }
11706 }
11707
11708 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
11709 {
11710 u32 val, major, minor;
11711
11712 /* Use native endian representation */
11713 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
11714 return;
11715
11716 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
11717 TG3_NVM_HWSB_CFG1_MAJSFT;
11718 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
11719 TG3_NVM_HWSB_CFG1_MINSFT;
11720
11721 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
11722 }
11723
11724 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
11725 {
11726 u32 offset, major, minor, build;
11727
11728 tp->fw_ver[0] = 's';
11729 tp->fw_ver[1] = 'b';
11730 tp->fw_ver[2] = '\0';
11731
11732 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
11733 return;
11734
11735 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
11736 case TG3_EEPROM_SB_REVISION_0:
11737 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
11738 break;
11739 case TG3_EEPROM_SB_REVISION_2:
11740 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
11741 break;
11742 case TG3_EEPROM_SB_REVISION_3:
11743 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
11744 break;
11745 default:
11746 return;
11747 }
11748
11749 if (tg3_nvram_read(tp, offset, &val))
11750 return;
11751
11752 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
11753 TG3_EEPROM_SB_EDH_BLD_SHFT;
11754 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
11755 TG3_EEPROM_SB_EDH_MAJ_SHFT;
11756 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
11757
11758 if (minor > 99 || build > 26)
11759 return;
11760
11761 snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
11762
11763 if (build > 0) {
11764 tp->fw_ver[8] = 'a' + build - 1;
11765 tp->fw_ver[9] = '\0';
11766 }
11767 }
11768
11769 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
11770 {
11771 u32 val, offset, start;
11772 int i, vlen;
11773
11774 for (offset = TG3_NVM_DIR_START;
11775 offset < TG3_NVM_DIR_END;
11776 offset += TG3_NVM_DIRENT_SIZE) {
11777 if (tg3_nvram_read(tp, offset, &val))
11778 return;
11779
11780 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
11781 break;
11782 }
11783
11784 if (offset == TG3_NVM_DIR_END)
11785 return;
11786
11787 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11788 start = 0x08000000;
11789 else if (tg3_nvram_read(tp, offset - 4, &start))
11790 return;
11791
11792 if (tg3_nvram_read(tp, offset + 4, &offset) ||
11793 !tg3_fw_img_is_valid(tp, offset) ||
11794 tg3_nvram_read(tp, offset + 8, &val))
11795 return;
11796
11797 offset += val - start;
11798
11799 vlen = strlen(tp->fw_ver);
11800
11801 tp->fw_ver[vlen++] = ',';
11802 tp->fw_ver[vlen++] = ' ';
11803
11804 for (i = 0; i < 4; i++) {
11805 __be32 v;
11806 if (tg3_nvram_read_be32(tp, offset, &v))
11807 return;
11808
11809 offset += sizeof(v);
11810
11811 if (vlen > TG3_VER_SIZE - sizeof(v)) {
11812 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
11813 break;
11814 }
11815
11816 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
11817 vlen += sizeof(v);
11818 }
11819 }
11820
11821 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
11822 {
11823 int vlen;
11824 u32 apedata;
11825
11826 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
11827 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
11828 return;
11829
11830 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
11831 if (apedata != APE_SEG_SIG_MAGIC)
11832 return;
11833
11834 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
11835 if (!(apedata & APE_FW_STATUS_READY))
11836 return;
11837
11838 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
11839
11840 vlen = strlen(tp->fw_ver);
11841
11842 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
11843 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
11844 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
11845 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
11846 (apedata & APE_FW_VERSION_BLDMSK));
11847 }
11848
11849 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
11850 {
11851 u32 val;
11852
11853 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
11854 tp->fw_ver[0] = 's';
11855 tp->fw_ver[1] = 'b';
11856 tp->fw_ver[2] = '\0';
11857
11858 return;
11859 }
11860
11861 if (tg3_nvram_read(tp, 0, &val))
11862 return;
11863
11864 if (val == TG3_EEPROM_MAGIC)
11865 tg3_read_bc_ver(tp);
11866 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
11867 tg3_read_sb_ver(tp, val);
11868 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
11869 tg3_read_hwsb_ver(tp);
11870 else
11871 return;
11872
11873 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11874 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
11875 return;
11876
11877 tg3_read_mgmtfw_ver(tp);
11878
11879 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
11880 }
11881
11882 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
11883
11884 static int __devinit tg3_get_invariants(struct tg3 *tp)
11885 {
11886 static struct pci_device_id write_reorder_chipsets[] = {
11887 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11888 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
11889 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11890 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
11891 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
11892 PCI_DEVICE_ID_VIA_8385_0) },
11893 { },
11894 };
11895 u32 misc_ctrl_reg;
11896 u32 pci_state_reg, grc_misc_cfg;
11897 u32 val;
11898 u16 pci_cmd;
11899 int err;
11900
11901 /* Force memory write invalidate off. If we leave it on,
11902 * then on 5700_BX chips we have to enable a workaround.
11903 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
11904 * to match the cacheline size. The Broadcom driver have this
11905 * workaround but turns MWI off all the times so never uses
11906 * it. This seems to suggest that the workaround is insufficient.
11907 */
11908 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11909 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
11910 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11911
11912 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
11913 * has the register indirect write enable bit set before
11914 * we try to access any of the MMIO registers. It is also
11915 * critical that the PCI-X hw workaround situation is decided
11916 * before that as well.
11917 */
11918 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11919 &misc_ctrl_reg);
11920
11921 tp->pci_chip_rev_id = (misc_ctrl_reg >>
11922 MISC_HOST_CTRL_CHIPREV_SHIFT);
11923 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
11924 u32 prod_id_asic_rev;
11925
11926 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
11927 &prod_id_asic_rev);
11928 tp->pci_chip_rev_id = prod_id_asic_rev;
11929 }
11930
11931 /* Wrong chip ID in 5752 A0. This code can be removed later
11932 * as A0 is not in production.
11933 */
11934 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
11935 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
11936
11937 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
11938 * we need to disable memory and use config. cycles
11939 * only to access all registers. The 5702/03 chips
11940 * can mistakenly decode the special cycles from the
11941 * ICH chipsets as memory write cycles, causing corruption
11942 * of register and memory space. Only certain ICH bridges
11943 * will drive special cycles with non-zero data during the
11944 * address phase which can fall within the 5703's address
11945 * range. This is not an ICH bug as the PCI spec allows
11946 * non-zero address during special cycles. However, only
11947 * these ICH bridges are known to drive non-zero addresses
11948 * during special cycles.
11949 *
11950 * Since special cycles do not cross PCI bridges, we only
11951 * enable this workaround if the 5703 is on the secondary
11952 * bus of these ICH bridges.
11953 */
11954 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
11955 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
11956 static struct tg3_dev_id {
11957 u32 vendor;
11958 u32 device;
11959 u32 rev;
11960 } ich_chipsets[] = {
11961 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
11962 PCI_ANY_ID },
11963 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
11964 PCI_ANY_ID },
11965 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
11966 0xa },
11967 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
11968 PCI_ANY_ID },
11969 { },
11970 };
11971 struct tg3_dev_id *pci_id = &ich_chipsets[0];
11972 struct pci_dev *bridge = NULL;
11973
11974 while (pci_id->vendor != 0) {
11975 bridge = pci_get_device(pci_id->vendor, pci_id->device,
11976 bridge);
11977 if (!bridge) {
11978 pci_id++;
11979 continue;
11980 }
11981 if (pci_id->rev != PCI_ANY_ID) {
11982 if (bridge->revision > pci_id->rev)
11983 continue;
11984 }
11985 if (bridge->subordinate &&
11986 (bridge->subordinate->number ==
11987 tp->pdev->bus->number)) {
11988
11989 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
11990 pci_dev_put(bridge);
11991 break;
11992 }
11993 }
11994 }
11995
11996 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
11997 static struct tg3_dev_id {
11998 u32 vendor;
11999 u32 device;
12000 } bridge_chipsets[] = {
12001 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12002 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12003 { },
12004 };
12005 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12006 struct pci_dev *bridge = NULL;
12007
12008 while (pci_id->vendor != 0) {
12009 bridge = pci_get_device(pci_id->vendor,
12010 pci_id->device,
12011 bridge);
12012 if (!bridge) {
12013 pci_id++;
12014 continue;
12015 }
12016 if (bridge->subordinate &&
12017 (bridge->subordinate->number <=
12018 tp->pdev->bus->number) &&
12019 (bridge->subordinate->subordinate >=
12020 tp->pdev->bus->number)) {
12021 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12022 pci_dev_put(bridge);
12023 break;
12024 }
12025 }
12026 }
12027
12028 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12029 * DMA addresses > 40-bit. This bridge may have other additional
12030 * 57xx devices behind it in some 4-port NIC designs for example.
12031 * Any tg3 device found behind the bridge will also need the 40-bit
12032 * DMA workaround.
12033 */
12034 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12035 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12036 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
12037 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12038 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
12039 }
12040 else {
12041 struct pci_dev *bridge = NULL;
12042
12043 do {
12044 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12045 PCI_DEVICE_ID_SERVERWORKS_EPB,
12046 bridge);
12047 if (bridge && bridge->subordinate &&
12048 (bridge->subordinate->number <=
12049 tp->pdev->bus->number) &&
12050 (bridge->subordinate->subordinate >=
12051 tp->pdev->bus->number)) {
12052 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12053 pci_dev_put(bridge);
12054 break;
12055 }
12056 } while (bridge);
12057 }
12058
12059 /* Initialize misc host control in PCI block. */
12060 tp->misc_host_ctrl |= (misc_ctrl_reg &
12061 MISC_HOST_CTRL_CHIPREV);
12062 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12063 tp->misc_host_ctrl);
12064
12065 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
12066 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
12067 tp->pdev_peer = tg3_find_peer(tp);
12068
12069 /* Intentionally exclude ASIC_REV_5906 */
12070 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12071 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12072 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12073 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12074 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12075 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12076 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
12077
12078 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12079 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12080 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
12081 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12082 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12083 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
12084
12085 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
12086 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12087 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
12088
12089 /* 5700 B0 chips do not support checksumming correctly due
12090 * to hardware bugs.
12091 */
12092 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
12093 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
12094 else {
12095 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12096 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
12097 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
12098 tp->dev->features |= NETIF_F_IPV6_CSUM;
12099 }
12100
12101 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
12102 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
12103 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
12104 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
12105 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
12106 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
12107 tp->pdev_peer == tp->pdev))
12108 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
12109
12110 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12111 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12112 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
12113 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
12114 } else {
12115 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
12116 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12117 ASIC_REV_5750 &&
12118 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
12119 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
12120 }
12121 }
12122
12123 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12124 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12125 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
12126
12127 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12128 &pci_state_reg);
12129
12130 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
12131 if (tp->pcie_cap != 0) {
12132 u16 lnkctl;
12133
12134 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12135
12136 pcie_set_readrq(tp->pdev, 4096);
12137
12138 pci_read_config_word(tp->pdev,
12139 tp->pcie_cap + PCI_EXP_LNKCTL,
12140 &lnkctl);
12141 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
12142 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12143 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
12144 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12145 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12146 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
12147 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
12148 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
12149 }
12150 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
12151 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12152 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12153 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12154 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
12155 if (!tp->pcix_cap) {
12156 printk(KERN_ERR PFX "Cannot find PCI-X "
12157 "capability, aborting.\n");
12158 return -EIO;
12159 }
12160
12161 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
12162 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
12163 }
12164
12165 /* If we have an AMD 762 or VIA K8T800 chipset, write
12166 * reordering to the mailbox registers done by the host
12167 * controller can cause major troubles. We read back from
12168 * every mailbox register write to force the writes to be
12169 * posted to the chip in order.
12170 */
12171 if (pci_dev_present(write_reorder_chipsets) &&
12172 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12173 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
12174
12175 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
12176 &tp->pci_cacheline_sz);
12177 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12178 &tp->pci_lat_timer);
12179 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12180 tp->pci_lat_timer < 64) {
12181 tp->pci_lat_timer = 64;
12182 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12183 tp->pci_lat_timer);
12184 }
12185
12186 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
12187 /* 5700 BX chips need to have their TX producer index
12188 * mailboxes written twice to workaround a bug.
12189 */
12190 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
12191
12192 /* If we are in PCI-X mode, enable register write workaround.
12193 *
12194 * The workaround is to use indirect register accesses
12195 * for all chip writes not to mailbox registers.
12196 */
12197 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
12198 u32 pm_reg;
12199
12200 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12201
12202 /* The chip can have it's power management PCI config
12203 * space registers clobbered due to this bug.
12204 * So explicitly force the chip into D0 here.
12205 */
12206 pci_read_config_dword(tp->pdev,
12207 tp->pm_cap + PCI_PM_CTRL,
12208 &pm_reg);
12209 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12210 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
12211 pci_write_config_dword(tp->pdev,
12212 tp->pm_cap + PCI_PM_CTRL,
12213 pm_reg);
12214
12215 /* Also, force SERR#/PERR# in PCI command. */
12216 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12217 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12218 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12219 }
12220 }
12221
12222 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12223 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12224 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12225 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12226
12227 /* Chip-specific fixup from Broadcom driver */
12228 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12229 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12230 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12231 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12232 }
12233
12234 /* Default fast path register access methods */
12235 tp->read32 = tg3_read32;
12236 tp->write32 = tg3_write32;
12237 tp->read32_mbox = tg3_read32;
12238 tp->write32_mbox = tg3_write32;
12239 tp->write32_tx_mbox = tg3_write32;
12240 tp->write32_rx_mbox = tg3_write32;
12241
12242 /* Various workaround register access methods */
12243 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12244 tp->write32 = tg3_write_indirect_reg32;
12245 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12246 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12247 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12248 /*
12249 * Back to back register writes can cause problems on these
12250 * chips, the workaround is to read back all reg writes
12251 * except those to mailbox regs.
12252 *
12253 * See tg3_write_indirect_reg32().
12254 */
12255 tp->write32 = tg3_write_flush_reg32;
12256 }
12257
12258
12259 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12260 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12261 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12262 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12263 tp->write32_rx_mbox = tg3_write_flush_reg32;
12264 }
12265
12266 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12267 tp->read32 = tg3_read_indirect_reg32;
12268 tp->write32 = tg3_write_indirect_reg32;
12269 tp->read32_mbox = tg3_read_indirect_mbox;
12270 tp->write32_mbox = tg3_write_indirect_mbox;
12271 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12272 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12273
12274 iounmap(tp->regs);
12275 tp->regs = NULL;
12276
12277 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12278 pci_cmd &= ~PCI_COMMAND_MEMORY;
12279 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12280 }
12281 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12282 tp->read32_mbox = tg3_read32_mbox_5906;
12283 tp->write32_mbox = tg3_write32_mbox_5906;
12284 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12285 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12286 }
12287
12288 if (tp->write32 == tg3_write_indirect_reg32 ||
12289 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12290 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12291 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
12292 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12293
12294 /* Get eeprom hw config before calling tg3_set_power_state().
12295 * In particular, the TG3_FLG2_IS_NIC flag must be
12296 * determined before calling tg3_set_power_state() so that
12297 * we know whether or not to switch out of Vaux power.
12298 * When the flag is set, it means that GPIO1 is used for eeprom
12299 * write protect and also implies that it is a LOM where GPIOs
12300 * are not used to switch power.
12301 */
12302 tg3_get_eeprom_hw_cfg(tp);
12303
12304 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12305 /* Allow reads and writes to the
12306 * APE register and memory space.
12307 */
12308 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12309 PCISTATE_ALLOW_APE_SHMEM_WR;
12310 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12311 pci_state_reg);
12312 }
12313
12314 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12315 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12316 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12317 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12318 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12319
12320 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12321 * GPIO1 driven high will bring 5700's external PHY out of reset.
12322 * It is also used as eeprom write protect on LOMs.
12323 */
12324 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12325 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12326 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12327 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12328 GRC_LCLCTRL_GPIO_OUTPUT1);
12329 /* Unused GPIO3 must be driven as output on 5752 because there
12330 * are no pull-up resistors on unused GPIO pins.
12331 */
12332 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12333 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
12334
12335 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12336 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12337 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12338
12339 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
12340 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
12341 /* Turn off the debug UART. */
12342 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12343 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
12344 /* Keep VMain power. */
12345 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
12346 GRC_LCLCTRL_GPIO_OUTPUT0;
12347 }
12348
12349 /* Force the chip into D0. */
12350 err = tg3_set_power_state(tp, PCI_D0);
12351 if (err) {
12352 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
12353 pci_name(tp->pdev));
12354 return err;
12355 }
12356
12357 /* Derive initial jumbo mode from MTU assigned in
12358 * ether_setup() via the alloc_etherdev() call
12359 */
12360 if (tp->dev->mtu > ETH_DATA_LEN &&
12361 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12362 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
12363
12364 /* Determine WakeOnLan speed to use. */
12365 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12366 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12367 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
12368 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
12369 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
12370 } else {
12371 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
12372 }
12373
12374 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12375 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
12376
12377 /* A few boards don't want Ethernet@WireSpeed phy feature */
12378 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12379 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
12380 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
12381 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
12382 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
12383 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
12384 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
12385
12386 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
12387 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
12388 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
12389 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12390 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12391
12392 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
12393 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
12394 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12395 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780) {
12396 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12397 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12398 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12399 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
12400 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
12401 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
12402 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
12403 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
12404 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
12405 } else
12406 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
12407 }
12408
12409 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12410 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
12411 tp->phy_otp = tg3_read_otp_phycfg(tp);
12412 if (tp->phy_otp == 0)
12413 tp->phy_otp = TG3_OTP_DEFAULT;
12414 }
12415
12416 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
12417 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
12418 else
12419 tp->mi_mode = MAC_MI_MODE_BASE;
12420
12421 tp->coalesce_mode = 0;
12422 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
12423 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
12424 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
12425
12426 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12427 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12428 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
12429
12430 if ((tp->pci_chip_rev_id == CHIPREV_ID_57780_A1 &&
12431 tr32(RCVLPC_STATS_ENABLE) & RCVLPC_STATSENAB_ASF_FIX) ||
12432 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0)
12433 tp->tg3_flags3 |= TG3_FLG3_TOGGLE_10_100_L1PLLPD;
12434
12435 err = tg3_mdio_init(tp);
12436 if (err)
12437 return err;
12438
12439 /* Initialize data/descriptor byte/word swapping. */
12440 val = tr32(GRC_MODE);
12441 val &= GRC_MODE_HOST_STACKUP;
12442 tw32(GRC_MODE, val | tp->grc_mode);
12443
12444 tg3_switch_clocks(tp);
12445
12446 /* Clear this out for sanity. */
12447 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
12448
12449 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12450 &pci_state_reg);
12451 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
12452 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
12453 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
12454
12455 if (chiprevid == CHIPREV_ID_5701_A0 ||
12456 chiprevid == CHIPREV_ID_5701_B0 ||
12457 chiprevid == CHIPREV_ID_5701_B2 ||
12458 chiprevid == CHIPREV_ID_5701_B5) {
12459 void __iomem *sram_base;
12460
12461 /* Write some dummy words into the SRAM status block
12462 * area, see if it reads back correctly. If the return
12463 * value is bad, force enable the PCIX workaround.
12464 */
12465 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
12466
12467 writel(0x00000000, sram_base);
12468 writel(0x00000000, sram_base + 4);
12469 writel(0xffffffff, sram_base + 4);
12470 if (readl(sram_base) != 0x00000000)
12471 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12472 }
12473 }
12474
12475 udelay(50);
12476 tg3_nvram_init(tp);
12477
12478 grc_misc_cfg = tr32(GRC_MISC_CFG);
12479 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
12480
12481 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12482 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
12483 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
12484 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
12485
12486 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
12487 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
12488 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
12489 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
12490 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
12491 HOSTCC_MODE_CLRTICK_TXBD);
12492
12493 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
12494 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12495 tp->misc_host_ctrl);
12496 }
12497
12498 /* Preserve the APE MAC_MODE bits */
12499 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
12500 tp->mac_mode = tr32(MAC_MODE) |
12501 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
12502 else
12503 tp->mac_mode = TG3_DEF_MAC_MODE;
12504
12505 /* these are limited to 10/100 only */
12506 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12507 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
12508 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12509 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12510 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
12511 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
12512 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
12513 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12514 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
12515 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
12516 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
12517 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
12518 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
12519 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
12520
12521 err = tg3_phy_probe(tp);
12522 if (err) {
12523 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
12524 pci_name(tp->pdev), err);
12525 /* ... but do not return immediately ... */
12526 tg3_mdio_fini(tp);
12527 }
12528
12529 tg3_read_partno(tp);
12530 tg3_read_fw_ver(tp);
12531
12532 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
12533 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12534 } else {
12535 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12536 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
12537 else
12538 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12539 }
12540
12541 /* 5700 {AX,BX} chips have a broken status block link
12542 * change bit implementation, so we must use the
12543 * status register in those cases.
12544 */
12545 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12546 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
12547 else
12548 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
12549
12550 /* The led_ctrl is set during tg3_phy_probe, here we might
12551 * have to force the link status polling mechanism based
12552 * upon subsystem IDs.
12553 */
12554 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
12555 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12556 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
12557 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
12558 TG3_FLAG_USE_LINKCHG_REG);
12559 }
12560
12561 /* For all SERDES we poll the MAC status register. */
12562 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
12563 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
12564 else
12565 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
12566
12567 tp->rx_offset = NET_IP_ALIGN;
12568 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12569 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
12570 tp->rx_offset = 0;
12571
12572 tp->rx_std_max_post = TG3_RX_RING_SIZE;
12573
12574 /* Increment the rx prod index on the rx std ring by at most
12575 * 8 for these chips to workaround hw errata.
12576 */
12577 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12578 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12579 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12580 tp->rx_std_max_post = 8;
12581
12582 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
12583 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
12584 PCIE_PWR_MGMT_L1_THRESH_MSK;
12585
12586 return err;
12587 }
12588
12589 #ifdef CONFIG_SPARC
12590 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
12591 {
12592 struct net_device *dev = tp->dev;
12593 struct pci_dev *pdev = tp->pdev;
12594 struct device_node *dp = pci_device_to_OF_node(pdev);
12595 const unsigned char *addr;
12596 int len;
12597
12598 addr = of_get_property(dp, "local-mac-address", &len);
12599 if (addr && len == 6) {
12600 memcpy(dev->dev_addr, addr, 6);
12601 memcpy(dev->perm_addr, dev->dev_addr, 6);
12602 return 0;
12603 }
12604 return -ENODEV;
12605 }
12606
12607 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
12608 {
12609 struct net_device *dev = tp->dev;
12610
12611 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
12612 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
12613 return 0;
12614 }
12615 #endif
12616
12617 static int __devinit tg3_get_device_address(struct tg3 *tp)
12618 {
12619 struct net_device *dev = tp->dev;
12620 u32 hi, lo, mac_offset;
12621 int addr_ok = 0;
12622
12623 #ifdef CONFIG_SPARC
12624 if (!tg3_get_macaddr_sparc(tp))
12625 return 0;
12626 #endif
12627
12628 mac_offset = 0x7c;
12629 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
12630 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12631 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
12632 mac_offset = 0xcc;
12633 if (tg3_nvram_lock(tp))
12634 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
12635 else
12636 tg3_nvram_unlock(tp);
12637 }
12638 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12639 mac_offset = 0x10;
12640
12641 /* First try to get it from MAC address mailbox. */
12642 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
12643 if ((hi >> 16) == 0x484b) {
12644 dev->dev_addr[0] = (hi >> 8) & 0xff;
12645 dev->dev_addr[1] = (hi >> 0) & 0xff;
12646
12647 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
12648 dev->dev_addr[2] = (lo >> 24) & 0xff;
12649 dev->dev_addr[3] = (lo >> 16) & 0xff;
12650 dev->dev_addr[4] = (lo >> 8) & 0xff;
12651 dev->dev_addr[5] = (lo >> 0) & 0xff;
12652
12653 /* Some old bootcode may report a 0 MAC address in SRAM */
12654 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
12655 }
12656 if (!addr_ok) {
12657 /* Next, try NVRAM. */
12658 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
12659 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
12660 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
12661 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
12662 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
12663 }
12664 /* Finally just fetch it out of the MAC control regs. */
12665 else {
12666 hi = tr32(MAC_ADDR_0_HIGH);
12667 lo = tr32(MAC_ADDR_0_LOW);
12668
12669 dev->dev_addr[5] = lo & 0xff;
12670 dev->dev_addr[4] = (lo >> 8) & 0xff;
12671 dev->dev_addr[3] = (lo >> 16) & 0xff;
12672 dev->dev_addr[2] = (lo >> 24) & 0xff;
12673 dev->dev_addr[1] = hi & 0xff;
12674 dev->dev_addr[0] = (hi >> 8) & 0xff;
12675 }
12676 }
12677
12678 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
12679 #ifdef CONFIG_SPARC
12680 if (!tg3_get_default_macaddr_sparc(tp))
12681 return 0;
12682 #endif
12683 return -EINVAL;
12684 }
12685 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
12686 return 0;
12687 }
12688
12689 #define BOUNDARY_SINGLE_CACHELINE 1
12690 #define BOUNDARY_MULTI_CACHELINE 2
12691
12692 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
12693 {
12694 int cacheline_size;
12695 u8 byte;
12696 int goal;
12697
12698 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
12699 if (byte == 0)
12700 cacheline_size = 1024;
12701 else
12702 cacheline_size = (int) byte * 4;
12703
12704 /* On 5703 and later chips, the boundary bits have no
12705 * effect.
12706 */
12707 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12708 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12709 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12710 goto out;
12711
12712 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
12713 goal = BOUNDARY_MULTI_CACHELINE;
12714 #else
12715 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
12716 goal = BOUNDARY_SINGLE_CACHELINE;
12717 #else
12718 goal = 0;
12719 #endif
12720 #endif
12721
12722 if (!goal)
12723 goto out;
12724
12725 /* PCI controllers on most RISC systems tend to disconnect
12726 * when a device tries to burst across a cache-line boundary.
12727 * Therefore, letting tg3 do so just wastes PCI bandwidth.
12728 *
12729 * Unfortunately, for PCI-E there are only limited
12730 * write-side controls for this, and thus for reads
12731 * we will still get the disconnects. We'll also waste
12732 * these PCI cycles for both read and write for chips
12733 * other than 5700 and 5701 which do not implement the
12734 * boundary bits.
12735 */
12736 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12737 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
12738 switch (cacheline_size) {
12739 case 16:
12740 case 32:
12741 case 64:
12742 case 128:
12743 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12744 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
12745 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
12746 } else {
12747 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12748 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12749 }
12750 break;
12751
12752 case 256:
12753 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
12754 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
12755 break;
12756
12757 default:
12758 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12759 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12760 break;
12761 }
12762 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12763 switch (cacheline_size) {
12764 case 16:
12765 case 32:
12766 case 64:
12767 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12768 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12769 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
12770 break;
12771 }
12772 /* fallthrough */
12773 case 128:
12774 default:
12775 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12776 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
12777 break;
12778 }
12779 } else {
12780 switch (cacheline_size) {
12781 case 16:
12782 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12783 val |= (DMA_RWCTRL_READ_BNDRY_16 |
12784 DMA_RWCTRL_WRITE_BNDRY_16);
12785 break;
12786 }
12787 /* fallthrough */
12788 case 32:
12789 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12790 val |= (DMA_RWCTRL_READ_BNDRY_32 |
12791 DMA_RWCTRL_WRITE_BNDRY_32);
12792 break;
12793 }
12794 /* fallthrough */
12795 case 64:
12796 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12797 val |= (DMA_RWCTRL_READ_BNDRY_64 |
12798 DMA_RWCTRL_WRITE_BNDRY_64);
12799 break;
12800 }
12801 /* fallthrough */
12802 case 128:
12803 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12804 val |= (DMA_RWCTRL_READ_BNDRY_128 |
12805 DMA_RWCTRL_WRITE_BNDRY_128);
12806 break;
12807 }
12808 /* fallthrough */
12809 case 256:
12810 val |= (DMA_RWCTRL_READ_BNDRY_256 |
12811 DMA_RWCTRL_WRITE_BNDRY_256);
12812 break;
12813 case 512:
12814 val |= (DMA_RWCTRL_READ_BNDRY_512 |
12815 DMA_RWCTRL_WRITE_BNDRY_512);
12816 break;
12817 case 1024:
12818 default:
12819 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
12820 DMA_RWCTRL_WRITE_BNDRY_1024);
12821 break;
12822 }
12823 }
12824
12825 out:
12826 return val;
12827 }
12828
12829 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
12830 {
12831 struct tg3_internal_buffer_desc test_desc;
12832 u32 sram_dma_descs;
12833 int i, ret;
12834
12835 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
12836
12837 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
12838 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
12839 tw32(RDMAC_STATUS, 0);
12840 tw32(WDMAC_STATUS, 0);
12841
12842 tw32(BUFMGR_MODE, 0);
12843 tw32(FTQ_RESET, 0);
12844
12845 test_desc.addr_hi = ((u64) buf_dma) >> 32;
12846 test_desc.addr_lo = buf_dma & 0xffffffff;
12847 test_desc.nic_mbuf = 0x00002100;
12848 test_desc.len = size;
12849
12850 /*
12851 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
12852 * the *second* time the tg3 driver was getting loaded after an
12853 * initial scan.
12854 *
12855 * Broadcom tells me:
12856 * ...the DMA engine is connected to the GRC block and a DMA
12857 * reset may affect the GRC block in some unpredictable way...
12858 * The behavior of resets to individual blocks has not been tested.
12859 *
12860 * Broadcom noted the GRC reset will also reset all sub-components.
12861 */
12862 if (to_device) {
12863 test_desc.cqid_sqid = (13 << 8) | 2;
12864
12865 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
12866 udelay(40);
12867 } else {
12868 test_desc.cqid_sqid = (16 << 8) | 7;
12869
12870 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
12871 udelay(40);
12872 }
12873 test_desc.flags = 0x00000005;
12874
12875 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
12876 u32 val;
12877
12878 val = *(((u32 *)&test_desc) + i);
12879 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
12880 sram_dma_descs + (i * sizeof(u32)));
12881 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
12882 }
12883 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
12884
12885 if (to_device) {
12886 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
12887 } else {
12888 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
12889 }
12890
12891 ret = -ENODEV;
12892 for (i = 0; i < 40; i++) {
12893 u32 val;
12894
12895 if (to_device)
12896 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
12897 else
12898 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
12899 if ((val & 0xffff) == sram_dma_descs) {
12900 ret = 0;
12901 break;
12902 }
12903
12904 udelay(100);
12905 }
12906
12907 return ret;
12908 }
12909
12910 #define TEST_BUFFER_SIZE 0x2000
12911
12912 static int __devinit tg3_test_dma(struct tg3 *tp)
12913 {
12914 dma_addr_t buf_dma;
12915 u32 *buf, saved_dma_rwctrl;
12916 int ret;
12917
12918 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
12919 if (!buf) {
12920 ret = -ENOMEM;
12921 goto out_nofree;
12922 }
12923
12924 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
12925 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
12926
12927 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
12928
12929 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12930 /* DMA read watermark not used on PCIE */
12931 tp->dma_rwctrl |= 0x00180000;
12932 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
12933 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
12934 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
12935 tp->dma_rwctrl |= 0x003f0000;
12936 else
12937 tp->dma_rwctrl |= 0x003f000f;
12938 } else {
12939 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12940 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
12941 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
12942 u32 read_water = 0x7;
12943
12944 /* If the 5704 is behind the EPB bridge, we can
12945 * do the less restrictive ONE_DMA workaround for
12946 * better performance.
12947 */
12948 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
12949 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12950 tp->dma_rwctrl |= 0x8000;
12951 else if (ccval == 0x6 || ccval == 0x7)
12952 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
12953
12954 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
12955 read_water = 4;
12956 /* Set bit 23 to enable PCIX hw bug fix */
12957 tp->dma_rwctrl |=
12958 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
12959 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
12960 (1 << 23);
12961 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
12962 /* 5780 always in PCIX mode */
12963 tp->dma_rwctrl |= 0x00144000;
12964 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12965 /* 5714 always in PCIX mode */
12966 tp->dma_rwctrl |= 0x00148000;
12967 } else {
12968 tp->dma_rwctrl |= 0x001b000f;
12969 }
12970 }
12971
12972 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12973 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12974 tp->dma_rwctrl &= 0xfffffff0;
12975
12976 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12977 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
12978 /* Remove this if it causes problems for some boards. */
12979 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
12980
12981 /* On 5700/5701 chips, we need to set this bit.
12982 * Otherwise the chip will issue cacheline transactions
12983 * to streamable DMA memory with not all the byte
12984 * enables turned on. This is an error on several
12985 * RISC PCI controllers, in particular sparc64.
12986 *
12987 * On 5703/5704 chips, this bit has been reassigned
12988 * a different meaning. In particular, it is used
12989 * on those chips to enable a PCI-X workaround.
12990 */
12991 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
12992 }
12993
12994 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12995
12996 #if 0
12997 /* Unneeded, already done by tg3_get_invariants. */
12998 tg3_switch_clocks(tp);
12999 #endif
13000
13001 ret = 0;
13002 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13003 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
13004 goto out;
13005
13006 /* It is best to perform DMA test with maximum write burst size
13007 * to expose the 5700/5701 write DMA bug.
13008 */
13009 saved_dma_rwctrl = tp->dma_rwctrl;
13010 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13011 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13012
13013 while (1) {
13014 u32 *p = buf, i;
13015
13016 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
13017 p[i] = i;
13018
13019 /* Send the buffer to the chip. */
13020 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
13021 if (ret) {
13022 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
13023 break;
13024 }
13025
13026 #if 0
13027 /* validate data reached card RAM correctly. */
13028 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13029 u32 val;
13030 tg3_read_mem(tp, 0x2100 + (i*4), &val);
13031 if (le32_to_cpu(val) != p[i]) {
13032 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
13033 /* ret = -ENODEV here? */
13034 }
13035 p[i] = 0;
13036 }
13037 #endif
13038 /* Now read it back. */
13039 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
13040 if (ret) {
13041 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
13042
13043 break;
13044 }
13045
13046 /* Verify it. */
13047 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13048 if (p[i] == i)
13049 continue;
13050
13051 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13052 DMA_RWCTRL_WRITE_BNDRY_16) {
13053 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13054 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13055 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13056 break;
13057 } else {
13058 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
13059 ret = -ENODEV;
13060 goto out;
13061 }
13062 }
13063
13064 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
13065 /* Success. */
13066 ret = 0;
13067 break;
13068 }
13069 }
13070 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13071 DMA_RWCTRL_WRITE_BNDRY_16) {
13072 static struct pci_device_id dma_wait_state_chipsets[] = {
13073 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
13074 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
13075 { },
13076 };
13077
13078 /* DMA test passed without adjusting DMA boundary,
13079 * now look for chipsets that are known to expose the
13080 * DMA bug without failing the test.
13081 */
13082 if (pci_dev_present(dma_wait_state_chipsets)) {
13083 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13084 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13085 }
13086 else
13087 /* Safe to use the calculated DMA boundary. */
13088 tp->dma_rwctrl = saved_dma_rwctrl;
13089
13090 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13091 }
13092
13093 out:
13094 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
13095 out_nofree:
13096 return ret;
13097 }
13098
13099 static void __devinit tg3_init_link_config(struct tg3 *tp)
13100 {
13101 tp->link_config.advertising =
13102 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
13103 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
13104 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
13105 ADVERTISED_Autoneg | ADVERTISED_MII);
13106 tp->link_config.speed = SPEED_INVALID;
13107 tp->link_config.duplex = DUPLEX_INVALID;
13108 tp->link_config.autoneg = AUTONEG_ENABLE;
13109 tp->link_config.active_speed = SPEED_INVALID;
13110 tp->link_config.active_duplex = DUPLEX_INVALID;
13111 tp->link_config.phy_is_low_power = 0;
13112 tp->link_config.orig_speed = SPEED_INVALID;
13113 tp->link_config.orig_duplex = DUPLEX_INVALID;
13114 tp->link_config.orig_autoneg = AUTONEG_INVALID;
13115 }
13116
13117 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
13118 {
13119 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13120 tp->bufmgr_config.mbuf_read_dma_low_water =
13121 DEFAULT_MB_RDMA_LOW_WATER_5705;
13122 tp->bufmgr_config.mbuf_mac_rx_low_water =
13123 DEFAULT_MB_MACRX_LOW_WATER_5705;
13124 tp->bufmgr_config.mbuf_high_water =
13125 DEFAULT_MB_HIGH_WATER_5705;
13126 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13127 tp->bufmgr_config.mbuf_mac_rx_low_water =
13128 DEFAULT_MB_MACRX_LOW_WATER_5906;
13129 tp->bufmgr_config.mbuf_high_water =
13130 DEFAULT_MB_HIGH_WATER_5906;
13131 }
13132
13133 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13134 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
13135 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13136 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
13137 tp->bufmgr_config.mbuf_high_water_jumbo =
13138 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
13139 } else {
13140 tp->bufmgr_config.mbuf_read_dma_low_water =
13141 DEFAULT_MB_RDMA_LOW_WATER;
13142 tp->bufmgr_config.mbuf_mac_rx_low_water =
13143 DEFAULT_MB_MACRX_LOW_WATER;
13144 tp->bufmgr_config.mbuf_high_water =
13145 DEFAULT_MB_HIGH_WATER;
13146
13147 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13148 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
13149 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13150 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
13151 tp->bufmgr_config.mbuf_high_water_jumbo =
13152 DEFAULT_MB_HIGH_WATER_JUMBO;
13153 }
13154
13155 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
13156 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
13157 }
13158
13159 static char * __devinit tg3_phy_string(struct tg3 *tp)
13160 {
13161 switch (tp->phy_id & PHY_ID_MASK) {
13162 case PHY_ID_BCM5400: return "5400";
13163 case PHY_ID_BCM5401: return "5401";
13164 case PHY_ID_BCM5411: return "5411";
13165 case PHY_ID_BCM5701: return "5701";
13166 case PHY_ID_BCM5703: return "5703";
13167 case PHY_ID_BCM5704: return "5704";
13168 case PHY_ID_BCM5705: return "5705";
13169 case PHY_ID_BCM5750: return "5750";
13170 case PHY_ID_BCM5752: return "5752";
13171 case PHY_ID_BCM5714: return "5714";
13172 case PHY_ID_BCM5780: return "5780";
13173 case PHY_ID_BCM5755: return "5755";
13174 case PHY_ID_BCM5787: return "5787";
13175 case PHY_ID_BCM5784: return "5784";
13176 case PHY_ID_BCM5756: return "5722/5756";
13177 case PHY_ID_BCM5906: return "5906";
13178 case PHY_ID_BCM5761: return "5761";
13179 case PHY_ID_BCM8002: return "8002/serdes";
13180 case 0: return "serdes";
13181 default: return "unknown";
13182 }
13183 }
13184
13185 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
13186 {
13187 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13188 strcpy(str, "PCI Express");
13189 return str;
13190 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13191 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
13192
13193 strcpy(str, "PCIX:");
13194
13195 if ((clock_ctrl == 7) ||
13196 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
13197 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
13198 strcat(str, "133MHz");
13199 else if (clock_ctrl == 0)
13200 strcat(str, "33MHz");
13201 else if (clock_ctrl == 2)
13202 strcat(str, "50MHz");
13203 else if (clock_ctrl == 4)
13204 strcat(str, "66MHz");
13205 else if (clock_ctrl == 6)
13206 strcat(str, "100MHz");
13207 } else {
13208 strcpy(str, "PCI:");
13209 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
13210 strcat(str, "66MHz");
13211 else
13212 strcat(str, "33MHz");
13213 }
13214 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13215 strcat(str, ":32-bit");
13216 else
13217 strcat(str, ":64-bit");
13218 return str;
13219 }
13220
13221 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
13222 {
13223 struct pci_dev *peer;
13224 unsigned int func, devnr = tp->pdev->devfn & ~7;
13225
13226 for (func = 0; func < 8; func++) {
13227 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13228 if (peer && peer != tp->pdev)
13229 break;
13230 pci_dev_put(peer);
13231 }
13232 /* 5704 can be configured in single-port mode, set peer to
13233 * tp->pdev in that case.
13234 */
13235 if (!peer) {
13236 peer = tp->pdev;
13237 return peer;
13238 }
13239
13240 /*
13241 * We don't need to keep the refcount elevated; there's no way
13242 * to remove one half of this device without removing the other
13243 */
13244 pci_dev_put(peer);
13245
13246 return peer;
13247 }
13248
13249 static void __devinit tg3_init_coal(struct tg3 *tp)
13250 {
13251 struct ethtool_coalesce *ec = &tp->coal;
13252
13253 memset(ec, 0, sizeof(*ec));
13254 ec->cmd = ETHTOOL_GCOALESCE;
13255 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13256 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13257 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13258 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13259 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13260 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13261 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13262 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13263 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13264
13265 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13266 HOSTCC_MODE_CLRTICK_TXBD)) {
13267 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13268 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13269 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13270 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13271 }
13272
13273 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13274 ec->rx_coalesce_usecs_irq = 0;
13275 ec->tx_coalesce_usecs_irq = 0;
13276 ec->stats_block_coalesce_usecs = 0;
13277 }
13278 }
13279
13280 static const struct net_device_ops tg3_netdev_ops = {
13281 .ndo_open = tg3_open,
13282 .ndo_stop = tg3_close,
13283 .ndo_start_xmit = tg3_start_xmit,
13284 .ndo_get_stats = tg3_get_stats,
13285 .ndo_validate_addr = eth_validate_addr,
13286 .ndo_set_multicast_list = tg3_set_rx_mode,
13287 .ndo_set_mac_address = tg3_set_mac_addr,
13288 .ndo_do_ioctl = tg3_ioctl,
13289 .ndo_tx_timeout = tg3_tx_timeout,
13290 .ndo_change_mtu = tg3_change_mtu,
13291 #if TG3_VLAN_TAG_USED
13292 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13293 #endif
13294 #ifdef CONFIG_NET_POLL_CONTROLLER
13295 .ndo_poll_controller = tg3_poll_controller,
13296 #endif
13297 };
13298
13299 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
13300 .ndo_open = tg3_open,
13301 .ndo_stop = tg3_close,
13302 .ndo_start_xmit = tg3_start_xmit_dma_bug,
13303 .ndo_get_stats = tg3_get_stats,
13304 .ndo_validate_addr = eth_validate_addr,
13305 .ndo_set_multicast_list = tg3_set_rx_mode,
13306 .ndo_set_mac_address = tg3_set_mac_addr,
13307 .ndo_do_ioctl = tg3_ioctl,
13308 .ndo_tx_timeout = tg3_tx_timeout,
13309 .ndo_change_mtu = tg3_change_mtu,
13310 #if TG3_VLAN_TAG_USED
13311 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13312 #endif
13313 #ifdef CONFIG_NET_POLL_CONTROLLER
13314 .ndo_poll_controller = tg3_poll_controller,
13315 #endif
13316 };
13317
13318 static int __devinit tg3_init_one(struct pci_dev *pdev,
13319 const struct pci_device_id *ent)
13320 {
13321 static int tg3_version_printed = 0;
13322 struct net_device *dev;
13323 struct tg3 *tp;
13324 int err, pm_cap;
13325 char str[40];
13326 u64 dma_mask, persist_dma_mask;
13327
13328 if (tg3_version_printed++ == 0)
13329 printk(KERN_INFO "%s", version);
13330
13331 err = pci_enable_device(pdev);
13332 if (err) {
13333 printk(KERN_ERR PFX "Cannot enable PCI device, "
13334 "aborting.\n");
13335 return err;
13336 }
13337
13338 err = pci_request_regions(pdev, DRV_MODULE_NAME);
13339 if (err) {
13340 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
13341 "aborting.\n");
13342 goto err_out_disable_pdev;
13343 }
13344
13345 pci_set_master(pdev);
13346
13347 /* Find power-management capability. */
13348 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
13349 if (pm_cap == 0) {
13350 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
13351 "aborting.\n");
13352 err = -EIO;
13353 goto err_out_free_res;
13354 }
13355
13356 dev = alloc_etherdev(sizeof(*tp));
13357 if (!dev) {
13358 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
13359 err = -ENOMEM;
13360 goto err_out_free_res;
13361 }
13362
13363 SET_NETDEV_DEV(dev, &pdev->dev);
13364
13365 #if TG3_VLAN_TAG_USED
13366 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
13367 #endif
13368
13369 tp = netdev_priv(dev);
13370 tp->pdev = pdev;
13371 tp->dev = dev;
13372 tp->pm_cap = pm_cap;
13373 tp->rx_mode = TG3_DEF_RX_MODE;
13374 tp->tx_mode = TG3_DEF_TX_MODE;
13375
13376 if (tg3_debug > 0)
13377 tp->msg_enable = tg3_debug;
13378 else
13379 tp->msg_enable = TG3_DEF_MSG_ENABLE;
13380
13381 /* The word/byte swap controls here control register access byte
13382 * swapping. DMA data byte swapping is controlled in the GRC_MODE
13383 * setting below.
13384 */
13385 tp->misc_host_ctrl =
13386 MISC_HOST_CTRL_MASK_PCI_INT |
13387 MISC_HOST_CTRL_WORD_SWAP |
13388 MISC_HOST_CTRL_INDIR_ACCESS |
13389 MISC_HOST_CTRL_PCISTATE_RW;
13390
13391 /* The NONFRM (non-frame) byte/word swap controls take effect
13392 * on descriptor entries, anything which isn't packet data.
13393 *
13394 * The StrongARM chips on the board (one for tx, one for rx)
13395 * are running in big-endian mode.
13396 */
13397 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
13398 GRC_MODE_WSWAP_NONFRM_DATA);
13399 #ifdef __BIG_ENDIAN
13400 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
13401 #endif
13402 spin_lock_init(&tp->lock);
13403 spin_lock_init(&tp->indirect_lock);
13404 INIT_WORK(&tp->reset_task, tg3_reset_task);
13405
13406 tp->regs = pci_ioremap_bar(pdev, BAR_0);
13407 if (!tp->regs) {
13408 printk(KERN_ERR PFX "Cannot map device registers, "
13409 "aborting.\n");
13410 err = -ENOMEM;
13411 goto err_out_free_dev;
13412 }
13413
13414 tg3_init_link_config(tp);
13415
13416 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
13417 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
13418 tp->tx_pending = TG3_DEF_TX_RING_PENDING;
13419
13420 tp->napi[0].tp = tp;
13421 tp->napi[0].int_mbox = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
13422 tp->napi[0].consmbox = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
13423 netif_napi_add(dev, &tp->napi[0].napi, tg3_poll, 64);
13424 dev->ethtool_ops = &tg3_ethtool_ops;
13425 dev->watchdog_timeo = TG3_TX_TIMEOUT;
13426 dev->irq = pdev->irq;
13427
13428 err = tg3_get_invariants(tp);
13429 if (err) {
13430 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
13431 "aborting.\n");
13432 goto err_out_iounmap;
13433 }
13434
13435 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13436 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13437 dev->netdev_ops = &tg3_netdev_ops;
13438 else
13439 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
13440
13441
13442 /* The EPB bridge inside 5714, 5715, and 5780 and any
13443 * device behind the EPB cannot support DMA addresses > 40-bit.
13444 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
13445 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
13446 * do DMA address check in tg3_start_xmit().
13447 */
13448 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
13449 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
13450 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
13451 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
13452 #ifdef CONFIG_HIGHMEM
13453 dma_mask = DMA_BIT_MASK(64);
13454 #endif
13455 } else
13456 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
13457
13458 /* Configure DMA attributes. */
13459 if (dma_mask > DMA_BIT_MASK(32)) {
13460 err = pci_set_dma_mask(pdev, dma_mask);
13461 if (!err) {
13462 dev->features |= NETIF_F_HIGHDMA;
13463 err = pci_set_consistent_dma_mask(pdev,
13464 persist_dma_mask);
13465 if (err < 0) {
13466 printk(KERN_ERR PFX "Unable to obtain 64 bit "
13467 "DMA for consistent allocations\n");
13468 goto err_out_iounmap;
13469 }
13470 }
13471 }
13472 if (err || dma_mask == DMA_BIT_MASK(32)) {
13473 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
13474 if (err) {
13475 printk(KERN_ERR PFX "No usable DMA configuration, "
13476 "aborting.\n");
13477 goto err_out_iounmap;
13478 }
13479 }
13480
13481 tg3_init_bufmgr_config(tp);
13482
13483 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
13484 tp->fw_needed = FIRMWARE_TG3;
13485
13486 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13487 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
13488 }
13489 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13490 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13491 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
13492 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13493 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
13494 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
13495 } else {
13496 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
13497 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13498 tp->fw_needed = FIRMWARE_TG3TSO5;
13499 else
13500 tp->fw_needed = FIRMWARE_TG3TSO;
13501 }
13502
13503 /* TSO is on by default on chips that support hardware TSO.
13504 * Firmware TSO on older chips gives lower performance, so it
13505 * is off by default, but can be enabled using ethtool.
13506 */
13507 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13508 if (dev->features & NETIF_F_IP_CSUM)
13509 dev->features |= NETIF_F_TSO;
13510 if ((dev->features & NETIF_F_IPV6_CSUM) &&
13511 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2))
13512 dev->features |= NETIF_F_TSO6;
13513 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13514 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13515 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
13516 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13517 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13518 dev->features |= NETIF_F_TSO_ECN;
13519 }
13520
13521
13522 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
13523 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
13524 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
13525 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
13526 tp->rx_pending = 63;
13527 }
13528
13529 err = tg3_get_device_address(tp);
13530 if (err) {
13531 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
13532 "aborting.\n");
13533 goto err_out_fw;
13534 }
13535
13536 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13537 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
13538 if (!tp->aperegs) {
13539 printk(KERN_ERR PFX "Cannot map APE registers, "
13540 "aborting.\n");
13541 err = -ENOMEM;
13542 goto err_out_fw;
13543 }
13544
13545 tg3_ape_lock_init(tp);
13546
13547 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
13548 tg3_read_dash_ver(tp);
13549 }
13550
13551 /*
13552 * Reset chip in case UNDI or EFI driver did not shutdown
13553 * DMA self test will enable WDMAC and we'll see (spurious)
13554 * pending DMA on the PCI bus at that point.
13555 */
13556 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
13557 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
13558 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
13559 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13560 }
13561
13562 err = tg3_test_dma(tp);
13563 if (err) {
13564 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
13565 goto err_out_apeunmap;
13566 }
13567
13568 /* flow control autonegotiation is default behavior */
13569 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
13570 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
13571
13572 tg3_init_coal(tp);
13573
13574 pci_set_drvdata(pdev, dev);
13575
13576 err = register_netdev(dev);
13577 if (err) {
13578 printk(KERN_ERR PFX "Cannot register net device, "
13579 "aborting.\n");
13580 goto err_out_apeunmap;
13581 }
13582
13583 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
13584 dev->name,
13585 tp->board_part_number,
13586 tp->pci_chip_rev_id,
13587 tg3_bus_string(tp, str),
13588 dev->dev_addr);
13589
13590 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
13591 printk(KERN_INFO
13592 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
13593 tp->dev->name,
13594 tp->mdio_bus->phy_map[PHY_ADDR]->drv->name,
13595 dev_name(&tp->mdio_bus->phy_map[PHY_ADDR]->dev));
13596 else
13597 printk(KERN_INFO
13598 "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
13599 tp->dev->name, tg3_phy_string(tp),
13600 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
13601 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
13602 "10/100/1000Base-T")),
13603 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
13604
13605 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
13606 dev->name,
13607 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
13608 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
13609 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
13610 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
13611 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
13612 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
13613 dev->name, tp->dma_rwctrl,
13614 (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
13615 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
13616
13617 return 0;
13618
13619 err_out_apeunmap:
13620 if (tp->aperegs) {
13621 iounmap(tp->aperegs);
13622 tp->aperegs = NULL;
13623 }
13624
13625 err_out_fw:
13626 if (tp->fw)
13627 release_firmware(tp->fw);
13628
13629 err_out_iounmap:
13630 if (tp->regs) {
13631 iounmap(tp->regs);
13632 tp->regs = NULL;
13633 }
13634
13635 err_out_free_dev:
13636 free_netdev(dev);
13637
13638 err_out_free_res:
13639 pci_release_regions(pdev);
13640
13641 err_out_disable_pdev:
13642 pci_disable_device(pdev);
13643 pci_set_drvdata(pdev, NULL);
13644 return err;
13645 }
13646
13647 static void __devexit tg3_remove_one(struct pci_dev *pdev)
13648 {
13649 struct net_device *dev = pci_get_drvdata(pdev);
13650
13651 if (dev) {
13652 struct tg3 *tp = netdev_priv(dev);
13653
13654 if (tp->fw)
13655 release_firmware(tp->fw);
13656
13657 flush_scheduled_work();
13658
13659 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
13660 tg3_phy_fini(tp);
13661 tg3_mdio_fini(tp);
13662 }
13663
13664 unregister_netdev(dev);
13665 if (tp->aperegs) {
13666 iounmap(tp->aperegs);
13667 tp->aperegs = NULL;
13668 }
13669 if (tp->regs) {
13670 iounmap(tp->regs);
13671 tp->regs = NULL;
13672 }
13673 free_netdev(dev);
13674 pci_release_regions(pdev);
13675 pci_disable_device(pdev);
13676 pci_set_drvdata(pdev, NULL);
13677 }
13678 }
13679
13680 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
13681 {
13682 struct net_device *dev = pci_get_drvdata(pdev);
13683 struct tg3 *tp = netdev_priv(dev);
13684 pci_power_t target_state;
13685 int err;
13686
13687 /* PCI register 4 needs to be saved whether netif_running() or not.
13688 * MSI address and data need to be saved if using MSI and
13689 * netif_running().
13690 */
13691 pci_save_state(pdev);
13692
13693 if (!netif_running(dev))
13694 return 0;
13695
13696 flush_scheduled_work();
13697 tg3_phy_stop(tp);
13698 tg3_netif_stop(tp);
13699
13700 del_timer_sync(&tp->timer);
13701
13702 tg3_full_lock(tp, 1);
13703 tg3_disable_ints(tp);
13704 tg3_full_unlock(tp);
13705
13706 netif_device_detach(dev);
13707
13708 tg3_full_lock(tp, 0);
13709 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13710 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
13711 tg3_full_unlock(tp);
13712
13713 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
13714
13715 err = tg3_set_power_state(tp, target_state);
13716 if (err) {
13717 int err2;
13718
13719 tg3_full_lock(tp, 0);
13720
13721 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
13722 err2 = tg3_restart_hw(tp, 1);
13723 if (err2)
13724 goto out;
13725
13726 tp->timer.expires = jiffies + tp->timer_offset;
13727 add_timer(&tp->timer);
13728
13729 netif_device_attach(dev);
13730 tg3_netif_start(tp);
13731
13732 out:
13733 tg3_full_unlock(tp);
13734
13735 if (!err2)
13736 tg3_phy_start(tp);
13737 }
13738
13739 return err;
13740 }
13741
13742 static int tg3_resume(struct pci_dev *pdev)
13743 {
13744 struct net_device *dev = pci_get_drvdata(pdev);
13745 struct tg3 *tp = netdev_priv(dev);
13746 int err;
13747
13748 pci_restore_state(tp->pdev);
13749
13750 if (!netif_running(dev))
13751 return 0;
13752
13753 err = tg3_set_power_state(tp, PCI_D0);
13754 if (err)
13755 return err;
13756
13757 netif_device_attach(dev);
13758
13759 tg3_full_lock(tp, 0);
13760
13761 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
13762 err = tg3_restart_hw(tp, 1);
13763 if (err)
13764 goto out;
13765
13766 tp->timer.expires = jiffies + tp->timer_offset;
13767 add_timer(&tp->timer);
13768
13769 tg3_netif_start(tp);
13770
13771 out:
13772 tg3_full_unlock(tp);
13773
13774 if (!err)
13775 tg3_phy_start(tp);
13776
13777 return err;
13778 }
13779
13780 static struct pci_driver tg3_driver = {
13781 .name = DRV_MODULE_NAME,
13782 .id_table = tg3_pci_tbl,
13783 .probe = tg3_init_one,
13784 .remove = __devexit_p(tg3_remove_one),
13785 .suspend = tg3_suspend,
13786 .resume = tg3_resume
13787 };
13788
13789 static int __init tg3_init(void)
13790 {
13791 return pci_register_driver(&tg3_driver);
13792 }
13793
13794 static void __exit tg3_cleanup(void)
13795 {
13796 pci_unregister_driver(&tg3_driver);
13797 }
13798
13799 module_init(tg3_init);
13800 module_exit(tg3_cleanup);
Linux kernel - Deliverables
This page took 0.303347 seconds and 4 git commands to generate.