2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2010 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
28 #include <linux/init.h>
29 #include <linux/ioport.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/ethtool.h>
35 #include <linux/mii.h>
36 #include <linux/phy.h>
37 #include <linux/brcmphy.h>
38 #include <linux/if_vlan.h>
40 #include <linux/tcp.h>
41 #include <linux/workqueue.h>
42 #include <linux/prefetch.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/firmware.h>
46 #include <net/checksum.h>
49 #include <asm/system.h>
51 #include <asm/byteorder.h>
52 #include <asm/uaccess.h>
55 #include <asm/idprom.h>
62 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
63 #define TG3_VLAN_TAG_USED 1
65 #define TG3_VLAN_TAG_USED 0
70 #define DRV_MODULE_NAME "tg3"
72 #define TG3_MIN_NUM 113
73 #define DRV_MODULE_VERSION \
74 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
75 #define DRV_MODULE_RELDATE "August 2, 2010"
77 #define TG3_DEF_MAC_MODE 0
78 #define TG3_DEF_RX_MODE 0
79 #define TG3_DEF_TX_MODE 0
80 #define TG3_DEF_MSG_ENABLE \
90 /* length of time before we decide the hardware is borked,
91 * and dev->tx_timeout() should be called to fix the problem
93 #define TG3_TX_TIMEOUT (5 * HZ)
95 /* hardware minimum and maximum for a single frame's data payload */
96 #define TG3_MIN_MTU 60
97 #define TG3_MAX_MTU(tp) \
98 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
100 /* These numbers seem to be hard coded in the NIC firmware somehow.
101 * You can't change the ring sizes, but you can change where you place
102 * them in the NIC onboard memory.
104 #define TG3_RX_STD_RING_SIZE(tp) 512
105 #define TG3_DEF_RX_RING_PENDING 200
106 #define TG3_RX_JMB_RING_SIZE(tp) 256
107 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
108 #define TG3_RSS_INDIR_TBL_SIZE 128
110 /* Do not place this n-ring entries value into the tp struct itself,
111 * we really want to expose these constants to GCC so that modulo et
112 * al. operations are done with shifts and masks instead of with
113 * hw multiply/modulo instructions. Another solution would be to
114 * replace things like '% foo' with '& (foo - 1)'.
116 #define TG3_RX_RCB_RING_SIZE(tp) \
117 (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
118 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
120 #define TG3_TX_RING_SIZE 512
121 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
123 #define TG3_RX_STD_RING_BYTES(tp) \
124 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
125 #define TG3_RX_JMB_RING_BYTES(tp) \
126 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
127 #define TG3_RX_RCB_RING_BYTES(tp) \
128 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_RCB_RING_SIZE(tp))
129 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
131 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
133 #define TG3_RX_DMA_ALIGN 16
134 #define TG3_RX_HEADROOM ALIGN(VLAN_HLEN, TG3_RX_DMA_ALIGN)
136 #define TG3_DMA_BYTE_ENAB 64
138 #define TG3_RX_STD_DMA_SZ 1536
139 #define TG3_RX_JMB_DMA_SZ 9046
141 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
143 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
144 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
146 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
147 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
149 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
150 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
152 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
153 * that are at least dword aligned when used in PCIX mode. The driver
154 * works around this bug by double copying the packet. This workaround
155 * is built into the normal double copy length check for efficiency.
157 * However, the double copy is only necessary on those architectures
158 * where unaligned memory accesses are inefficient. For those architectures
159 * where unaligned memory accesses incur little penalty, we can reintegrate
160 * the 5701 in the normal rx path. Doing so saves a device structure
161 * dereference by hardcoding the double copy threshold in place.
163 #define TG3_RX_COPY_THRESHOLD 256
164 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
165 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
167 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
170 /* minimum number of free TX descriptors required to wake up TX process */
171 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
173 #define TG3_RAW_IP_ALIGN 2
175 /* number of ETHTOOL_GSTATS u64's */
176 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
178 #define TG3_NUM_TEST 6
180 #define TG3_FW_UPDATE_TIMEOUT_SEC 5
182 #define FIRMWARE_TG3 "tigon/tg3.bin"
183 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
184 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
186 static char version
[] __devinitdata
=
187 DRV_MODULE_NAME
".c:v" DRV_MODULE_VERSION
" (" DRV_MODULE_RELDATE
")";
189 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
190 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
191 MODULE_LICENSE("GPL");
192 MODULE_VERSION(DRV_MODULE_VERSION
);
193 MODULE_FIRMWARE(FIRMWARE_TG3
);
194 MODULE_FIRMWARE(FIRMWARE_TG3TSO
);
195 MODULE_FIRMWARE(FIRMWARE_TG3TSO5
);
197 static int tg3_debug
= -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
198 module_param(tg3_debug
, int, 0);
199 MODULE_PARM_DESC(tg3_debug
, "Tigon3 bitmapped debugging message enable value");
201 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl
) = {
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5700
)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5701
)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702
)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5703
)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5704
)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702FE
)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705
)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705_2
)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705M
)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705M_2
)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702X
)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5703X
)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5704S
)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702A3
)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5703A3
)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5782
)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5788
)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5789
)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5901
)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5901_2
)},
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5704S_2
)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705F
)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5721
)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5722
)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5751
)},
227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5751M
)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5751F
)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5752
)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5752M
)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5753
)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5753M
)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5753F
)},
234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5754
)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5754M
)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5755
)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5755M
)},
238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5756
)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5786
)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5787
)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5787M
)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5787F
)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5714
)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5714S
)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5715
)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5715S
)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5780
)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5780S
)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5781
)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5906
)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5906M
)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5784
)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5764
)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5723
)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5761
)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5761E
)},
257 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5761S
)},
258 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5761SE
)},
259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5785_G
)},
260 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5785_F
)},
261 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57780
)},
262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57760
)},
263 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57790
)},
264 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57788
)},
265 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5717
)},
266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5718
)},
267 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57781
)},
268 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57785
)},
269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57761
)},
270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57765
)},
271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57791
)},
272 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57795
)},
273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5719
)},
274 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, PCI_DEVICE_ID_SYSKONNECT_9DXX
)},
275 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, PCI_DEVICE_ID_SYSKONNECT_9MXX
)},
276 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC1000
)},
277 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC1001
)},
278 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC1003
)},
279 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC9100
)},
280 {PCI_DEVICE(PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_TIGON3
)},
284 MODULE_DEVICE_TABLE(pci
, tg3_pci_tbl
);
286 static const struct {
287 const char string
[ETH_GSTRING_LEN
];
288 } ethtool_stats_keys
[TG3_NUM_STATS
] = {
291 { "rx_ucast_packets" },
292 { "rx_mcast_packets" },
293 { "rx_bcast_packets" },
295 { "rx_align_errors" },
296 { "rx_xon_pause_rcvd" },
297 { "rx_xoff_pause_rcvd" },
298 { "rx_mac_ctrl_rcvd" },
299 { "rx_xoff_entered" },
300 { "rx_frame_too_long_errors" },
302 { "rx_undersize_packets" },
303 { "rx_in_length_errors" },
304 { "rx_out_length_errors" },
305 { "rx_64_or_less_octet_packets" },
306 { "rx_65_to_127_octet_packets" },
307 { "rx_128_to_255_octet_packets" },
308 { "rx_256_to_511_octet_packets" },
309 { "rx_512_to_1023_octet_packets" },
310 { "rx_1024_to_1522_octet_packets" },
311 { "rx_1523_to_2047_octet_packets" },
312 { "rx_2048_to_4095_octet_packets" },
313 { "rx_4096_to_8191_octet_packets" },
314 { "rx_8192_to_9022_octet_packets" },
321 { "tx_flow_control" },
323 { "tx_single_collisions" },
324 { "tx_mult_collisions" },
326 { "tx_excessive_collisions" },
327 { "tx_late_collisions" },
328 { "tx_collide_2times" },
329 { "tx_collide_3times" },
330 { "tx_collide_4times" },
331 { "tx_collide_5times" },
332 { "tx_collide_6times" },
333 { "tx_collide_7times" },
334 { "tx_collide_8times" },
335 { "tx_collide_9times" },
336 { "tx_collide_10times" },
337 { "tx_collide_11times" },
338 { "tx_collide_12times" },
339 { "tx_collide_13times" },
340 { "tx_collide_14times" },
341 { "tx_collide_15times" },
342 { "tx_ucast_packets" },
343 { "tx_mcast_packets" },
344 { "tx_bcast_packets" },
345 { "tx_carrier_sense_errors" },
349 { "dma_writeq_full" },
350 { "dma_write_prioq_full" },
354 { "rx_threshold_hit" },
356 { "dma_readq_full" },
357 { "dma_read_prioq_full" },
358 { "tx_comp_queue_full" },
360 { "ring_set_send_prod_index" },
361 { "ring_status_update" },
363 { "nic_avoided_irqs" },
364 { "nic_tx_threshold_hit" }
367 static const struct {
368 const char string
[ETH_GSTRING_LEN
];
369 } ethtool_test_keys
[TG3_NUM_TEST
] = {
370 { "nvram test (online) " },
371 { "link test (online) " },
372 { "register test (offline)" },
373 { "memory test (offline)" },
374 { "loopback test (offline)" },
375 { "interrupt test (offline)" },
378 static void tg3_write32(struct tg3
*tp
, u32 off
, u32 val
)
380 writel(val
, tp
->regs
+ off
);
383 static u32
tg3_read32(struct tg3
*tp
, u32 off
)
385 return readl(tp
->regs
+ off
);
388 static void tg3_ape_write32(struct tg3
*tp
, u32 off
, u32 val
)
390 writel(val
, tp
->aperegs
+ off
);
393 static u32
tg3_ape_read32(struct tg3
*tp
, u32 off
)
395 return readl(tp
->aperegs
+ off
);
398 static void tg3_write_indirect_reg32(struct tg3
*tp
, u32 off
, u32 val
)
402 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
403 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
);
404 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, val
);
405 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
408 static void tg3_write_flush_reg32(struct tg3
*tp
, u32 off
, u32 val
)
410 writel(val
, tp
->regs
+ off
);
411 readl(tp
->regs
+ off
);
414 static u32
tg3_read_indirect_reg32(struct tg3
*tp
, u32 off
)
419 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
420 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
);
421 pci_read_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, &val
);
422 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
426 static void tg3_write_indirect_mbox(struct tg3
*tp
, u32 off
, u32 val
)
430 if (off
== (MAILBOX_RCVRET_CON_IDX_0
+ TG3_64BIT_REG_LOW
)) {
431 pci_write_config_dword(tp
->pdev
, TG3PCI_RCV_RET_RING_CON_IDX
+
432 TG3_64BIT_REG_LOW
, val
);
435 if (off
== TG3_RX_STD_PROD_IDX_REG
) {
436 pci_write_config_dword(tp
->pdev
, TG3PCI_STD_RING_PROD_IDX
+
437 TG3_64BIT_REG_LOW
, val
);
441 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
442 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
+ 0x5600);
443 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, val
);
444 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
446 /* In indirect mode when disabling interrupts, we also need
447 * to clear the interrupt bit in the GRC local ctrl register.
449 if ((off
== (MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
)) &&
451 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_LOCAL_CTRL
,
452 tp
->grc_local_ctrl
|GRC_LCLCTRL_CLEARINT
);
456 static u32
tg3_read_indirect_mbox(struct tg3
*tp
, u32 off
)
461 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
462 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
+ 0x5600);
463 pci_read_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, &val
);
464 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
468 /* usec_wait specifies the wait time in usec when writing to certain registers
469 * where it is unsafe to read back the register without some delay.
470 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
471 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
473 static void _tw32_flush(struct tg3
*tp
, u32 off
, u32 val
, u32 usec_wait
)
475 if ((tp
->tg3_flags
& TG3_FLAG_PCIX_TARGET_HWBUG
) ||
476 (tp
->tg3_flags2
& TG3_FLG2_ICH_WORKAROUND
))
477 /* Non-posted methods */
478 tp
->write32(tp
, off
, val
);
481 tg3_write32(tp
, off
, val
);
486 /* Wait again after the read for the posted method to guarantee that
487 * the wait time is met.
493 static inline void tw32_mailbox_flush(struct tg3
*tp
, u32 off
, u32 val
)
495 tp
->write32_mbox(tp
, off
, val
);
496 if (!(tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
) &&
497 !(tp
->tg3_flags2
& TG3_FLG2_ICH_WORKAROUND
))
498 tp
->read32_mbox(tp
, off
);
501 static void tg3_write32_tx_mbox(struct tg3
*tp
, u32 off
, u32 val
)
503 void __iomem
*mbox
= tp
->regs
+ off
;
505 if (tp
->tg3_flags
& TG3_FLAG_TXD_MBOX_HWBUG
)
507 if (tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
)
511 static u32
tg3_read32_mbox_5906(struct tg3
*tp
, u32 off
)
513 return readl(tp
->regs
+ off
+ GRCMBOX_BASE
);
516 static void tg3_write32_mbox_5906(struct tg3
*tp
, u32 off
, u32 val
)
518 writel(val
, tp
->regs
+ off
+ GRCMBOX_BASE
);
521 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
522 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
523 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
524 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
525 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
527 #define tw32(reg, val) tp->write32(tp, reg, val)
528 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
529 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
530 #define tr32(reg) tp->read32(tp, reg)
532 static void tg3_write_mem(struct tg3
*tp
, u32 off
, u32 val
)
536 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) &&
537 (off
>= NIC_SRAM_STATS_BLK
) && (off
< NIC_SRAM_TX_BUFFER_DESC
))
540 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
541 if (tp
->tg3_flags
& TG3_FLAG_SRAM_USE_CONFIG
) {
542 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, off
);
543 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_DATA
, val
);
545 /* Always leave this as zero. */
546 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, 0);
548 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, off
);
549 tw32_f(TG3PCI_MEM_WIN_DATA
, val
);
551 /* Always leave this as zero. */
552 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
554 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
557 static void tg3_read_mem(struct tg3
*tp
, u32 off
, u32
*val
)
561 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) &&
562 (off
>= NIC_SRAM_STATS_BLK
) && (off
< NIC_SRAM_TX_BUFFER_DESC
)) {
567 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
568 if (tp
->tg3_flags
& TG3_FLAG_SRAM_USE_CONFIG
) {
569 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, off
);
570 pci_read_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_DATA
, val
);
572 /* Always leave this as zero. */
573 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, 0);
575 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, off
);
576 *val
= tr32(TG3PCI_MEM_WIN_DATA
);
578 /* Always leave this as zero. */
579 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
581 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
584 static void tg3_ape_lock_init(struct tg3
*tp
)
589 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
)
590 regbase
= TG3_APE_LOCK_GRANT
;
592 regbase
= TG3_APE_PER_LOCK_GRANT
;
594 /* Make sure the driver hasn't any stale locks. */
595 for (i
= 0; i
< 8; i
++)
596 tg3_ape_write32(tp
, regbase
+ 4 * i
, APE_LOCK_GRANT_DRIVER
);
599 static int tg3_ape_lock(struct tg3
*tp
, int locknum
)
603 u32 status
, req
, gnt
;
605 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
))
609 case TG3_APE_LOCK_GRC
:
610 case TG3_APE_LOCK_MEM
:
616 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
) {
617 req
= TG3_APE_LOCK_REQ
;
618 gnt
= TG3_APE_LOCK_GRANT
;
620 req
= TG3_APE_PER_LOCK_REQ
;
621 gnt
= TG3_APE_PER_LOCK_GRANT
;
626 tg3_ape_write32(tp
, req
+ off
, APE_LOCK_REQ_DRIVER
);
628 /* Wait for up to 1 millisecond to acquire lock. */
629 for (i
= 0; i
< 100; i
++) {
630 status
= tg3_ape_read32(tp
, gnt
+ off
);
631 if (status
== APE_LOCK_GRANT_DRIVER
)
636 if (status
!= APE_LOCK_GRANT_DRIVER
) {
637 /* Revoke the lock request. */
638 tg3_ape_write32(tp
, gnt
+ off
,
639 APE_LOCK_GRANT_DRIVER
);
647 static void tg3_ape_unlock(struct tg3
*tp
, int locknum
)
651 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
))
655 case TG3_APE_LOCK_GRC
:
656 case TG3_APE_LOCK_MEM
:
662 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
)
663 gnt
= TG3_APE_LOCK_GRANT
;
665 gnt
= TG3_APE_PER_LOCK_GRANT
;
667 tg3_ape_write32(tp
, gnt
+ 4 * locknum
, APE_LOCK_GRANT_DRIVER
);
670 static void tg3_disable_ints(struct tg3
*tp
)
674 tw32(TG3PCI_MISC_HOST_CTRL
,
675 (tp
->misc_host_ctrl
| MISC_HOST_CTRL_MASK_PCI_INT
));
676 for (i
= 0; i
< tp
->irq_max
; i
++)
677 tw32_mailbox_f(tp
->napi
[i
].int_mbox
, 0x00000001);
680 static void tg3_enable_ints(struct tg3
*tp
)
687 tw32(TG3PCI_MISC_HOST_CTRL
,
688 (tp
->misc_host_ctrl
& ~MISC_HOST_CTRL_MASK_PCI_INT
));
690 tp
->coal_now
= tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
;
691 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
692 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
694 tw32_mailbox_f(tnapi
->int_mbox
, tnapi
->last_tag
<< 24);
695 if (tp
->tg3_flags2
& TG3_FLG2_1SHOT_MSI
)
696 tw32_mailbox_f(tnapi
->int_mbox
, tnapi
->last_tag
<< 24);
698 tp
->coal_now
|= tnapi
->coal_now
;
701 /* Force an initial interrupt */
702 if (!(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) &&
703 (tp
->napi
[0].hw_status
->status
& SD_STATUS_UPDATED
))
704 tw32(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
| GRC_LCLCTRL_SETINT
);
706 tw32(HOSTCC_MODE
, tp
->coal_now
);
708 tp
->coal_now
&= ~(tp
->napi
[0].coal_now
| tp
->napi
[1].coal_now
);
711 static inline unsigned int tg3_has_work(struct tg3_napi
*tnapi
)
713 struct tg3
*tp
= tnapi
->tp
;
714 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
715 unsigned int work_exists
= 0;
717 /* check for phy events */
718 if (!(tp
->tg3_flags
&
719 (TG3_FLAG_USE_LINKCHG_REG
|
720 TG3_FLAG_POLL_SERDES
))) {
721 if (sblk
->status
& SD_STATUS_LINK_CHG
)
724 /* check for RX/TX work to do */
725 if (sblk
->idx
[0].tx_consumer
!= tnapi
->tx_cons
||
726 *(tnapi
->rx_rcb_prod_idx
) != tnapi
->rx_rcb_ptr
)
733 * similar to tg3_enable_ints, but it accurately determines whether there
734 * is new work pending and can return without flushing the PIO write
735 * which reenables interrupts
737 static void tg3_int_reenable(struct tg3_napi
*tnapi
)
739 struct tg3
*tp
= tnapi
->tp
;
741 tw32_mailbox(tnapi
->int_mbox
, tnapi
->last_tag
<< 24);
744 /* When doing tagged status, this work check is unnecessary.
745 * The last_tag we write above tells the chip which piece of
746 * work we've completed.
748 if (!(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) &&
750 tw32(HOSTCC_MODE
, tp
->coalesce_mode
|
751 HOSTCC_MODE_ENABLE
| tnapi
->coal_now
);
754 static void tg3_switch_clocks(struct tg3
*tp
)
759 if ((tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) ||
760 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
763 clock_ctrl
= tr32(TG3PCI_CLOCK_CTRL
);
765 orig_clock_ctrl
= clock_ctrl
;
766 clock_ctrl
&= (CLOCK_CTRL_FORCE_CLKRUN
|
767 CLOCK_CTRL_CLKRUN_OENABLE
|
769 tp
->pci_clock_ctrl
= clock_ctrl
;
771 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
772 if (orig_clock_ctrl
& CLOCK_CTRL_625_CORE
) {
773 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
774 clock_ctrl
| CLOCK_CTRL_625_CORE
, 40);
776 } else if ((orig_clock_ctrl
& CLOCK_CTRL_44MHZ_CORE
) != 0) {
777 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
779 (CLOCK_CTRL_44MHZ_CORE
| CLOCK_CTRL_ALTCLK
),
781 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
782 clock_ctrl
| (CLOCK_CTRL_ALTCLK
),
785 tw32_wait_f(TG3PCI_CLOCK_CTRL
, clock_ctrl
, 40);
788 #define PHY_BUSY_LOOPS 5000
790 static int tg3_readphy(struct tg3
*tp
, int reg
, u32
*val
)
796 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
798 (tp
->mi_mode
& ~MAC_MI_MODE_AUTO_POLL
));
804 frame_val
= ((tp
->phy_addr
<< MI_COM_PHY_ADDR_SHIFT
) &
805 MI_COM_PHY_ADDR_MASK
);
806 frame_val
|= ((reg
<< MI_COM_REG_ADDR_SHIFT
) &
807 MI_COM_REG_ADDR_MASK
);
808 frame_val
|= (MI_COM_CMD_READ
| MI_COM_START
);
810 tw32_f(MAC_MI_COM
, frame_val
);
812 loops
= PHY_BUSY_LOOPS
;
815 frame_val
= tr32(MAC_MI_COM
);
817 if ((frame_val
& MI_COM_BUSY
) == 0) {
819 frame_val
= tr32(MAC_MI_COM
);
827 *val
= frame_val
& MI_COM_DATA_MASK
;
831 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
832 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
839 static int tg3_writephy(struct tg3
*tp
, int reg
, u32 val
)
845 if ((tp
->phy_flags
& TG3_PHYFLG_IS_FET
) &&
846 (reg
== MII_TG3_CTRL
|| reg
== MII_TG3_AUX_CTRL
))
849 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
851 (tp
->mi_mode
& ~MAC_MI_MODE_AUTO_POLL
));
855 frame_val
= ((tp
->phy_addr
<< MI_COM_PHY_ADDR_SHIFT
) &
856 MI_COM_PHY_ADDR_MASK
);
857 frame_val
|= ((reg
<< MI_COM_REG_ADDR_SHIFT
) &
858 MI_COM_REG_ADDR_MASK
);
859 frame_val
|= (val
& MI_COM_DATA_MASK
);
860 frame_val
|= (MI_COM_CMD_WRITE
| MI_COM_START
);
862 tw32_f(MAC_MI_COM
, frame_val
);
864 loops
= PHY_BUSY_LOOPS
;
867 frame_val
= tr32(MAC_MI_COM
);
868 if ((frame_val
& MI_COM_BUSY
) == 0) {
870 frame_val
= tr32(MAC_MI_COM
);
880 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
881 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
888 static int tg3_bmcr_reset(struct tg3
*tp
)
893 /* OK, reset it, and poll the BMCR_RESET bit until it
894 * clears or we time out.
896 phy_control
= BMCR_RESET
;
897 err
= tg3_writephy(tp
, MII_BMCR
, phy_control
);
903 err
= tg3_readphy(tp
, MII_BMCR
, &phy_control
);
907 if ((phy_control
& BMCR_RESET
) == 0) {
919 static int tg3_mdio_read(struct mii_bus
*bp
, int mii_id
, int reg
)
921 struct tg3
*tp
= bp
->priv
;
924 spin_lock_bh(&tp
->lock
);
926 if (tg3_readphy(tp
, reg
, &val
))
929 spin_unlock_bh(&tp
->lock
);
934 static int tg3_mdio_write(struct mii_bus
*bp
, int mii_id
, int reg
, u16 val
)
936 struct tg3
*tp
= bp
->priv
;
939 spin_lock_bh(&tp
->lock
);
941 if (tg3_writephy(tp
, reg
, val
))
944 spin_unlock_bh(&tp
->lock
);
949 static int tg3_mdio_reset(struct mii_bus
*bp
)
954 static void tg3_mdio_config_5785(struct tg3
*tp
)
957 struct phy_device
*phydev
;
959 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
960 switch (phydev
->drv
->phy_id
& phydev
->drv
->phy_id_mask
) {
961 case PHY_ID_BCM50610
:
962 case PHY_ID_BCM50610M
:
963 val
= MAC_PHYCFG2_50610_LED_MODES
;
965 case PHY_ID_BCMAC131
:
966 val
= MAC_PHYCFG2_AC131_LED_MODES
;
968 case PHY_ID_RTL8211C
:
969 val
= MAC_PHYCFG2_RTL8211C_LED_MODES
;
971 case PHY_ID_RTL8201E
:
972 val
= MAC_PHYCFG2_RTL8201E_LED_MODES
;
978 if (phydev
->interface
!= PHY_INTERFACE_MODE_RGMII
) {
979 tw32(MAC_PHYCFG2
, val
);
981 val
= tr32(MAC_PHYCFG1
);
982 val
&= ~(MAC_PHYCFG1_RGMII_INT
|
983 MAC_PHYCFG1_RXCLK_TO_MASK
| MAC_PHYCFG1_TXCLK_TO_MASK
);
984 val
|= MAC_PHYCFG1_RXCLK_TIMEOUT
| MAC_PHYCFG1_TXCLK_TIMEOUT
;
985 tw32(MAC_PHYCFG1
, val
);
990 if (!(tp
->tg3_flags3
& TG3_FLG3_RGMII_INBAND_DISABLE
))
991 val
|= MAC_PHYCFG2_EMODE_MASK_MASK
|
992 MAC_PHYCFG2_FMODE_MASK_MASK
|
993 MAC_PHYCFG2_GMODE_MASK_MASK
|
994 MAC_PHYCFG2_ACT_MASK_MASK
|
995 MAC_PHYCFG2_QUAL_MASK_MASK
|
996 MAC_PHYCFG2_INBAND_ENABLE
;
998 tw32(MAC_PHYCFG2
, val
);
1000 val
= tr32(MAC_PHYCFG1
);
1001 val
&= ~(MAC_PHYCFG1_RXCLK_TO_MASK
| MAC_PHYCFG1_TXCLK_TO_MASK
|
1002 MAC_PHYCFG1_RGMII_EXT_RX_DEC
| MAC_PHYCFG1_RGMII_SND_STAT_EN
);
1003 if (!(tp
->tg3_flags3
& TG3_FLG3_RGMII_INBAND_DISABLE
)) {
1004 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_RX_EN
)
1005 val
|= MAC_PHYCFG1_RGMII_EXT_RX_DEC
;
1006 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_TX_EN
)
1007 val
|= MAC_PHYCFG1_RGMII_SND_STAT_EN
;
1009 val
|= MAC_PHYCFG1_RXCLK_TIMEOUT
| MAC_PHYCFG1_TXCLK_TIMEOUT
|
1010 MAC_PHYCFG1_RGMII_INT
| MAC_PHYCFG1_TXC_DRV
;
1011 tw32(MAC_PHYCFG1
, val
);
1013 val
= tr32(MAC_EXT_RGMII_MODE
);
1014 val
&= ~(MAC_RGMII_MODE_RX_INT_B
|
1015 MAC_RGMII_MODE_RX_QUALITY
|
1016 MAC_RGMII_MODE_RX_ACTIVITY
|
1017 MAC_RGMII_MODE_RX_ENG_DET
|
1018 MAC_RGMII_MODE_TX_ENABLE
|
1019 MAC_RGMII_MODE_TX_LOWPWR
|
1020 MAC_RGMII_MODE_TX_RESET
);
1021 if (!(tp
->tg3_flags3
& TG3_FLG3_RGMII_INBAND_DISABLE
)) {
1022 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_RX_EN
)
1023 val
|= MAC_RGMII_MODE_RX_INT_B
|
1024 MAC_RGMII_MODE_RX_QUALITY
|
1025 MAC_RGMII_MODE_RX_ACTIVITY
|
1026 MAC_RGMII_MODE_RX_ENG_DET
;
1027 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_TX_EN
)
1028 val
|= MAC_RGMII_MODE_TX_ENABLE
|
1029 MAC_RGMII_MODE_TX_LOWPWR
|
1030 MAC_RGMII_MODE_TX_RESET
;
1032 tw32(MAC_EXT_RGMII_MODE
, val
);
1035 static void tg3_mdio_start(struct tg3
*tp
)
1037 tp
->mi_mode
&= ~MAC_MI_MODE_AUTO_POLL
;
1038 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
1041 if ((tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_INITED
) &&
1042 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
1043 tg3_mdio_config_5785(tp
);
1046 static int tg3_mdio_init(struct tg3
*tp
)
1050 struct phy_device
*phydev
;
1052 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
1053 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
) {
1056 tp
->phy_addr
= PCI_FUNC(tp
->pdev
->devfn
) + 1;
1058 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5717_A0
)
1059 is_serdes
= tr32(SG_DIG_STATUS
) & SG_DIG_IS_SERDES
;
1061 is_serdes
= tr32(TG3_CPMU_PHY_STRAP
) &
1062 TG3_CPMU_PHY_STRAP_IS_SERDES
;
1066 tp
->phy_addr
= TG3_PHY_MII_ADDR
;
1070 if (!(tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) ||
1071 (tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_INITED
))
1074 tp
->mdio_bus
= mdiobus_alloc();
1075 if (tp
->mdio_bus
== NULL
)
1078 tp
->mdio_bus
->name
= "tg3 mdio bus";
1079 snprintf(tp
->mdio_bus
->id
, MII_BUS_ID_SIZE
, "%x",
1080 (tp
->pdev
->bus
->number
<< 8) | tp
->pdev
->devfn
);
1081 tp
->mdio_bus
->priv
= tp
;
1082 tp
->mdio_bus
->parent
= &tp
->pdev
->dev
;
1083 tp
->mdio_bus
->read
= &tg3_mdio_read
;
1084 tp
->mdio_bus
->write
= &tg3_mdio_write
;
1085 tp
->mdio_bus
->reset
= &tg3_mdio_reset
;
1086 tp
->mdio_bus
->phy_mask
= ~(1 << TG3_PHY_MII_ADDR
);
1087 tp
->mdio_bus
->irq
= &tp
->mdio_irq
[0];
1089 for (i
= 0; i
< PHY_MAX_ADDR
; i
++)
1090 tp
->mdio_bus
->irq
[i
] = PHY_POLL
;
1092 /* The bus registration will look for all the PHYs on the mdio bus.
1093 * Unfortunately, it does not ensure the PHY is powered up before
1094 * accessing the PHY ID registers. A chip reset is the
1095 * quickest way to bring the device back to an operational state..
1097 if (tg3_readphy(tp
, MII_BMCR
, ®
) || (reg
& BMCR_PDOWN
))
1100 i
= mdiobus_register(tp
->mdio_bus
);
1102 dev_warn(&tp
->pdev
->dev
, "mdiobus_reg failed (0x%x)\n", i
);
1103 mdiobus_free(tp
->mdio_bus
);
1107 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
1109 if (!phydev
|| !phydev
->drv
) {
1110 dev_warn(&tp
->pdev
->dev
, "No PHY devices\n");
1111 mdiobus_unregister(tp
->mdio_bus
);
1112 mdiobus_free(tp
->mdio_bus
);
1116 switch (phydev
->drv
->phy_id
& phydev
->drv
->phy_id_mask
) {
1117 case PHY_ID_BCM57780
:
1118 phydev
->interface
= PHY_INTERFACE_MODE_GMII
;
1119 phydev
->dev_flags
|= PHY_BRCM_AUTO_PWRDWN_ENABLE
;
1121 case PHY_ID_BCM50610
:
1122 case PHY_ID_BCM50610M
:
1123 phydev
->dev_flags
|= PHY_BRCM_CLEAR_RGMII_MODE
|
1124 PHY_BRCM_RX_REFCLK_UNUSED
|
1125 PHY_BRCM_DIS_TXCRXC_NOENRGY
|
1126 PHY_BRCM_AUTO_PWRDWN_ENABLE
;
1127 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_INBAND_DISABLE
)
1128 phydev
->dev_flags
|= PHY_BRCM_STD_IBND_DISABLE
;
1129 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_RX_EN
)
1130 phydev
->dev_flags
|= PHY_BRCM_EXT_IBND_RX_ENABLE
;
1131 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_TX_EN
)
1132 phydev
->dev_flags
|= PHY_BRCM_EXT_IBND_TX_ENABLE
;
1134 case PHY_ID_RTL8211C
:
1135 phydev
->interface
= PHY_INTERFACE_MODE_RGMII
;
1137 case PHY_ID_RTL8201E
:
1138 case PHY_ID_BCMAC131
:
1139 phydev
->interface
= PHY_INTERFACE_MODE_MII
;
1140 phydev
->dev_flags
|= PHY_BRCM_AUTO_PWRDWN_ENABLE
;
1141 tp
->phy_flags
|= TG3_PHYFLG_IS_FET
;
1145 tp
->tg3_flags3
|= TG3_FLG3_MDIOBUS_INITED
;
1147 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
1148 tg3_mdio_config_5785(tp
);
1153 static void tg3_mdio_fini(struct tg3
*tp
)
1155 if (tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_INITED
) {
1156 tp
->tg3_flags3
&= ~TG3_FLG3_MDIOBUS_INITED
;
1157 mdiobus_unregister(tp
->mdio_bus
);
1158 mdiobus_free(tp
->mdio_bus
);
1162 /* tp->lock is held. */
1163 static inline void tg3_generate_fw_event(struct tg3
*tp
)
1167 val
= tr32(GRC_RX_CPU_EVENT
);
1168 val
|= GRC_RX_CPU_DRIVER_EVENT
;
1169 tw32_f(GRC_RX_CPU_EVENT
, val
);
1171 tp
->last_event_jiffies
= jiffies
;
1174 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1176 /* tp->lock is held. */
1177 static void tg3_wait_for_event_ack(struct tg3
*tp
)
1180 unsigned int delay_cnt
;
1183 /* If enough time has passed, no wait is necessary. */
1184 time_remain
= (long)(tp
->last_event_jiffies
+ 1 +
1185 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC
)) -
1187 if (time_remain
< 0)
1190 /* Check if we can shorten the wait time. */
1191 delay_cnt
= jiffies_to_usecs(time_remain
);
1192 if (delay_cnt
> TG3_FW_EVENT_TIMEOUT_USEC
)
1193 delay_cnt
= TG3_FW_EVENT_TIMEOUT_USEC
;
1194 delay_cnt
= (delay_cnt
>> 3) + 1;
1196 for (i
= 0; i
< delay_cnt
; i
++) {
1197 if (!(tr32(GRC_RX_CPU_EVENT
) & GRC_RX_CPU_DRIVER_EVENT
))
1203 /* tp->lock is held. */
1204 static void tg3_ump_link_report(struct tg3
*tp
)
1209 if (!(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) ||
1210 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
1213 tg3_wait_for_event_ack(tp
);
1215 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_MBOX
, FWCMD_NICDRV_LINK_UPDATE
);
1217 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_LEN_MBOX
, 14);
1220 if (!tg3_readphy(tp
, MII_BMCR
, ®
))
1222 if (!tg3_readphy(tp
, MII_BMSR
, ®
))
1223 val
|= (reg
& 0xffff);
1224 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
, val
);
1227 if (!tg3_readphy(tp
, MII_ADVERTISE
, ®
))
1229 if (!tg3_readphy(tp
, MII_LPA
, ®
))
1230 val
|= (reg
& 0xffff);
1231 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
+ 4, val
);
1234 if (!(tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
)) {
1235 if (!tg3_readphy(tp
, MII_CTRL1000
, ®
))
1237 if (!tg3_readphy(tp
, MII_STAT1000
, ®
))
1238 val
|= (reg
& 0xffff);
1240 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
+ 8, val
);
1242 if (!tg3_readphy(tp
, MII_PHYADDR
, ®
))
1246 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
+ 12, val
);
1248 tg3_generate_fw_event(tp
);
1251 static void tg3_link_report(struct tg3
*tp
)
1253 if (!netif_carrier_ok(tp
->dev
)) {
1254 netif_info(tp
, link
, tp
->dev
, "Link is down\n");
1255 tg3_ump_link_report(tp
);
1256 } else if (netif_msg_link(tp
)) {
1257 netdev_info(tp
->dev
, "Link is up at %d Mbps, %s duplex\n",
1258 (tp
->link_config
.active_speed
== SPEED_1000
?
1260 (tp
->link_config
.active_speed
== SPEED_100
?
1262 (tp
->link_config
.active_duplex
== DUPLEX_FULL
?
1265 netdev_info(tp
->dev
, "Flow control is %s for TX and %s for RX\n",
1266 (tp
->link_config
.active_flowctrl
& FLOW_CTRL_TX
) ?
1268 (tp
->link_config
.active_flowctrl
& FLOW_CTRL_RX
) ?
1270 tg3_ump_link_report(tp
);
1274 static u16
tg3_advert_flowctrl_1000T(u8 flow_ctrl
)
1278 if ((flow_ctrl
& FLOW_CTRL_TX
) && (flow_ctrl
& FLOW_CTRL_RX
))
1279 miireg
= ADVERTISE_PAUSE_CAP
;
1280 else if (flow_ctrl
& FLOW_CTRL_TX
)
1281 miireg
= ADVERTISE_PAUSE_ASYM
;
1282 else if (flow_ctrl
& FLOW_CTRL_RX
)
1283 miireg
= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
1290 static u16
tg3_advert_flowctrl_1000X(u8 flow_ctrl
)
1294 if ((flow_ctrl
& FLOW_CTRL_TX
) && (flow_ctrl
& FLOW_CTRL_RX
))
1295 miireg
= ADVERTISE_1000XPAUSE
;
1296 else if (flow_ctrl
& FLOW_CTRL_TX
)
1297 miireg
= ADVERTISE_1000XPSE_ASYM
;
1298 else if (flow_ctrl
& FLOW_CTRL_RX
)
1299 miireg
= ADVERTISE_1000XPAUSE
| ADVERTISE_1000XPSE_ASYM
;
1306 static u8
tg3_resolve_flowctrl_1000X(u16 lcladv
, u16 rmtadv
)
1310 if (lcladv
& ADVERTISE_1000XPAUSE
) {
1311 if (lcladv
& ADVERTISE_1000XPSE_ASYM
) {
1312 if (rmtadv
& LPA_1000XPAUSE
)
1313 cap
= FLOW_CTRL_TX
| FLOW_CTRL_RX
;
1314 else if (rmtadv
& LPA_1000XPAUSE_ASYM
)
1317 if (rmtadv
& LPA_1000XPAUSE
)
1318 cap
= FLOW_CTRL_TX
| FLOW_CTRL_RX
;
1320 } else if (lcladv
& ADVERTISE_1000XPSE_ASYM
) {
1321 if ((rmtadv
& LPA_1000XPAUSE
) && (rmtadv
& LPA_1000XPAUSE_ASYM
))
1328 static void tg3_setup_flow_control(struct tg3
*tp
, u32 lcladv
, u32 rmtadv
)
1332 u32 old_rx_mode
= tp
->rx_mode
;
1333 u32 old_tx_mode
= tp
->tx_mode
;
1335 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
)
1336 autoneg
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
]->autoneg
;
1338 autoneg
= tp
->link_config
.autoneg
;
1340 if (autoneg
== AUTONEG_ENABLE
&&
1341 (tp
->tg3_flags
& TG3_FLAG_PAUSE_AUTONEG
)) {
1342 if (tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
)
1343 flowctrl
= tg3_resolve_flowctrl_1000X(lcladv
, rmtadv
);
1345 flowctrl
= mii_resolve_flowctrl_fdx(lcladv
, rmtadv
);
1347 flowctrl
= tp
->link_config
.flowctrl
;
1349 tp
->link_config
.active_flowctrl
= flowctrl
;
1351 if (flowctrl
& FLOW_CTRL_RX
)
1352 tp
->rx_mode
|= RX_MODE_FLOW_CTRL_ENABLE
;
1354 tp
->rx_mode
&= ~RX_MODE_FLOW_CTRL_ENABLE
;
1356 if (old_rx_mode
!= tp
->rx_mode
)
1357 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
1359 if (flowctrl
& FLOW_CTRL_TX
)
1360 tp
->tx_mode
|= TX_MODE_FLOW_CTRL_ENABLE
;
1362 tp
->tx_mode
&= ~TX_MODE_FLOW_CTRL_ENABLE
;
1364 if (old_tx_mode
!= tp
->tx_mode
)
1365 tw32_f(MAC_TX_MODE
, tp
->tx_mode
);
1368 static void tg3_adjust_link(struct net_device
*dev
)
1370 u8 oldflowctrl
, linkmesg
= 0;
1371 u32 mac_mode
, lcl_adv
, rmt_adv
;
1372 struct tg3
*tp
= netdev_priv(dev
);
1373 struct phy_device
*phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
1375 spin_lock_bh(&tp
->lock
);
1377 mac_mode
= tp
->mac_mode
& ~(MAC_MODE_PORT_MODE_MASK
|
1378 MAC_MODE_HALF_DUPLEX
);
1380 oldflowctrl
= tp
->link_config
.active_flowctrl
;
1386 if (phydev
->speed
== SPEED_100
|| phydev
->speed
== SPEED_10
)
1387 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
1388 else if (phydev
->speed
== SPEED_1000
||
1389 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5785
)
1390 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
1392 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
1394 if (phydev
->duplex
== DUPLEX_HALF
)
1395 mac_mode
|= MAC_MODE_HALF_DUPLEX
;
1397 lcl_adv
= tg3_advert_flowctrl_1000T(
1398 tp
->link_config
.flowctrl
);
1401 rmt_adv
= LPA_PAUSE_CAP
;
1402 if (phydev
->asym_pause
)
1403 rmt_adv
|= LPA_PAUSE_ASYM
;
1406 tg3_setup_flow_control(tp
, lcl_adv
, rmt_adv
);
1408 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
1410 if (mac_mode
!= tp
->mac_mode
) {
1411 tp
->mac_mode
= mac_mode
;
1412 tw32_f(MAC_MODE
, tp
->mac_mode
);
1416 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
) {
1417 if (phydev
->speed
== SPEED_10
)
1419 MAC_MI_STAT_10MBPS_MODE
|
1420 MAC_MI_STAT_LNKSTAT_ATTN_ENAB
);
1422 tw32(MAC_MI_STAT
, MAC_MI_STAT_LNKSTAT_ATTN_ENAB
);
1425 if (phydev
->speed
== SPEED_1000
&& phydev
->duplex
== DUPLEX_HALF
)
1426 tw32(MAC_TX_LENGTHS
,
1427 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
1428 (6 << TX_LENGTHS_IPG_SHIFT
) |
1429 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT
)));
1431 tw32(MAC_TX_LENGTHS
,
1432 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
1433 (6 << TX_LENGTHS_IPG_SHIFT
) |
1434 (32 << TX_LENGTHS_SLOT_TIME_SHIFT
)));
1436 if ((phydev
->link
&& tp
->link_config
.active_speed
== SPEED_INVALID
) ||
1437 (!phydev
->link
&& tp
->link_config
.active_speed
!= SPEED_INVALID
) ||
1438 phydev
->speed
!= tp
->link_config
.active_speed
||
1439 phydev
->duplex
!= tp
->link_config
.active_duplex
||
1440 oldflowctrl
!= tp
->link_config
.active_flowctrl
)
1443 tp
->link_config
.active_speed
= phydev
->speed
;
1444 tp
->link_config
.active_duplex
= phydev
->duplex
;
1446 spin_unlock_bh(&tp
->lock
);
1449 tg3_link_report(tp
);
1452 static int tg3_phy_init(struct tg3
*tp
)
1454 struct phy_device
*phydev
;
1456 if (tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
)
1459 /* Bring the PHY back to a known state. */
1462 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
1464 /* Attach the MAC to the PHY. */
1465 phydev
= phy_connect(tp
->dev
, dev_name(&phydev
->dev
), tg3_adjust_link
,
1466 phydev
->dev_flags
, phydev
->interface
);
1467 if (IS_ERR(phydev
)) {
1468 dev_err(&tp
->pdev
->dev
, "Could not attach to PHY\n");
1469 return PTR_ERR(phydev
);
1472 /* Mask with MAC supported features. */
1473 switch (phydev
->interface
) {
1474 case PHY_INTERFACE_MODE_GMII
:
1475 case PHY_INTERFACE_MODE_RGMII
:
1476 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
)) {
1477 phydev
->supported
&= (PHY_GBIT_FEATURES
|
1479 SUPPORTED_Asym_Pause
);
1483 case PHY_INTERFACE_MODE_MII
:
1484 phydev
->supported
&= (PHY_BASIC_FEATURES
|
1486 SUPPORTED_Asym_Pause
);
1489 phy_disconnect(tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
]);
1493 tp
->phy_flags
|= TG3_PHYFLG_IS_CONNECTED
;
1495 phydev
->advertising
= phydev
->supported
;
1500 static void tg3_phy_start(struct tg3
*tp
)
1502 struct phy_device
*phydev
;
1504 if (!(tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
))
1507 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
1509 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
) {
1510 tp
->phy_flags
&= ~TG3_PHYFLG_IS_LOW_POWER
;
1511 phydev
->speed
= tp
->link_config
.orig_speed
;
1512 phydev
->duplex
= tp
->link_config
.orig_duplex
;
1513 phydev
->autoneg
= tp
->link_config
.orig_autoneg
;
1514 phydev
->advertising
= tp
->link_config
.orig_advertising
;
1519 phy_start_aneg(phydev
);
1522 static void tg3_phy_stop(struct tg3
*tp
)
1524 if (!(tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
))
1527 phy_stop(tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
]);
1530 static void tg3_phy_fini(struct tg3
*tp
)
1532 if (tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
) {
1533 phy_disconnect(tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
]);
1534 tp
->phy_flags
&= ~TG3_PHYFLG_IS_CONNECTED
;
1538 static int tg3_phydsp_write(struct tg3
*tp
, u32 reg
, u32 val
)
1542 err
= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, reg
);
1544 err
= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, val
);
1549 static void tg3_phy_fet_toggle_apd(struct tg3
*tp
, bool enable
)
1553 if (!tg3_readphy(tp
, MII_TG3_FET_TEST
, &phytest
)) {
1556 tg3_writephy(tp
, MII_TG3_FET_TEST
,
1557 phytest
| MII_TG3_FET_SHADOW_EN
);
1558 if (!tg3_readphy(tp
, MII_TG3_FET_SHDW_AUXSTAT2
, &phy
)) {
1560 phy
|= MII_TG3_FET_SHDW_AUXSTAT2_APD
;
1562 phy
&= ~MII_TG3_FET_SHDW_AUXSTAT2_APD
;
1563 tg3_writephy(tp
, MII_TG3_FET_SHDW_AUXSTAT2
, phy
);
1565 tg3_writephy(tp
, MII_TG3_FET_TEST
, phytest
);
1569 static void tg3_phy_toggle_apd(struct tg3
*tp
, bool enable
)
1573 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) ||
1574 ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
1575 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
) &&
1576 (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
)))
1579 if (tp
->phy_flags
& TG3_PHYFLG_IS_FET
) {
1580 tg3_phy_fet_toggle_apd(tp
, enable
);
1584 reg
= MII_TG3_MISC_SHDW_WREN
|
1585 MII_TG3_MISC_SHDW_SCR5_SEL
|
1586 MII_TG3_MISC_SHDW_SCR5_LPED
|
1587 MII_TG3_MISC_SHDW_SCR5_DLPTLM
|
1588 MII_TG3_MISC_SHDW_SCR5_SDTL
|
1589 MII_TG3_MISC_SHDW_SCR5_C125OE
;
1590 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5784
|| !enable
)
1591 reg
|= MII_TG3_MISC_SHDW_SCR5_DLLAPD
;
1593 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, reg
);
1596 reg
= MII_TG3_MISC_SHDW_WREN
|
1597 MII_TG3_MISC_SHDW_APD_SEL
|
1598 MII_TG3_MISC_SHDW_APD_WKTM_84MS
;
1600 reg
|= MII_TG3_MISC_SHDW_APD_ENABLE
;
1602 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, reg
);
1605 static void tg3_phy_toggle_automdix(struct tg3
*tp
, int enable
)
1609 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) ||
1610 (tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
))
1613 if (tp
->phy_flags
& TG3_PHYFLG_IS_FET
) {
1616 if (!tg3_readphy(tp
, MII_TG3_FET_TEST
, &ephy
)) {
1617 u32 reg
= MII_TG3_FET_SHDW_MISCCTRL
;
1619 tg3_writephy(tp
, MII_TG3_FET_TEST
,
1620 ephy
| MII_TG3_FET_SHADOW_EN
);
1621 if (!tg3_readphy(tp
, reg
, &phy
)) {
1623 phy
|= MII_TG3_FET_SHDW_MISCCTRL_MDIX
;
1625 phy
&= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX
;
1626 tg3_writephy(tp
, reg
, phy
);
1628 tg3_writephy(tp
, MII_TG3_FET_TEST
, ephy
);
1631 phy
= MII_TG3_AUXCTL_MISC_RDSEL_MISC
|
1632 MII_TG3_AUXCTL_SHDWSEL_MISC
;
1633 if (!tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy
) &&
1634 !tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &phy
)) {
1636 phy
|= MII_TG3_AUXCTL_MISC_FORCE_AMDIX
;
1638 phy
&= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX
;
1639 phy
|= MII_TG3_AUXCTL_MISC_WREN
;
1640 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy
);
1645 static void tg3_phy_set_wirespeed(struct tg3
*tp
)
1649 if (tp
->phy_flags
& TG3_PHYFLG_NO_ETH_WIRE_SPEED
)
1652 if (!tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x7007) &&
1653 !tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &val
))
1654 tg3_writephy(tp
, MII_TG3_AUX_CTRL
,
1655 (val
| (1 << 15) | (1 << 4)));
1658 static void tg3_phy_apply_otp(struct tg3
*tp
)
1667 /* Enable SM_DSP clock and tx 6dB coding. */
1668 phy
= MII_TG3_AUXCTL_SHDWSEL_AUXCTL
|
1669 MII_TG3_AUXCTL_ACTL_SMDSP_ENA
|
1670 MII_TG3_AUXCTL_ACTL_TX_6DB
;
1671 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy
);
1673 phy
= ((otp
& TG3_OTP_AGCTGT_MASK
) >> TG3_OTP_AGCTGT_SHIFT
);
1674 phy
|= MII_TG3_DSP_TAP1_AGCTGT_DFLT
;
1675 tg3_phydsp_write(tp
, MII_TG3_DSP_TAP1
, phy
);
1677 phy
= ((otp
& TG3_OTP_HPFFLTR_MASK
) >> TG3_OTP_HPFFLTR_SHIFT
) |
1678 ((otp
& TG3_OTP_HPFOVER_MASK
) >> TG3_OTP_HPFOVER_SHIFT
);
1679 tg3_phydsp_write(tp
, MII_TG3_DSP_AADJ1CH0
, phy
);
1681 phy
= ((otp
& TG3_OTP_LPFDIS_MASK
) >> TG3_OTP_LPFDIS_SHIFT
);
1682 phy
|= MII_TG3_DSP_AADJ1CH3_ADCCKADJ
;
1683 tg3_phydsp_write(tp
, MII_TG3_DSP_AADJ1CH3
, phy
);
1685 phy
= ((otp
& TG3_OTP_VDAC_MASK
) >> TG3_OTP_VDAC_SHIFT
);
1686 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP75
, phy
);
1688 phy
= ((otp
& TG3_OTP_10BTAMP_MASK
) >> TG3_OTP_10BTAMP_SHIFT
);
1689 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP96
, phy
);
1691 phy
= ((otp
& TG3_OTP_ROFF_MASK
) >> TG3_OTP_ROFF_SHIFT
) |
1692 ((otp
& TG3_OTP_RCOFF_MASK
) >> TG3_OTP_RCOFF_SHIFT
);
1693 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP97
, phy
);
1695 /* Turn off SM_DSP clock. */
1696 phy
= MII_TG3_AUXCTL_SHDWSEL_AUXCTL
|
1697 MII_TG3_AUXCTL_ACTL_TX_6DB
;
1698 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy
);
1701 static int tg3_wait_macro_done(struct tg3
*tp
)
1708 if (!tg3_readphy(tp
, MII_TG3_DSP_CONTROL
, &tmp32
)) {
1709 if ((tmp32
& 0x1000) == 0)
1719 static int tg3_phy_write_and_check_testpat(struct tg3
*tp
, int *resetp
)
1721 static const u32 test_pat
[4][6] = {
1722 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1723 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1724 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1725 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1729 for (chan
= 0; chan
< 4; chan
++) {
1732 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
1733 (chan
* 0x2000) | 0x0200);
1734 tg3_writephy(tp
, MII_TG3_DSP_CONTROL
, 0x0002);
1736 for (i
= 0; i
< 6; i
++)
1737 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
,
1740 tg3_writephy(tp
, MII_TG3_DSP_CONTROL
, 0x0202);
1741 if (tg3_wait_macro_done(tp
)) {
1746 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
1747 (chan
* 0x2000) | 0x0200);
1748 tg3_writephy(tp
, MII_TG3_DSP_CONTROL
, 0x0082);
1749 if (tg3_wait_macro_done(tp
)) {
1754 tg3_writephy(tp
, MII_TG3_DSP_CONTROL
, 0x0802);
1755 if (tg3_wait_macro_done(tp
)) {
1760 for (i
= 0; i
< 6; i
+= 2) {
1763 if (tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &low
) ||
1764 tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &high
) ||
1765 tg3_wait_macro_done(tp
)) {
1771 if (low
!= test_pat
[chan
][i
] ||
1772 high
!= test_pat
[chan
][i
+1]) {
1773 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x000b);
1774 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x4001);
1775 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x4005);
1785 static int tg3_phy_reset_chanpat(struct tg3
*tp
)
1789 for (chan
= 0; chan
< 4; chan
++) {
1792 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
1793 (chan
* 0x2000) | 0x0200);
1794 tg3_writephy(tp
, MII_TG3_DSP_CONTROL
, 0x0002);
1795 for (i
= 0; i
< 6; i
++)
1796 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x000);
1797 tg3_writephy(tp
, MII_TG3_DSP_CONTROL
, 0x0202);
1798 if (tg3_wait_macro_done(tp
))
1805 static int tg3_phy_reset_5703_4_5(struct tg3
*tp
)
1807 u32 reg32
, phy9_orig
;
1808 int retries
, do_phy_reset
, err
;
1814 err
= tg3_bmcr_reset(tp
);
1820 /* Disable transmitter and interrupt. */
1821 if (tg3_readphy(tp
, MII_TG3_EXT_CTRL
, ®32
))
1825 tg3_writephy(tp
, MII_TG3_EXT_CTRL
, reg32
);
1827 /* Set full-duplex, 1000 mbps. */
1828 tg3_writephy(tp
, MII_BMCR
,
1829 BMCR_FULLDPLX
| TG3_BMCR_SPEED1000
);
1831 /* Set to master mode. */
1832 if (tg3_readphy(tp
, MII_TG3_CTRL
, &phy9_orig
))
1835 tg3_writephy(tp
, MII_TG3_CTRL
,
1836 (MII_TG3_CTRL_AS_MASTER
|
1837 MII_TG3_CTRL_ENABLE_AS_MASTER
));
1839 /* Enable SM_DSP_CLOCK and 6dB. */
1840 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
1842 /* Block the PHY control access. */
1843 tg3_phydsp_write(tp
, 0x8005, 0x0800);
1845 err
= tg3_phy_write_and_check_testpat(tp
, &do_phy_reset
);
1848 } while (--retries
);
1850 err
= tg3_phy_reset_chanpat(tp
);
1854 tg3_phydsp_write(tp
, 0x8005, 0x0000);
1856 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8200);
1857 tg3_writephy(tp
, MII_TG3_DSP_CONTROL
, 0x0000);
1859 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
1860 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
1861 /* Set Extended packet length bit for jumbo frames */
1862 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4400);
1864 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
1867 tg3_writephy(tp
, MII_TG3_CTRL
, phy9_orig
);
1869 if (!tg3_readphy(tp
, MII_TG3_EXT_CTRL
, ®32
)) {
1871 tg3_writephy(tp
, MII_TG3_EXT_CTRL
, reg32
);
1878 /* This will reset the tigon3 PHY if there is no valid
1879 * link unless the FORCE argument is non-zero.
1881 static int tg3_phy_reset(struct tg3
*tp
)
1886 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
1887 val
= tr32(GRC_MISC_CFG
);
1888 tw32_f(GRC_MISC_CFG
, val
& ~GRC_MISC_CFG_EPHY_IDDQ
);
1891 err
= tg3_readphy(tp
, MII_BMSR
, &val
);
1892 err
|= tg3_readphy(tp
, MII_BMSR
, &val
);
1896 if (netif_running(tp
->dev
) && netif_carrier_ok(tp
->dev
)) {
1897 netif_carrier_off(tp
->dev
);
1898 tg3_link_report(tp
);
1901 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
1902 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
1903 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
1904 err
= tg3_phy_reset_5703_4_5(tp
);
1911 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
1912 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
) {
1913 cpmuctrl
= tr32(TG3_CPMU_CTRL
);
1914 if (cpmuctrl
& CPMU_CTRL_GPHY_10MB_RXONLY
)
1916 cpmuctrl
& ~CPMU_CTRL_GPHY_10MB_RXONLY
);
1919 err
= tg3_bmcr_reset(tp
);
1923 if (cpmuctrl
& CPMU_CTRL_GPHY_10MB_RXONLY
) {
1924 val
= MII_TG3_DSP_EXP8_AEDW
| MII_TG3_DSP_EXP8_REJ2MHz
;
1925 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP8
, val
);
1927 tw32(TG3_CPMU_CTRL
, cpmuctrl
);
1930 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
||
1931 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5761_AX
) {
1932 val
= tr32(TG3_CPMU_LSPD_1000MB_CLK
);
1933 if ((val
& CPMU_LSPD_1000MB_MACCLK_MASK
) ==
1934 CPMU_LSPD_1000MB_MACCLK_12_5
) {
1935 val
&= ~CPMU_LSPD_1000MB_MACCLK_MASK
;
1937 tw32_f(TG3_CPMU_LSPD_1000MB_CLK
, val
);
1941 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
1942 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
) &&
1943 (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
))
1946 tg3_phy_apply_otp(tp
);
1948 if (tp
->phy_flags
& TG3_PHYFLG_ENABLE_APD
)
1949 tg3_phy_toggle_apd(tp
, true);
1951 tg3_phy_toggle_apd(tp
, false);
1954 if (tp
->phy_flags
& TG3_PHYFLG_ADC_BUG
) {
1955 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
1956 tg3_phydsp_write(tp
, 0x201f, 0x2aaa);
1957 tg3_phydsp_write(tp
, 0x000a, 0x0323);
1958 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
1960 if (tp
->phy_flags
& TG3_PHYFLG_5704_A0_BUG
) {
1961 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, 0x8d68);
1962 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, 0x8d68);
1964 if (tp
->phy_flags
& TG3_PHYFLG_BER_BUG
) {
1965 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
1966 tg3_phydsp_write(tp
, 0x000a, 0x310b);
1967 tg3_phydsp_write(tp
, 0x201f, 0x9506);
1968 tg3_phydsp_write(tp
, 0x401f, 0x14e2);
1969 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
1970 } else if (tp
->phy_flags
& TG3_PHYFLG_JITTER_BUG
) {
1971 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
1972 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x000a);
1973 if (tp
->phy_flags
& TG3_PHYFLG_ADJUST_TRIM
) {
1974 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x110b);
1975 tg3_writephy(tp
, MII_TG3_TEST1
,
1976 MII_TG3_TEST1_TRIM_EN
| 0x4);
1978 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x010b);
1979 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
1981 /* Set Extended packet length bit (bit 14) on all chips that */
1982 /* support jumbo frames */
1983 if ((tp
->phy_id
& TG3_PHY_ID_MASK
) == TG3_PHY_ID_BCM5401
) {
1984 /* Cannot do read-modify-write on 5401 */
1985 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4c20);
1986 } else if (tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) {
1987 /* Set bit 14 with read-modify-write to preserve other bits */
1988 if (!tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0007) &&
1989 !tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &val
))
1990 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, val
| 0x4000);
1993 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1994 * jumbo frames transmission.
1996 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) {
1997 if (!tg3_readphy(tp
, MII_TG3_EXT_CTRL
, &val
))
1998 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
1999 val
| MII_TG3_EXT_CTRL_FIFO_ELASTIC
);
2002 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
2003 /* adjust output voltage */
2004 tg3_writephy(tp
, MII_TG3_FET_PTEST
, 0x12);
2007 tg3_phy_toggle_automdix(tp
, 1);
2008 tg3_phy_set_wirespeed(tp
);
2012 static void tg3_frob_aux_power(struct tg3
*tp
)
2014 struct tg3
*tp_peer
= tp
;
2016 /* The GPIOs do something completely different on 57765. */
2017 if ((tp
->tg3_flags2
& TG3_FLG2_IS_NIC
) == 0 ||
2018 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
||
2019 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
2022 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
2023 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
||
2024 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
) {
2025 struct net_device
*dev_peer
;
2027 dev_peer
= pci_get_drvdata(tp
->pdev_peer
);
2028 /* remove_one() may have been run on the peer. */
2032 tp_peer
= netdev_priv(dev_peer
);
2035 if ((tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
) != 0 ||
2036 (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) != 0 ||
2037 (tp_peer
->tg3_flags
& TG3_FLAG_WOL_ENABLE
) != 0 ||
2038 (tp_peer
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) != 0) {
2039 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2040 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
2041 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2042 (GRC_LCLCTRL_GPIO_OE0
|
2043 GRC_LCLCTRL_GPIO_OE1
|
2044 GRC_LCLCTRL_GPIO_OE2
|
2045 GRC_LCLCTRL_GPIO_OUTPUT0
|
2046 GRC_LCLCTRL_GPIO_OUTPUT1
),
2048 } else if (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5761
||
2049 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5761S
) {
2050 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2051 u32 grc_local_ctrl
= GRC_LCLCTRL_GPIO_OE0
|
2052 GRC_LCLCTRL_GPIO_OE1
|
2053 GRC_LCLCTRL_GPIO_OE2
|
2054 GRC_LCLCTRL_GPIO_OUTPUT0
|
2055 GRC_LCLCTRL_GPIO_OUTPUT1
|
2057 tw32_wait_f(GRC_LOCAL_CTRL
, grc_local_ctrl
, 100);
2059 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OUTPUT2
;
2060 tw32_wait_f(GRC_LOCAL_CTRL
, grc_local_ctrl
, 100);
2062 grc_local_ctrl
&= ~GRC_LCLCTRL_GPIO_OUTPUT0
;
2063 tw32_wait_f(GRC_LOCAL_CTRL
, grc_local_ctrl
, 100);
2066 u32 grc_local_ctrl
= 0;
2068 if (tp_peer
!= tp
&&
2069 (tp_peer
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
) != 0)
2072 /* Workaround to prevent overdrawing Amps. */
2073 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
2075 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE3
;
2076 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2077 grc_local_ctrl
, 100);
2080 /* On 5753 and variants, GPIO2 cannot be used. */
2081 no_gpio2
= tp
->nic_sram_data_cfg
&
2082 NIC_SRAM_DATA_CFG_NO_GPIO2
;
2084 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE0
|
2085 GRC_LCLCTRL_GPIO_OE1
|
2086 GRC_LCLCTRL_GPIO_OE2
|
2087 GRC_LCLCTRL_GPIO_OUTPUT1
|
2088 GRC_LCLCTRL_GPIO_OUTPUT2
;
2090 grc_local_ctrl
&= ~(GRC_LCLCTRL_GPIO_OE2
|
2091 GRC_LCLCTRL_GPIO_OUTPUT2
);
2093 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2094 grc_local_ctrl
, 100);
2096 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OUTPUT0
;
2098 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2099 grc_local_ctrl
, 100);
2102 grc_local_ctrl
&= ~GRC_LCLCTRL_GPIO_OUTPUT2
;
2103 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2104 grc_local_ctrl
, 100);
2108 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
2109 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
) {
2110 if (tp_peer
!= tp
&&
2111 (tp_peer
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
) != 0)
2114 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2115 (GRC_LCLCTRL_GPIO_OE1
|
2116 GRC_LCLCTRL_GPIO_OUTPUT1
), 100);
2118 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2119 GRC_LCLCTRL_GPIO_OE1
, 100);
2121 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2122 (GRC_LCLCTRL_GPIO_OE1
|
2123 GRC_LCLCTRL_GPIO_OUTPUT1
), 100);
2128 static int tg3_5700_link_polarity(struct tg3
*tp
, u32 speed
)
2130 if (tp
->led_ctrl
== LED_CTRL_MODE_PHY_2
)
2132 else if ((tp
->phy_id
& TG3_PHY_ID_MASK
) == TG3_PHY_ID_BCM5411
) {
2133 if (speed
!= SPEED_10
)
2135 } else if (speed
== SPEED_10
)
2141 static int tg3_setup_phy(struct tg3
*, int);
2143 #define RESET_KIND_SHUTDOWN 0
2144 #define RESET_KIND_INIT 1
2145 #define RESET_KIND_SUSPEND 2
2147 static void tg3_write_sig_post_reset(struct tg3
*, int);
2148 static int tg3_halt_cpu(struct tg3
*, u32
);
2150 static void tg3_power_down_phy(struct tg3
*tp
, bool do_low_power
)
2154 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) {
2155 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
2156 u32 sg_dig_ctrl
= tr32(SG_DIG_CTRL
);
2157 u32 serdes_cfg
= tr32(MAC_SERDES_CFG
);
2160 SG_DIG_USING_HW_AUTONEG
| SG_DIG_SOFT_RESET
;
2161 tw32(SG_DIG_CTRL
, sg_dig_ctrl
);
2162 tw32(MAC_SERDES_CFG
, serdes_cfg
| (1 << 15));
2167 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
2169 val
= tr32(GRC_MISC_CFG
);
2170 tw32_f(GRC_MISC_CFG
, val
| GRC_MISC_CFG_EPHY_IDDQ
);
2173 } else if (tp
->phy_flags
& TG3_PHYFLG_IS_FET
) {
2175 if (!tg3_readphy(tp
, MII_TG3_FET_TEST
, &phytest
)) {
2178 tg3_writephy(tp
, MII_ADVERTISE
, 0);
2179 tg3_writephy(tp
, MII_BMCR
,
2180 BMCR_ANENABLE
| BMCR_ANRESTART
);
2182 tg3_writephy(tp
, MII_TG3_FET_TEST
,
2183 phytest
| MII_TG3_FET_SHADOW_EN
);
2184 if (!tg3_readphy(tp
, MII_TG3_FET_SHDW_AUXMODE4
, &phy
)) {
2185 phy
|= MII_TG3_FET_SHDW_AUXMODE4_SBPD
;
2187 MII_TG3_FET_SHDW_AUXMODE4
,
2190 tg3_writephy(tp
, MII_TG3_FET_TEST
, phytest
);
2193 } else if (do_low_power
) {
2194 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
2195 MII_TG3_EXT_CTRL_FORCE_LED_OFF
);
2197 tg3_writephy(tp
, MII_TG3_AUX_CTRL
,
2198 MII_TG3_AUXCTL_SHDWSEL_PWRCTL
|
2199 MII_TG3_AUXCTL_PCTL_100TX_LPWR
|
2200 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE
|
2201 MII_TG3_AUXCTL_PCTL_VREG_11V
);
2204 /* The PHY should not be powered down on some chips because
2207 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2208 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
2209 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5780
&&
2210 (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
)))
2213 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
||
2214 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5761_AX
) {
2215 val
= tr32(TG3_CPMU_LSPD_1000MB_CLK
);
2216 val
&= ~CPMU_LSPD_1000MB_MACCLK_MASK
;
2217 val
|= CPMU_LSPD_1000MB_MACCLK_12_5
;
2218 tw32_f(TG3_CPMU_LSPD_1000MB_CLK
, val
);
2221 tg3_writephy(tp
, MII_BMCR
, BMCR_PDOWN
);
2224 /* tp->lock is held. */
2225 static int tg3_nvram_lock(struct tg3
*tp
)
2227 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
) {
2230 if (tp
->nvram_lock_cnt
== 0) {
2231 tw32(NVRAM_SWARB
, SWARB_REQ_SET1
);
2232 for (i
= 0; i
< 8000; i
++) {
2233 if (tr32(NVRAM_SWARB
) & SWARB_GNT1
)
2238 tw32(NVRAM_SWARB
, SWARB_REQ_CLR1
);
2242 tp
->nvram_lock_cnt
++;
2247 /* tp->lock is held. */
2248 static void tg3_nvram_unlock(struct tg3
*tp
)
2250 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
) {
2251 if (tp
->nvram_lock_cnt
> 0)
2252 tp
->nvram_lock_cnt
--;
2253 if (tp
->nvram_lock_cnt
== 0)
2254 tw32_f(NVRAM_SWARB
, SWARB_REQ_CLR1
);
2258 /* tp->lock is held. */
2259 static void tg3_enable_nvram_access(struct tg3
*tp
)
2261 if ((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
2262 !(tp
->tg3_flags3
& TG3_FLG3_PROTECTED_NVRAM
)) {
2263 u32 nvaccess
= tr32(NVRAM_ACCESS
);
2265 tw32(NVRAM_ACCESS
, nvaccess
| ACCESS_ENABLE
);
2269 /* tp->lock is held. */
2270 static void tg3_disable_nvram_access(struct tg3
*tp
)
2272 if ((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
2273 !(tp
->tg3_flags3
& TG3_FLG3_PROTECTED_NVRAM
)) {
2274 u32 nvaccess
= tr32(NVRAM_ACCESS
);
2276 tw32(NVRAM_ACCESS
, nvaccess
& ~ACCESS_ENABLE
);
2280 static int tg3_nvram_read_using_eeprom(struct tg3
*tp
,
2281 u32 offset
, u32
*val
)
2286 if (offset
> EEPROM_ADDR_ADDR_MASK
|| (offset
% 4) != 0)
2289 tmp
= tr32(GRC_EEPROM_ADDR
) & ~(EEPROM_ADDR_ADDR_MASK
|
2290 EEPROM_ADDR_DEVID_MASK
|
2292 tw32(GRC_EEPROM_ADDR
,
2294 (0 << EEPROM_ADDR_DEVID_SHIFT
) |
2295 ((offset
<< EEPROM_ADDR_ADDR_SHIFT
) &
2296 EEPROM_ADDR_ADDR_MASK
) |
2297 EEPROM_ADDR_READ
| EEPROM_ADDR_START
);
2299 for (i
= 0; i
< 1000; i
++) {
2300 tmp
= tr32(GRC_EEPROM_ADDR
);
2302 if (tmp
& EEPROM_ADDR_COMPLETE
)
2306 if (!(tmp
& EEPROM_ADDR_COMPLETE
))
2309 tmp
= tr32(GRC_EEPROM_DATA
);
2312 * The data will always be opposite the native endian
2313 * format. Perform a blind byteswap to compensate.
2320 #define NVRAM_CMD_TIMEOUT 10000
2322 static int tg3_nvram_exec_cmd(struct tg3
*tp
, u32 nvram_cmd
)
2326 tw32(NVRAM_CMD
, nvram_cmd
);
2327 for (i
= 0; i
< NVRAM_CMD_TIMEOUT
; i
++) {
2329 if (tr32(NVRAM_CMD
) & NVRAM_CMD_DONE
) {
2335 if (i
== NVRAM_CMD_TIMEOUT
)
2341 static u32
tg3_nvram_phys_addr(struct tg3
*tp
, u32 addr
)
2343 if ((tp
->tg3_flags
& TG3_FLAG_NVRAM
) &&
2344 (tp
->tg3_flags
& TG3_FLAG_NVRAM_BUFFERED
) &&
2345 (tp
->tg3_flags2
& TG3_FLG2_FLASH
) &&
2346 !(tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM_ADDR_TRANS
) &&
2347 (tp
->nvram_jedecnum
== JEDEC_ATMEL
))
2349 addr
= ((addr
/ tp
->nvram_pagesize
) <<
2350 ATMEL_AT45DB0X1B_PAGE_POS
) +
2351 (addr
% tp
->nvram_pagesize
);
2356 static u32
tg3_nvram_logical_addr(struct tg3
*tp
, u32 addr
)
2358 if ((tp
->tg3_flags
& TG3_FLAG_NVRAM
) &&
2359 (tp
->tg3_flags
& TG3_FLAG_NVRAM_BUFFERED
) &&
2360 (tp
->tg3_flags2
& TG3_FLG2_FLASH
) &&
2361 !(tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM_ADDR_TRANS
) &&
2362 (tp
->nvram_jedecnum
== JEDEC_ATMEL
))
2364 addr
= ((addr
>> ATMEL_AT45DB0X1B_PAGE_POS
) *
2365 tp
->nvram_pagesize
) +
2366 (addr
& ((1 << ATMEL_AT45DB0X1B_PAGE_POS
) - 1));
2371 /* NOTE: Data read in from NVRAM is byteswapped according to
2372 * the byteswapping settings for all other register accesses.
2373 * tg3 devices are BE devices, so on a BE machine, the data
2374 * returned will be exactly as it is seen in NVRAM. On a LE
2375 * machine, the 32-bit value will be byteswapped.
2377 static int tg3_nvram_read(struct tg3
*tp
, u32 offset
, u32
*val
)
2381 if (!(tp
->tg3_flags
& TG3_FLAG_NVRAM
))
2382 return tg3_nvram_read_using_eeprom(tp
, offset
, val
);
2384 offset
= tg3_nvram_phys_addr(tp
, offset
);
2386 if (offset
> NVRAM_ADDR_MSK
)
2389 ret
= tg3_nvram_lock(tp
);
2393 tg3_enable_nvram_access(tp
);
2395 tw32(NVRAM_ADDR
, offset
);
2396 ret
= tg3_nvram_exec_cmd(tp
, NVRAM_CMD_RD
| NVRAM_CMD_GO
|
2397 NVRAM_CMD_FIRST
| NVRAM_CMD_LAST
| NVRAM_CMD_DONE
);
2400 *val
= tr32(NVRAM_RDDATA
);
2402 tg3_disable_nvram_access(tp
);
2404 tg3_nvram_unlock(tp
);
2409 /* Ensures NVRAM data is in bytestream format. */
2410 static int tg3_nvram_read_be32(struct tg3
*tp
, u32 offset
, __be32
*val
)
2413 int res
= tg3_nvram_read(tp
, offset
, &v
);
2415 *val
= cpu_to_be32(v
);
2419 /* tp->lock is held. */
2420 static void __tg3_set_mac_addr(struct tg3
*tp
, int skip_mac_1
)
2422 u32 addr_high
, addr_low
;
2425 addr_high
= ((tp
->dev
->dev_addr
[0] << 8) |
2426 tp
->dev
->dev_addr
[1]);
2427 addr_low
= ((tp
->dev
->dev_addr
[2] << 24) |
2428 (tp
->dev
->dev_addr
[3] << 16) |
2429 (tp
->dev
->dev_addr
[4] << 8) |
2430 (tp
->dev
->dev_addr
[5] << 0));
2431 for (i
= 0; i
< 4; i
++) {
2432 if (i
== 1 && skip_mac_1
)
2434 tw32(MAC_ADDR_0_HIGH
+ (i
* 8), addr_high
);
2435 tw32(MAC_ADDR_0_LOW
+ (i
* 8), addr_low
);
2438 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
2439 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
2440 for (i
= 0; i
< 12; i
++) {
2441 tw32(MAC_EXTADDR_0_HIGH
+ (i
* 8), addr_high
);
2442 tw32(MAC_EXTADDR_0_LOW
+ (i
* 8), addr_low
);
2446 addr_high
= (tp
->dev
->dev_addr
[0] +
2447 tp
->dev
->dev_addr
[1] +
2448 tp
->dev
->dev_addr
[2] +
2449 tp
->dev
->dev_addr
[3] +
2450 tp
->dev
->dev_addr
[4] +
2451 tp
->dev
->dev_addr
[5]) &
2452 TX_BACKOFF_SEED_MASK
;
2453 tw32(MAC_TX_BACKOFF_SEED
, addr_high
);
2456 static int tg3_set_power_state(struct tg3
*tp
, pci_power_t state
)
2459 bool device_should_wake
, do_low_power
;
2461 /* Make sure register accesses (indirect or otherwise)
2462 * will function correctly.
2464 pci_write_config_dword(tp
->pdev
,
2465 TG3PCI_MISC_HOST_CTRL
,
2466 tp
->misc_host_ctrl
);
2470 pci_enable_wake(tp
->pdev
, state
, false);
2471 pci_set_power_state(tp
->pdev
, PCI_D0
);
2473 /* Switch out of Vaux if it is a NIC */
2474 if (tp
->tg3_flags2
& TG3_FLG2_IS_NIC
)
2475 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
, 100);
2485 netdev_err(tp
->dev
, "Invalid power state (D%d) requested\n",
2490 /* Restore the CLKREQ setting. */
2491 if (tp
->tg3_flags3
& TG3_FLG3_CLKREQ_BUG
) {
2494 pci_read_config_word(tp
->pdev
,
2495 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
2497 lnkctl
|= PCI_EXP_LNKCTL_CLKREQ_EN
;
2498 pci_write_config_word(tp
->pdev
,
2499 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
2503 misc_host_ctrl
= tr32(TG3PCI_MISC_HOST_CTRL
);
2504 tw32(TG3PCI_MISC_HOST_CTRL
,
2505 misc_host_ctrl
| MISC_HOST_CTRL_MASK_PCI_INT
);
2507 device_should_wake
= pci_pme_capable(tp
->pdev
, state
) &&
2508 device_may_wakeup(&tp
->pdev
->dev
) &&
2509 (tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
);
2511 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
2512 do_low_power
= false;
2513 if ((tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
) &&
2514 !(tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)) {
2515 struct phy_device
*phydev
;
2516 u32 phyid
, advertising
;
2518 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
2520 tp
->phy_flags
|= TG3_PHYFLG_IS_LOW_POWER
;
2522 tp
->link_config
.orig_speed
= phydev
->speed
;
2523 tp
->link_config
.orig_duplex
= phydev
->duplex
;
2524 tp
->link_config
.orig_autoneg
= phydev
->autoneg
;
2525 tp
->link_config
.orig_advertising
= phydev
->advertising
;
2527 advertising
= ADVERTISED_TP
|
2529 ADVERTISED_Autoneg
|
2530 ADVERTISED_10baseT_Half
;
2532 if ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) ||
2533 device_should_wake
) {
2534 if (tp
->tg3_flags
& TG3_FLAG_WOL_SPEED_100MB
)
2536 ADVERTISED_100baseT_Half
|
2537 ADVERTISED_100baseT_Full
|
2538 ADVERTISED_10baseT_Full
;
2540 advertising
|= ADVERTISED_10baseT_Full
;
2543 phydev
->advertising
= advertising
;
2545 phy_start_aneg(phydev
);
2547 phyid
= phydev
->drv
->phy_id
& phydev
->drv
->phy_id_mask
;
2548 if (phyid
!= PHY_ID_BCMAC131
) {
2549 phyid
&= PHY_BCM_OUI_MASK
;
2550 if (phyid
== PHY_BCM_OUI_1
||
2551 phyid
== PHY_BCM_OUI_2
||
2552 phyid
== PHY_BCM_OUI_3
)
2553 do_low_power
= true;
2557 do_low_power
= true;
2559 if (!(tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)) {
2560 tp
->phy_flags
|= TG3_PHYFLG_IS_LOW_POWER
;
2561 tp
->link_config
.orig_speed
= tp
->link_config
.speed
;
2562 tp
->link_config
.orig_duplex
= tp
->link_config
.duplex
;
2563 tp
->link_config
.orig_autoneg
= tp
->link_config
.autoneg
;
2566 if (!(tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
)) {
2567 tp
->link_config
.speed
= SPEED_10
;
2568 tp
->link_config
.duplex
= DUPLEX_HALF
;
2569 tp
->link_config
.autoneg
= AUTONEG_ENABLE
;
2570 tg3_setup_phy(tp
, 0);
2574 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
2577 val
= tr32(GRC_VCPU_EXT_CTRL
);
2578 tw32(GRC_VCPU_EXT_CTRL
, val
| GRC_VCPU_EXT_CTRL_DISABLE_WOL
);
2579 } else if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)) {
2583 for (i
= 0; i
< 200; i
++) {
2584 tg3_read_mem(tp
, NIC_SRAM_FW_ASF_STATUS_MBOX
, &val
);
2585 if (val
== ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1
)
2590 if (tp
->tg3_flags
& TG3_FLAG_WOL_CAP
)
2591 tg3_write_mem(tp
, NIC_SRAM_WOL_MBOX
, WOL_SIGNATURE
|
2592 WOL_DRV_STATE_SHUTDOWN
|
2596 if (device_should_wake
) {
2599 if (!(tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
)) {
2601 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x5a);
2605 if (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
)
2606 mac_mode
= MAC_MODE_PORT_MODE_GMII
;
2608 mac_mode
= MAC_MODE_PORT_MODE_MII
;
2610 mac_mode
|= tp
->mac_mode
& MAC_MODE_LINK_POLARITY
;
2611 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
2613 u32 speed
= (tp
->tg3_flags
&
2614 TG3_FLAG_WOL_SPEED_100MB
) ?
2615 SPEED_100
: SPEED_10
;
2616 if (tg3_5700_link_polarity(tp
, speed
))
2617 mac_mode
|= MAC_MODE_LINK_POLARITY
;
2619 mac_mode
&= ~MAC_MODE_LINK_POLARITY
;
2622 mac_mode
= MAC_MODE_PORT_MODE_TBI
;
2625 if (!(tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
))
2626 tw32(MAC_LED_CTRL
, tp
->led_ctrl
);
2628 mac_mode
|= MAC_MODE_MAGIC_PKT_ENABLE
;
2629 if (((tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
2630 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) &&
2631 ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) ||
2632 (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)))
2633 mac_mode
|= MAC_MODE_KEEP_FRAME_IN_WOL
;
2635 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
2636 mac_mode
|= tp
->mac_mode
&
2637 (MAC_MODE_APE_TX_EN
| MAC_MODE_APE_RX_EN
);
2638 if (mac_mode
& MAC_MODE_APE_TX_EN
)
2639 mac_mode
|= MAC_MODE_TDE_ENABLE
;
2642 tw32_f(MAC_MODE
, mac_mode
);
2645 tw32_f(MAC_RX_MODE
, RX_MODE_ENABLE
);
2649 if (!(tp
->tg3_flags
& TG3_FLAG_WOL_SPEED_100MB
) &&
2650 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2651 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)) {
2654 base_val
= tp
->pci_clock_ctrl
;
2655 base_val
|= (CLOCK_CTRL_RXCLK_DISABLE
|
2656 CLOCK_CTRL_TXCLK_DISABLE
);
2658 tw32_wait_f(TG3PCI_CLOCK_CTRL
, base_val
| CLOCK_CTRL_ALTCLK
|
2659 CLOCK_CTRL_PWRDOWN_PLL133
, 40);
2660 } else if ((tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) ||
2661 (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) ||
2662 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)) {
2664 } else if (!((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
2665 (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))) {
2666 u32 newbits1
, newbits2
;
2668 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2669 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
2670 newbits1
= (CLOCK_CTRL_RXCLK_DISABLE
|
2671 CLOCK_CTRL_TXCLK_DISABLE
|
2673 newbits2
= newbits1
| CLOCK_CTRL_44MHZ_CORE
;
2674 } else if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
2675 newbits1
= CLOCK_CTRL_625_CORE
;
2676 newbits2
= newbits1
| CLOCK_CTRL_ALTCLK
;
2678 newbits1
= CLOCK_CTRL_ALTCLK
;
2679 newbits2
= newbits1
| CLOCK_CTRL_44MHZ_CORE
;
2682 tw32_wait_f(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
| newbits1
,
2685 tw32_wait_f(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
| newbits2
,
2688 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
2691 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2692 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
2693 newbits3
= (CLOCK_CTRL_RXCLK_DISABLE
|
2694 CLOCK_CTRL_TXCLK_DISABLE
|
2695 CLOCK_CTRL_44MHZ_CORE
);
2697 newbits3
= CLOCK_CTRL_44MHZ_CORE
;
2700 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
2701 tp
->pci_clock_ctrl
| newbits3
, 40);
2705 if (!(device_should_wake
) &&
2706 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
2707 tg3_power_down_phy(tp
, do_low_power
);
2709 tg3_frob_aux_power(tp
);
2711 /* Workaround for unstable PLL clock */
2712 if ((GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_AX
) ||
2713 (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_BX
)) {
2714 u32 val
= tr32(0x7d00);
2716 val
&= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2718 if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)) {
2721 err
= tg3_nvram_lock(tp
);
2722 tg3_halt_cpu(tp
, RX_CPU_BASE
);
2724 tg3_nvram_unlock(tp
);
2728 tg3_write_sig_post_reset(tp
, RESET_KIND_SHUTDOWN
);
2730 if (device_should_wake
)
2731 pci_enable_wake(tp
->pdev
, state
, true);
2733 /* Finally, set the new power state. */
2734 pci_set_power_state(tp
->pdev
, state
);
2739 static void tg3_aux_stat_to_speed_duplex(struct tg3
*tp
, u32 val
, u16
*speed
, u8
*duplex
)
2741 switch (val
& MII_TG3_AUX_STAT_SPDMASK
) {
2742 case MII_TG3_AUX_STAT_10HALF
:
2744 *duplex
= DUPLEX_HALF
;
2747 case MII_TG3_AUX_STAT_10FULL
:
2749 *duplex
= DUPLEX_FULL
;
2752 case MII_TG3_AUX_STAT_100HALF
:
2754 *duplex
= DUPLEX_HALF
;
2757 case MII_TG3_AUX_STAT_100FULL
:
2759 *duplex
= DUPLEX_FULL
;
2762 case MII_TG3_AUX_STAT_1000HALF
:
2763 *speed
= SPEED_1000
;
2764 *duplex
= DUPLEX_HALF
;
2767 case MII_TG3_AUX_STAT_1000FULL
:
2768 *speed
= SPEED_1000
;
2769 *duplex
= DUPLEX_FULL
;
2773 if (tp
->phy_flags
& TG3_PHYFLG_IS_FET
) {
2774 *speed
= (val
& MII_TG3_AUX_STAT_100
) ? SPEED_100
:
2776 *duplex
= (val
& MII_TG3_AUX_STAT_FULL
) ? DUPLEX_FULL
:
2780 *speed
= SPEED_INVALID
;
2781 *duplex
= DUPLEX_INVALID
;
2786 static void tg3_phy_copper_begin(struct tg3
*tp
)
2791 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
) {
2792 /* Entering low power mode. Disable gigabit and
2793 * 100baseT advertisements.
2795 tg3_writephy(tp
, MII_TG3_CTRL
, 0);
2797 new_adv
= (ADVERTISE_10HALF
| ADVERTISE_10FULL
|
2798 ADVERTISE_CSMA
| ADVERTISE_PAUSE_CAP
);
2799 if (tp
->tg3_flags
& TG3_FLAG_WOL_SPEED_100MB
)
2800 new_adv
|= (ADVERTISE_100HALF
| ADVERTISE_100FULL
);
2802 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
2803 } else if (tp
->link_config
.speed
== SPEED_INVALID
) {
2804 if (tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
)
2805 tp
->link_config
.advertising
&=
2806 ~(ADVERTISED_1000baseT_Half
|
2807 ADVERTISED_1000baseT_Full
);
2809 new_adv
= ADVERTISE_CSMA
;
2810 if (tp
->link_config
.advertising
& ADVERTISED_10baseT_Half
)
2811 new_adv
|= ADVERTISE_10HALF
;
2812 if (tp
->link_config
.advertising
& ADVERTISED_10baseT_Full
)
2813 new_adv
|= ADVERTISE_10FULL
;
2814 if (tp
->link_config
.advertising
& ADVERTISED_100baseT_Half
)
2815 new_adv
|= ADVERTISE_100HALF
;
2816 if (tp
->link_config
.advertising
& ADVERTISED_100baseT_Full
)
2817 new_adv
|= ADVERTISE_100FULL
;
2819 new_adv
|= tg3_advert_flowctrl_1000T(tp
->link_config
.flowctrl
);
2821 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
2823 if (tp
->link_config
.advertising
&
2824 (ADVERTISED_1000baseT_Half
| ADVERTISED_1000baseT_Full
)) {
2826 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Half
)
2827 new_adv
|= MII_TG3_CTRL_ADV_1000_HALF
;
2828 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Full
)
2829 new_adv
|= MII_TG3_CTRL_ADV_1000_FULL
;
2830 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
) &&
2831 (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
2832 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
))
2833 new_adv
|= (MII_TG3_CTRL_AS_MASTER
|
2834 MII_TG3_CTRL_ENABLE_AS_MASTER
);
2835 tg3_writephy(tp
, MII_TG3_CTRL
, new_adv
);
2837 tg3_writephy(tp
, MII_TG3_CTRL
, 0);
2840 new_adv
= tg3_advert_flowctrl_1000T(tp
->link_config
.flowctrl
);
2841 new_adv
|= ADVERTISE_CSMA
;
2843 /* Asking for a specific link mode. */
2844 if (tp
->link_config
.speed
== SPEED_1000
) {
2845 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
2847 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
2848 new_adv
= MII_TG3_CTRL_ADV_1000_FULL
;
2850 new_adv
= MII_TG3_CTRL_ADV_1000_HALF
;
2851 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
2852 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
)
2853 new_adv
|= (MII_TG3_CTRL_AS_MASTER
|
2854 MII_TG3_CTRL_ENABLE_AS_MASTER
);
2856 if (tp
->link_config
.speed
== SPEED_100
) {
2857 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
2858 new_adv
|= ADVERTISE_100FULL
;
2860 new_adv
|= ADVERTISE_100HALF
;
2862 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
2863 new_adv
|= ADVERTISE_10FULL
;
2865 new_adv
|= ADVERTISE_10HALF
;
2867 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
2872 tg3_writephy(tp
, MII_TG3_CTRL
, new_adv
);
2875 if (tp
->link_config
.autoneg
== AUTONEG_DISABLE
&&
2876 tp
->link_config
.speed
!= SPEED_INVALID
) {
2877 u32 bmcr
, orig_bmcr
;
2879 tp
->link_config
.active_speed
= tp
->link_config
.speed
;
2880 tp
->link_config
.active_duplex
= tp
->link_config
.duplex
;
2883 switch (tp
->link_config
.speed
) {
2889 bmcr
|= BMCR_SPEED100
;
2893 bmcr
|= TG3_BMCR_SPEED1000
;
2897 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
2898 bmcr
|= BMCR_FULLDPLX
;
2900 if (!tg3_readphy(tp
, MII_BMCR
, &orig_bmcr
) &&
2901 (bmcr
!= orig_bmcr
)) {
2902 tg3_writephy(tp
, MII_BMCR
, BMCR_LOOPBACK
);
2903 for (i
= 0; i
< 1500; i
++) {
2907 if (tg3_readphy(tp
, MII_BMSR
, &tmp
) ||
2908 tg3_readphy(tp
, MII_BMSR
, &tmp
))
2910 if (!(tmp
& BMSR_LSTATUS
)) {
2915 tg3_writephy(tp
, MII_BMCR
, bmcr
);
2919 tg3_writephy(tp
, MII_BMCR
,
2920 BMCR_ANENABLE
| BMCR_ANRESTART
);
2924 static int tg3_init_5401phy_dsp(struct tg3
*tp
)
2928 /* Turn off tap power management. */
2929 /* Set Extended packet length bit */
2930 err
= tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4c20);
2932 err
|= tg3_phydsp_write(tp
, 0x0012, 0x1804);
2933 err
|= tg3_phydsp_write(tp
, 0x0013, 0x1204);
2934 err
|= tg3_phydsp_write(tp
, 0x8006, 0x0132);
2935 err
|= tg3_phydsp_write(tp
, 0x8006, 0x0232);
2936 err
|= tg3_phydsp_write(tp
, 0x201f, 0x0a20);
2943 static int tg3_copper_is_advertising_all(struct tg3
*tp
, u32 mask
)
2945 u32 adv_reg
, all_mask
= 0;
2947 if (mask
& ADVERTISED_10baseT_Half
)
2948 all_mask
|= ADVERTISE_10HALF
;
2949 if (mask
& ADVERTISED_10baseT_Full
)
2950 all_mask
|= ADVERTISE_10FULL
;
2951 if (mask
& ADVERTISED_100baseT_Half
)
2952 all_mask
|= ADVERTISE_100HALF
;
2953 if (mask
& ADVERTISED_100baseT_Full
)
2954 all_mask
|= ADVERTISE_100FULL
;
2956 if (tg3_readphy(tp
, MII_ADVERTISE
, &adv_reg
))
2959 if ((adv_reg
& all_mask
) != all_mask
)
2961 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
)) {
2965 if (mask
& ADVERTISED_1000baseT_Half
)
2966 all_mask
|= ADVERTISE_1000HALF
;
2967 if (mask
& ADVERTISED_1000baseT_Full
)
2968 all_mask
|= ADVERTISE_1000FULL
;
2970 if (tg3_readphy(tp
, MII_TG3_CTRL
, &tg3_ctrl
))
2973 if ((tg3_ctrl
& all_mask
) != all_mask
)
2979 static int tg3_adv_1000T_flowctrl_ok(struct tg3
*tp
, u32
*lcladv
, u32
*rmtadv
)
2983 if (tg3_readphy(tp
, MII_ADVERTISE
, lcladv
))
2986 curadv
= *lcladv
& (ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
2987 reqadv
= tg3_advert_flowctrl_1000T(tp
->link_config
.flowctrl
);
2989 if (tp
->link_config
.active_duplex
== DUPLEX_FULL
) {
2990 if (curadv
!= reqadv
)
2993 if (tp
->tg3_flags
& TG3_FLAG_PAUSE_AUTONEG
)
2994 tg3_readphy(tp
, MII_LPA
, rmtadv
);
2996 /* Reprogram the advertisement register, even if it
2997 * does not affect the current link. If the link
2998 * gets renegotiated in the future, we can save an
2999 * additional renegotiation cycle by advertising
3000 * it correctly in the first place.
3002 if (curadv
!= reqadv
) {
3003 *lcladv
&= ~(ADVERTISE_PAUSE_CAP
|
3004 ADVERTISE_PAUSE_ASYM
);
3005 tg3_writephy(tp
, MII_ADVERTISE
, *lcladv
| reqadv
);
3012 static int tg3_setup_copper_phy(struct tg3
*tp
, int force_reset
)
3014 int current_link_up
;
3016 u32 lcl_adv
, rmt_adv
;
3024 (MAC_STATUS_SYNC_CHANGED
|
3025 MAC_STATUS_CFG_CHANGED
|
3026 MAC_STATUS_MI_COMPLETION
|
3027 MAC_STATUS_LNKSTATE_CHANGED
));
3030 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
3032 (tp
->mi_mode
& ~MAC_MI_MODE_AUTO_POLL
));
3036 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x02);
3038 /* Some third-party PHYs need to be reset on link going
3041 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
3042 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
3043 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) &&
3044 netif_carrier_ok(tp
->dev
)) {
3045 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3046 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
3047 !(bmsr
& BMSR_LSTATUS
))
3053 if ((tp
->phy_id
& TG3_PHY_ID_MASK
) == TG3_PHY_ID_BCM5401
) {
3054 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3055 if (tg3_readphy(tp
, MII_BMSR
, &bmsr
) ||
3056 !(tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
))
3059 if (!(bmsr
& BMSR_LSTATUS
)) {
3060 err
= tg3_init_5401phy_dsp(tp
);
3064 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3065 for (i
= 0; i
< 1000; i
++) {
3067 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
3068 (bmsr
& BMSR_LSTATUS
)) {
3074 if ((tp
->phy_id
& TG3_PHY_ID_REV_MASK
) ==
3075 TG3_PHY_REV_BCM5401_B0
&&
3076 !(bmsr
& BMSR_LSTATUS
) &&
3077 tp
->link_config
.active_speed
== SPEED_1000
) {
3078 err
= tg3_phy_reset(tp
);
3080 err
= tg3_init_5401phy_dsp(tp
);
3085 } else if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
3086 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
) {
3087 /* 5701 {A0,B0} CRC bug workaround */
3088 tg3_writephy(tp
, 0x15, 0x0a75);
3089 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, 0x8c68);
3090 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, 0x8d68);
3091 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, 0x8c68);
3094 /* Clear pending interrupts... */
3095 tg3_readphy(tp
, MII_TG3_ISTAT
, &val
);
3096 tg3_readphy(tp
, MII_TG3_ISTAT
, &val
);
3098 if (tp
->phy_flags
& TG3_PHYFLG_USE_MI_INTERRUPT
)
3099 tg3_writephy(tp
, MII_TG3_IMASK
, ~MII_TG3_INT_LINKCHG
);
3100 else if (!(tp
->phy_flags
& TG3_PHYFLG_IS_FET
))
3101 tg3_writephy(tp
, MII_TG3_IMASK
, ~0);
3103 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
3104 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
3105 if (tp
->led_ctrl
== LED_CTRL_MODE_PHY_1
)
3106 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
3107 MII_TG3_EXT_CTRL_LNK3_LED_MODE
);
3109 tg3_writephy(tp
, MII_TG3_EXT_CTRL
, 0);
3112 current_link_up
= 0;
3113 current_speed
= SPEED_INVALID
;
3114 current_duplex
= DUPLEX_INVALID
;
3116 if (tp
->phy_flags
& TG3_PHYFLG_CAPACITIVE_COUPLING
) {
3117 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4007);
3118 tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &val
);
3119 if (!(val
& (1 << 10))) {
3121 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, val
);
3127 for (i
= 0; i
< 100; i
++) {
3128 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3129 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
3130 (bmsr
& BMSR_LSTATUS
))
3135 if (bmsr
& BMSR_LSTATUS
) {
3138 tg3_readphy(tp
, MII_TG3_AUX_STAT
, &aux_stat
);
3139 for (i
= 0; i
< 2000; i
++) {
3141 if (!tg3_readphy(tp
, MII_TG3_AUX_STAT
, &aux_stat
) &&
3146 tg3_aux_stat_to_speed_duplex(tp
, aux_stat
,
3151 for (i
= 0; i
< 200; i
++) {
3152 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
3153 if (tg3_readphy(tp
, MII_BMCR
, &bmcr
))
3155 if (bmcr
&& bmcr
!= 0x7fff)
3163 tp
->link_config
.active_speed
= current_speed
;
3164 tp
->link_config
.active_duplex
= current_duplex
;
3166 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) {
3167 if ((bmcr
& BMCR_ANENABLE
) &&
3168 tg3_copper_is_advertising_all(tp
,
3169 tp
->link_config
.advertising
)) {
3170 if (tg3_adv_1000T_flowctrl_ok(tp
, &lcl_adv
,
3172 current_link_up
= 1;
3175 if (!(bmcr
& BMCR_ANENABLE
) &&
3176 tp
->link_config
.speed
== current_speed
&&
3177 tp
->link_config
.duplex
== current_duplex
&&
3178 tp
->link_config
.flowctrl
==
3179 tp
->link_config
.active_flowctrl
) {
3180 current_link_up
= 1;
3184 if (current_link_up
== 1 &&
3185 tp
->link_config
.active_duplex
== DUPLEX_FULL
)
3186 tg3_setup_flow_control(tp
, lcl_adv
, rmt_adv
);
3190 if (current_link_up
== 0 || (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)) {
3191 tg3_phy_copper_begin(tp
);
3193 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3194 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
3195 (bmsr
& BMSR_LSTATUS
))
3196 current_link_up
= 1;
3199 tp
->mac_mode
&= ~MAC_MODE_PORT_MODE_MASK
;
3200 if (current_link_up
== 1) {
3201 if (tp
->link_config
.active_speed
== SPEED_100
||
3202 tp
->link_config
.active_speed
== SPEED_10
)
3203 tp
->mac_mode
|= MAC_MODE_PORT_MODE_MII
;
3205 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
3206 } else if (tp
->phy_flags
& TG3_PHYFLG_IS_FET
)
3207 tp
->mac_mode
|= MAC_MODE_PORT_MODE_MII
;
3209 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
3211 tp
->mac_mode
&= ~MAC_MODE_HALF_DUPLEX
;
3212 if (tp
->link_config
.active_duplex
== DUPLEX_HALF
)
3213 tp
->mac_mode
|= MAC_MODE_HALF_DUPLEX
;
3215 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) {
3216 if (current_link_up
== 1 &&
3217 tg3_5700_link_polarity(tp
, tp
->link_config
.active_speed
))
3218 tp
->mac_mode
|= MAC_MODE_LINK_POLARITY
;
3220 tp
->mac_mode
&= ~MAC_MODE_LINK_POLARITY
;
3223 /* ??? Without this setting Netgear GA302T PHY does not
3224 * ??? send/receive packets...
3226 if ((tp
->phy_id
& TG3_PHY_ID_MASK
) == TG3_PHY_ID_BCM5411
&&
3227 tp
->pci_chip_rev_id
== CHIPREV_ID_5700_ALTIMA
) {
3228 tp
->mi_mode
|= MAC_MI_MODE_AUTO_POLL
;
3229 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
3233 tw32_f(MAC_MODE
, tp
->mac_mode
);
3236 if (tp
->tg3_flags
& TG3_FLAG_USE_LINKCHG_REG
) {
3237 /* Polled via timer. */
3238 tw32_f(MAC_EVENT
, 0);
3240 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
3244 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
&&
3245 current_link_up
== 1 &&
3246 tp
->link_config
.active_speed
== SPEED_1000
&&
3247 ((tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) ||
3248 (tp
->tg3_flags
& TG3_FLAG_PCI_HIGH_SPEED
))) {
3251 (MAC_STATUS_SYNC_CHANGED
|
3252 MAC_STATUS_CFG_CHANGED
));
3255 NIC_SRAM_FIRMWARE_MBOX
,
3256 NIC_SRAM_FIRMWARE_MBOX_MAGIC2
);
3259 /* Prevent send BD corruption. */
3260 if (tp
->tg3_flags3
& TG3_FLG3_CLKREQ_BUG
) {
3261 u16 oldlnkctl
, newlnkctl
;
3263 pci_read_config_word(tp
->pdev
,
3264 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
3266 if (tp
->link_config
.active_speed
== SPEED_100
||
3267 tp
->link_config
.active_speed
== SPEED_10
)
3268 newlnkctl
= oldlnkctl
& ~PCI_EXP_LNKCTL_CLKREQ_EN
;
3270 newlnkctl
= oldlnkctl
| PCI_EXP_LNKCTL_CLKREQ_EN
;
3271 if (newlnkctl
!= oldlnkctl
)
3272 pci_write_config_word(tp
->pdev
,
3273 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
3277 if (current_link_up
!= netif_carrier_ok(tp
->dev
)) {
3278 if (current_link_up
)
3279 netif_carrier_on(tp
->dev
);
3281 netif_carrier_off(tp
->dev
);
3282 tg3_link_report(tp
);
3288 struct tg3_fiber_aneginfo
{
3290 #define ANEG_STATE_UNKNOWN 0
3291 #define ANEG_STATE_AN_ENABLE 1
3292 #define ANEG_STATE_RESTART_INIT 2
3293 #define ANEG_STATE_RESTART 3
3294 #define ANEG_STATE_DISABLE_LINK_OK 4
3295 #define ANEG_STATE_ABILITY_DETECT_INIT 5
3296 #define ANEG_STATE_ABILITY_DETECT 6
3297 #define ANEG_STATE_ACK_DETECT_INIT 7
3298 #define ANEG_STATE_ACK_DETECT 8
3299 #define ANEG_STATE_COMPLETE_ACK_INIT 9
3300 #define ANEG_STATE_COMPLETE_ACK 10
3301 #define ANEG_STATE_IDLE_DETECT_INIT 11
3302 #define ANEG_STATE_IDLE_DETECT 12
3303 #define ANEG_STATE_LINK_OK 13
3304 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3305 #define ANEG_STATE_NEXT_PAGE_WAIT 15
3308 #define MR_AN_ENABLE 0x00000001
3309 #define MR_RESTART_AN 0x00000002
3310 #define MR_AN_COMPLETE 0x00000004
3311 #define MR_PAGE_RX 0x00000008
3312 #define MR_NP_LOADED 0x00000010
3313 #define MR_TOGGLE_TX 0x00000020
3314 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
3315 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
3316 #define MR_LP_ADV_SYM_PAUSE 0x00000100
3317 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
3318 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3319 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3320 #define MR_LP_ADV_NEXT_PAGE 0x00001000
3321 #define MR_TOGGLE_RX 0x00002000
3322 #define MR_NP_RX 0x00004000
3324 #define MR_LINK_OK 0x80000000
3326 unsigned long link_time
, cur_time
;
3328 u32 ability_match_cfg
;
3329 int ability_match_count
;
3331 char ability_match
, idle_match
, ack_match
;
3333 u32 txconfig
, rxconfig
;
3334 #define ANEG_CFG_NP 0x00000080
3335 #define ANEG_CFG_ACK 0x00000040
3336 #define ANEG_CFG_RF2 0x00000020
3337 #define ANEG_CFG_RF1 0x00000010
3338 #define ANEG_CFG_PS2 0x00000001
3339 #define ANEG_CFG_PS1 0x00008000
3340 #define ANEG_CFG_HD 0x00004000
3341 #define ANEG_CFG_FD 0x00002000
3342 #define ANEG_CFG_INVAL 0x00001f06
3347 #define ANEG_TIMER_ENAB 2
3348 #define ANEG_FAILED -1
3350 #define ANEG_STATE_SETTLE_TIME 10000
3352 static int tg3_fiber_aneg_smachine(struct tg3
*tp
,
3353 struct tg3_fiber_aneginfo
*ap
)
3356 unsigned long delta
;
3360 if (ap
->state
== ANEG_STATE_UNKNOWN
) {
3364 ap
->ability_match_cfg
= 0;
3365 ap
->ability_match_count
= 0;
3366 ap
->ability_match
= 0;
3372 if (tr32(MAC_STATUS
) & MAC_STATUS_RCVD_CFG
) {
3373 rx_cfg_reg
= tr32(MAC_RX_AUTO_NEG
);
3375 if (rx_cfg_reg
!= ap
->ability_match_cfg
) {
3376 ap
->ability_match_cfg
= rx_cfg_reg
;
3377 ap
->ability_match
= 0;
3378 ap
->ability_match_count
= 0;
3380 if (++ap
->ability_match_count
> 1) {
3381 ap
->ability_match
= 1;
3382 ap
->ability_match_cfg
= rx_cfg_reg
;
3385 if (rx_cfg_reg
& ANEG_CFG_ACK
)
3393 ap
->ability_match_cfg
= 0;
3394 ap
->ability_match_count
= 0;
3395 ap
->ability_match
= 0;
3401 ap
->rxconfig
= rx_cfg_reg
;
3404 switch (ap
->state
) {
3405 case ANEG_STATE_UNKNOWN
:
3406 if (ap
->flags
& (MR_AN_ENABLE
| MR_RESTART_AN
))
3407 ap
->state
= ANEG_STATE_AN_ENABLE
;
3410 case ANEG_STATE_AN_ENABLE
:
3411 ap
->flags
&= ~(MR_AN_COMPLETE
| MR_PAGE_RX
);
3412 if (ap
->flags
& MR_AN_ENABLE
) {
3415 ap
->ability_match_cfg
= 0;
3416 ap
->ability_match_count
= 0;
3417 ap
->ability_match
= 0;
3421 ap
->state
= ANEG_STATE_RESTART_INIT
;
3423 ap
->state
= ANEG_STATE_DISABLE_LINK_OK
;
3427 case ANEG_STATE_RESTART_INIT
:
3428 ap
->link_time
= ap
->cur_time
;
3429 ap
->flags
&= ~(MR_NP_LOADED
);
3431 tw32(MAC_TX_AUTO_NEG
, 0);
3432 tp
->mac_mode
|= MAC_MODE_SEND_CONFIGS
;
3433 tw32_f(MAC_MODE
, tp
->mac_mode
);
3436 ret
= ANEG_TIMER_ENAB
;
3437 ap
->state
= ANEG_STATE_RESTART
;
3440 case ANEG_STATE_RESTART
:
3441 delta
= ap
->cur_time
- ap
->link_time
;
3442 if (delta
> ANEG_STATE_SETTLE_TIME
)
3443 ap
->state
= ANEG_STATE_ABILITY_DETECT_INIT
;
3445 ret
= ANEG_TIMER_ENAB
;
3448 case ANEG_STATE_DISABLE_LINK_OK
:
3452 case ANEG_STATE_ABILITY_DETECT_INIT
:
3453 ap
->flags
&= ~(MR_TOGGLE_TX
);
3454 ap
->txconfig
= ANEG_CFG_FD
;
3455 flowctrl
= tg3_advert_flowctrl_1000X(tp
->link_config
.flowctrl
);
3456 if (flowctrl
& ADVERTISE_1000XPAUSE
)
3457 ap
->txconfig
|= ANEG_CFG_PS1
;
3458 if (flowctrl
& ADVERTISE_1000XPSE_ASYM
)
3459 ap
->txconfig
|= ANEG_CFG_PS2
;
3460 tw32(MAC_TX_AUTO_NEG
, ap
->txconfig
);
3461 tp
->mac_mode
|= MAC_MODE_SEND_CONFIGS
;
3462 tw32_f(MAC_MODE
, tp
->mac_mode
);
3465 ap
->state
= ANEG_STATE_ABILITY_DETECT
;
3468 case ANEG_STATE_ABILITY_DETECT
:
3469 if (ap
->ability_match
!= 0 && ap
->rxconfig
!= 0)
3470 ap
->state
= ANEG_STATE_ACK_DETECT_INIT
;
3473 case ANEG_STATE_ACK_DETECT_INIT
:
3474 ap
->txconfig
|= ANEG_CFG_ACK
;
3475 tw32(MAC_TX_AUTO_NEG
, ap
->txconfig
);
3476 tp
->mac_mode
|= MAC_MODE_SEND_CONFIGS
;
3477 tw32_f(MAC_MODE
, tp
->mac_mode
);
3480 ap
->state
= ANEG_STATE_ACK_DETECT
;
3483 case ANEG_STATE_ACK_DETECT
:
3484 if (ap
->ack_match
!= 0) {
3485 if ((ap
->rxconfig
& ~ANEG_CFG_ACK
) ==
3486 (ap
->ability_match_cfg
& ~ANEG_CFG_ACK
)) {
3487 ap
->state
= ANEG_STATE_COMPLETE_ACK_INIT
;
3489 ap
->state
= ANEG_STATE_AN_ENABLE
;
3491 } else if (ap
->ability_match
!= 0 &&
3492 ap
->rxconfig
== 0) {
3493 ap
->state
= ANEG_STATE_AN_ENABLE
;
3497 case ANEG_STATE_COMPLETE_ACK_INIT
:
3498 if (ap
->rxconfig
& ANEG_CFG_INVAL
) {
3502 ap
->flags
&= ~(MR_LP_ADV_FULL_DUPLEX
|
3503 MR_LP_ADV_HALF_DUPLEX
|
3504 MR_LP_ADV_SYM_PAUSE
|
3505 MR_LP_ADV_ASYM_PAUSE
|
3506 MR_LP_ADV_REMOTE_FAULT1
|
3507 MR_LP_ADV_REMOTE_FAULT2
|
3508 MR_LP_ADV_NEXT_PAGE
|
3511 if (ap
->rxconfig
& ANEG_CFG_FD
)
3512 ap
->flags
|= MR_LP_ADV_FULL_DUPLEX
;
3513 if (ap
->rxconfig
& ANEG_CFG_HD
)
3514 ap
->flags
|= MR_LP_ADV_HALF_DUPLEX
;
3515 if (ap
->rxconfig
& ANEG_CFG_PS1
)
3516 ap
->flags
|= MR_LP_ADV_SYM_PAUSE
;
3517 if (ap
->rxconfig
& ANEG_CFG_PS2
)
3518 ap
->flags
|= MR_LP_ADV_ASYM_PAUSE
;
3519 if (ap
->rxconfig
& ANEG_CFG_RF1
)
3520 ap
->flags
|= MR_LP_ADV_REMOTE_FAULT1
;
3521 if (ap
->rxconfig
& ANEG_CFG_RF2
)
3522 ap
->flags
|= MR_LP_ADV_REMOTE_FAULT2
;
3523 if (ap
->rxconfig
& ANEG_CFG_NP
)
3524 ap
->flags
|= MR_LP_ADV_NEXT_PAGE
;
3526 ap
->link_time
= ap
->cur_time
;
3528 ap
->flags
^= (MR_TOGGLE_TX
);
3529 if (ap
->rxconfig
& 0x0008)
3530 ap
->flags
|= MR_TOGGLE_RX
;
3531 if (ap
->rxconfig
& ANEG_CFG_NP
)
3532 ap
->flags
|= MR_NP_RX
;
3533 ap
->flags
|= MR_PAGE_RX
;
3535 ap
->state
= ANEG_STATE_COMPLETE_ACK
;
3536 ret
= ANEG_TIMER_ENAB
;
3539 case ANEG_STATE_COMPLETE_ACK
:
3540 if (ap
->ability_match
!= 0 &&
3541 ap
->rxconfig
== 0) {
3542 ap
->state
= ANEG_STATE_AN_ENABLE
;
3545 delta
= ap
->cur_time
- ap
->link_time
;
3546 if (delta
> ANEG_STATE_SETTLE_TIME
) {
3547 if (!(ap
->flags
& (MR_LP_ADV_NEXT_PAGE
))) {
3548 ap
->state
= ANEG_STATE_IDLE_DETECT_INIT
;
3550 if ((ap
->txconfig
& ANEG_CFG_NP
) == 0 &&
3551 !(ap
->flags
& MR_NP_RX
)) {
3552 ap
->state
= ANEG_STATE_IDLE_DETECT_INIT
;
3560 case ANEG_STATE_IDLE_DETECT_INIT
:
3561 ap
->link_time
= ap
->cur_time
;
3562 tp
->mac_mode
&= ~MAC_MODE_SEND_CONFIGS
;
3563 tw32_f(MAC_MODE
, tp
->mac_mode
);
3566 ap
->state
= ANEG_STATE_IDLE_DETECT
;
3567 ret
= ANEG_TIMER_ENAB
;
3570 case ANEG_STATE_IDLE_DETECT
:
3571 if (ap
->ability_match
!= 0 &&
3572 ap
->rxconfig
== 0) {
3573 ap
->state
= ANEG_STATE_AN_ENABLE
;
3576 delta
= ap
->cur_time
- ap
->link_time
;
3577 if (delta
> ANEG_STATE_SETTLE_TIME
) {
3578 /* XXX another gem from the Broadcom driver :( */
3579 ap
->state
= ANEG_STATE_LINK_OK
;
3583 case ANEG_STATE_LINK_OK
:
3584 ap
->flags
|= (MR_AN_COMPLETE
| MR_LINK_OK
);
3588 case ANEG_STATE_NEXT_PAGE_WAIT_INIT
:
3589 /* ??? unimplemented */
3592 case ANEG_STATE_NEXT_PAGE_WAIT
:
3593 /* ??? unimplemented */
3604 static int fiber_autoneg(struct tg3
*tp
, u32
*txflags
, u32
*rxflags
)
3607 struct tg3_fiber_aneginfo aninfo
;
3608 int status
= ANEG_FAILED
;
3612 tw32_f(MAC_TX_AUTO_NEG
, 0);
3614 tmp
= tp
->mac_mode
& ~MAC_MODE_PORT_MODE_MASK
;
3615 tw32_f(MAC_MODE
, tmp
| MAC_MODE_PORT_MODE_GMII
);
3618 tw32_f(MAC_MODE
, tp
->mac_mode
| MAC_MODE_SEND_CONFIGS
);
3621 memset(&aninfo
, 0, sizeof(aninfo
));
3622 aninfo
.flags
|= MR_AN_ENABLE
;
3623 aninfo
.state
= ANEG_STATE_UNKNOWN
;
3624 aninfo
.cur_time
= 0;
3626 while (++tick
< 195000) {
3627 status
= tg3_fiber_aneg_smachine(tp
, &aninfo
);
3628 if (status
== ANEG_DONE
|| status
== ANEG_FAILED
)
3634 tp
->mac_mode
&= ~MAC_MODE_SEND_CONFIGS
;
3635 tw32_f(MAC_MODE
, tp
->mac_mode
);
3638 *txflags
= aninfo
.txconfig
;
3639 *rxflags
= aninfo
.flags
;
3641 if (status
== ANEG_DONE
&&
3642 (aninfo
.flags
& (MR_AN_COMPLETE
| MR_LINK_OK
|
3643 MR_LP_ADV_FULL_DUPLEX
)))
3649 static void tg3_init_bcm8002(struct tg3
*tp
)
3651 u32 mac_status
= tr32(MAC_STATUS
);
3654 /* Reset when initting first time or we have a link. */
3655 if ((tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
) &&
3656 !(mac_status
& MAC_STATUS_PCS_SYNCED
))
3659 /* Set PLL lock range. */
3660 tg3_writephy(tp
, 0x16, 0x8007);
3663 tg3_writephy(tp
, MII_BMCR
, BMCR_RESET
);
3665 /* Wait for reset to complete. */
3666 /* XXX schedule_timeout() ... */
3667 for (i
= 0; i
< 500; i
++)
3670 /* Config mode; select PMA/Ch 1 regs. */
3671 tg3_writephy(tp
, 0x10, 0x8411);
3673 /* Enable auto-lock and comdet, select txclk for tx. */
3674 tg3_writephy(tp
, 0x11, 0x0a10);
3676 tg3_writephy(tp
, 0x18, 0x00a0);
3677 tg3_writephy(tp
, 0x16, 0x41ff);
3679 /* Assert and deassert POR. */
3680 tg3_writephy(tp
, 0x13, 0x0400);
3682 tg3_writephy(tp
, 0x13, 0x0000);
3684 tg3_writephy(tp
, 0x11, 0x0a50);
3686 tg3_writephy(tp
, 0x11, 0x0a10);
3688 /* Wait for signal to stabilize */
3689 /* XXX schedule_timeout() ... */
3690 for (i
= 0; i
< 15000; i
++)
3693 /* Deselect the channel register so we can read the PHYID
3696 tg3_writephy(tp
, 0x10, 0x8011);
3699 static int tg3_setup_fiber_hw_autoneg(struct tg3
*tp
, u32 mac_status
)
3702 u32 sg_dig_ctrl
, sg_dig_status
;
3703 u32 serdes_cfg
, expected_sg_dig_ctrl
;
3704 int workaround
, port_a
;
3705 int current_link_up
;
3708 expected_sg_dig_ctrl
= 0;
3711 current_link_up
= 0;
3713 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5704_A0
&&
3714 tp
->pci_chip_rev_id
!= CHIPREV_ID_5704_A1
) {
3716 if (tr32(TG3PCI_DUAL_MAC_CTRL
) & DUAL_MAC_CTRL_ID
)
3719 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3720 /* preserve bits 20-23 for voltage regulator */
3721 serdes_cfg
= tr32(MAC_SERDES_CFG
) & 0x00f06fff;
3724 sg_dig_ctrl
= tr32(SG_DIG_CTRL
);
3726 if (tp
->link_config
.autoneg
!= AUTONEG_ENABLE
) {
3727 if (sg_dig_ctrl
& SG_DIG_USING_HW_AUTONEG
) {
3729 u32 val
= serdes_cfg
;
3735 tw32_f(MAC_SERDES_CFG
, val
);
3738 tw32_f(SG_DIG_CTRL
, SG_DIG_COMMON_SETUP
);
3740 if (mac_status
& MAC_STATUS_PCS_SYNCED
) {
3741 tg3_setup_flow_control(tp
, 0, 0);
3742 current_link_up
= 1;
3747 /* Want auto-negotiation. */
3748 expected_sg_dig_ctrl
= SG_DIG_USING_HW_AUTONEG
| SG_DIG_COMMON_SETUP
;
3750 flowctrl
= tg3_advert_flowctrl_1000X(tp
->link_config
.flowctrl
);
3751 if (flowctrl
& ADVERTISE_1000XPAUSE
)
3752 expected_sg_dig_ctrl
|= SG_DIG_PAUSE_CAP
;
3753 if (flowctrl
& ADVERTISE_1000XPSE_ASYM
)
3754 expected_sg_dig_ctrl
|= SG_DIG_ASYM_PAUSE
;
3756 if (sg_dig_ctrl
!= expected_sg_dig_ctrl
) {
3757 if ((tp
->phy_flags
& TG3_PHYFLG_PARALLEL_DETECT
) &&
3758 tp
->serdes_counter
&&
3759 ((mac_status
& (MAC_STATUS_PCS_SYNCED
|
3760 MAC_STATUS_RCVD_CFG
)) ==
3761 MAC_STATUS_PCS_SYNCED
)) {
3762 tp
->serdes_counter
--;
3763 current_link_up
= 1;
3768 tw32_f(MAC_SERDES_CFG
, serdes_cfg
| 0xc011000);
3769 tw32_f(SG_DIG_CTRL
, expected_sg_dig_ctrl
| SG_DIG_SOFT_RESET
);
3771 tw32_f(SG_DIG_CTRL
, expected_sg_dig_ctrl
);
3773 tp
->serdes_counter
= SERDES_AN_TIMEOUT_5704S
;
3774 tp
->phy_flags
&= ~TG3_PHYFLG_PARALLEL_DETECT
;
3775 } else if (mac_status
& (MAC_STATUS_PCS_SYNCED
|
3776 MAC_STATUS_SIGNAL_DET
)) {
3777 sg_dig_status
= tr32(SG_DIG_STATUS
);
3778 mac_status
= tr32(MAC_STATUS
);
3780 if ((sg_dig_status
& SG_DIG_AUTONEG_COMPLETE
) &&
3781 (mac_status
& MAC_STATUS_PCS_SYNCED
)) {
3782 u32 local_adv
= 0, remote_adv
= 0;
3784 if (sg_dig_ctrl
& SG_DIG_PAUSE_CAP
)
3785 local_adv
|= ADVERTISE_1000XPAUSE
;
3786 if (sg_dig_ctrl
& SG_DIG_ASYM_PAUSE
)
3787 local_adv
|= ADVERTISE_1000XPSE_ASYM
;
3789 if (sg_dig_status
& SG_DIG_PARTNER_PAUSE_CAPABLE
)
3790 remote_adv
|= LPA_1000XPAUSE
;
3791 if (sg_dig_status
& SG_DIG_PARTNER_ASYM_PAUSE
)
3792 remote_adv
|= LPA_1000XPAUSE_ASYM
;
3794 tg3_setup_flow_control(tp
, local_adv
, remote_adv
);
3795 current_link_up
= 1;
3796 tp
->serdes_counter
= 0;
3797 tp
->phy_flags
&= ~TG3_PHYFLG_PARALLEL_DETECT
;
3798 } else if (!(sg_dig_status
& SG_DIG_AUTONEG_COMPLETE
)) {
3799 if (tp
->serdes_counter
)
3800 tp
->serdes_counter
--;
3803 u32 val
= serdes_cfg
;
3810 tw32_f(MAC_SERDES_CFG
, val
);
3813 tw32_f(SG_DIG_CTRL
, SG_DIG_COMMON_SETUP
);
3816 /* Link parallel detection - link is up */
3817 /* only if we have PCS_SYNC and not */
3818 /* receiving config code words */
3819 mac_status
= tr32(MAC_STATUS
);
3820 if ((mac_status
& MAC_STATUS_PCS_SYNCED
) &&
3821 !(mac_status
& MAC_STATUS_RCVD_CFG
)) {
3822 tg3_setup_flow_control(tp
, 0, 0);
3823 current_link_up
= 1;
3825 TG3_PHYFLG_PARALLEL_DETECT
;
3826 tp
->serdes_counter
=
3827 SERDES_PARALLEL_DET_TIMEOUT
;
3829 goto restart_autoneg
;
3833 tp
->serdes_counter
= SERDES_AN_TIMEOUT_5704S
;
3834 tp
->phy_flags
&= ~TG3_PHYFLG_PARALLEL_DETECT
;
3838 return current_link_up
;
3841 static int tg3_setup_fiber_by_hand(struct tg3
*tp
, u32 mac_status
)
3843 int current_link_up
= 0;
3845 if (!(mac_status
& MAC_STATUS_PCS_SYNCED
))
3848 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) {
3849 u32 txflags
, rxflags
;
3852 if (fiber_autoneg(tp
, &txflags
, &rxflags
)) {
3853 u32 local_adv
= 0, remote_adv
= 0;
3855 if (txflags
& ANEG_CFG_PS1
)
3856 local_adv
|= ADVERTISE_1000XPAUSE
;
3857 if (txflags
& ANEG_CFG_PS2
)
3858 local_adv
|= ADVERTISE_1000XPSE_ASYM
;
3860 if (rxflags
& MR_LP_ADV_SYM_PAUSE
)
3861 remote_adv
|= LPA_1000XPAUSE
;
3862 if (rxflags
& MR_LP_ADV_ASYM_PAUSE
)
3863 remote_adv
|= LPA_1000XPAUSE_ASYM
;
3865 tg3_setup_flow_control(tp
, local_adv
, remote_adv
);
3867 current_link_up
= 1;
3869 for (i
= 0; i
< 30; i
++) {
3872 (MAC_STATUS_SYNC_CHANGED
|
3873 MAC_STATUS_CFG_CHANGED
));
3875 if ((tr32(MAC_STATUS
) &
3876 (MAC_STATUS_SYNC_CHANGED
|
3877 MAC_STATUS_CFG_CHANGED
)) == 0)
3881 mac_status
= tr32(MAC_STATUS
);
3882 if (current_link_up
== 0 &&
3883 (mac_status
& MAC_STATUS_PCS_SYNCED
) &&
3884 !(mac_status
& MAC_STATUS_RCVD_CFG
))
3885 current_link_up
= 1;
3887 tg3_setup_flow_control(tp
, 0, 0);
3889 /* Forcing 1000FD link up. */
3890 current_link_up
= 1;
3892 tw32_f(MAC_MODE
, (tp
->mac_mode
| MAC_MODE_SEND_CONFIGS
));
3895 tw32_f(MAC_MODE
, tp
->mac_mode
);
3900 return current_link_up
;
3903 static int tg3_setup_fiber_phy(struct tg3
*tp
, int force_reset
)
3906 u16 orig_active_speed
;
3907 u8 orig_active_duplex
;
3909 int current_link_up
;
3912 orig_pause_cfg
= tp
->link_config
.active_flowctrl
;
3913 orig_active_speed
= tp
->link_config
.active_speed
;
3914 orig_active_duplex
= tp
->link_config
.active_duplex
;
3916 if (!(tp
->tg3_flags2
& TG3_FLG2_HW_AUTONEG
) &&
3917 netif_carrier_ok(tp
->dev
) &&
3918 (tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
)) {
3919 mac_status
= tr32(MAC_STATUS
);
3920 mac_status
&= (MAC_STATUS_PCS_SYNCED
|
3921 MAC_STATUS_SIGNAL_DET
|
3922 MAC_STATUS_CFG_CHANGED
|
3923 MAC_STATUS_RCVD_CFG
);
3924 if (mac_status
== (MAC_STATUS_PCS_SYNCED
|
3925 MAC_STATUS_SIGNAL_DET
)) {
3926 tw32_f(MAC_STATUS
, (MAC_STATUS_SYNC_CHANGED
|
3927 MAC_STATUS_CFG_CHANGED
));
3932 tw32_f(MAC_TX_AUTO_NEG
, 0);
3934 tp
->mac_mode
&= ~(MAC_MODE_PORT_MODE_MASK
| MAC_MODE_HALF_DUPLEX
);
3935 tp
->mac_mode
|= MAC_MODE_PORT_MODE_TBI
;
3936 tw32_f(MAC_MODE
, tp
->mac_mode
);
3939 if (tp
->phy_id
== TG3_PHY_ID_BCM8002
)
3940 tg3_init_bcm8002(tp
);
3942 /* Enable link change event even when serdes polling. */
3943 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
3946 current_link_up
= 0;
3947 mac_status
= tr32(MAC_STATUS
);
3949 if (tp
->tg3_flags2
& TG3_FLG2_HW_AUTONEG
)
3950 current_link_up
= tg3_setup_fiber_hw_autoneg(tp
, mac_status
);
3952 current_link_up
= tg3_setup_fiber_by_hand(tp
, mac_status
);
3954 tp
->napi
[0].hw_status
->status
=
3955 (SD_STATUS_UPDATED
|
3956 (tp
->napi
[0].hw_status
->status
& ~SD_STATUS_LINK_CHG
));
3958 for (i
= 0; i
< 100; i
++) {
3959 tw32_f(MAC_STATUS
, (MAC_STATUS_SYNC_CHANGED
|
3960 MAC_STATUS_CFG_CHANGED
));
3962 if ((tr32(MAC_STATUS
) & (MAC_STATUS_SYNC_CHANGED
|
3963 MAC_STATUS_CFG_CHANGED
|
3964 MAC_STATUS_LNKSTATE_CHANGED
)) == 0)
3968 mac_status
= tr32(MAC_STATUS
);
3969 if ((mac_status
& MAC_STATUS_PCS_SYNCED
) == 0) {
3970 current_link_up
= 0;
3971 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
&&
3972 tp
->serdes_counter
== 0) {
3973 tw32_f(MAC_MODE
, (tp
->mac_mode
|
3974 MAC_MODE_SEND_CONFIGS
));
3976 tw32_f(MAC_MODE
, tp
->mac_mode
);
3980 if (current_link_up
== 1) {
3981 tp
->link_config
.active_speed
= SPEED_1000
;
3982 tp
->link_config
.active_duplex
= DUPLEX_FULL
;
3983 tw32(MAC_LED_CTRL
, (tp
->led_ctrl
|
3984 LED_CTRL_LNKLED_OVERRIDE
|
3985 LED_CTRL_1000MBPS_ON
));
3987 tp
->link_config
.active_speed
= SPEED_INVALID
;
3988 tp
->link_config
.active_duplex
= DUPLEX_INVALID
;
3989 tw32(MAC_LED_CTRL
, (tp
->led_ctrl
|
3990 LED_CTRL_LNKLED_OVERRIDE
|
3991 LED_CTRL_TRAFFIC_OVERRIDE
));
3994 if (current_link_up
!= netif_carrier_ok(tp
->dev
)) {
3995 if (current_link_up
)
3996 netif_carrier_on(tp
->dev
);
3998 netif_carrier_off(tp
->dev
);
3999 tg3_link_report(tp
);
4001 u32 now_pause_cfg
= tp
->link_config
.active_flowctrl
;
4002 if (orig_pause_cfg
!= now_pause_cfg
||
4003 orig_active_speed
!= tp
->link_config
.active_speed
||
4004 orig_active_duplex
!= tp
->link_config
.active_duplex
)
4005 tg3_link_report(tp
);
4011 static int tg3_setup_fiber_mii_phy(struct tg3
*tp
, int force_reset
)
4013 int current_link_up
, err
= 0;
4017 u32 local_adv
, remote_adv
;
4019 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
4020 tw32_f(MAC_MODE
, tp
->mac_mode
);
4026 (MAC_STATUS_SYNC_CHANGED
|
4027 MAC_STATUS_CFG_CHANGED
|
4028 MAC_STATUS_MI_COMPLETION
|
4029 MAC_STATUS_LNKSTATE_CHANGED
));
4035 current_link_up
= 0;
4036 current_speed
= SPEED_INVALID
;
4037 current_duplex
= DUPLEX_INVALID
;
4039 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
4040 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
4041 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
) {
4042 if (tr32(MAC_TX_STATUS
) & TX_STATUS_LINK_UP
)
4043 bmsr
|= BMSR_LSTATUS
;
4045 bmsr
&= ~BMSR_LSTATUS
;
4048 err
|= tg3_readphy(tp
, MII_BMCR
, &bmcr
);
4050 if ((tp
->link_config
.autoneg
== AUTONEG_ENABLE
) && !force_reset
&&
4051 (tp
->phy_flags
& TG3_PHYFLG_PARALLEL_DETECT
)) {
4052 /* do nothing, just check for link up at the end */
4053 } else if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) {
4056 err
|= tg3_readphy(tp
, MII_ADVERTISE
, &adv
);
4057 new_adv
= adv
& ~(ADVERTISE_1000XFULL
| ADVERTISE_1000XHALF
|
4058 ADVERTISE_1000XPAUSE
|
4059 ADVERTISE_1000XPSE_ASYM
|
4062 new_adv
|= tg3_advert_flowctrl_1000X(tp
->link_config
.flowctrl
);
4064 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Half
)
4065 new_adv
|= ADVERTISE_1000XHALF
;
4066 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Full
)
4067 new_adv
|= ADVERTISE_1000XFULL
;
4069 if ((new_adv
!= adv
) || !(bmcr
& BMCR_ANENABLE
)) {
4070 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
4071 bmcr
|= BMCR_ANENABLE
| BMCR_ANRESTART
;
4072 tg3_writephy(tp
, MII_BMCR
, bmcr
);
4074 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
4075 tp
->serdes_counter
= SERDES_AN_TIMEOUT_5714S
;
4076 tp
->phy_flags
&= ~TG3_PHYFLG_PARALLEL_DETECT
;
4083 bmcr
&= ~BMCR_SPEED1000
;
4084 new_bmcr
= bmcr
& ~(BMCR_ANENABLE
| BMCR_FULLDPLX
);
4086 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
4087 new_bmcr
|= BMCR_FULLDPLX
;
4089 if (new_bmcr
!= bmcr
) {
4090 /* BMCR_SPEED1000 is a reserved bit that needs
4091 * to be set on write.
4093 new_bmcr
|= BMCR_SPEED1000
;
4095 /* Force a linkdown */
4096 if (netif_carrier_ok(tp
->dev
)) {
4099 err
|= tg3_readphy(tp
, MII_ADVERTISE
, &adv
);
4100 adv
&= ~(ADVERTISE_1000XFULL
|
4101 ADVERTISE_1000XHALF
|
4103 tg3_writephy(tp
, MII_ADVERTISE
, adv
);
4104 tg3_writephy(tp
, MII_BMCR
, bmcr
|
4108 netif_carrier_off(tp
->dev
);
4110 tg3_writephy(tp
, MII_BMCR
, new_bmcr
);
4112 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
4113 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
4114 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
4116 if (tr32(MAC_TX_STATUS
) & TX_STATUS_LINK_UP
)
4117 bmsr
|= BMSR_LSTATUS
;
4119 bmsr
&= ~BMSR_LSTATUS
;
4121 tp
->phy_flags
&= ~TG3_PHYFLG_PARALLEL_DETECT
;
4125 if (bmsr
& BMSR_LSTATUS
) {
4126 current_speed
= SPEED_1000
;
4127 current_link_up
= 1;
4128 if (bmcr
& BMCR_FULLDPLX
)
4129 current_duplex
= DUPLEX_FULL
;
4131 current_duplex
= DUPLEX_HALF
;
4136 if (bmcr
& BMCR_ANENABLE
) {
4139 err
|= tg3_readphy(tp
, MII_ADVERTISE
, &local_adv
);
4140 err
|= tg3_readphy(tp
, MII_LPA
, &remote_adv
);
4141 common
= local_adv
& remote_adv
;
4142 if (common
& (ADVERTISE_1000XHALF
|
4143 ADVERTISE_1000XFULL
)) {
4144 if (common
& ADVERTISE_1000XFULL
)
4145 current_duplex
= DUPLEX_FULL
;
4147 current_duplex
= DUPLEX_HALF
;
4148 } else if (!(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
4149 /* Link is up via parallel detect */
4151 current_link_up
= 0;
4156 if (current_link_up
== 1 && current_duplex
== DUPLEX_FULL
)
4157 tg3_setup_flow_control(tp
, local_adv
, remote_adv
);
4159 tp
->mac_mode
&= ~MAC_MODE_HALF_DUPLEX
;
4160 if (tp
->link_config
.active_duplex
== DUPLEX_HALF
)
4161 tp
->mac_mode
|= MAC_MODE_HALF_DUPLEX
;
4163 tw32_f(MAC_MODE
, tp
->mac_mode
);
4166 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
4168 tp
->link_config
.active_speed
= current_speed
;
4169 tp
->link_config
.active_duplex
= current_duplex
;
4171 if (current_link_up
!= netif_carrier_ok(tp
->dev
)) {
4172 if (current_link_up
)
4173 netif_carrier_on(tp
->dev
);
4175 netif_carrier_off(tp
->dev
);
4176 tp
->phy_flags
&= ~TG3_PHYFLG_PARALLEL_DETECT
;
4178 tg3_link_report(tp
);
4183 static void tg3_serdes_parallel_detect(struct tg3
*tp
)
4185 if (tp
->serdes_counter
) {
4186 /* Give autoneg time to complete. */
4187 tp
->serdes_counter
--;
4191 if (!netif_carrier_ok(tp
->dev
) &&
4192 (tp
->link_config
.autoneg
== AUTONEG_ENABLE
)) {
4195 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
4196 if (bmcr
& BMCR_ANENABLE
) {
4199 /* Select shadow register 0x1f */
4200 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, 0x7c00);
4201 tg3_readphy(tp
, MII_TG3_MISC_SHDW
, &phy1
);
4203 /* Select expansion interrupt status register */
4204 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
4205 MII_TG3_DSP_EXP1_INT_STAT
);
4206 tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &phy2
);
4207 tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &phy2
);
4209 if ((phy1
& 0x10) && !(phy2
& 0x20)) {
4210 /* We have signal detect and not receiving
4211 * config code words, link is up by parallel
4215 bmcr
&= ~BMCR_ANENABLE
;
4216 bmcr
|= BMCR_SPEED1000
| BMCR_FULLDPLX
;
4217 tg3_writephy(tp
, MII_BMCR
, bmcr
);
4218 tp
->phy_flags
|= TG3_PHYFLG_PARALLEL_DETECT
;
4221 } else if (netif_carrier_ok(tp
->dev
) &&
4222 (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) &&
4223 (tp
->phy_flags
& TG3_PHYFLG_PARALLEL_DETECT
)) {
4226 /* Select expansion interrupt status register */
4227 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
4228 MII_TG3_DSP_EXP1_INT_STAT
);
4229 tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &phy2
);
4233 /* Config code words received, turn on autoneg. */
4234 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
4235 tg3_writephy(tp
, MII_BMCR
, bmcr
| BMCR_ANENABLE
);
4237 tp
->phy_flags
&= ~TG3_PHYFLG_PARALLEL_DETECT
;
4243 static int tg3_setup_phy(struct tg3
*tp
, int force_reset
)
4247 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
)
4248 err
= tg3_setup_fiber_phy(tp
, force_reset
);
4249 else if (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
)
4250 err
= tg3_setup_fiber_mii_phy(tp
, force_reset
);
4252 err
= tg3_setup_copper_phy(tp
, force_reset
);
4254 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
) {
4257 val
= tr32(TG3_CPMU_CLCK_STAT
) & CPMU_CLCK_STAT_MAC_CLCK_MASK
;
4258 if (val
== CPMU_CLCK_STAT_MAC_CLCK_62_5
)
4260 else if (val
== CPMU_CLCK_STAT_MAC_CLCK_6_25
)
4265 val
= tr32(GRC_MISC_CFG
) & ~GRC_MISC_CFG_PRESCALAR_MASK
;
4266 val
|= (scale
<< GRC_MISC_CFG_PRESCALAR_SHIFT
);
4267 tw32(GRC_MISC_CFG
, val
);
4270 if (tp
->link_config
.active_speed
== SPEED_1000
&&
4271 tp
->link_config
.active_duplex
== DUPLEX_HALF
)
4272 tw32(MAC_TX_LENGTHS
,
4273 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
4274 (6 << TX_LENGTHS_IPG_SHIFT
) |
4275 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT
)));
4277 tw32(MAC_TX_LENGTHS
,
4278 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
4279 (6 << TX_LENGTHS_IPG_SHIFT
) |
4280 (32 << TX_LENGTHS_SLOT_TIME_SHIFT
)));
4282 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
4283 if (netif_carrier_ok(tp
->dev
)) {
4284 tw32(HOSTCC_STAT_COAL_TICKS
,
4285 tp
->coal
.stats_block_coalesce_usecs
);
4287 tw32(HOSTCC_STAT_COAL_TICKS
, 0);
4291 if (tp
->tg3_flags
& TG3_FLAG_ASPM_WORKAROUND
) {
4292 u32 val
= tr32(PCIE_PWR_MGMT_THRESH
);
4293 if (!netif_carrier_ok(tp
->dev
))
4294 val
= (val
& ~PCIE_PWR_MGMT_L1_THRESH_MSK
) |
4297 val
|= PCIE_PWR_MGMT_L1_THRESH_MSK
;
4298 tw32(PCIE_PWR_MGMT_THRESH
, val
);
4304 static inline int tg3_irq_sync(struct tg3
*tp
)
4306 return tp
->irq_sync
;
4309 /* This is called whenever we suspect that the system chipset is re-
4310 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4311 * is bogus tx completions. We try to recover by setting the
4312 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4315 static void tg3_tx_recover(struct tg3
*tp
)
4317 BUG_ON((tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
) ||
4318 tp
->write32_tx_mbox
== tg3_write_indirect_mbox
);
4320 netdev_warn(tp
->dev
,
4321 "The system may be re-ordering memory-mapped I/O "
4322 "cycles to the network device, attempting to recover. "
4323 "Please report the problem to the driver maintainer "
4324 "and include system chipset information.\n");
4326 spin_lock(&tp
->lock
);
4327 tp
->tg3_flags
|= TG3_FLAG_TX_RECOVERY_PENDING
;
4328 spin_unlock(&tp
->lock
);
4331 static inline u32
tg3_tx_avail(struct tg3_napi
*tnapi
)
4333 /* Tell compiler to fetch tx indices from memory. */
4335 return tnapi
->tx_pending
-
4336 ((tnapi
->tx_prod
- tnapi
->tx_cons
) & (TG3_TX_RING_SIZE
- 1));
4339 /* Tigon3 never reports partial packet sends. So we do not
4340 * need special logic to handle SKBs that have not had all
4341 * of their frags sent yet, like SunGEM does.
4343 static void tg3_tx(struct tg3_napi
*tnapi
)
4345 struct tg3
*tp
= tnapi
->tp
;
4346 u32 hw_idx
= tnapi
->hw_status
->idx
[0].tx_consumer
;
4347 u32 sw_idx
= tnapi
->tx_cons
;
4348 struct netdev_queue
*txq
;
4349 int index
= tnapi
- tp
->napi
;
4351 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)
4354 txq
= netdev_get_tx_queue(tp
->dev
, index
);
4356 while (sw_idx
!= hw_idx
) {
4357 struct ring_info
*ri
= &tnapi
->tx_buffers
[sw_idx
];
4358 struct sk_buff
*skb
= ri
->skb
;
4361 if (unlikely(skb
== NULL
)) {
4366 pci_unmap_single(tp
->pdev
,
4367 dma_unmap_addr(ri
, mapping
),
4373 sw_idx
= NEXT_TX(sw_idx
);
4375 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
4376 ri
= &tnapi
->tx_buffers
[sw_idx
];
4377 if (unlikely(ri
->skb
!= NULL
|| sw_idx
== hw_idx
))
4380 pci_unmap_page(tp
->pdev
,
4381 dma_unmap_addr(ri
, mapping
),
4382 skb_shinfo(skb
)->frags
[i
].size
,
4384 sw_idx
= NEXT_TX(sw_idx
);
4389 if (unlikely(tx_bug
)) {
4395 tnapi
->tx_cons
= sw_idx
;
4397 /* Need to make the tx_cons update visible to tg3_start_xmit()
4398 * before checking for netif_queue_stopped(). Without the
4399 * memory barrier, there is a small possibility that tg3_start_xmit()
4400 * will miss it and cause the queue to be stopped forever.
4404 if (unlikely(netif_tx_queue_stopped(txq
) &&
4405 (tg3_tx_avail(tnapi
) > TG3_TX_WAKEUP_THRESH(tnapi
)))) {
4406 __netif_tx_lock(txq
, smp_processor_id());
4407 if (netif_tx_queue_stopped(txq
) &&
4408 (tg3_tx_avail(tnapi
) > TG3_TX_WAKEUP_THRESH(tnapi
)))
4409 netif_tx_wake_queue(txq
);
4410 __netif_tx_unlock(txq
);
4414 static void tg3_rx_skb_free(struct tg3
*tp
, struct ring_info
*ri
, u32 map_sz
)
4419 pci_unmap_single(tp
->pdev
, dma_unmap_addr(ri
, mapping
),
4420 map_sz
, PCI_DMA_FROMDEVICE
);
4421 dev_kfree_skb_any(ri
->skb
);
4425 /* Returns size of skb allocated or < 0 on error.
4427 * We only need to fill in the address because the other members
4428 * of the RX descriptor are invariant, see tg3_init_rings.
4430 * Note the purposeful assymetry of cpu vs. chip accesses. For
4431 * posting buffers we only dirty the first cache line of the RX
4432 * descriptor (containing the address). Whereas for the RX status
4433 * buffers the cpu only reads the last cacheline of the RX descriptor
4434 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4436 static int tg3_alloc_rx_skb(struct tg3
*tp
, struct tg3_rx_prodring_set
*tpr
,
4437 u32 opaque_key
, u32 dest_idx_unmasked
)
4439 struct tg3_rx_buffer_desc
*desc
;
4440 struct ring_info
*map
, *src_map
;
4441 struct sk_buff
*skb
;
4443 int skb_size
, dest_idx
;
4446 switch (opaque_key
) {
4447 case RXD_OPAQUE_RING_STD
:
4448 dest_idx
= dest_idx_unmasked
& tp
->rx_std_ring_mask
;
4449 desc
= &tpr
->rx_std
[dest_idx
];
4450 map
= &tpr
->rx_std_buffers
[dest_idx
];
4451 skb_size
= tp
->rx_pkt_map_sz
;
4454 case RXD_OPAQUE_RING_JUMBO
:
4455 dest_idx
= dest_idx_unmasked
& tp
->rx_jmb_ring_mask
;
4456 desc
= &tpr
->rx_jmb
[dest_idx
].std
;
4457 map
= &tpr
->rx_jmb_buffers
[dest_idx
];
4458 skb_size
= TG3_RX_JMB_MAP_SZ
;
4465 /* Do not overwrite any of the map or rp information
4466 * until we are sure we can commit to a new buffer.
4468 * Callers depend upon this behavior and assume that
4469 * we leave everything unchanged if we fail.
4471 skb
= netdev_alloc_skb(tp
->dev
, skb_size
+ tp
->rx_offset
);
4475 skb_reserve(skb
, tp
->rx_offset
);
4477 mapping
= pci_map_single(tp
->pdev
, skb
->data
, skb_size
,
4478 PCI_DMA_FROMDEVICE
);
4479 if (pci_dma_mapping_error(tp
->pdev
, mapping
)) {
4485 dma_unmap_addr_set(map
, mapping
, mapping
);
4487 desc
->addr_hi
= ((u64
)mapping
>> 32);
4488 desc
->addr_lo
= ((u64
)mapping
& 0xffffffff);
4493 /* We only need to move over in the address because the other
4494 * members of the RX descriptor are invariant. See notes above
4495 * tg3_alloc_rx_skb for full details.
4497 static void tg3_recycle_rx(struct tg3_napi
*tnapi
,
4498 struct tg3_rx_prodring_set
*dpr
,
4499 u32 opaque_key
, int src_idx
,
4500 u32 dest_idx_unmasked
)
4502 struct tg3
*tp
= tnapi
->tp
;
4503 struct tg3_rx_buffer_desc
*src_desc
, *dest_desc
;
4504 struct ring_info
*src_map
, *dest_map
;
4505 struct tg3_rx_prodring_set
*spr
= &tp
->napi
[0].prodring
;
4508 switch (opaque_key
) {
4509 case RXD_OPAQUE_RING_STD
:
4510 dest_idx
= dest_idx_unmasked
& tp
->rx_std_ring_mask
;
4511 dest_desc
= &dpr
->rx_std
[dest_idx
];
4512 dest_map
= &dpr
->rx_std_buffers
[dest_idx
];
4513 src_desc
= &spr
->rx_std
[src_idx
];
4514 src_map
= &spr
->rx_std_buffers
[src_idx
];
4517 case RXD_OPAQUE_RING_JUMBO
:
4518 dest_idx
= dest_idx_unmasked
& tp
->rx_jmb_ring_mask
;
4519 dest_desc
= &dpr
->rx_jmb
[dest_idx
].std
;
4520 dest_map
= &dpr
->rx_jmb_buffers
[dest_idx
];
4521 src_desc
= &spr
->rx_jmb
[src_idx
].std
;
4522 src_map
= &spr
->rx_jmb_buffers
[src_idx
];
4529 dest_map
->skb
= src_map
->skb
;
4530 dma_unmap_addr_set(dest_map
, mapping
,
4531 dma_unmap_addr(src_map
, mapping
));
4532 dest_desc
->addr_hi
= src_desc
->addr_hi
;
4533 dest_desc
->addr_lo
= src_desc
->addr_lo
;
4535 /* Ensure that the update to the skb happens after the physical
4536 * addresses have been transferred to the new BD location.
4540 src_map
->skb
= NULL
;
4543 /* The RX ring scheme is composed of multiple rings which post fresh
4544 * buffers to the chip, and one special ring the chip uses to report
4545 * status back to the host.
4547 * The special ring reports the status of received packets to the
4548 * host. The chip does not write into the original descriptor the
4549 * RX buffer was obtained from. The chip simply takes the original
4550 * descriptor as provided by the host, updates the status and length
4551 * field, then writes this into the next status ring entry.
4553 * Each ring the host uses to post buffers to the chip is described
4554 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4555 * it is first placed into the on-chip ram. When the packet's length
4556 * is known, it walks down the TG3_BDINFO entries to select the ring.
4557 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4558 * which is within the range of the new packet's length is chosen.
4560 * The "separate ring for rx status" scheme may sound queer, but it makes
4561 * sense from a cache coherency perspective. If only the host writes
4562 * to the buffer post rings, and only the chip writes to the rx status
4563 * rings, then cache lines never move beyond shared-modified state.
4564 * If both the host and chip were to write into the same ring, cache line
4565 * eviction could occur since both entities want it in an exclusive state.
4567 static int tg3_rx(struct tg3_napi
*tnapi
, int budget
)
4569 struct tg3
*tp
= tnapi
->tp
;
4570 u32 work_mask
, rx_std_posted
= 0;
4571 u32 std_prod_idx
, jmb_prod_idx
;
4572 u32 sw_idx
= tnapi
->rx_rcb_ptr
;
4575 struct tg3_rx_prodring_set
*tpr
= &tnapi
->prodring
;
4577 hw_idx
= *(tnapi
->rx_rcb_prod_idx
);
4579 * We need to order the read of hw_idx and the read of
4580 * the opaque cookie.
4585 std_prod_idx
= tpr
->rx_std_prod_idx
;
4586 jmb_prod_idx
= tpr
->rx_jmb_prod_idx
;
4587 while (sw_idx
!= hw_idx
&& budget
> 0) {
4588 struct ring_info
*ri
;
4589 struct tg3_rx_buffer_desc
*desc
= &tnapi
->rx_rcb
[sw_idx
];
4591 struct sk_buff
*skb
;
4592 dma_addr_t dma_addr
;
4593 u32 opaque_key
, desc_idx
, *post_ptr
;
4594 bool hw_vlan __maybe_unused
= false;
4595 u16 vtag __maybe_unused
= 0;
4597 desc_idx
= desc
->opaque
& RXD_OPAQUE_INDEX_MASK
;
4598 opaque_key
= desc
->opaque
& RXD_OPAQUE_RING_MASK
;
4599 if (opaque_key
== RXD_OPAQUE_RING_STD
) {
4600 ri
= &tp
->napi
[0].prodring
.rx_std_buffers
[desc_idx
];
4601 dma_addr
= dma_unmap_addr(ri
, mapping
);
4603 post_ptr
= &std_prod_idx
;
4605 } else if (opaque_key
== RXD_OPAQUE_RING_JUMBO
) {
4606 ri
= &tp
->napi
[0].prodring
.rx_jmb_buffers
[desc_idx
];
4607 dma_addr
= dma_unmap_addr(ri
, mapping
);
4609 post_ptr
= &jmb_prod_idx
;
4611 goto next_pkt_nopost
;
4613 work_mask
|= opaque_key
;
4615 if ((desc
->err_vlan
& RXD_ERR_MASK
) != 0 &&
4616 (desc
->err_vlan
!= RXD_ERR_ODD_NIBBLE_RCVD_MII
)) {
4618 tg3_recycle_rx(tnapi
, tpr
, opaque_key
,
4619 desc_idx
, *post_ptr
);
4621 /* Other statistics kept track of by card. */
4622 tp
->net_stats
.rx_dropped
++;
4626 len
= ((desc
->idx_len
& RXD_LEN_MASK
) >> RXD_LEN_SHIFT
) -
4629 if (len
> TG3_RX_COPY_THRESH(tp
)) {
4632 skb_size
= tg3_alloc_rx_skb(tp
, tpr
, opaque_key
,
4637 pci_unmap_single(tp
->pdev
, dma_addr
, skb_size
,
4638 PCI_DMA_FROMDEVICE
);
4640 /* Ensure that the update to the skb happens
4641 * after the usage of the old DMA mapping.
4649 struct sk_buff
*copy_skb
;
4651 tg3_recycle_rx(tnapi
, tpr
, opaque_key
,
4652 desc_idx
, *post_ptr
);
4654 copy_skb
= netdev_alloc_skb(tp
->dev
, len
+ VLAN_HLEN
+
4656 if (copy_skb
== NULL
)
4657 goto drop_it_no_recycle
;
4659 skb_reserve(copy_skb
, TG3_RAW_IP_ALIGN
+ VLAN_HLEN
);
4660 skb_put(copy_skb
, len
);
4661 pci_dma_sync_single_for_cpu(tp
->pdev
, dma_addr
, len
, PCI_DMA_FROMDEVICE
);
4662 skb_copy_from_linear_data(skb
, copy_skb
->data
, len
);
4663 pci_dma_sync_single_for_device(tp
->pdev
, dma_addr
, len
, PCI_DMA_FROMDEVICE
);
4665 /* We'll reuse the original ring buffer. */
4669 if ((tp
->tg3_flags
& TG3_FLAG_RX_CHECKSUMS
) &&
4670 (desc
->type_flags
& RXD_FLAG_TCPUDP_CSUM
) &&
4671 (((desc
->ip_tcp_csum
& RXD_TCPCSUM_MASK
)
4672 >> RXD_TCPCSUM_SHIFT
) == 0xffff))
4673 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
4675 skb_checksum_none_assert(skb
);
4677 skb
->protocol
= eth_type_trans(skb
, tp
->dev
);
4679 if (len
> (tp
->dev
->mtu
+ ETH_HLEN
) &&
4680 skb
->protocol
!= htons(ETH_P_8021Q
)) {
4685 if (desc
->type_flags
& RXD_FLAG_VLAN
&&
4686 !(tp
->rx_mode
& RX_MODE_KEEP_VLAN_TAG
)) {
4687 vtag
= desc
->err_vlan
& RXD_VLAN_MASK
;
4688 #if TG3_VLAN_TAG_USED
4694 struct vlan_ethhdr
*ve
= (struct vlan_ethhdr
*)
4695 __skb_push(skb
, VLAN_HLEN
);
4697 memmove(ve
, skb
->data
+ VLAN_HLEN
,
4699 ve
->h_vlan_proto
= htons(ETH_P_8021Q
);
4700 ve
->h_vlan_TCI
= htons(vtag
);
4704 #if TG3_VLAN_TAG_USED
4706 vlan_gro_receive(&tnapi
->napi
, tp
->vlgrp
, vtag
, skb
);
4709 napi_gro_receive(&tnapi
->napi
, skb
);
4717 if (unlikely(rx_std_posted
>= tp
->rx_std_max_post
)) {
4718 tpr
->rx_std_prod_idx
= std_prod_idx
&
4719 tp
->rx_std_ring_mask
;
4720 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG
,
4721 tpr
->rx_std_prod_idx
);
4722 work_mask
&= ~RXD_OPAQUE_RING_STD
;
4727 sw_idx
&= (TG3_RX_RCB_RING_SIZE(tp
) - 1);
4729 /* Refresh hw_idx to see if there is new work */
4730 if (sw_idx
== hw_idx
) {
4731 hw_idx
= *(tnapi
->rx_rcb_prod_idx
);
4736 /* ACK the status ring. */
4737 tnapi
->rx_rcb_ptr
= sw_idx
;
4738 tw32_rx_mbox(tnapi
->consmbox
, sw_idx
);
4740 /* Refill RX ring(s). */
4741 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_RSS
)) {
4742 if (work_mask
& RXD_OPAQUE_RING_STD
) {
4743 tpr
->rx_std_prod_idx
= std_prod_idx
&
4744 tp
->rx_std_ring_mask
;
4745 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG
,
4746 tpr
->rx_std_prod_idx
);
4748 if (work_mask
& RXD_OPAQUE_RING_JUMBO
) {
4749 tpr
->rx_jmb_prod_idx
= jmb_prod_idx
&
4750 tp
->rx_jmb_ring_mask
;
4751 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG
,
4752 tpr
->rx_jmb_prod_idx
);
4755 } else if (work_mask
) {
4756 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4757 * updated before the producer indices can be updated.
4761 tpr
->rx_std_prod_idx
= std_prod_idx
& tp
->rx_std_ring_mask
;
4762 tpr
->rx_jmb_prod_idx
= jmb_prod_idx
& tp
->rx_jmb_ring_mask
;
4764 if (tnapi
!= &tp
->napi
[1])
4765 napi_schedule(&tp
->napi
[1].napi
);
4771 static void tg3_poll_link(struct tg3
*tp
)
4773 /* handle link change and other phy events */
4774 if (!(tp
->tg3_flags
&
4775 (TG3_FLAG_USE_LINKCHG_REG
|
4776 TG3_FLAG_POLL_SERDES
))) {
4777 struct tg3_hw_status
*sblk
= tp
->napi
[0].hw_status
;
4779 if (sblk
->status
& SD_STATUS_LINK_CHG
) {
4780 sblk
->status
= SD_STATUS_UPDATED
|
4781 (sblk
->status
& ~SD_STATUS_LINK_CHG
);
4782 spin_lock(&tp
->lock
);
4783 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
4785 (MAC_STATUS_SYNC_CHANGED
|
4786 MAC_STATUS_CFG_CHANGED
|
4787 MAC_STATUS_MI_COMPLETION
|
4788 MAC_STATUS_LNKSTATE_CHANGED
));
4791 tg3_setup_phy(tp
, 0);
4792 spin_unlock(&tp
->lock
);
4797 static int tg3_rx_prodring_xfer(struct tg3
*tp
,
4798 struct tg3_rx_prodring_set
*dpr
,
4799 struct tg3_rx_prodring_set
*spr
)
4801 u32 si
, di
, cpycnt
, src_prod_idx
;
4805 src_prod_idx
= spr
->rx_std_prod_idx
;
4807 /* Make sure updates to the rx_std_buffers[] entries and the
4808 * standard producer index are seen in the correct order.
4812 if (spr
->rx_std_cons_idx
== src_prod_idx
)
4815 if (spr
->rx_std_cons_idx
< src_prod_idx
)
4816 cpycnt
= src_prod_idx
- spr
->rx_std_cons_idx
;
4818 cpycnt
= tp
->rx_std_ring_mask
+ 1 -
4819 spr
->rx_std_cons_idx
;
4821 cpycnt
= min(cpycnt
,
4822 tp
->rx_std_ring_mask
+ 1 - dpr
->rx_std_prod_idx
);
4824 si
= spr
->rx_std_cons_idx
;
4825 di
= dpr
->rx_std_prod_idx
;
4827 for (i
= di
; i
< di
+ cpycnt
; i
++) {
4828 if (dpr
->rx_std_buffers
[i
].skb
) {
4838 /* Ensure that updates to the rx_std_buffers ring and the
4839 * shadowed hardware producer ring from tg3_recycle_skb() are
4840 * ordered correctly WRT the skb check above.
4844 memcpy(&dpr
->rx_std_buffers
[di
],
4845 &spr
->rx_std_buffers
[si
],
4846 cpycnt
* sizeof(struct ring_info
));
4848 for (i
= 0; i
< cpycnt
; i
++, di
++, si
++) {
4849 struct tg3_rx_buffer_desc
*sbd
, *dbd
;
4850 sbd
= &spr
->rx_std
[si
];
4851 dbd
= &dpr
->rx_std
[di
];
4852 dbd
->addr_hi
= sbd
->addr_hi
;
4853 dbd
->addr_lo
= sbd
->addr_lo
;
4856 spr
->rx_std_cons_idx
= (spr
->rx_std_cons_idx
+ cpycnt
) &
4857 tp
->rx_std_ring_mask
;
4858 dpr
->rx_std_prod_idx
= (dpr
->rx_std_prod_idx
+ cpycnt
) &
4859 tp
->rx_std_ring_mask
;
4863 src_prod_idx
= spr
->rx_jmb_prod_idx
;
4865 /* Make sure updates to the rx_jmb_buffers[] entries and
4866 * the jumbo producer index are seen in the correct order.
4870 if (spr
->rx_jmb_cons_idx
== src_prod_idx
)
4873 if (spr
->rx_jmb_cons_idx
< src_prod_idx
)
4874 cpycnt
= src_prod_idx
- spr
->rx_jmb_cons_idx
;
4876 cpycnt
= tp
->rx_jmb_ring_mask
+ 1 -
4877 spr
->rx_jmb_cons_idx
;
4879 cpycnt
= min(cpycnt
,
4880 tp
->rx_jmb_ring_mask
+ 1 - dpr
->rx_jmb_prod_idx
);
4882 si
= spr
->rx_jmb_cons_idx
;
4883 di
= dpr
->rx_jmb_prod_idx
;
4885 for (i
= di
; i
< di
+ cpycnt
; i
++) {
4886 if (dpr
->rx_jmb_buffers
[i
].skb
) {
4896 /* Ensure that updates to the rx_jmb_buffers ring and the
4897 * shadowed hardware producer ring from tg3_recycle_skb() are
4898 * ordered correctly WRT the skb check above.
4902 memcpy(&dpr
->rx_jmb_buffers
[di
],
4903 &spr
->rx_jmb_buffers
[si
],
4904 cpycnt
* sizeof(struct ring_info
));
4906 for (i
= 0; i
< cpycnt
; i
++, di
++, si
++) {
4907 struct tg3_rx_buffer_desc
*sbd
, *dbd
;
4908 sbd
= &spr
->rx_jmb
[si
].std
;
4909 dbd
= &dpr
->rx_jmb
[di
].std
;
4910 dbd
->addr_hi
= sbd
->addr_hi
;
4911 dbd
->addr_lo
= sbd
->addr_lo
;
4914 spr
->rx_jmb_cons_idx
= (spr
->rx_jmb_cons_idx
+ cpycnt
) &
4915 tp
->rx_jmb_ring_mask
;
4916 dpr
->rx_jmb_prod_idx
= (dpr
->rx_jmb_prod_idx
+ cpycnt
) &
4917 tp
->rx_jmb_ring_mask
;
4923 static int tg3_poll_work(struct tg3_napi
*tnapi
, int work_done
, int budget
)
4925 struct tg3
*tp
= tnapi
->tp
;
4927 /* run TX completion thread */
4928 if (tnapi
->hw_status
->idx
[0].tx_consumer
!= tnapi
->tx_cons
) {
4930 if (unlikely(tp
->tg3_flags
& TG3_FLAG_TX_RECOVERY_PENDING
))
4934 /* run RX thread, within the bounds set by NAPI.
4935 * All RX "locking" is done by ensuring outside
4936 * code synchronizes with tg3->napi.poll()
4938 if (*(tnapi
->rx_rcb_prod_idx
) != tnapi
->rx_rcb_ptr
)
4939 work_done
+= tg3_rx(tnapi
, budget
- work_done
);
4941 if ((tp
->tg3_flags3
& TG3_FLG3_ENABLE_RSS
) && tnapi
== &tp
->napi
[1]) {
4942 struct tg3_rx_prodring_set
*dpr
= &tp
->napi
[0].prodring
;
4944 u32 std_prod_idx
= dpr
->rx_std_prod_idx
;
4945 u32 jmb_prod_idx
= dpr
->rx_jmb_prod_idx
;
4947 for (i
= 1; i
< tp
->irq_cnt
; i
++)
4948 err
|= tg3_rx_prodring_xfer(tp
, dpr
,
4949 &tp
->napi
[i
].prodring
);
4953 if (std_prod_idx
!= dpr
->rx_std_prod_idx
)
4954 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG
,
4955 dpr
->rx_std_prod_idx
);
4957 if (jmb_prod_idx
!= dpr
->rx_jmb_prod_idx
)
4958 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG
,
4959 dpr
->rx_jmb_prod_idx
);
4964 tw32_f(HOSTCC_MODE
, tp
->coal_now
);
4970 static int tg3_poll_msix(struct napi_struct
*napi
, int budget
)
4972 struct tg3_napi
*tnapi
= container_of(napi
, struct tg3_napi
, napi
);
4973 struct tg3
*tp
= tnapi
->tp
;
4975 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
4978 work_done
= tg3_poll_work(tnapi
, work_done
, budget
);
4980 if (unlikely(tp
->tg3_flags
& TG3_FLAG_TX_RECOVERY_PENDING
))
4983 if (unlikely(work_done
>= budget
))
4986 /* tp->last_tag is used in tg3_int_reenable() below
4987 * to tell the hw how much work has been processed,
4988 * so we must read it before checking for more work.
4990 tnapi
->last_tag
= sblk
->status_tag
;
4991 tnapi
->last_irq_tag
= tnapi
->last_tag
;
4994 /* check for RX/TX work to do */
4995 if (likely(sblk
->idx
[0].tx_consumer
== tnapi
->tx_cons
&&
4996 *(tnapi
->rx_rcb_prod_idx
) == tnapi
->rx_rcb_ptr
)) {
4997 napi_complete(napi
);
4998 /* Reenable interrupts. */
4999 tw32_mailbox(tnapi
->int_mbox
, tnapi
->last_tag
<< 24);
5008 /* work_done is guaranteed to be less than budget. */
5009 napi_complete(napi
);
5010 schedule_work(&tp
->reset_task
);
5014 static int tg3_poll(struct napi_struct
*napi
, int budget
)
5016 struct tg3_napi
*tnapi
= container_of(napi
, struct tg3_napi
, napi
);
5017 struct tg3
*tp
= tnapi
->tp
;
5019 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
5024 work_done
= tg3_poll_work(tnapi
, work_done
, budget
);
5026 if (unlikely(tp
->tg3_flags
& TG3_FLAG_TX_RECOVERY_PENDING
))
5029 if (unlikely(work_done
>= budget
))
5032 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) {
5033 /* tp->last_tag is used in tg3_int_reenable() below
5034 * to tell the hw how much work has been processed,
5035 * so we must read it before checking for more work.
5037 tnapi
->last_tag
= sblk
->status_tag
;
5038 tnapi
->last_irq_tag
= tnapi
->last_tag
;
5041 sblk
->status
&= ~SD_STATUS_UPDATED
;
5043 if (likely(!tg3_has_work(tnapi
))) {
5044 napi_complete(napi
);
5045 tg3_int_reenable(tnapi
);
5053 /* work_done is guaranteed to be less than budget. */
5054 napi_complete(napi
);
5055 schedule_work(&tp
->reset_task
);
5059 static void tg3_napi_disable(struct tg3
*tp
)
5063 for (i
= tp
->irq_cnt
- 1; i
>= 0; i
--)
5064 napi_disable(&tp
->napi
[i
].napi
);
5067 static void tg3_napi_enable(struct tg3
*tp
)
5071 for (i
= 0; i
< tp
->irq_cnt
; i
++)
5072 napi_enable(&tp
->napi
[i
].napi
);
5075 static void tg3_napi_init(struct tg3
*tp
)
5079 netif_napi_add(tp
->dev
, &tp
->napi
[0].napi
, tg3_poll
, 64);
5080 for (i
= 1; i
< tp
->irq_cnt
; i
++)
5081 netif_napi_add(tp
->dev
, &tp
->napi
[i
].napi
, tg3_poll_msix
, 64);
5084 static void tg3_napi_fini(struct tg3
*tp
)
5088 for (i
= 0; i
< tp
->irq_cnt
; i
++)
5089 netif_napi_del(&tp
->napi
[i
].napi
);
5092 static inline void tg3_netif_stop(struct tg3
*tp
)
5094 tp
->dev
->trans_start
= jiffies
; /* prevent tx timeout */
5095 tg3_napi_disable(tp
);
5096 netif_tx_disable(tp
->dev
);
5099 static inline void tg3_netif_start(struct tg3
*tp
)
5101 /* NOTE: unconditional netif_tx_wake_all_queues is only
5102 * appropriate so long as all callers are assured to
5103 * have free tx slots (such as after tg3_init_hw)
5105 netif_tx_wake_all_queues(tp
->dev
);
5107 tg3_napi_enable(tp
);
5108 tp
->napi
[0].hw_status
->status
|= SD_STATUS_UPDATED
;
5109 tg3_enable_ints(tp
);
5112 static void tg3_irq_quiesce(struct tg3
*tp
)
5116 BUG_ON(tp
->irq_sync
);
5121 for (i
= 0; i
< tp
->irq_cnt
; i
++)
5122 synchronize_irq(tp
->napi
[i
].irq_vec
);
5125 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5126 * If irq_sync is non-zero, then the IRQ handler must be synchronized
5127 * with as well. Most of the time, this is not necessary except when
5128 * shutting down the device.
5130 static inline void tg3_full_lock(struct tg3
*tp
, int irq_sync
)
5132 spin_lock_bh(&tp
->lock
);
5134 tg3_irq_quiesce(tp
);
5137 static inline void tg3_full_unlock(struct tg3
*tp
)
5139 spin_unlock_bh(&tp
->lock
);
5142 /* One-shot MSI handler - Chip automatically disables interrupt
5143 * after sending MSI so driver doesn't have to do it.
5145 static irqreturn_t
tg3_msi_1shot(int irq
, void *dev_id
)
5147 struct tg3_napi
*tnapi
= dev_id
;
5148 struct tg3
*tp
= tnapi
->tp
;
5150 prefetch(tnapi
->hw_status
);
5152 prefetch(&tnapi
->rx_rcb
[tnapi
->rx_rcb_ptr
]);
5154 if (likely(!tg3_irq_sync(tp
)))
5155 napi_schedule(&tnapi
->napi
);
5160 /* MSI ISR - No need to check for interrupt sharing and no need to
5161 * flush status block and interrupt mailbox. PCI ordering rules
5162 * guarantee that MSI will arrive after the status block.
5164 static irqreturn_t
tg3_msi(int irq
, void *dev_id
)
5166 struct tg3_napi
*tnapi
= dev_id
;
5167 struct tg3
*tp
= tnapi
->tp
;
5169 prefetch(tnapi
->hw_status
);
5171 prefetch(&tnapi
->rx_rcb
[tnapi
->rx_rcb_ptr
]);
5173 * Writing any value to intr-mbox-0 clears PCI INTA# and
5174 * chip-internal interrupt pending events.
5175 * Writing non-zero to intr-mbox-0 additional tells the
5176 * NIC to stop sending us irqs, engaging "in-intr-handler"
5179 tw32_mailbox(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0x00000001);
5180 if (likely(!tg3_irq_sync(tp
)))
5181 napi_schedule(&tnapi
->napi
);
5183 return IRQ_RETVAL(1);
5186 static irqreturn_t
tg3_interrupt(int irq
, void *dev_id
)
5188 struct tg3_napi
*tnapi
= dev_id
;
5189 struct tg3
*tp
= tnapi
->tp
;
5190 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
5191 unsigned int handled
= 1;
5193 /* In INTx mode, it is possible for the interrupt to arrive at
5194 * the CPU before the status block posted prior to the interrupt.
5195 * Reading the PCI State register will confirm whether the
5196 * interrupt is ours and will flush the status block.
5198 if (unlikely(!(sblk
->status
& SD_STATUS_UPDATED
))) {
5199 if ((tp
->tg3_flags
& TG3_FLAG_CHIP_RESETTING
) ||
5200 (tr32(TG3PCI_PCISTATE
) & PCISTATE_INT_NOT_ACTIVE
)) {
5207 * Writing any value to intr-mbox-0 clears PCI INTA# and
5208 * chip-internal interrupt pending events.
5209 * Writing non-zero to intr-mbox-0 additional tells the
5210 * NIC to stop sending us irqs, engaging "in-intr-handler"
5213 * Flush the mailbox to de-assert the IRQ immediately to prevent
5214 * spurious interrupts. The flush impacts performance but
5215 * excessive spurious interrupts can be worse in some cases.
5217 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0x00000001);
5218 if (tg3_irq_sync(tp
))
5220 sblk
->status
&= ~SD_STATUS_UPDATED
;
5221 if (likely(tg3_has_work(tnapi
))) {
5222 prefetch(&tnapi
->rx_rcb
[tnapi
->rx_rcb_ptr
]);
5223 napi_schedule(&tnapi
->napi
);
5225 /* No work, shared interrupt perhaps? re-enable
5226 * interrupts, and flush that PCI write
5228 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
,
5232 return IRQ_RETVAL(handled
);
5235 static irqreturn_t
tg3_interrupt_tagged(int irq
, void *dev_id
)
5237 struct tg3_napi
*tnapi
= dev_id
;
5238 struct tg3
*tp
= tnapi
->tp
;
5239 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
5240 unsigned int handled
= 1;
5242 /* In INTx mode, it is possible for the interrupt to arrive at
5243 * the CPU before the status block posted prior to the interrupt.
5244 * Reading the PCI State register will confirm whether the
5245 * interrupt is ours and will flush the status block.
5247 if (unlikely(sblk
->status_tag
== tnapi
->last_irq_tag
)) {
5248 if ((tp
->tg3_flags
& TG3_FLAG_CHIP_RESETTING
) ||
5249 (tr32(TG3PCI_PCISTATE
) & PCISTATE_INT_NOT_ACTIVE
)) {
5256 * writing any value to intr-mbox-0 clears PCI INTA# and
5257 * chip-internal interrupt pending events.
5258 * writing non-zero to intr-mbox-0 additional tells the
5259 * NIC to stop sending us irqs, engaging "in-intr-handler"
5262 * Flush the mailbox to de-assert the IRQ immediately to prevent
5263 * spurious interrupts. The flush impacts performance but
5264 * excessive spurious interrupts can be worse in some cases.
5266 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0x00000001);
5269 * In a shared interrupt configuration, sometimes other devices'
5270 * interrupts will scream. We record the current status tag here
5271 * so that the above check can report that the screaming interrupts
5272 * are unhandled. Eventually they will be silenced.
5274 tnapi
->last_irq_tag
= sblk
->status_tag
;
5276 if (tg3_irq_sync(tp
))
5279 prefetch(&tnapi
->rx_rcb
[tnapi
->rx_rcb_ptr
]);
5281 napi_schedule(&tnapi
->napi
);
5284 return IRQ_RETVAL(handled
);
5287 /* ISR for interrupt test */
5288 static irqreturn_t
tg3_test_isr(int irq
, void *dev_id
)
5290 struct tg3_napi
*tnapi
= dev_id
;
5291 struct tg3
*tp
= tnapi
->tp
;
5292 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
5294 if ((sblk
->status
& SD_STATUS_UPDATED
) ||
5295 !(tr32(TG3PCI_PCISTATE
) & PCISTATE_INT_NOT_ACTIVE
)) {
5296 tg3_disable_ints(tp
);
5297 return IRQ_RETVAL(1);
5299 return IRQ_RETVAL(0);
5302 static int tg3_init_hw(struct tg3
*, int);
5303 static int tg3_halt(struct tg3
*, int, int);
5305 /* Restart hardware after configuration changes, self-test, etc.
5306 * Invoked with tp->lock held.
5308 static int tg3_restart_hw(struct tg3
*tp
, int reset_phy
)
5309 __releases(tp
->lock
)
5310 __acquires(tp
->lock
)
5314 err
= tg3_init_hw(tp
, reset_phy
);
5317 "Failed to re-initialize device, aborting\n");
5318 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
5319 tg3_full_unlock(tp
);
5320 del_timer_sync(&tp
->timer
);
5322 tg3_napi_enable(tp
);
5324 tg3_full_lock(tp
, 0);
5329 #ifdef CONFIG_NET_POLL_CONTROLLER
5330 static void tg3_poll_controller(struct net_device
*dev
)
5333 struct tg3
*tp
= netdev_priv(dev
);
5335 for (i
= 0; i
< tp
->irq_cnt
; i
++)
5336 tg3_interrupt(tp
->napi
[i
].irq_vec
, &tp
->napi
[i
]);
5340 static void tg3_reset_task(struct work_struct
*work
)
5342 struct tg3
*tp
= container_of(work
, struct tg3
, reset_task
);
5344 unsigned int restart_timer
;
5346 tg3_full_lock(tp
, 0);
5348 if (!netif_running(tp
->dev
)) {
5349 tg3_full_unlock(tp
);
5353 tg3_full_unlock(tp
);
5359 tg3_full_lock(tp
, 1);
5361 restart_timer
= tp
->tg3_flags2
& TG3_FLG2_RESTART_TIMER
;
5362 tp
->tg3_flags2
&= ~TG3_FLG2_RESTART_TIMER
;
5364 if (tp
->tg3_flags
& TG3_FLAG_TX_RECOVERY_PENDING
) {
5365 tp
->write32_tx_mbox
= tg3_write32_tx_mbox
;
5366 tp
->write32_rx_mbox
= tg3_write_flush_reg32
;
5367 tp
->tg3_flags
|= TG3_FLAG_MBOX_WRITE_REORDER
;
5368 tp
->tg3_flags
&= ~TG3_FLAG_TX_RECOVERY_PENDING
;
5371 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 0);
5372 err
= tg3_init_hw(tp
, 1);
5376 tg3_netif_start(tp
);
5379 mod_timer(&tp
->timer
, jiffies
+ 1);
5382 tg3_full_unlock(tp
);
5388 static void tg3_dump_short_state(struct tg3
*tp
)
5390 netdev_err(tp
->dev
, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5391 tr32(MAC_TX_STATUS
), tr32(MAC_RX_STATUS
));
5392 netdev_err(tp
->dev
, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5393 tr32(RDMAC_STATUS
), tr32(WDMAC_STATUS
));
5396 static void tg3_tx_timeout(struct net_device
*dev
)
5398 struct tg3
*tp
= netdev_priv(dev
);
5400 if (netif_msg_tx_err(tp
)) {
5401 netdev_err(dev
, "transmit timed out, resetting\n");
5402 tg3_dump_short_state(tp
);
5405 schedule_work(&tp
->reset_task
);
5408 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5409 static inline int tg3_4g_overflow_test(dma_addr_t mapping
, int len
)
5411 u32 base
= (u32
) mapping
& 0xffffffff;
5413 return (base
> 0xffffdcc0) && (base
+ len
+ 8 < base
);
5416 /* Test for DMA addresses > 40-bit */
5417 static inline int tg3_40bit_overflow_test(struct tg3
*tp
, dma_addr_t mapping
,
5420 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5421 if (tp
->tg3_flags
& TG3_FLAG_40BIT_DMA_BUG
)
5422 return ((u64
) mapping
+ len
) > DMA_BIT_MASK(40);
5429 static void tg3_set_txd(struct tg3_napi
*, int, dma_addr_t
, int, u32
, u32
);
5431 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5432 static int tigon3_dma_hwbug_workaround(struct tg3_napi
*tnapi
,
5433 struct sk_buff
*skb
, u32 last_plus_one
,
5434 u32
*start
, u32 base_flags
, u32 mss
)
5436 struct tg3
*tp
= tnapi
->tp
;
5437 struct sk_buff
*new_skb
;
5438 dma_addr_t new_addr
= 0;
5442 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
)
5443 new_skb
= skb_copy(skb
, GFP_ATOMIC
);
5445 int more_headroom
= 4 - ((unsigned long)skb
->data
& 3);
5447 new_skb
= skb_copy_expand(skb
,
5448 skb_headroom(skb
) + more_headroom
,
5449 skb_tailroom(skb
), GFP_ATOMIC
);
5455 /* New SKB is guaranteed to be linear. */
5457 new_addr
= pci_map_single(tp
->pdev
, new_skb
->data
, new_skb
->len
,
5459 /* Make sure the mapping succeeded */
5460 if (pci_dma_mapping_error(tp
->pdev
, new_addr
)) {
5462 dev_kfree_skb(new_skb
);
5465 /* Make sure new skb does not cross any 4G boundaries.
5466 * Drop the packet if it does.
5468 } else if ((tp
->tg3_flags3
& TG3_FLG3_4G_DMA_BNDRY_BUG
) &&
5469 tg3_4g_overflow_test(new_addr
, new_skb
->len
)) {
5470 pci_unmap_single(tp
->pdev
, new_addr
, new_skb
->len
,
5473 dev_kfree_skb(new_skb
);
5476 tg3_set_txd(tnapi
, entry
, new_addr
, new_skb
->len
,
5477 base_flags
, 1 | (mss
<< 1));
5478 *start
= NEXT_TX(entry
);
5482 /* Now clean up the sw ring entries. */
5484 while (entry
!= last_plus_one
) {
5488 len
= skb_headlen(skb
);
5490 len
= skb_shinfo(skb
)->frags
[i
-1].size
;
5492 pci_unmap_single(tp
->pdev
,
5493 dma_unmap_addr(&tnapi
->tx_buffers
[entry
],
5495 len
, PCI_DMA_TODEVICE
);
5497 tnapi
->tx_buffers
[entry
].skb
= new_skb
;
5498 dma_unmap_addr_set(&tnapi
->tx_buffers
[entry
], mapping
,
5501 tnapi
->tx_buffers
[entry
].skb
= NULL
;
5503 entry
= NEXT_TX(entry
);
5512 static void tg3_set_txd(struct tg3_napi
*tnapi
, int entry
,
5513 dma_addr_t mapping
, int len
, u32 flags
,
5516 struct tg3_tx_buffer_desc
*txd
= &tnapi
->tx_ring
[entry
];
5517 int is_end
= (mss_and_is_end
& 0x1);
5518 u32 mss
= (mss_and_is_end
>> 1);
5522 flags
|= TXD_FLAG_END
;
5523 if (flags
& TXD_FLAG_VLAN
) {
5524 vlan_tag
= flags
>> 16;
5527 vlan_tag
|= (mss
<< TXD_MSS_SHIFT
);
5529 txd
->addr_hi
= ((u64
) mapping
>> 32);
5530 txd
->addr_lo
= ((u64
) mapping
& 0xffffffff);
5531 txd
->len_flags
= (len
<< TXD_LEN_SHIFT
) | flags
;
5532 txd
->vlan_tag
= vlan_tag
<< TXD_VLAN_TAG_SHIFT
;
5535 /* hard_start_xmit for devices that don't have any bugs and
5536 * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5538 static netdev_tx_t
tg3_start_xmit(struct sk_buff
*skb
,
5539 struct net_device
*dev
)
5541 struct tg3
*tp
= netdev_priv(dev
);
5542 u32 len
, entry
, base_flags
, mss
;
5544 struct tg3_napi
*tnapi
;
5545 struct netdev_queue
*txq
;
5546 unsigned int i
, last
;
5548 txq
= netdev_get_tx_queue(dev
, skb_get_queue_mapping(skb
));
5549 tnapi
= &tp
->napi
[skb_get_queue_mapping(skb
)];
5550 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)
5553 /* We are running in BH disabled context with netif_tx_lock
5554 * and TX reclaim runs via tp->napi.poll inside of a software
5555 * interrupt. Furthermore, IRQ processing runs lockless so we have
5556 * no IRQ context deadlocks to worry about either. Rejoice!
5558 if (unlikely(tg3_tx_avail(tnapi
) <= (skb_shinfo(skb
)->nr_frags
+ 1))) {
5559 if (!netif_tx_queue_stopped(txq
)) {
5560 netif_tx_stop_queue(txq
);
5562 /* This is a hard error, log it. */
5564 "BUG! Tx Ring full when queue awake!\n");
5566 return NETDEV_TX_BUSY
;
5569 entry
= tnapi
->tx_prod
;
5571 mss
= skb_shinfo(skb
)->gso_size
;
5573 int tcp_opt_len
, ip_tcp_len
;
5576 if (skb_header_cloned(skb
) &&
5577 pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
)) {
5582 if (skb_is_gso_v6(skb
)) {
5583 hdrlen
= skb_headlen(skb
) - ETH_HLEN
;
5585 struct iphdr
*iph
= ip_hdr(skb
);
5587 tcp_opt_len
= tcp_optlen(skb
);
5588 ip_tcp_len
= ip_hdrlen(skb
) + sizeof(struct tcphdr
);
5591 iph
->tot_len
= htons(mss
+ ip_tcp_len
+ tcp_opt_len
);
5592 hdrlen
= ip_tcp_len
+ tcp_opt_len
;
5595 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO_3
) {
5596 mss
|= (hdrlen
& 0xc) << 12;
5598 base_flags
|= 0x00000010;
5599 base_flags
|= (hdrlen
& 0x3e0) << 5;
5603 base_flags
|= (TXD_FLAG_CPU_PRE_DMA
|
5604 TXD_FLAG_CPU_POST_DMA
);
5606 tcp_hdr(skb
)->check
= 0;
5608 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
5609 base_flags
|= TXD_FLAG_TCPUDP_CSUM
;
5612 #if TG3_VLAN_TAG_USED
5613 if (tp
->vlgrp
!= NULL
&& vlan_tx_tag_present(skb
))
5614 base_flags
|= (TXD_FLAG_VLAN
|
5615 (vlan_tx_tag_get(skb
) << 16));
5618 len
= skb_headlen(skb
);
5620 /* Queue skb data, a.k.a. the main skb fragment. */
5621 mapping
= pci_map_single(tp
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
5622 if (pci_dma_mapping_error(tp
->pdev
, mapping
)) {
5627 tnapi
->tx_buffers
[entry
].skb
= skb
;
5628 dma_unmap_addr_set(&tnapi
->tx_buffers
[entry
], mapping
, mapping
);
5630 if ((tp
->tg3_flags3
& TG3_FLG3_USE_JUMBO_BDFLAG
) &&
5631 !mss
&& skb
->len
> ETH_DATA_LEN
)
5632 base_flags
|= TXD_FLAG_JMB_PKT
;
5634 tg3_set_txd(tnapi
, entry
, mapping
, len
, base_flags
,
5635 (skb_shinfo(skb
)->nr_frags
== 0) | (mss
<< 1));
5637 entry
= NEXT_TX(entry
);
5639 /* Now loop through additional data fragments, and queue them. */
5640 if (skb_shinfo(skb
)->nr_frags
> 0) {
5641 last
= skb_shinfo(skb
)->nr_frags
- 1;
5642 for (i
= 0; i
<= last
; i
++) {
5643 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
5646 mapping
= pci_map_page(tp
->pdev
,
5649 len
, PCI_DMA_TODEVICE
);
5650 if (pci_dma_mapping_error(tp
->pdev
, mapping
))
5653 tnapi
->tx_buffers
[entry
].skb
= NULL
;
5654 dma_unmap_addr_set(&tnapi
->tx_buffers
[entry
], mapping
,
5657 tg3_set_txd(tnapi
, entry
, mapping
, len
,
5658 base_flags
, (i
== last
) | (mss
<< 1));
5660 entry
= NEXT_TX(entry
);
5664 /* Packets are ready, update Tx producer idx local and on card. */
5665 tw32_tx_mbox(tnapi
->prodmbox
, entry
);
5667 tnapi
->tx_prod
= entry
;
5668 if (unlikely(tg3_tx_avail(tnapi
) <= (MAX_SKB_FRAGS
+ 1))) {
5669 netif_tx_stop_queue(txq
);
5671 /* netif_tx_stop_queue() must be done before checking
5672 * checking tx index in tg3_tx_avail() below, because in
5673 * tg3_tx(), we update tx index before checking for
5674 * netif_tx_queue_stopped().
5677 if (tg3_tx_avail(tnapi
) > TG3_TX_WAKEUP_THRESH(tnapi
))
5678 netif_tx_wake_queue(txq
);
5684 return NETDEV_TX_OK
;
5688 entry
= tnapi
->tx_prod
;
5689 tnapi
->tx_buffers
[entry
].skb
= NULL
;
5690 pci_unmap_single(tp
->pdev
,
5691 dma_unmap_addr(&tnapi
->tx_buffers
[entry
], mapping
),
5694 for (i
= 0; i
<= last
; i
++) {
5695 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
5696 entry
= NEXT_TX(entry
);
5698 pci_unmap_page(tp
->pdev
,
5699 dma_unmap_addr(&tnapi
->tx_buffers
[entry
],
5701 frag
->size
, PCI_DMA_TODEVICE
);
5705 return NETDEV_TX_OK
;
5708 static netdev_tx_t
tg3_start_xmit_dma_bug(struct sk_buff
*,
5709 struct net_device
*);
5711 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5712 * TSO header is greater than 80 bytes.
5714 static int tg3_tso_bug(struct tg3
*tp
, struct sk_buff
*skb
)
5716 struct sk_buff
*segs
, *nskb
;
5717 u32 frag_cnt_est
= skb_shinfo(skb
)->gso_segs
* 3;
5719 /* Estimate the number of fragments in the worst case */
5720 if (unlikely(tg3_tx_avail(&tp
->napi
[0]) <= frag_cnt_est
)) {
5721 netif_stop_queue(tp
->dev
);
5723 /* netif_tx_stop_queue() must be done before checking
5724 * checking tx index in tg3_tx_avail() below, because in
5725 * tg3_tx(), we update tx index before checking for
5726 * netif_tx_queue_stopped().
5729 if (tg3_tx_avail(&tp
->napi
[0]) <= frag_cnt_est
)
5730 return NETDEV_TX_BUSY
;
5732 netif_wake_queue(tp
->dev
);
5735 segs
= skb_gso_segment(skb
, tp
->dev
->features
& ~NETIF_F_TSO
);
5737 goto tg3_tso_bug_end
;
5743 tg3_start_xmit_dma_bug(nskb
, tp
->dev
);
5749 return NETDEV_TX_OK
;
5752 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5753 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5755 static netdev_tx_t
tg3_start_xmit_dma_bug(struct sk_buff
*skb
,
5756 struct net_device
*dev
)
5758 struct tg3
*tp
= netdev_priv(dev
);
5759 u32 len
, entry
, base_flags
, mss
;
5760 int would_hit_hwbug
;
5762 struct tg3_napi
*tnapi
;
5763 struct netdev_queue
*txq
;
5764 unsigned int i
, last
;
5766 txq
= netdev_get_tx_queue(dev
, skb_get_queue_mapping(skb
));
5767 tnapi
= &tp
->napi
[skb_get_queue_mapping(skb
)];
5768 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)
5771 /* We are running in BH disabled context with netif_tx_lock
5772 * and TX reclaim runs via tp->napi.poll inside of a software
5773 * interrupt. Furthermore, IRQ processing runs lockless so we have
5774 * no IRQ context deadlocks to worry about either. Rejoice!
5776 if (unlikely(tg3_tx_avail(tnapi
) <= (skb_shinfo(skb
)->nr_frags
+ 1))) {
5777 if (!netif_tx_queue_stopped(txq
)) {
5778 netif_tx_stop_queue(txq
);
5780 /* This is a hard error, log it. */
5782 "BUG! Tx Ring full when queue awake!\n");
5784 return NETDEV_TX_BUSY
;
5787 entry
= tnapi
->tx_prod
;
5789 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
5790 base_flags
|= TXD_FLAG_TCPUDP_CSUM
;
5792 mss
= skb_shinfo(skb
)->gso_size
;
5795 u32 tcp_opt_len
, hdr_len
;
5797 if (skb_header_cloned(skb
) &&
5798 pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
)) {
5804 tcp_opt_len
= tcp_optlen(skb
);
5806 if (skb_is_gso_v6(skb
)) {
5807 hdr_len
= skb_headlen(skb
) - ETH_HLEN
;
5811 ip_tcp_len
= ip_hdrlen(skb
) + sizeof(struct tcphdr
);
5812 hdr_len
= ip_tcp_len
+ tcp_opt_len
;
5815 iph
->tot_len
= htons(mss
+ hdr_len
);
5818 if (unlikely((ETH_HLEN
+ hdr_len
) > 80) &&
5819 (tp
->tg3_flags2
& TG3_FLG2_TSO_BUG
))
5820 return tg3_tso_bug(tp
, skb
);
5822 base_flags
|= (TXD_FLAG_CPU_PRE_DMA
|
5823 TXD_FLAG_CPU_POST_DMA
);
5825 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
) {
5826 tcp_hdr(skb
)->check
= 0;
5827 base_flags
&= ~TXD_FLAG_TCPUDP_CSUM
;
5829 tcp_hdr(skb
)->check
= ~csum_tcpudp_magic(iph
->saddr
,
5834 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO_3
) {
5835 mss
|= (hdr_len
& 0xc) << 12;
5837 base_flags
|= 0x00000010;
5838 base_flags
|= (hdr_len
& 0x3e0) << 5;
5839 } else if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO_2
)
5840 mss
|= hdr_len
<< 9;
5841 else if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO_1
) ||
5842 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
5843 if (tcp_opt_len
|| iph
->ihl
> 5) {
5846 tsflags
= (iph
->ihl
- 5) + (tcp_opt_len
>> 2);
5847 mss
|= (tsflags
<< 11);
5850 if (tcp_opt_len
|| iph
->ihl
> 5) {
5853 tsflags
= (iph
->ihl
- 5) + (tcp_opt_len
>> 2);
5854 base_flags
|= tsflags
<< 12;
5858 #if TG3_VLAN_TAG_USED
5859 if (tp
->vlgrp
!= NULL
&& vlan_tx_tag_present(skb
))
5860 base_flags
|= (TXD_FLAG_VLAN
|
5861 (vlan_tx_tag_get(skb
) << 16));
5864 if ((tp
->tg3_flags3
& TG3_FLG3_USE_JUMBO_BDFLAG
) &&
5865 !mss
&& skb
->len
> ETH_DATA_LEN
)
5866 base_flags
|= TXD_FLAG_JMB_PKT
;
5868 len
= skb_headlen(skb
);
5870 mapping
= pci_map_single(tp
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
5871 if (pci_dma_mapping_error(tp
->pdev
, mapping
)) {
5876 tnapi
->tx_buffers
[entry
].skb
= skb
;
5877 dma_unmap_addr_set(&tnapi
->tx_buffers
[entry
], mapping
, mapping
);
5879 would_hit_hwbug
= 0;
5881 if ((tp
->tg3_flags3
& TG3_FLG3_SHORT_DMA_BUG
) && len
<= 8)
5882 would_hit_hwbug
= 1;
5884 if ((tp
->tg3_flags3
& TG3_FLG3_4G_DMA_BNDRY_BUG
) &&
5885 tg3_4g_overflow_test(mapping
, len
))
5886 would_hit_hwbug
= 1;
5888 if ((tp
->tg3_flags3
& TG3_FLG3_40BIT_DMA_LIMIT_BUG
) &&
5889 tg3_40bit_overflow_test(tp
, mapping
, len
))
5890 would_hit_hwbug
= 1;
5892 if (tp
->tg3_flags3
& TG3_FLG3_5701_DMA_BUG
)
5893 would_hit_hwbug
= 1;
5895 tg3_set_txd(tnapi
, entry
, mapping
, len
, base_flags
,
5896 (skb_shinfo(skb
)->nr_frags
== 0) | (mss
<< 1));
5898 entry
= NEXT_TX(entry
);
5900 /* Now loop through additional data fragments, and queue them. */
5901 if (skb_shinfo(skb
)->nr_frags
> 0) {
5902 last
= skb_shinfo(skb
)->nr_frags
- 1;
5903 for (i
= 0; i
<= last
; i
++) {
5904 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
5907 mapping
= pci_map_page(tp
->pdev
,
5910 len
, PCI_DMA_TODEVICE
);
5912 tnapi
->tx_buffers
[entry
].skb
= NULL
;
5913 dma_unmap_addr_set(&tnapi
->tx_buffers
[entry
], mapping
,
5915 if (pci_dma_mapping_error(tp
->pdev
, mapping
))
5918 if ((tp
->tg3_flags3
& TG3_FLG3_SHORT_DMA_BUG
) &&
5920 would_hit_hwbug
= 1;
5922 if ((tp
->tg3_flags3
& TG3_FLG3_4G_DMA_BNDRY_BUG
) &&
5923 tg3_4g_overflow_test(mapping
, len
))
5924 would_hit_hwbug
= 1;
5926 if ((tp
->tg3_flags3
& TG3_FLG3_40BIT_DMA_LIMIT_BUG
) &&
5927 tg3_40bit_overflow_test(tp
, mapping
, len
))
5928 would_hit_hwbug
= 1;
5930 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
5931 tg3_set_txd(tnapi
, entry
, mapping
, len
,
5932 base_flags
, (i
== last
)|(mss
<< 1));
5934 tg3_set_txd(tnapi
, entry
, mapping
, len
,
5935 base_flags
, (i
== last
));
5937 entry
= NEXT_TX(entry
);
5941 if (would_hit_hwbug
) {
5942 u32 last_plus_one
= entry
;
5945 start
= entry
- 1 - skb_shinfo(skb
)->nr_frags
;
5946 start
&= (TG3_TX_RING_SIZE
- 1);
5948 /* If the workaround fails due to memory/mapping
5949 * failure, silently drop this packet.
5951 if (tigon3_dma_hwbug_workaround(tnapi
, skb
, last_plus_one
,
5952 &start
, base_flags
, mss
))
5958 /* Packets are ready, update Tx producer idx local and on card. */
5959 tw32_tx_mbox(tnapi
->prodmbox
, entry
);
5961 tnapi
->tx_prod
= entry
;
5962 if (unlikely(tg3_tx_avail(tnapi
) <= (MAX_SKB_FRAGS
+ 1))) {
5963 netif_tx_stop_queue(txq
);
5965 /* netif_tx_stop_queue() must be done before checking
5966 * checking tx index in tg3_tx_avail() below, because in
5967 * tg3_tx(), we update tx index before checking for
5968 * netif_tx_queue_stopped().
5971 if (tg3_tx_avail(tnapi
) > TG3_TX_WAKEUP_THRESH(tnapi
))
5972 netif_tx_wake_queue(txq
);
5978 return NETDEV_TX_OK
;
5982 entry
= tnapi
->tx_prod
;
5983 tnapi
->tx_buffers
[entry
].skb
= NULL
;
5984 pci_unmap_single(tp
->pdev
,
5985 dma_unmap_addr(&tnapi
->tx_buffers
[entry
], mapping
),
5988 for (i
= 0; i
<= last
; i
++) {
5989 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
5990 entry
= NEXT_TX(entry
);
5992 pci_unmap_page(tp
->pdev
,
5993 dma_unmap_addr(&tnapi
->tx_buffers
[entry
],
5995 frag
->size
, PCI_DMA_TODEVICE
);
5999 return NETDEV_TX_OK
;
6002 static inline void tg3_set_mtu(struct net_device
*dev
, struct tg3
*tp
,
6007 if (new_mtu
> ETH_DATA_LEN
) {
6008 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) {
6009 tp
->tg3_flags2
&= ~TG3_FLG2_TSO_CAPABLE
;
6010 ethtool_op_set_tso(dev
, 0);
6012 tp
->tg3_flags
|= TG3_FLAG_JUMBO_RING_ENABLE
;
6015 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)
6016 tp
->tg3_flags2
|= TG3_FLG2_TSO_CAPABLE
;
6017 tp
->tg3_flags
&= ~TG3_FLAG_JUMBO_RING_ENABLE
;
6021 static int tg3_change_mtu(struct net_device
*dev
, int new_mtu
)
6023 struct tg3
*tp
= netdev_priv(dev
);
6026 if (new_mtu
< TG3_MIN_MTU
|| new_mtu
> TG3_MAX_MTU(tp
))
6029 if (!netif_running(dev
)) {
6030 /* We'll just catch it later when the
6033 tg3_set_mtu(dev
, tp
, new_mtu
);
6041 tg3_full_lock(tp
, 1);
6043 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
6045 tg3_set_mtu(dev
, tp
, new_mtu
);
6047 err
= tg3_restart_hw(tp
, 0);
6050 tg3_netif_start(tp
);
6052 tg3_full_unlock(tp
);
6060 static void tg3_rx_prodring_free(struct tg3
*tp
,
6061 struct tg3_rx_prodring_set
*tpr
)
6065 if (tpr
!= &tp
->napi
[0].prodring
) {
6066 for (i
= tpr
->rx_std_cons_idx
; i
!= tpr
->rx_std_prod_idx
;
6067 i
= (i
+ 1) & tp
->rx_std_ring_mask
)
6068 tg3_rx_skb_free(tp
, &tpr
->rx_std_buffers
[i
],
6071 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) {
6072 for (i
= tpr
->rx_jmb_cons_idx
;
6073 i
!= tpr
->rx_jmb_prod_idx
;
6074 i
= (i
+ 1) & tp
->rx_jmb_ring_mask
) {
6075 tg3_rx_skb_free(tp
, &tpr
->rx_jmb_buffers
[i
],
6083 for (i
= 0; i
<= tp
->rx_std_ring_mask
; i
++)
6084 tg3_rx_skb_free(tp
, &tpr
->rx_std_buffers
[i
],
6087 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) {
6088 for (i
= 0; i
<= tp
->rx_jmb_ring_mask
; i
++)
6089 tg3_rx_skb_free(tp
, &tpr
->rx_jmb_buffers
[i
],
6094 /* Initialize rx rings for packet processing.
6096 * The chip has been shut down and the driver detached from
6097 * the networking, so no interrupts or new tx packets will
6098 * end up in the driver. tp->{tx,}lock are held and thus
6101 static int tg3_rx_prodring_alloc(struct tg3
*tp
,
6102 struct tg3_rx_prodring_set
*tpr
)
6104 u32 i
, rx_pkt_dma_sz
;
6106 tpr
->rx_std_cons_idx
= 0;
6107 tpr
->rx_std_prod_idx
= 0;
6108 tpr
->rx_jmb_cons_idx
= 0;
6109 tpr
->rx_jmb_prod_idx
= 0;
6111 if (tpr
!= &tp
->napi
[0].prodring
) {
6112 memset(&tpr
->rx_std_buffers
[0], 0,
6113 TG3_RX_STD_BUFF_RING_SIZE(tp
));
6114 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
)
6115 memset(&tpr
->rx_jmb_buffers
[0], 0,
6116 TG3_RX_JMB_BUFF_RING_SIZE(tp
));
6120 /* Zero out all descriptors. */
6121 memset(tpr
->rx_std
, 0, TG3_RX_STD_RING_BYTES(tp
));
6123 rx_pkt_dma_sz
= TG3_RX_STD_DMA_SZ
;
6124 if ((tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) &&
6125 tp
->dev
->mtu
> ETH_DATA_LEN
)
6126 rx_pkt_dma_sz
= TG3_RX_JMB_DMA_SZ
;
6127 tp
->rx_pkt_map_sz
= TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz
);
6129 /* Initialize invariants of the rings, we only set this
6130 * stuff once. This works because the card does not
6131 * write into the rx buffer posting rings.
6133 for (i
= 0; i
<= tp
->rx_std_ring_mask
; i
++) {
6134 struct tg3_rx_buffer_desc
*rxd
;
6136 rxd
= &tpr
->rx_std
[i
];
6137 rxd
->idx_len
= rx_pkt_dma_sz
<< RXD_LEN_SHIFT
;
6138 rxd
->type_flags
= (RXD_FLAG_END
<< RXD_FLAGS_SHIFT
);
6139 rxd
->opaque
= (RXD_OPAQUE_RING_STD
|
6140 (i
<< RXD_OPAQUE_INDEX_SHIFT
));
6143 /* Now allocate fresh SKBs for each rx ring. */
6144 for (i
= 0; i
< tp
->rx_pending
; i
++) {
6145 if (tg3_alloc_rx_skb(tp
, tpr
, RXD_OPAQUE_RING_STD
, i
) < 0) {
6146 netdev_warn(tp
->dev
,
6147 "Using a smaller RX standard ring. Only "
6148 "%d out of %d buffers were allocated "
6149 "successfully\n", i
, tp
->rx_pending
);
6157 if (!(tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
))
6160 memset(tpr
->rx_jmb
, 0, TG3_RX_JMB_RING_BYTES(tp
));
6162 if (!(tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
))
6165 for (i
= 0; i
<= tp
->rx_jmb_ring_mask
; i
++) {
6166 struct tg3_rx_buffer_desc
*rxd
;
6168 rxd
= &tpr
->rx_jmb
[i
].std
;
6169 rxd
->idx_len
= TG3_RX_JMB_DMA_SZ
<< RXD_LEN_SHIFT
;
6170 rxd
->type_flags
= (RXD_FLAG_END
<< RXD_FLAGS_SHIFT
) |
6172 rxd
->opaque
= (RXD_OPAQUE_RING_JUMBO
|
6173 (i
<< RXD_OPAQUE_INDEX_SHIFT
));
6176 for (i
= 0; i
< tp
->rx_jumbo_pending
; i
++) {
6177 if (tg3_alloc_rx_skb(tp
, tpr
, RXD_OPAQUE_RING_JUMBO
, i
) < 0) {
6178 netdev_warn(tp
->dev
,
6179 "Using a smaller RX jumbo ring. Only %d "
6180 "out of %d buffers were allocated "
6181 "successfully\n", i
, tp
->rx_jumbo_pending
);
6184 tp
->rx_jumbo_pending
= i
;
6193 tg3_rx_prodring_free(tp
, tpr
);
6197 static void tg3_rx_prodring_fini(struct tg3
*tp
,
6198 struct tg3_rx_prodring_set
*tpr
)
6200 kfree(tpr
->rx_std_buffers
);
6201 tpr
->rx_std_buffers
= NULL
;
6202 kfree(tpr
->rx_jmb_buffers
);
6203 tpr
->rx_jmb_buffers
= NULL
;
6205 pci_free_consistent(tp
->pdev
, TG3_RX_STD_RING_BYTES(tp
),
6206 tpr
->rx_std
, tpr
->rx_std_mapping
);
6210 pci_free_consistent(tp
->pdev
, TG3_RX_JMB_RING_BYTES(tp
),
6211 tpr
->rx_jmb
, tpr
->rx_jmb_mapping
);
6216 static int tg3_rx_prodring_init(struct tg3
*tp
,
6217 struct tg3_rx_prodring_set
*tpr
)
6219 tpr
->rx_std_buffers
= kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp
),
6221 if (!tpr
->rx_std_buffers
)
6224 tpr
->rx_std
= pci_alloc_consistent(tp
->pdev
, TG3_RX_STD_RING_BYTES(tp
),
6225 &tpr
->rx_std_mapping
);
6229 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) {
6230 tpr
->rx_jmb_buffers
= kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp
),
6232 if (!tpr
->rx_jmb_buffers
)
6235 tpr
->rx_jmb
= pci_alloc_consistent(tp
->pdev
,
6236 TG3_RX_JMB_RING_BYTES(tp
),
6237 &tpr
->rx_jmb_mapping
);
6245 tg3_rx_prodring_fini(tp
, tpr
);
6249 /* Free up pending packets in all rx/tx rings.
6251 * The chip has been shut down and the driver detached from
6252 * the networking, so no interrupts or new tx packets will
6253 * end up in the driver. tp->{tx,}lock is not held and we are not
6254 * in an interrupt context and thus may sleep.
6256 static void tg3_free_rings(struct tg3
*tp
)
6260 for (j
= 0; j
< tp
->irq_cnt
; j
++) {
6261 struct tg3_napi
*tnapi
= &tp
->napi
[j
];
6263 tg3_rx_prodring_free(tp
, &tnapi
->prodring
);
6265 if (!tnapi
->tx_buffers
)
6268 for (i
= 0; i
< TG3_TX_RING_SIZE
; ) {
6269 struct ring_info
*txp
;
6270 struct sk_buff
*skb
;
6273 txp
= &tnapi
->tx_buffers
[i
];
6281 pci_unmap_single(tp
->pdev
,
6282 dma_unmap_addr(txp
, mapping
),
6289 for (k
= 0; k
< skb_shinfo(skb
)->nr_frags
; k
++) {
6290 txp
= &tnapi
->tx_buffers
[i
& (TG3_TX_RING_SIZE
- 1)];
6291 pci_unmap_page(tp
->pdev
,
6292 dma_unmap_addr(txp
, mapping
),
6293 skb_shinfo(skb
)->frags
[k
].size
,
6298 dev_kfree_skb_any(skb
);
6303 /* Initialize tx/rx rings for packet processing.
6305 * The chip has been shut down and the driver detached from
6306 * the networking, so no interrupts or new tx packets will
6307 * end up in the driver. tp->{tx,}lock are held and thus
6310 static int tg3_init_rings(struct tg3
*tp
)
6314 /* Free up all the SKBs. */
6317 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
6318 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
6320 tnapi
->last_tag
= 0;
6321 tnapi
->last_irq_tag
= 0;
6322 tnapi
->hw_status
->status
= 0;
6323 tnapi
->hw_status
->status_tag
= 0;
6324 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
6329 memset(tnapi
->tx_ring
, 0, TG3_TX_RING_BYTES
);
6331 tnapi
->rx_rcb_ptr
= 0;
6333 memset(tnapi
->rx_rcb
, 0, TG3_RX_RCB_RING_BYTES(tp
));
6335 if (tg3_rx_prodring_alloc(tp
, &tnapi
->prodring
)) {
6345 * Must not be invoked with interrupt sources disabled and
6346 * the hardware shutdown down.
6348 static void tg3_free_consistent(struct tg3
*tp
)
6352 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
6353 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
6355 if (tnapi
->tx_ring
) {
6356 pci_free_consistent(tp
->pdev
, TG3_TX_RING_BYTES
,
6357 tnapi
->tx_ring
, tnapi
->tx_desc_mapping
);
6358 tnapi
->tx_ring
= NULL
;
6361 kfree(tnapi
->tx_buffers
);
6362 tnapi
->tx_buffers
= NULL
;
6364 if (tnapi
->rx_rcb
) {
6365 pci_free_consistent(tp
->pdev
, TG3_RX_RCB_RING_BYTES(tp
),
6367 tnapi
->rx_rcb_mapping
);
6368 tnapi
->rx_rcb
= NULL
;
6371 tg3_rx_prodring_fini(tp
, &tnapi
->prodring
);
6373 if (tnapi
->hw_status
) {
6374 pci_free_consistent(tp
->pdev
, TG3_HW_STATUS_SIZE
,
6376 tnapi
->status_mapping
);
6377 tnapi
->hw_status
= NULL
;
6382 pci_free_consistent(tp
->pdev
, sizeof(struct tg3_hw_stats
),
6383 tp
->hw_stats
, tp
->stats_mapping
);
6384 tp
->hw_stats
= NULL
;
6389 * Must not be invoked with interrupt sources disabled and
6390 * the hardware shutdown down. Can sleep.
6392 static int tg3_alloc_consistent(struct tg3
*tp
)
6396 tp
->hw_stats
= pci_alloc_consistent(tp
->pdev
,
6397 sizeof(struct tg3_hw_stats
),
6398 &tp
->stats_mapping
);
6402 memset(tp
->hw_stats
, 0, sizeof(struct tg3_hw_stats
));
6404 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
6405 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
6406 struct tg3_hw_status
*sblk
;
6408 tnapi
->hw_status
= pci_alloc_consistent(tp
->pdev
,
6410 &tnapi
->status_mapping
);
6411 if (!tnapi
->hw_status
)
6414 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
6415 sblk
= tnapi
->hw_status
;
6417 if (tg3_rx_prodring_init(tp
, &tnapi
->prodring
))
6420 /* If multivector TSS is enabled, vector 0 does not handle
6421 * tx interrupts. Don't allocate any resources for it.
6423 if ((!i
&& !(tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)) ||
6424 (i
&& (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
))) {
6425 tnapi
->tx_buffers
= kzalloc(sizeof(struct ring_info
) *
6428 if (!tnapi
->tx_buffers
)
6431 tnapi
->tx_ring
= pci_alloc_consistent(tp
->pdev
,
6433 &tnapi
->tx_desc_mapping
);
6434 if (!tnapi
->tx_ring
)
6439 * When RSS is enabled, the status block format changes
6440 * slightly. The "rx_jumbo_consumer", "reserved",
6441 * and "rx_mini_consumer" members get mapped to the
6442 * other three rx return ring producer indexes.
6446 tnapi
->rx_rcb_prod_idx
= &sblk
->idx
[0].rx_producer
;
6449 tnapi
->rx_rcb_prod_idx
= &sblk
->rx_jumbo_consumer
;
6452 tnapi
->rx_rcb_prod_idx
= &sblk
->reserved
;
6455 tnapi
->rx_rcb_prod_idx
= &sblk
->rx_mini_consumer
;
6460 * If multivector RSS is enabled, vector 0 does not handle
6461 * rx or tx interrupts. Don't allocate any resources for it.
6463 if (!i
&& (tp
->tg3_flags3
& TG3_FLG3_ENABLE_RSS
))
6466 tnapi
->rx_rcb
= pci_alloc_consistent(tp
->pdev
,
6467 TG3_RX_RCB_RING_BYTES(tp
),
6468 &tnapi
->rx_rcb_mapping
);
6472 memset(tnapi
->rx_rcb
, 0, TG3_RX_RCB_RING_BYTES(tp
));
6478 tg3_free_consistent(tp
);
6482 #define MAX_WAIT_CNT 1000
6484 /* To stop a block, clear the enable bit and poll till it
6485 * clears. tp->lock is held.
6487 static int tg3_stop_block(struct tg3
*tp
, unsigned long ofs
, u32 enable_bit
, int silent
)
6492 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
6499 /* We can't enable/disable these bits of the
6500 * 5705/5750, just say success.
6513 for (i
= 0; i
< MAX_WAIT_CNT
; i
++) {
6516 if ((val
& enable_bit
) == 0)
6520 if (i
== MAX_WAIT_CNT
&& !silent
) {
6521 dev_err(&tp
->pdev
->dev
,
6522 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6530 /* tp->lock is held. */
6531 static int tg3_abort_hw(struct tg3
*tp
, int silent
)
6535 tg3_disable_ints(tp
);
6537 tp
->rx_mode
&= ~RX_MODE_ENABLE
;
6538 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
6541 err
= tg3_stop_block(tp
, RCVBDI_MODE
, RCVBDI_MODE_ENABLE
, silent
);
6542 err
|= tg3_stop_block(tp
, RCVLPC_MODE
, RCVLPC_MODE_ENABLE
, silent
);
6543 err
|= tg3_stop_block(tp
, RCVLSC_MODE
, RCVLSC_MODE_ENABLE
, silent
);
6544 err
|= tg3_stop_block(tp
, RCVDBDI_MODE
, RCVDBDI_MODE_ENABLE
, silent
);
6545 err
|= tg3_stop_block(tp
, RCVDCC_MODE
, RCVDCC_MODE_ENABLE
, silent
);
6546 err
|= tg3_stop_block(tp
, RCVCC_MODE
, RCVCC_MODE_ENABLE
, silent
);
6548 err
|= tg3_stop_block(tp
, SNDBDS_MODE
, SNDBDS_MODE_ENABLE
, silent
);
6549 err
|= tg3_stop_block(tp
, SNDBDI_MODE
, SNDBDI_MODE_ENABLE
, silent
);
6550 err
|= tg3_stop_block(tp
, SNDDATAI_MODE
, SNDDATAI_MODE_ENABLE
, silent
);
6551 err
|= tg3_stop_block(tp
, RDMAC_MODE
, RDMAC_MODE_ENABLE
, silent
);
6552 err
|= tg3_stop_block(tp
, SNDDATAC_MODE
, SNDDATAC_MODE_ENABLE
, silent
);
6553 err
|= tg3_stop_block(tp
, DMAC_MODE
, DMAC_MODE_ENABLE
, silent
);
6554 err
|= tg3_stop_block(tp
, SNDBDC_MODE
, SNDBDC_MODE_ENABLE
, silent
);
6556 tp
->mac_mode
&= ~MAC_MODE_TDE_ENABLE
;
6557 tw32_f(MAC_MODE
, tp
->mac_mode
);
6560 tp
->tx_mode
&= ~TX_MODE_ENABLE
;
6561 tw32_f(MAC_TX_MODE
, tp
->tx_mode
);
6563 for (i
= 0; i
< MAX_WAIT_CNT
; i
++) {
6565 if (!(tr32(MAC_TX_MODE
) & TX_MODE_ENABLE
))
6568 if (i
>= MAX_WAIT_CNT
) {
6569 dev_err(&tp
->pdev
->dev
,
6570 "%s timed out, TX_MODE_ENABLE will not clear "
6571 "MAC_TX_MODE=%08x\n", __func__
, tr32(MAC_TX_MODE
));
6575 err
|= tg3_stop_block(tp
, HOSTCC_MODE
, HOSTCC_MODE_ENABLE
, silent
);
6576 err
|= tg3_stop_block(tp
, WDMAC_MODE
, WDMAC_MODE_ENABLE
, silent
);
6577 err
|= tg3_stop_block(tp
, MBFREE_MODE
, MBFREE_MODE_ENABLE
, silent
);
6579 tw32(FTQ_RESET
, 0xffffffff);
6580 tw32(FTQ_RESET
, 0x00000000);
6582 err
|= tg3_stop_block(tp
, BUFMGR_MODE
, BUFMGR_MODE_ENABLE
, silent
);
6583 err
|= tg3_stop_block(tp
, MEMARB_MODE
, MEMARB_MODE_ENABLE
, silent
);
6585 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
6586 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
6587 if (tnapi
->hw_status
)
6588 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
6591 memset(tp
->hw_stats
, 0, sizeof(struct tg3_hw_stats
));
6596 static void tg3_ape_send_event(struct tg3
*tp
, u32 event
)
6601 /* NCSI does not support APE events */
6602 if (tp
->tg3_flags3
& TG3_FLG3_APE_HAS_NCSI
)
6605 apedata
= tg3_ape_read32(tp
, TG3_APE_SEG_SIG
);
6606 if (apedata
!= APE_SEG_SIG_MAGIC
)
6609 apedata
= tg3_ape_read32(tp
, TG3_APE_FW_STATUS
);
6610 if (!(apedata
& APE_FW_STATUS_READY
))
6613 /* Wait for up to 1 millisecond for APE to service previous event. */
6614 for (i
= 0; i
< 10; i
++) {
6615 if (tg3_ape_lock(tp
, TG3_APE_LOCK_MEM
))
6618 apedata
= tg3_ape_read32(tp
, TG3_APE_EVENT_STATUS
);
6620 if (!(apedata
& APE_EVENT_STATUS_EVENT_PENDING
))
6621 tg3_ape_write32(tp
, TG3_APE_EVENT_STATUS
,
6622 event
| APE_EVENT_STATUS_EVENT_PENDING
);
6624 tg3_ape_unlock(tp
, TG3_APE_LOCK_MEM
);
6626 if (!(apedata
& APE_EVENT_STATUS_EVENT_PENDING
))
6632 if (!(apedata
& APE_EVENT_STATUS_EVENT_PENDING
))
6633 tg3_ape_write32(tp
, TG3_APE_EVENT
, APE_EVENT_1
);
6636 static void tg3_ape_driver_state_change(struct tg3
*tp
, int kind
)
6641 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
))
6645 case RESET_KIND_INIT
:
6646 tg3_ape_write32(tp
, TG3_APE_HOST_SEG_SIG
,
6647 APE_HOST_SEG_SIG_MAGIC
);
6648 tg3_ape_write32(tp
, TG3_APE_HOST_SEG_LEN
,
6649 APE_HOST_SEG_LEN_MAGIC
);
6650 apedata
= tg3_ape_read32(tp
, TG3_APE_HOST_INIT_COUNT
);
6651 tg3_ape_write32(tp
, TG3_APE_HOST_INIT_COUNT
, ++apedata
);
6652 tg3_ape_write32(tp
, TG3_APE_HOST_DRIVER_ID
,
6653 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM
, TG3_MIN_NUM
));
6654 tg3_ape_write32(tp
, TG3_APE_HOST_BEHAVIOR
,
6655 APE_HOST_BEHAV_NO_PHYLOCK
);
6656 tg3_ape_write32(tp
, TG3_APE_HOST_DRVR_STATE
,
6657 TG3_APE_HOST_DRVR_STATE_START
);
6659 event
= APE_EVENT_STATUS_STATE_START
;
6661 case RESET_KIND_SHUTDOWN
:
6662 /* With the interface we are currently using,
6663 * APE does not track driver state. Wiping
6664 * out the HOST SEGMENT SIGNATURE forces
6665 * the APE to assume OS absent status.
6667 tg3_ape_write32(tp
, TG3_APE_HOST_SEG_SIG
, 0x0);
6669 if (device_may_wakeup(&tp
->pdev
->dev
) &&
6670 (tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
)) {
6671 tg3_ape_write32(tp
, TG3_APE_HOST_WOL_SPEED
,
6672 TG3_APE_HOST_WOL_SPEED_AUTO
);
6673 apedata
= TG3_APE_HOST_DRVR_STATE_WOL
;
6675 apedata
= TG3_APE_HOST_DRVR_STATE_UNLOAD
;
6677 tg3_ape_write32(tp
, TG3_APE_HOST_DRVR_STATE
, apedata
);
6679 event
= APE_EVENT_STATUS_STATE_UNLOAD
;
6681 case RESET_KIND_SUSPEND
:
6682 event
= APE_EVENT_STATUS_STATE_SUSPEND
;
6688 event
|= APE_EVENT_STATUS_DRIVER_EVNT
| APE_EVENT_STATUS_STATE_CHNGE
;
6690 tg3_ape_send_event(tp
, event
);
6693 /* tp->lock is held. */
6694 static void tg3_write_sig_pre_reset(struct tg3
*tp
, int kind
)
6696 tg3_write_mem(tp
, NIC_SRAM_FIRMWARE_MBOX
,
6697 NIC_SRAM_FIRMWARE_MBOX_MAGIC1
);
6699 if (tp
->tg3_flags2
& TG3_FLG2_ASF_NEW_HANDSHAKE
) {
6701 case RESET_KIND_INIT
:
6702 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6706 case RESET_KIND_SHUTDOWN
:
6707 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6711 case RESET_KIND_SUSPEND
:
6712 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6721 if (kind
== RESET_KIND_INIT
||
6722 kind
== RESET_KIND_SUSPEND
)
6723 tg3_ape_driver_state_change(tp
, kind
);
6726 /* tp->lock is held. */
6727 static void tg3_write_sig_post_reset(struct tg3
*tp
, int kind
)
6729 if (tp
->tg3_flags2
& TG3_FLG2_ASF_NEW_HANDSHAKE
) {
6731 case RESET_KIND_INIT
:
6732 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6733 DRV_STATE_START_DONE
);
6736 case RESET_KIND_SHUTDOWN
:
6737 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6738 DRV_STATE_UNLOAD_DONE
);
6746 if (kind
== RESET_KIND_SHUTDOWN
)
6747 tg3_ape_driver_state_change(tp
, kind
);
6750 /* tp->lock is held. */
6751 static void tg3_write_sig_legacy(struct tg3
*tp
, int kind
)
6753 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) {
6755 case RESET_KIND_INIT
:
6756 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6760 case RESET_KIND_SHUTDOWN
:
6761 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6765 case RESET_KIND_SUSPEND
:
6766 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6776 static int tg3_poll_fw(struct tg3
*tp
)
6781 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
6782 /* Wait up to 20ms for init done. */
6783 for (i
= 0; i
< 200; i
++) {
6784 if (tr32(VCPU_STATUS
) & VCPU_STATUS_INIT_DONE
)
6791 /* Wait for firmware initialization to complete. */
6792 for (i
= 0; i
< 100000; i
++) {
6793 tg3_read_mem(tp
, NIC_SRAM_FIRMWARE_MBOX
, &val
);
6794 if (val
== ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1
)
6799 /* Chip might not be fitted with firmware. Some Sun onboard
6800 * parts are configured like that. So don't signal the timeout
6801 * of the above loop as an error, but do report the lack of
6802 * running firmware once.
6805 !(tp
->tg3_flags2
& TG3_FLG2_NO_FWARE_REPORTED
)) {
6806 tp
->tg3_flags2
|= TG3_FLG2_NO_FWARE_REPORTED
;
6808 netdev_info(tp
->dev
, "No firmware running\n");
6811 if (tp
->pci_chip_rev_id
== CHIPREV_ID_57765_A0
) {
6812 /* The 57765 A0 needs a little more
6813 * time to do some important work.
6821 /* Save PCI command register before chip reset */
6822 static void tg3_save_pci_state(struct tg3
*tp
)
6824 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &tp
->pci_cmd
);
6827 /* Restore PCI state after chip reset */
6828 static void tg3_restore_pci_state(struct tg3
*tp
)
6832 /* Re-enable indirect register accesses. */
6833 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
6834 tp
->misc_host_ctrl
);
6836 /* Set MAX PCI retry to zero. */
6837 val
= (PCISTATE_ROM_ENABLE
| PCISTATE_ROM_RETRY_ENABLE
);
6838 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
&&
6839 (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
))
6840 val
|= PCISTATE_RETRY_SAME_DMA
;
6841 /* Allow reads and writes to the APE register and memory space. */
6842 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
6843 val
|= PCISTATE_ALLOW_APE_CTLSPC_WR
|
6844 PCISTATE_ALLOW_APE_SHMEM_WR
|
6845 PCISTATE_ALLOW_APE_PSPACE_WR
;
6846 pci_write_config_dword(tp
->pdev
, TG3PCI_PCISTATE
, val
);
6848 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, tp
->pci_cmd
);
6850 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5785
) {
6851 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)
6852 pcie_set_readrq(tp
->pdev
, 4096);
6854 pci_write_config_byte(tp
->pdev
, PCI_CACHE_LINE_SIZE
,
6855 tp
->pci_cacheline_sz
);
6856 pci_write_config_byte(tp
->pdev
, PCI_LATENCY_TIMER
,
6861 /* Make sure PCI-X relaxed ordering bit is clear. */
6862 if (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) {
6865 pci_read_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
6867 pcix_cmd
&= ~PCI_X_CMD_ERO
;
6868 pci_write_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
6872 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) {
6874 /* Chip reset on 5780 will reset MSI enable bit,
6875 * so need to restore it.
6877 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
6880 pci_read_config_word(tp
->pdev
,
6881 tp
->msi_cap
+ PCI_MSI_FLAGS
,
6883 pci_write_config_word(tp
->pdev
,
6884 tp
->msi_cap
+ PCI_MSI_FLAGS
,
6885 ctrl
| PCI_MSI_FLAGS_ENABLE
);
6886 val
= tr32(MSGINT_MODE
);
6887 tw32(MSGINT_MODE
, val
| MSGINT_MODE_ENABLE
);
6892 static void tg3_stop_fw(struct tg3
*);
6894 /* tp->lock is held. */
6895 static int tg3_chip_reset(struct tg3
*tp
)
6898 void (*write_op
)(struct tg3
*, u32
, u32
);
6903 tg3_ape_lock(tp
, TG3_APE_LOCK_GRC
);
6905 /* No matching tg3_nvram_unlock() after this because
6906 * chip reset below will undo the nvram lock.
6908 tp
->nvram_lock_cnt
= 0;
6910 /* GRC_MISC_CFG core clock reset will clear the memory
6911 * enable bit in PCI register 4 and the MSI enable bit
6912 * on some chips, so we save relevant registers here.
6914 tg3_save_pci_state(tp
);
6916 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
||
6917 (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
))
6918 tw32(GRC_FASTBOOT_PC
, 0);
6921 * We must avoid the readl() that normally takes place.
6922 * It locks machines, causes machine checks, and other
6923 * fun things. So, temporarily disable the 5701
6924 * hardware workaround, while we do the reset.
6926 write_op
= tp
->write32
;
6927 if (write_op
== tg3_write_flush_reg32
)
6928 tp
->write32
= tg3_write32
;
6930 /* Prevent the irq handler from reading or writing PCI registers
6931 * during chip reset when the memory enable bit in the PCI command
6932 * register may be cleared. The chip does not generate interrupt
6933 * at this time, but the irq handler may still be called due to irq
6934 * sharing or irqpoll.
6936 tp
->tg3_flags
|= TG3_FLAG_CHIP_RESETTING
;
6937 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
6938 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
6939 if (tnapi
->hw_status
) {
6940 tnapi
->hw_status
->status
= 0;
6941 tnapi
->hw_status
->status_tag
= 0;
6943 tnapi
->last_tag
= 0;
6944 tnapi
->last_irq_tag
= 0;
6948 for (i
= 0; i
< tp
->irq_cnt
; i
++)
6949 synchronize_irq(tp
->napi
[i
].irq_vec
);
6951 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
) {
6952 val
= tr32(TG3_PCIE_LNKCTL
) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN
;
6953 tw32(TG3_PCIE_LNKCTL
, val
| TG3_PCIE_LNKCTL_L1_PLL_PD_DIS
);
6957 val
= GRC_MISC_CFG_CORECLK_RESET
;
6959 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
6960 /* Force PCIe 1.0a mode */
6961 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5785
&&
6962 !(tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
) &&
6963 tr32(TG3_PCIE_PHY_TSTCTL
) ==
6964 (TG3_PCIE_PHY_TSTCTL_PCIE10
| TG3_PCIE_PHY_TSTCTL_PSCRAM
))
6965 tw32(TG3_PCIE_PHY_TSTCTL
, TG3_PCIE_PHY_TSTCTL_PSCRAM
);
6967 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
) {
6968 tw32(GRC_MISC_CFG
, (1 << 29));
6973 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
6974 tw32(VCPU_STATUS
, tr32(VCPU_STATUS
) | VCPU_STATUS_DRV_RESET
);
6975 tw32(GRC_VCPU_EXT_CTRL
,
6976 tr32(GRC_VCPU_EXT_CTRL
) & ~GRC_VCPU_EXT_CTRL_HALT_CPU
);
6979 /* Manage gphy power for all CPMU absent PCIe devices. */
6980 if ((tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
6981 !(tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
))
6982 val
|= GRC_MISC_CFG_KEEP_GPHY_POWER
;
6984 tw32(GRC_MISC_CFG
, val
);
6986 /* restore 5701 hardware bug workaround write method */
6987 tp
->write32
= write_op
;
6989 /* Unfortunately, we have to delay before the PCI read back.
6990 * Some 575X chips even will not respond to a PCI cfg access
6991 * when the reset command is given to the chip.
6993 * How do these hardware designers expect things to work
6994 * properly if the PCI write is posted for a long period
6995 * of time? It is always necessary to have some method by
6996 * which a register read back can occur to push the write
6997 * out which does the reset.
6999 * For most tg3 variants the trick below was working.
7004 /* Flush PCI posted writes. The normal MMIO registers
7005 * are inaccessible at this time so this is the only
7006 * way to make this reliably (actually, this is no longer
7007 * the case, see above). I tried to use indirect
7008 * register read/write but this upset some 5701 variants.
7010 pci_read_config_dword(tp
->pdev
, PCI_COMMAND
, &val
);
7014 if ((tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) && tp
->pcie_cap
) {
7017 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5750_A0
) {
7021 /* Wait for link training to complete. */
7022 for (i
= 0; i
< 5000; i
++)
7025 pci_read_config_dword(tp
->pdev
, 0xc4, &cfg_val
);
7026 pci_write_config_dword(tp
->pdev
, 0xc4,
7027 cfg_val
| (1 << 15));
7030 /* Clear the "no snoop" and "relaxed ordering" bits. */
7031 pci_read_config_word(tp
->pdev
,
7032 tp
->pcie_cap
+ PCI_EXP_DEVCTL
,
7034 val16
&= ~(PCI_EXP_DEVCTL_RELAX_EN
|
7035 PCI_EXP_DEVCTL_NOSNOOP_EN
);
7037 * Older PCIe devices only support the 128 byte
7038 * MPS setting. Enforce the restriction.
7040 if (!(tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
))
7041 val16
&= ~PCI_EXP_DEVCTL_PAYLOAD
;
7042 pci_write_config_word(tp
->pdev
,
7043 tp
->pcie_cap
+ PCI_EXP_DEVCTL
,
7046 pcie_set_readrq(tp
->pdev
, 4096);
7048 /* Clear error status */
7049 pci_write_config_word(tp
->pdev
,
7050 tp
->pcie_cap
+ PCI_EXP_DEVSTA
,
7051 PCI_EXP_DEVSTA_CED
|
7052 PCI_EXP_DEVSTA_NFED
|
7053 PCI_EXP_DEVSTA_FED
|
7054 PCI_EXP_DEVSTA_URD
);
7057 tg3_restore_pci_state(tp
);
7059 tp
->tg3_flags
&= ~TG3_FLAG_CHIP_RESETTING
;
7062 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)
7063 val
= tr32(MEMARB_MODE
);
7064 tw32(MEMARB_MODE
, val
| MEMARB_MODE_ENABLE
);
7066 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5750_A3
) {
7068 tw32(0x5000, 0x400);
7071 tw32(GRC_MODE
, tp
->grc_mode
);
7073 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A0
) {
7076 tw32(0xc4, val
| (1 << 15));
7079 if ((tp
->nic_sram_data_cfg
& NIC_SRAM_DATA_CFG_MINI_PCI
) != 0 &&
7080 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
7081 tp
->pci_clock_ctrl
|= CLOCK_CTRL_CLKRUN_OENABLE
;
7082 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A0
)
7083 tp
->pci_clock_ctrl
|= CLOCK_CTRL_FORCE_CLKRUN
;
7084 tw32(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
);
7087 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) {
7088 tp
->mac_mode
= MAC_MODE_PORT_MODE_TBI
;
7089 tw32_f(MAC_MODE
, tp
->mac_mode
);
7090 } else if (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
) {
7091 tp
->mac_mode
= MAC_MODE_PORT_MODE_GMII
;
7092 tw32_f(MAC_MODE
, tp
->mac_mode
);
7093 } else if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
7094 tp
->mac_mode
&= (MAC_MODE_APE_TX_EN
| MAC_MODE_APE_RX_EN
);
7095 if (tp
->mac_mode
& MAC_MODE_APE_TX_EN
)
7096 tp
->mac_mode
|= MAC_MODE_TDE_ENABLE
;
7097 tw32_f(MAC_MODE
, tp
->mac_mode
);
7099 tw32_f(MAC_MODE
, 0);
7102 tg3_ape_unlock(tp
, TG3_APE_LOCK_GRC
);
7104 err
= tg3_poll_fw(tp
);
7110 if ((tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) &&
7111 tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
&&
7112 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5785
&&
7113 !(tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
)) {
7116 tw32(0x7c00, val
| (1 << 25));
7119 /* Reprobe ASF enable state. */
7120 tp
->tg3_flags
&= ~TG3_FLAG_ENABLE_ASF
;
7121 tp
->tg3_flags2
&= ~TG3_FLG2_ASF_NEW_HANDSHAKE
;
7122 tg3_read_mem(tp
, NIC_SRAM_DATA_SIG
, &val
);
7123 if (val
== NIC_SRAM_DATA_SIG_MAGIC
) {
7126 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG
, &nic_cfg
);
7127 if (nic_cfg
& NIC_SRAM_DATA_CFG_ASF_ENABLE
) {
7128 tp
->tg3_flags
|= TG3_FLAG_ENABLE_ASF
;
7129 tp
->last_event_jiffies
= jiffies
;
7130 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
7131 tp
->tg3_flags2
|= TG3_FLG2_ASF_NEW_HANDSHAKE
;
7138 /* tp->lock is held. */
7139 static void tg3_stop_fw(struct tg3
*tp
)
7141 if ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) &&
7142 !(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)) {
7143 /* Wait for RX cpu to ACK the previous event. */
7144 tg3_wait_for_event_ack(tp
);
7146 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_MBOX
, FWCMD_NICDRV_PAUSE_FW
);
7148 tg3_generate_fw_event(tp
);
7150 /* Wait for RX cpu to ACK this event. */
7151 tg3_wait_for_event_ack(tp
);
7155 /* tp->lock is held. */
7156 static int tg3_halt(struct tg3
*tp
, int kind
, int silent
)
7162 tg3_write_sig_pre_reset(tp
, kind
);
7164 tg3_abort_hw(tp
, silent
);
7165 err
= tg3_chip_reset(tp
);
7167 __tg3_set_mac_addr(tp
, 0);
7169 tg3_write_sig_legacy(tp
, kind
);
7170 tg3_write_sig_post_reset(tp
, kind
);
7178 #define RX_CPU_SCRATCH_BASE 0x30000
7179 #define RX_CPU_SCRATCH_SIZE 0x04000
7180 #define TX_CPU_SCRATCH_BASE 0x34000
7181 #define TX_CPU_SCRATCH_SIZE 0x04000
7183 /* tp->lock is held. */
7184 static int tg3_halt_cpu(struct tg3
*tp
, u32 offset
)
7188 BUG_ON(offset
== TX_CPU_BASE
&&
7189 (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
));
7191 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
7192 u32 val
= tr32(GRC_VCPU_EXT_CTRL
);
7194 tw32(GRC_VCPU_EXT_CTRL
, val
| GRC_VCPU_EXT_CTRL_HALT_CPU
);
7197 if (offset
== RX_CPU_BASE
) {
7198 for (i
= 0; i
< 10000; i
++) {
7199 tw32(offset
+ CPU_STATE
, 0xffffffff);
7200 tw32(offset
+ CPU_MODE
, CPU_MODE_HALT
);
7201 if (tr32(offset
+ CPU_MODE
) & CPU_MODE_HALT
)
7205 tw32(offset
+ CPU_STATE
, 0xffffffff);
7206 tw32_f(offset
+ CPU_MODE
, CPU_MODE_HALT
);
7209 for (i
= 0; i
< 10000; i
++) {
7210 tw32(offset
+ CPU_STATE
, 0xffffffff);
7211 tw32(offset
+ CPU_MODE
, CPU_MODE_HALT
);
7212 if (tr32(offset
+ CPU_MODE
) & CPU_MODE_HALT
)
7218 netdev_err(tp
->dev
, "%s timed out, %s CPU\n",
7219 __func__
, offset
== RX_CPU_BASE
? "RX" : "TX");
7223 /* Clear firmware's nvram arbitration. */
7224 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
)
7225 tw32(NVRAM_SWARB
, SWARB_REQ_CLR0
);
7230 unsigned int fw_base
;
7231 unsigned int fw_len
;
7232 const __be32
*fw_data
;
7235 /* tp->lock is held. */
7236 static int tg3_load_firmware_cpu(struct tg3
*tp
, u32 cpu_base
, u32 cpu_scratch_base
,
7237 int cpu_scratch_size
, struct fw_info
*info
)
7239 int err
, lock_err
, i
;
7240 void (*write_op
)(struct tg3
*, u32
, u32
);
7242 if (cpu_base
== TX_CPU_BASE
&&
7243 (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
7245 "%s: Trying to load TX cpu firmware which is 5705\n",
7250 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
7251 write_op
= tg3_write_mem
;
7253 write_op
= tg3_write_indirect_reg32
;
7255 /* It is possible that bootcode is still loading at this point.
7256 * Get the nvram lock first before halting the cpu.
7258 lock_err
= tg3_nvram_lock(tp
);
7259 err
= tg3_halt_cpu(tp
, cpu_base
);
7261 tg3_nvram_unlock(tp
);
7265 for (i
= 0; i
< cpu_scratch_size
; i
+= sizeof(u32
))
7266 write_op(tp
, cpu_scratch_base
+ i
, 0);
7267 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
7268 tw32(cpu_base
+ CPU_MODE
, tr32(cpu_base
+CPU_MODE
)|CPU_MODE_HALT
);
7269 for (i
= 0; i
< (info
->fw_len
/ sizeof(u32
)); i
++)
7270 write_op(tp
, (cpu_scratch_base
+
7271 (info
->fw_base
& 0xffff) +
7273 be32_to_cpu(info
->fw_data
[i
]));
7281 /* tp->lock is held. */
7282 static int tg3_load_5701_a0_firmware_fix(struct tg3
*tp
)
7284 struct fw_info info
;
7285 const __be32
*fw_data
;
7288 fw_data
= (void *)tp
->fw
->data
;
7290 /* Firmware blob starts with version numbers, followed by
7291 start address and length. We are setting complete length.
7292 length = end_address_of_bss - start_address_of_text.
7293 Remainder is the blob to be loaded contiguously
7294 from start address. */
7296 info
.fw_base
= be32_to_cpu(fw_data
[1]);
7297 info
.fw_len
= tp
->fw
->size
- 12;
7298 info
.fw_data
= &fw_data
[3];
7300 err
= tg3_load_firmware_cpu(tp
, RX_CPU_BASE
,
7301 RX_CPU_SCRATCH_BASE
, RX_CPU_SCRATCH_SIZE
,
7306 err
= tg3_load_firmware_cpu(tp
, TX_CPU_BASE
,
7307 TX_CPU_SCRATCH_BASE
, TX_CPU_SCRATCH_SIZE
,
7312 /* Now startup only the RX cpu. */
7313 tw32(RX_CPU_BASE
+ CPU_STATE
, 0xffffffff);
7314 tw32_f(RX_CPU_BASE
+ CPU_PC
, info
.fw_base
);
7316 for (i
= 0; i
< 5; i
++) {
7317 if (tr32(RX_CPU_BASE
+ CPU_PC
) == info
.fw_base
)
7319 tw32(RX_CPU_BASE
+ CPU_STATE
, 0xffffffff);
7320 tw32(RX_CPU_BASE
+ CPU_MODE
, CPU_MODE_HALT
);
7321 tw32_f(RX_CPU_BASE
+ CPU_PC
, info
.fw_base
);
7325 netdev_err(tp
->dev
, "%s fails to set RX CPU PC, is %08x "
7326 "should be %08x\n", __func__
,
7327 tr32(RX_CPU_BASE
+ CPU_PC
), info
.fw_base
);
7330 tw32(RX_CPU_BASE
+ CPU_STATE
, 0xffffffff);
7331 tw32_f(RX_CPU_BASE
+ CPU_MODE
, 0x00000000);
7336 /* 5705 needs a special version of the TSO firmware. */
7338 /* tp->lock is held. */
7339 static int tg3_load_tso_firmware(struct tg3
*tp
)
7341 struct fw_info info
;
7342 const __be32
*fw_data
;
7343 unsigned long cpu_base
, cpu_scratch_base
, cpu_scratch_size
;
7346 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
7349 fw_data
= (void *)tp
->fw
->data
;
7351 /* Firmware blob starts with version numbers, followed by
7352 start address and length. We are setting complete length.
7353 length = end_address_of_bss - start_address_of_text.
7354 Remainder is the blob to be loaded contiguously
7355 from start address. */
7357 info
.fw_base
= be32_to_cpu(fw_data
[1]);
7358 cpu_scratch_size
= tp
->fw_len
;
7359 info
.fw_len
= tp
->fw
->size
- 12;
7360 info
.fw_data
= &fw_data
[3];
7362 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
7363 cpu_base
= RX_CPU_BASE
;
7364 cpu_scratch_base
= NIC_SRAM_MBUF_POOL_BASE5705
;
7366 cpu_base
= TX_CPU_BASE
;
7367 cpu_scratch_base
= TX_CPU_SCRATCH_BASE
;
7368 cpu_scratch_size
= TX_CPU_SCRATCH_SIZE
;
7371 err
= tg3_load_firmware_cpu(tp
, cpu_base
,
7372 cpu_scratch_base
, cpu_scratch_size
,
7377 /* Now startup the cpu. */
7378 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
7379 tw32_f(cpu_base
+ CPU_PC
, info
.fw_base
);
7381 for (i
= 0; i
< 5; i
++) {
7382 if (tr32(cpu_base
+ CPU_PC
) == info
.fw_base
)
7384 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
7385 tw32(cpu_base
+ CPU_MODE
, CPU_MODE_HALT
);
7386 tw32_f(cpu_base
+ CPU_PC
, info
.fw_base
);
7391 "%s fails to set CPU PC, is %08x should be %08x\n",
7392 __func__
, tr32(cpu_base
+ CPU_PC
), info
.fw_base
);
7395 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
7396 tw32_f(cpu_base
+ CPU_MODE
, 0x00000000);
7401 static int tg3_set_mac_addr(struct net_device
*dev
, void *p
)
7403 struct tg3
*tp
= netdev_priv(dev
);
7404 struct sockaddr
*addr
= p
;
7405 int err
= 0, skip_mac_1
= 0;
7407 if (!is_valid_ether_addr(addr
->sa_data
))
7410 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
7412 if (!netif_running(dev
))
7415 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) {
7416 u32 addr0_high
, addr0_low
, addr1_high
, addr1_low
;
7418 addr0_high
= tr32(MAC_ADDR_0_HIGH
);
7419 addr0_low
= tr32(MAC_ADDR_0_LOW
);
7420 addr1_high
= tr32(MAC_ADDR_1_HIGH
);
7421 addr1_low
= tr32(MAC_ADDR_1_LOW
);
7423 /* Skip MAC addr 1 if ASF is using it. */
7424 if ((addr0_high
!= addr1_high
|| addr0_low
!= addr1_low
) &&
7425 !(addr1_high
== 0 && addr1_low
== 0))
7428 spin_lock_bh(&tp
->lock
);
7429 __tg3_set_mac_addr(tp
, skip_mac_1
);
7430 spin_unlock_bh(&tp
->lock
);
7435 /* tp->lock is held. */
7436 static void tg3_set_bdinfo(struct tg3
*tp
, u32 bdinfo_addr
,
7437 dma_addr_t mapping
, u32 maxlen_flags
,
7441 (bdinfo_addr
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_HIGH
),
7442 ((u64
) mapping
>> 32));
7444 (bdinfo_addr
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_LOW
),
7445 ((u64
) mapping
& 0xffffffff));
7447 (bdinfo_addr
+ TG3_BDINFO_MAXLEN_FLAGS
),
7450 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
7452 (bdinfo_addr
+ TG3_BDINFO_NIC_ADDR
),
7456 static void __tg3_set_rx_mode(struct net_device
*);
7457 static void __tg3_set_coalesce(struct tg3
*tp
, struct ethtool_coalesce
*ec
)
7461 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)) {
7462 tw32(HOSTCC_TXCOL_TICKS
, ec
->tx_coalesce_usecs
);
7463 tw32(HOSTCC_TXMAX_FRAMES
, ec
->tx_max_coalesced_frames
);
7464 tw32(HOSTCC_TXCOAL_MAXF_INT
, ec
->tx_max_coalesced_frames_irq
);
7466 tw32(HOSTCC_TXCOL_TICKS
, 0);
7467 tw32(HOSTCC_TXMAX_FRAMES
, 0);
7468 tw32(HOSTCC_TXCOAL_MAXF_INT
, 0);
7471 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_RSS
)) {
7472 tw32(HOSTCC_RXCOL_TICKS
, ec
->rx_coalesce_usecs
);
7473 tw32(HOSTCC_RXMAX_FRAMES
, ec
->rx_max_coalesced_frames
);
7474 tw32(HOSTCC_RXCOAL_MAXF_INT
, ec
->rx_max_coalesced_frames_irq
);
7476 tw32(HOSTCC_RXCOL_TICKS
, 0);
7477 tw32(HOSTCC_RXMAX_FRAMES
, 0);
7478 tw32(HOSTCC_RXCOAL_MAXF_INT
, 0);
7481 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
7482 u32 val
= ec
->stats_block_coalesce_usecs
;
7484 tw32(HOSTCC_RXCOAL_TICK_INT
, ec
->rx_coalesce_usecs_irq
);
7485 tw32(HOSTCC_TXCOAL_TICK_INT
, ec
->tx_coalesce_usecs_irq
);
7487 if (!netif_carrier_ok(tp
->dev
))
7490 tw32(HOSTCC_STAT_COAL_TICKS
, val
);
7493 for (i
= 0; i
< tp
->irq_cnt
- 1; i
++) {
7496 reg
= HOSTCC_RXCOL_TICKS_VEC1
+ i
* 0x18;
7497 tw32(reg
, ec
->rx_coalesce_usecs
);
7498 reg
= HOSTCC_RXMAX_FRAMES_VEC1
+ i
* 0x18;
7499 tw32(reg
, ec
->rx_max_coalesced_frames
);
7500 reg
= HOSTCC_RXCOAL_MAXF_INT_VEC1
+ i
* 0x18;
7501 tw32(reg
, ec
->rx_max_coalesced_frames_irq
);
7503 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
) {
7504 reg
= HOSTCC_TXCOL_TICKS_VEC1
+ i
* 0x18;
7505 tw32(reg
, ec
->tx_coalesce_usecs
);
7506 reg
= HOSTCC_TXMAX_FRAMES_VEC1
+ i
* 0x18;
7507 tw32(reg
, ec
->tx_max_coalesced_frames
);
7508 reg
= HOSTCC_TXCOAL_MAXF_INT_VEC1
+ i
* 0x18;
7509 tw32(reg
, ec
->tx_max_coalesced_frames_irq
);
7513 for (; i
< tp
->irq_max
- 1; i
++) {
7514 tw32(HOSTCC_RXCOL_TICKS_VEC1
+ i
* 0x18, 0);
7515 tw32(HOSTCC_RXMAX_FRAMES_VEC1
+ i
* 0x18, 0);
7516 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1
+ i
* 0x18, 0);
7518 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
) {
7519 tw32(HOSTCC_TXCOL_TICKS_VEC1
+ i
* 0x18, 0);
7520 tw32(HOSTCC_TXMAX_FRAMES_VEC1
+ i
* 0x18, 0);
7521 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1
+ i
* 0x18, 0);
7526 /* tp->lock is held. */
7527 static void tg3_rings_reset(struct tg3
*tp
)
7530 u32 stblk
, txrcb
, rxrcb
, limit
;
7531 struct tg3_napi
*tnapi
= &tp
->napi
[0];
7533 /* Disable all transmit rings but the first. */
7534 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
7535 limit
= NIC_SRAM_SEND_RCB
+ TG3_BDINFO_SIZE
* 16;
7536 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
7537 limit
= NIC_SRAM_SEND_RCB
+ TG3_BDINFO_SIZE
* 2;
7539 limit
= NIC_SRAM_SEND_RCB
+ TG3_BDINFO_SIZE
;
7541 for (txrcb
= NIC_SRAM_SEND_RCB
+ TG3_BDINFO_SIZE
;
7542 txrcb
< limit
; txrcb
+= TG3_BDINFO_SIZE
)
7543 tg3_write_mem(tp
, txrcb
+ TG3_BDINFO_MAXLEN_FLAGS
,
7544 BDINFO_FLAGS_DISABLED
);
7547 /* Disable all receive return rings but the first. */
7548 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
7549 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
)
7550 limit
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
* 17;
7551 else if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
7552 limit
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
* 16;
7553 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
||
7554 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
7555 limit
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
* 4;
7557 limit
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
;
7559 for (rxrcb
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
;
7560 rxrcb
< limit
; rxrcb
+= TG3_BDINFO_SIZE
)
7561 tg3_write_mem(tp
, rxrcb
+ TG3_BDINFO_MAXLEN_FLAGS
,
7562 BDINFO_FLAGS_DISABLED
);
7564 /* Disable interrupts */
7565 tw32_mailbox_f(tp
->napi
[0].int_mbox
, 1);
7567 /* Zero mailbox registers. */
7568 if (tp
->tg3_flags
& TG3_FLAG_SUPPORT_MSIX
) {
7569 for (i
= 1; i
< tp
->irq_max
; i
++) {
7570 tp
->napi
[i
].tx_prod
= 0;
7571 tp
->napi
[i
].tx_cons
= 0;
7572 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)
7573 tw32_mailbox(tp
->napi
[i
].prodmbox
, 0);
7574 tw32_rx_mbox(tp
->napi
[i
].consmbox
, 0);
7575 tw32_mailbox_f(tp
->napi
[i
].int_mbox
, 1);
7577 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
))
7578 tw32_mailbox(tp
->napi
[0].prodmbox
, 0);
7580 tp
->napi
[0].tx_prod
= 0;
7581 tp
->napi
[0].tx_cons
= 0;
7582 tw32_mailbox(tp
->napi
[0].prodmbox
, 0);
7583 tw32_rx_mbox(tp
->napi
[0].consmbox
, 0);
7586 /* Make sure the NIC-based send BD rings are disabled. */
7587 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
7588 u32 mbox
= MAILBOX_SNDNIC_PROD_IDX_0
+ TG3_64BIT_REG_LOW
;
7589 for (i
= 0; i
< 16; i
++)
7590 tw32_tx_mbox(mbox
+ i
* 8, 0);
7593 txrcb
= NIC_SRAM_SEND_RCB
;
7594 rxrcb
= NIC_SRAM_RCV_RET_RCB
;
7596 /* Clear status block in ram. */
7597 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
7599 /* Set status block DMA address */
7600 tw32(HOSTCC_STATUS_BLK_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
7601 ((u64
) tnapi
->status_mapping
>> 32));
7602 tw32(HOSTCC_STATUS_BLK_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
7603 ((u64
) tnapi
->status_mapping
& 0xffffffff));
7605 if (tnapi
->tx_ring
) {
7606 tg3_set_bdinfo(tp
, txrcb
, tnapi
->tx_desc_mapping
,
7607 (TG3_TX_RING_SIZE
<<
7608 BDINFO_FLAGS_MAXLEN_SHIFT
),
7609 NIC_SRAM_TX_BUFFER_DESC
);
7610 txrcb
+= TG3_BDINFO_SIZE
;
7613 if (tnapi
->rx_rcb
) {
7614 tg3_set_bdinfo(tp
, rxrcb
, tnapi
->rx_rcb_mapping
,
7615 (TG3_RX_RCB_RING_SIZE(tp
) <<
7616 BDINFO_FLAGS_MAXLEN_SHIFT
), 0);
7617 rxrcb
+= TG3_BDINFO_SIZE
;
7620 stblk
= HOSTCC_STATBLCK_RING1
;
7622 for (i
= 1, tnapi
++; i
< tp
->irq_cnt
; i
++, tnapi
++) {
7623 u64 mapping
= (u64
)tnapi
->status_mapping
;
7624 tw32(stblk
+ TG3_64BIT_REG_HIGH
, mapping
>> 32);
7625 tw32(stblk
+ TG3_64BIT_REG_LOW
, mapping
& 0xffffffff);
7627 /* Clear status block in ram. */
7628 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
7630 if (tnapi
->tx_ring
) {
7631 tg3_set_bdinfo(tp
, txrcb
, tnapi
->tx_desc_mapping
,
7632 (TG3_TX_RING_SIZE
<<
7633 BDINFO_FLAGS_MAXLEN_SHIFT
),
7634 NIC_SRAM_TX_BUFFER_DESC
);
7635 txrcb
+= TG3_BDINFO_SIZE
;
7638 tg3_set_bdinfo(tp
, rxrcb
, tnapi
->rx_rcb_mapping
,
7639 (TG3_RX_RCB_RING_SIZE(tp
) <<
7640 BDINFO_FLAGS_MAXLEN_SHIFT
), 0);
7643 rxrcb
+= TG3_BDINFO_SIZE
;
7647 /* tp->lock is held. */
7648 static int tg3_reset_hw(struct tg3
*tp
, int reset_phy
)
7650 u32 val
, rdmac_mode
;
7652 struct tg3_rx_prodring_set
*tpr
= &tp
->napi
[0].prodring
;
7654 tg3_disable_ints(tp
);
7658 tg3_write_sig_pre_reset(tp
, RESET_KIND_INIT
);
7660 if (tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
)
7661 tg3_abort_hw(tp
, 1);
7666 err
= tg3_chip_reset(tp
);
7670 tg3_write_sig_legacy(tp
, RESET_KIND_INIT
);
7672 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
) {
7673 val
= tr32(TG3_CPMU_CTRL
);
7674 val
&= ~(CPMU_CTRL_LINK_AWARE_MODE
| CPMU_CTRL_LINK_IDLE_MODE
);
7675 tw32(TG3_CPMU_CTRL
, val
);
7677 val
= tr32(TG3_CPMU_LSPD_10MB_CLK
);
7678 val
&= ~CPMU_LSPD_10MB_MACCLK_MASK
;
7679 val
|= CPMU_LSPD_10MB_MACCLK_6_25
;
7680 tw32(TG3_CPMU_LSPD_10MB_CLK
, val
);
7682 val
= tr32(TG3_CPMU_LNK_AWARE_PWRMD
);
7683 val
&= ~CPMU_LNK_AWARE_MACCLK_MASK
;
7684 val
|= CPMU_LNK_AWARE_MACCLK_6_25
;
7685 tw32(TG3_CPMU_LNK_AWARE_PWRMD
, val
);
7687 val
= tr32(TG3_CPMU_HST_ACC
);
7688 val
&= ~CPMU_HST_ACC_MACCLK_MASK
;
7689 val
|= CPMU_HST_ACC_MACCLK_6_25
;
7690 tw32(TG3_CPMU_HST_ACC
, val
);
7693 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
) {
7694 val
= tr32(PCIE_PWR_MGMT_THRESH
) & ~PCIE_PWR_MGMT_L1_THRESH_MSK
;
7695 val
|= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN
|
7696 PCIE_PWR_MGMT_L1_THRESH_4MS
;
7697 tw32(PCIE_PWR_MGMT_THRESH
, val
);
7699 val
= tr32(TG3_PCIE_EIDLE_DELAY
) & ~TG3_PCIE_EIDLE_DELAY_MASK
;
7700 tw32(TG3_PCIE_EIDLE_DELAY
, val
| TG3_PCIE_EIDLE_DELAY_13_CLKS
);
7702 tw32(TG3_CORR_ERR_STAT
, TG3_CORR_ERR_STAT_CLEAR
);
7704 val
= tr32(TG3_PCIE_LNKCTL
) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN
;
7705 tw32(TG3_PCIE_LNKCTL
, val
| TG3_PCIE_LNKCTL_L1_PLL_PD_DIS
);
7708 if (tp
->tg3_flags3
& TG3_FLG3_L1PLLPD_EN
) {
7709 u32 grc_mode
= tr32(GRC_MODE
);
7711 /* Access the lower 1K of PL PCIE block registers. */
7712 val
= grc_mode
& ~GRC_MODE_PCIE_PORT_MASK
;
7713 tw32(GRC_MODE
, val
| GRC_MODE_PCIE_PL_SEL
);
7715 val
= tr32(TG3_PCIE_TLDLPL_PORT
+ TG3_PCIE_PL_LO_PHYCTL1
);
7716 tw32(TG3_PCIE_TLDLPL_PORT
+ TG3_PCIE_PL_LO_PHYCTL1
,
7717 val
| TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN
);
7719 tw32(GRC_MODE
, grc_mode
);
7722 if (tp
->pci_chip_rev_id
== CHIPREV_ID_57765_A0
) {
7723 u32 grc_mode
= tr32(GRC_MODE
);
7725 /* Access the lower 1K of PL PCIE block registers. */
7726 val
= grc_mode
& ~GRC_MODE_PCIE_PORT_MASK
;
7727 tw32(GRC_MODE
, val
| GRC_MODE_PCIE_PL_SEL
);
7729 val
= tr32(TG3_PCIE_TLDLPL_PORT
+ TG3_PCIE_PL_LO_PHYCTL5
);
7730 tw32(TG3_PCIE_TLDLPL_PORT
+ TG3_PCIE_PL_LO_PHYCTL5
,
7731 val
| TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ
);
7733 tw32(GRC_MODE
, grc_mode
);
7735 val
= tr32(TG3_CPMU_LSPD_10MB_CLK
);
7736 val
&= ~CPMU_LSPD_10MB_MACCLK_MASK
;
7737 val
|= CPMU_LSPD_10MB_MACCLK_6_25
;
7738 tw32(TG3_CPMU_LSPD_10MB_CLK
, val
);
7741 /* This works around an issue with Athlon chipsets on
7742 * B3 tigon3 silicon. This bit has no effect on any
7743 * other revision. But do not set this on PCI Express
7744 * chips and don't even touch the clocks if the CPMU is present.
7746 if (!(tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
)) {
7747 if (!(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
))
7748 tp
->pci_clock_ctrl
|= CLOCK_CTRL_DELAY_PCI_GRANT
;
7749 tw32_f(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
);
7752 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
&&
7753 (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
)) {
7754 val
= tr32(TG3PCI_PCISTATE
);
7755 val
|= PCISTATE_RETRY_SAME_DMA
;
7756 tw32(TG3PCI_PCISTATE
, val
);
7759 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
7760 /* Allow reads and writes to the
7761 * APE register and memory space.
7763 val
= tr32(TG3PCI_PCISTATE
);
7764 val
|= PCISTATE_ALLOW_APE_CTLSPC_WR
|
7765 PCISTATE_ALLOW_APE_SHMEM_WR
|
7766 PCISTATE_ALLOW_APE_PSPACE_WR
;
7767 tw32(TG3PCI_PCISTATE
, val
);
7770 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5704_BX
) {
7771 /* Enable some hw fixes. */
7772 val
= tr32(TG3PCI_MSI_DATA
);
7773 val
|= (1 << 26) | (1 << 28) | (1 << 29);
7774 tw32(TG3PCI_MSI_DATA
, val
);
7777 /* Descriptor ring init may make accesses to the
7778 * NIC SRAM area to setup the TX descriptors, so we
7779 * can only do this after the hardware has been
7780 * successfully reset.
7782 err
= tg3_init_rings(tp
);
7786 if (tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
) {
7787 val
= tr32(TG3PCI_DMA_RW_CTRL
) &
7788 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT
;
7789 if (tp
->pci_chip_rev_id
== CHIPREV_ID_57765_A0
)
7790 val
&= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK
;
7791 tw32(TG3PCI_DMA_RW_CTRL
, val
| tp
->dma_rwctrl
);
7792 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5784
&&
7793 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5761
) {
7794 /* This value is determined during the probe time DMA
7795 * engine test, tg3_test_dma.
7797 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
7800 tp
->grc_mode
&= ~(GRC_MODE_HOST_SENDBDS
|
7801 GRC_MODE_4X_NIC_SEND_RINGS
|
7802 GRC_MODE_NO_TX_PHDR_CSUM
|
7803 GRC_MODE_NO_RX_PHDR_CSUM
);
7804 tp
->grc_mode
|= GRC_MODE_HOST_SENDBDS
;
7806 /* Pseudo-header checksum is done by hardware logic and not
7807 * the offload processers, so make the chip do the pseudo-
7808 * header checksums on receive. For transmit it is more
7809 * convenient to do the pseudo-header checksum in software
7810 * as Linux does that on transmit for us in all cases.
7812 tp
->grc_mode
|= GRC_MODE_NO_TX_PHDR_CSUM
;
7816 (GRC_MODE_IRQ_ON_MAC_ATTN
| GRC_MODE_HOST_STACKUP
));
7818 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7819 val
= tr32(GRC_MISC_CFG
);
7821 val
|= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT
);
7822 tw32(GRC_MISC_CFG
, val
);
7824 /* Initialize MBUF/DESC pool. */
7825 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) {
7827 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5705
) {
7828 tw32(BUFMGR_MB_POOL_ADDR
, NIC_SRAM_MBUF_POOL_BASE
);
7829 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
)
7830 tw32(BUFMGR_MB_POOL_SIZE
, NIC_SRAM_MBUF_POOL_SIZE64
);
7832 tw32(BUFMGR_MB_POOL_SIZE
, NIC_SRAM_MBUF_POOL_SIZE96
);
7833 tw32(BUFMGR_DMA_DESC_POOL_ADDR
, NIC_SRAM_DMA_DESC_POOL_BASE
);
7834 tw32(BUFMGR_DMA_DESC_POOL_SIZE
, NIC_SRAM_DMA_DESC_POOL_SIZE
);
7835 } else if (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) {
7838 fw_len
= tp
->fw_len
;
7839 fw_len
= (fw_len
+ (0x80 - 1)) & ~(0x80 - 1);
7840 tw32(BUFMGR_MB_POOL_ADDR
,
7841 NIC_SRAM_MBUF_POOL_BASE5705
+ fw_len
);
7842 tw32(BUFMGR_MB_POOL_SIZE
,
7843 NIC_SRAM_MBUF_POOL_SIZE5705
- fw_len
- 0xa00);
7846 if (tp
->dev
->mtu
<= ETH_DATA_LEN
) {
7847 tw32(BUFMGR_MB_RDMA_LOW_WATER
,
7848 tp
->bufmgr_config
.mbuf_read_dma_low_water
);
7849 tw32(BUFMGR_MB_MACRX_LOW_WATER
,
7850 tp
->bufmgr_config
.mbuf_mac_rx_low_water
);
7851 tw32(BUFMGR_MB_HIGH_WATER
,
7852 tp
->bufmgr_config
.mbuf_high_water
);
7854 tw32(BUFMGR_MB_RDMA_LOW_WATER
,
7855 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
);
7856 tw32(BUFMGR_MB_MACRX_LOW_WATER
,
7857 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
);
7858 tw32(BUFMGR_MB_HIGH_WATER
,
7859 tp
->bufmgr_config
.mbuf_high_water_jumbo
);
7861 tw32(BUFMGR_DMA_LOW_WATER
,
7862 tp
->bufmgr_config
.dma_low_water
);
7863 tw32(BUFMGR_DMA_HIGH_WATER
,
7864 tp
->bufmgr_config
.dma_high_water
);
7866 val
= BUFMGR_MODE_ENABLE
| BUFMGR_MODE_ATTN_ENABLE
;
7867 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
)
7868 val
|= BUFMGR_MODE_NO_TX_UNDERRUN
;
7869 tw32(BUFMGR_MODE
, val
);
7870 for (i
= 0; i
< 2000; i
++) {
7871 if (tr32(BUFMGR_MODE
) & BUFMGR_MODE_ENABLE
)
7876 netdev_err(tp
->dev
, "%s cannot enable BUFMGR\n", __func__
);
7880 /* Setup replenish threshold. */
7881 val
= tp
->rx_pending
/ 8;
7884 else if (val
> tp
->rx_std_max_post
)
7885 val
= tp
->rx_std_max_post
;
7886 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
7887 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5906_A1
)
7888 tw32(ISO_PKT_TX
, (tr32(ISO_PKT_TX
) & ~0x3) | 0x2);
7890 if (val
> (TG3_RX_INTERNAL_RING_SZ_5906
/ 2))
7891 val
= TG3_RX_INTERNAL_RING_SZ_5906
/ 2;
7894 tw32(RCVBDI_STD_THRESH
, val
);
7896 /* Initialize TG3_BDINFO's at:
7897 * RCVDBDI_STD_BD: standard eth size rx ring
7898 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7899 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7902 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7903 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7904 * ring attribute flags
7905 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7907 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7908 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7910 * The size of each ring is fixed in the firmware, but the location is
7913 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
7914 ((u64
) tpr
->rx_std_mapping
>> 32));
7915 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
7916 ((u64
) tpr
->rx_std_mapping
& 0xffffffff));
7917 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5717
&&
7918 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5719
)
7919 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_NIC_ADDR
,
7920 NIC_SRAM_RX_BUFFER_DESC
);
7922 /* Disable the mini ring */
7923 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
7924 tw32(RCVDBDI_MINI_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
7925 BDINFO_FLAGS_DISABLED
);
7927 /* Program the jumbo buffer descriptor ring control
7928 * blocks on those devices that have them.
7930 if ((tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) &&
7931 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
7932 /* Setup replenish threshold. */
7933 tw32(RCVBDI_JUMBO_THRESH
, tp
->rx_jumbo_pending
/ 8);
7935 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
) {
7936 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
7937 ((u64
) tpr
->rx_jmb_mapping
>> 32));
7938 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
7939 ((u64
) tpr
->rx_jmb_mapping
& 0xffffffff));
7940 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
7941 (RX_JUMBO_MAX_SIZE
<< BDINFO_FLAGS_MAXLEN_SHIFT
) |
7942 BDINFO_FLAGS_USE_EXT_RECV
);
7943 if (!(tp
->tg3_flags3
& TG3_FLG3_USE_JUMBO_BDFLAG
) ||
7944 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
7945 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_NIC_ADDR
,
7946 NIC_SRAM_RX_JUMBO_BUFFER_DESC
);
7948 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
7949 BDINFO_FLAGS_DISABLED
);
7952 if (tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
)
7953 val
= (RX_STD_MAX_SIZE_5705
<< BDINFO_FLAGS_MAXLEN_SHIFT
) |
7954 (TG3_RX_STD_DMA_SZ
<< 2);
7956 val
= TG3_RX_STD_DMA_SZ
<< BDINFO_FLAGS_MAXLEN_SHIFT
;
7958 val
= RX_STD_MAX_SIZE_5705
<< BDINFO_FLAGS_MAXLEN_SHIFT
;
7960 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_MAXLEN_FLAGS
, val
);
7962 tpr
->rx_std_prod_idx
= tp
->rx_pending
;
7963 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG
, tpr
->rx_std_prod_idx
);
7965 tpr
->rx_jmb_prod_idx
= (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
) ?
7966 tp
->rx_jumbo_pending
: 0;
7967 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG
, tpr
->rx_jmb_prod_idx
);
7969 if (tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
) {
7970 tw32(STD_REPLENISH_LWM
, 32);
7971 tw32(JMB_REPLENISH_LWM
, 16);
7974 tg3_rings_reset(tp
);
7976 /* Initialize MAC address and backoff seed. */
7977 __tg3_set_mac_addr(tp
, 0);
7979 /* MTU + ethernet header + FCS + optional VLAN tag */
7980 tw32(MAC_RX_MTU_SIZE
,
7981 tp
->dev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
+ VLAN_HLEN
);
7983 /* The slot time is changed by tg3_setup_phy if we
7984 * run at gigabit with half duplex.
7986 tw32(MAC_TX_LENGTHS
,
7987 (2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
7988 (6 << TX_LENGTHS_IPG_SHIFT
) |
7989 (32 << TX_LENGTHS_SLOT_TIME_SHIFT
));
7991 /* Receive rules. */
7992 tw32(MAC_RCV_RULE_CFG
, RCV_RULE_CFG_DEFAULT_CLASS
);
7993 tw32(RCVLPC_CONFIG
, 0x0181);
7995 /* Calculate RDMAC_MODE setting early, we need it to determine
7996 * the RCVLPC_STATE_ENABLE mask.
7998 rdmac_mode
= (RDMAC_MODE_ENABLE
| RDMAC_MODE_TGTABORT_ENAB
|
7999 RDMAC_MODE_MSTABORT_ENAB
| RDMAC_MODE_PARITYERR_ENAB
|
8000 RDMAC_MODE_ADDROFLOW_ENAB
| RDMAC_MODE_FIFOOFLOW_ENAB
|
8001 RDMAC_MODE_FIFOURUN_ENAB
| RDMAC_MODE_FIFOOREAD_ENAB
|
8002 RDMAC_MODE_LNGREAD_ENAB
);
8004 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
8005 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
)
8006 rdmac_mode
|= RDMAC_MODE_MULT_DMA_RD_DIS
;
8008 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
8009 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
8010 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
8011 rdmac_mode
|= RDMAC_MODE_BD_SBD_CRPT_ENAB
|
8012 RDMAC_MODE_MBUF_RBD_CRPT_ENAB
|
8013 RDMAC_MODE_MBUF_SBD_CRPT_ENAB
;
8015 /* If statement applies to 5705 and 5750 PCI devices only */
8016 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
8017 tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A0
) ||
8018 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
)) {
8019 if (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
&&
8020 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
8021 rdmac_mode
|= RDMAC_MODE_FIFO_SIZE_128
;
8022 } else if (!(tr32(TG3PCI_PCISTATE
) & PCISTATE_BUS_SPEED_HIGH
) &&
8023 !(tp
->tg3_flags2
& TG3_FLG2_IS_5788
)) {
8024 rdmac_mode
|= RDMAC_MODE_FIFO_LONG_BURST
;
8028 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)
8029 rdmac_mode
|= RDMAC_MODE_FIFO_LONG_BURST
;
8031 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
8032 rdmac_mode
|= RDMAC_MODE_IPV4_LSO_EN
;
8034 if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO_3
) ||
8035 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
8036 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
8037 rdmac_mode
|= RDMAC_MODE_IPV6_LSO_EN
;
8039 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
8040 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
8041 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
8042 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
||
8043 (tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
)) {
8044 val
= tr32(TG3_RDMA_RSRVCTRL_REG
);
8045 tw32(TG3_RDMA_RSRVCTRL_REG
,
8046 val
| TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX
);
8049 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
) {
8050 val
= tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL
);
8051 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL
, val
|
8052 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K
|
8053 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K
);
8056 /* Receive/send statistics. */
8057 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) {
8058 val
= tr32(RCVLPC_STATS_ENABLE
);
8059 val
&= ~RCVLPC_STATSENAB_DACK_FIX
;
8060 tw32(RCVLPC_STATS_ENABLE
, val
);
8061 } else if ((rdmac_mode
& RDMAC_MODE_FIFO_SIZE_128
) &&
8062 (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
)) {
8063 val
= tr32(RCVLPC_STATS_ENABLE
);
8064 val
&= ~RCVLPC_STATSENAB_LNGBRST_RFIX
;
8065 tw32(RCVLPC_STATS_ENABLE
, val
);
8067 tw32(RCVLPC_STATS_ENABLE
, 0xffffff);
8069 tw32(RCVLPC_STATSCTRL
, RCVLPC_STATSCTRL_ENABLE
);
8070 tw32(SNDDATAI_STATSENAB
, 0xffffff);
8071 tw32(SNDDATAI_STATSCTRL
,
8072 (SNDDATAI_SCTRL_ENABLE
|
8073 SNDDATAI_SCTRL_FASTUPD
));
8075 /* Setup host coalescing engine. */
8076 tw32(HOSTCC_MODE
, 0);
8077 for (i
= 0; i
< 2000; i
++) {
8078 if (!(tr32(HOSTCC_MODE
) & HOSTCC_MODE_ENABLE
))
8083 __tg3_set_coalesce(tp
, &tp
->coal
);
8085 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
8086 /* Status/statistics block address. See tg3_timer,
8087 * the tg3_periodic_fetch_stats call there, and
8088 * tg3_get_stats to see how this works for 5705/5750 chips.
8090 tw32(HOSTCC_STATS_BLK_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
8091 ((u64
) tp
->stats_mapping
>> 32));
8092 tw32(HOSTCC_STATS_BLK_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
8093 ((u64
) tp
->stats_mapping
& 0xffffffff));
8094 tw32(HOSTCC_STATS_BLK_NIC_ADDR
, NIC_SRAM_STATS_BLK
);
8096 tw32(HOSTCC_STATUS_BLK_NIC_ADDR
, NIC_SRAM_STATUS_BLK
);
8098 /* Clear statistics and status block memory areas */
8099 for (i
= NIC_SRAM_STATS_BLK
;
8100 i
< NIC_SRAM_STATUS_BLK
+ TG3_HW_STATUS_SIZE
;
8102 tg3_write_mem(tp
, i
, 0);
8107 tw32(HOSTCC_MODE
, HOSTCC_MODE_ENABLE
| tp
->coalesce_mode
);
8109 tw32(RCVCC_MODE
, RCVCC_MODE_ENABLE
| RCVCC_MODE_ATTN_ENABLE
);
8110 tw32(RCVLPC_MODE
, RCVLPC_MODE_ENABLE
);
8111 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
8112 tw32(RCVLSC_MODE
, RCVLSC_MODE_ENABLE
| RCVLSC_MODE_ATTN_ENABLE
);
8114 if (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
) {
8115 tp
->phy_flags
&= ~TG3_PHYFLG_PARALLEL_DETECT
;
8116 /* reset to prevent losing 1st rx packet intermittently */
8117 tw32_f(MAC_RX_MODE
, RX_MODE_RESET
);
8121 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
8122 tp
->mac_mode
&= MAC_MODE_APE_TX_EN
| MAC_MODE_APE_RX_EN
;
8125 tp
->mac_mode
|= MAC_MODE_TXSTAT_ENABLE
| MAC_MODE_RXSTAT_ENABLE
|
8126 MAC_MODE_TDE_ENABLE
| MAC_MODE_RDE_ENABLE
| MAC_MODE_FHDE_ENABLE
;
8127 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
8128 !(tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) &&
8129 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
)
8130 tp
->mac_mode
|= MAC_MODE_LINK_POLARITY
;
8131 tw32_f(MAC_MODE
, tp
->mac_mode
| MAC_MODE_RXSTAT_CLEAR
| MAC_MODE_TXSTAT_CLEAR
);
8134 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8135 * If TG3_FLG2_IS_NIC is zero, we should read the
8136 * register to preserve the GPIO settings for LOMs. The GPIOs,
8137 * whether used as inputs or outputs, are set by boot code after
8140 if (!(tp
->tg3_flags2
& TG3_FLG2_IS_NIC
)) {
8143 gpio_mask
= GRC_LCLCTRL_GPIO_OE0
| GRC_LCLCTRL_GPIO_OE1
|
8144 GRC_LCLCTRL_GPIO_OE2
| GRC_LCLCTRL_GPIO_OUTPUT0
|
8145 GRC_LCLCTRL_GPIO_OUTPUT1
| GRC_LCLCTRL_GPIO_OUTPUT2
;
8147 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
)
8148 gpio_mask
|= GRC_LCLCTRL_GPIO_OE3
|
8149 GRC_LCLCTRL_GPIO_OUTPUT3
;
8151 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
)
8152 gpio_mask
|= GRC_LCLCTRL_GPIO_UART_SEL
;
8154 tp
->grc_local_ctrl
&= ~gpio_mask
;
8155 tp
->grc_local_ctrl
|= tr32(GRC_LOCAL_CTRL
) & gpio_mask
;
8157 /* GPIO1 must be driven high for eeprom write protect */
8158 if (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
)
8159 tp
->grc_local_ctrl
|= (GRC_LCLCTRL_GPIO_OE1
|
8160 GRC_LCLCTRL_GPIO_OUTPUT1
);
8162 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
);
8165 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSIX
) {
8166 val
= tr32(MSGINT_MODE
);
8167 val
|= MSGINT_MODE_MULTIVEC_EN
| MSGINT_MODE_ENABLE
;
8168 tw32(MSGINT_MODE
, val
);
8171 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
8172 tw32_f(DMAC_MODE
, DMAC_MODE_ENABLE
);
8176 val
= (WDMAC_MODE_ENABLE
| WDMAC_MODE_TGTABORT_ENAB
|
8177 WDMAC_MODE_MSTABORT_ENAB
| WDMAC_MODE_PARITYERR_ENAB
|
8178 WDMAC_MODE_ADDROFLOW_ENAB
| WDMAC_MODE_FIFOOFLOW_ENAB
|
8179 WDMAC_MODE_FIFOURUN_ENAB
| WDMAC_MODE_FIFOOREAD_ENAB
|
8180 WDMAC_MODE_LNGREAD_ENAB
);
8182 /* If statement applies to 5705 and 5750 PCI devices only */
8183 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
8184 tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A0
) ||
8185 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
) {
8186 if ((tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) &&
8187 (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A1
||
8188 tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A2
)) {
8190 } else if (!(tr32(TG3PCI_PCISTATE
) & PCISTATE_BUS_SPEED_HIGH
) &&
8191 !(tp
->tg3_flags2
& TG3_FLG2_IS_5788
) &&
8192 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)) {
8193 val
|= WDMAC_MODE_RX_ACCEL
;
8197 /* Enable host coalescing bug fix */
8198 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
8199 val
|= WDMAC_MODE_STATUS_TAG_FIX
;
8201 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
8202 val
|= WDMAC_MODE_BURST_ALL_DATA
;
8204 tw32_f(WDMAC_MODE
, val
);
8207 if (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) {
8210 pci_read_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
8212 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
) {
8213 pcix_cmd
&= ~PCI_X_CMD_MAX_READ
;
8214 pcix_cmd
|= PCI_X_CMD_READ_2K
;
8215 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
8216 pcix_cmd
&= ~(PCI_X_CMD_MAX_SPLIT
| PCI_X_CMD_MAX_READ
);
8217 pcix_cmd
|= PCI_X_CMD_READ_2K
;
8219 pci_write_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
8223 tw32_f(RDMAC_MODE
, rdmac_mode
);
8226 tw32(RCVDCC_MODE
, RCVDCC_MODE_ENABLE
| RCVDCC_MODE_ATTN_ENABLE
);
8227 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
8228 tw32(MBFREE_MODE
, MBFREE_MODE_ENABLE
);
8230 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
)
8232 SNDDATAC_MODE_ENABLE
| SNDDATAC_MODE_CDELAY
);
8234 tw32(SNDDATAC_MODE
, SNDDATAC_MODE_ENABLE
);
8236 tw32(SNDBDC_MODE
, SNDBDC_MODE_ENABLE
| SNDBDC_MODE_ATTN_ENABLE
);
8237 tw32(RCVBDI_MODE
, RCVBDI_MODE_ENABLE
| RCVBDI_MODE_RCB_ATTN_ENAB
);
8238 tw32(RCVDBDI_MODE
, RCVDBDI_MODE_ENABLE
| RCVDBDI_MODE_INV_RING_SZ
);
8239 tw32(SNDDATAI_MODE
, SNDDATAI_MODE_ENABLE
);
8240 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
8241 tw32(SNDDATAI_MODE
, SNDDATAI_MODE_ENABLE
| 0x8);
8242 val
= SNDBDI_MODE_ENABLE
| SNDBDI_MODE_ATTN_ENABLE
;
8243 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)
8244 val
|= SNDBDI_MODE_MULTI_TXQ_EN
;
8245 tw32(SNDBDI_MODE
, val
);
8246 tw32(SNDBDS_MODE
, SNDBDS_MODE_ENABLE
| SNDBDS_MODE_ATTN_ENABLE
);
8248 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
) {
8249 err
= tg3_load_5701_a0_firmware_fix(tp
);
8254 if (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) {
8255 err
= tg3_load_tso_firmware(tp
);
8260 tp
->tx_mode
= TX_MODE_ENABLE
;
8261 if ((tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) ||
8262 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
8263 tp
->tx_mode
|= TX_MODE_MBUF_LOCKUP_FIX
;
8264 tw32_f(MAC_TX_MODE
, tp
->tx_mode
);
8267 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_RSS
) {
8268 u32 reg
= MAC_RSS_INDIR_TBL_0
;
8269 u8
*ent
= (u8
*)&val
;
8271 /* Setup the indirection table */
8272 for (i
= 0; i
< TG3_RSS_INDIR_TBL_SIZE
; i
++) {
8273 int idx
= i
% sizeof(val
);
8275 ent
[idx
] = i
% (tp
->irq_cnt
- 1);
8276 if (idx
== sizeof(val
) - 1) {
8282 /* Setup the "secret" hash key. */
8283 tw32(MAC_RSS_HASH_KEY_0
, 0x5f865437);
8284 tw32(MAC_RSS_HASH_KEY_1
, 0xe4ac62cc);
8285 tw32(MAC_RSS_HASH_KEY_2
, 0x50103a45);
8286 tw32(MAC_RSS_HASH_KEY_3
, 0x36621985);
8287 tw32(MAC_RSS_HASH_KEY_4
, 0xbf14c0e8);
8288 tw32(MAC_RSS_HASH_KEY_5
, 0x1bc27a1e);
8289 tw32(MAC_RSS_HASH_KEY_6
, 0x84f4b556);
8290 tw32(MAC_RSS_HASH_KEY_7
, 0x094ea6fe);
8291 tw32(MAC_RSS_HASH_KEY_8
, 0x7dda01e7);
8292 tw32(MAC_RSS_HASH_KEY_9
, 0xc04d7481);
8295 tp
->rx_mode
= RX_MODE_ENABLE
;
8296 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
8297 tp
->rx_mode
|= RX_MODE_IPV6_CSUM_ENABLE
;
8299 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_RSS
)
8300 tp
->rx_mode
|= RX_MODE_RSS_ENABLE
|
8301 RX_MODE_RSS_ITBL_HASH_BITS_7
|
8302 RX_MODE_RSS_IPV6_HASH_EN
|
8303 RX_MODE_RSS_TCP_IPV6_HASH_EN
|
8304 RX_MODE_RSS_IPV4_HASH_EN
|
8305 RX_MODE_RSS_TCP_IPV4_HASH_EN
;
8307 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
8310 tw32(MAC_LED_CTRL
, tp
->led_ctrl
);
8312 tw32(MAC_MI_STAT
, MAC_MI_STAT_LNKSTAT_ATTN_ENAB
);
8313 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) {
8314 tw32_f(MAC_RX_MODE
, RX_MODE_RESET
);
8317 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
8320 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) {
8321 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) &&
8322 !(tp
->phy_flags
& TG3_PHYFLG_SERDES_PREEMPHASIS
)) {
8323 /* Set drive transmission level to 1.2V */
8324 /* only if the signal pre-emphasis bit is not set */
8325 val
= tr32(MAC_SERDES_CFG
);
8328 tw32(MAC_SERDES_CFG
, val
);
8330 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5703_A1
)
8331 tw32(MAC_SERDES_CFG
, 0x616000);
8334 /* Prevent chip from dropping frames when flow control
8337 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
8341 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME
, val
);
8343 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
&&
8344 (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
)) {
8345 /* Use hardware link auto-negotiation */
8346 tp
->tg3_flags2
|= TG3_FLG2_HW_AUTONEG
;
8349 if ((tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
) &&
8350 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
)) {
8353 tmp
= tr32(SERDES_RX_CTRL
);
8354 tw32(SERDES_RX_CTRL
, tmp
| SERDES_RX_SIG_DETECT
);
8355 tp
->grc_local_ctrl
&= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT
;
8356 tp
->grc_local_ctrl
|= GRC_LCLCTRL_USE_SIG_DETECT
;
8357 tw32(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
);
8360 if (!(tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
)) {
8361 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
) {
8362 tp
->phy_flags
&= ~TG3_PHYFLG_IS_LOW_POWER
;
8363 tp
->link_config
.speed
= tp
->link_config
.orig_speed
;
8364 tp
->link_config
.duplex
= tp
->link_config
.orig_duplex
;
8365 tp
->link_config
.autoneg
= tp
->link_config
.orig_autoneg
;
8368 err
= tg3_setup_phy(tp
, 0);
8372 if (!(tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) &&
8373 !(tp
->phy_flags
& TG3_PHYFLG_IS_FET
)) {
8376 /* Clear CRC stats. */
8377 if (!tg3_readphy(tp
, MII_TG3_TEST1
, &tmp
)) {
8378 tg3_writephy(tp
, MII_TG3_TEST1
,
8379 tmp
| MII_TG3_TEST1_CRC_EN
);
8380 tg3_readphy(tp
, MII_TG3_RXR_COUNTERS
, &tmp
);
8385 __tg3_set_rx_mode(tp
->dev
);
8387 /* Initialize receive rules. */
8388 tw32(MAC_RCV_RULE_0
, 0xc2000000 & RCV_RULE_DISABLE_MASK
);
8389 tw32(MAC_RCV_VALUE_0
, 0xffffffff & RCV_RULE_DISABLE_MASK
);
8390 tw32(MAC_RCV_RULE_1
, 0x86000004 & RCV_RULE_DISABLE_MASK
);
8391 tw32(MAC_RCV_VALUE_1
, 0xffffffff & RCV_RULE_DISABLE_MASK
);
8393 if ((tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
8394 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
8398 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)
8402 tw32(MAC_RCV_RULE_15
, 0); tw32(MAC_RCV_VALUE_15
, 0);
8404 tw32(MAC_RCV_RULE_14
, 0); tw32(MAC_RCV_VALUE_14
, 0);
8406 tw32(MAC_RCV_RULE_13
, 0); tw32(MAC_RCV_VALUE_13
, 0);
8408 tw32(MAC_RCV_RULE_12
, 0); tw32(MAC_RCV_VALUE_12
, 0);
8410 tw32(MAC_RCV_RULE_11
, 0); tw32(MAC_RCV_VALUE_11
, 0);
8412 tw32(MAC_RCV_RULE_10
, 0); tw32(MAC_RCV_VALUE_10
, 0);
8414 tw32(MAC_RCV_RULE_9
, 0); tw32(MAC_RCV_VALUE_9
, 0);
8416 tw32(MAC_RCV_RULE_8
, 0); tw32(MAC_RCV_VALUE_8
, 0);
8418 tw32(MAC_RCV_RULE_7
, 0); tw32(MAC_RCV_VALUE_7
, 0);
8420 tw32(MAC_RCV_RULE_6
, 0); tw32(MAC_RCV_VALUE_6
, 0);
8422 tw32(MAC_RCV_RULE_5
, 0); tw32(MAC_RCV_VALUE_5
, 0);
8424 tw32(MAC_RCV_RULE_4
, 0); tw32(MAC_RCV_VALUE_4
, 0);
8426 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
8428 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
8436 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
8437 /* Write our heartbeat update interval to APE. */
8438 tg3_ape_write32(tp
, TG3_APE_HOST_HEARTBEAT_INT_MS
,
8439 APE_HOST_HEARTBEAT_INT_DISABLE
);
8441 tg3_write_sig_post_reset(tp
, RESET_KIND_INIT
);
8446 /* Called at device open time to get the chip ready for
8447 * packet processing. Invoked with tp->lock held.
8449 static int tg3_init_hw(struct tg3
*tp
, int reset_phy
)
8451 tg3_switch_clocks(tp
);
8453 tw32(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
8455 return tg3_reset_hw(tp
, reset_phy
);
8458 #define TG3_STAT_ADD32(PSTAT, REG) \
8459 do { u32 __val = tr32(REG); \
8460 (PSTAT)->low += __val; \
8461 if ((PSTAT)->low < __val) \
8462 (PSTAT)->high += 1; \
8465 static void tg3_periodic_fetch_stats(struct tg3
*tp
)
8467 struct tg3_hw_stats
*sp
= tp
->hw_stats
;
8469 if (!netif_carrier_ok(tp
->dev
))
8472 TG3_STAT_ADD32(&sp
->tx_octets
, MAC_TX_STATS_OCTETS
);
8473 TG3_STAT_ADD32(&sp
->tx_collisions
, MAC_TX_STATS_COLLISIONS
);
8474 TG3_STAT_ADD32(&sp
->tx_xon_sent
, MAC_TX_STATS_XON_SENT
);
8475 TG3_STAT_ADD32(&sp
->tx_xoff_sent
, MAC_TX_STATS_XOFF_SENT
);
8476 TG3_STAT_ADD32(&sp
->tx_mac_errors
, MAC_TX_STATS_MAC_ERRORS
);
8477 TG3_STAT_ADD32(&sp
->tx_single_collisions
, MAC_TX_STATS_SINGLE_COLLISIONS
);
8478 TG3_STAT_ADD32(&sp
->tx_mult_collisions
, MAC_TX_STATS_MULT_COLLISIONS
);
8479 TG3_STAT_ADD32(&sp
->tx_deferred
, MAC_TX_STATS_DEFERRED
);
8480 TG3_STAT_ADD32(&sp
->tx_excessive_collisions
, MAC_TX_STATS_EXCESSIVE_COL
);
8481 TG3_STAT_ADD32(&sp
->tx_late_collisions
, MAC_TX_STATS_LATE_COL
);
8482 TG3_STAT_ADD32(&sp
->tx_ucast_packets
, MAC_TX_STATS_UCAST
);
8483 TG3_STAT_ADD32(&sp
->tx_mcast_packets
, MAC_TX_STATS_MCAST
);
8484 TG3_STAT_ADD32(&sp
->tx_bcast_packets
, MAC_TX_STATS_BCAST
);
8486 TG3_STAT_ADD32(&sp
->rx_octets
, MAC_RX_STATS_OCTETS
);
8487 TG3_STAT_ADD32(&sp
->rx_fragments
, MAC_RX_STATS_FRAGMENTS
);
8488 TG3_STAT_ADD32(&sp
->rx_ucast_packets
, MAC_RX_STATS_UCAST
);
8489 TG3_STAT_ADD32(&sp
->rx_mcast_packets
, MAC_RX_STATS_MCAST
);
8490 TG3_STAT_ADD32(&sp
->rx_bcast_packets
, MAC_RX_STATS_BCAST
);
8491 TG3_STAT_ADD32(&sp
->rx_fcs_errors
, MAC_RX_STATS_FCS_ERRORS
);
8492 TG3_STAT_ADD32(&sp
->rx_align_errors
, MAC_RX_STATS_ALIGN_ERRORS
);
8493 TG3_STAT_ADD32(&sp
->rx_xon_pause_rcvd
, MAC_RX_STATS_XON_PAUSE_RECVD
);
8494 TG3_STAT_ADD32(&sp
->rx_xoff_pause_rcvd
, MAC_RX_STATS_XOFF_PAUSE_RECVD
);
8495 TG3_STAT_ADD32(&sp
->rx_mac_ctrl_rcvd
, MAC_RX_STATS_MAC_CTRL_RECVD
);
8496 TG3_STAT_ADD32(&sp
->rx_xoff_entered
, MAC_RX_STATS_XOFF_ENTERED
);
8497 TG3_STAT_ADD32(&sp
->rx_frame_too_long_errors
, MAC_RX_STATS_FRAME_TOO_LONG
);
8498 TG3_STAT_ADD32(&sp
->rx_jabbers
, MAC_RX_STATS_JABBERS
);
8499 TG3_STAT_ADD32(&sp
->rx_undersize_packets
, MAC_RX_STATS_UNDERSIZE
);
8501 TG3_STAT_ADD32(&sp
->rxbds_empty
, RCVLPC_NO_RCV_BD_CNT
);
8502 TG3_STAT_ADD32(&sp
->rx_discards
, RCVLPC_IN_DISCARDS_CNT
);
8503 TG3_STAT_ADD32(&sp
->rx_errors
, RCVLPC_IN_ERRORS_CNT
);
8506 static void tg3_timer(unsigned long __opaque
)
8508 struct tg3
*tp
= (struct tg3
*) __opaque
;
8513 spin_lock(&tp
->lock
);
8515 if (!(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)) {
8516 /* All of this garbage is because when using non-tagged
8517 * IRQ status the mailbox/status_block protocol the chip
8518 * uses with the cpu is race prone.
8520 if (tp
->napi
[0].hw_status
->status
& SD_STATUS_UPDATED
) {
8521 tw32(GRC_LOCAL_CTRL
,
8522 tp
->grc_local_ctrl
| GRC_LCLCTRL_SETINT
);
8524 tw32(HOSTCC_MODE
, tp
->coalesce_mode
|
8525 HOSTCC_MODE_ENABLE
| HOSTCC_MODE_NOW
);
8528 if (!(tr32(WDMAC_MODE
) & WDMAC_MODE_ENABLE
)) {
8529 tp
->tg3_flags2
|= TG3_FLG2_RESTART_TIMER
;
8530 spin_unlock(&tp
->lock
);
8531 schedule_work(&tp
->reset_task
);
8536 /* This part only runs once per second. */
8537 if (!--tp
->timer_counter
) {
8538 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
8539 tg3_periodic_fetch_stats(tp
);
8541 if (tp
->tg3_flags
& TG3_FLAG_USE_LINKCHG_REG
) {
8545 mac_stat
= tr32(MAC_STATUS
);
8548 if (tp
->phy_flags
& TG3_PHYFLG_USE_MI_INTERRUPT
) {
8549 if (mac_stat
& MAC_STATUS_MI_INTERRUPT
)
8551 } else if (mac_stat
& MAC_STATUS_LNKSTATE_CHANGED
)
8555 tg3_setup_phy(tp
, 0);
8556 } else if (tp
->tg3_flags
& TG3_FLAG_POLL_SERDES
) {
8557 u32 mac_stat
= tr32(MAC_STATUS
);
8560 if (netif_carrier_ok(tp
->dev
) &&
8561 (mac_stat
& MAC_STATUS_LNKSTATE_CHANGED
)) {
8564 if (!netif_carrier_ok(tp
->dev
) &&
8565 (mac_stat
& (MAC_STATUS_PCS_SYNCED
|
8566 MAC_STATUS_SIGNAL_DET
))) {
8570 if (!tp
->serdes_counter
) {
8573 ~MAC_MODE_PORT_MODE_MASK
));
8575 tw32_f(MAC_MODE
, tp
->mac_mode
);
8578 tg3_setup_phy(tp
, 0);
8580 } else if ((tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
) &&
8581 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
8582 tg3_serdes_parallel_detect(tp
);
8585 tp
->timer_counter
= tp
->timer_multiplier
;
8588 /* Heartbeat is only sent once every 2 seconds.
8590 * The heartbeat is to tell the ASF firmware that the host
8591 * driver is still alive. In the event that the OS crashes,
8592 * ASF needs to reset the hardware to free up the FIFO space
8593 * that may be filled with rx packets destined for the host.
8594 * If the FIFO is full, ASF will no longer function properly.
8596 * Unintended resets have been reported on real time kernels
8597 * where the timer doesn't run on time. Netpoll will also have
8600 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8601 * to check the ring condition when the heartbeat is expiring
8602 * before doing the reset. This will prevent most unintended
8605 if (!--tp
->asf_counter
) {
8606 if ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) &&
8607 !(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)) {
8608 tg3_wait_for_event_ack(tp
);
8610 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_MBOX
,
8611 FWCMD_NICDRV_ALIVE3
);
8612 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_LEN_MBOX
, 4);
8613 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
,
8614 TG3_FW_UPDATE_TIMEOUT_SEC
);
8616 tg3_generate_fw_event(tp
);
8618 tp
->asf_counter
= tp
->asf_multiplier
;
8621 spin_unlock(&tp
->lock
);
8624 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
8625 add_timer(&tp
->timer
);
8628 static int tg3_request_irq(struct tg3
*tp
, int irq_num
)
8631 unsigned long flags
;
8633 struct tg3_napi
*tnapi
= &tp
->napi
[irq_num
];
8635 if (tp
->irq_cnt
== 1)
8636 name
= tp
->dev
->name
;
8638 name
= &tnapi
->irq_lbl
[0];
8639 snprintf(name
, IFNAMSIZ
, "%s-%d", tp
->dev
->name
, irq_num
);
8640 name
[IFNAMSIZ
-1] = 0;
8643 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI_OR_MSIX
) {
8645 if (tp
->tg3_flags2
& TG3_FLG2_1SHOT_MSI
)
8647 flags
= IRQF_SAMPLE_RANDOM
;
8650 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)
8651 fn
= tg3_interrupt_tagged
;
8652 flags
= IRQF_SHARED
| IRQF_SAMPLE_RANDOM
;
8655 return request_irq(tnapi
->irq_vec
, fn
, flags
, name
, tnapi
);
8658 static int tg3_test_interrupt(struct tg3
*tp
)
8660 struct tg3_napi
*tnapi
= &tp
->napi
[0];
8661 struct net_device
*dev
= tp
->dev
;
8662 int err
, i
, intr_ok
= 0;
8665 if (!netif_running(dev
))
8668 tg3_disable_ints(tp
);
8670 free_irq(tnapi
->irq_vec
, tnapi
);
8673 * Turn off MSI one shot mode. Otherwise this test has no
8674 * observable way to know whether the interrupt was delivered.
8676 if ((tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
) &&
8677 (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
)) {
8678 val
= tr32(MSGINT_MODE
) | MSGINT_MODE_ONE_SHOT_DISABLE
;
8679 tw32(MSGINT_MODE
, val
);
8682 err
= request_irq(tnapi
->irq_vec
, tg3_test_isr
,
8683 IRQF_SHARED
| IRQF_SAMPLE_RANDOM
, dev
->name
, tnapi
);
8687 tnapi
->hw_status
->status
&= ~SD_STATUS_UPDATED
;
8688 tg3_enable_ints(tp
);
8690 tw32_f(HOSTCC_MODE
, tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
|
8693 for (i
= 0; i
< 5; i
++) {
8694 u32 int_mbox
, misc_host_ctrl
;
8696 int_mbox
= tr32_mailbox(tnapi
->int_mbox
);
8697 misc_host_ctrl
= tr32(TG3PCI_MISC_HOST_CTRL
);
8699 if ((int_mbox
!= 0) ||
8700 (misc_host_ctrl
& MISC_HOST_CTRL_MASK_PCI_INT
)) {
8708 tg3_disable_ints(tp
);
8710 free_irq(tnapi
->irq_vec
, tnapi
);
8712 err
= tg3_request_irq(tp
, 0);
8718 /* Reenable MSI one shot mode. */
8719 if ((tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
) &&
8720 (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
)) {
8721 val
= tr32(MSGINT_MODE
) & ~MSGINT_MODE_ONE_SHOT_DISABLE
;
8722 tw32(MSGINT_MODE
, val
);
8730 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8731 * successfully restored
8733 static int tg3_test_msi(struct tg3
*tp
)
8738 if (!(tp
->tg3_flags2
& TG3_FLG2_USING_MSI
))
8741 /* Turn off SERR reporting in case MSI terminates with Master
8744 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
8745 pci_write_config_word(tp
->pdev
, PCI_COMMAND
,
8746 pci_cmd
& ~PCI_COMMAND_SERR
);
8748 err
= tg3_test_interrupt(tp
);
8750 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
8755 /* other failures */
8759 /* MSI test failed, go back to INTx mode */
8760 netdev_warn(tp
->dev
, "No interrupt was generated using MSI. Switching "
8761 "to INTx mode. Please report this failure to the PCI "
8762 "maintainer and include system chipset information\n");
8764 free_irq(tp
->napi
[0].irq_vec
, &tp
->napi
[0]);
8766 pci_disable_msi(tp
->pdev
);
8768 tp
->tg3_flags2
&= ~TG3_FLG2_USING_MSI
;
8769 tp
->napi
[0].irq_vec
= tp
->pdev
->irq
;
8771 err
= tg3_request_irq(tp
, 0);
8775 /* Need to reset the chip because the MSI cycle may have terminated
8776 * with Master Abort.
8778 tg3_full_lock(tp
, 1);
8780 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
8781 err
= tg3_init_hw(tp
, 1);
8783 tg3_full_unlock(tp
);
8786 free_irq(tp
->napi
[0].irq_vec
, &tp
->napi
[0]);
8791 static int tg3_request_firmware(struct tg3
*tp
)
8793 const __be32
*fw_data
;
8795 if (request_firmware(&tp
->fw
, tp
->fw_needed
, &tp
->pdev
->dev
)) {
8796 netdev_err(tp
->dev
, "Failed to load firmware \"%s\"\n",
8801 fw_data
= (void *)tp
->fw
->data
;
8803 /* Firmware blob starts with version numbers, followed by
8804 * start address and _full_ length including BSS sections
8805 * (which must be longer than the actual data, of course
8808 tp
->fw_len
= be32_to_cpu(fw_data
[2]); /* includes bss */
8809 if (tp
->fw_len
< (tp
->fw
->size
- 12)) {
8810 netdev_err(tp
->dev
, "bogus length %d in \"%s\"\n",
8811 tp
->fw_len
, tp
->fw_needed
);
8812 release_firmware(tp
->fw
);
8817 /* We no longer need firmware; we have it. */
8818 tp
->fw_needed
= NULL
;
8822 static bool tg3_enable_msix(struct tg3
*tp
)
8824 int i
, rc
, cpus
= num_online_cpus();
8825 struct msix_entry msix_ent
[tp
->irq_max
];
8828 /* Just fallback to the simpler MSI mode. */
8832 * We want as many rx rings enabled as there are cpus.
8833 * The first MSIX vector only deals with link interrupts, etc,
8834 * so we add one to the number of vectors we are requesting.
8836 tp
->irq_cnt
= min_t(unsigned, cpus
+ 1, tp
->irq_max
);
8838 for (i
= 0; i
< tp
->irq_max
; i
++) {
8839 msix_ent
[i
].entry
= i
;
8840 msix_ent
[i
].vector
= 0;
8843 rc
= pci_enable_msix(tp
->pdev
, msix_ent
, tp
->irq_cnt
);
8846 } else if (rc
!= 0) {
8847 if (pci_enable_msix(tp
->pdev
, msix_ent
, rc
))
8849 netdev_notice(tp
->dev
, "Requested %d MSI-X vectors, received %d\n",
8854 for (i
= 0; i
< tp
->irq_max
; i
++)
8855 tp
->napi
[i
].irq_vec
= msix_ent
[i
].vector
;
8857 netif_set_real_num_tx_queues(tp
->dev
, 1);
8858 rc
= tp
->irq_cnt
> 1 ? tp
->irq_cnt
- 1 : 1;
8859 if (netif_set_real_num_rx_queues(tp
->dev
, rc
)) {
8860 pci_disable_msix(tp
->pdev
);
8863 if (tp
->irq_cnt
> 1)
8864 tp
->tg3_flags3
|= TG3_FLG3_ENABLE_RSS
;
8869 static void tg3_ints_init(struct tg3
*tp
)
8871 if ((tp
->tg3_flags
& TG3_FLAG_SUPPORT_MSI_OR_MSIX
) &&
8872 !(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)) {
8873 /* All MSI supporting chips should support tagged
8874 * status. Assert that this is the case.
8876 netdev_warn(tp
->dev
,
8877 "MSI without TAGGED_STATUS? Not using MSI\n");
8881 if ((tp
->tg3_flags
& TG3_FLAG_SUPPORT_MSIX
) && tg3_enable_msix(tp
))
8882 tp
->tg3_flags2
|= TG3_FLG2_USING_MSIX
;
8883 else if ((tp
->tg3_flags
& TG3_FLAG_SUPPORT_MSI
) &&
8884 pci_enable_msi(tp
->pdev
) == 0)
8885 tp
->tg3_flags2
|= TG3_FLG2_USING_MSI
;
8887 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI_OR_MSIX
) {
8888 u32 msi_mode
= tr32(MSGINT_MODE
);
8889 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSIX
)
8890 msi_mode
|= MSGINT_MODE_MULTIVEC_EN
;
8891 tw32(MSGINT_MODE
, msi_mode
| MSGINT_MODE_ENABLE
);
8894 if (!(tp
->tg3_flags2
& TG3_FLG2_USING_MSIX
)) {
8896 tp
->napi
[0].irq_vec
= tp
->pdev
->irq
;
8897 netif_set_real_num_tx_queues(tp
->dev
, 1);
8901 static void tg3_ints_fini(struct tg3
*tp
)
8903 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSIX
)
8904 pci_disable_msix(tp
->pdev
);
8905 else if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
)
8906 pci_disable_msi(tp
->pdev
);
8907 tp
->tg3_flags2
&= ~TG3_FLG2_USING_MSI_OR_MSIX
;
8908 tp
->tg3_flags3
&= ~(TG3_FLG3_ENABLE_RSS
| TG3_FLG3_ENABLE_TSS
);
8911 static int tg3_open(struct net_device
*dev
)
8913 struct tg3
*tp
= netdev_priv(dev
);
8916 if (tp
->fw_needed
) {
8917 err
= tg3_request_firmware(tp
);
8918 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
) {
8922 netdev_warn(tp
->dev
, "TSO capability disabled\n");
8923 tp
->tg3_flags2
&= ~TG3_FLG2_TSO_CAPABLE
;
8924 } else if (!(tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
)) {
8925 netdev_notice(tp
->dev
, "TSO capability restored\n");
8926 tp
->tg3_flags2
|= TG3_FLG2_TSO_CAPABLE
;
8930 netif_carrier_off(tp
->dev
);
8932 err
= tg3_set_power_state(tp
, PCI_D0
);
8936 tg3_full_lock(tp
, 0);
8938 tg3_disable_ints(tp
);
8939 tp
->tg3_flags
&= ~TG3_FLAG_INIT_COMPLETE
;
8941 tg3_full_unlock(tp
);
8944 * Setup interrupts first so we know how
8945 * many NAPI resources to allocate
8949 /* The placement of this call is tied
8950 * to the setup and use of Host TX descriptors.
8952 err
= tg3_alloc_consistent(tp
);
8958 tg3_napi_enable(tp
);
8960 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
8961 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
8962 err
= tg3_request_irq(tp
, i
);
8964 for (i
--; i
>= 0; i
--)
8965 free_irq(tnapi
->irq_vec
, tnapi
);
8973 tg3_full_lock(tp
, 0);
8975 err
= tg3_init_hw(tp
, 1);
8977 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
8980 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)
8981 tp
->timer_offset
= HZ
;
8983 tp
->timer_offset
= HZ
/ 10;
8985 BUG_ON(tp
->timer_offset
> HZ
);
8986 tp
->timer_counter
= tp
->timer_multiplier
=
8987 (HZ
/ tp
->timer_offset
);
8988 tp
->asf_counter
= tp
->asf_multiplier
=
8989 ((HZ
/ tp
->timer_offset
) * 2);
8991 init_timer(&tp
->timer
);
8992 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
8993 tp
->timer
.data
= (unsigned long) tp
;
8994 tp
->timer
.function
= tg3_timer
;
8997 tg3_full_unlock(tp
);
9002 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
9003 err
= tg3_test_msi(tp
);
9006 tg3_full_lock(tp
, 0);
9007 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
9009 tg3_full_unlock(tp
);
9014 if (!(tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
) &&
9015 (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
)) {
9016 u32 val
= tr32(PCIE_TRANSACTION_CFG
);
9018 tw32(PCIE_TRANSACTION_CFG
,
9019 val
| PCIE_TRANS_CFG_1SHOT_MSI
);
9025 tg3_full_lock(tp
, 0);
9027 add_timer(&tp
->timer
);
9028 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
9029 tg3_enable_ints(tp
);
9031 tg3_full_unlock(tp
);
9033 netif_tx_start_all_queues(dev
);
9038 for (i
= tp
->irq_cnt
- 1; i
>= 0; i
--) {
9039 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
9040 free_irq(tnapi
->irq_vec
, tnapi
);
9044 tg3_napi_disable(tp
);
9046 tg3_free_consistent(tp
);
9053 static struct rtnl_link_stats64
*tg3_get_stats64(struct net_device
*,
9054 struct rtnl_link_stats64
*);
9055 static struct tg3_ethtool_stats
*tg3_get_estats(struct tg3
*);
9057 static int tg3_close(struct net_device
*dev
)
9060 struct tg3
*tp
= netdev_priv(dev
);
9062 tg3_napi_disable(tp
);
9063 cancel_work_sync(&tp
->reset_task
);
9065 netif_tx_stop_all_queues(dev
);
9067 del_timer_sync(&tp
->timer
);
9071 tg3_full_lock(tp
, 1);
9073 tg3_disable_ints(tp
);
9075 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
9077 tp
->tg3_flags
&= ~TG3_FLAG_INIT_COMPLETE
;
9079 tg3_full_unlock(tp
);
9081 for (i
= tp
->irq_cnt
- 1; i
>= 0; i
--) {
9082 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
9083 free_irq(tnapi
->irq_vec
, tnapi
);
9088 tg3_get_stats64(tp
->dev
, &tp
->net_stats_prev
);
9090 memcpy(&tp
->estats_prev
, tg3_get_estats(tp
),
9091 sizeof(tp
->estats_prev
));
9095 tg3_free_consistent(tp
);
9097 tg3_set_power_state(tp
, PCI_D3hot
);
9099 netif_carrier_off(tp
->dev
);
9104 static inline u64
get_stat64(tg3_stat64_t
*val
)
9106 return ((u64
)val
->high
<< 32) | ((u64
)val
->low
);
9109 static u64
calc_crc_errors(struct tg3
*tp
)
9111 struct tg3_hw_stats
*hw_stats
= tp
->hw_stats
;
9113 if (!(tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) &&
9114 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
9115 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)) {
9118 spin_lock_bh(&tp
->lock
);
9119 if (!tg3_readphy(tp
, MII_TG3_TEST1
, &val
)) {
9120 tg3_writephy(tp
, MII_TG3_TEST1
,
9121 val
| MII_TG3_TEST1_CRC_EN
);
9122 tg3_readphy(tp
, MII_TG3_RXR_COUNTERS
, &val
);
9125 spin_unlock_bh(&tp
->lock
);
9127 tp
->phy_crc_errors
+= val
;
9129 return tp
->phy_crc_errors
;
9132 return get_stat64(&hw_stats
->rx_fcs_errors
);
9135 #define ESTAT_ADD(member) \
9136 estats->member = old_estats->member + \
9137 get_stat64(&hw_stats->member)
9139 static struct tg3_ethtool_stats
*tg3_get_estats(struct tg3
*tp
)
9141 struct tg3_ethtool_stats
*estats
= &tp
->estats
;
9142 struct tg3_ethtool_stats
*old_estats
= &tp
->estats_prev
;
9143 struct tg3_hw_stats
*hw_stats
= tp
->hw_stats
;
9148 ESTAT_ADD(rx_octets
);
9149 ESTAT_ADD(rx_fragments
);
9150 ESTAT_ADD(rx_ucast_packets
);
9151 ESTAT_ADD(rx_mcast_packets
);
9152 ESTAT_ADD(rx_bcast_packets
);
9153 ESTAT_ADD(rx_fcs_errors
);
9154 ESTAT_ADD(rx_align_errors
);
9155 ESTAT_ADD(rx_xon_pause_rcvd
);
9156 ESTAT_ADD(rx_xoff_pause_rcvd
);
9157 ESTAT_ADD(rx_mac_ctrl_rcvd
);
9158 ESTAT_ADD(rx_xoff_entered
);
9159 ESTAT_ADD(rx_frame_too_long_errors
);
9160 ESTAT_ADD(rx_jabbers
);
9161 ESTAT_ADD(rx_undersize_packets
);
9162 ESTAT_ADD(rx_in_length_errors
);
9163 ESTAT_ADD(rx_out_length_errors
);
9164 ESTAT_ADD(rx_64_or_less_octet_packets
);
9165 ESTAT_ADD(rx_65_to_127_octet_packets
);
9166 ESTAT_ADD(rx_128_to_255_octet_packets
);
9167 ESTAT_ADD(rx_256_to_511_octet_packets
);
9168 ESTAT_ADD(rx_512_to_1023_octet_packets
);
9169 ESTAT_ADD(rx_1024_to_1522_octet_packets
);
9170 ESTAT_ADD(rx_1523_to_2047_octet_packets
);
9171 ESTAT_ADD(rx_2048_to_4095_octet_packets
);
9172 ESTAT_ADD(rx_4096_to_8191_octet_packets
);
9173 ESTAT_ADD(rx_8192_to_9022_octet_packets
);
9175 ESTAT_ADD(tx_octets
);
9176 ESTAT_ADD(tx_collisions
);
9177 ESTAT_ADD(tx_xon_sent
);
9178 ESTAT_ADD(tx_xoff_sent
);
9179 ESTAT_ADD(tx_flow_control
);
9180 ESTAT_ADD(tx_mac_errors
);
9181 ESTAT_ADD(tx_single_collisions
);
9182 ESTAT_ADD(tx_mult_collisions
);
9183 ESTAT_ADD(tx_deferred
);
9184 ESTAT_ADD(tx_excessive_collisions
);
9185 ESTAT_ADD(tx_late_collisions
);
9186 ESTAT_ADD(tx_collide_2times
);
9187 ESTAT_ADD(tx_collide_3times
);
9188 ESTAT_ADD(tx_collide_4times
);
9189 ESTAT_ADD(tx_collide_5times
);
9190 ESTAT_ADD(tx_collide_6times
);
9191 ESTAT_ADD(tx_collide_7times
);
9192 ESTAT_ADD(tx_collide_8times
);
9193 ESTAT_ADD(tx_collide_9times
);
9194 ESTAT_ADD(tx_collide_10times
);
9195 ESTAT_ADD(tx_collide_11times
);
9196 ESTAT_ADD(tx_collide_12times
);
9197 ESTAT_ADD(tx_collide_13times
);
9198 ESTAT_ADD(tx_collide_14times
);
9199 ESTAT_ADD(tx_collide_15times
);
9200 ESTAT_ADD(tx_ucast_packets
);
9201 ESTAT_ADD(tx_mcast_packets
);
9202 ESTAT_ADD(tx_bcast_packets
);
9203 ESTAT_ADD(tx_carrier_sense_errors
);
9204 ESTAT_ADD(tx_discards
);
9205 ESTAT_ADD(tx_errors
);
9207 ESTAT_ADD(dma_writeq_full
);
9208 ESTAT_ADD(dma_write_prioq_full
);
9209 ESTAT_ADD(rxbds_empty
);
9210 ESTAT_ADD(rx_discards
);
9211 ESTAT_ADD(rx_errors
);
9212 ESTAT_ADD(rx_threshold_hit
);
9214 ESTAT_ADD(dma_readq_full
);
9215 ESTAT_ADD(dma_read_prioq_full
);
9216 ESTAT_ADD(tx_comp_queue_full
);
9218 ESTAT_ADD(ring_set_send_prod_index
);
9219 ESTAT_ADD(ring_status_update
);
9220 ESTAT_ADD(nic_irqs
);
9221 ESTAT_ADD(nic_avoided_irqs
);
9222 ESTAT_ADD(nic_tx_threshold_hit
);
9227 static struct rtnl_link_stats64
*tg3_get_stats64(struct net_device
*dev
,
9228 struct rtnl_link_stats64
*stats
)
9230 struct tg3
*tp
= netdev_priv(dev
);
9231 struct rtnl_link_stats64
*old_stats
= &tp
->net_stats_prev
;
9232 struct tg3_hw_stats
*hw_stats
= tp
->hw_stats
;
9237 stats
->rx_packets
= old_stats
->rx_packets
+
9238 get_stat64(&hw_stats
->rx_ucast_packets
) +
9239 get_stat64(&hw_stats
->rx_mcast_packets
) +
9240 get_stat64(&hw_stats
->rx_bcast_packets
);
9242 stats
->tx_packets
= old_stats
->tx_packets
+
9243 get_stat64(&hw_stats
->tx_ucast_packets
) +
9244 get_stat64(&hw_stats
->tx_mcast_packets
) +
9245 get_stat64(&hw_stats
->tx_bcast_packets
);
9247 stats
->rx_bytes
= old_stats
->rx_bytes
+
9248 get_stat64(&hw_stats
->rx_octets
);
9249 stats
->tx_bytes
= old_stats
->tx_bytes
+
9250 get_stat64(&hw_stats
->tx_octets
);
9252 stats
->rx_errors
= old_stats
->rx_errors
+
9253 get_stat64(&hw_stats
->rx_errors
);
9254 stats
->tx_errors
= old_stats
->tx_errors
+
9255 get_stat64(&hw_stats
->tx_errors
) +
9256 get_stat64(&hw_stats
->tx_mac_errors
) +
9257 get_stat64(&hw_stats
->tx_carrier_sense_errors
) +
9258 get_stat64(&hw_stats
->tx_discards
);
9260 stats
->multicast
= old_stats
->multicast
+
9261 get_stat64(&hw_stats
->rx_mcast_packets
);
9262 stats
->collisions
= old_stats
->collisions
+
9263 get_stat64(&hw_stats
->tx_collisions
);
9265 stats
->rx_length_errors
= old_stats
->rx_length_errors
+
9266 get_stat64(&hw_stats
->rx_frame_too_long_errors
) +
9267 get_stat64(&hw_stats
->rx_undersize_packets
);
9269 stats
->rx_over_errors
= old_stats
->rx_over_errors
+
9270 get_stat64(&hw_stats
->rxbds_empty
);
9271 stats
->rx_frame_errors
= old_stats
->rx_frame_errors
+
9272 get_stat64(&hw_stats
->rx_align_errors
);
9273 stats
->tx_aborted_errors
= old_stats
->tx_aborted_errors
+
9274 get_stat64(&hw_stats
->tx_discards
);
9275 stats
->tx_carrier_errors
= old_stats
->tx_carrier_errors
+
9276 get_stat64(&hw_stats
->tx_carrier_sense_errors
);
9278 stats
->rx_crc_errors
= old_stats
->rx_crc_errors
+
9279 calc_crc_errors(tp
);
9281 stats
->rx_missed_errors
= old_stats
->rx_missed_errors
+
9282 get_stat64(&hw_stats
->rx_discards
);
9287 static inline u32
calc_crc(unsigned char *buf
, int len
)
9295 for (j
= 0; j
< len
; j
++) {
9298 for (k
= 0; k
< 8; k
++) {
9311 static void tg3_set_multi(struct tg3
*tp
, unsigned int accept_all
)
9313 /* accept or reject all multicast frames */
9314 tw32(MAC_HASH_REG_0
, accept_all
? 0xffffffff : 0);
9315 tw32(MAC_HASH_REG_1
, accept_all
? 0xffffffff : 0);
9316 tw32(MAC_HASH_REG_2
, accept_all
? 0xffffffff : 0);
9317 tw32(MAC_HASH_REG_3
, accept_all
? 0xffffffff : 0);
9320 static void __tg3_set_rx_mode(struct net_device
*dev
)
9322 struct tg3
*tp
= netdev_priv(dev
);
9325 rx_mode
= tp
->rx_mode
& ~(RX_MODE_PROMISC
|
9326 RX_MODE_KEEP_VLAN_TAG
);
9328 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9331 #if TG3_VLAN_TAG_USED
9333 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
9334 rx_mode
|= RX_MODE_KEEP_VLAN_TAG
;
9336 /* By definition, VLAN is disabled always in this
9339 if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
9340 rx_mode
|= RX_MODE_KEEP_VLAN_TAG
;
9343 if (dev
->flags
& IFF_PROMISC
) {
9344 /* Promiscuous mode. */
9345 rx_mode
|= RX_MODE_PROMISC
;
9346 } else if (dev
->flags
& IFF_ALLMULTI
) {
9347 /* Accept all multicast. */
9348 tg3_set_multi(tp
, 1);
9349 } else if (netdev_mc_empty(dev
)) {
9350 /* Reject all multicast. */
9351 tg3_set_multi(tp
, 0);
9353 /* Accept one or more multicast(s). */
9354 struct netdev_hw_addr
*ha
;
9355 u32 mc_filter
[4] = { 0, };
9360 netdev_for_each_mc_addr(ha
, dev
) {
9361 crc
= calc_crc(ha
->addr
, ETH_ALEN
);
9363 regidx
= (bit
& 0x60) >> 5;
9365 mc_filter
[regidx
] |= (1 << bit
);
9368 tw32(MAC_HASH_REG_0
, mc_filter
[0]);
9369 tw32(MAC_HASH_REG_1
, mc_filter
[1]);
9370 tw32(MAC_HASH_REG_2
, mc_filter
[2]);
9371 tw32(MAC_HASH_REG_3
, mc_filter
[3]);
9374 if (rx_mode
!= tp
->rx_mode
) {
9375 tp
->rx_mode
= rx_mode
;
9376 tw32_f(MAC_RX_MODE
, rx_mode
);
9381 static void tg3_set_rx_mode(struct net_device
*dev
)
9383 struct tg3
*tp
= netdev_priv(dev
);
9385 if (!netif_running(dev
))
9388 tg3_full_lock(tp
, 0);
9389 __tg3_set_rx_mode(dev
);
9390 tg3_full_unlock(tp
);
9393 #define TG3_REGDUMP_LEN (32 * 1024)
9395 static int tg3_get_regs_len(struct net_device
*dev
)
9397 return TG3_REGDUMP_LEN
;
9400 static void tg3_get_regs(struct net_device
*dev
,
9401 struct ethtool_regs
*regs
, void *_p
)
9404 struct tg3
*tp
= netdev_priv(dev
);
9410 memset(p
, 0, TG3_REGDUMP_LEN
);
9412 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)
9415 tg3_full_lock(tp
, 0);
9417 #define __GET_REG32(reg) (*(p)++ = tr32(reg))
9418 #define GET_REG32_LOOP(base, len) \
9419 do { p = (u32 *)(orig_p + (base)); \
9420 for (i = 0; i < len; i += 4) \
9421 __GET_REG32((base) + i); \
9423 #define GET_REG32_1(reg) \
9424 do { p = (u32 *)(orig_p + (reg)); \
9425 __GET_REG32((reg)); \
9428 GET_REG32_LOOP(TG3PCI_VENDOR
, 0xb0);
9429 GET_REG32_LOOP(MAILBOX_INTERRUPT_0
, 0x200);
9430 GET_REG32_LOOP(MAC_MODE
, 0x4f0);
9431 GET_REG32_LOOP(SNDDATAI_MODE
, 0xe0);
9432 GET_REG32_1(SNDDATAC_MODE
);
9433 GET_REG32_LOOP(SNDBDS_MODE
, 0x80);
9434 GET_REG32_LOOP(SNDBDI_MODE
, 0x48);
9435 GET_REG32_1(SNDBDC_MODE
);
9436 GET_REG32_LOOP(RCVLPC_MODE
, 0x20);
9437 GET_REG32_LOOP(RCVLPC_SELLST_BASE
, 0x15c);
9438 GET_REG32_LOOP(RCVDBDI_MODE
, 0x0c);
9439 GET_REG32_LOOP(RCVDBDI_JUMBO_BD
, 0x3c);
9440 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0
, 0x44);
9441 GET_REG32_1(RCVDCC_MODE
);
9442 GET_REG32_LOOP(RCVBDI_MODE
, 0x20);
9443 GET_REG32_LOOP(RCVCC_MODE
, 0x14);
9444 GET_REG32_LOOP(RCVLSC_MODE
, 0x08);
9445 GET_REG32_1(MBFREE_MODE
);
9446 GET_REG32_LOOP(HOSTCC_MODE
, 0x100);
9447 GET_REG32_LOOP(MEMARB_MODE
, 0x10);
9448 GET_REG32_LOOP(BUFMGR_MODE
, 0x58);
9449 GET_REG32_LOOP(RDMAC_MODE
, 0x08);
9450 GET_REG32_LOOP(WDMAC_MODE
, 0x08);
9451 GET_REG32_1(RX_CPU_MODE
);
9452 GET_REG32_1(RX_CPU_STATE
);
9453 GET_REG32_1(RX_CPU_PGMCTR
);
9454 GET_REG32_1(RX_CPU_HWBKPT
);
9455 GET_REG32_1(TX_CPU_MODE
);
9456 GET_REG32_1(TX_CPU_STATE
);
9457 GET_REG32_1(TX_CPU_PGMCTR
);
9458 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0
, 0x110);
9459 GET_REG32_LOOP(FTQ_RESET
, 0x120);
9460 GET_REG32_LOOP(MSGINT_MODE
, 0x0c);
9461 GET_REG32_1(DMAC_MODE
);
9462 GET_REG32_LOOP(GRC_MODE
, 0x4c);
9463 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
)
9464 GET_REG32_LOOP(NVRAM_CMD
, 0x24);
9467 #undef GET_REG32_LOOP
9470 tg3_full_unlock(tp
);
9473 static int tg3_get_eeprom_len(struct net_device
*dev
)
9475 struct tg3
*tp
= netdev_priv(dev
);
9477 return tp
->nvram_size
;
9480 static int tg3_get_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
, u8
*data
)
9482 struct tg3
*tp
= netdev_priv(dev
);
9485 u32 i
, offset
, len
, b_offset
, b_count
;
9488 if (tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
)
9491 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)
9494 offset
= eeprom
->offset
;
9498 eeprom
->magic
= TG3_EEPROM_MAGIC
;
9501 /* adjustments to start on required 4 byte boundary */
9502 b_offset
= offset
& 3;
9503 b_count
= 4 - b_offset
;
9504 if (b_count
> len
) {
9505 /* i.e. offset=1 len=2 */
9508 ret
= tg3_nvram_read_be32(tp
, offset
-b_offset
, &val
);
9511 memcpy(data
, ((char *)&val
) + b_offset
, b_count
);
9514 eeprom
->len
+= b_count
;
9517 /* read bytes upto the last 4 byte boundary */
9518 pd
= &data
[eeprom
->len
];
9519 for (i
= 0; i
< (len
- (len
& 3)); i
+= 4) {
9520 ret
= tg3_nvram_read_be32(tp
, offset
+ i
, &val
);
9525 memcpy(pd
+ i
, &val
, 4);
9530 /* read last bytes not ending on 4 byte boundary */
9531 pd
= &data
[eeprom
->len
];
9533 b_offset
= offset
+ len
- b_count
;
9534 ret
= tg3_nvram_read_be32(tp
, b_offset
, &val
);
9537 memcpy(pd
, &val
, b_count
);
9538 eeprom
->len
+= b_count
;
9543 static int tg3_nvram_write_block(struct tg3
*tp
, u32 offset
, u32 len
, u8
*buf
);
9545 static int tg3_set_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
, u8
*data
)
9547 struct tg3
*tp
= netdev_priv(dev
);
9549 u32 offset
, len
, b_offset
, odd_len
;
9553 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)
9556 if ((tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) ||
9557 eeprom
->magic
!= TG3_EEPROM_MAGIC
)
9560 offset
= eeprom
->offset
;
9563 if ((b_offset
= (offset
& 3))) {
9564 /* adjustments to start on required 4 byte boundary */
9565 ret
= tg3_nvram_read_be32(tp
, offset
-b_offset
, &start
);
9576 /* adjustments to end on required 4 byte boundary */
9578 len
= (len
+ 3) & ~3;
9579 ret
= tg3_nvram_read_be32(tp
, offset
+len
-4, &end
);
9585 if (b_offset
|| odd_len
) {
9586 buf
= kmalloc(len
, GFP_KERNEL
);
9590 memcpy(buf
, &start
, 4);
9592 memcpy(buf
+len
-4, &end
, 4);
9593 memcpy(buf
+ b_offset
, data
, eeprom
->len
);
9596 ret
= tg3_nvram_write_block(tp
, offset
, len
, buf
);
9604 static int tg3_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
9606 struct tg3
*tp
= netdev_priv(dev
);
9608 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
9609 struct phy_device
*phydev
;
9610 if (!(tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
))
9612 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
9613 return phy_ethtool_gset(phydev
, cmd
);
9616 cmd
->supported
= (SUPPORTED_Autoneg
);
9618 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
))
9619 cmd
->supported
|= (SUPPORTED_1000baseT_Half
|
9620 SUPPORTED_1000baseT_Full
);
9622 if (!(tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
)) {
9623 cmd
->supported
|= (SUPPORTED_100baseT_Half
|
9624 SUPPORTED_100baseT_Full
|
9625 SUPPORTED_10baseT_Half
|
9626 SUPPORTED_10baseT_Full
|
9628 cmd
->port
= PORT_TP
;
9630 cmd
->supported
|= SUPPORTED_FIBRE
;
9631 cmd
->port
= PORT_FIBRE
;
9634 cmd
->advertising
= tp
->link_config
.advertising
;
9635 if (netif_running(dev
)) {
9636 cmd
->speed
= tp
->link_config
.active_speed
;
9637 cmd
->duplex
= tp
->link_config
.active_duplex
;
9639 cmd
->phy_address
= tp
->phy_addr
;
9640 cmd
->transceiver
= XCVR_INTERNAL
;
9641 cmd
->autoneg
= tp
->link_config
.autoneg
;
9647 static int tg3_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
9649 struct tg3
*tp
= netdev_priv(dev
);
9651 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
9652 struct phy_device
*phydev
;
9653 if (!(tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
))
9655 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
9656 return phy_ethtool_sset(phydev
, cmd
);
9659 if (cmd
->autoneg
!= AUTONEG_ENABLE
&&
9660 cmd
->autoneg
!= AUTONEG_DISABLE
)
9663 if (cmd
->autoneg
== AUTONEG_DISABLE
&&
9664 cmd
->duplex
!= DUPLEX_FULL
&&
9665 cmd
->duplex
!= DUPLEX_HALF
)
9668 if (cmd
->autoneg
== AUTONEG_ENABLE
) {
9669 u32 mask
= ADVERTISED_Autoneg
|
9671 ADVERTISED_Asym_Pause
;
9673 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
))
9674 mask
|= ADVERTISED_1000baseT_Half
|
9675 ADVERTISED_1000baseT_Full
;
9677 if (!(tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
))
9678 mask
|= ADVERTISED_100baseT_Half
|
9679 ADVERTISED_100baseT_Full
|
9680 ADVERTISED_10baseT_Half
|
9681 ADVERTISED_10baseT_Full
|
9684 mask
|= ADVERTISED_FIBRE
;
9686 if (cmd
->advertising
& ~mask
)
9689 mask
&= (ADVERTISED_1000baseT_Half
|
9690 ADVERTISED_1000baseT_Full
|
9691 ADVERTISED_100baseT_Half
|
9692 ADVERTISED_100baseT_Full
|
9693 ADVERTISED_10baseT_Half
|
9694 ADVERTISED_10baseT_Full
);
9696 cmd
->advertising
&= mask
;
9698 if (tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
) {
9699 if (cmd
->speed
!= SPEED_1000
)
9702 if (cmd
->duplex
!= DUPLEX_FULL
)
9705 if (cmd
->speed
!= SPEED_100
&&
9706 cmd
->speed
!= SPEED_10
)
9711 tg3_full_lock(tp
, 0);
9713 tp
->link_config
.autoneg
= cmd
->autoneg
;
9714 if (cmd
->autoneg
== AUTONEG_ENABLE
) {
9715 tp
->link_config
.advertising
= (cmd
->advertising
|
9716 ADVERTISED_Autoneg
);
9717 tp
->link_config
.speed
= SPEED_INVALID
;
9718 tp
->link_config
.duplex
= DUPLEX_INVALID
;
9720 tp
->link_config
.advertising
= 0;
9721 tp
->link_config
.speed
= cmd
->speed
;
9722 tp
->link_config
.duplex
= cmd
->duplex
;
9725 tp
->link_config
.orig_speed
= tp
->link_config
.speed
;
9726 tp
->link_config
.orig_duplex
= tp
->link_config
.duplex
;
9727 tp
->link_config
.orig_autoneg
= tp
->link_config
.autoneg
;
9729 if (netif_running(dev
))
9730 tg3_setup_phy(tp
, 1);
9732 tg3_full_unlock(tp
);
9737 static void tg3_get_drvinfo(struct net_device
*dev
, struct ethtool_drvinfo
*info
)
9739 struct tg3
*tp
= netdev_priv(dev
);
9741 strcpy(info
->driver
, DRV_MODULE_NAME
);
9742 strcpy(info
->version
, DRV_MODULE_VERSION
);
9743 strcpy(info
->fw_version
, tp
->fw_ver
);
9744 strcpy(info
->bus_info
, pci_name(tp
->pdev
));
9747 static void tg3_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
9749 struct tg3
*tp
= netdev_priv(dev
);
9751 if ((tp
->tg3_flags
& TG3_FLAG_WOL_CAP
) &&
9752 device_can_wakeup(&tp
->pdev
->dev
))
9753 wol
->supported
= WAKE_MAGIC
;
9757 if ((tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
) &&
9758 device_can_wakeup(&tp
->pdev
->dev
))
9759 wol
->wolopts
= WAKE_MAGIC
;
9760 memset(&wol
->sopass
, 0, sizeof(wol
->sopass
));
9763 static int tg3_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
9765 struct tg3
*tp
= netdev_priv(dev
);
9766 struct device
*dp
= &tp
->pdev
->dev
;
9768 if (wol
->wolopts
& ~WAKE_MAGIC
)
9770 if ((wol
->wolopts
& WAKE_MAGIC
) &&
9771 !((tp
->tg3_flags
& TG3_FLAG_WOL_CAP
) && device_can_wakeup(dp
)))
9774 spin_lock_bh(&tp
->lock
);
9775 if (wol
->wolopts
& WAKE_MAGIC
) {
9776 tp
->tg3_flags
|= TG3_FLAG_WOL_ENABLE
;
9777 device_set_wakeup_enable(dp
, true);
9779 tp
->tg3_flags
&= ~TG3_FLAG_WOL_ENABLE
;
9780 device_set_wakeup_enable(dp
, false);
9782 spin_unlock_bh(&tp
->lock
);
9787 static u32
tg3_get_msglevel(struct net_device
*dev
)
9789 struct tg3
*tp
= netdev_priv(dev
);
9790 return tp
->msg_enable
;
9793 static void tg3_set_msglevel(struct net_device
*dev
, u32 value
)
9795 struct tg3
*tp
= netdev_priv(dev
);
9796 tp
->msg_enable
= value
;
9799 static int tg3_set_tso(struct net_device
*dev
, u32 value
)
9801 struct tg3
*tp
= netdev_priv(dev
);
9803 if (!(tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
)) {
9808 if ((dev
->features
& NETIF_F_IPV6_CSUM
) &&
9809 ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO_2
) ||
9810 (tp
->tg3_flags2
& TG3_FLG2_HW_TSO_3
))) {
9812 dev
->features
|= NETIF_F_TSO6
;
9813 if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO_3
) ||
9814 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
9815 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
9816 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
) ||
9817 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
9818 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
9819 dev
->features
|= NETIF_F_TSO_ECN
;
9821 dev
->features
&= ~(NETIF_F_TSO6
| NETIF_F_TSO_ECN
);
9823 return ethtool_op_set_tso(dev
, value
);
9826 static int tg3_nway_reset(struct net_device
*dev
)
9828 struct tg3
*tp
= netdev_priv(dev
);
9831 if (!netif_running(dev
))
9834 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
)
9837 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
9838 if (!(tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
))
9840 r
= phy_start_aneg(tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
]);
9844 spin_lock_bh(&tp
->lock
);
9846 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
9847 if (!tg3_readphy(tp
, MII_BMCR
, &bmcr
) &&
9848 ((bmcr
& BMCR_ANENABLE
) ||
9849 (tp
->phy_flags
& TG3_PHYFLG_PARALLEL_DETECT
))) {
9850 tg3_writephy(tp
, MII_BMCR
, bmcr
| BMCR_ANRESTART
|
9854 spin_unlock_bh(&tp
->lock
);
9860 static void tg3_get_ringparam(struct net_device
*dev
, struct ethtool_ringparam
*ering
)
9862 struct tg3
*tp
= netdev_priv(dev
);
9864 ering
->rx_max_pending
= tp
->rx_std_ring_mask
;
9865 ering
->rx_mini_max_pending
= 0;
9866 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
)
9867 ering
->rx_jumbo_max_pending
= tp
->rx_jmb_ring_mask
;
9869 ering
->rx_jumbo_max_pending
= 0;
9871 ering
->tx_max_pending
= TG3_TX_RING_SIZE
- 1;
9873 ering
->rx_pending
= tp
->rx_pending
;
9874 ering
->rx_mini_pending
= 0;
9875 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
)
9876 ering
->rx_jumbo_pending
= tp
->rx_jumbo_pending
;
9878 ering
->rx_jumbo_pending
= 0;
9880 ering
->tx_pending
= tp
->napi
[0].tx_pending
;
9883 static int tg3_set_ringparam(struct net_device
*dev
, struct ethtool_ringparam
*ering
)
9885 struct tg3
*tp
= netdev_priv(dev
);
9886 int i
, irq_sync
= 0, err
= 0;
9888 if ((ering
->rx_pending
> tp
->rx_std_ring_mask
) ||
9889 (ering
->rx_jumbo_pending
> tp
->rx_jmb_ring_mask
) ||
9890 (ering
->tx_pending
> TG3_TX_RING_SIZE
- 1) ||
9891 (ering
->tx_pending
<= MAX_SKB_FRAGS
) ||
9892 ((tp
->tg3_flags2
& TG3_FLG2_TSO_BUG
) &&
9893 (ering
->tx_pending
<= (MAX_SKB_FRAGS
* 3))))
9896 if (netif_running(dev
)) {
9902 tg3_full_lock(tp
, irq_sync
);
9904 tp
->rx_pending
= ering
->rx_pending
;
9906 if ((tp
->tg3_flags2
& TG3_FLG2_MAX_RXPEND_64
) &&
9907 tp
->rx_pending
> 63)
9908 tp
->rx_pending
= 63;
9909 tp
->rx_jumbo_pending
= ering
->rx_jumbo_pending
;
9911 for (i
= 0; i
< tp
->irq_max
; i
++)
9912 tp
->napi
[i
].tx_pending
= ering
->tx_pending
;
9914 if (netif_running(dev
)) {
9915 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
9916 err
= tg3_restart_hw(tp
, 1);
9918 tg3_netif_start(tp
);
9921 tg3_full_unlock(tp
);
9923 if (irq_sync
&& !err
)
9929 static void tg3_get_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
*epause
)
9931 struct tg3
*tp
= netdev_priv(dev
);
9933 epause
->autoneg
= (tp
->tg3_flags
& TG3_FLAG_PAUSE_AUTONEG
) != 0;
9935 if (tp
->link_config
.active_flowctrl
& FLOW_CTRL_RX
)
9936 epause
->rx_pause
= 1;
9938 epause
->rx_pause
= 0;
9940 if (tp
->link_config
.active_flowctrl
& FLOW_CTRL_TX
)
9941 epause
->tx_pause
= 1;
9943 epause
->tx_pause
= 0;
9946 static int tg3_set_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
*epause
)
9948 struct tg3
*tp
= netdev_priv(dev
);
9951 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
9953 struct phy_device
*phydev
;
9955 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
9957 if (!(phydev
->supported
& SUPPORTED_Pause
) ||
9958 (!(phydev
->supported
& SUPPORTED_Asym_Pause
) &&
9959 ((epause
->rx_pause
&& !epause
->tx_pause
) ||
9960 (!epause
->rx_pause
&& epause
->tx_pause
))))
9963 tp
->link_config
.flowctrl
= 0;
9964 if (epause
->rx_pause
) {
9965 tp
->link_config
.flowctrl
|= FLOW_CTRL_RX
;
9967 if (epause
->tx_pause
) {
9968 tp
->link_config
.flowctrl
|= FLOW_CTRL_TX
;
9969 newadv
= ADVERTISED_Pause
;
9971 newadv
= ADVERTISED_Pause
|
9972 ADVERTISED_Asym_Pause
;
9973 } else if (epause
->tx_pause
) {
9974 tp
->link_config
.flowctrl
|= FLOW_CTRL_TX
;
9975 newadv
= ADVERTISED_Asym_Pause
;
9979 if (epause
->autoneg
)
9980 tp
->tg3_flags
|= TG3_FLAG_PAUSE_AUTONEG
;
9982 tp
->tg3_flags
&= ~TG3_FLAG_PAUSE_AUTONEG
;
9984 if (tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
) {
9985 u32 oldadv
= phydev
->advertising
&
9986 (ADVERTISED_Pause
| ADVERTISED_Asym_Pause
);
9987 if (oldadv
!= newadv
) {
9988 phydev
->advertising
&=
9989 ~(ADVERTISED_Pause
|
9990 ADVERTISED_Asym_Pause
);
9991 phydev
->advertising
|= newadv
;
9992 if (phydev
->autoneg
) {
9994 * Always renegotiate the link to
9995 * inform our link partner of our
9996 * flow control settings, even if the
9997 * flow control is forced. Let
9998 * tg3_adjust_link() do the final
9999 * flow control setup.
10001 return phy_start_aneg(phydev
);
10005 if (!epause
->autoneg
)
10006 tg3_setup_flow_control(tp
, 0, 0);
10008 tp
->link_config
.orig_advertising
&=
10009 ~(ADVERTISED_Pause
|
10010 ADVERTISED_Asym_Pause
);
10011 tp
->link_config
.orig_advertising
|= newadv
;
10016 if (netif_running(dev
)) {
10017 tg3_netif_stop(tp
);
10021 tg3_full_lock(tp
, irq_sync
);
10023 if (epause
->autoneg
)
10024 tp
->tg3_flags
|= TG3_FLAG_PAUSE_AUTONEG
;
10026 tp
->tg3_flags
&= ~TG3_FLAG_PAUSE_AUTONEG
;
10027 if (epause
->rx_pause
)
10028 tp
->link_config
.flowctrl
|= FLOW_CTRL_RX
;
10030 tp
->link_config
.flowctrl
&= ~FLOW_CTRL_RX
;
10031 if (epause
->tx_pause
)
10032 tp
->link_config
.flowctrl
|= FLOW_CTRL_TX
;
10034 tp
->link_config
.flowctrl
&= ~FLOW_CTRL_TX
;
10036 if (netif_running(dev
)) {
10037 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
10038 err
= tg3_restart_hw(tp
, 1);
10040 tg3_netif_start(tp
);
10043 tg3_full_unlock(tp
);
10049 static u32
tg3_get_rx_csum(struct net_device
*dev
)
10051 struct tg3
*tp
= netdev_priv(dev
);
10052 return (tp
->tg3_flags
& TG3_FLAG_RX_CHECKSUMS
) != 0;
10055 static int tg3_set_rx_csum(struct net_device
*dev
, u32 data
)
10057 struct tg3
*tp
= netdev_priv(dev
);
10059 if (tp
->tg3_flags
& TG3_FLAG_BROKEN_CHECKSUMS
) {
10065 spin_lock_bh(&tp
->lock
);
10067 tp
->tg3_flags
|= TG3_FLAG_RX_CHECKSUMS
;
10069 tp
->tg3_flags
&= ~TG3_FLAG_RX_CHECKSUMS
;
10070 spin_unlock_bh(&tp
->lock
);
10075 static int tg3_set_tx_csum(struct net_device
*dev
, u32 data
)
10077 struct tg3
*tp
= netdev_priv(dev
);
10079 if (tp
->tg3_flags
& TG3_FLAG_BROKEN_CHECKSUMS
) {
10085 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
10086 ethtool_op_set_tx_ipv6_csum(dev
, data
);
10088 ethtool_op_set_tx_csum(dev
, data
);
10093 static int tg3_get_sset_count(struct net_device
*dev
, int sset
)
10097 return TG3_NUM_TEST
;
10099 return TG3_NUM_STATS
;
10101 return -EOPNOTSUPP
;
10105 static void tg3_get_strings(struct net_device
*dev
, u32 stringset
, u8
*buf
)
10107 switch (stringset
) {
10109 memcpy(buf
, ðtool_stats_keys
, sizeof(ethtool_stats_keys
));
10112 memcpy(buf
, ðtool_test_keys
, sizeof(ethtool_test_keys
));
10115 WARN_ON(1); /* we need a WARN() */
10120 static int tg3_phys_id(struct net_device
*dev
, u32 data
)
10122 struct tg3
*tp
= netdev_priv(dev
);
10125 if (!netif_running(tp
->dev
))
10129 data
= UINT_MAX
/ 2;
10131 for (i
= 0; i
< (data
* 2); i
++) {
10133 tw32(MAC_LED_CTRL
, LED_CTRL_LNKLED_OVERRIDE
|
10134 LED_CTRL_1000MBPS_ON
|
10135 LED_CTRL_100MBPS_ON
|
10136 LED_CTRL_10MBPS_ON
|
10137 LED_CTRL_TRAFFIC_OVERRIDE
|
10138 LED_CTRL_TRAFFIC_BLINK
|
10139 LED_CTRL_TRAFFIC_LED
);
10142 tw32(MAC_LED_CTRL
, LED_CTRL_LNKLED_OVERRIDE
|
10143 LED_CTRL_TRAFFIC_OVERRIDE
);
10145 if (msleep_interruptible(500))
10148 tw32(MAC_LED_CTRL
, tp
->led_ctrl
);
10152 static void tg3_get_ethtool_stats(struct net_device
*dev
,
10153 struct ethtool_stats
*estats
, u64
*tmp_stats
)
10155 struct tg3
*tp
= netdev_priv(dev
);
10156 memcpy(tmp_stats
, tg3_get_estats(tp
), sizeof(tp
->estats
));
10159 #define NVRAM_TEST_SIZE 0x100
10160 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
10161 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
10162 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
10163 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10164 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10166 static int tg3_test_nvram(struct tg3
*tp
)
10170 int i
, j
, k
, err
= 0, size
;
10172 if (tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
)
10175 if (tg3_nvram_read(tp
, 0, &magic
) != 0)
10178 if (magic
== TG3_EEPROM_MAGIC
)
10179 size
= NVRAM_TEST_SIZE
;
10180 else if ((magic
& TG3_EEPROM_MAGIC_FW_MSK
) == TG3_EEPROM_MAGIC_FW
) {
10181 if ((magic
& TG3_EEPROM_SB_FORMAT_MASK
) ==
10182 TG3_EEPROM_SB_FORMAT_1
) {
10183 switch (magic
& TG3_EEPROM_SB_REVISION_MASK
) {
10184 case TG3_EEPROM_SB_REVISION_0
:
10185 size
= NVRAM_SELFBOOT_FORMAT1_0_SIZE
;
10187 case TG3_EEPROM_SB_REVISION_2
:
10188 size
= NVRAM_SELFBOOT_FORMAT1_2_SIZE
;
10190 case TG3_EEPROM_SB_REVISION_3
:
10191 size
= NVRAM_SELFBOOT_FORMAT1_3_SIZE
;
10198 } else if ((magic
& TG3_EEPROM_MAGIC_HW_MSK
) == TG3_EEPROM_MAGIC_HW
)
10199 size
= NVRAM_SELFBOOT_HW_SIZE
;
10203 buf
= kmalloc(size
, GFP_KERNEL
);
10208 for (i
= 0, j
= 0; i
< size
; i
+= 4, j
++) {
10209 err
= tg3_nvram_read_be32(tp
, i
, &buf
[j
]);
10216 /* Selfboot format */
10217 magic
= be32_to_cpu(buf
[0]);
10218 if ((magic
& TG3_EEPROM_MAGIC_FW_MSK
) ==
10219 TG3_EEPROM_MAGIC_FW
) {
10220 u8
*buf8
= (u8
*) buf
, csum8
= 0;
10222 if ((magic
& TG3_EEPROM_SB_REVISION_MASK
) ==
10223 TG3_EEPROM_SB_REVISION_2
) {
10224 /* For rev 2, the csum doesn't include the MBA. */
10225 for (i
= 0; i
< TG3_EEPROM_SB_F1R2_MBA_OFF
; i
++)
10227 for (i
= TG3_EEPROM_SB_F1R2_MBA_OFF
+ 4; i
< size
; i
++)
10230 for (i
= 0; i
< size
; i
++)
10243 if ((magic
& TG3_EEPROM_MAGIC_HW_MSK
) ==
10244 TG3_EEPROM_MAGIC_HW
) {
10245 u8 data
[NVRAM_SELFBOOT_DATA_SIZE
];
10246 u8 parity
[NVRAM_SELFBOOT_DATA_SIZE
];
10247 u8
*buf8
= (u8
*) buf
;
10249 /* Separate the parity bits and the data bytes. */
10250 for (i
= 0, j
= 0, k
= 0; i
< NVRAM_SELFBOOT_HW_SIZE
; i
++) {
10251 if ((i
== 0) || (i
== 8)) {
10255 for (l
= 0, msk
= 0x80; l
< 7; l
++, msk
>>= 1)
10256 parity
[k
++] = buf8
[i
] & msk
;
10258 } else if (i
== 16) {
10262 for (l
= 0, msk
= 0x20; l
< 6; l
++, msk
>>= 1)
10263 parity
[k
++] = buf8
[i
] & msk
;
10266 for (l
= 0, msk
= 0x80; l
< 8; l
++, msk
>>= 1)
10267 parity
[k
++] = buf8
[i
] & msk
;
10270 data
[j
++] = buf8
[i
];
10274 for (i
= 0; i
< NVRAM_SELFBOOT_DATA_SIZE
; i
++) {
10275 u8 hw8
= hweight8(data
[i
]);
10277 if ((hw8
& 0x1) && parity
[i
])
10279 else if (!(hw8
& 0x1) && !parity
[i
])
10286 /* Bootstrap checksum at offset 0x10 */
10287 csum
= calc_crc((unsigned char *) buf
, 0x10);
10288 if (csum
!= be32_to_cpu(buf
[0x10/4]))
10291 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10292 csum
= calc_crc((unsigned char *) &buf
[0x74/4], 0x88);
10293 if (csum
!= be32_to_cpu(buf
[0xfc/4]))
10303 #define TG3_SERDES_TIMEOUT_SEC 2
10304 #define TG3_COPPER_TIMEOUT_SEC 6
10306 static int tg3_test_link(struct tg3
*tp
)
10310 if (!netif_running(tp
->dev
))
10313 if (tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
)
10314 max
= TG3_SERDES_TIMEOUT_SEC
;
10316 max
= TG3_COPPER_TIMEOUT_SEC
;
10318 for (i
= 0; i
< max
; i
++) {
10319 if (netif_carrier_ok(tp
->dev
))
10322 if (msleep_interruptible(1000))
10329 /* Only test the commonly used registers */
10330 static int tg3_test_registers(struct tg3
*tp
)
10332 int i
, is_5705
, is_5750
;
10333 u32 offset
, read_mask
, write_mask
, val
, save_val
, read_val
;
10337 #define TG3_FL_5705 0x1
10338 #define TG3_FL_NOT_5705 0x2
10339 #define TG3_FL_NOT_5788 0x4
10340 #define TG3_FL_NOT_5750 0x8
10344 /* MAC Control Registers */
10345 { MAC_MODE
, TG3_FL_NOT_5705
,
10346 0x00000000, 0x00ef6f8c },
10347 { MAC_MODE
, TG3_FL_5705
,
10348 0x00000000, 0x01ef6b8c },
10349 { MAC_STATUS
, TG3_FL_NOT_5705
,
10350 0x03800107, 0x00000000 },
10351 { MAC_STATUS
, TG3_FL_5705
,
10352 0x03800100, 0x00000000 },
10353 { MAC_ADDR_0_HIGH
, 0x0000,
10354 0x00000000, 0x0000ffff },
10355 { MAC_ADDR_0_LOW
, 0x0000,
10356 0x00000000, 0xffffffff },
10357 { MAC_RX_MTU_SIZE
, 0x0000,
10358 0x00000000, 0x0000ffff },
10359 { MAC_TX_MODE
, 0x0000,
10360 0x00000000, 0x00000070 },
10361 { MAC_TX_LENGTHS
, 0x0000,
10362 0x00000000, 0x00003fff },
10363 { MAC_RX_MODE
, TG3_FL_NOT_5705
,
10364 0x00000000, 0x000007fc },
10365 { MAC_RX_MODE
, TG3_FL_5705
,
10366 0x00000000, 0x000007dc },
10367 { MAC_HASH_REG_0
, 0x0000,
10368 0x00000000, 0xffffffff },
10369 { MAC_HASH_REG_1
, 0x0000,
10370 0x00000000, 0xffffffff },
10371 { MAC_HASH_REG_2
, 0x0000,
10372 0x00000000, 0xffffffff },
10373 { MAC_HASH_REG_3
, 0x0000,
10374 0x00000000, 0xffffffff },
10376 /* Receive Data and Receive BD Initiator Control Registers. */
10377 { RCVDBDI_JUMBO_BD
+0, TG3_FL_NOT_5705
,
10378 0x00000000, 0xffffffff },
10379 { RCVDBDI_JUMBO_BD
+4, TG3_FL_NOT_5705
,
10380 0x00000000, 0xffffffff },
10381 { RCVDBDI_JUMBO_BD
+8, TG3_FL_NOT_5705
,
10382 0x00000000, 0x00000003 },
10383 { RCVDBDI_JUMBO_BD
+0xc, TG3_FL_NOT_5705
,
10384 0x00000000, 0xffffffff },
10385 { RCVDBDI_STD_BD
+0, 0x0000,
10386 0x00000000, 0xffffffff },
10387 { RCVDBDI_STD_BD
+4, 0x0000,
10388 0x00000000, 0xffffffff },
10389 { RCVDBDI_STD_BD
+8, 0x0000,
10390 0x00000000, 0xffff0002 },
10391 { RCVDBDI_STD_BD
+0xc, 0x0000,
10392 0x00000000, 0xffffffff },
10394 /* Receive BD Initiator Control Registers. */
10395 { RCVBDI_STD_THRESH
, TG3_FL_NOT_5705
,
10396 0x00000000, 0xffffffff },
10397 { RCVBDI_STD_THRESH
, TG3_FL_5705
,
10398 0x00000000, 0x000003ff },
10399 { RCVBDI_JUMBO_THRESH
, TG3_FL_NOT_5705
,
10400 0x00000000, 0xffffffff },
10402 /* Host Coalescing Control Registers. */
10403 { HOSTCC_MODE
, TG3_FL_NOT_5705
,
10404 0x00000000, 0x00000004 },
10405 { HOSTCC_MODE
, TG3_FL_5705
,
10406 0x00000000, 0x000000f6 },
10407 { HOSTCC_RXCOL_TICKS
, TG3_FL_NOT_5705
,
10408 0x00000000, 0xffffffff },
10409 { HOSTCC_RXCOL_TICKS
, TG3_FL_5705
,
10410 0x00000000, 0x000003ff },
10411 { HOSTCC_TXCOL_TICKS
, TG3_FL_NOT_5705
,
10412 0x00000000, 0xffffffff },
10413 { HOSTCC_TXCOL_TICKS
, TG3_FL_5705
,
10414 0x00000000, 0x000003ff },
10415 { HOSTCC_RXMAX_FRAMES
, TG3_FL_NOT_5705
,
10416 0x00000000, 0xffffffff },
10417 { HOSTCC_RXMAX_FRAMES
, TG3_FL_5705
| TG3_FL_NOT_5788
,
10418 0x00000000, 0x000000ff },
10419 { HOSTCC_TXMAX_FRAMES
, TG3_FL_NOT_5705
,
10420 0x00000000, 0xffffffff },
10421 { HOSTCC_TXMAX_FRAMES
, TG3_FL_5705
| TG3_FL_NOT_5788
,
10422 0x00000000, 0x000000ff },
10423 { HOSTCC_RXCOAL_TICK_INT
, TG3_FL_NOT_5705
,
10424 0x00000000, 0xffffffff },
10425 { HOSTCC_TXCOAL_TICK_INT
, TG3_FL_NOT_5705
,
10426 0x00000000, 0xffffffff },
10427 { HOSTCC_RXCOAL_MAXF_INT
, TG3_FL_NOT_5705
,
10428 0x00000000, 0xffffffff },
10429 { HOSTCC_RXCOAL_MAXF_INT
, TG3_FL_5705
| TG3_FL_NOT_5788
,
10430 0x00000000, 0x000000ff },
10431 { HOSTCC_TXCOAL_MAXF_INT
, TG3_FL_NOT_5705
,
10432 0x00000000, 0xffffffff },
10433 { HOSTCC_TXCOAL_MAXF_INT
, TG3_FL_5705
| TG3_FL_NOT_5788
,
10434 0x00000000, 0x000000ff },
10435 { HOSTCC_STAT_COAL_TICKS
, TG3_FL_NOT_5705
,
10436 0x00000000, 0xffffffff },
10437 { HOSTCC_STATS_BLK_HOST_ADDR
, TG3_FL_NOT_5705
,
10438 0x00000000, 0xffffffff },
10439 { HOSTCC_STATS_BLK_HOST_ADDR
+4, TG3_FL_NOT_5705
,
10440 0x00000000, 0xffffffff },
10441 { HOSTCC_STATUS_BLK_HOST_ADDR
, 0x0000,
10442 0x00000000, 0xffffffff },
10443 { HOSTCC_STATUS_BLK_HOST_ADDR
+4, 0x0000,
10444 0x00000000, 0xffffffff },
10445 { HOSTCC_STATS_BLK_NIC_ADDR
, 0x0000,
10446 0xffffffff, 0x00000000 },
10447 { HOSTCC_STATUS_BLK_NIC_ADDR
, 0x0000,
10448 0xffffffff, 0x00000000 },
10450 /* Buffer Manager Control Registers. */
10451 { BUFMGR_MB_POOL_ADDR
, TG3_FL_NOT_5750
,
10452 0x00000000, 0x007fff80 },
10453 { BUFMGR_MB_POOL_SIZE
, TG3_FL_NOT_5750
,
10454 0x00000000, 0x007fffff },
10455 { BUFMGR_MB_RDMA_LOW_WATER
, 0x0000,
10456 0x00000000, 0x0000003f },
10457 { BUFMGR_MB_MACRX_LOW_WATER
, 0x0000,
10458 0x00000000, 0x000001ff },
10459 { BUFMGR_MB_HIGH_WATER
, 0x0000,
10460 0x00000000, 0x000001ff },
10461 { BUFMGR_DMA_DESC_POOL_ADDR
, TG3_FL_NOT_5705
,
10462 0xffffffff, 0x00000000 },
10463 { BUFMGR_DMA_DESC_POOL_SIZE
, TG3_FL_NOT_5705
,
10464 0xffffffff, 0x00000000 },
10466 /* Mailbox Registers */
10467 { GRCMBOX_RCVSTD_PROD_IDX
+4, 0x0000,
10468 0x00000000, 0x000001ff },
10469 { GRCMBOX_RCVJUMBO_PROD_IDX
+4, TG3_FL_NOT_5705
,
10470 0x00000000, 0x000001ff },
10471 { GRCMBOX_RCVRET_CON_IDX_0
+4, 0x0000,
10472 0x00000000, 0x000007ff },
10473 { GRCMBOX_SNDHOST_PROD_IDX_0
+4, 0x0000,
10474 0x00000000, 0x000001ff },
10476 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10479 is_5705
= is_5750
= 0;
10480 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
10482 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
10486 for (i
= 0; reg_tbl
[i
].offset
!= 0xffff; i
++) {
10487 if (is_5705
&& (reg_tbl
[i
].flags
& TG3_FL_NOT_5705
))
10490 if (!is_5705
&& (reg_tbl
[i
].flags
& TG3_FL_5705
))
10493 if ((tp
->tg3_flags2
& TG3_FLG2_IS_5788
) &&
10494 (reg_tbl
[i
].flags
& TG3_FL_NOT_5788
))
10497 if (is_5750
&& (reg_tbl
[i
].flags
& TG3_FL_NOT_5750
))
10500 offset
= (u32
) reg_tbl
[i
].offset
;
10501 read_mask
= reg_tbl
[i
].read_mask
;
10502 write_mask
= reg_tbl
[i
].write_mask
;
10504 /* Save the original register content */
10505 save_val
= tr32(offset
);
10507 /* Determine the read-only value. */
10508 read_val
= save_val
& read_mask
;
10510 /* Write zero to the register, then make sure the read-only bits
10511 * are not changed and the read/write bits are all zeros.
10515 val
= tr32(offset
);
10517 /* Test the read-only and read/write bits. */
10518 if (((val
& read_mask
) != read_val
) || (val
& write_mask
))
10521 /* Write ones to all the bits defined by RdMask and WrMask, then
10522 * make sure the read-only bits are not changed and the
10523 * read/write bits are all ones.
10525 tw32(offset
, read_mask
| write_mask
);
10527 val
= tr32(offset
);
10529 /* Test the read-only bits. */
10530 if ((val
& read_mask
) != read_val
)
10533 /* Test the read/write bits. */
10534 if ((val
& write_mask
) != write_mask
)
10537 tw32(offset
, save_val
);
10543 if (netif_msg_hw(tp
))
10544 netdev_err(tp
->dev
,
10545 "Register test failed at offset %x\n", offset
);
10546 tw32(offset
, save_val
);
10550 static int tg3_do_mem_test(struct tg3
*tp
, u32 offset
, u32 len
)
10552 static const u32 test_pattern
[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10556 for (i
= 0; i
< ARRAY_SIZE(test_pattern
); i
++) {
10557 for (j
= 0; j
< len
; j
+= 4) {
10560 tg3_write_mem(tp
, offset
+ j
, test_pattern
[i
]);
10561 tg3_read_mem(tp
, offset
+ j
, &val
);
10562 if (val
!= test_pattern
[i
])
10569 static int tg3_test_memory(struct tg3
*tp
)
10571 static struct mem_entry
{
10574 } mem_tbl_570x
[] = {
10575 { 0x00000000, 0x00b50},
10576 { 0x00002000, 0x1c000},
10577 { 0xffffffff, 0x00000}
10578 }, mem_tbl_5705
[] = {
10579 { 0x00000100, 0x0000c},
10580 { 0x00000200, 0x00008},
10581 { 0x00004000, 0x00800},
10582 { 0x00006000, 0x01000},
10583 { 0x00008000, 0x02000},
10584 { 0x00010000, 0x0e000},
10585 { 0xffffffff, 0x00000}
10586 }, mem_tbl_5755
[] = {
10587 { 0x00000200, 0x00008},
10588 { 0x00004000, 0x00800},
10589 { 0x00006000, 0x00800},
10590 { 0x00008000, 0x02000},
10591 { 0x00010000, 0x0c000},
10592 { 0xffffffff, 0x00000}
10593 }, mem_tbl_5906
[] = {
10594 { 0x00000200, 0x00008},
10595 { 0x00004000, 0x00400},
10596 { 0x00006000, 0x00400},
10597 { 0x00008000, 0x01000},
10598 { 0x00010000, 0x01000},
10599 { 0xffffffff, 0x00000}
10600 }, mem_tbl_5717
[] = {
10601 { 0x00000200, 0x00008},
10602 { 0x00010000, 0x0a000},
10603 { 0x00020000, 0x13c00},
10604 { 0xffffffff, 0x00000}
10605 }, mem_tbl_57765
[] = {
10606 { 0x00000200, 0x00008},
10607 { 0x00004000, 0x00800},
10608 { 0x00006000, 0x09800},
10609 { 0x00010000, 0x0a000},
10610 { 0xffffffff, 0x00000}
10612 struct mem_entry
*mem_tbl
;
10616 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
10617 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
)
10618 mem_tbl
= mem_tbl_5717
;
10619 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
10620 mem_tbl
= mem_tbl_57765
;
10621 else if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
10622 mem_tbl
= mem_tbl_5755
;
10623 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
10624 mem_tbl
= mem_tbl_5906
;
10625 else if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
10626 mem_tbl
= mem_tbl_5705
;
10628 mem_tbl
= mem_tbl_570x
;
10630 for (i
= 0; mem_tbl
[i
].offset
!= 0xffffffff; i
++) {
10631 err
= tg3_do_mem_test(tp
, mem_tbl
[i
].offset
, mem_tbl
[i
].len
);
10639 #define TG3_MAC_LOOPBACK 0
10640 #define TG3_PHY_LOOPBACK 1
10642 static int tg3_run_loopback(struct tg3
*tp
, int loopback_mode
)
10644 u32 mac_mode
, rx_start_idx
, rx_idx
, tx_idx
, opaque_key
;
10645 u32 desc_idx
, coal_now
;
10646 struct sk_buff
*skb
, *rx_skb
;
10649 int num_pkts
, tx_len
, rx_len
, i
, err
;
10650 struct tg3_rx_buffer_desc
*desc
;
10651 struct tg3_napi
*tnapi
, *rnapi
;
10652 struct tg3_rx_prodring_set
*tpr
= &tp
->napi
[0].prodring
;
10654 tnapi
= &tp
->napi
[0];
10655 rnapi
= &tp
->napi
[0];
10656 if (tp
->irq_cnt
> 1) {
10657 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_RSS
)
10658 rnapi
= &tp
->napi
[1];
10659 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)
10660 tnapi
= &tp
->napi
[1];
10662 coal_now
= tnapi
->coal_now
| rnapi
->coal_now
;
10664 if (loopback_mode
== TG3_MAC_LOOPBACK
) {
10665 /* HW errata - mac loopback fails in some cases on 5780.
10666 * Normal traffic and PHY loopback are not affected by
10669 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5780
)
10672 mac_mode
= (tp
->mac_mode
& ~MAC_MODE_PORT_MODE_MASK
) |
10673 MAC_MODE_PORT_INT_LPBACK
;
10674 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
10675 mac_mode
|= MAC_MODE_LINK_POLARITY
;
10676 if (tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
)
10677 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
10679 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
10680 tw32(MAC_MODE
, mac_mode
);
10681 } else if (loopback_mode
== TG3_PHY_LOOPBACK
) {
10684 if (tp
->phy_flags
& TG3_PHYFLG_IS_FET
) {
10685 tg3_phy_fet_toggle_apd(tp
, false);
10686 val
= BMCR_LOOPBACK
| BMCR_FULLDPLX
| BMCR_SPEED100
;
10688 val
= BMCR_LOOPBACK
| BMCR_FULLDPLX
| BMCR_SPEED1000
;
10690 tg3_phy_toggle_automdix(tp
, 0);
10692 tg3_writephy(tp
, MII_BMCR
, val
);
10695 mac_mode
= tp
->mac_mode
& ~MAC_MODE_PORT_MODE_MASK
;
10696 if (tp
->phy_flags
& TG3_PHYFLG_IS_FET
) {
10697 tg3_writephy(tp
, MII_TG3_FET_PTEST
,
10698 MII_TG3_FET_PTEST_FRC_TX_LINK
|
10699 MII_TG3_FET_PTEST_FRC_TX_LOCK
);
10700 /* The write needs to be flushed for the AC131 */
10701 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
10702 tg3_readphy(tp
, MII_TG3_FET_PTEST
, &val
);
10703 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
10705 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
10707 /* reset to prevent losing 1st rx packet intermittently */
10708 if (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
) {
10709 tw32_f(MAC_RX_MODE
, RX_MODE_RESET
);
10711 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
10713 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) {
10714 u32 masked_phy_id
= tp
->phy_id
& TG3_PHY_ID_MASK
;
10715 if (masked_phy_id
== TG3_PHY_ID_BCM5401
)
10716 mac_mode
&= ~MAC_MODE_LINK_POLARITY
;
10717 else if (masked_phy_id
== TG3_PHY_ID_BCM5411
)
10718 mac_mode
|= MAC_MODE_LINK_POLARITY
;
10719 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
10720 MII_TG3_EXT_CTRL_LNK3_LED_MODE
);
10722 tw32(MAC_MODE
, mac_mode
);
10730 skb
= netdev_alloc_skb(tp
->dev
, tx_len
);
10734 tx_data
= skb_put(skb
, tx_len
);
10735 memcpy(tx_data
, tp
->dev
->dev_addr
, 6);
10736 memset(tx_data
+ 6, 0x0, 8);
10738 tw32(MAC_RX_MTU_SIZE
, tx_len
+ 4);
10740 for (i
= 14; i
< tx_len
; i
++)
10741 tx_data
[i
] = (u8
) (i
& 0xff);
10743 map
= pci_map_single(tp
->pdev
, skb
->data
, tx_len
, PCI_DMA_TODEVICE
);
10744 if (pci_dma_mapping_error(tp
->pdev
, map
)) {
10745 dev_kfree_skb(skb
);
10749 tw32_f(HOSTCC_MODE
, tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
|
10754 rx_start_idx
= rnapi
->hw_status
->idx
[0].rx_producer
;
10758 tg3_set_txd(tnapi
, tnapi
->tx_prod
, map
, tx_len
, 0, 1);
10763 tw32_tx_mbox(tnapi
->prodmbox
, tnapi
->tx_prod
);
10764 tr32_mailbox(tnapi
->prodmbox
);
10768 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
10769 for (i
= 0; i
< 35; i
++) {
10770 tw32_f(HOSTCC_MODE
, tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
|
10775 tx_idx
= tnapi
->hw_status
->idx
[0].tx_consumer
;
10776 rx_idx
= rnapi
->hw_status
->idx
[0].rx_producer
;
10777 if ((tx_idx
== tnapi
->tx_prod
) &&
10778 (rx_idx
== (rx_start_idx
+ num_pkts
)))
10782 pci_unmap_single(tp
->pdev
, map
, tx_len
, PCI_DMA_TODEVICE
);
10783 dev_kfree_skb(skb
);
10785 if (tx_idx
!= tnapi
->tx_prod
)
10788 if (rx_idx
!= rx_start_idx
+ num_pkts
)
10791 desc
= &rnapi
->rx_rcb
[rx_start_idx
];
10792 desc_idx
= desc
->opaque
& RXD_OPAQUE_INDEX_MASK
;
10793 opaque_key
= desc
->opaque
& RXD_OPAQUE_RING_MASK
;
10794 if (opaque_key
!= RXD_OPAQUE_RING_STD
)
10797 if ((desc
->err_vlan
& RXD_ERR_MASK
) != 0 &&
10798 (desc
->err_vlan
!= RXD_ERR_ODD_NIBBLE_RCVD_MII
))
10801 rx_len
= ((desc
->idx_len
& RXD_LEN_MASK
) >> RXD_LEN_SHIFT
) - 4;
10802 if (rx_len
!= tx_len
)
10805 rx_skb
= tpr
->rx_std_buffers
[desc_idx
].skb
;
10807 map
= dma_unmap_addr(&tpr
->rx_std_buffers
[desc_idx
], mapping
);
10808 pci_dma_sync_single_for_cpu(tp
->pdev
, map
, rx_len
, PCI_DMA_FROMDEVICE
);
10810 for (i
= 14; i
< tx_len
; i
++) {
10811 if (*(rx_skb
->data
+ i
) != (u8
) (i
& 0xff))
10816 /* tg3_free_rings will unmap and free the rx_skb */
10821 #define TG3_MAC_LOOPBACK_FAILED 1
10822 #define TG3_PHY_LOOPBACK_FAILED 2
10823 #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
10824 TG3_PHY_LOOPBACK_FAILED)
10826 static int tg3_test_loopback(struct tg3
*tp
)
10831 if (!netif_running(tp
->dev
))
10832 return TG3_LOOPBACK_FAILED
;
10834 err
= tg3_reset_hw(tp
, 1);
10836 return TG3_LOOPBACK_FAILED
;
10838 /* Turn off gphy autopowerdown. */
10839 if (tp
->phy_flags
& TG3_PHYFLG_ENABLE_APD
)
10840 tg3_phy_toggle_apd(tp
, false);
10842 if (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) {
10846 tw32(TG3_CPMU_MUTEX_REQ
, CPMU_MUTEX_REQ_DRIVER
);
10848 /* Wait for up to 40 microseconds to acquire lock. */
10849 for (i
= 0; i
< 4; i
++) {
10850 status
= tr32(TG3_CPMU_MUTEX_GNT
);
10851 if (status
== CPMU_MUTEX_GNT_DRIVER
)
10856 if (status
!= CPMU_MUTEX_GNT_DRIVER
)
10857 return TG3_LOOPBACK_FAILED
;
10859 /* Turn off link-based power management. */
10860 cpmuctrl
= tr32(TG3_CPMU_CTRL
);
10861 tw32(TG3_CPMU_CTRL
,
10862 cpmuctrl
& ~(CPMU_CTRL_LINK_SPEED_MODE
|
10863 CPMU_CTRL_LINK_AWARE_MODE
));
10866 if (tg3_run_loopback(tp
, TG3_MAC_LOOPBACK
))
10867 err
|= TG3_MAC_LOOPBACK_FAILED
;
10869 if (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) {
10870 tw32(TG3_CPMU_CTRL
, cpmuctrl
);
10872 /* Release the mutex */
10873 tw32(TG3_CPMU_MUTEX_GNT
, CPMU_MUTEX_GNT_DRIVER
);
10876 if (!(tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) &&
10877 !(tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
)) {
10878 if (tg3_run_loopback(tp
, TG3_PHY_LOOPBACK
))
10879 err
|= TG3_PHY_LOOPBACK_FAILED
;
10882 /* Re-enable gphy autopowerdown. */
10883 if (tp
->phy_flags
& TG3_PHYFLG_ENABLE_APD
)
10884 tg3_phy_toggle_apd(tp
, true);
10889 static void tg3_self_test(struct net_device
*dev
, struct ethtool_test
*etest
,
10892 struct tg3
*tp
= netdev_priv(dev
);
10894 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)
10895 tg3_set_power_state(tp
, PCI_D0
);
10897 memset(data
, 0, sizeof(u64
) * TG3_NUM_TEST
);
10899 if (tg3_test_nvram(tp
) != 0) {
10900 etest
->flags
|= ETH_TEST_FL_FAILED
;
10903 if (tg3_test_link(tp
) != 0) {
10904 etest
->flags
|= ETH_TEST_FL_FAILED
;
10907 if (etest
->flags
& ETH_TEST_FL_OFFLINE
) {
10908 int err
, err2
= 0, irq_sync
= 0;
10910 if (netif_running(dev
)) {
10912 tg3_netif_stop(tp
);
10916 tg3_full_lock(tp
, irq_sync
);
10918 tg3_halt(tp
, RESET_KIND_SUSPEND
, 1);
10919 err
= tg3_nvram_lock(tp
);
10920 tg3_halt_cpu(tp
, RX_CPU_BASE
);
10921 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
10922 tg3_halt_cpu(tp
, TX_CPU_BASE
);
10924 tg3_nvram_unlock(tp
);
10926 if (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
)
10929 if (tg3_test_registers(tp
) != 0) {
10930 etest
->flags
|= ETH_TEST_FL_FAILED
;
10933 if (tg3_test_memory(tp
) != 0) {
10934 etest
->flags
|= ETH_TEST_FL_FAILED
;
10937 if ((data
[4] = tg3_test_loopback(tp
)) != 0)
10938 etest
->flags
|= ETH_TEST_FL_FAILED
;
10940 tg3_full_unlock(tp
);
10942 if (tg3_test_interrupt(tp
) != 0) {
10943 etest
->flags
|= ETH_TEST_FL_FAILED
;
10947 tg3_full_lock(tp
, 0);
10949 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
10950 if (netif_running(dev
)) {
10951 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
10952 err2
= tg3_restart_hw(tp
, 1);
10954 tg3_netif_start(tp
);
10957 tg3_full_unlock(tp
);
10959 if (irq_sync
&& !err2
)
10962 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)
10963 tg3_set_power_state(tp
, PCI_D3hot
);
10967 static int tg3_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
10969 struct mii_ioctl_data
*data
= if_mii(ifr
);
10970 struct tg3
*tp
= netdev_priv(dev
);
10973 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
10974 struct phy_device
*phydev
;
10975 if (!(tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
))
10977 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
10978 return phy_mii_ioctl(phydev
, ifr
, cmd
);
10983 data
->phy_id
= tp
->phy_addr
;
10986 case SIOCGMIIREG
: {
10989 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
)
10990 break; /* We have no PHY */
10992 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)
10995 spin_lock_bh(&tp
->lock
);
10996 err
= tg3_readphy(tp
, data
->reg_num
& 0x1f, &mii_regval
);
10997 spin_unlock_bh(&tp
->lock
);
10999 data
->val_out
= mii_regval
;
11005 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
)
11006 break; /* We have no PHY */
11008 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)
11011 spin_lock_bh(&tp
->lock
);
11012 err
= tg3_writephy(tp
, data
->reg_num
& 0x1f, data
->val_in
);
11013 spin_unlock_bh(&tp
->lock
);
11021 return -EOPNOTSUPP
;
11024 #if TG3_VLAN_TAG_USED
11025 static void tg3_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*grp
)
11027 struct tg3
*tp
= netdev_priv(dev
);
11029 if (!netif_running(dev
)) {
11034 tg3_netif_stop(tp
);
11036 tg3_full_lock(tp
, 0);
11040 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
11041 __tg3_set_rx_mode(dev
);
11043 tg3_netif_start(tp
);
11045 tg3_full_unlock(tp
);
11049 static int tg3_get_coalesce(struct net_device
*dev
, struct ethtool_coalesce
*ec
)
11051 struct tg3
*tp
= netdev_priv(dev
);
11053 memcpy(ec
, &tp
->coal
, sizeof(*ec
));
11057 static int tg3_set_coalesce(struct net_device
*dev
, struct ethtool_coalesce
*ec
)
11059 struct tg3
*tp
= netdev_priv(dev
);
11060 u32 max_rxcoal_tick_int
= 0, max_txcoal_tick_int
= 0;
11061 u32 max_stat_coal_ticks
= 0, min_stat_coal_ticks
= 0;
11063 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
11064 max_rxcoal_tick_int
= MAX_RXCOAL_TICK_INT
;
11065 max_txcoal_tick_int
= MAX_TXCOAL_TICK_INT
;
11066 max_stat_coal_ticks
= MAX_STAT_COAL_TICKS
;
11067 min_stat_coal_ticks
= MIN_STAT_COAL_TICKS
;
11070 if ((ec
->rx_coalesce_usecs
> MAX_RXCOL_TICKS
) ||
11071 (ec
->tx_coalesce_usecs
> MAX_TXCOL_TICKS
) ||
11072 (ec
->rx_max_coalesced_frames
> MAX_RXMAX_FRAMES
) ||
11073 (ec
->tx_max_coalesced_frames
> MAX_TXMAX_FRAMES
) ||
11074 (ec
->rx_coalesce_usecs_irq
> max_rxcoal_tick_int
) ||
11075 (ec
->tx_coalesce_usecs_irq
> max_txcoal_tick_int
) ||
11076 (ec
->rx_max_coalesced_frames_irq
> MAX_RXCOAL_MAXF_INT
) ||
11077 (ec
->tx_max_coalesced_frames_irq
> MAX_TXCOAL_MAXF_INT
) ||
11078 (ec
->stats_block_coalesce_usecs
> max_stat_coal_ticks
) ||
11079 (ec
->stats_block_coalesce_usecs
< min_stat_coal_ticks
))
11082 /* No rx interrupts will be generated if both are zero */
11083 if ((ec
->rx_coalesce_usecs
== 0) &&
11084 (ec
->rx_max_coalesced_frames
== 0))
11087 /* No tx interrupts will be generated if both are zero */
11088 if ((ec
->tx_coalesce_usecs
== 0) &&
11089 (ec
->tx_max_coalesced_frames
== 0))
11092 /* Only copy relevant parameters, ignore all others. */
11093 tp
->coal
.rx_coalesce_usecs
= ec
->rx_coalesce_usecs
;
11094 tp
->coal
.tx_coalesce_usecs
= ec
->tx_coalesce_usecs
;
11095 tp
->coal
.rx_max_coalesced_frames
= ec
->rx_max_coalesced_frames
;
11096 tp
->coal
.tx_max_coalesced_frames
= ec
->tx_max_coalesced_frames
;
11097 tp
->coal
.rx_coalesce_usecs_irq
= ec
->rx_coalesce_usecs_irq
;
11098 tp
->coal
.tx_coalesce_usecs_irq
= ec
->tx_coalesce_usecs_irq
;
11099 tp
->coal
.rx_max_coalesced_frames_irq
= ec
->rx_max_coalesced_frames_irq
;
11100 tp
->coal
.tx_max_coalesced_frames_irq
= ec
->tx_max_coalesced_frames_irq
;
11101 tp
->coal
.stats_block_coalesce_usecs
= ec
->stats_block_coalesce_usecs
;
11103 if (netif_running(dev
)) {
11104 tg3_full_lock(tp
, 0);
11105 __tg3_set_coalesce(tp
, &tp
->coal
);
11106 tg3_full_unlock(tp
);
11111 static const struct ethtool_ops tg3_ethtool_ops
= {
11112 .get_settings
= tg3_get_settings
,
11113 .set_settings
= tg3_set_settings
,
11114 .get_drvinfo
= tg3_get_drvinfo
,
11115 .get_regs_len
= tg3_get_regs_len
,
11116 .get_regs
= tg3_get_regs
,
11117 .get_wol
= tg3_get_wol
,
11118 .set_wol
= tg3_set_wol
,
11119 .get_msglevel
= tg3_get_msglevel
,
11120 .set_msglevel
= tg3_set_msglevel
,
11121 .nway_reset
= tg3_nway_reset
,
11122 .get_link
= ethtool_op_get_link
,
11123 .get_eeprom_len
= tg3_get_eeprom_len
,
11124 .get_eeprom
= tg3_get_eeprom
,
11125 .set_eeprom
= tg3_set_eeprom
,
11126 .get_ringparam
= tg3_get_ringparam
,
11127 .set_ringparam
= tg3_set_ringparam
,
11128 .get_pauseparam
= tg3_get_pauseparam
,
11129 .set_pauseparam
= tg3_set_pauseparam
,
11130 .get_rx_csum
= tg3_get_rx_csum
,
11131 .set_rx_csum
= tg3_set_rx_csum
,
11132 .set_tx_csum
= tg3_set_tx_csum
,
11133 .set_sg
= ethtool_op_set_sg
,
11134 .set_tso
= tg3_set_tso
,
11135 .self_test
= tg3_self_test
,
11136 .get_strings
= tg3_get_strings
,
11137 .phys_id
= tg3_phys_id
,
11138 .get_ethtool_stats
= tg3_get_ethtool_stats
,
11139 .get_coalesce
= tg3_get_coalesce
,
11140 .set_coalesce
= tg3_set_coalesce
,
11141 .get_sset_count
= tg3_get_sset_count
,
11144 static void __devinit
tg3_get_eeprom_size(struct tg3
*tp
)
11146 u32 cursize
, val
, magic
;
11148 tp
->nvram_size
= EEPROM_CHIP_SIZE
;
11150 if (tg3_nvram_read(tp
, 0, &magic
) != 0)
11153 if ((magic
!= TG3_EEPROM_MAGIC
) &&
11154 ((magic
& TG3_EEPROM_MAGIC_FW_MSK
) != TG3_EEPROM_MAGIC_FW
) &&
11155 ((magic
& TG3_EEPROM_MAGIC_HW_MSK
) != TG3_EEPROM_MAGIC_HW
))
11159 * Size the chip by reading offsets at increasing powers of two.
11160 * When we encounter our validation signature, we know the addressing
11161 * has wrapped around, and thus have our chip size.
11165 while (cursize
< tp
->nvram_size
) {
11166 if (tg3_nvram_read(tp
, cursize
, &val
) != 0)
11175 tp
->nvram_size
= cursize
;
11178 static void __devinit
tg3_get_nvram_size(struct tg3
*tp
)
11182 if ((tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) ||
11183 tg3_nvram_read(tp
, 0, &val
) != 0)
11186 /* Selfboot format */
11187 if (val
!= TG3_EEPROM_MAGIC
) {
11188 tg3_get_eeprom_size(tp
);
11192 if (tg3_nvram_read(tp
, 0xf0, &val
) == 0) {
11194 /* This is confusing. We want to operate on the
11195 * 16-bit value at offset 0xf2. The tg3_nvram_read()
11196 * call will read from NVRAM and byteswap the data
11197 * according to the byteswapping settings for all
11198 * other register accesses. This ensures the data we
11199 * want will always reside in the lower 16-bits.
11200 * However, the data in NVRAM is in LE format, which
11201 * means the data from the NVRAM read will always be
11202 * opposite the endianness of the CPU. The 16-bit
11203 * byteswap then brings the data to CPU endianness.
11205 tp
->nvram_size
= swab16((u16
)(val
& 0x0000ffff)) * 1024;
11209 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
11212 static void __devinit
tg3_get_nvram_info(struct tg3
*tp
)
11216 nvcfg1
= tr32(NVRAM_CFG1
);
11217 if (nvcfg1
& NVRAM_CFG1_FLASHIF_ENAB
) {
11218 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11220 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
11221 tw32(NVRAM_CFG1
, nvcfg1
);
11224 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
) ||
11225 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
11226 switch (nvcfg1
& NVRAM_CFG1_VENDOR_MASK
) {
11227 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED
:
11228 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11229 tp
->nvram_pagesize
= ATMEL_AT45DB0X1B_PAGE_SIZE
;
11230 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11232 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED
:
11233 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11234 tp
->nvram_pagesize
= ATMEL_AT25F512_PAGE_SIZE
;
11236 case FLASH_VENDOR_ATMEL_EEPROM
:
11237 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11238 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
11239 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11241 case FLASH_VENDOR_ST
:
11242 tp
->nvram_jedecnum
= JEDEC_ST
;
11243 tp
->nvram_pagesize
= ST_M45PEX0_PAGE_SIZE
;
11244 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11246 case FLASH_VENDOR_SAIFUN
:
11247 tp
->nvram_jedecnum
= JEDEC_SAIFUN
;
11248 tp
->nvram_pagesize
= SAIFUN_SA25F0XX_PAGE_SIZE
;
11250 case FLASH_VENDOR_SST_SMALL
:
11251 case FLASH_VENDOR_SST_LARGE
:
11252 tp
->nvram_jedecnum
= JEDEC_SST
;
11253 tp
->nvram_pagesize
= SST_25VF0X0_PAGE_SIZE
;
11257 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11258 tp
->nvram_pagesize
= ATMEL_AT45DB0X1B_PAGE_SIZE
;
11259 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11263 static void __devinit
tg3_nvram_get_pagesize(struct tg3
*tp
, u32 nvmcfg1
)
11265 switch (nvmcfg1
& NVRAM_CFG1_5752PAGE_SIZE_MASK
) {
11266 case FLASH_5752PAGE_SIZE_256
:
11267 tp
->nvram_pagesize
= 256;
11269 case FLASH_5752PAGE_SIZE_512
:
11270 tp
->nvram_pagesize
= 512;
11272 case FLASH_5752PAGE_SIZE_1K
:
11273 tp
->nvram_pagesize
= 1024;
11275 case FLASH_5752PAGE_SIZE_2K
:
11276 tp
->nvram_pagesize
= 2048;
11278 case FLASH_5752PAGE_SIZE_4K
:
11279 tp
->nvram_pagesize
= 4096;
11281 case FLASH_5752PAGE_SIZE_264
:
11282 tp
->nvram_pagesize
= 264;
11284 case FLASH_5752PAGE_SIZE_528
:
11285 tp
->nvram_pagesize
= 528;
11290 static void __devinit
tg3_get_5752_nvram_info(struct tg3
*tp
)
11294 nvcfg1
= tr32(NVRAM_CFG1
);
11296 /* NVRAM protection for TPM */
11297 if (nvcfg1
& (1 << 27))
11298 tp
->tg3_flags3
|= TG3_FLG3_PROTECTED_NVRAM
;
11300 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11301 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ
:
11302 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ
:
11303 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11304 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11306 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
11307 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11308 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11309 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11311 case FLASH_5752VENDOR_ST_M45PE10
:
11312 case FLASH_5752VENDOR_ST_M45PE20
:
11313 case FLASH_5752VENDOR_ST_M45PE40
:
11314 tp
->nvram_jedecnum
= JEDEC_ST
;
11315 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11316 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11320 if (tp
->tg3_flags2
& TG3_FLG2_FLASH
) {
11321 tg3_nvram_get_pagesize(tp
, nvcfg1
);
11323 /* For eeprom, set pagesize to maximum eeprom size */
11324 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
11326 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
11327 tw32(NVRAM_CFG1
, nvcfg1
);
11331 static void __devinit
tg3_get_5755_nvram_info(struct tg3
*tp
)
11333 u32 nvcfg1
, protect
= 0;
11335 nvcfg1
= tr32(NVRAM_CFG1
);
11337 /* NVRAM protection for TPM */
11338 if (nvcfg1
& (1 << 27)) {
11339 tp
->tg3_flags3
|= TG3_FLG3_PROTECTED_NVRAM
;
11343 nvcfg1
&= NVRAM_CFG1_5752VENDOR_MASK
;
11345 case FLASH_5755VENDOR_ATMEL_FLASH_1
:
11346 case FLASH_5755VENDOR_ATMEL_FLASH_2
:
11347 case FLASH_5755VENDOR_ATMEL_FLASH_3
:
11348 case FLASH_5755VENDOR_ATMEL_FLASH_5
:
11349 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11350 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11351 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11352 tp
->nvram_pagesize
= 264;
11353 if (nvcfg1
== FLASH_5755VENDOR_ATMEL_FLASH_1
||
11354 nvcfg1
== FLASH_5755VENDOR_ATMEL_FLASH_5
)
11355 tp
->nvram_size
= (protect
? 0x3e200 :
11356 TG3_NVRAM_SIZE_512KB
);
11357 else if (nvcfg1
== FLASH_5755VENDOR_ATMEL_FLASH_2
)
11358 tp
->nvram_size
= (protect
? 0x1f200 :
11359 TG3_NVRAM_SIZE_256KB
);
11361 tp
->nvram_size
= (protect
? 0x1f200 :
11362 TG3_NVRAM_SIZE_128KB
);
11364 case FLASH_5752VENDOR_ST_M45PE10
:
11365 case FLASH_5752VENDOR_ST_M45PE20
:
11366 case FLASH_5752VENDOR_ST_M45PE40
:
11367 tp
->nvram_jedecnum
= JEDEC_ST
;
11368 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11369 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11370 tp
->nvram_pagesize
= 256;
11371 if (nvcfg1
== FLASH_5752VENDOR_ST_M45PE10
)
11372 tp
->nvram_size
= (protect
?
11373 TG3_NVRAM_SIZE_64KB
:
11374 TG3_NVRAM_SIZE_128KB
);
11375 else if (nvcfg1
== FLASH_5752VENDOR_ST_M45PE20
)
11376 tp
->nvram_size
= (protect
?
11377 TG3_NVRAM_SIZE_64KB
:
11378 TG3_NVRAM_SIZE_256KB
);
11380 tp
->nvram_size
= (protect
?
11381 TG3_NVRAM_SIZE_128KB
:
11382 TG3_NVRAM_SIZE_512KB
);
11387 static void __devinit
tg3_get_5787_nvram_info(struct tg3
*tp
)
11391 nvcfg1
= tr32(NVRAM_CFG1
);
11393 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11394 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ
:
11395 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ
:
11396 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ
:
11397 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ
:
11398 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11399 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11400 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
11402 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
11403 tw32(NVRAM_CFG1
, nvcfg1
);
11405 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
11406 case FLASH_5755VENDOR_ATMEL_FLASH_1
:
11407 case FLASH_5755VENDOR_ATMEL_FLASH_2
:
11408 case FLASH_5755VENDOR_ATMEL_FLASH_3
:
11409 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11410 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11411 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11412 tp
->nvram_pagesize
= 264;
11414 case FLASH_5752VENDOR_ST_M45PE10
:
11415 case FLASH_5752VENDOR_ST_M45PE20
:
11416 case FLASH_5752VENDOR_ST_M45PE40
:
11417 tp
->nvram_jedecnum
= JEDEC_ST
;
11418 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11419 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11420 tp
->nvram_pagesize
= 256;
11425 static void __devinit
tg3_get_5761_nvram_info(struct tg3
*tp
)
11427 u32 nvcfg1
, protect
= 0;
11429 nvcfg1
= tr32(NVRAM_CFG1
);
11431 /* NVRAM protection for TPM */
11432 if (nvcfg1
& (1 << 27)) {
11433 tp
->tg3_flags3
|= TG3_FLG3_PROTECTED_NVRAM
;
11437 nvcfg1
&= NVRAM_CFG1_5752VENDOR_MASK
;
11439 case FLASH_5761VENDOR_ATMEL_ADB021D
:
11440 case FLASH_5761VENDOR_ATMEL_ADB041D
:
11441 case FLASH_5761VENDOR_ATMEL_ADB081D
:
11442 case FLASH_5761VENDOR_ATMEL_ADB161D
:
11443 case FLASH_5761VENDOR_ATMEL_MDB021D
:
11444 case FLASH_5761VENDOR_ATMEL_MDB041D
:
11445 case FLASH_5761VENDOR_ATMEL_MDB081D
:
11446 case FLASH_5761VENDOR_ATMEL_MDB161D
:
11447 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11448 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11449 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11450 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
11451 tp
->nvram_pagesize
= 256;
11453 case FLASH_5761VENDOR_ST_A_M45PE20
:
11454 case FLASH_5761VENDOR_ST_A_M45PE40
:
11455 case FLASH_5761VENDOR_ST_A_M45PE80
:
11456 case FLASH_5761VENDOR_ST_A_M45PE16
:
11457 case FLASH_5761VENDOR_ST_M_M45PE20
:
11458 case FLASH_5761VENDOR_ST_M_M45PE40
:
11459 case FLASH_5761VENDOR_ST_M_M45PE80
:
11460 case FLASH_5761VENDOR_ST_M_M45PE16
:
11461 tp
->nvram_jedecnum
= JEDEC_ST
;
11462 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11463 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11464 tp
->nvram_pagesize
= 256;
11469 tp
->nvram_size
= tr32(NVRAM_ADDR_LOCKOUT
);
11472 case FLASH_5761VENDOR_ATMEL_ADB161D
:
11473 case FLASH_5761VENDOR_ATMEL_MDB161D
:
11474 case FLASH_5761VENDOR_ST_A_M45PE16
:
11475 case FLASH_5761VENDOR_ST_M_M45PE16
:
11476 tp
->nvram_size
= TG3_NVRAM_SIZE_2MB
;
11478 case FLASH_5761VENDOR_ATMEL_ADB081D
:
11479 case FLASH_5761VENDOR_ATMEL_MDB081D
:
11480 case FLASH_5761VENDOR_ST_A_M45PE80
:
11481 case FLASH_5761VENDOR_ST_M_M45PE80
:
11482 tp
->nvram_size
= TG3_NVRAM_SIZE_1MB
;
11484 case FLASH_5761VENDOR_ATMEL_ADB041D
:
11485 case FLASH_5761VENDOR_ATMEL_MDB041D
:
11486 case FLASH_5761VENDOR_ST_A_M45PE40
:
11487 case FLASH_5761VENDOR_ST_M_M45PE40
:
11488 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
11490 case FLASH_5761VENDOR_ATMEL_ADB021D
:
11491 case FLASH_5761VENDOR_ATMEL_MDB021D
:
11492 case FLASH_5761VENDOR_ST_A_M45PE20
:
11493 case FLASH_5761VENDOR_ST_M_M45PE20
:
11494 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
11500 static void __devinit
tg3_get_5906_nvram_info(struct tg3
*tp
)
11502 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11503 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11504 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
11507 static void __devinit
tg3_get_57780_nvram_info(struct tg3
*tp
)
11511 nvcfg1
= tr32(NVRAM_CFG1
);
11513 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11514 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ
:
11515 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ
:
11516 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11517 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11518 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
11520 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
11521 tw32(NVRAM_CFG1
, nvcfg1
);
11523 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
11524 case FLASH_57780VENDOR_ATMEL_AT45DB011D
:
11525 case FLASH_57780VENDOR_ATMEL_AT45DB011B
:
11526 case FLASH_57780VENDOR_ATMEL_AT45DB021D
:
11527 case FLASH_57780VENDOR_ATMEL_AT45DB021B
:
11528 case FLASH_57780VENDOR_ATMEL_AT45DB041D
:
11529 case FLASH_57780VENDOR_ATMEL_AT45DB041B
:
11530 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11531 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11532 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11534 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11535 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
11536 case FLASH_57780VENDOR_ATMEL_AT45DB011D
:
11537 case FLASH_57780VENDOR_ATMEL_AT45DB011B
:
11538 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
11540 case FLASH_57780VENDOR_ATMEL_AT45DB021D
:
11541 case FLASH_57780VENDOR_ATMEL_AT45DB021B
:
11542 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
11544 case FLASH_57780VENDOR_ATMEL_AT45DB041D
:
11545 case FLASH_57780VENDOR_ATMEL_AT45DB041B
:
11546 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
11550 case FLASH_5752VENDOR_ST_M45PE10
:
11551 case FLASH_5752VENDOR_ST_M45PE20
:
11552 case FLASH_5752VENDOR_ST_M45PE40
:
11553 tp
->nvram_jedecnum
= JEDEC_ST
;
11554 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11555 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11557 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11558 case FLASH_5752VENDOR_ST_M45PE10
:
11559 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
11561 case FLASH_5752VENDOR_ST_M45PE20
:
11562 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
11564 case FLASH_5752VENDOR_ST_M45PE40
:
11565 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
11570 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM
;
11574 tg3_nvram_get_pagesize(tp
, nvcfg1
);
11575 if (tp
->nvram_pagesize
!= 264 && tp
->nvram_pagesize
!= 528)
11576 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
11580 static void __devinit
tg3_get_5717_nvram_info(struct tg3
*tp
)
11584 nvcfg1
= tr32(NVRAM_CFG1
);
11586 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11587 case FLASH_5717VENDOR_ATMEL_EEPROM
:
11588 case FLASH_5717VENDOR_MICRO_EEPROM
:
11589 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11590 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11591 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
11593 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
11594 tw32(NVRAM_CFG1
, nvcfg1
);
11596 case FLASH_5717VENDOR_ATMEL_MDB011D
:
11597 case FLASH_5717VENDOR_ATMEL_ADB011B
:
11598 case FLASH_5717VENDOR_ATMEL_ADB011D
:
11599 case FLASH_5717VENDOR_ATMEL_MDB021D
:
11600 case FLASH_5717VENDOR_ATMEL_ADB021B
:
11601 case FLASH_5717VENDOR_ATMEL_ADB021D
:
11602 case FLASH_5717VENDOR_ATMEL_45USPT
:
11603 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11604 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11605 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11607 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11608 case FLASH_5717VENDOR_ATMEL_MDB021D
:
11609 case FLASH_5717VENDOR_ATMEL_ADB021B
:
11610 case FLASH_5717VENDOR_ATMEL_ADB021D
:
11611 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
11614 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
11618 case FLASH_5717VENDOR_ST_M_M25PE10
:
11619 case FLASH_5717VENDOR_ST_A_M25PE10
:
11620 case FLASH_5717VENDOR_ST_M_M45PE10
:
11621 case FLASH_5717VENDOR_ST_A_M45PE10
:
11622 case FLASH_5717VENDOR_ST_M_M25PE20
:
11623 case FLASH_5717VENDOR_ST_A_M25PE20
:
11624 case FLASH_5717VENDOR_ST_M_M45PE20
:
11625 case FLASH_5717VENDOR_ST_A_M45PE20
:
11626 case FLASH_5717VENDOR_ST_25USPT
:
11627 case FLASH_5717VENDOR_ST_45USPT
:
11628 tp
->nvram_jedecnum
= JEDEC_ST
;
11629 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11630 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11632 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11633 case FLASH_5717VENDOR_ST_M_M25PE20
:
11634 case FLASH_5717VENDOR_ST_A_M25PE20
:
11635 case FLASH_5717VENDOR_ST_M_M45PE20
:
11636 case FLASH_5717VENDOR_ST_A_M45PE20
:
11637 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
11640 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
11645 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM
;
11649 tg3_nvram_get_pagesize(tp
, nvcfg1
);
11650 if (tp
->nvram_pagesize
!= 264 && tp
->nvram_pagesize
!= 528)
11651 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
11654 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11655 static void __devinit
tg3_nvram_init(struct tg3
*tp
)
11657 tw32_f(GRC_EEPROM_ADDR
,
11658 (EEPROM_ADDR_FSM_RESET
|
11659 (EEPROM_DEFAULT_CLOCK_PERIOD
<<
11660 EEPROM_ADDR_CLKPERD_SHIFT
)));
11664 /* Enable seeprom accesses. */
11665 tw32_f(GRC_LOCAL_CTRL
,
11666 tr32(GRC_LOCAL_CTRL
) | GRC_LCLCTRL_AUTO_SEEPROM
);
11669 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
11670 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
) {
11671 tp
->tg3_flags
|= TG3_FLAG_NVRAM
;
11673 if (tg3_nvram_lock(tp
)) {
11674 netdev_warn(tp
->dev
,
11675 "Cannot get nvram lock, %s failed\n",
11679 tg3_enable_nvram_access(tp
);
11681 tp
->nvram_size
= 0;
11683 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
)
11684 tg3_get_5752_nvram_info(tp
);
11685 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
)
11686 tg3_get_5755_nvram_info(tp
);
11687 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5787
||
11688 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
11689 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
11690 tg3_get_5787_nvram_info(tp
);
11691 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
)
11692 tg3_get_5761_nvram_info(tp
);
11693 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
11694 tg3_get_5906_nvram_info(tp
);
11695 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
||
11696 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
11697 tg3_get_57780_nvram_info(tp
);
11698 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
11699 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
)
11700 tg3_get_5717_nvram_info(tp
);
11702 tg3_get_nvram_info(tp
);
11704 if (tp
->nvram_size
== 0)
11705 tg3_get_nvram_size(tp
);
11707 tg3_disable_nvram_access(tp
);
11708 tg3_nvram_unlock(tp
);
11711 tp
->tg3_flags
&= ~(TG3_FLAG_NVRAM
| TG3_FLAG_NVRAM_BUFFERED
);
11713 tg3_get_eeprom_size(tp
);
11717 static int tg3_nvram_write_block_using_eeprom(struct tg3
*tp
,
11718 u32 offset
, u32 len
, u8
*buf
)
11723 for (i
= 0; i
< len
; i
+= 4) {
11729 memcpy(&data
, buf
+ i
, 4);
11732 * The SEEPROM interface expects the data to always be opposite
11733 * the native endian format. We accomplish this by reversing
11734 * all the operations that would have been performed on the
11735 * data from a call to tg3_nvram_read_be32().
11737 tw32(GRC_EEPROM_DATA
, swab32(be32_to_cpu(data
)));
11739 val
= tr32(GRC_EEPROM_ADDR
);
11740 tw32(GRC_EEPROM_ADDR
, val
| EEPROM_ADDR_COMPLETE
);
11742 val
&= ~(EEPROM_ADDR_ADDR_MASK
| EEPROM_ADDR_DEVID_MASK
|
11744 tw32(GRC_EEPROM_ADDR
, val
|
11745 (0 << EEPROM_ADDR_DEVID_SHIFT
) |
11746 (addr
& EEPROM_ADDR_ADDR_MASK
) |
11747 EEPROM_ADDR_START
|
11748 EEPROM_ADDR_WRITE
);
11750 for (j
= 0; j
< 1000; j
++) {
11751 val
= tr32(GRC_EEPROM_ADDR
);
11753 if (val
& EEPROM_ADDR_COMPLETE
)
11757 if (!(val
& EEPROM_ADDR_COMPLETE
)) {
11766 /* offset and length are dword aligned */
11767 static int tg3_nvram_write_block_unbuffered(struct tg3
*tp
, u32 offset
, u32 len
,
11771 u32 pagesize
= tp
->nvram_pagesize
;
11772 u32 pagemask
= pagesize
- 1;
11776 tmp
= kmalloc(pagesize
, GFP_KERNEL
);
11782 u32 phy_addr
, page_off
, size
;
11784 phy_addr
= offset
& ~pagemask
;
11786 for (j
= 0; j
< pagesize
; j
+= 4) {
11787 ret
= tg3_nvram_read_be32(tp
, phy_addr
+ j
,
11788 (__be32
*) (tmp
+ j
));
11795 page_off
= offset
& pagemask
;
11802 memcpy(tmp
+ page_off
, buf
, size
);
11804 offset
= offset
+ (pagesize
- page_off
);
11806 tg3_enable_nvram_access(tp
);
11809 * Before we can erase the flash page, we need
11810 * to issue a special "write enable" command.
11812 nvram_cmd
= NVRAM_CMD_WREN
| NVRAM_CMD_GO
| NVRAM_CMD_DONE
;
11814 if (tg3_nvram_exec_cmd(tp
, nvram_cmd
))
11817 /* Erase the target page */
11818 tw32(NVRAM_ADDR
, phy_addr
);
11820 nvram_cmd
= NVRAM_CMD_GO
| NVRAM_CMD_DONE
| NVRAM_CMD_WR
|
11821 NVRAM_CMD_FIRST
| NVRAM_CMD_LAST
| NVRAM_CMD_ERASE
;
11823 if (tg3_nvram_exec_cmd(tp
, nvram_cmd
))
11826 /* Issue another write enable to start the write. */
11827 nvram_cmd
= NVRAM_CMD_WREN
| NVRAM_CMD_GO
| NVRAM_CMD_DONE
;
11829 if (tg3_nvram_exec_cmd(tp
, nvram_cmd
))
11832 for (j
= 0; j
< pagesize
; j
+= 4) {
11835 data
= *((__be32
*) (tmp
+ j
));
11837 tw32(NVRAM_WRDATA
, be32_to_cpu(data
));
11839 tw32(NVRAM_ADDR
, phy_addr
+ j
);
11841 nvram_cmd
= NVRAM_CMD_GO
| NVRAM_CMD_DONE
|
11845 nvram_cmd
|= NVRAM_CMD_FIRST
;
11846 else if (j
== (pagesize
- 4))
11847 nvram_cmd
|= NVRAM_CMD_LAST
;
11849 if ((ret
= tg3_nvram_exec_cmd(tp
, nvram_cmd
)))
11856 nvram_cmd
= NVRAM_CMD_WRDI
| NVRAM_CMD_GO
| NVRAM_CMD_DONE
;
11857 tg3_nvram_exec_cmd(tp
, nvram_cmd
);
11864 /* offset and length are dword aligned */
11865 static int tg3_nvram_write_block_buffered(struct tg3
*tp
, u32 offset
, u32 len
,
11870 for (i
= 0; i
< len
; i
+= 4, offset
+= 4) {
11871 u32 page_off
, phy_addr
, nvram_cmd
;
11874 memcpy(&data
, buf
+ i
, 4);
11875 tw32(NVRAM_WRDATA
, be32_to_cpu(data
));
11877 page_off
= offset
% tp
->nvram_pagesize
;
11879 phy_addr
= tg3_nvram_phys_addr(tp
, offset
);
11881 tw32(NVRAM_ADDR
, phy_addr
);
11883 nvram_cmd
= NVRAM_CMD_GO
| NVRAM_CMD_DONE
| NVRAM_CMD_WR
;
11885 if (page_off
== 0 || i
== 0)
11886 nvram_cmd
|= NVRAM_CMD_FIRST
;
11887 if (page_off
== (tp
->nvram_pagesize
- 4))
11888 nvram_cmd
|= NVRAM_CMD_LAST
;
11890 if (i
== (len
- 4))
11891 nvram_cmd
|= NVRAM_CMD_LAST
;
11893 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5752
&&
11894 !(tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) &&
11895 (tp
->nvram_jedecnum
== JEDEC_ST
) &&
11896 (nvram_cmd
& NVRAM_CMD_FIRST
)) {
11898 if ((ret
= tg3_nvram_exec_cmd(tp
,
11899 NVRAM_CMD_WREN
| NVRAM_CMD_GO
|
11904 if (!(tp
->tg3_flags2
& TG3_FLG2_FLASH
)) {
11905 /* We always do complete word writes to eeprom. */
11906 nvram_cmd
|= (NVRAM_CMD_FIRST
| NVRAM_CMD_LAST
);
11909 if ((ret
= tg3_nvram_exec_cmd(tp
, nvram_cmd
)))
11915 /* offset and length are dword aligned */
11916 static int tg3_nvram_write_block(struct tg3
*tp
, u32 offset
, u32 len
, u8
*buf
)
11920 if (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
) {
11921 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
&
11922 ~GRC_LCLCTRL_GPIO_OUTPUT1
);
11926 if (!(tp
->tg3_flags
& TG3_FLAG_NVRAM
)) {
11927 ret
= tg3_nvram_write_block_using_eeprom(tp
, offset
, len
, buf
);
11931 ret
= tg3_nvram_lock(tp
);
11935 tg3_enable_nvram_access(tp
);
11936 if ((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
11937 !(tp
->tg3_flags3
& TG3_FLG3_PROTECTED_NVRAM
))
11938 tw32(NVRAM_WRITE1
, 0x406);
11940 grc_mode
= tr32(GRC_MODE
);
11941 tw32(GRC_MODE
, grc_mode
| GRC_MODE_NVRAM_WR_ENABLE
);
11943 if ((tp
->tg3_flags
& TG3_FLAG_NVRAM_BUFFERED
) ||
11944 !(tp
->tg3_flags2
& TG3_FLG2_FLASH
)) {
11946 ret
= tg3_nvram_write_block_buffered(tp
, offset
, len
,
11949 ret
= tg3_nvram_write_block_unbuffered(tp
, offset
, len
,
11953 grc_mode
= tr32(GRC_MODE
);
11954 tw32(GRC_MODE
, grc_mode
& ~GRC_MODE_NVRAM_WR_ENABLE
);
11956 tg3_disable_nvram_access(tp
);
11957 tg3_nvram_unlock(tp
);
11960 if (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
) {
11961 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
);
11968 struct subsys_tbl_ent
{
11969 u16 subsys_vendor
, subsys_devid
;
11973 static struct subsys_tbl_ent subsys_id_to_phy_id
[] __devinitdata
= {
11974 /* Broadcom boards. */
11975 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11976 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6
, TG3_PHY_ID_BCM5401
},
11977 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11978 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5
, TG3_PHY_ID_BCM5701
},
11979 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11980 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6
, TG3_PHY_ID_BCM8002
},
11981 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11982 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9
, 0 },
11983 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11984 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1
, TG3_PHY_ID_BCM5701
},
11985 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11986 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8
, TG3_PHY_ID_BCM5701
},
11987 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11988 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7
, 0 },
11989 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11990 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10
, TG3_PHY_ID_BCM5701
},
11991 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11992 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12
, TG3_PHY_ID_BCM5701
},
11993 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11994 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1
, TG3_PHY_ID_BCM5703
},
11995 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11996 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2
, TG3_PHY_ID_BCM5703
},
11999 { TG3PCI_SUBVENDOR_ID_3COM
,
12000 TG3PCI_SUBDEVICE_ID_3COM_3C996T
, TG3_PHY_ID_BCM5401
},
12001 { TG3PCI_SUBVENDOR_ID_3COM
,
12002 TG3PCI_SUBDEVICE_ID_3COM_3C996BT
, TG3_PHY_ID_BCM5701
},
12003 { TG3PCI_SUBVENDOR_ID_3COM
,
12004 TG3PCI_SUBDEVICE_ID_3COM_3C996SX
, 0 },
12005 { TG3PCI_SUBVENDOR_ID_3COM
,
12006 TG3PCI_SUBDEVICE_ID_3COM_3C1000T
, TG3_PHY_ID_BCM5701
},
12007 { TG3PCI_SUBVENDOR_ID_3COM
,
12008 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01
, TG3_PHY_ID_BCM5701
},
12011 { TG3PCI_SUBVENDOR_ID_DELL
,
12012 TG3PCI_SUBDEVICE_ID_DELL_VIPER
, TG3_PHY_ID_BCM5401
},
12013 { TG3PCI_SUBVENDOR_ID_DELL
,
12014 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR
, TG3_PHY_ID_BCM5401
},
12015 { TG3PCI_SUBVENDOR_ID_DELL
,
12016 TG3PCI_SUBDEVICE_ID_DELL_MERLOT
, TG3_PHY_ID_BCM5411
},
12017 { TG3PCI_SUBVENDOR_ID_DELL
,
12018 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT
, TG3_PHY_ID_BCM5411
},
12020 /* Compaq boards. */
12021 { TG3PCI_SUBVENDOR_ID_COMPAQ
,
12022 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE
, TG3_PHY_ID_BCM5701
},
12023 { TG3PCI_SUBVENDOR_ID_COMPAQ
,
12024 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2
, TG3_PHY_ID_BCM5701
},
12025 { TG3PCI_SUBVENDOR_ID_COMPAQ
,
12026 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING
, 0 },
12027 { TG3PCI_SUBVENDOR_ID_COMPAQ
,
12028 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780
, TG3_PHY_ID_BCM5701
},
12029 { TG3PCI_SUBVENDOR_ID_COMPAQ
,
12030 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2
, TG3_PHY_ID_BCM5701
},
12033 { TG3PCI_SUBVENDOR_ID_IBM
,
12034 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2
, 0 }
12037 static struct subsys_tbl_ent
* __devinit
tg3_lookup_by_subsys(struct tg3
*tp
)
12041 for (i
= 0; i
< ARRAY_SIZE(subsys_id_to_phy_id
); i
++) {
12042 if ((subsys_id_to_phy_id
[i
].subsys_vendor
==
12043 tp
->pdev
->subsystem_vendor
) &&
12044 (subsys_id_to_phy_id
[i
].subsys_devid
==
12045 tp
->pdev
->subsystem_device
))
12046 return &subsys_id_to_phy_id
[i
];
12051 static void __devinit
tg3_get_eeprom_hw_cfg(struct tg3
*tp
)
12056 /* On some early chips the SRAM cannot be accessed in D3hot state,
12057 * so need make sure we're in D0.
12059 pci_read_config_word(tp
->pdev
, tp
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
12060 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
12061 pci_write_config_word(tp
->pdev
, tp
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
12064 /* Make sure register accesses (indirect or otherwise)
12065 * will function correctly.
12067 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
12068 tp
->misc_host_ctrl
);
12070 /* The memory arbiter has to be enabled in order for SRAM accesses
12071 * to succeed. Normally on powerup the tg3 chip firmware will make
12072 * sure it is enabled, but other entities such as system netboot
12073 * code might disable it.
12075 val
= tr32(MEMARB_MODE
);
12076 tw32(MEMARB_MODE
, val
| MEMARB_MODE_ENABLE
);
12078 tp
->phy_id
= TG3_PHY_ID_INVALID
;
12079 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
12081 /* Assume an onboard device and WOL capable by default. */
12082 tp
->tg3_flags
|= TG3_FLAG_EEPROM_WRITE_PROT
| TG3_FLAG_WOL_CAP
;
12084 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
12085 if (!(tr32(PCIE_TRANSACTION_CFG
) & PCIE_TRANS_CFG_LOM
)) {
12086 tp
->tg3_flags
&= ~TG3_FLAG_EEPROM_WRITE_PROT
;
12087 tp
->tg3_flags2
|= TG3_FLG2_IS_NIC
;
12089 val
= tr32(VCPU_CFGSHDW
);
12090 if (val
& VCPU_CFGSHDW_ASPM_DBNC
)
12091 tp
->tg3_flags
|= TG3_FLAG_ASPM_WORKAROUND
;
12092 if ((val
& VCPU_CFGSHDW_WOL_ENABLE
) &&
12093 (val
& VCPU_CFGSHDW_WOL_MAGPKT
))
12094 tp
->tg3_flags
|= TG3_FLAG_WOL_ENABLE
;
12098 tg3_read_mem(tp
, NIC_SRAM_DATA_SIG
, &val
);
12099 if (val
== NIC_SRAM_DATA_SIG_MAGIC
) {
12100 u32 nic_cfg
, led_cfg
;
12101 u32 nic_phy_id
, ver
, cfg2
= 0, cfg4
= 0, eeprom_phy_id
;
12102 int eeprom_phy_serdes
= 0;
12104 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG
, &nic_cfg
);
12105 tp
->nic_sram_data_cfg
= nic_cfg
;
12107 tg3_read_mem(tp
, NIC_SRAM_DATA_VER
, &ver
);
12108 ver
>>= NIC_SRAM_DATA_VER_SHIFT
;
12109 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
) &&
12110 (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
) &&
12111 (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5703
) &&
12112 (ver
> 0) && (ver
< 0x100))
12113 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG_2
, &cfg2
);
12115 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
12116 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG_4
, &cfg4
);
12118 if ((nic_cfg
& NIC_SRAM_DATA_CFG_PHY_TYPE_MASK
) ==
12119 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER
)
12120 eeprom_phy_serdes
= 1;
12122 tg3_read_mem(tp
, NIC_SRAM_DATA_PHY_ID
, &nic_phy_id
);
12123 if (nic_phy_id
!= 0) {
12124 u32 id1
= nic_phy_id
& NIC_SRAM_DATA_PHY_ID1_MASK
;
12125 u32 id2
= nic_phy_id
& NIC_SRAM_DATA_PHY_ID2_MASK
;
12127 eeprom_phy_id
= (id1
>> 16) << 10;
12128 eeprom_phy_id
|= (id2
& 0xfc00) << 16;
12129 eeprom_phy_id
|= (id2
& 0x03ff) << 0;
12133 tp
->phy_id
= eeprom_phy_id
;
12134 if (eeprom_phy_serdes
) {
12135 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
12136 tp
->phy_flags
|= TG3_PHYFLG_PHY_SERDES
;
12138 tp
->phy_flags
|= TG3_PHYFLG_MII_SERDES
;
12141 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
12142 led_cfg
= cfg2
& (NIC_SRAM_DATA_CFG_LED_MODE_MASK
|
12143 SHASTA_EXT_LED_MODE_MASK
);
12145 led_cfg
= nic_cfg
& NIC_SRAM_DATA_CFG_LED_MODE_MASK
;
12149 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1
:
12150 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
12153 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2
:
12154 tp
->led_ctrl
= LED_CTRL_MODE_PHY_2
;
12157 case NIC_SRAM_DATA_CFG_LED_MODE_MAC
:
12158 tp
->led_ctrl
= LED_CTRL_MODE_MAC
;
12160 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12161 * read on some older 5700/5701 bootcode.
12163 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
12165 GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
12167 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
12171 case SHASTA_EXT_LED_SHARED
:
12172 tp
->led_ctrl
= LED_CTRL_MODE_SHARED
;
12173 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
&&
12174 tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A1
)
12175 tp
->led_ctrl
|= (LED_CTRL_MODE_PHY_1
|
12176 LED_CTRL_MODE_PHY_2
);
12179 case SHASTA_EXT_LED_MAC
:
12180 tp
->led_ctrl
= LED_CTRL_MODE_SHASTA_MAC
;
12183 case SHASTA_EXT_LED_COMBO
:
12184 tp
->led_ctrl
= LED_CTRL_MODE_COMBO
;
12185 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
)
12186 tp
->led_ctrl
|= (LED_CTRL_MODE_PHY_1
|
12187 LED_CTRL_MODE_PHY_2
);
12192 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
12193 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) &&
12194 tp
->pdev
->subsystem_vendor
== PCI_VENDOR_ID_DELL
)
12195 tp
->led_ctrl
= LED_CTRL_MODE_PHY_2
;
12197 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
)
12198 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
12200 if (nic_cfg
& NIC_SRAM_DATA_CFG_EEPROM_WP
) {
12201 tp
->tg3_flags
|= TG3_FLAG_EEPROM_WRITE_PROT
;
12202 if ((tp
->pdev
->subsystem_vendor
==
12203 PCI_VENDOR_ID_ARIMA
) &&
12204 (tp
->pdev
->subsystem_device
== 0x205a ||
12205 tp
->pdev
->subsystem_device
== 0x2063))
12206 tp
->tg3_flags
&= ~TG3_FLAG_EEPROM_WRITE_PROT
;
12208 tp
->tg3_flags
&= ~TG3_FLAG_EEPROM_WRITE_PROT
;
12209 tp
->tg3_flags2
|= TG3_FLG2_IS_NIC
;
12212 if (nic_cfg
& NIC_SRAM_DATA_CFG_ASF_ENABLE
) {
12213 tp
->tg3_flags
|= TG3_FLAG_ENABLE_ASF
;
12214 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
12215 tp
->tg3_flags2
|= TG3_FLG2_ASF_NEW_HANDSHAKE
;
12218 if ((nic_cfg
& NIC_SRAM_DATA_CFG_APE_ENABLE
) &&
12219 (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
))
12220 tp
->tg3_flags3
|= TG3_FLG3_ENABLE_APE
;
12222 if (tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
&&
12223 !(nic_cfg
& NIC_SRAM_DATA_CFG_FIBER_WOL
))
12224 tp
->tg3_flags
&= ~TG3_FLAG_WOL_CAP
;
12226 if ((tp
->tg3_flags
& TG3_FLAG_WOL_CAP
) &&
12227 (nic_cfg
& NIC_SRAM_DATA_CFG_WOL_ENABLE
))
12228 tp
->tg3_flags
|= TG3_FLAG_WOL_ENABLE
;
12230 if (cfg2
& (1 << 17))
12231 tp
->phy_flags
|= TG3_PHYFLG_CAPACITIVE_COUPLING
;
12233 /* serdes signal pre-emphasis in register 0x590 set by */
12234 /* bootcode if bit 18 is set */
12235 if (cfg2
& (1 << 18))
12236 tp
->phy_flags
|= TG3_PHYFLG_SERDES_PREEMPHASIS
;
12238 if (((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
12239 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
)) &&
12240 (cfg2
& NIC_SRAM_DATA_CFG_2_APD_EN
))
12241 tp
->phy_flags
|= TG3_PHYFLG_ENABLE_APD
;
12243 if ((tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) &&
12244 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5785
&&
12245 !(tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
)) {
12248 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG_3
, &cfg3
);
12249 if (cfg3
& NIC_SRAM_ASPM_DEBOUNCE
)
12250 tp
->tg3_flags
|= TG3_FLAG_ASPM_WORKAROUND
;
12253 if (cfg4
& NIC_SRAM_RGMII_INBAND_DISABLE
)
12254 tp
->tg3_flags3
|= TG3_FLG3_RGMII_INBAND_DISABLE
;
12255 if (cfg4
& NIC_SRAM_RGMII_EXT_IBND_RX_EN
)
12256 tp
->tg3_flags3
|= TG3_FLG3_RGMII_EXT_IBND_RX_EN
;
12257 if (cfg4
& NIC_SRAM_RGMII_EXT_IBND_TX_EN
)
12258 tp
->tg3_flags3
|= TG3_FLG3_RGMII_EXT_IBND_TX_EN
;
12261 device_init_wakeup(&tp
->pdev
->dev
, tp
->tg3_flags
& TG3_FLAG_WOL_CAP
);
12262 device_set_wakeup_enable(&tp
->pdev
->dev
,
12263 tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
);
12266 static int __devinit
tg3_issue_otp_command(struct tg3
*tp
, u32 cmd
)
12271 tw32(OTP_CTRL
, cmd
| OTP_CTRL_OTP_CMD_START
);
12272 tw32(OTP_CTRL
, cmd
);
12274 /* Wait for up to 1 ms for command to execute. */
12275 for (i
= 0; i
< 100; i
++) {
12276 val
= tr32(OTP_STATUS
);
12277 if (val
& OTP_STATUS_CMD_DONE
)
12282 return (val
& OTP_STATUS_CMD_DONE
) ? 0 : -EBUSY
;
12285 /* Read the gphy configuration from the OTP region of the chip. The gphy
12286 * configuration is a 32-bit value that straddles the alignment boundary.
12287 * We do two 32-bit reads and then shift and merge the results.
12289 static u32 __devinit
tg3_read_otp_phycfg(struct tg3
*tp
)
12291 u32 bhalf_otp
, thalf_otp
;
12293 tw32(OTP_MODE
, OTP_MODE_OTP_THRU_GRC
);
12295 if (tg3_issue_otp_command(tp
, OTP_CTRL_OTP_CMD_INIT
))
12298 tw32(OTP_ADDRESS
, OTP_ADDRESS_MAGIC1
);
12300 if (tg3_issue_otp_command(tp
, OTP_CTRL_OTP_CMD_READ
))
12303 thalf_otp
= tr32(OTP_READ_DATA
);
12305 tw32(OTP_ADDRESS
, OTP_ADDRESS_MAGIC2
);
12307 if (tg3_issue_otp_command(tp
, OTP_CTRL_OTP_CMD_READ
))
12310 bhalf_otp
= tr32(OTP_READ_DATA
);
12312 return ((thalf_otp
& 0x0000ffff) << 16) | (bhalf_otp
>> 16);
12315 static int __devinit
tg3_phy_probe(struct tg3
*tp
)
12317 u32 hw_phy_id_1
, hw_phy_id_2
;
12318 u32 hw_phy_id
, hw_phy_id_masked
;
12321 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
)
12322 return tg3_phy_init(tp
);
12324 /* Reading the PHY ID register can conflict with ASF
12325 * firmware access to the PHY hardware.
12328 if ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) ||
12329 (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)) {
12330 hw_phy_id
= hw_phy_id_masked
= TG3_PHY_ID_INVALID
;
12332 /* Now read the physical PHY_ID from the chip and verify
12333 * that it is sane. If it doesn't look good, we fall back
12334 * to either the hard-coded table based PHY_ID and failing
12335 * that the value found in the eeprom area.
12337 err
|= tg3_readphy(tp
, MII_PHYSID1
, &hw_phy_id_1
);
12338 err
|= tg3_readphy(tp
, MII_PHYSID2
, &hw_phy_id_2
);
12340 hw_phy_id
= (hw_phy_id_1
& 0xffff) << 10;
12341 hw_phy_id
|= (hw_phy_id_2
& 0xfc00) << 16;
12342 hw_phy_id
|= (hw_phy_id_2
& 0x03ff) << 0;
12344 hw_phy_id_masked
= hw_phy_id
& TG3_PHY_ID_MASK
;
12347 if (!err
&& TG3_KNOWN_PHY_ID(hw_phy_id_masked
)) {
12348 tp
->phy_id
= hw_phy_id
;
12349 if (hw_phy_id_masked
== TG3_PHY_ID_BCM8002
)
12350 tp
->phy_flags
|= TG3_PHYFLG_PHY_SERDES
;
12352 tp
->phy_flags
&= ~TG3_PHYFLG_PHY_SERDES
;
12354 if (tp
->phy_id
!= TG3_PHY_ID_INVALID
) {
12355 /* Do nothing, phy ID already set up in
12356 * tg3_get_eeprom_hw_cfg().
12359 struct subsys_tbl_ent
*p
;
12361 /* No eeprom signature? Try the hardcoded
12362 * subsys device table.
12364 p
= tg3_lookup_by_subsys(tp
);
12368 tp
->phy_id
= p
->phy_id
;
12370 tp
->phy_id
== TG3_PHY_ID_BCM8002
)
12371 tp
->phy_flags
|= TG3_PHYFLG_PHY_SERDES
;
12375 if (!(tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
) &&
12376 !(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) &&
12377 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)) {
12378 u32 bmsr
, adv_reg
, tg3_ctrl
, mask
;
12380 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
12381 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
12382 (bmsr
& BMSR_LSTATUS
))
12383 goto skip_phy_reset
;
12385 err
= tg3_phy_reset(tp
);
12389 adv_reg
= (ADVERTISE_10HALF
| ADVERTISE_10FULL
|
12390 ADVERTISE_100HALF
| ADVERTISE_100FULL
|
12391 ADVERTISE_CSMA
| ADVERTISE_PAUSE_CAP
);
12393 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
)) {
12394 tg3_ctrl
= (MII_TG3_CTRL_ADV_1000_HALF
|
12395 MII_TG3_CTRL_ADV_1000_FULL
);
12396 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
12397 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
)
12398 tg3_ctrl
|= (MII_TG3_CTRL_AS_MASTER
|
12399 MII_TG3_CTRL_ENABLE_AS_MASTER
);
12402 mask
= (ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
12403 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
|
12404 ADVERTISED_1000baseT_Half
| ADVERTISED_1000baseT_Full
);
12405 if (!tg3_copper_is_advertising_all(tp
, mask
)) {
12406 tg3_writephy(tp
, MII_ADVERTISE
, adv_reg
);
12408 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
))
12409 tg3_writephy(tp
, MII_TG3_CTRL
, tg3_ctrl
);
12411 tg3_writephy(tp
, MII_BMCR
,
12412 BMCR_ANENABLE
| BMCR_ANRESTART
);
12414 tg3_phy_set_wirespeed(tp
);
12416 tg3_writephy(tp
, MII_ADVERTISE
, adv_reg
);
12417 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
))
12418 tg3_writephy(tp
, MII_TG3_CTRL
, tg3_ctrl
);
12422 if ((tp
->phy_id
& TG3_PHY_ID_MASK
) == TG3_PHY_ID_BCM5401
) {
12423 err
= tg3_init_5401phy_dsp(tp
);
12427 err
= tg3_init_5401phy_dsp(tp
);
12430 if (tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
)
12431 tp
->link_config
.advertising
=
12432 (ADVERTISED_1000baseT_Half
|
12433 ADVERTISED_1000baseT_Full
|
12434 ADVERTISED_Autoneg
|
12436 if (tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
)
12437 tp
->link_config
.advertising
&=
12438 ~(ADVERTISED_1000baseT_Half
|
12439 ADVERTISED_1000baseT_Full
);
12444 static void __devinit
tg3_read_vpd(struct tg3
*tp
)
12447 unsigned int block_end
, rosize
, len
;
12451 if ((tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) ||
12452 tg3_nvram_read(tp
, 0x0, &magic
))
12455 vpd_data
= kmalloc(TG3_NVM_VPD_LEN
, GFP_KERNEL
);
12459 if (magic
== TG3_EEPROM_MAGIC
) {
12460 for (i
= 0; i
< TG3_NVM_VPD_LEN
; i
+= 4) {
12463 /* The data is in little-endian format in NVRAM.
12464 * Use the big-endian read routines to preserve
12465 * the byte order as it exists in NVRAM.
12467 if (tg3_nvram_read_be32(tp
, TG3_NVM_VPD_OFF
+ i
, &tmp
))
12468 goto out_not_found
;
12470 memcpy(&vpd_data
[i
], &tmp
, sizeof(tmp
));
12474 unsigned int pos
= 0;
12476 for (; pos
< TG3_NVM_VPD_LEN
&& i
< 3; i
++, pos
+= cnt
) {
12477 cnt
= pci_read_vpd(tp
->pdev
, pos
,
12478 TG3_NVM_VPD_LEN
- pos
,
12480 if (cnt
== -ETIMEDOUT
|| -EINTR
)
12483 goto out_not_found
;
12485 if (pos
!= TG3_NVM_VPD_LEN
)
12486 goto out_not_found
;
12489 i
= pci_vpd_find_tag(vpd_data
, 0, TG3_NVM_VPD_LEN
,
12490 PCI_VPD_LRDT_RO_DATA
);
12492 goto out_not_found
;
12494 rosize
= pci_vpd_lrdt_size(&vpd_data
[i
]);
12495 block_end
= i
+ PCI_VPD_LRDT_TAG_SIZE
+ rosize
;
12496 i
+= PCI_VPD_LRDT_TAG_SIZE
;
12498 if (block_end
> TG3_NVM_VPD_LEN
)
12499 goto out_not_found
;
12501 j
= pci_vpd_find_info_keyword(vpd_data
, i
, rosize
,
12502 PCI_VPD_RO_KEYWORD_MFR_ID
);
12504 len
= pci_vpd_info_field_size(&vpd_data
[j
]);
12506 j
+= PCI_VPD_INFO_FLD_HDR_SIZE
;
12507 if (j
+ len
> block_end
|| len
!= 4 ||
12508 memcmp(&vpd_data
[j
], "1028", 4))
12511 j
= pci_vpd_find_info_keyword(vpd_data
, i
, rosize
,
12512 PCI_VPD_RO_KEYWORD_VENDOR0
);
12516 len
= pci_vpd_info_field_size(&vpd_data
[j
]);
12518 j
+= PCI_VPD_INFO_FLD_HDR_SIZE
;
12519 if (j
+ len
> block_end
)
12522 memcpy(tp
->fw_ver
, &vpd_data
[j
], len
);
12523 strncat(tp
->fw_ver
, " bc ", TG3_NVM_VPD_LEN
- len
- 1);
12527 i
= pci_vpd_find_info_keyword(vpd_data
, i
, rosize
,
12528 PCI_VPD_RO_KEYWORD_PARTNO
);
12530 goto out_not_found
;
12532 len
= pci_vpd_info_field_size(&vpd_data
[i
]);
12534 i
+= PCI_VPD_INFO_FLD_HDR_SIZE
;
12535 if (len
> TG3_BPN_SIZE
||
12536 (len
+ i
) > TG3_NVM_VPD_LEN
)
12537 goto out_not_found
;
12539 memcpy(tp
->board_part_number
, &vpd_data
[i
], len
);
12543 if (tp
->board_part_number
[0])
12547 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
) {
12548 if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5717
)
12549 strcpy(tp
->board_part_number
, "BCM5717");
12550 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5718
)
12551 strcpy(tp
->board_part_number
, "BCM5718");
12554 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
) {
12555 if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57780
)
12556 strcpy(tp
->board_part_number
, "BCM57780");
12557 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57760
)
12558 strcpy(tp
->board_part_number
, "BCM57760");
12559 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57790
)
12560 strcpy(tp
->board_part_number
, "BCM57790");
12561 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57788
)
12562 strcpy(tp
->board_part_number
, "BCM57788");
12565 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
) {
12566 if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57761
)
12567 strcpy(tp
->board_part_number
, "BCM57761");
12568 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57765
)
12569 strcpy(tp
->board_part_number
, "BCM57765");
12570 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57781
)
12571 strcpy(tp
->board_part_number
, "BCM57781");
12572 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57785
)
12573 strcpy(tp
->board_part_number
, "BCM57785");
12574 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57791
)
12575 strcpy(tp
->board_part_number
, "BCM57791");
12576 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57795
)
12577 strcpy(tp
->board_part_number
, "BCM57795");
12580 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
12581 strcpy(tp
->board_part_number
, "BCM95906");
12584 strcpy(tp
->board_part_number
, "none");
12588 static int __devinit
tg3_fw_img_is_valid(struct tg3
*tp
, u32 offset
)
12592 if (tg3_nvram_read(tp
, offset
, &val
) ||
12593 (val
& 0xfc000000) != 0x0c000000 ||
12594 tg3_nvram_read(tp
, offset
+ 4, &val
) ||
12601 static void __devinit
tg3_read_bc_ver(struct tg3
*tp
)
12603 u32 val
, offset
, start
, ver_offset
;
12605 bool newver
= false;
12607 if (tg3_nvram_read(tp
, 0xc, &offset
) ||
12608 tg3_nvram_read(tp
, 0x4, &start
))
12611 offset
= tg3_nvram_logical_addr(tp
, offset
);
12613 if (tg3_nvram_read(tp
, offset
, &val
))
12616 if ((val
& 0xfc000000) == 0x0c000000) {
12617 if (tg3_nvram_read(tp
, offset
+ 4, &val
))
12624 dst_off
= strlen(tp
->fw_ver
);
12627 if (TG3_VER_SIZE
- dst_off
< 16 ||
12628 tg3_nvram_read(tp
, offset
+ 8, &ver_offset
))
12631 offset
= offset
+ ver_offset
- start
;
12632 for (i
= 0; i
< 16; i
+= 4) {
12634 if (tg3_nvram_read_be32(tp
, offset
+ i
, &v
))
12637 memcpy(tp
->fw_ver
+ dst_off
+ i
, &v
, sizeof(v
));
12642 if (tg3_nvram_read(tp
, TG3_NVM_PTREV_BCVER
, &ver_offset
))
12645 major
= (ver_offset
& TG3_NVM_BCVER_MAJMSK
) >>
12646 TG3_NVM_BCVER_MAJSFT
;
12647 minor
= ver_offset
& TG3_NVM_BCVER_MINMSK
;
12648 snprintf(&tp
->fw_ver
[dst_off
], TG3_VER_SIZE
- dst_off
,
12649 "v%d.%02d", major
, minor
);
12653 static void __devinit
tg3_read_hwsb_ver(struct tg3
*tp
)
12655 u32 val
, major
, minor
;
12657 /* Use native endian representation */
12658 if (tg3_nvram_read(tp
, TG3_NVM_HWSB_CFG1
, &val
))
12661 major
= (val
& TG3_NVM_HWSB_CFG1_MAJMSK
) >>
12662 TG3_NVM_HWSB_CFG1_MAJSFT
;
12663 minor
= (val
& TG3_NVM_HWSB_CFG1_MINMSK
) >>
12664 TG3_NVM_HWSB_CFG1_MINSFT
;
12666 snprintf(&tp
->fw_ver
[0], 32, "sb v%d.%02d", major
, minor
);
12669 static void __devinit
tg3_read_sb_ver(struct tg3
*tp
, u32 val
)
12671 u32 offset
, major
, minor
, build
;
12673 strncat(tp
->fw_ver
, "sb", TG3_VER_SIZE
- strlen(tp
->fw_ver
) - 1);
12675 if ((val
& TG3_EEPROM_SB_FORMAT_MASK
) != TG3_EEPROM_SB_FORMAT_1
)
12678 switch (val
& TG3_EEPROM_SB_REVISION_MASK
) {
12679 case TG3_EEPROM_SB_REVISION_0
:
12680 offset
= TG3_EEPROM_SB_F1R0_EDH_OFF
;
12682 case TG3_EEPROM_SB_REVISION_2
:
12683 offset
= TG3_EEPROM_SB_F1R2_EDH_OFF
;
12685 case TG3_EEPROM_SB_REVISION_3
:
12686 offset
= TG3_EEPROM_SB_F1R3_EDH_OFF
;
12688 case TG3_EEPROM_SB_REVISION_4
:
12689 offset
= TG3_EEPROM_SB_F1R4_EDH_OFF
;
12691 case TG3_EEPROM_SB_REVISION_5
:
12692 offset
= TG3_EEPROM_SB_F1R5_EDH_OFF
;
12698 if (tg3_nvram_read(tp
, offset
, &val
))
12701 build
= (val
& TG3_EEPROM_SB_EDH_BLD_MASK
) >>
12702 TG3_EEPROM_SB_EDH_BLD_SHFT
;
12703 major
= (val
& TG3_EEPROM_SB_EDH_MAJ_MASK
) >>
12704 TG3_EEPROM_SB_EDH_MAJ_SHFT
;
12705 minor
= val
& TG3_EEPROM_SB_EDH_MIN_MASK
;
12707 if (minor
> 99 || build
> 26)
12710 offset
= strlen(tp
->fw_ver
);
12711 snprintf(&tp
->fw_ver
[offset
], TG3_VER_SIZE
- offset
,
12712 " v%d.%02d", major
, minor
);
12715 offset
= strlen(tp
->fw_ver
);
12716 if (offset
< TG3_VER_SIZE
- 1)
12717 tp
->fw_ver
[offset
] = 'a' + build
- 1;
12721 static void __devinit
tg3_read_mgmtfw_ver(struct tg3
*tp
)
12723 u32 val
, offset
, start
;
12726 for (offset
= TG3_NVM_DIR_START
;
12727 offset
< TG3_NVM_DIR_END
;
12728 offset
+= TG3_NVM_DIRENT_SIZE
) {
12729 if (tg3_nvram_read(tp
, offset
, &val
))
12732 if ((val
>> TG3_NVM_DIRTYPE_SHIFT
) == TG3_NVM_DIRTYPE_ASFINI
)
12736 if (offset
== TG3_NVM_DIR_END
)
12739 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
12740 start
= 0x08000000;
12741 else if (tg3_nvram_read(tp
, offset
- 4, &start
))
12744 if (tg3_nvram_read(tp
, offset
+ 4, &offset
) ||
12745 !tg3_fw_img_is_valid(tp
, offset
) ||
12746 tg3_nvram_read(tp
, offset
+ 8, &val
))
12749 offset
+= val
- start
;
12751 vlen
= strlen(tp
->fw_ver
);
12753 tp
->fw_ver
[vlen
++] = ',';
12754 tp
->fw_ver
[vlen
++] = ' ';
12756 for (i
= 0; i
< 4; i
++) {
12758 if (tg3_nvram_read_be32(tp
, offset
, &v
))
12761 offset
+= sizeof(v
);
12763 if (vlen
> TG3_VER_SIZE
- sizeof(v
)) {
12764 memcpy(&tp
->fw_ver
[vlen
], &v
, TG3_VER_SIZE
- vlen
);
12768 memcpy(&tp
->fw_ver
[vlen
], &v
, sizeof(v
));
12773 static void __devinit
tg3_read_dash_ver(struct tg3
*tp
)
12779 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) ||
12780 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
12783 apedata
= tg3_ape_read32(tp
, TG3_APE_SEG_SIG
);
12784 if (apedata
!= APE_SEG_SIG_MAGIC
)
12787 apedata
= tg3_ape_read32(tp
, TG3_APE_FW_STATUS
);
12788 if (!(apedata
& APE_FW_STATUS_READY
))
12791 apedata
= tg3_ape_read32(tp
, TG3_APE_FW_VERSION
);
12793 if (tg3_ape_read32(tp
, TG3_APE_FW_FEATURES
) & TG3_APE_FW_FEATURE_NCSI
) {
12794 tp
->tg3_flags3
|= TG3_FLG3_APE_HAS_NCSI
;
12800 vlen
= strlen(tp
->fw_ver
);
12802 snprintf(&tp
->fw_ver
[vlen
], TG3_VER_SIZE
- vlen
, " %s v%d.%d.%d.%d",
12804 (apedata
& APE_FW_VERSION_MAJMSK
) >> APE_FW_VERSION_MAJSFT
,
12805 (apedata
& APE_FW_VERSION_MINMSK
) >> APE_FW_VERSION_MINSFT
,
12806 (apedata
& APE_FW_VERSION_REVMSK
) >> APE_FW_VERSION_REVSFT
,
12807 (apedata
& APE_FW_VERSION_BLDMSK
));
12810 static void __devinit
tg3_read_fw_ver(struct tg3
*tp
)
12813 bool vpd_vers
= false;
12815 if (tp
->fw_ver
[0] != 0)
12818 if (tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) {
12819 strcat(tp
->fw_ver
, "sb");
12823 if (tg3_nvram_read(tp
, 0, &val
))
12826 if (val
== TG3_EEPROM_MAGIC
)
12827 tg3_read_bc_ver(tp
);
12828 else if ((val
& TG3_EEPROM_MAGIC_FW_MSK
) == TG3_EEPROM_MAGIC_FW
)
12829 tg3_read_sb_ver(tp
, val
);
12830 else if ((val
& TG3_EEPROM_MAGIC_HW_MSK
) == TG3_EEPROM_MAGIC_HW
)
12831 tg3_read_hwsb_ver(tp
);
12835 if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) ||
12836 (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) || vpd_vers
)
12839 tg3_read_mgmtfw_ver(tp
);
12842 tp
->fw_ver
[TG3_VER_SIZE
- 1] = 0;
12845 static struct pci_dev
* __devinit
tg3_find_peer(struct tg3
*);
12847 static void inline vlan_features_add(struct net_device
*dev
, unsigned long flags
)
12849 #if TG3_VLAN_TAG_USED
12850 dev
->vlan_features
|= flags
;
12854 static int __devinit
tg3_get_invariants(struct tg3
*tp
)
12856 static struct pci_device_id write_reorder_chipsets
[] = {
12857 { PCI_DEVICE(PCI_VENDOR_ID_AMD
,
12858 PCI_DEVICE_ID_AMD_FE_GATE_700C
) },
12859 { PCI_DEVICE(PCI_VENDOR_ID_AMD
,
12860 PCI_DEVICE_ID_AMD_8131_BRIDGE
) },
12861 { PCI_DEVICE(PCI_VENDOR_ID_VIA
,
12862 PCI_DEVICE_ID_VIA_8385_0
) },
12866 u32 pci_state_reg
, grc_misc_cfg
;
12871 /* Force memory write invalidate off. If we leave it on,
12872 * then on 5700_BX chips we have to enable a workaround.
12873 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12874 * to match the cacheline size. The Broadcom driver have this
12875 * workaround but turns MWI off all the times so never uses
12876 * it. This seems to suggest that the workaround is insufficient.
12878 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
12879 pci_cmd
&= ~PCI_COMMAND_INVALIDATE
;
12880 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
12882 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12883 * has the register indirect write enable bit set before
12884 * we try to access any of the MMIO registers. It is also
12885 * critical that the PCI-X hw workaround situation is decided
12886 * before that as well.
12888 pci_read_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
12891 tp
->pci_chip_rev_id
= (misc_ctrl_reg
>>
12892 MISC_HOST_CTRL_CHIPREV_SHIFT
);
12893 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_USE_PROD_ID_REG
) {
12894 u32 prod_id_asic_rev
;
12896 if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5717
||
12897 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5718
||
12898 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5719
)
12899 pci_read_config_dword(tp
->pdev
,
12900 TG3PCI_GEN2_PRODID_ASICREV
,
12901 &prod_id_asic_rev
);
12902 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57781
||
12903 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57785
||
12904 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57761
||
12905 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57765
||
12906 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57791
||
12907 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57795
)
12908 pci_read_config_dword(tp
->pdev
,
12909 TG3PCI_GEN15_PRODID_ASICREV
,
12910 &prod_id_asic_rev
);
12912 pci_read_config_dword(tp
->pdev
, TG3PCI_PRODID_ASICREV
,
12913 &prod_id_asic_rev
);
12915 tp
->pci_chip_rev_id
= prod_id_asic_rev
;
12918 /* Wrong chip ID in 5752 A0. This code can be removed later
12919 * as A0 is not in production.
12921 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5752_A0_HW
)
12922 tp
->pci_chip_rev_id
= CHIPREV_ID_5752_A0
;
12924 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12925 * we need to disable memory and use config. cycles
12926 * only to access all registers. The 5702/03 chips
12927 * can mistakenly decode the special cycles from the
12928 * ICH chipsets as memory write cycles, causing corruption
12929 * of register and memory space. Only certain ICH bridges
12930 * will drive special cycles with non-zero data during the
12931 * address phase which can fall within the 5703's address
12932 * range. This is not an ICH bug as the PCI spec allows
12933 * non-zero address during special cycles. However, only
12934 * these ICH bridges are known to drive non-zero addresses
12935 * during special cycles.
12937 * Since special cycles do not cross PCI bridges, we only
12938 * enable this workaround if the 5703 is on the secondary
12939 * bus of these ICH bridges.
12941 if ((tp
->pci_chip_rev_id
== CHIPREV_ID_5703_A1
) ||
12942 (tp
->pci_chip_rev_id
== CHIPREV_ID_5703_A2
)) {
12943 static struct tg3_dev_id
{
12947 } ich_chipsets
[] = {
12948 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AA_8
,
12950 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AB_8
,
12952 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_11
,
12954 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_6
,
12958 struct tg3_dev_id
*pci_id
= &ich_chipsets
[0];
12959 struct pci_dev
*bridge
= NULL
;
12961 while (pci_id
->vendor
!= 0) {
12962 bridge
= pci_get_device(pci_id
->vendor
, pci_id
->device
,
12968 if (pci_id
->rev
!= PCI_ANY_ID
) {
12969 if (bridge
->revision
> pci_id
->rev
)
12972 if (bridge
->subordinate
&&
12973 (bridge
->subordinate
->number
==
12974 tp
->pdev
->bus
->number
)) {
12976 tp
->tg3_flags2
|= TG3_FLG2_ICH_WORKAROUND
;
12977 pci_dev_put(bridge
);
12983 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)) {
12984 static struct tg3_dev_id
{
12987 } bridge_chipsets
[] = {
12988 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_0
},
12989 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_1
},
12992 struct tg3_dev_id
*pci_id
= &bridge_chipsets
[0];
12993 struct pci_dev
*bridge
= NULL
;
12995 while (pci_id
->vendor
!= 0) {
12996 bridge
= pci_get_device(pci_id
->vendor
,
13003 if (bridge
->subordinate
&&
13004 (bridge
->subordinate
->number
<=
13005 tp
->pdev
->bus
->number
) &&
13006 (bridge
->subordinate
->subordinate
>=
13007 tp
->pdev
->bus
->number
)) {
13008 tp
->tg3_flags3
|= TG3_FLG3_5701_DMA_BUG
;
13009 pci_dev_put(bridge
);
13015 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
13016 * DMA addresses > 40-bit. This bridge may have other additional
13017 * 57xx devices behind it in some 4-port NIC designs for example.
13018 * Any tg3 device found behind the bridge will also need the 40-bit
13021 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5780
||
13022 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
) {
13023 tp
->tg3_flags2
|= TG3_FLG2_5780_CLASS
;
13024 tp
->tg3_flags
|= TG3_FLAG_40BIT_DMA_BUG
;
13025 tp
->msi_cap
= pci_find_capability(tp
->pdev
, PCI_CAP_ID_MSI
);
13027 struct pci_dev
*bridge
= NULL
;
13030 bridge
= pci_get_device(PCI_VENDOR_ID_SERVERWORKS
,
13031 PCI_DEVICE_ID_SERVERWORKS_EPB
,
13033 if (bridge
&& bridge
->subordinate
&&
13034 (bridge
->subordinate
->number
<=
13035 tp
->pdev
->bus
->number
) &&
13036 (bridge
->subordinate
->subordinate
>=
13037 tp
->pdev
->bus
->number
)) {
13038 tp
->tg3_flags
|= TG3_FLAG_40BIT_DMA_BUG
;
13039 pci_dev_put(bridge
);
13045 /* Initialize misc host control in PCI block. */
13046 tp
->misc_host_ctrl
|= (misc_ctrl_reg
&
13047 MISC_HOST_CTRL_CHIPREV
);
13048 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
13049 tp
->misc_host_ctrl
);
13051 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
13052 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
||
13053 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
)
13054 tp
->pdev_peer
= tg3_find_peer(tp
);
13056 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
13057 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
||
13058 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
13059 tp
->tg3_flags3
|= TG3_FLG3_5717_PLUS
;
13061 /* Intentionally exclude ASIC_REV_5906 */
13062 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
||
13063 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5787
||
13064 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
13065 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
13066 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
13067 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
||
13068 (tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
))
13069 tp
->tg3_flags3
|= TG3_FLG3_5755_PLUS
;
13071 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
||
13072 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
||
13073 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
||
13074 (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) ||
13075 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
13076 tp
->tg3_flags2
|= TG3_FLG2_5750_PLUS
;
13078 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) ||
13079 (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
))
13080 tp
->tg3_flags2
|= TG3_FLG2_5705_PLUS
;
13082 /* 5700 B0 chips do not support checksumming correctly due
13083 * to hardware bugs.
13085 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5700_B0
)
13086 tp
->tg3_flags
|= TG3_FLAG_BROKEN_CHECKSUMS
;
13088 unsigned long features
= NETIF_F_IP_CSUM
| NETIF_F_SG
| NETIF_F_GRO
;
13090 tp
->tg3_flags
|= TG3_FLAG_RX_CHECKSUMS
;
13091 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
13092 features
|= NETIF_F_IPV6_CSUM
;
13093 tp
->dev
->features
|= features
;
13094 vlan_features_add(tp
->dev
, features
);
13097 /* Determine TSO capabilities */
13098 if (tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
)
13099 tp
->tg3_flags2
|= TG3_FLG2_HW_TSO_3
;
13100 else if ((tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) ||
13101 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
13102 tp
->tg3_flags2
|= TG3_FLG2_HW_TSO_2
;
13103 else if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) {
13104 tp
->tg3_flags2
|= TG3_FLG2_HW_TSO_1
| TG3_FLG2_TSO_BUG
;
13105 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
&&
13106 tp
->pci_chip_rev_id
>= CHIPREV_ID_5750_C2
)
13107 tp
->tg3_flags2
&= ~TG3_FLG2_TSO_BUG
;
13108 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
13109 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
&&
13110 tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A0
) {
13111 tp
->tg3_flags2
|= TG3_FLG2_TSO_BUG
;
13112 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
)
13113 tp
->fw_needed
= FIRMWARE_TG3TSO5
;
13115 tp
->fw_needed
= FIRMWARE_TG3TSO
;
13120 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) {
13121 tp
->tg3_flags
|= TG3_FLAG_SUPPORT_MSI
;
13122 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_AX
||
13123 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_BX
||
13124 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
&&
13125 tp
->pci_chip_rev_id
<= CHIPREV_ID_5714_A2
&&
13126 tp
->pdev_peer
== tp
->pdev
))
13127 tp
->tg3_flags
&= ~TG3_FLAG_SUPPORT_MSI
;
13129 if ((tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) ||
13130 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
13131 tp
->tg3_flags2
|= TG3_FLG2_1SHOT_MSI
;
13134 if (tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
) {
13135 tp
->tg3_flags
|= TG3_FLAG_SUPPORT_MSIX
;
13136 tp
->irq_max
= TG3_IRQ_MAX_VECS
;
13140 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
13141 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
||
13142 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
13143 tp
->tg3_flags3
|= TG3_FLG3_SHORT_DMA_BUG
;
13144 else if (!(tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)) {
13145 tp
->tg3_flags3
|= TG3_FLG3_4G_DMA_BNDRY_BUG
;
13146 tp
->tg3_flags3
|= TG3_FLG3_40BIT_DMA_LIMIT_BUG
;
13149 if (tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
)
13150 tp
->tg3_flags3
|= TG3_FLG3_USE_JUMBO_BDFLAG
;
13152 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) ||
13153 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) ||
13154 (tp
->tg3_flags3
& TG3_FLG3_USE_JUMBO_BDFLAG
))
13155 tp
->tg3_flags
|= TG3_FLAG_JUMBO_CAPABLE
;
13157 pci_read_config_dword(tp
->pdev
, TG3PCI_PCISTATE
,
13160 tp
->pcie_cap
= pci_find_capability(tp
->pdev
, PCI_CAP_ID_EXP
);
13161 if (tp
->pcie_cap
!= 0) {
13164 tp
->tg3_flags2
|= TG3_FLG2_PCI_EXPRESS
;
13166 pcie_set_readrq(tp
->pdev
, 4096);
13168 pci_read_config_word(tp
->pdev
,
13169 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
13171 if (lnkctl
& PCI_EXP_LNKCTL_CLKREQ_EN
) {
13172 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
13173 tp
->tg3_flags2
&= ~TG3_FLG2_HW_TSO_2
;
13174 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
13175 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
13176 tp
->pci_chip_rev_id
== CHIPREV_ID_57780_A0
||
13177 tp
->pci_chip_rev_id
== CHIPREV_ID_57780_A1
)
13178 tp
->tg3_flags3
|= TG3_FLG3_CLKREQ_BUG
;
13179 } else if (tp
->pci_chip_rev_id
== CHIPREV_ID_5717_A0
) {
13180 tp
->tg3_flags3
|= TG3_FLG3_L1PLLPD_EN
;
13182 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
) {
13183 tp
->tg3_flags2
|= TG3_FLG2_PCI_EXPRESS
;
13184 } else if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) ||
13185 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
13186 tp
->pcix_cap
= pci_find_capability(tp
->pdev
, PCI_CAP_ID_PCIX
);
13187 if (!tp
->pcix_cap
) {
13188 dev_err(&tp
->pdev
->dev
,
13189 "Cannot find PCI-X capability, aborting\n");
13193 if (!(pci_state_reg
& PCISTATE_CONV_PCI_MODE
))
13194 tp
->tg3_flags
|= TG3_FLAG_PCIX_MODE
;
13197 /* If we have an AMD 762 or VIA K8T800 chipset, write
13198 * reordering to the mailbox registers done by the host
13199 * controller can cause major troubles. We read back from
13200 * every mailbox register write to force the writes to be
13201 * posted to the chip in order.
13203 if (pci_dev_present(write_reorder_chipsets
) &&
13204 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
))
13205 tp
->tg3_flags
|= TG3_FLAG_MBOX_WRITE_REORDER
;
13207 pci_read_config_byte(tp
->pdev
, PCI_CACHE_LINE_SIZE
,
13208 &tp
->pci_cacheline_sz
);
13209 pci_read_config_byte(tp
->pdev
, PCI_LATENCY_TIMER
,
13210 &tp
->pci_lat_timer
);
13211 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
&&
13212 tp
->pci_lat_timer
< 64) {
13213 tp
->pci_lat_timer
= 64;
13214 pci_write_config_byte(tp
->pdev
, PCI_LATENCY_TIMER
,
13215 tp
->pci_lat_timer
);
13218 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5700_BX
) {
13219 /* 5700 BX chips need to have their TX producer index
13220 * mailboxes written twice to workaround a bug.
13222 tp
->tg3_flags
|= TG3_FLAG_TXD_MBOX_HWBUG
;
13224 /* If we are in PCI-X mode, enable register write workaround.
13226 * The workaround is to use indirect register accesses
13227 * for all chip writes not to mailbox registers.
13229 if (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) {
13232 tp
->tg3_flags
|= TG3_FLAG_PCIX_TARGET_HWBUG
;
13234 /* The chip can have it's power management PCI config
13235 * space registers clobbered due to this bug.
13236 * So explicitly force the chip into D0 here.
13238 pci_read_config_dword(tp
->pdev
,
13239 tp
->pm_cap
+ PCI_PM_CTRL
,
13241 pm_reg
&= ~PCI_PM_CTRL_STATE_MASK
;
13242 pm_reg
|= PCI_PM_CTRL_PME_ENABLE
| 0 /* D0 */;
13243 pci_write_config_dword(tp
->pdev
,
13244 tp
->pm_cap
+ PCI_PM_CTRL
,
13247 /* Also, force SERR#/PERR# in PCI command. */
13248 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
13249 pci_cmd
|= PCI_COMMAND_PARITY
| PCI_COMMAND_SERR
;
13250 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
13254 if ((pci_state_reg
& PCISTATE_BUS_SPEED_HIGH
) != 0)
13255 tp
->tg3_flags
|= TG3_FLAG_PCI_HIGH_SPEED
;
13256 if ((pci_state_reg
& PCISTATE_BUS_32BIT
) != 0)
13257 tp
->tg3_flags
|= TG3_FLAG_PCI_32BIT
;
13259 /* Chip-specific fixup from Broadcom driver */
13260 if ((tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
) &&
13261 (!(pci_state_reg
& PCISTATE_RETRY_SAME_DMA
))) {
13262 pci_state_reg
|= PCISTATE_RETRY_SAME_DMA
;
13263 pci_write_config_dword(tp
->pdev
, TG3PCI_PCISTATE
, pci_state_reg
);
13266 /* Default fast path register access methods */
13267 tp
->read32
= tg3_read32
;
13268 tp
->write32
= tg3_write32
;
13269 tp
->read32_mbox
= tg3_read32
;
13270 tp
->write32_mbox
= tg3_write32
;
13271 tp
->write32_tx_mbox
= tg3_write32
;
13272 tp
->write32_rx_mbox
= tg3_write32
;
13274 /* Various workaround register access methods */
13275 if (tp
->tg3_flags
& TG3_FLAG_PCIX_TARGET_HWBUG
)
13276 tp
->write32
= tg3_write_indirect_reg32
;
13277 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
||
13278 ((tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) &&
13279 tp
->pci_chip_rev_id
== CHIPREV_ID_5750_A0
)) {
13281 * Back to back register writes can cause problems on these
13282 * chips, the workaround is to read back all reg writes
13283 * except those to mailbox regs.
13285 * See tg3_write_indirect_reg32().
13287 tp
->write32
= tg3_write_flush_reg32
;
13290 if ((tp
->tg3_flags
& TG3_FLAG_TXD_MBOX_HWBUG
) ||
13291 (tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
)) {
13292 tp
->write32_tx_mbox
= tg3_write32_tx_mbox
;
13293 if (tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
)
13294 tp
->write32_rx_mbox
= tg3_write_flush_reg32
;
13297 if (tp
->tg3_flags2
& TG3_FLG2_ICH_WORKAROUND
) {
13298 tp
->read32
= tg3_read_indirect_reg32
;
13299 tp
->write32
= tg3_write_indirect_reg32
;
13300 tp
->read32_mbox
= tg3_read_indirect_mbox
;
13301 tp
->write32_mbox
= tg3_write_indirect_mbox
;
13302 tp
->write32_tx_mbox
= tg3_write_indirect_mbox
;
13303 tp
->write32_rx_mbox
= tg3_write_indirect_mbox
;
13308 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
13309 pci_cmd
&= ~PCI_COMMAND_MEMORY
;
13310 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
13312 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
13313 tp
->read32_mbox
= tg3_read32_mbox_5906
;
13314 tp
->write32_mbox
= tg3_write32_mbox_5906
;
13315 tp
->write32_tx_mbox
= tg3_write32_mbox_5906
;
13316 tp
->write32_rx_mbox
= tg3_write32_mbox_5906
;
13319 if (tp
->write32
== tg3_write_indirect_reg32
||
13320 ((tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) &&
13321 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
13322 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)))
13323 tp
->tg3_flags
|= TG3_FLAG_SRAM_USE_CONFIG
;
13325 /* Get eeprom hw config before calling tg3_set_power_state().
13326 * In particular, the TG3_FLG2_IS_NIC flag must be
13327 * determined before calling tg3_set_power_state() so that
13328 * we know whether or not to switch out of Vaux power.
13329 * When the flag is set, it means that GPIO1 is used for eeprom
13330 * write protect and also implies that it is a LOM where GPIOs
13331 * are not used to switch power.
13333 tg3_get_eeprom_hw_cfg(tp
);
13335 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
13336 /* Allow reads and writes to the
13337 * APE register and memory space.
13339 pci_state_reg
|= PCISTATE_ALLOW_APE_CTLSPC_WR
|
13340 PCISTATE_ALLOW_APE_SHMEM_WR
|
13341 PCISTATE_ALLOW_APE_PSPACE_WR
;
13342 pci_write_config_dword(tp
->pdev
, TG3PCI_PCISTATE
,
13346 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
13347 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
13348 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
13349 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
||
13350 (tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
))
13351 tp
->tg3_flags
|= TG3_FLAG_CPMU_PRESENT
;
13353 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13354 * GPIO1 driven high will bring 5700's external PHY out of reset.
13355 * It is also used as eeprom write protect on LOMs.
13357 tp
->grc_local_ctrl
= GRC_LCLCTRL_INT_ON_ATTN
| GRC_LCLCTRL_AUTO_SEEPROM
;
13358 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) ||
13359 (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
))
13360 tp
->grc_local_ctrl
|= (GRC_LCLCTRL_GPIO_OE1
|
13361 GRC_LCLCTRL_GPIO_OUTPUT1
);
13362 /* Unused GPIO3 must be driven as output on 5752 because there
13363 * are no pull-up resistors on unused GPIO pins.
13365 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
)
13366 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE3
;
13368 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
||
13369 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
||
13370 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
13371 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_UART_SEL
;
13373 if (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5761
||
13374 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5761S
) {
13375 /* Turn off the debug UART. */
13376 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_UART_SEL
;
13377 if (tp
->tg3_flags2
& TG3_FLG2_IS_NIC
)
13378 /* Keep VMain power. */
13379 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE0
|
13380 GRC_LCLCTRL_GPIO_OUTPUT0
;
13383 /* Force the chip into D0. */
13384 err
= tg3_set_power_state(tp
, PCI_D0
);
13386 dev_err(&tp
->pdev
->dev
, "Transition to D0 failed\n");
13390 /* Derive initial jumbo mode from MTU assigned in
13391 * ether_setup() via the alloc_etherdev() call
13393 if (tp
->dev
->mtu
> ETH_DATA_LEN
&&
13394 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
13395 tp
->tg3_flags
|= TG3_FLAG_JUMBO_RING_ENABLE
;
13397 /* Determine WakeOnLan speed to use. */
13398 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
13399 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
13400 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
||
13401 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B2
) {
13402 tp
->tg3_flags
&= ~(TG3_FLAG_WOL_SPEED_100MB
);
13404 tp
->tg3_flags
|= TG3_FLAG_WOL_SPEED_100MB
;
13407 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
13408 tp
->phy_flags
|= TG3_PHYFLG_IS_FET
;
13410 /* A few boards don't want Ethernet@WireSpeed phy feature */
13411 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) ||
13412 ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) &&
13413 (tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A0
) &&
13414 (tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A1
)) ||
13415 (tp
->phy_flags
& TG3_PHYFLG_IS_FET
) ||
13416 (tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
))
13417 tp
->phy_flags
|= TG3_PHYFLG_NO_ETH_WIRE_SPEED
;
13419 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5703_AX
||
13420 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5704_AX
)
13421 tp
->phy_flags
|= TG3_PHYFLG_ADC_BUG
;
13422 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
)
13423 tp
->phy_flags
|= TG3_PHYFLG_5704_A0_BUG
;
13425 if ((tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
13426 !(tp
->phy_flags
& TG3_PHYFLG_IS_FET
) &&
13427 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5785
&&
13428 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_57780
&&
13429 !(tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
)) {
13430 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
||
13431 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5787
||
13432 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
13433 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
) {
13434 if (tp
->pdev
->device
!= PCI_DEVICE_ID_TIGON3_5756
&&
13435 tp
->pdev
->device
!= PCI_DEVICE_ID_TIGON3_5722
)
13436 tp
->phy_flags
|= TG3_PHYFLG_JITTER_BUG
;
13437 if (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5755M
)
13438 tp
->phy_flags
|= TG3_PHYFLG_ADJUST_TRIM
;
13440 tp
->phy_flags
|= TG3_PHYFLG_BER_BUG
;
13443 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
13444 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
) {
13445 tp
->phy_otp
= tg3_read_otp_phycfg(tp
);
13446 if (tp
->phy_otp
== 0)
13447 tp
->phy_otp
= TG3_OTP_DEFAULT
;
13450 if (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
)
13451 tp
->mi_mode
= MAC_MI_MODE_500KHZ_CONST
;
13453 tp
->mi_mode
= MAC_MI_MODE_BASE
;
13455 tp
->coalesce_mode
= 0;
13456 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5700_AX
&&
13457 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5700_BX
)
13458 tp
->coalesce_mode
|= HOSTCC_MODE_32BYTE
;
13460 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
13461 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
13462 tp
->tg3_flags3
|= TG3_FLG3_USE_PHYLIB
;
13464 err
= tg3_mdio_init(tp
);
13468 /* Initialize data/descriptor byte/word swapping. */
13469 val
= tr32(GRC_MODE
);
13470 val
&= GRC_MODE_HOST_STACKUP
;
13471 tw32(GRC_MODE
, val
| tp
->grc_mode
);
13473 tg3_switch_clocks(tp
);
13475 /* Clear this out for sanity. */
13476 tw32(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
13478 pci_read_config_dword(tp
->pdev
, TG3PCI_PCISTATE
,
13480 if ((pci_state_reg
& PCISTATE_CONV_PCI_MODE
) == 0 &&
13481 (tp
->tg3_flags
& TG3_FLAG_PCIX_TARGET_HWBUG
) == 0) {
13482 u32 chiprevid
= GET_CHIP_REV_ID(tp
->misc_host_ctrl
);
13484 if (chiprevid
== CHIPREV_ID_5701_A0
||
13485 chiprevid
== CHIPREV_ID_5701_B0
||
13486 chiprevid
== CHIPREV_ID_5701_B2
||
13487 chiprevid
== CHIPREV_ID_5701_B5
) {
13488 void __iomem
*sram_base
;
13490 /* Write some dummy words into the SRAM status block
13491 * area, see if it reads back correctly. If the return
13492 * value is bad, force enable the PCIX workaround.
13494 sram_base
= tp
->regs
+ NIC_SRAM_WIN_BASE
+ NIC_SRAM_STATS_BLK
;
13496 writel(0x00000000, sram_base
);
13497 writel(0x00000000, sram_base
+ 4);
13498 writel(0xffffffff, sram_base
+ 4);
13499 if (readl(sram_base
) != 0x00000000)
13500 tp
->tg3_flags
|= TG3_FLAG_PCIX_TARGET_HWBUG
;
13505 tg3_nvram_init(tp
);
13507 grc_misc_cfg
= tr32(GRC_MISC_CFG
);
13508 grc_misc_cfg
&= GRC_MISC_CFG_BOARD_ID_MASK
;
13510 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
13511 (grc_misc_cfg
== GRC_MISC_CFG_BOARD_ID_5788
||
13512 grc_misc_cfg
== GRC_MISC_CFG_BOARD_ID_5788M
))
13513 tp
->tg3_flags2
|= TG3_FLG2_IS_5788
;
13515 if (!(tp
->tg3_flags2
& TG3_FLG2_IS_5788
) &&
13516 (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
))
13517 tp
->tg3_flags
|= TG3_FLAG_TAGGED_STATUS
;
13518 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) {
13519 tp
->coalesce_mode
|= (HOSTCC_MODE_CLRTICK_RXBD
|
13520 HOSTCC_MODE_CLRTICK_TXBD
);
13522 tp
->misc_host_ctrl
|= MISC_HOST_CTRL_TAGGED_STATUS
;
13523 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
13524 tp
->misc_host_ctrl
);
13527 /* Preserve the APE MAC_MODE bits */
13528 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
13529 tp
->mac_mode
= tr32(MAC_MODE
) |
13530 MAC_MODE_APE_TX_EN
| MAC_MODE_APE_RX_EN
;
13532 tp
->mac_mode
= TG3_DEF_MAC_MODE
;
13534 /* these are limited to 10/100 only */
13535 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
&&
13536 (grc_misc_cfg
== 0x8000 || grc_misc_cfg
== 0x4000)) ||
13537 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
13538 tp
->pdev
->vendor
== PCI_VENDOR_ID_BROADCOM
&&
13539 (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5901
||
13540 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5901_2
||
13541 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5705F
)) ||
13542 (tp
->pdev
->vendor
== PCI_VENDOR_ID_BROADCOM
&&
13543 (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5751F
||
13544 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5753F
||
13545 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5787F
)) ||
13546 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57790
||
13547 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57791
||
13548 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57795
||
13549 (tp
->phy_flags
& TG3_PHYFLG_IS_FET
))
13550 tp
->phy_flags
|= TG3_PHYFLG_10_100_ONLY
;
13552 err
= tg3_phy_probe(tp
);
13554 dev_err(&tp
->pdev
->dev
, "phy probe failed, err %d\n", err
);
13555 /* ... but do not return immediately ... */
13560 tg3_read_fw_ver(tp
);
13562 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) {
13563 tp
->phy_flags
&= ~TG3_PHYFLG_USE_MI_INTERRUPT
;
13565 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
)
13566 tp
->phy_flags
|= TG3_PHYFLG_USE_MI_INTERRUPT
;
13568 tp
->phy_flags
&= ~TG3_PHYFLG_USE_MI_INTERRUPT
;
13571 /* 5700 {AX,BX} chips have a broken status block link
13572 * change bit implementation, so we must use the
13573 * status register in those cases.
13575 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
)
13576 tp
->tg3_flags
|= TG3_FLAG_USE_LINKCHG_REG
;
13578 tp
->tg3_flags
&= ~TG3_FLAG_USE_LINKCHG_REG
;
13580 /* The led_ctrl is set during tg3_phy_probe, here we might
13581 * have to force the link status polling mechanism based
13582 * upon subsystem IDs.
13584 if (tp
->pdev
->subsystem_vendor
== PCI_VENDOR_ID_DELL
&&
13585 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
&&
13586 !(tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
)) {
13587 tp
->phy_flags
|= TG3_PHYFLG_USE_MI_INTERRUPT
;
13588 tp
->tg3_flags
|= TG3_FLAG_USE_LINKCHG_REG
;
13591 /* For all SERDES we poll the MAC status register. */
13592 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
)
13593 tp
->tg3_flags
|= TG3_FLAG_POLL_SERDES
;
13595 tp
->tg3_flags
&= ~TG3_FLAG_POLL_SERDES
;
13597 tp
->rx_offset
= NET_IP_ALIGN
+ TG3_RX_HEADROOM
;
13598 tp
->rx_copy_thresh
= TG3_RX_COPY_THRESHOLD
;
13599 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
&&
13600 (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) != 0) {
13601 tp
->rx_offset
-= NET_IP_ALIGN
;
13602 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
13603 tp
->rx_copy_thresh
= ~(u16
)0;
13607 tp
->rx_std_ring_mask
= TG3_RX_STD_RING_SIZE(tp
) - 1;
13608 tp
->rx_jmb_ring_mask
= TG3_RX_JMB_RING_SIZE(tp
) - 1;
13609 tp
->rx_std_max_post
= tp
->rx_std_ring_mask
+ 1;
13611 /* Increment the rx prod index on the rx std ring by at most
13612 * 8 for these chips to workaround hw errata.
13614 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
||
13615 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
||
13616 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
)
13617 tp
->rx_std_max_post
= 8;
13619 if (tp
->tg3_flags
& TG3_FLAG_ASPM_WORKAROUND
)
13620 tp
->pwrmgmt_thresh
= tr32(PCIE_PWR_MGMT_THRESH
) &
13621 PCIE_PWR_MGMT_L1_THRESH_MSK
;
13626 #ifdef CONFIG_SPARC
13627 static int __devinit
tg3_get_macaddr_sparc(struct tg3
*tp
)
13629 struct net_device
*dev
= tp
->dev
;
13630 struct pci_dev
*pdev
= tp
->pdev
;
13631 struct device_node
*dp
= pci_device_to_OF_node(pdev
);
13632 const unsigned char *addr
;
13635 addr
= of_get_property(dp
, "local-mac-address", &len
);
13636 if (addr
&& len
== 6) {
13637 memcpy(dev
->dev_addr
, addr
, 6);
13638 memcpy(dev
->perm_addr
, dev
->dev_addr
, 6);
13644 static int __devinit
tg3_get_default_macaddr_sparc(struct tg3
*tp
)
13646 struct net_device
*dev
= tp
->dev
;
13648 memcpy(dev
->dev_addr
, idprom
->id_ethaddr
, 6);
13649 memcpy(dev
->perm_addr
, idprom
->id_ethaddr
, 6);
13654 static int __devinit
tg3_get_device_address(struct tg3
*tp
)
13656 struct net_device
*dev
= tp
->dev
;
13657 u32 hi
, lo
, mac_offset
;
13660 #ifdef CONFIG_SPARC
13661 if (!tg3_get_macaddr_sparc(tp
))
13666 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) ||
13667 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
13668 if (tr32(TG3PCI_DUAL_MAC_CTRL
) & DUAL_MAC_CTRL_ID
)
13670 if (tg3_nvram_lock(tp
))
13671 tw32_f(NVRAM_CMD
, NVRAM_CMD_RESET
);
13673 tg3_nvram_unlock(tp
);
13674 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
13675 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
) {
13676 if (PCI_FUNC(tp
->pdev
->devfn
) & 1)
13678 if (PCI_FUNC(tp
->pdev
->devfn
) > 1)
13679 mac_offset
+= 0x18c;
13680 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
13683 /* First try to get it from MAC address mailbox. */
13684 tg3_read_mem(tp
, NIC_SRAM_MAC_ADDR_HIGH_MBOX
, &hi
);
13685 if ((hi
>> 16) == 0x484b) {
13686 dev
->dev_addr
[0] = (hi
>> 8) & 0xff;
13687 dev
->dev_addr
[1] = (hi
>> 0) & 0xff;
13689 tg3_read_mem(tp
, NIC_SRAM_MAC_ADDR_LOW_MBOX
, &lo
);
13690 dev
->dev_addr
[2] = (lo
>> 24) & 0xff;
13691 dev
->dev_addr
[3] = (lo
>> 16) & 0xff;
13692 dev
->dev_addr
[4] = (lo
>> 8) & 0xff;
13693 dev
->dev_addr
[5] = (lo
>> 0) & 0xff;
13695 /* Some old bootcode may report a 0 MAC address in SRAM */
13696 addr_ok
= is_valid_ether_addr(&dev
->dev_addr
[0]);
13699 /* Next, try NVRAM. */
13700 if (!(tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) &&
13701 !tg3_nvram_read_be32(tp
, mac_offset
+ 0, &hi
) &&
13702 !tg3_nvram_read_be32(tp
, mac_offset
+ 4, &lo
)) {
13703 memcpy(&dev
->dev_addr
[0], ((char *)&hi
) + 2, 2);
13704 memcpy(&dev
->dev_addr
[2], (char *)&lo
, sizeof(lo
));
13706 /* Finally just fetch it out of the MAC control regs. */
13708 hi
= tr32(MAC_ADDR_0_HIGH
);
13709 lo
= tr32(MAC_ADDR_0_LOW
);
13711 dev
->dev_addr
[5] = lo
& 0xff;
13712 dev
->dev_addr
[4] = (lo
>> 8) & 0xff;
13713 dev
->dev_addr
[3] = (lo
>> 16) & 0xff;
13714 dev
->dev_addr
[2] = (lo
>> 24) & 0xff;
13715 dev
->dev_addr
[1] = hi
& 0xff;
13716 dev
->dev_addr
[0] = (hi
>> 8) & 0xff;
13720 if (!is_valid_ether_addr(&dev
->dev_addr
[0])) {
13721 #ifdef CONFIG_SPARC
13722 if (!tg3_get_default_macaddr_sparc(tp
))
13727 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
13731 #define BOUNDARY_SINGLE_CACHELINE 1
13732 #define BOUNDARY_MULTI_CACHELINE 2
13734 static u32 __devinit
tg3_calc_dma_bndry(struct tg3
*tp
, u32 val
)
13736 int cacheline_size
;
13740 pci_read_config_byte(tp
->pdev
, PCI_CACHE_LINE_SIZE
, &byte
);
13742 cacheline_size
= 1024;
13744 cacheline_size
= (int) byte
* 4;
13746 /* On 5703 and later chips, the boundary bits have no
13749 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
13750 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
&&
13751 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
))
13754 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13755 goal
= BOUNDARY_MULTI_CACHELINE
;
13757 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13758 goal
= BOUNDARY_SINGLE_CACHELINE
;
13764 if (tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
) {
13765 val
= goal
? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT
;
13772 /* PCI controllers on most RISC systems tend to disconnect
13773 * when a device tries to burst across a cache-line boundary.
13774 * Therefore, letting tg3 do so just wastes PCI bandwidth.
13776 * Unfortunately, for PCI-E there are only limited
13777 * write-side controls for this, and thus for reads
13778 * we will still get the disconnects. We'll also waste
13779 * these PCI cycles for both read and write for chips
13780 * other than 5700 and 5701 which do not implement the
13783 if ((tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) &&
13784 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)) {
13785 switch (cacheline_size
) {
13790 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
13791 val
|= (DMA_RWCTRL_READ_BNDRY_128_PCIX
|
13792 DMA_RWCTRL_WRITE_BNDRY_128_PCIX
);
13794 val
|= (DMA_RWCTRL_READ_BNDRY_384_PCIX
|
13795 DMA_RWCTRL_WRITE_BNDRY_384_PCIX
);
13800 val
|= (DMA_RWCTRL_READ_BNDRY_256_PCIX
|
13801 DMA_RWCTRL_WRITE_BNDRY_256_PCIX
);
13805 val
|= (DMA_RWCTRL_READ_BNDRY_384_PCIX
|
13806 DMA_RWCTRL_WRITE_BNDRY_384_PCIX
);
13809 } else if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
13810 switch (cacheline_size
) {
13814 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
13815 val
&= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE
;
13816 val
|= DMA_RWCTRL_WRITE_BNDRY_64_PCIE
;
13822 val
&= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE
;
13823 val
|= DMA_RWCTRL_WRITE_BNDRY_128_PCIE
;
13827 switch (cacheline_size
) {
13829 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
13830 val
|= (DMA_RWCTRL_READ_BNDRY_16
|
13831 DMA_RWCTRL_WRITE_BNDRY_16
);
13836 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
13837 val
|= (DMA_RWCTRL_READ_BNDRY_32
|
13838 DMA_RWCTRL_WRITE_BNDRY_32
);
13843 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
13844 val
|= (DMA_RWCTRL_READ_BNDRY_64
|
13845 DMA_RWCTRL_WRITE_BNDRY_64
);
13850 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
13851 val
|= (DMA_RWCTRL_READ_BNDRY_128
|
13852 DMA_RWCTRL_WRITE_BNDRY_128
);
13857 val
|= (DMA_RWCTRL_READ_BNDRY_256
|
13858 DMA_RWCTRL_WRITE_BNDRY_256
);
13861 val
|= (DMA_RWCTRL_READ_BNDRY_512
|
13862 DMA_RWCTRL_WRITE_BNDRY_512
);
13866 val
|= (DMA_RWCTRL_READ_BNDRY_1024
|
13867 DMA_RWCTRL_WRITE_BNDRY_1024
);
13876 static int __devinit
tg3_do_test_dma(struct tg3
*tp
, u32
*buf
, dma_addr_t buf_dma
, int size
, int to_device
)
13878 struct tg3_internal_buffer_desc test_desc
;
13879 u32 sram_dma_descs
;
13882 sram_dma_descs
= NIC_SRAM_DMA_DESC_POOL_BASE
;
13884 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ
, 0);
13885 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ
, 0);
13886 tw32(RDMAC_STATUS
, 0);
13887 tw32(WDMAC_STATUS
, 0);
13889 tw32(BUFMGR_MODE
, 0);
13890 tw32(FTQ_RESET
, 0);
13892 test_desc
.addr_hi
= ((u64
) buf_dma
) >> 32;
13893 test_desc
.addr_lo
= buf_dma
& 0xffffffff;
13894 test_desc
.nic_mbuf
= 0x00002100;
13895 test_desc
.len
= size
;
13898 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13899 * the *second* time the tg3 driver was getting loaded after an
13902 * Broadcom tells me:
13903 * ...the DMA engine is connected to the GRC block and a DMA
13904 * reset may affect the GRC block in some unpredictable way...
13905 * The behavior of resets to individual blocks has not been tested.
13907 * Broadcom noted the GRC reset will also reset all sub-components.
13910 test_desc
.cqid_sqid
= (13 << 8) | 2;
13912 tw32_f(RDMAC_MODE
, RDMAC_MODE_ENABLE
);
13915 test_desc
.cqid_sqid
= (16 << 8) | 7;
13917 tw32_f(WDMAC_MODE
, WDMAC_MODE_ENABLE
);
13920 test_desc
.flags
= 0x00000005;
13922 for (i
= 0; i
< (sizeof(test_desc
) / sizeof(u32
)); i
++) {
13925 val
= *(((u32
*)&test_desc
) + i
);
13926 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
,
13927 sram_dma_descs
+ (i
* sizeof(u32
)));
13928 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_DATA
, val
);
13930 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, 0);
13933 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ
, sram_dma_descs
);
13935 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ
, sram_dma_descs
);
13938 for (i
= 0; i
< 40; i
++) {
13942 val
= tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ
);
13944 val
= tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ
);
13945 if ((val
& 0xffff) == sram_dma_descs
) {
13956 #define TEST_BUFFER_SIZE 0x2000
13958 static int __devinit
tg3_test_dma(struct tg3
*tp
)
13960 dma_addr_t buf_dma
;
13961 u32
*buf
, saved_dma_rwctrl
;
13964 buf
= pci_alloc_consistent(tp
->pdev
, TEST_BUFFER_SIZE
, &buf_dma
);
13970 tp
->dma_rwctrl
= ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT
) |
13971 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT
));
13973 tp
->dma_rwctrl
= tg3_calc_dma_bndry(tp
, tp
->dma_rwctrl
);
13975 if (tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
)
13978 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
13979 /* DMA read watermark not used on PCIE */
13980 tp
->dma_rwctrl
|= 0x00180000;
13981 } else if (!(tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
)) {
13982 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
||
13983 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
)
13984 tp
->dma_rwctrl
|= 0x003f0000;
13986 tp
->dma_rwctrl
|= 0x003f000f;
13988 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
13989 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
13990 u32 ccval
= (tr32(TG3PCI_CLOCK_CTRL
) & 0x1f);
13991 u32 read_water
= 0x7;
13993 /* If the 5704 is behind the EPB bridge, we can
13994 * do the less restrictive ONE_DMA workaround for
13995 * better performance.
13997 if ((tp
->tg3_flags
& TG3_FLAG_40BIT_DMA_BUG
) &&
13998 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
)
13999 tp
->dma_rwctrl
|= 0x8000;
14000 else if (ccval
== 0x6 || ccval
== 0x7)
14001 tp
->dma_rwctrl
|= DMA_RWCTRL_ONE_DMA
;
14003 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
)
14005 /* Set bit 23 to enable PCIX hw bug fix */
14007 (read_water
<< DMA_RWCTRL_READ_WATER_SHIFT
) |
14008 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT
) |
14010 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5780
) {
14011 /* 5780 always in PCIX mode */
14012 tp
->dma_rwctrl
|= 0x00144000;
14013 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
) {
14014 /* 5714 always in PCIX mode */
14015 tp
->dma_rwctrl
|= 0x00148000;
14017 tp
->dma_rwctrl
|= 0x001b000f;
14021 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
14022 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
)
14023 tp
->dma_rwctrl
&= 0xfffffff0;
14025 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
14026 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
14027 /* Remove this if it causes problems for some boards. */
14028 tp
->dma_rwctrl
|= DMA_RWCTRL_USE_MEM_READ_MULT
;
14030 /* On 5700/5701 chips, we need to set this bit.
14031 * Otherwise the chip will issue cacheline transactions
14032 * to streamable DMA memory with not all the byte
14033 * enables turned on. This is an error on several
14034 * RISC PCI controllers, in particular sparc64.
14036 * On 5703/5704 chips, this bit has been reassigned
14037 * a different meaning. In particular, it is used
14038 * on those chips to enable a PCI-X workaround.
14040 tp
->dma_rwctrl
|= DMA_RWCTRL_ASSERT_ALL_BE
;
14043 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
14046 /* Unneeded, already done by tg3_get_invariants. */
14047 tg3_switch_clocks(tp
);
14050 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
14051 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
)
14054 /* It is best to perform DMA test with maximum write burst size
14055 * to expose the 5700/5701 write DMA bug.
14057 saved_dma_rwctrl
= tp
->dma_rwctrl
;
14058 tp
->dma_rwctrl
&= ~DMA_RWCTRL_WRITE_BNDRY_MASK
;
14059 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
14064 for (i
= 0; i
< TEST_BUFFER_SIZE
/ sizeof(u32
); i
++)
14067 /* Send the buffer to the chip. */
14068 ret
= tg3_do_test_dma(tp
, buf
, buf_dma
, TEST_BUFFER_SIZE
, 1);
14070 dev_err(&tp
->pdev
->dev
,
14071 "%s: Buffer write failed. err = %d\n",
14077 /* validate data reached card RAM correctly. */
14078 for (i
= 0; i
< TEST_BUFFER_SIZE
/ sizeof(u32
); i
++) {
14080 tg3_read_mem(tp
, 0x2100 + (i
*4), &val
);
14081 if (le32_to_cpu(val
) != p
[i
]) {
14082 dev_err(&tp
->pdev
->dev
,
14083 "%s: Buffer corrupted on device! "
14084 "(%d != %d)\n", __func__
, val
, i
);
14085 /* ret = -ENODEV here? */
14090 /* Now read it back. */
14091 ret
= tg3_do_test_dma(tp
, buf
, buf_dma
, TEST_BUFFER_SIZE
, 0);
14093 dev_err(&tp
->pdev
->dev
, "%s: Buffer read failed. "
14094 "err = %d\n", __func__
, ret
);
14099 for (i
= 0; i
< TEST_BUFFER_SIZE
/ sizeof(u32
); i
++) {
14103 if ((tp
->dma_rwctrl
& DMA_RWCTRL_WRITE_BNDRY_MASK
) !=
14104 DMA_RWCTRL_WRITE_BNDRY_16
) {
14105 tp
->dma_rwctrl
&= ~DMA_RWCTRL_WRITE_BNDRY_MASK
;
14106 tp
->dma_rwctrl
|= DMA_RWCTRL_WRITE_BNDRY_16
;
14107 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
14110 dev_err(&tp
->pdev
->dev
,
14111 "%s: Buffer corrupted on read back! "
14112 "(%d != %d)\n", __func__
, p
[i
], i
);
14118 if (i
== (TEST_BUFFER_SIZE
/ sizeof(u32
))) {
14124 if ((tp
->dma_rwctrl
& DMA_RWCTRL_WRITE_BNDRY_MASK
) !=
14125 DMA_RWCTRL_WRITE_BNDRY_16
) {
14126 static struct pci_device_id dma_wait_state_chipsets
[] = {
14127 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
,
14128 PCI_DEVICE_ID_APPLE_UNI_N_PCI15
) },
14132 /* DMA test passed without adjusting DMA boundary,
14133 * now look for chipsets that are known to expose the
14134 * DMA bug without failing the test.
14136 if (pci_dev_present(dma_wait_state_chipsets
)) {
14137 tp
->dma_rwctrl
&= ~DMA_RWCTRL_WRITE_BNDRY_MASK
;
14138 tp
->dma_rwctrl
|= DMA_RWCTRL_WRITE_BNDRY_16
;
14140 /* Safe to use the calculated DMA boundary. */
14141 tp
->dma_rwctrl
= saved_dma_rwctrl
;
14144 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
14148 pci_free_consistent(tp
->pdev
, TEST_BUFFER_SIZE
, buf
, buf_dma
);
14153 static void __devinit
tg3_init_link_config(struct tg3
*tp
)
14155 tp
->link_config
.advertising
=
14156 (ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
14157 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
|
14158 ADVERTISED_1000baseT_Half
| ADVERTISED_1000baseT_Full
|
14159 ADVERTISED_Autoneg
| ADVERTISED_MII
);
14160 tp
->link_config
.speed
= SPEED_INVALID
;
14161 tp
->link_config
.duplex
= DUPLEX_INVALID
;
14162 tp
->link_config
.autoneg
= AUTONEG_ENABLE
;
14163 tp
->link_config
.active_speed
= SPEED_INVALID
;
14164 tp
->link_config
.active_duplex
= DUPLEX_INVALID
;
14165 tp
->link_config
.orig_speed
= SPEED_INVALID
;
14166 tp
->link_config
.orig_duplex
= DUPLEX_INVALID
;
14167 tp
->link_config
.orig_autoneg
= AUTONEG_INVALID
;
14170 static void __devinit
tg3_init_bufmgr_config(struct tg3
*tp
)
14172 if (tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
) {
14173 tp
->bufmgr_config
.mbuf_read_dma_low_water
=
14174 DEFAULT_MB_RDMA_LOW_WATER_5705
;
14175 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
14176 DEFAULT_MB_MACRX_LOW_WATER_57765
;
14177 tp
->bufmgr_config
.mbuf_high_water
=
14178 DEFAULT_MB_HIGH_WATER_57765
;
14180 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
=
14181 DEFAULT_MB_RDMA_LOW_WATER_5705
;
14182 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
=
14183 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765
;
14184 tp
->bufmgr_config
.mbuf_high_water_jumbo
=
14185 DEFAULT_MB_HIGH_WATER_JUMBO_57765
;
14186 } else if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
14187 tp
->bufmgr_config
.mbuf_read_dma_low_water
=
14188 DEFAULT_MB_RDMA_LOW_WATER_5705
;
14189 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
14190 DEFAULT_MB_MACRX_LOW_WATER_5705
;
14191 tp
->bufmgr_config
.mbuf_high_water
=
14192 DEFAULT_MB_HIGH_WATER_5705
;
14193 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
14194 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
14195 DEFAULT_MB_MACRX_LOW_WATER_5906
;
14196 tp
->bufmgr_config
.mbuf_high_water
=
14197 DEFAULT_MB_HIGH_WATER_5906
;
14200 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
=
14201 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780
;
14202 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
=
14203 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780
;
14204 tp
->bufmgr_config
.mbuf_high_water_jumbo
=
14205 DEFAULT_MB_HIGH_WATER_JUMBO_5780
;
14207 tp
->bufmgr_config
.mbuf_read_dma_low_water
=
14208 DEFAULT_MB_RDMA_LOW_WATER
;
14209 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
14210 DEFAULT_MB_MACRX_LOW_WATER
;
14211 tp
->bufmgr_config
.mbuf_high_water
=
14212 DEFAULT_MB_HIGH_WATER
;
14214 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
=
14215 DEFAULT_MB_RDMA_LOW_WATER_JUMBO
;
14216 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
=
14217 DEFAULT_MB_MACRX_LOW_WATER_JUMBO
;
14218 tp
->bufmgr_config
.mbuf_high_water_jumbo
=
14219 DEFAULT_MB_HIGH_WATER_JUMBO
;
14222 tp
->bufmgr_config
.dma_low_water
= DEFAULT_DMA_LOW_WATER
;
14223 tp
->bufmgr_config
.dma_high_water
= DEFAULT_DMA_HIGH_WATER
;
14226 static char * __devinit
tg3_phy_string(struct tg3
*tp
)
14228 switch (tp
->phy_id
& TG3_PHY_ID_MASK
) {
14229 case TG3_PHY_ID_BCM5400
: return "5400";
14230 case TG3_PHY_ID_BCM5401
: return "5401";
14231 case TG3_PHY_ID_BCM5411
: return "5411";
14232 case TG3_PHY_ID_BCM5701
: return "5701";
14233 case TG3_PHY_ID_BCM5703
: return "5703";
14234 case TG3_PHY_ID_BCM5704
: return "5704";
14235 case TG3_PHY_ID_BCM5705
: return "5705";
14236 case TG3_PHY_ID_BCM5750
: return "5750";
14237 case TG3_PHY_ID_BCM5752
: return "5752";
14238 case TG3_PHY_ID_BCM5714
: return "5714";
14239 case TG3_PHY_ID_BCM5780
: return "5780";
14240 case TG3_PHY_ID_BCM5755
: return "5755";
14241 case TG3_PHY_ID_BCM5787
: return "5787";
14242 case TG3_PHY_ID_BCM5784
: return "5784";
14243 case TG3_PHY_ID_BCM5756
: return "5722/5756";
14244 case TG3_PHY_ID_BCM5906
: return "5906";
14245 case TG3_PHY_ID_BCM5761
: return "5761";
14246 case TG3_PHY_ID_BCM5718C
: return "5718C";
14247 case TG3_PHY_ID_BCM5718S
: return "5718S";
14248 case TG3_PHY_ID_BCM57765
: return "57765";
14249 case TG3_PHY_ID_BCM5719C
: return "5719C";
14250 case TG3_PHY_ID_BCM8002
: return "8002/serdes";
14251 case 0: return "serdes";
14252 default: return "unknown";
14256 static char * __devinit
tg3_bus_string(struct tg3
*tp
, char *str
)
14258 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
14259 strcpy(str
, "PCI Express");
14261 } else if (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) {
14262 u32 clock_ctrl
= tr32(TG3PCI_CLOCK_CTRL
) & 0x1f;
14264 strcpy(str
, "PCIX:");
14266 if ((clock_ctrl
== 7) ||
14267 ((tr32(GRC_MISC_CFG
) & GRC_MISC_CFG_BOARD_ID_MASK
) ==
14268 GRC_MISC_CFG_BOARD_ID_5704CIOBE
))
14269 strcat(str
, "133MHz");
14270 else if (clock_ctrl
== 0)
14271 strcat(str
, "33MHz");
14272 else if (clock_ctrl
== 2)
14273 strcat(str
, "50MHz");
14274 else if (clock_ctrl
== 4)
14275 strcat(str
, "66MHz");
14276 else if (clock_ctrl
== 6)
14277 strcat(str
, "100MHz");
14279 strcpy(str
, "PCI:");
14280 if (tp
->tg3_flags
& TG3_FLAG_PCI_HIGH_SPEED
)
14281 strcat(str
, "66MHz");
14283 strcat(str
, "33MHz");
14285 if (tp
->tg3_flags
& TG3_FLAG_PCI_32BIT
)
14286 strcat(str
, ":32-bit");
14288 strcat(str
, ":64-bit");
14292 static struct pci_dev
* __devinit
tg3_find_peer(struct tg3
*tp
)
14294 struct pci_dev
*peer
;
14295 unsigned int func
, devnr
= tp
->pdev
->devfn
& ~7;
14297 for (func
= 0; func
< 8; func
++) {
14298 peer
= pci_get_slot(tp
->pdev
->bus
, devnr
| func
);
14299 if (peer
&& peer
!= tp
->pdev
)
14303 /* 5704 can be configured in single-port mode, set peer to
14304 * tp->pdev in that case.
14312 * We don't need to keep the refcount elevated; there's no way
14313 * to remove one half of this device without removing the other
14320 static void __devinit
tg3_init_coal(struct tg3
*tp
)
14322 struct ethtool_coalesce
*ec
= &tp
->coal
;
14324 memset(ec
, 0, sizeof(*ec
));
14325 ec
->cmd
= ETHTOOL_GCOALESCE
;
14326 ec
->rx_coalesce_usecs
= LOW_RXCOL_TICKS
;
14327 ec
->tx_coalesce_usecs
= LOW_TXCOL_TICKS
;
14328 ec
->rx_max_coalesced_frames
= LOW_RXMAX_FRAMES
;
14329 ec
->tx_max_coalesced_frames
= LOW_TXMAX_FRAMES
;
14330 ec
->rx_coalesce_usecs_irq
= DEFAULT_RXCOAL_TICK_INT
;
14331 ec
->tx_coalesce_usecs_irq
= DEFAULT_TXCOAL_TICK_INT
;
14332 ec
->rx_max_coalesced_frames_irq
= DEFAULT_RXCOAL_MAXF_INT
;
14333 ec
->tx_max_coalesced_frames_irq
= DEFAULT_TXCOAL_MAXF_INT
;
14334 ec
->stats_block_coalesce_usecs
= DEFAULT_STAT_COAL_TICKS
;
14336 if (tp
->coalesce_mode
& (HOSTCC_MODE_CLRTICK_RXBD
|
14337 HOSTCC_MODE_CLRTICK_TXBD
)) {
14338 ec
->rx_coalesce_usecs
= LOW_RXCOL_TICKS_CLRTCKS
;
14339 ec
->rx_coalesce_usecs_irq
= DEFAULT_RXCOAL_TICK_INT_CLRTCKS
;
14340 ec
->tx_coalesce_usecs
= LOW_TXCOL_TICKS_CLRTCKS
;
14341 ec
->tx_coalesce_usecs_irq
= DEFAULT_TXCOAL_TICK_INT_CLRTCKS
;
14344 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
14345 ec
->rx_coalesce_usecs_irq
= 0;
14346 ec
->tx_coalesce_usecs_irq
= 0;
14347 ec
->stats_block_coalesce_usecs
= 0;
14351 static const struct net_device_ops tg3_netdev_ops
= {
14352 .ndo_open
= tg3_open
,
14353 .ndo_stop
= tg3_close
,
14354 .ndo_start_xmit
= tg3_start_xmit
,
14355 .ndo_get_stats64
= tg3_get_stats64
,
14356 .ndo_validate_addr
= eth_validate_addr
,
14357 .ndo_set_multicast_list
= tg3_set_rx_mode
,
14358 .ndo_set_mac_address
= tg3_set_mac_addr
,
14359 .ndo_do_ioctl
= tg3_ioctl
,
14360 .ndo_tx_timeout
= tg3_tx_timeout
,
14361 .ndo_change_mtu
= tg3_change_mtu
,
14362 #if TG3_VLAN_TAG_USED
14363 .ndo_vlan_rx_register
= tg3_vlan_rx_register
,
14365 #ifdef CONFIG_NET_POLL_CONTROLLER
14366 .ndo_poll_controller
= tg3_poll_controller
,
14370 static const struct net_device_ops tg3_netdev_ops_dma_bug
= {
14371 .ndo_open
= tg3_open
,
14372 .ndo_stop
= tg3_close
,
14373 .ndo_start_xmit
= tg3_start_xmit_dma_bug
,
14374 .ndo_get_stats64
= tg3_get_stats64
,
14375 .ndo_validate_addr
= eth_validate_addr
,
14376 .ndo_set_multicast_list
= tg3_set_rx_mode
,
14377 .ndo_set_mac_address
= tg3_set_mac_addr
,
14378 .ndo_do_ioctl
= tg3_ioctl
,
14379 .ndo_tx_timeout
= tg3_tx_timeout
,
14380 .ndo_change_mtu
= tg3_change_mtu
,
14381 #if TG3_VLAN_TAG_USED
14382 .ndo_vlan_rx_register
= tg3_vlan_rx_register
,
14384 #ifdef CONFIG_NET_POLL_CONTROLLER
14385 .ndo_poll_controller
= tg3_poll_controller
,
14389 static int __devinit
tg3_init_one(struct pci_dev
*pdev
,
14390 const struct pci_device_id
*ent
)
14392 struct net_device
*dev
;
14394 int i
, err
, pm_cap
;
14395 u32 sndmbx
, rcvmbx
, intmbx
;
14397 u64 dma_mask
, persist_dma_mask
;
14399 printk_once(KERN_INFO
"%s\n", version
);
14401 err
= pci_enable_device(pdev
);
14403 dev_err(&pdev
->dev
, "Cannot enable PCI device, aborting\n");
14407 err
= pci_request_regions(pdev
, DRV_MODULE_NAME
);
14409 dev_err(&pdev
->dev
, "Cannot obtain PCI resources, aborting\n");
14410 goto err_out_disable_pdev
;
14413 pci_set_master(pdev
);
14415 /* Find power-management capability. */
14416 pm_cap
= pci_find_capability(pdev
, PCI_CAP_ID_PM
);
14418 dev_err(&pdev
->dev
,
14419 "Cannot find Power Management capability, aborting\n");
14421 goto err_out_free_res
;
14424 dev
= alloc_etherdev_mq(sizeof(*tp
), TG3_IRQ_MAX_VECS
);
14426 dev_err(&pdev
->dev
, "Etherdev alloc failed, aborting\n");
14428 goto err_out_free_res
;
14431 SET_NETDEV_DEV(dev
, &pdev
->dev
);
14433 #if TG3_VLAN_TAG_USED
14434 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
14437 tp
= netdev_priv(dev
);
14440 tp
->pm_cap
= pm_cap
;
14441 tp
->rx_mode
= TG3_DEF_RX_MODE
;
14442 tp
->tx_mode
= TG3_DEF_TX_MODE
;
14445 tp
->msg_enable
= tg3_debug
;
14447 tp
->msg_enable
= TG3_DEF_MSG_ENABLE
;
14449 /* The word/byte swap controls here control register access byte
14450 * swapping. DMA data byte swapping is controlled in the GRC_MODE
14453 tp
->misc_host_ctrl
=
14454 MISC_HOST_CTRL_MASK_PCI_INT
|
14455 MISC_HOST_CTRL_WORD_SWAP
|
14456 MISC_HOST_CTRL_INDIR_ACCESS
|
14457 MISC_HOST_CTRL_PCISTATE_RW
;
14459 /* The NONFRM (non-frame) byte/word swap controls take effect
14460 * on descriptor entries, anything which isn't packet data.
14462 * The StrongARM chips on the board (one for tx, one for rx)
14463 * are running in big-endian mode.
14465 tp
->grc_mode
= (GRC_MODE_WSWAP_DATA
| GRC_MODE_BSWAP_DATA
|
14466 GRC_MODE_WSWAP_NONFRM_DATA
);
14467 #ifdef __BIG_ENDIAN
14468 tp
->grc_mode
|= GRC_MODE_BSWAP_NONFRM_DATA
;
14470 spin_lock_init(&tp
->lock
);
14471 spin_lock_init(&tp
->indirect_lock
);
14472 INIT_WORK(&tp
->reset_task
, tg3_reset_task
);
14474 tp
->regs
= pci_ioremap_bar(pdev
, BAR_0
);
14476 dev_err(&pdev
->dev
, "Cannot map device registers, aborting\n");
14478 goto err_out_free_dev
;
14481 tg3_init_link_config(tp
);
14483 tp
->rx_pending
= TG3_DEF_RX_RING_PENDING
;
14484 tp
->rx_jumbo_pending
= TG3_DEF_RX_JUMBO_RING_PENDING
;
14486 dev
->ethtool_ops
= &tg3_ethtool_ops
;
14487 dev
->watchdog_timeo
= TG3_TX_TIMEOUT
;
14488 dev
->irq
= pdev
->irq
;
14490 err
= tg3_get_invariants(tp
);
14492 dev_err(&pdev
->dev
,
14493 "Problem fetching invariants of chip, aborting\n");
14494 goto err_out_iounmap
;
14497 if ((tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) &&
14498 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5717
&&
14499 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5719
)
14500 dev
->netdev_ops
= &tg3_netdev_ops
;
14502 dev
->netdev_ops
= &tg3_netdev_ops_dma_bug
;
14505 /* The EPB bridge inside 5714, 5715, and 5780 and any
14506 * device behind the EPB cannot support DMA addresses > 40-bit.
14507 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14508 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14509 * do DMA address check in tg3_start_xmit().
14511 if (tp
->tg3_flags2
& TG3_FLG2_IS_5788
)
14512 persist_dma_mask
= dma_mask
= DMA_BIT_MASK(32);
14513 else if (tp
->tg3_flags
& TG3_FLAG_40BIT_DMA_BUG
) {
14514 persist_dma_mask
= dma_mask
= DMA_BIT_MASK(40);
14515 #ifdef CONFIG_HIGHMEM
14516 dma_mask
= DMA_BIT_MASK(64);
14519 persist_dma_mask
= dma_mask
= DMA_BIT_MASK(64);
14521 /* Configure DMA attributes. */
14522 if (dma_mask
> DMA_BIT_MASK(32)) {
14523 err
= pci_set_dma_mask(pdev
, dma_mask
);
14525 dev
->features
|= NETIF_F_HIGHDMA
;
14526 err
= pci_set_consistent_dma_mask(pdev
,
14529 dev_err(&pdev
->dev
, "Unable to obtain 64 bit "
14530 "DMA for consistent allocations\n");
14531 goto err_out_iounmap
;
14535 if (err
|| dma_mask
== DMA_BIT_MASK(32)) {
14536 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
14538 dev_err(&pdev
->dev
,
14539 "No usable DMA configuration, aborting\n");
14540 goto err_out_iounmap
;
14544 tg3_init_bufmgr_config(tp
);
14546 /* Selectively allow TSO based on operating conditions */
14547 if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO
) ||
14548 (tp
->fw_needed
&& !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)))
14549 tp
->tg3_flags2
|= TG3_FLG2_TSO_CAPABLE
;
14551 tp
->tg3_flags2
&= ~(TG3_FLG2_TSO_CAPABLE
| TG3_FLG2_TSO_BUG
);
14552 tp
->fw_needed
= NULL
;
14555 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
)
14556 tp
->fw_needed
= FIRMWARE_TG3
;
14558 /* TSO is on by default on chips that support hardware TSO.
14559 * Firmware TSO on older chips gives lower performance, so it
14560 * is off by default, but can be enabled using ethtool.
14562 if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO
) &&
14563 (dev
->features
& NETIF_F_IP_CSUM
)) {
14564 dev
->features
|= NETIF_F_TSO
;
14565 vlan_features_add(dev
, NETIF_F_TSO
);
14567 if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO_2
) ||
14568 (tp
->tg3_flags2
& TG3_FLG2_HW_TSO_3
)) {
14569 if (dev
->features
& NETIF_F_IPV6_CSUM
) {
14570 dev
->features
|= NETIF_F_TSO6
;
14571 vlan_features_add(dev
, NETIF_F_TSO6
);
14573 if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO_3
) ||
14574 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
14575 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
14576 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
) ||
14577 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
14578 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
) {
14579 dev
->features
|= NETIF_F_TSO_ECN
;
14580 vlan_features_add(dev
, NETIF_F_TSO_ECN
);
14584 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A1
&&
14585 !(tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) &&
14586 !(tr32(TG3PCI_PCISTATE
) & PCISTATE_BUS_SPEED_HIGH
)) {
14587 tp
->tg3_flags2
|= TG3_FLG2_MAX_RXPEND_64
;
14588 tp
->rx_pending
= 63;
14591 err
= tg3_get_device_address(tp
);
14593 dev_err(&pdev
->dev
,
14594 "Could not obtain valid ethernet address, aborting\n");
14595 goto err_out_iounmap
;
14598 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
14599 tp
->aperegs
= pci_ioremap_bar(pdev
, BAR_2
);
14600 if (!tp
->aperegs
) {
14601 dev_err(&pdev
->dev
,
14602 "Cannot map APE registers, aborting\n");
14604 goto err_out_iounmap
;
14607 tg3_ape_lock_init(tp
);
14609 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)
14610 tg3_read_dash_ver(tp
);
14614 * Reset chip in case UNDI or EFI driver did not shutdown
14615 * DMA self test will enable WDMAC and we'll see (spurious)
14616 * pending DMA on the PCI bus at that point.
14618 if ((tr32(HOSTCC_MODE
) & HOSTCC_MODE_ENABLE
) ||
14619 (tr32(WDMAC_MODE
) & WDMAC_MODE_ENABLE
)) {
14620 tw32(MEMARB_MODE
, MEMARB_MODE_ENABLE
);
14621 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
14624 err
= tg3_test_dma(tp
);
14626 dev_err(&pdev
->dev
, "DMA engine test failed, aborting\n");
14627 goto err_out_apeunmap
;
14630 /* flow control autonegotiation is default behavior */
14631 tp
->tg3_flags
|= TG3_FLAG_PAUSE_AUTONEG
;
14632 tp
->link_config
.flowctrl
= FLOW_CTRL_TX
| FLOW_CTRL_RX
;
14634 intmbx
= MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
;
14635 rcvmbx
= MAILBOX_RCVRET_CON_IDX_0
+ TG3_64BIT_REG_LOW
;
14636 sndmbx
= MAILBOX_SNDHOST_PROD_IDX_0
+ TG3_64BIT_REG_LOW
;
14637 for (i
= 0; i
< tp
->irq_max
; i
++) {
14638 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
14641 tnapi
->tx_pending
= TG3_DEF_TX_RING_PENDING
;
14643 tnapi
->int_mbox
= intmbx
;
14649 tnapi
->consmbox
= rcvmbx
;
14650 tnapi
->prodmbox
= sndmbx
;
14653 tnapi
->coal_now
= HOSTCC_MODE_COAL_VEC1_NOW
<< (i
- 1);
14655 tnapi
->coal_now
= HOSTCC_MODE_NOW
;
14657 if (!(tp
->tg3_flags
& TG3_FLAG_SUPPORT_MSIX
))
14661 * If we support MSIX, we'll be using RSS. If we're using
14662 * RSS, the first vector only handles link interrupts and the
14663 * remaining vectors handle rx and tx interrupts. Reuse the
14664 * mailbox values for the next iteration. The values we setup
14665 * above are still useful for the single vectored mode.
14680 pci_set_drvdata(pdev
, dev
);
14682 err
= register_netdev(dev
);
14684 dev_err(&pdev
->dev
, "Cannot register net device, aborting\n");
14685 goto err_out_apeunmap
;
14688 netdev_info(dev
, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14689 tp
->board_part_number
,
14690 tp
->pci_chip_rev_id
,
14691 tg3_bus_string(tp
, str
),
14694 if (tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
) {
14695 struct phy_device
*phydev
;
14696 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
14698 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14699 phydev
->drv
->name
, dev_name(&phydev
->dev
));
14703 if (tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
)
14704 ethtype
= "10/100Base-TX";
14705 else if (tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
)
14706 ethtype
= "1000Base-SX";
14708 ethtype
= "10/100/1000Base-T";
14710 netdev_info(dev
, "attached PHY is %s (%s Ethernet) "
14711 "(WireSpeed[%d])\n", tg3_phy_string(tp
), ethtype
,
14712 (tp
->phy_flags
& TG3_PHYFLG_NO_ETH_WIRE_SPEED
) == 0);
14715 netdev_info(dev
, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14716 (tp
->tg3_flags
& TG3_FLAG_RX_CHECKSUMS
) != 0,
14717 (tp
->tg3_flags
& TG3_FLAG_USE_LINKCHG_REG
) != 0,
14718 (tp
->phy_flags
& TG3_PHYFLG_USE_MI_INTERRUPT
) != 0,
14719 (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) != 0,
14720 (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) != 0);
14721 netdev_info(dev
, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14723 pdev
->dma_mask
== DMA_BIT_MASK(32) ? 32 :
14724 ((u64
)pdev
->dma_mask
) == DMA_BIT_MASK(40) ? 40 : 64);
14730 iounmap(tp
->aperegs
);
14731 tp
->aperegs
= NULL
;
14744 pci_release_regions(pdev
);
14746 err_out_disable_pdev
:
14747 pci_disable_device(pdev
);
14748 pci_set_drvdata(pdev
, NULL
);
14752 static void __devexit
tg3_remove_one(struct pci_dev
*pdev
)
14754 struct net_device
*dev
= pci_get_drvdata(pdev
);
14757 struct tg3
*tp
= netdev_priv(dev
);
14760 release_firmware(tp
->fw
);
14762 flush_scheduled_work();
14764 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
14769 unregister_netdev(dev
);
14771 iounmap(tp
->aperegs
);
14772 tp
->aperegs
= NULL
;
14779 pci_release_regions(pdev
);
14780 pci_disable_device(pdev
);
14781 pci_set_drvdata(pdev
, NULL
);
14785 static int tg3_suspend(struct pci_dev
*pdev
, pm_message_t state
)
14787 struct net_device
*dev
= pci_get_drvdata(pdev
);
14788 struct tg3
*tp
= netdev_priv(dev
);
14789 pci_power_t target_state
;
14792 /* PCI register 4 needs to be saved whether netif_running() or not.
14793 * MSI address and data need to be saved if using MSI and
14796 pci_save_state(pdev
);
14798 if (!netif_running(dev
))
14801 flush_scheduled_work();
14803 tg3_netif_stop(tp
);
14805 del_timer_sync(&tp
->timer
);
14807 tg3_full_lock(tp
, 1);
14808 tg3_disable_ints(tp
);
14809 tg3_full_unlock(tp
);
14811 netif_device_detach(dev
);
14813 tg3_full_lock(tp
, 0);
14814 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
14815 tp
->tg3_flags
&= ~TG3_FLAG_INIT_COMPLETE
;
14816 tg3_full_unlock(tp
);
14818 target_state
= pdev
->pm_cap
? pci_target_state(pdev
) : PCI_D3hot
;
14820 err
= tg3_set_power_state(tp
, target_state
);
14824 tg3_full_lock(tp
, 0);
14826 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
14827 err2
= tg3_restart_hw(tp
, 1);
14831 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
14832 add_timer(&tp
->timer
);
14834 netif_device_attach(dev
);
14835 tg3_netif_start(tp
);
14838 tg3_full_unlock(tp
);
14847 static int tg3_resume(struct pci_dev
*pdev
)
14849 struct net_device
*dev
= pci_get_drvdata(pdev
);
14850 struct tg3
*tp
= netdev_priv(dev
);
14853 pci_restore_state(tp
->pdev
);
14855 if (!netif_running(dev
))
14858 err
= tg3_set_power_state(tp
, PCI_D0
);
14862 netif_device_attach(dev
);
14864 tg3_full_lock(tp
, 0);
14866 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
14867 err
= tg3_restart_hw(tp
, 1);
14871 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
14872 add_timer(&tp
->timer
);
14874 tg3_netif_start(tp
);
14877 tg3_full_unlock(tp
);
14885 static struct pci_driver tg3_driver
= {
14886 .name
= DRV_MODULE_NAME
,
14887 .id_table
= tg3_pci_tbl
,
14888 .probe
= tg3_init_one
,
14889 .remove
= __devexit_p(tg3_remove_one
),
14890 .suspend
= tg3_suspend
,
14891 .resume
= tg3_resume
14894 static int __init
tg3_init(void)
14896 return pci_register_driver(&tg3_driver
);
14899 static void __exit
tg3_cleanup(void)
14901 pci_unregister_driver(&tg3_driver
);
14904 module_init(tg3_init
);
14905 module_exit(tg3_cleanup
);