2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2010 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
28 #include <linux/init.h>
29 #include <linux/ioport.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/ethtool.h>
35 #include <linux/mii.h>
36 #include <linux/phy.h>
37 #include <linux/brcmphy.h>
38 #include <linux/if_vlan.h>
40 #include <linux/tcp.h>
41 #include <linux/workqueue.h>
42 #include <linux/prefetch.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/firmware.h>
46 #include <net/checksum.h>
49 #include <asm/system.h>
51 #include <asm/byteorder.h>
52 #include <asm/uaccess.h>
55 #include <asm/idprom.h>
62 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
63 #define TG3_VLAN_TAG_USED 1
65 #define TG3_VLAN_TAG_USED 0
70 #define DRV_MODULE_NAME "tg3"
72 #define TG3_MIN_NUM 112
73 #define DRV_MODULE_VERSION \
74 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
75 #define DRV_MODULE_RELDATE "July 11, 2010"
77 #define TG3_DEF_MAC_MODE 0
78 #define TG3_DEF_RX_MODE 0
79 #define TG3_DEF_TX_MODE 0
80 #define TG3_DEF_MSG_ENABLE \
90 /* length of time before we decide the hardware is borked,
91 * and dev->tx_timeout() should be called to fix the problem
93 #define TG3_TX_TIMEOUT (5 * HZ)
95 /* hardware minimum and maximum for a single frame's data payload */
96 #define TG3_MIN_MTU 60
97 #define TG3_MAX_MTU(tp) \
98 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
100 /* These numbers seem to be hard coded in the NIC firmware somehow.
101 * You can't change the ring sizes, but you can change where you place
102 * them in the NIC onboard memory.
104 #define TG3_RX_RING_SIZE 512
105 #define TG3_DEF_RX_RING_PENDING 200
106 #define TG3_RX_JUMBO_RING_SIZE 256
107 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
108 #define TG3_RSS_INDIR_TBL_SIZE 128
110 /* Do not place this n-ring entries value into the tp struct itself,
111 * we really want to expose these constants to GCC so that modulo et
112 * al. operations are done with shifts and masks instead of with
113 * hw multiply/modulo instructions. Another solution would be to
114 * replace things like '% foo' with '& (foo - 1)'.
116 #define TG3_RX_RCB_RING_SIZE(tp) \
117 (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
118 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
120 #define TG3_TX_RING_SIZE 512
121 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
123 #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
125 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
126 TG3_RX_JUMBO_RING_SIZE)
127 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
128 TG3_RX_RCB_RING_SIZE(tp))
129 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
131 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
133 #define TG3_RX_DMA_ALIGN 16
134 #define TG3_RX_HEADROOM ALIGN(VLAN_HLEN, TG3_RX_DMA_ALIGN)
136 #define TG3_DMA_BYTE_ENAB 64
138 #define TG3_RX_STD_DMA_SZ 1536
139 #define TG3_RX_JMB_DMA_SZ 9046
141 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
143 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
144 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
146 #define TG3_RX_STD_BUFF_RING_SIZE \
147 (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
149 #define TG3_RX_JMB_BUFF_RING_SIZE \
150 (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
152 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
153 * that are at least dword aligned when used in PCIX mode. The driver
154 * works around this bug by double copying the packet. This workaround
155 * is built into the normal double copy length check for efficiency.
157 * However, the double copy is only necessary on those architectures
158 * where unaligned memory accesses are inefficient. For those architectures
159 * where unaligned memory accesses incur little penalty, we can reintegrate
160 * the 5701 in the normal rx path. Doing so saves a device structure
161 * dereference by hardcoding the double copy threshold in place.
163 #define TG3_RX_COPY_THRESHOLD 256
164 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
165 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
167 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
170 /* minimum number of free TX descriptors required to wake up TX process */
171 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
173 #define TG3_RAW_IP_ALIGN 2
175 /* number of ETHTOOL_GSTATS u64's */
176 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
178 #define TG3_NUM_TEST 6
180 #define TG3_FW_UPDATE_TIMEOUT_SEC 5
182 #define FIRMWARE_TG3 "tigon/tg3.bin"
183 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
184 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
186 static char version
[] __devinitdata
=
187 DRV_MODULE_NAME
".c:v" DRV_MODULE_VERSION
" (" DRV_MODULE_RELDATE
")";
189 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
190 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
191 MODULE_LICENSE("GPL");
192 MODULE_VERSION(DRV_MODULE_VERSION
);
193 MODULE_FIRMWARE(FIRMWARE_TG3
);
194 MODULE_FIRMWARE(FIRMWARE_TG3TSO
);
195 MODULE_FIRMWARE(FIRMWARE_TG3TSO5
);
197 static int tg3_debug
= -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
198 module_param(tg3_debug
, int, 0);
199 MODULE_PARM_DESC(tg3_debug
, "Tigon3 bitmapped debugging message enable value");
201 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl
) = {
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5700
)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5701
)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702
)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5703
)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5704
)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702FE
)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705
)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705_2
)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705M
)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705M_2
)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702X
)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5703X
)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5704S
)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702A3
)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5703A3
)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5782
)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5788
)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5789
)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5901
)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5901_2
)},
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5704S_2
)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705F
)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5720
)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5721
)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5722
)},
227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5750
)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5751
)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5750M
)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5751M
)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5751F
)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5752
)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5752M
)},
234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5753
)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5753M
)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5753F
)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5754
)},
238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5754M
)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5755
)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5755M
)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5756
)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5786
)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5787
)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5787M
)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5787F
)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5714
)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5714S
)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5715
)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5715S
)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5780
)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5780S
)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5781
)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5906
)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5906M
)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5784
)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5764
)},
257 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5723
)},
258 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5761
)},
259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5761E
)},
260 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5761S
)},
261 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5761SE
)},
262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5785_G
)},
263 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5785_F
)},
264 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57780
)},
265 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57760
)},
266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57790
)},
267 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57788
)},
268 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5717
)},
269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5718
)},
270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5724
)},
271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57781
)},
272 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57785
)},
273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57761
)},
274 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57765
)},
275 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57791
)},
276 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57795
)},
277 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5719
)},
278 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, PCI_DEVICE_ID_SYSKONNECT_9DXX
)},
279 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, PCI_DEVICE_ID_SYSKONNECT_9MXX
)},
280 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC1000
)},
281 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC1001
)},
282 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC1003
)},
283 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC9100
)},
284 {PCI_DEVICE(PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_TIGON3
)},
288 MODULE_DEVICE_TABLE(pci
, tg3_pci_tbl
);
290 static const struct {
291 const char string
[ETH_GSTRING_LEN
];
292 } ethtool_stats_keys
[TG3_NUM_STATS
] = {
295 { "rx_ucast_packets" },
296 { "rx_mcast_packets" },
297 { "rx_bcast_packets" },
299 { "rx_align_errors" },
300 { "rx_xon_pause_rcvd" },
301 { "rx_xoff_pause_rcvd" },
302 { "rx_mac_ctrl_rcvd" },
303 { "rx_xoff_entered" },
304 { "rx_frame_too_long_errors" },
306 { "rx_undersize_packets" },
307 { "rx_in_length_errors" },
308 { "rx_out_length_errors" },
309 { "rx_64_or_less_octet_packets" },
310 { "rx_65_to_127_octet_packets" },
311 { "rx_128_to_255_octet_packets" },
312 { "rx_256_to_511_octet_packets" },
313 { "rx_512_to_1023_octet_packets" },
314 { "rx_1024_to_1522_octet_packets" },
315 { "rx_1523_to_2047_octet_packets" },
316 { "rx_2048_to_4095_octet_packets" },
317 { "rx_4096_to_8191_octet_packets" },
318 { "rx_8192_to_9022_octet_packets" },
325 { "tx_flow_control" },
327 { "tx_single_collisions" },
328 { "tx_mult_collisions" },
330 { "tx_excessive_collisions" },
331 { "tx_late_collisions" },
332 { "tx_collide_2times" },
333 { "tx_collide_3times" },
334 { "tx_collide_4times" },
335 { "tx_collide_5times" },
336 { "tx_collide_6times" },
337 { "tx_collide_7times" },
338 { "tx_collide_8times" },
339 { "tx_collide_9times" },
340 { "tx_collide_10times" },
341 { "tx_collide_11times" },
342 { "tx_collide_12times" },
343 { "tx_collide_13times" },
344 { "tx_collide_14times" },
345 { "tx_collide_15times" },
346 { "tx_ucast_packets" },
347 { "tx_mcast_packets" },
348 { "tx_bcast_packets" },
349 { "tx_carrier_sense_errors" },
353 { "dma_writeq_full" },
354 { "dma_write_prioq_full" },
358 { "rx_threshold_hit" },
360 { "dma_readq_full" },
361 { "dma_read_prioq_full" },
362 { "tx_comp_queue_full" },
364 { "ring_set_send_prod_index" },
365 { "ring_status_update" },
367 { "nic_avoided_irqs" },
368 { "nic_tx_threshold_hit" }
371 static const struct {
372 const char string
[ETH_GSTRING_LEN
];
373 } ethtool_test_keys
[TG3_NUM_TEST
] = {
374 { "nvram test (online) " },
375 { "link test (online) " },
376 { "register test (offline)" },
377 { "memory test (offline)" },
378 { "loopback test (offline)" },
379 { "interrupt test (offline)" },
382 static void tg3_write32(struct tg3
*tp
, u32 off
, u32 val
)
384 writel(val
, tp
->regs
+ off
);
387 static u32
tg3_read32(struct tg3
*tp
, u32 off
)
389 return readl(tp
->regs
+ off
);
392 static void tg3_ape_write32(struct tg3
*tp
, u32 off
, u32 val
)
394 writel(val
, tp
->aperegs
+ off
);
397 static u32
tg3_ape_read32(struct tg3
*tp
, u32 off
)
399 return readl(tp
->aperegs
+ off
);
402 static void tg3_write_indirect_reg32(struct tg3
*tp
, u32 off
, u32 val
)
406 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
407 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
);
408 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, val
);
409 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
412 static void tg3_write_flush_reg32(struct tg3
*tp
, u32 off
, u32 val
)
414 writel(val
, tp
->regs
+ off
);
415 readl(tp
->regs
+ off
);
418 static u32
tg3_read_indirect_reg32(struct tg3
*tp
, u32 off
)
423 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
424 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
);
425 pci_read_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, &val
);
426 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
430 static void tg3_write_indirect_mbox(struct tg3
*tp
, u32 off
, u32 val
)
434 if (off
== (MAILBOX_RCVRET_CON_IDX_0
+ TG3_64BIT_REG_LOW
)) {
435 pci_write_config_dword(tp
->pdev
, TG3PCI_RCV_RET_RING_CON_IDX
+
436 TG3_64BIT_REG_LOW
, val
);
439 if (off
== TG3_RX_STD_PROD_IDX_REG
) {
440 pci_write_config_dword(tp
->pdev
, TG3PCI_STD_RING_PROD_IDX
+
441 TG3_64BIT_REG_LOW
, val
);
445 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
446 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
+ 0x5600);
447 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, val
);
448 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
450 /* In indirect mode when disabling interrupts, we also need
451 * to clear the interrupt bit in the GRC local ctrl register.
453 if ((off
== (MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
)) &&
455 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_LOCAL_CTRL
,
456 tp
->grc_local_ctrl
|GRC_LCLCTRL_CLEARINT
);
460 static u32
tg3_read_indirect_mbox(struct tg3
*tp
, u32 off
)
465 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
466 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
+ 0x5600);
467 pci_read_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, &val
);
468 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
472 /* usec_wait specifies the wait time in usec when writing to certain registers
473 * where it is unsafe to read back the register without some delay.
474 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
475 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
477 static void _tw32_flush(struct tg3
*tp
, u32 off
, u32 val
, u32 usec_wait
)
479 if ((tp
->tg3_flags
& TG3_FLAG_PCIX_TARGET_HWBUG
) ||
480 (tp
->tg3_flags2
& TG3_FLG2_ICH_WORKAROUND
))
481 /* Non-posted methods */
482 tp
->write32(tp
, off
, val
);
485 tg3_write32(tp
, off
, val
);
490 /* Wait again after the read for the posted method to guarantee that
491 * the wait time is met.
497 static inline void tw32_mailbox_flush(struct tg3
*tp
, u32 off
, u32 val
)
499 tp
->write32_mbox(tp
, off
, val
);
500 if (!(tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
) &&
501 !(tp
->tg3_flags2
& TG3_FLG2_ICH_WORKAROUND
))
502 tp
->read32_mbox(tp
, off
);
505 static void tg3_write32_tx_mbox(struct tg3
*tp
, u32 off
, u32 val
)
507 void __iomem
*mbox
= tp
->regs
+ off
;
509 if (tp
->tg3_flags
& TG3_FLAG_TXD_MBOX_HWBUG
)
511 if (tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
)
515 static u32
tg3_read32_mbox_5906(struct tg3
*tp
, u32 off
)
517 return readl(tp
->regs
+ off
+ GRCMBOX_BASE
);
520 static void tg3_write32_mbox_5906(struct tg3
*tp
, u32 off
, u32 val
)
522 writel(val
, tp
->regs
+ off
+ GRCMBOX_BASE
);
525 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
526 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
527 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
528 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
529 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
531 #define tw32(reg, val) tp->write32(tp, reg, val)
532 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
533 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
534 #define tr32(reg) tp->read32(tp, reg)
536 static void tg3_write_mem(struct tg3
*tp
, u32 off
, u32 val
)
540 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) &&
541 (off
>= NIC_SRAM_STATS_BLK
) && (off
< NIC_SRAM_TX_BUFFER_DESC
))
544 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
545 if (tp
->tg3_flags
& TG3_FLAG_SRAM_USE_CONFIG
) {
546 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, off
);
547 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_DATA
, val
);
549 /* Always leave this as zero. */
550 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, 0);
552 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, off
);
553 tw32_f(TG3PCI_MEM_WIN_DATA
, val
);
555 /* Always leave this as zero. */
556 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
558 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
561 static void tg3_read_mem(struct tg3
*tp
, u32 off
, u32
*val
)
565 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) &&
566 (off
>= NIC_SRAM_STATS_BLK
) && (off
< NIC_SRAM_TX_BUFFER_DESC
)) {
571 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
572 if (tp
->tg3_flags
& TG3_FLAG_SRAM_USE_CONFIG
) {
573 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, off
);
574 pci_read_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_DATA
, val
);
576 /* Always leave this as zero. */
577 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, 0);
579 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, off
);
580 *val
= tr32(TG3PCI_MEM_WIN_DATA
);
582 /* Always leave this as zero. */
583 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
585 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
588 static void tg3_ape_lock_init(struct tg3
*tp
)
593 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
)
594 regbase
= TG3_APE_LOCK_GRANT
;
596 regbase
= TG3_APE_PER_LOCK_GRANT
;
598 /* Make sure the driver hasn't any stale locks. */
599 for (i
= 0; i
< 8; i
++)
600 tg3_ape_write32(tp
, regbase
+ 4 * i
, APE_LOCK_GRANT_DRIVER
);
603 static int tg3_ape_lock(struct tg3
*tp
, int locknum
)
607 u32 status
, req
, gnt
;
609 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
))
613 case TG3_APE_LOCK_GRC
:
614 case TG3_APE_LOCK_MEM
:
620 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
) {
621 req
= TG3_APE_LOCK_REQ
;
622 gnt
= TG3_APE_LOCK_GRANT
;
624 req
= TG3_APE_PER_LOCK_REQ
;
625 gnt
= TG3_APE_PER_LOCK_GRANT
;
630 tg3_ape_write32(tp
, req
+ off
, APE_LOCK_REQ_DRIVER
);
632 /* Wait for up to 1 millisecond to acquire lock. */
633 for (i
= 0; i
< 100; i
++) {
634 status
= tg3_ape_read32(tp
, gnt
+ off
);
635 if (status
== APE_LOCK_GRANT_DRIVER
)
640 if (status
!= APE_LOCK_GRANT_DRIVER
) {
641 /* Revoke the lock request. */
642 tg3_ape_write32(tp
, gnt
+ off
,
643 APE_LOCK_GRANT_DRIVER
);
651 static void tg3_ape_unlock(struct tg3
*tp
, int locknum
)
655 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
))
659 case TG3_APE_LOCK_GRC
:
660 case TG3_APE_LOCK_MEM
:
666 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
)
667 gnt
= TG3_APE_LOCK_GRANT
;
669 gnt
= TG3_APE_PER_LOCK_GRANT
;
671 tg3_ape_write32(tp
, gnt
+ 4 * locknum
, APE_LOCK_GRANT_DRIVER
);
674 static void tg3_disable_ints(struct tg3
*tp
)
678 tw32(TG3PCI_MISC_HOST_CTRL
,
679 (tp
->misc_host_ctrl
| MISC_HOST_CTRL_MASK_PCI_INT
));
680 for (i
= 0; i
< tp
->irq_max
; i
++)
681 tw32_mailbox_f(tp
->napi
[i
].int_mbox
, 0x00000001);
684 static void tg3_enable_ints(struct tg3
*tp
)
691 tw32(TG3PCI_MISC_HOST_CTRL
,
692 (tp
->misc_host_ctrl
& ~MISC_HOST_CTRL_MASK_PCI_INT
));
694 tp
->coal_now
= tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
;
695 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
696 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
698 tw32_mailbox_f(tnapi
->int_mbox
, tnapi
->last_tag
<< 24);
699 if (tp
->tg3_flags2
& TG3_FLG2_1SHOT_MSI
)
700 tw32_mailbox_f(tnapi
->int_mbox
, tnapi
->last_tag
<< 24);
702 tp
->coal_now
|= tnapi
->coal_now
;
705 /* Force an initial interrupt */
706 if (!(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) &&
707 (tp
->napi
[0].hw_status
->status
& SD_STATUS_UPDATED
))
708 tw32(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
| GRC_LCLCTRL_SETINT
);
710 tw32(HOSTCC_MODE
, tp
->coal_now
);
712 tp
->coal_now
&= ~(tp
->napi
[0].coal_now
| tp
->napi
[1].coal_now
);
715 static inline unsigned int tg3_has_work(struct tg3_napi
*tnapi
)
717 struct tg3
*tp
= tnapi
->tp
;
718 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
719 unsigned int work_exists
= 0;
721 /* check for phy events */
722 if (!(tp
->tg3_flags
&
723 (TG3_FLAG_USE_LINKCHG_REG
|
724 TG3_FLAG_POLL_SERDES
))) {
725 if (sblk
->status
& SD_STATUS_LINK_CHG
)
728 /* check for RX/TX work to do */
729 if (sblk
->idx
[0].tx_consumer
!= tnapi
->tx_cons
||
730 *(tnapi
->rx_rcb_prod_idx
) != tnapi
->rx_rcb_ptr
)
737 * similar to tg3_enable_ints, but it accurately determines whether there
738 * is new work pending and can return without flushing the PIO write
739 * which reenables interrupts
741 static void tg3_int_reenable(struct tg3_napi
*tnapi
)
743 struct tg3
*tp
= tnapi
->tp
;
745 tw32_mailbox(tnapi
->int_mbox
, tnapi
->last_tag
<< 24);
748 /* When doing tagged status, this work check is unnecessary.
749 * The last_tag we write above tells the chip which piece of
750 * work we've completed.
752 if (!(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) &&
754 tw32(HOSTCC_MODE
, tp
->coalesce_mode
|
755 HOSTCC_MODE_ENABLE
| tnapi
->coal_now
);
758 static void tg3_napi_disable(struct tg3
*tp
)
762 for (i
= tp
->irq_cnt
- 1; i
>= 0; i
--)
763 napi_disable(&tp
->napi
[i
].napi
);
766 static void tg3_napi_enable(struct tg3
*tp
)
770 for (i
= 0; i
< tp
->irq_cnt
; i
++)
771 napi_enable(&tp
->napi
[i
].napi
);
774 static inline void tg3_netif_stop(struct tg3
*tp
)
776 tp
->dev
->trans_start
= jiffies
; /* prevent tx timeout */
777 tg3_napi_disable(tp
);
778 netif_tx_disable(tp
->dev
);
781 static inline void tg3_netif_start(struct tg3
*tp
)
783 /* NOTE: unconditional netif_tx_wake_all_queues is only
784 * appropriate so long as all callers are assured to
785 * have free tx slots (such as after tg3_init_hw)
787 netif_tx_wake_all_queues(tp
->dev
);
790 tp
->napi
[0].hw_status
->status
|= SD_STATUS_UPDATED
;
794 static void tg3_switch_clocks(struct tg3
*tp
)
799 if ((tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) ||
800 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
803 clock_ctrl
= tr32(TG3PCI_CLOCK_CTRL
);
805 orig_clock_ctrl
= clock_ctrl
;
806 clock_ctrl
&= (CLOCK_CTRL_FORCE_CLKRUN
|
807 CLOCK_CTRL_CLKRUN_OENABLE
|
809 tp
->pci_clock_ctrl
= clock_ctrl
;
811 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
812 if (orig_clock_ctrl
& CLOCK_CTRL_625_CORE
) {
813 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
814 clock_ctrl
| CLOCK_CTRL_625_CORE
, 40);
816 } else if ((orig_clock_ctrl
& CLOCK_CTRL_44MHZ_CORE
) != 0) {
817 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
819 (CLOCK_CTRL_44MHZ_CORE
| CLOCK_CTRL_ALTCLK
),
821 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
822 clock_ctrl
| (CLOCK_CTRL_ALTCLK
),
825 tw32_wait_f(TG3PCI_CLOCK_CTRL
, clock_ctrl
, 40);
828 #define PHY_BUSY_LOOPS 5000
830 static int tg3_readphy(struct tg3
*tp
, int reg
, u32
*val
)
836 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
838 (tp
->mi_mode
& ~MAC_MI_MODE_AUTO_POLL
));
844 frame_val
= ((tp
->phy_addr
<< MI_COM_PHY_ADDR_SHIFT
) &
845 MI_COM_PHY_ADDR_MASK
);
846 frame_val
|= ((reg
<< MI_COM_REG_ADDR_SHIFT
) &
847 MI_COM_REG_ADDR_MASK
);
848 frame_val
|= (MI_COM_CMD_READ
| MI_COM_START
);
850 tw32_f(MAC_MI_COM
, frame_val
);
852 loops
= PHY_BUSY_LOOPS
;
855 frame_val
= tr32(MAC_MI_COM
);
857 if ((frame_val
& MI_COM_BUSY
) == 0) {
859 frame_val
= tr32(MAC_MI_COM
);
867 *val
= frame_val
& MI_COM_DATA_MASK
;
871 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
872 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
879 static int tg3_writephy(struct tg3
*tp
, int reg
, u32 val
)
885 if ((tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
) &&
886 (reg
== MII_TG3_CTRL
|| reg
== MII_TG3_AUX_CTRL
))
889 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
891 (tp
->mi_mode
& ~MAC_MI_MODE_AUTO_POLL
));
895 frame_val
= ((tp
->phy_addr
<< MI_COM_PHY_ADDR_SHIFT
) &
896 MI_COM_PHY_ADDR_MASK
);
897 frame_val
|= ((reg
<< MI_COM_REG_ADDR_SHIFT
) &
898 MI_COM_REG_ADDR_MASK
);
899 frame_val
|= (val
& MI_COM_DATA_MASK
);
900 frame_val
|= (MI_COM_CMD_WRITE
| MI_COM_START
);
902 tw32_f(MAC_MI_COM
, frame_val
);
904 loops
= PHY_BUSY_LOOPS
;
907 frame_val
= tr32(MAC_MI_COM
);
908 if ((frame_val
& MI_COM_BUSY
) == 0) {
910 frame_val
= tr32(MAC_MI_COM
);
920 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
921 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
928 static int tg3_bmcr_reset(struct tg3
*tp
)
933 /* OK, reset it, and poll the BMCR_RESET bit until it
934 * clears or we time out.
936 phy_control
= BMCR_RESET
;
937 err
= tg3_writephy(tp
, MII_BMCR
, phy_control
);
943 err
= tg3_readphy(tp
, MII_BMCR
, &phy_control
);
947 if ((phy_control
& BMCR_RESET
) == 0) {
959 static int tg3_mdio_read(struct mii_bus
*bp
, int mii_id
, int reg
)
961 struct tg3
*tp
= bp
->priv
;
964 spin_lock_bh(&tp
->lock
);
966 if (tg3_readphy(tp
, reg
, &val
))
969 spin_unlock_bh(&tp
->lock
);
974 static int tg3_mdio_write(struct mii_bus
*bp
, int mii_id
, int reg
, u16 val
)
976 struct tg3
*tp
= bp
->priv
;
979 spin_lock_bh(&tp
->lock
);
981 if (tg3_writephy(tp
, reg
, val
))
984 spin_unlock_bh(&tp
->lock
);
989 static int tg3_mdio_reset(struct mii_bus
*bp
)
994 static void tg3_mdio_config_5785(struct tg3
*tp
)
997 struct phy_device
*phydev
;
999 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
1000 switch (phydev
->drv
->phy_id
& phydev
->drv
->phy_id_mask
) {
1001 case PHY_ID_BCM50610
:
1002 case PHY_ID_BCM50610M
:
1003 val
= MAC_PHYCFG2_50610_LED_MODES
;
1005 case PHY_ID_BCMAC131
:
1006 val
= MAC_PHYCFG2_AC131_LED_MODES
;
1008 case PHY_ID_RTL8211C
:
1009 val
= MAC_PHYCFG2_RTL8211C_LED_MODES
;
1011 case PHY_ID_RTL8201E
:
1012 val
= MAC_PHYCFG2_RTL8201E_LED_MODES
;
1018 if (phydev
->interface
!= PHY_INTERFACE_MODE_RGMII
) {
1019 tw32(MAC_PHYCFG2
, val
);
1021 val
= tr32(MAC_PHYCFG1
);
1022 val
&= ~(MAC_PHYCFG1_RGMII_INT
|
1023 MAC_PHYCFG1_RXCLK_TO_MASK
| MAC_PHYCFG1_TXCLK_TO_MASK
);
1024 val
|= MAC_PHYCFG1_RXCLK_TIMEOUT
| MAC_PHYCFG1_TXCLK_TIMEOUT
;
1025 tw32(MAC_PHYCFG1
, val
);
1030 if (!(tp
->tg3_flags3
& TG3_FLG3_RGMII_INBAND_DISABLE
))
1031 val
|= MAC_PHYCFG2_EMODE_MASK_MASK
|
1032 MAC_PHYCFG2_FMODE_MASK_MASK
|
1033 MAC_PHYCFG2_GMODE_MASK_MASK
|
1034 MAC_PHYCFG2_ACT_MASK_MASK
|
1035 MAC_PHYCFG2_QUAL_MASK_MASK
|
1036 MAC_PHYCFG2_INBAND_ENABLE
;
1038 tw32(MAC_PHYCFG2
, val
);
1040 val
= tr32(MAC_PHYCFG1
);
1041 val
&= ~(MAC_PHYCFG1_RXCLK_TO_MASK
| MAC_PHYCFG1_TXCLK_TO_MASK
|
1042 MAC_PHYCFG1_RGMII_EXT_RX_DEC
| MAC_PHYCFG1_RGMII_SND_STAT_EN
);
1043 if (!(tp
->tg3_flags3
& TG3_FLG3_RGMII_INBAND_DISABLE
)) {
1044 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_RX_EN
)
1045 val
|= MAC_PHYCFG1_RGMII_EXT_RX_DEC
;
1046 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_TX_EN
)
1047 val
|= MAC_PHYCFG1_RGMII_SND_STAT_EN
;
1049 val
|= MAC_PHYCFG1_RXCLK_TIMEOUT
| MAC_PHYCFG1_TXCLK_TIMEOUT
|
1050 MAC_PHYCFG1_RGMII_INT
| MAC_PHYCFG1_TXC_DRV
;
1051 tw32(MAC_PHYCFG1
, val
);
1053 val
= tr32(MAC_EXT_RGMII_MODE
);
1054 val
&= ~(MAC_RGMII_MODE_RX_INT_B
|
1055 MAC_RGMII_MODE_RX_QUALITY
|
1056 MAC_RGMII_MODE_RX_ACTIVITY
|
1057 MAC_RGMII_MODE_RX_ENG_DET
|
1058 MAC_RGMII_MODE_TX_ENABLE
|
1059 MAC_RGMII_MODE_TX_LOWPWR
|
1060 MAC_RGMII_MODE_TX_RESET
);
1061 if (!(tp
->tg3_flags3
& TG3_FLG3_RGMII_INBAND_DISABLE
)) {
1062 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_RX_EN
)
1063 val
|= MAC_RGMII_MODE_RX_INT_B
|
1064 MAC_RGMII_MODE_RX_QUALITY
|
1065 MAC_RGMII_MODE_RX_ACTIVITY
|
1066 MAC_RGMII_MODE_RX_ENG_DET
;
1067 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_TX_EN
)
1068 val
|= MAC_RGMII_MODE_TX_ENABLE
|
1069 MAC_RGMII_MODE_TX_LOWPWR
|
1070 MAC_RGMII_MODE_TX_RESET
;
1072 tw32(MAC_EXT_RGMII_MODE
, val
);
1075 static void tg3_mdio_start(struct tg3
*tp
)
1077 tp
->mi_mode
&= ~MAC_MI_MODE_AUTO_POLL
;
1078 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
1081 if ((tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_INITED
) &&
1082 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
1083 tg3_mdio_config_5785(tp
);
1086 static int tg3_mdio_init(struct tg3
*tp
)
1090 struct phy_device
*phydev
;
1092 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
1093 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
) {
1096 tp
->phy_addr
= PCI_FUNC(tp
->pdev
->devfn
) + 1;
1098 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5717_A0
)
1099 is_serdes
= tr32(SG_DIG_STATUS
) & SG_DIG_IS_SERDES
;
1101 is_serdes
= tr32(TG3_CPMU_PHY_STRAP
) &
1102 TG3_CPMU_PHY_STRAP_IS_SERDES
;
1106 tp
->phy_addr
= TG3_PHY_MII_ADDR
;
1110 if (!(tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) ||
1111 (tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_INITED
))
1114 tp
->mdio_bus
= mdiobus_alloc();
1115 if (tp
->mdio_bus
== NULL
)
1118 tp
->mdio_bus
->name
= "tg3 mdio bus";
1119 snprintf(tp
->mdio_bus
->id
, MII_BUS_ID_SIZE
, "%x",
1120 (tp
->pdev
->bus
->number
<< 8) | tp
->pdev
->devfn
);
1121 tp
->mdio_bus
->priv
= tp
;
1122 tp
->mdio_bus
->parent
= &tp
->pdev
->dev
;
1123 tp
->mdio_bus
->read
= &tg3_mdio_read
;
1124 tp
->mdio_bus
->write
= &tg3_mdio_write
;
1125 tp
->mdio_bus
->reset
= &tg3_mdio_reset
;
1126 tp
->mdio_bus
->phy_mask
= ~(1 << TG3_PHY_MII_ADDR
);
1127 tp
->mdio_bus
->irq
= &tp
->mdio_irq
[0];
1129 for (i
= 0; i
< PHY_MAX_ADDR
; i
++)
1130 tp
->mdio_bus
->irq
[i
] = PHY_POLL
;
1132 /* The bus registration will look for all the PHYs on the mdio bus.
1133 * Unfortunately, it does not ensure the PHY is powered up before
1134 * accessing the PHY ID registers. A chip reset is the
1135 * quickest way to bring the device back to an operational state..
1137 if (tg3_readphy(tp
, MII_BMCR
, ®
) || (reg
& BMCR_PDOWN
))
1140 i
= mdiobus_register(tp
->mdio_bus
);
1142 dev_warn(&tp
->pdev
->dev
, "mdiobus_reg failed (0x%x)\n", i
);
1143 mdiobus_free(tp
->mdio_bus
);
1147 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
1149 if (!phydev
|| !phydev
->drv
) {
1150 dev_warn(&tp
->pdev
->dev
, "No PHY devices\n");
1151 mdiobus_unregister(tp
->mdio_bus
);
1152 mdiobus_free(tp
->mdio_bus
);
1156 switch (phydev
->drv
->phy_id
& phydev
->drv
->phy_id_mask
) {
1157 case PHY_ID_BCM57780
:
1158 phydev
->interface
= PHY_INTERFACE_MODE_GMII
;
1159 phydev
->dev_flags
|= PHY_BRCM_AUTO_PWRDWN_ENABLE
;
1161 case PHY_ID_BCM50610
:
1162 case PHY_ID_BCM50610M
:
1163 phydev
->dev_flags
|= PHY_BRCM_CLEAR_RGMII_MODE
|
1164 PHY_BRCM_RX_REFCLK_UNUSED
|
1165 PHY_BRCM_DIS_TXCRXC_NOENRGY
|
1166 PHY_BRCM_AUTO_PWRDWN_ENABLE
;
1167 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_INBAND_DISABLE
)
1168 phydev
->dev_flags
|= PHY_BRCM_STD_IBND_DISABLE
;
1169 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_RX_EN
)
1170 phydev
->dev_flags
|= PHY_BRCM_EXT_IBND_RX_ENABLE
;
1171 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_TX_EN
)
1172 phydev
->dev_flags
|= PHY_BRCM_EXT_IBND_TX_ENABLE
;
1174 case PHY_ID_RTL8211C
:
1175 phydev
->interface
= PHY_INTERFACE_MODE_RGMII
;
1177 case PHY_ID_RTL8201E
:
1178 case PHY_ID_BCMAC131
:
1179 phydev
->interface
= PHY_INTERFACE_MODE_MII
;
1180 phydev
->dev_flags
|= PHY_BRCM_AUTO_PWRDWN_ENABLE
;
1181 tp
->tg3_flags3
|= TG3_FLG3_PHY_IS_FET
;
1185 tp
->tg3_flags3
|= TG3_FLG3_MDIOBUS_INITED
;
1187 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
1188 tg3_mdio_config_5785(tp
);
1193 static void tg3_mdio_fini(struct tg3
*tp
)
1195 if (tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_INITED
) {
1196 tp
->tg3_flags3
&= ~TG3_FLG3_MDIOBUS_INITED
;
1197 mdiobus_unregister(tp
->mdio_bus
);
1198 mdiobus_free(tp
->mdio_bus
);
1202 /* tp->lock is held. */
1203 static inline void tg3_generate_fw_event(struct tg3
*tp
)
1207 val
= tr32(GRC_RX_CPU_EVENT
);
1208 val
|= GRC_RX_CPU_DRIVER_EVENT
;
1209 tw32_f(GRC_RX_CPU_EVENT
, val
);
1211 tp
->last_event_jiffies
= jiffies
;
1214 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1216 /* tp->lock is held. */
1217 static void tg3_wait_for_event_ack(struct tg3
*tp
)
1220 unsigned int delay_cnt
;
1223 /* If enough time has passed, no wait is necessary. */
1224 time_remain
= (long)(tp
->last_event_jiffies
+ 1 +
1225 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC
)) -
1227 if (time_remain
< 0)
1230 /* Check if we can shorten the wait time. */
1231 delay_cnt
= jiffies_to_usecs(time_remain
);
1232 if (delay_cnt
> TG3_FW_EVENT_TIMEOUT_USEC
)
1233 delay_cnt
= TG3_FW_EVENT_TIMEOUT_USEC
;
1234 delay_cnt
= (delay_cnt
>> 3) + 1;
1236 for (i
= 0; i
< delay_cnt
; i
++) {
1237 if (!(tr32(GRC_RX_CPU_EVENT
) & GRC_RX_CPU_DRIVER_EVENT
))
1243 /* tp->lock is held. */
1244 static void tg3_ump_link_report(struct tg3
*tp
)
1249 if (!(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) ||
1250 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
1253 tg3_wait_for_event_ack(tp
);
1255 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_MBOX
, FWCMD_NICDRV_LINK_UPDATE
);
1257 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_LEN_MBOX
, 14);
1260 if (!tg3_readphy(tp
, MII_BMCR
, ®
))
1262 if (!tg3_readphy(tp
, MII_BMSR
, ®
))
1263 val
|= (reg
& 0xffff);
1264 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
, val
);
1267 if (!tg3_readphy(tp
, MII_ADVERTISE
, ®
))
1269 if (!tg3_readphy(tp
, MII_LPA
, ®
))
1270 val
|= (reg
& 0xffff);
1271 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
+ 4, val
);
1274 if (!(tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
)) {
1275 if (!tg3_readphy(tp
, MII_CTRL1000
, ®
))
1277 if (!tg3_readphy(tp
, MII_STAT1000
, ®
))
1278 val
|= (reg
& 0xffff);
1280 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
+ 8, val
);
1282 if (!tg3_readphy(tp
, MII_PHYADDR
, ®
))
1286 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
+ 12, val
);
1288 tg3_generate_fw_event(tp
);
1291 static void tg3_link_report(struct tg3
*tp
)
1293 if (!netif_carrier_ok(tp
->dev
)) {
1294 netif_info(tp
, link
, tp
->dev
, "Link is down\n");
1295 tg3_ump_link_report(tp
);
1296 } else if (netif_msg_link(tp
)) {
1297 netdev_info(tp
->dev
, "Link is up at %d Mbps, %s duplex\n",
1298 (tp
->link_config
.active_speed
== SPEED_1000
?
1300 (tp
->link_config
.active_speed
== SPEED_100
?
1302 (tp
->link_config
.active_duplex
== DUPLEX_FULL
?
1305 netdev_info(tp
->dev
, "Flow control is %s for TX and %s for RX\n",
1306 (tp
->link_config
.active_flowctrl
& FLOW_CTRL_TX
) ?
1308 (tp
->link_config
.active_flowctrl
& FLOW_CTRL_RX
) ?
1310 tg3_ump_link_report(tp
);
1314 static u16
tg3_advert_flowctrl_1000T(u8 flow_ctrl
)
1318 if ((flow_ctrl
& FLOW_CTRL_TX
) && (flow_ctrl
& FLOW_CTRL_RX
))
1319 miireg
= ADVERTISE_PAUSE_CAP
;
1320 else if (flow_ctrl
& FLOW_CTRL_TX
)
1321 miireg
= ADVERTISE_PAUSE_ASYM
;
1322 else if (flow_ctrl
& FLOW_CTRL_RX
)
1323 miireg
= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
1330 static u16
tg3_advert_flowctrl_1000X(u8 flow_ctrl
)
1334 if ((flow_ctrl
& FLOW_CTRL_TX
) && (flow_ctrl
& FLOW_CTRL_RX
))
1335 miireg
= ADVERTISE_1000XPAUSE
;
1336 else if (flow_ctrl
& FLOW_CTRL_TX
)
1337 miireg
= ADVERTISE_1000XPSE_ASYM
;
1338 else if (flow_ctrl
& FLOW_CTRL_RX
)
1339 miireg
= ADVERTISE_1000XPAUSE
| ADVERTISE_1000XPSE_ASYM
;
1346 static u8
tg3_resolve_flowctrl_1000X(u16 lcladv
, u16 rmtadv
)
1350 if (lcladv
& ADVERTISE_1000XPAUSE
) {
1351 if (lcladv
& ADVERTISE_1000XPSE_ASYM
) {
1352 if (rmtadv
& LPA_1000XPAUSE
)
1353 cap
= FLOW_CTRL_TX
| FLOW_CTRL_RX
;
1354 else if (rmtadv
& LPA_1000XPAUSE_ASYM
)
1357 if (rmtadv
& LPA_1000XPAUSE
)
1358 cap
= FLOW_CTRL_TX
| FLOW_CTRL_RX
;
1360 } else if (lcladv
& ADVERTISE_1000XPSE_ASYM
) {
1361 if ((rmtadv
& LPA_1000XPAUSE
) && (rmtadv
& LPA_1000XPAUSE_ASYM
))
1368 static void tg3_setup_flow_control(struct tg3
*tp
, u32 lcladv
, u32 rmtadv
)
1372 u32 old_rx_mode
= tp
->rx_mode
;
1373 u32 old_tx_mode
= tp
->tx_mode
;
1375 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
)
1376 autoneg
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
]->autoneg
;
1378 autoneg
= tp
->link_config
.autoneg
;
1380 if (autoneg
== AUTONEG_ENABLE
&&
1381 (tp
->tg3_flags
& TG3_FLAG_PAUSE_AUTONEG
)) {
1382 if (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
)
1383 flowctrl
= tg3_resolve_flowctrl_1000X(lcladv
, rmtadv
);
1385 flowctrl
= mii_resolve_flowctrl_fdx(lcladv
, rmtadv
);
1387 flowctrl
= tp
->link_config
.flowctrl
;
1389 tp
->link_config
.active_flowctrl
= flowctrl
;
1391 if (flowctrl
& FLOW_CTRL_RX
)
1392 tp
->rx_mode
|= RX_MODE_FLOW_CTRL_ENABLE
;
1394 tp
->rx_mode
&= ~RX_MODE_FLOW_CTRL_ENABLE
;
1396 if (old_rx_mode
!= tp
->rx_mode
)
1397 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
1399 if (flowctrl
& FLOW_CTRL_TX
)
1400 tp
->tx_mode
|= TX_MODE_FLOW_CTRL_ENABLE
;
1402 tp
->tx_mode
&= ~TX_MODE_FLOW_CTRL_ENABLE
;
1404 if (old_tx_mode
!= tp
->tx_mode
)
1405 tw32_f(MAC_TX_MODE
, tp
->tx_mode
);
1408 static void tg3_adjust_link(struct net_device
*dev
)
1410 u8 oldflowctrl
, linkmesg
= 0;
1411 u32 mac_mode
, lcl_adv
, rmt_adv
;
1412 struct tg3
*tp
= netdev_priv(dev
);
1413 struct phy_device
*phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
1415 spin_lock_bh(&tp
->lock
);
1417 mac_mode
= tp
->mac_mode
& ~(MAC_MODE_PORT_MODE_MASK
|
1418 MAC_MODE_HALF_DUPLEX
);
1420 oldflowctrl
= tp
->link_config
.active_flowctrl
;
1426 if (phydev
->speed
== SPEED_100
|| phydev
->speed
== SPEED_10
)
1427 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
1428 else if (phydev
->speed
== SPEED_1000
||
1429 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5785
)
1430 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
1432 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
1434 if (phydev
->duplex
== DUPLEX_HALF
)
1435 mac_mode
|= MAC_MODE_HALF_DUPLEX
;
1437 lcl_adv
= tg3_advert_flowctrl_1000T(
1438 tp
->link_config
.flowctrl
);
1441 rmt_adv
= LPA_PAUSE_CAP
;
1442 if (phydev
->asym_pause
)
1443 rmt_adv
|= LPA_PAUSE_ASYM
;
1446 tg3_setup_flow_control(tp
, lcl_adv
, rmt_adv
);
1448 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
1450 if (mac_mode
!= tp
->mac_mode
) {
1451 tp
->mac_mode
= mac_mode
;
1452 tw32_f(MAC_MODE
, tp
->mac_mode
);
1456 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
) {
1457 if (phydev
->speed
== SPEED_10
)
1459 MAC_MI_STAT_10MBPS_MODE
|
1460 MAC_MI_STAT_LNKSTAT_ATTN_ENAB
);
1462 tw32(MAC_MI_STAT
, MAC_MI_STAT_LNKSTAT_ATTN_ENAB
);
1465 if (phydev
->speed
== SPEED_1000
&& phydev
->duplex
== DUPLEX_HALF
)
1466 tw32(MAC_TX_LENGTHS
,
1467 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
1468 (6 << TX_LENGTHS_IPG_SHIFT
) |
1469 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT
)));
1471 tw32(MAC_TX_LENGTHS
,
1472 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
1473 (6 << TX_LENGTHS_IPG_SHIFT
) |
1474 (32 << TX_LENGTHS_SLOT_TIME_SHIFT
)));
1476 if ((phydev
->link
&& tp
->link_config
.active_speed
== SPEED_INVALID
) ||
1477 (!phydev
->link
&& tp
->link_config
.active_speed
!= SPEED_INVALID
) ||
1478 phydev
->speed
!= tp
->link_config
.active_speed
||
1479 phydev
->duplex
!= tp
->link_config
.active_duplex
||
1480 oldflowctrl
!= tp
->link_config
.active_flowctrl
)
1483 tp
->link_config
.active_speed
= phydev
->speed
;
1484 tp
->link_config
.active_duplex
= phydev
->duplex
;
1486 spin_unlock_bh(&tp
->lock
);
1489 tg3_link_report(tp
);
1492 static int tg3_phy_init(struct tg3
*tp
)
1494 struct phy_device
*phydev
;
1496 if (tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
)
1499 /* Bring the PHY back to a known state. */
1502 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
1504 /* Attach the MAC to the PHY. */
1505 phydev
= phy_connect(tp
->dev
, dev_name(&phydev
->dev
), tg3_adjust_link
,
1506 phydev
->dev_flags
, phydev
->interface
);
1507 if (IS_ERR(phydev
)) {
1508 dev_err(&tp
->pdev
->dev
, "Could not attach to PHY\n");
1509 return PTR_ERR(phydev
);
1512 /* Mask with MAC supported features. */
1513 switch (phydev
->interface
) {
1514 case PHY_INTERFACE_MODE_GMII
:
1515 case PHY_INTERFACE_MODE_RGMII
:
1516 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)) {
1517 phydev
->supported
&= (PHY_GBIT_FEATURES
|
1519 SUPPORTED_Asym_Pause
);
1523 case PHY_INTERFACE_MODE_MII
:
1524 phydev
->supported
&= (PHY_BASIC_FEATURES
|
1526 SUPPORTED_Asym_Pause
);
1529 phy_disconnect(tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
]);
1533 tp
->tg3_flags3
|= TG3_FLG3_PHY_CONNECTED
;
1535 phydev
->advertising
= phydev
->supported
;
1540 static void tg3_phy_start(struct tg3
*tp
)
1542 struct phy_device
*phydev
;
1544 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
1547 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
1549 if (tp
->link_config
.phy_is_low_power
) {
1550 tp
->link_config
.phy_is_low_power
= 0;
1551 phydev
->speed
= tp
->link_config
.orig_speed
;
1552 phydev
->duplex
= tp
->link_config
.orig_duplex
;
1553 phydev
->autoneg
= tp
->link_config
.orig_autoneg
;
1554 phydev
->advertising
= tp
->link_config
.orig_advertising
;
1559 phy_start_aneg(phydev
);
1562 static void tg3_phy_stop(struct tg3
*tp
)
1564 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
1567 phy_stop(tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
]);
1570 static void tg3_phy_fini(struct tg3
*tp
)
1572 if (tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
) {
1573 phy_disconnect(tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
]);
1574 tp
->tg3_flags3
&= ~TG3_FLG3_PHY_CONNECTED
;
1578 static void tg3_phydsp_write(struct tg3
*tp
, u32 reg
, u32 val
)
1580 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, reg
);
1581 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, val
);
1584 static void tg3_phy_fet_toggle_apd(struct tg3
*tp
, bool enable
)
1588 if (!tg3_readphy(tp
, MII_TG3_FET_TEST
, &phytest
)) {
1591 tg3_writephy(tp
, MII_TG3_FET_TEST
,
1592 phytest
| MII_TG3_FET_SHADOW_EN
);
1593 if (!tg3_readphy(tp
, MII_TG3_FET_SHDW_AUXSTAT2
, &phy
)) {
1595 phy
|= MII_TG3_FET_SHDW_AUXSTAT2_APD
;
1597 phy
&= ~MII_TG3_FET_SHDW_AUXSTAT2_APD
;
1598 tg3_writephy(tp
, MII_TG3_FET_SHDW_AUXSTAT2
, phy
);
1600 tg3_writephy(tp
, MII_TG3_FET_TEST
, phytest
);
1604 static void tg3_phy_toggle_apd(struct tg3
*tp
, bool enable
)
1608 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) ||
1609 ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
1610 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
) &&
1611 (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
)))
1614 if (tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
) {
1615 tg3_phy_fet_toggle_apd(tp
, enable
);
1619 reg
= MII_TG3_MISC_SHDW_WREN
|
1620 MII_TG3_MISC_SHDW_SCR5_SEL
|
1621 MII_TG3_MISC_SHDW_SCR5_LPED
|
1622 MII_TG3_MISC_SHDW_SCR5_DLPTLM
|
1623 MII_TG3_MISC_SHDW_SCR5_SDTL
|
1624 MII_TG3_MISC_SHDW_SCR5_C125OE
;
1625 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5784
|| !enable
)
1626 reg
|= MII_TG3_MISC_SHDW_SCR5_DLLAPD
;
1628 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, reg
);
1631 reg
= MII_TG3_MISC_SHDW_WREN
|
1632 MII_TG3_MISC_SHDW_APD_SEL
|
1633 MII_TG3_MISC_SHDW_APD_WKTM_84MS
;
1635 reg
|= MII_TG3_MISC_SHDW_APD_ENABLE
;
1637 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, reg
);
1640 static void tg3_phy_toggle_automdix(struct tg3
*tp
, int enable
)
1644 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) ||
1645 (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
))
1648 if (tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
) {
1651 if (!tg3_readphy(tp
, MII_TG3_FET_TEST
, &ephy
)) {
1652 u32 reg
= MII_TG3_FET_SHDW_MISCCTRL
;
1654 tg3_writephy(tp
, MII_TG3_FET_TEST
,
1655 ephy
| MII_TG3_FET_SHADOW_EN
);
1656 if (!tg3_readphy(tp
, reg
, &phy
)) {
1658 phy
|= MII_TG3_FET_SHDW_MISCCTRL_MDIX
;
1660 phy
&= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX
;
1661 tg3_writephy(tp
, reg
, phy
);
1663 tg3_writephy(tp
, MII_TG3_FET_TEST
, ephy
);
1666 phy
= MII_TG3_AUXCTL_MISC_RDSEL_MISC
|
1667 MII_TG3_AUXCTL_SHDWSEL_MISC
;
1668 if (!tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy
) &&
1669 !tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &phy
)) {
1671 phy
|= MII_TG3_AUXCTL_MISC_FORCE_AMDIX
;
1673 phy
&= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX
;
1674 phy
|= MII_TG3_AUXCTL_MISC_WREN
;
1675 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy
);
1680 static void tg3_phy_set_wirespeed(struct tg3
*tp
)
1684 if (tp
->tg3_flags2
& TG3_FLG2_NO_ETH_WIRE_SPEED
)
1687 if (!tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x7007) &&
1688 !tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &val
))
1689 tg3_writephy(tp
, MII_TG3_AUX_CTRL
,
1690 (val
| (1 << 15) | (1 << 4)));
1693 static void tg3_phy_apply_otp(struct tg3
*tp
)
1702 /* Enable SM_DSP clock and tx 6dB coding. */
1703 phy
= MII_TG3_AUXCTL_SHDWSEL_AUXCTL
|
1704 MII_TG3_AUXCTL_ACTL_SMDSP_ENA
|
1705 MII_TG3_AUXCTL_ACTL_TX_6DB
;
1706 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy
);
1708 phy
= ((otp
& TG3_OTP_AGCTGT_MASK
) >> TG3_OTP_AGCTGT_SHIFT
);
1709 phy
|= MII_TG3_DSP_TAP1_AGCTGT_DFLT
;
1710 tg3_phydsp_write(tp
, MII_TG3_DSP_TAP1
, phy
);
1712 phy
= ((otp
& TG3_OTP_HPFFLTR_MASK
) >> TG3_OTP_HPFFLTR_SHIFT
) |
1713 ((otp
& TG3_OTP_HPFOVER_MASK
) >> TG3_OTP_HPFOVER_SHIFT
);
1714 tg3_phydsp_write(tp
, MII_TG3_DSP_AADJ1CH0
, phy
);
1716 phy
= ((otp
& TG3_OTP_LPFDIS_MASK
) >> TG3_OTP_LPFDIS_SHIFT
);
1717 phy
|= MII_TG3_DSP_AADJ1CH3_ADCCKADJ
;
1718 tg3_phydsp_write(tp
, MII_TG3_DSP_AADJ1CH3
, phy
);
1720 phy
= ((otp
& TG3_OTP_VDAC_MASK
) >> TG3_OTP_VDAC_SHIFT
);
1721 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP75
, phy
);
1723 phy
= ((otp
& TG3_OTP_10BTAMP_MASK
) >> TG3_OTP_10BTAMP_SHIFT
);
1724 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP96
, phy
);
1726 phy
= ((otp
& TG3_OTP_ROFF_MASK
) >> TG3_OTP_ROFF_SHIFT
) |
1727 ((otp
& TG3_OTP_RCOFF_MASK
) >> TG3_OTP_RCOFF_SHIFT
);
1728 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP97
, phy
);
1730 /* Turn off SM_DSP clock. */
1731 phy
= MII_TG3_AUXCTL_SHDWSEL_AUXCTL
|
1732 MII_TG3_AUXCTL_ACTL_TX_6DB
;
1733 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy
);
1736 static int tg3_wait_macro_done(struct tg3
*tp
)
1743 if (!tg3_readphy(tp
, 0x16, &tmp32
)) {
1744 if ((tmp32
& 0x1000) == 0)
1754 static int tg3_phy_write_and_check_testpat(struct tg3
*tp
, int *resetp
)
1756 static const u32 test_pat
[4][6] = {
1757 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1758 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1759 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1760 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1764 for (chan
= 0; chan
< 4; chan
++) {
1767 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
1768 (chan
* 0x2000) | 0x0200);
1769 tg3_writephy(tp
, 0x16, 0x0002);
1771 for (i
= 0; i
< 6; i
++)
1772 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
,
1775 tg3_writephy(tp
, 0x16, 0x0202);
1776 if (tg3_wait_macro_done(tp
)) {
1781 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
1782 (chan
* 0x2000) | 0x0200);
1783 tg3_writephy(tp
, 0x16, 0x0082);
1784 if (tg3_wait_macro_done(tp
)) {
1789 tg3_writephy(tp
, 0x16, 0x0802);
1790 if (tg3_wait_macro_done(tp
)) {
1795 for (i
= 0; i
< 6; i
+= 2) {
1798 if (tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &low
) ||
1799 tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &high
) ||
1800 tg3_wait_macro_done(tp
)) {
1806 if (low
!= test_pat
[chan
][i
] ||
1807 high
!= test_pat
[chan
][i
+1]) {
1808 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x000b);
1809 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x4001);
1810 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x4005);
1820 static int tg3_phy_reset_chanpat(struct tg3
*tp
)
1824 for (chan
= 0; chan
< 4; chan
++) {
1827 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
1828 (chan
* 0x2000) | 0x0200);
1829 tg3_writephy(tp
, 0x16, 0x0002);
1830 for (i
= 0; i
< 6; i
++)
1831 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x000);
1832 tg3_writephy(tp
, 0x16, 0x0202);
1833 if (tg3_wait_macro_done(tp
))
1840 static int tg3_phy_reset_5703_4_5(struct tg3
*tp
)
1842 u32 reg32
, phy9_orig
;
1843 int retries
, do_phy_reset
, err
;
1849 err
= tg3_bmcr_reset(tp
);
1855 /* Disable transmitter and interrupt. */
1856 if (tg3_readphy(tp
, MII_TG3_EXT_CTRL
, ®32
))
1860 tg3_writephy(tp
, MII_TG3_EXT_CTRL
, reg32
);
1862 /* Set full-duplex, 1000 mbps. */
1863 tg3_writephy(tp
, MII_BMCR
,
1864 BMCR_FULLDPLX
| TG3_BMCR_SPEED1000
);
1866 /* Set to master mode. */
1867 if (tg3_readphy(tp
, MII_TG3_CTRL
, &phy9_orig
))
1870 tg3_writephy(tp
, MII_TG3_CTRL
,
1871 (MII_TG3_CTRL_AS_MASTER
|
1872 MII_TG3_CTRL_ENABLE_AS_MASTER
));
1874 /* Enable SM_DSP_CLOCK and 6dB. */
1875 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
1877 /* Block the PHY control access. */
1878 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8005);
1879 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0800);
1881 err
= tg3_phy_write_and_check_testpat(tp
, &do_phy_reset
);
1884 } while (--retries
);
1886 err
= tg3_phy_reset_chanpat(tp
);
1890 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8005);
1891 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0000);
1893 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8200);
1894 tg3_writephy(tp
, 0x16, 0x0000);
1896 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
1897 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
1898 /* Set Extended packet length bit for jumbo frames */
1899 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4400);
1901 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
1904 tg3_writephy(tp
, MII_TG3_CTRL
, phy9_orig
);
1906 if (!tg3_readphy(tp
, MII_TG3_EXT_CTRL
, ®32
)) {
1908 tg3_writephy(tp
, MII_TG3_EXT_CTRL
, reg32
);
1915 /* This will reset the tigon3 PHY if there is no valid
1916 * link unless the FORCE argument is non-zero.
1918 static int tg3_phy_reset(struct tg3
*tp
)
1924 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
1927 val
= tr32(GRC_MISC_CFG
);
1928 tw32_f(GRC_MISC_CFG
, val
& ~GRC_MISC_CFG_EPHY_IDDQ
);
1931 err
= tg3_readphy(tp
, MII_BMSR
, &phy_status
);
1932 err
|= tg3_readphy(tp
, MII_BMSR
, &phy_status
);
1936 if (netif_running(tp
->dev
) && netif_carrier_ok(tp
->dev
)) {
1937 netif_carrier_off(tp
->dev
);
1938 tg3_link_report(tp
);
1941 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
1942 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
1943 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
1944 err
= tg3_phy_reset_5703_4_5(tp
);
1951 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
1952 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
) {
1953 cpmuctrl
= tr32(TG3_CPMU_CTRL
);
1954 if (cpmuctrl
& CPMU_CTRL_GPHY_10MB_RXONLY
)
1956 cpmuctrl
& ~CPMU_CTRL_GPHY_10MB_RXONLY
);
1959 err
= tg3_bmcr_reset(tp
);
1963 if (cpmuctrl
& CPMU_CTRL_GPHY_10MB_RXONLY
) {
1966 phy
= MII_TG3_DSP_EXP8_AEDW
| MII_TG3_DSP_EXP8_REJ2MHz
;
1967 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP8
, phy
);
1969 tw32(TG3_CPMU_CTRL
, cpmuctrl
);
1972 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
||
1973 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5761_AX
) {
1976 val
= tr32(TG3_CPMU_LSPD_1000MB_CLK
);
1977 if ((val
& CPMU_LSPD_1000MB_MACCLK_MASK
) ==
1978 CPMU_LSPD_1000MB_MACCLK_12_5
) {
1979 val
&= ~CPMU_LSPD_1000MB_MACCLK_MASK
;
1981 tw32_f(TG3_CPMU_LSPD_1000MB_CLK
, val
);
1985 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
1986 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
) &&
1987 (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
))
1990 tg3_phy_apply_otp(tp
);
1992 if (tp
->tg3_flags3
& TG3_FLG3_PHY_ENABLE_APD
)
1993 tg3_phy_toggle_apd(tp
, true);
1995 tg3_phy_toggle_apd(tp
, false);
1998 if (tp
->tg3_flags2
& TG3_FLG2_PHY_ADC_BUG
) {
1999 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
2000 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x201f);
2001 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x2aaa);
2002 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x000a);
2003 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0323);
2004 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
2006 if (tp
->tg3_flags2
& TG3_FLG2_PHY_5704_A0_BUG
) {
2007 tg3_writephy(tp
, 0x1c, 0x8d68);
2008 tg3_writephy(tp
, 0x1c, 0x8d68);
2010 if (tp
->tg3_flags2
& TG3_FLG2_PHY_BER_BUG
) {
2011 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
2012 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x000a);
2013 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x310b);
2014 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x201f);
2015 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x9506);
2016 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x401f);
2017 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x14e2);
2018 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
2019 } else if (tp
->tg3_flags2
& TG3_FLG2_PHY_JITTER_BUG
) {
2020 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
2021 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x000a);
2022 if (tp
->tg3_flags2
& TG3_FLG2_PHY_ADJUST_TRIM
) {
2023 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x110b);
2024 tg3_writephy(tp
, MII_TG3_TEST1
,
2025 MII_TG3_TEST1_TRIM_EN
| 0x4);
2027 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x010b);
2028 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
2030 /* Set Extended packet length bit (bit 14) on all chips that */
2031 /* support jumbo frames */
2032 if ((tp
->phy_id
& TG3_PHY_ID_MASK
) == TG3_PHY_ID_BCM5401
) {
2033 /* Cannot do read-modify-write on 5401 */
2034 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4c20);
2035 } else if (tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) {
2038 /* Set bit 14 with read-modify-write to preserve other bits */
2039 if (!tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0007) &&
2040 !tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &phy_reg
))
2041 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy_reg
| 0x4000);
2044 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2045 * jumbo frames transmission.
2047 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) {
2050 if (!tg3_readphy(tp
, MII_TG3_EXT_CTRL
, &phy_reg
))
2051 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
2052 phy_reg
| MII_TG3_EXT_CTRL_FIFO_ELASTIC
);
2055 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
2056 /* adjust output voltage */
2057 tg3_writephy(tp
, MII_TG3_FET_PTEST
, 0x12);
2060 tg3_phy_toggle_automdix(tp
, 1);
2061 tg3_phy_set_wirespeed(tp
);
2065 static void tg3_frob_aux_power(struct tg3
*tp
)
2067 struct tg3
*tp_peer
= tp
;
2069 /* The GPIOs do something completely different on 57765. */
2070 if ((tp
->tg3_flags2
& TG3_FLG2_IS_NIC
) == 0 ||
2071 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
||
2072 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
2075 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
2076 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
||
2077 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
) {
2078 struct net_device
*dev_peer
;
2080 dev_peer
= pci_get_drvdata(tp
->pdev_peer
);
2081 /* remove_one() may have been run on the peer. */
2085 tp_peer
= netdev_priv(dev_peer
);
2088 if ((tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
) != 0 ||
2089 (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) != 0 ||
2090 (tp_peer
->tg3_flags
& TG3_FLAG_WOL_ENABLE
) != 0 ||
2091 (tp_peer
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) != 0) {
2092 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2093 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
2094 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2095 (GRC_LCLCTRL_GPIO_OE0
|
2096 GRC_LCLCTRL_GPIO_OE1
|
2097 GRC_LCLCTRL_GPIO_OE2
|
2098 GRC_LCLCTRL_GPIO_OUTPUT0
|
2099 GRC_LCLCTRL_GPIO_OUTPUT1
),
2101 } else if (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5761
||
2102 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5761S
) {
2103 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2104 u32 grc_local_ctrl
= GRC_LCLCTRL_GPIO_OE0
|
2105 GRC_LCLCTRL_GPIO_OE1
|
2106 GRC_LCLCTRL_GPIO_OE2
|
2107 GRC_LCLCTRL_GPIO_OUTPUT0
|
2108 GRC_LCLCTRL_GPIO_OUTPUT1
|
2110 tw32_wait_f(GRC_LOCAL_CTRL
, grc_local_ctrl
, 100);
2112 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OUTPUT2
;
2113 tw32_wait_f(GRC_LOCAL_CTRL
, grc_local_ctrl
, 100);
2115 grc_local_ctrl
&= ~GRC_LCLCTRL_GPIO_OUTPUT0
;
2116 tw32_wait_f(GRC_LOCAL_CTRL
, grc_local_ctrl
, 100);
2119 u32 grc_local_ctrl
= 0;
2121 if (tp_peer
!= tp
&&
2122 (tp_peer
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
) != 0)
2125 /* Workaround to prevent overdrawing Amps. */
2126 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
2128 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE3
;
2129 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2130 grc_local_ctrl
, 100);
2133 /* On 5753 and variants, GPIO2 cannot be used. */
2134 no_gpio2
= tp
->nic_sram_data_cfg
&
2135 NIC_SRAM_DATA_CFG_NO_GPIO2
;
2137 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE0
|
2138 GRC_LCLCTRL_GPIO_OE1
|
2139 GRC_LCLCTRL_GPIO_OE2
|
2140 GRC_LCLCTRL_GPIO_OUTPUT1
|
2141 GRC_LCLCTRL_GPIO_OUTPUT2
;
2143 grc_local_ctrl
&= ~(GRC_LCLCTRL_GPIO_OE2
|
2144 GRC_LCLCTRL_GPIO_OUTPUT2
);
2146 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2147 grc_local_ctrl
, 100);
2149 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OUTPUT0
;
2151 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2152 grc_local_ctrl
, 100);
2155 grc_local_ctrl
&= ~GRC_LCLCTRL_GPIO_OUTPUT2
;
2156 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2157 grc_local_ctrl
, 100);
2161 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
2162 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
) {
2163 if (tp_peer
!= tp
&&
2164 (tp_peer
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
) != 0)
2167 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2168 (GRC_LCLCTRL_GPIO_OE1
|
2169 GRC_LCLCTRL_GPIO_OUTPUT1
), 100);
2171 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2172 GRC_LCLCTRL_GPIO_OE1
, 100);
2174 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2175 (GRC_LCLCTRL_GPIO_OE1
|
2176 GRC_LCLCTRL_GPIO_OUTPUT1
), 100);
2181 static int tg3_5700_link_polarity(struct tg3
*tp
, u32 speed
)
2183 if (tp
->led_ctrl
== LED_CTRL_MODE_PHY_2
)
2185 else if ((tp
->phy_id
& TG3_PHY_ID_MASK
) == TG3_PHY_ID_BCM5411
) {
2186 if (speed
!= SPEED_10
)
2188 } else if (speed
== SPEED_10
)
2194 static int tg3_setup_phy(struct tg3
*, int);
2196 #define RESET_KIND_SHUTDOWN 0
2197 #define RESET_KIND_INIT 1
2198 #define RESET_KIND_SUSPEND 2
2200 static void tg3_write_sig_post_reset(struct tg3
*, int);
2201 static int tg3_halt_cpu(struct tg3
*, u32
);
2203 static void tg3_power_down_phy(struct tg3
*tp
, bool do_low_power
)
2207 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
2208 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
2209 u32 sg_dig_ctrl
= tr32(SG_DIG_CTRL
);
2210 u32 serdes_cfg
= tr32(MAC_SERDES_CFG
);
2213 SG_DIG_USING_HW_AUTONEG
| SG_DIG_SOFT_RESET
;
2214 tw32(SG_DIG_CTRL
, sg_dig_ctrl
);
2215 tw32(MAC_SERDES_CFG
, serdes_cfg
| (1 << 15));
2220 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
2222 val
= tr32(GRC_MISC_CFG
);
2223 tw32_f(GRC_MISC_CFG
, val
| GRC_MISC_CFG_EPHY_IDDQ
);
2226 } else if (tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
) {
2228 if (!tg3_readphy(tp
, MII_TG3_FET_TEST
, &phytest
)) {
2231 tg3_writephy(tp
, MII_ADVERTISE
, 0);
2232 tg3_writephy(tp
, MII_BMCR
,
2233 BMCR_ANENABLE
| BMCR_ANRESTART
);
2235 tg3_writephy(tp
, MII_TG3_FET_TEST
,
2236 phytest
| MII_TG3_FET_SHADOW_EN
);
2237 if (!tg3_readphy(tp
, MII_TG3_FET_SHDW_AUXMODE4
, &phy
)) {
2238 phy
|= MII_TG3_FET_SHDW_AUXMODE4_SBPD
;
2240 MII_TG3_FET_SHDW_AUXMODE4
,
2243 tg3_writephy(tp
, MII_TG3_FET_TEST
, phytest
);
2246 } else if (do_low_power
) {
2247 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
2248 MII_TG3_EXT_CTRL_FORCE_LED_OFF
);
2250 tg3_writephy(tp
, MII_TG3_AUX_CTRL
,
2251 MII_TG3_AUXCTL_SHDWSEL_PWRCTL
|
2252 MII_TG3_AUXCTL_PCTL_100TX_LPWR
|
2253 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE
|
2254 MII_TG3_AUXCTL_PCTL_VREG_11V
);
2257 /* The PHY should not be powered down on some chips because
2260 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2261 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
2262 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5780
&&
2263 (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
)))
2266 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
||
2267 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5761_AX
) {
2268 val
= tr32(TG3_CPMU_LSPD_1000MB_CLK
);
2269 val
&= ~CPMU_LSPD_1000MB_MACCLK_MASK
;
2270 val
|= CPMU_LSPD_1000MB_MACCLK_12_5
;
2271 tw32_f(TG3_CPMU_LSPD_1000MB_CLK
, val
);
2274 tg3_writephy(tp
, MII_BMCR
, BMCR_PDOWN
);
2277 /* tp->lock is held. */
2278 static int tg3_nvram_lock(struct tg3
*tp
)
2280 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
) {
2283 if (tp
->nvram_lock_cnt
== 0) {
2284 tw32(NVRAM_SWARB
, SWARB_REQ_SET1
);
2285 for (i
= 0; i
< 8000; i
++) {
2286 if (tr32(NVRAM_SWARB
) & SWARB_GNT1
)
2291 tw32(NVRAM_SWARB
, SWARB_REQ_CLR1
);
2295 tp
->nvram_lock_cnt
++;
2300 /* tp->lock is held. */
2301 static void tg3_nvram_unlock(struct tg3
*tp
)
2303 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
) {
2304 if (tp
->nvram_lock_cnt
> 0)
2305 tp
->nvram_lock_cnt
--;
2306 if (tp
->nvram_lock_cnt
== 0)
2307 tw32_f(NVRAM_SWARB
, SWARB_REQ_CLR1
);
2311 /* tp->lock is held. */
2312 static void tg3_enable_nvram_access(struct tg3
*tp
)
2314 if ((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
2315 !(tp
->tg3_flags3
& TG3_FLG3_PROTECTED_NVRAM
)) {
2316 u32 nvaccess
= tr32(NVRAM_ACCESS
);
2318 tw32(NVRAM_ACCESS
, nvaccess
| ACCESS_ENABLE
);
2322 /* tp->lock is held. */
2323 static void tg3_disable_nvram_access(struct tg3
*tp
)
2325 if ((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
2326 !(tp
->tg3_flags3
& TG3_FLG3_PROTECTED_NVRAM
)) {
2327 u32 nvaccess
= tr32(NVRAM_ACCESS
);
2329 tw32(NVRAM_ACCESS
, nvaccess
& ~ACCESS_ENABLE
);
2333 static int tg3_nvram_read_using_eeprom(struct tg3
*tp
,
2334 u32 offset
, u32
*val
)
2339 if (offset
> EEPROM_ADDR_ADDR_MASK
|| (offset
% 4) != 0)
2342 tmp
= tr32(GRC_EEPROM_ADDR
) & ~(EEPROM_ADDR_ADDR_MASK
|
2343 EEPROM_ADDR_DEVID_MASK
|
2345 tw32(GRC_EEPROM_ADDR
,
2347 (0 << EEPROM_ADDR_DEVID_SHIFT
) |
2348 ((offset
<< EEPROM_ADDR_ADDR_SHIFT
) &
2349 EEPROM_ADDR_ADDR_MASK
) |
2350 EEPROM_ADDR_READ
| EEPROM_ADDR_START
);
2352 for (i
= 0; i
< 1000; i
++) {
2353 tmp
= tr32(GRC_EEPROM_ADDR
);
2355 if (tmp
& EEPROM_ADDR_COMPLETE
)
2359 if (!(tmp
& EEPROM_ADDR_COMPLETE
))
2362 tmp
= tr32(GRC_EEPROM_DATA
);
2365 * The data will always be opposite the native endian
2366 * format. Perform a blind byteswap to compensate.
2373 #define NVRAM_CMD_TIMEOUT 10000
2375 static int tg3_nvram_exec_cmd(struct tg3
*tp
, u32 nvram_cmd
)
2379 tw32(NVRAM_CMD
, nvram_cmd
);
2380 for (i
= 0; i
< NVRAM_CMD_TIMEOUT
; i
++) {
2382 if (tr32(NVRAM_CMD
) & NVRAM_CMD_DONE
) {
2388 if (i
== NVRAM_CMD_TIMEOUT
)
2394 static u32
tg3_nvram_phys_addr(struct tg3
*tp
, u32 addr
)
2396 if ((tp
->tg3_flags
& TG3_FLAG_NVRAM
) &&
2397 (tp
->tg3_flags
& TG3_FLAG_NVRAM_BUFFERED
) &&
2398 (tp
->tg3_flags2
& TG3_FLG2_FLASH
) &&
2399 !(tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM_ADDR_TRANS
) &&
2400 (tp
->nvram_jedecnum
== JEDEC_ATMEL
))
2402 addr
= ((addr
/ tp
->nvram_pagesize
) <<
2403 ATMEL_AT45DB0X1B_PAGE_POS
) +
2404 (addr
% tp
->nvram_pagesize
);
2409 static u32
tg3_nvram_logical_addr(struct tg3
*tp
, u32 addr
)
2411 if ((tp
->tg3_flags
& TG3_FLAG_NVRAM
) &&
2412 (tp
->tg3_flags
& TG3_FLAG_NVRAM_BUFFERED
) &&
2413 (tp
->tg3_flags2
& TG3_FLG2_FLASH
) &&
2414 !(tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM_ADDR_TRANS
) &&
2415 (tp
->nvram_jedecnum
== JEDEC_ATMEL
))
2417 addr
= ((addr
>> ATMEL_AT45DB0X1B_PAGE_POS
) *
2418 tp
->nvram_pagesize
) +
2419 (addr
& ((1 << ATMEL_AT45DB0X1B_PAGE_POS
) - 1));
2424 /* NOTE: Data read in from NVRAM is byteswapped according to
2425 * the byteswapping settings for all other register accesses.
2426 * tg3 devices are BE devices, so on a BE machine, the data
2427 * returned will be exactly as it is seen in NVRAM. On a LE
2428 * machine, the 32-bit value will be byteswapped.
2430 static int tg3_nvram_read(struct tg3
*tp
, u32 offset
, u32
*val
)
2434 if (!(tp
->tg3_flags
& TG3_FLAG_NVRAM
))
2435 return tg3_nvram_read_using_eeprom(tp
, offset
, val
);
2437 offset
= tg3_nvram_phys_addr(tp
, offset
);
2439 if (offset
> NVRAM_ADDR_MSK
)
2442 ret
= tg3_nvram_lock(tp
);
2446 tg3_enable_nvram_access(tp
);
2448 tw32(NVRAM_ADDR
, offset
);
2449 ret
= tg3_nvram_exec_cmd(tp
, NVRAM_CMD_RD
| NVRAM_CMD_GO
|
2450 NVRAM_CMD_FIRST
| NVRAM_CMD_LAST
| NVRAM_CMD_DONE
);
2453 *val
= tr32(NVRAM_RDDATA
);
2455 tg3_disable_nvram_access(tp
);
2457 tg3_nvram_unlock(tp
);
2462 /* Ensures NVRAM data is in bytestream format. */
2463 static int tg3_nvram_read_be32(struct tg3
*tp
, u32 offset
, __be32
*val
)
2466 int res
= tg3_nvram_read(tp
, offset
, &v
);
2468 *val
= cpu_to_be32(v
);
2472 /* tp->lock is held. */
2473 static void __tg3_set_mac_addr(struct tg3
*tp
, int skip_mac_1
)
2475 u32 addr_high
, addr_low
;
2478 addr_high
= ((tp
->dev
->dev_addr
[0] << 8) |
2479 tp
->dev
->dev_addr
[1]);
2480 addr_low
= ((tp
->dev
->dev_addr
[2] << 24) |
2481 (tp
->dev
->dev_addr
[3] << 16) |
2482 (tp
->dev
->dev_addr
[4] << 8) |
2483 (tp
->dev
->dev_addr
[5] << 0));
2484 for (i
= 0; i
< 4; i
++) {
2485 if (i
== 1 && skip_mac_1
)
2487 tw32(MAC_ADDR_0_HIGH
+ (i
* 8), addr_high
);
2488 tw32(MAC_ADDR_0_LOW
+ (i
* 8), addr_low
);
2491 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
2492 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
2493 for (i
= 0; i
< 12; i
++) {
2494 tw32(MAC_EXTADDR_0_HIGH
+ (i
* 8), addr_high
);
2495 tw32(MAC_EXTADDR_0_LOW
+ (i
* 8), addr_low
);
2499 addr_high
= (tp
->dev
->dev_addr
[0] +
2500 tp
->dev
->dev_addr
[1] +
2501 tp
->dev
->dev_addr
[2] +
2502 tp
->dev
->dev_addr
[3] +
2503 tp
->dev
->dev_addr
[4] +
2504 tp
->dev
->dev_addr
[5]) &
2505 TX_BACKOFF_SEED_MASK
;
2506 tw32(MAC_TX_BACKOFF_SEED
, addr_high
);
2509 static int tg3_set_power_state(struct tg3
*tp
, pci_power_t state
)
2512 bool device_should_wake
, do_low_power
;
2514 /* Make sure register accesses (indirect or otherwise)
2515 * will function correctly.
2517 pci_write_config_dword(tp
->pdev
,
2518 TG3PCI_MISC_HOST_CTRL
,
2519 tp
->misc_host_ctrl
);
2523 pci_enable_wake(tp
->pdev
, state
, false);
2524 pci_set_power_state(tp
->pdev
, PCI_D0
);
2526 /* Switch out of Vaux if it is a NIC */
2527 if (tp
->tg3_flags2
& TG3_FLG2_IS_NIC
)
2528 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
, 100);
2538 netdev_err(tp
->dev
, "Invalid power state (D%d) requested\n",
2543 /* Restore the CLKREQ setting. */
2544 if (tp
->tg3_flags3
& TG3_FLG3_CLKREQ_BUG
) {
2547 pci_read_config_word(tp
->pdev
,
2548 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
2550 lnkctl
|= PCI_EXP_LNKCTL_CLKREQ_EN
;
2551 pci_write_config_word(tp
->pdev
,
2552 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
2556 misc_host_ctrl
= tr32(TG3PCI_MISC_HOST_CTRL
);
2557 tw32(TG3PCI_MISC_HOST_CTRL
,
2558 misc_host_ctrl
| MISC_HOST_CTRL_MASK_PCI_INT
);
2560 device_should_wake
= pci_pme_capable(tp
->pdev
, state
) &&
2561 device_may_wakeup(&tp
->pdev
->dev
) &&
2562 (tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
);
2564 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
2565 do_low_power
= false;
2566 if ((tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
) &&
2567 !tp
->link_config
.phy_is_low_power
) {
2568 struct phy_device
*phydev
;
2569 u32 phyid
, advertising
;
2571 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
2573 tp
->link_config
.phy_is_low_power
= 1;
2575 tp
->link_config
.orig_speed
= phydev
->speed
;
2576 tp
->link_config
.orig_duplex
= phydev
->duplex
;
2577 tp
->link_config
.orig_autoneg
= phydev
->autoneg
;
2578 tp
->link_config
.orig_advertising
= phydev
->advertising
;
2580 advertising
= ADVERTISED_TP
|
2582 ADVERTISED_Autoneg
|
2583 ADVERTISED_10baseT_Half
;
2585 if ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) ||
2586 device_should_wake
) {
2587 if (tp
->tg3_flags
& TG3_FLAG_WOL_SPEED_100MB
)
2589 ADVERTISED_100baseT_Half
|
2590 ADVERTISED_100baseT_Full
|
2591 ADVERTISED_10baseT_Full
;
2593 advertising
|= ADVERTISED_10baseT_Full
;
2596 phydev
->advertising
= advertising
;
2598 phy_start_aneg(phydev
);
2600 phyid
= phydev
->drv
->phy_id
& phydev
->drv
->phy_id_mask
;
2601 if (phyid
!= PHY_ID_BCMAC131
) {
2602 phyid
&= PHY_BCM_OUI_MASK
;
2603 if (phyid
== PHY_BCM_OUI_1
||
2604 phyid
== PHY_BCM_OUI_2
||
2605 phyid
== PHY_BCM_OUI_3
)
2606 do_low_power
= true;
2610 do_low_power
= true;
2612 if (tp
->link_config
.phy_is_low_power
== 0) {
2613 tp
->link_config
.phy_is_low_power
= 1;
2614 tp
->link_config
.orig_speed
= tp
->link_config
.speed
;
2615 tp
->link_config
.orig_duplex
= tp
->link_config
.duplex
;
2616 tp
->link_config
.orig_autoneg
= tp
->link_config
.autoneg
;
2619 if (!(tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
)) {
2620 tp
->link_config
.speed
= SPEED_10
;
2621 tp
->link_config
.duplex
= DUPLEX_HALF
;
2622 tp
->link_config
.autoneg
= AUTONEG_ENABLE
;
2623 tg3_setup_phy(tp
, 0);
2627 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
2630 val
= tr32(GRC_VCPU_EXT_CTRL
);
2631 tw32(GRC_VCPU_EXT_CTRL
, val
| GRC_VCPU_EXT_CTRL_DISABLE_WOL
);
2632 } else if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)) {
2636 for (i
= 0; i
< 200; i
++) {
2637 tg3_read_mem(tp
, NIC_SRAM_FW_ASF_STATUS_MBOX
, &val
);
2638 if (val
== ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1
)
2643 if (tp
->tg3_flags
& TG3_FLAG_WOL_CAP
)
2644 tg3_write_mem(tp
, NIC_SRAM_WOL_MBOX
, WOL_SIGNATURE
|
2645 WOL_DRV_STATE_SHUTDOWN
|
2649 if (device_should_wake
) {
2652 if (!(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)) {
2654 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x5a);
2658 if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
)
2659 mac_mode
= MAC_MODE_PORT_MODE_GMII
;
2661 mac_mode
= MAC_MODE_PORT_MODE_MII
;
2663 mac_mode
|= tp
->mac_mode
& MAC_MODE_LINK_POLARITY
;
2664 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
2666 u32 speed
= (tp
->tg3_flags
&
2667 TG3_FLAG_WOL_SPEED_100MB
) ?
2668 SPEED_100
: SPEED_10
;
2669 if (tg3_5700_link_polarity(tp
, speed
))
2670 mac_mode
|= MAC_MODE_LINK_POLARITY
;
2672 mac_mode
&= ~MAC_MODE_LINK_POLARITY
;
2675 mac_mode
= MAC_MODE_PORT_MODE_TBI
;
2678 if (!(tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
))
2679 tw32(MAC_LED_CTRL
, tp
->led_ctrl
);
2681 mac_mode
|= MAC_MODE_MAGIC_PKT_ENABLE
;
2682 if (((tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
2683 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) &&
2684 ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) ||
2685 (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)))
2686 mac_mode
|= MAC_MODE_KEEP_FRAME_IN_WOL
;
2688 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
2689 mac_mode
|= tp
->mac_mode
&
2690 (MAC_MODE_APE_TX_EN
| MAC_MODE_APE_RX_EN
);
2691 if (mac_mode
& MAC_MODE_APE_TX_EN
)
2692 mac_mode
|= MAC_MODE_TDE_ENABLE
;
2695 tw32_f(MAC_MODE
, mac_mode
);
2698 tw32_f(MAC_RX_MODE
, RX_MODE_ENABLE
);
2702 if (!(tp
->tg3_flags
& TG3_FLAG_WOL_SPEED_100MB
) &&
2703 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2704 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)) {
2707 base_val
= tp
->pci_clock_ctrl
;
2708 base_val
|= (CLOCK_CTRL_RXCLK_DISABLE
|
2709 CLOCK_CTRL_TXCLK_DISABLE
);
2711 tw32_wait_f(TG3PCI_CLOCK_CTRL
, base_val
| CLOCK_CTRL_ALTCLK
|
2712 CLOCK_CTRL_PWRDOWN_PLL133
, 40);
2713 } else if ((tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) ||
2714 (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) ||
2715 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)) {
2717 } else if (!((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
2718 (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))) {
2719 u32 newbits1
, newbits2
;
2721 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2722 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
2723 newbits1
= (CLOCK_CTRL_RXCLK_DISABLE
|
2724 CLOCK_CTRL_TXCLK_DISABLE
|
2726 newbits2
= newbits1
| CLOCK_CTRL_44MHZ_CORE
;
2727 } else if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
2728 newbits1
= CLOCK_CTRL_625_CORE
;
2729 newbits2
= newbits1
| CLOCK_CTRL_ALTCLK
;
2731 newbits1
= CLOCK_CTRL_ALTCLK
;
2732 newbits2
= newbits1
| CLOCK_CTRL_44MHZ_CORE
;
2735 tw32_wait_f(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
| newbits1
,
2738 tw32_wait_f(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
| newbits2
,
2741 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
2744 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2745 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
2746 newbits3
= (CLOCK_CTRL_RXCLK_DISABLE
|
2747 CLOCK_CTRL_TXCLK_DISABLE
|
2748 CLOCK_CTRL_44MHZ_CORE
);
2750 newbits3
= CLOCK_CTRL_44MHZ_CORE
;
2753 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
2754 tp
->pci_clock_ctrl
| newbits3
, 40);
2758 if (!(device_should_wake
) &&
2759 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
2760 tg3_power_down_phy(tp
, do_low_power
);
2762 tg3_frob_aux_power(tp
);
2764 /* Workaround for unstable PLL clock */
2765 if ((GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_AX
) ||
2766 (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_BX
)) {
2767 u32 val
= tr32(0x7d00);
2769 val
&= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2771 if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)) {
2774 err
= tg3_nvram_lock(tp
);
2775 tg3_halt_cpu(tp
, RX_CPU_BASE
);
2777 tg3_nvram_unlock(tp
);
2781 tg3_write_sig_post_reset(tp
, RESET_KIND_SHUTDOWN
);
2783 if (device_should_wake
)
2784 pci_enable_wake(tp
->pdev
, state
, true);
2786 /* Finally, set the new power state. */
2787 pci_set_power_state(tp
->pdev
, state
);
2792 static void tg3_aux_stat_to_speed_duplex(struct tg3
*tp
, u32 val
, u16
*speed
, u8
*duplex
)
2794 switch (val
& MII_TG3_AUX_STAT_SPDMASK
) {
2795 case MII_TG3_AUX_STAT_10HALF
:
2797 *duplex
= DUPLEX_HALF
;
2800 case MII_TG3_AUX_STAT_10FULL
:
2802 *duplex
= DUPLEX_FULL
;
2805 case MII_TG3_AUX_STAT_100HALF
:
2807 *duplex
= DUPLEX_HALF
;
2810 case MII_TG3_AUX_STAT_100FULL
:
2812 *duplex
= DUPLEX_FULL
;
2815 case MII_TG3_AUX_STAT_1000HALF
:
2816 *speed
= SPEED_1000
;
2817 *duplex
= DUPLEX_HALF
;
2820 case MII_TG3_AUX_STAT_1000FULL
:
2821 *speed
= SPEED_1000
;
2822 *duplex
= DUPLEX_FULL
;
2826 if (tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
) {
2827 *speed
= (val
& MII_TG3_AUX_STAT_100
) ? SPEED_100
:
2829 *duplex
= (val
& MII_TG3_AUX_STAT_FULL
) ? DUPLEX_FULL
:
2833 *speed
= SPEED_INVALID
;
2834 *duplex
= DUPLEX_INVALID
;
2839 static void tg3_phy_copper_begin(struct tg3
*tp
)
2844 if (tp
->link_config
.phy_is_low_power
) {
2845 /* Entering low power mode. Disable gigabit and
2846 * 100baseT advertisements.
2848 tg3_writephy(tp
, MII_TG3_CTRL
, 0);
2850 new_adv
= (ADVERTISE_10HALF
| ADVERTISE_10FULL
|
2851 ADVERTISE_CSMA
| ADVERTISE_PAUSE_CAP
);
2852 if (tp
->tg3_flags
& TG3_FLAG_WOL_SPEED_100MB
)
2853 new_adv
|= (ADVERTISE_100HALF
| ADVERTISE_100FULL
);
2855 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
2856 } else if (tp
->link_config
.speed
== SPEED_INVALID
) {
2857 if (tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)
2858 tp
->link_config
.advertising
&=
2859 ~(ADVERTISED_1000baseT_Half
|
2860 ADVERTISED_1000baseT_Full
);
2862 new_adv
= ADVERTISE_CSMA
;
2863 if (tp
->link_config
.advertising
& ADVERTISED_10baseT_Half
)
2864 new_adv
|= ADVERTISE_10HALF
;
2865 if (tp
->link_config
.advertising
& ADVERTISED_10baseT_Full
)
2866 new_adv
|= ADVERTISE_10FULL
;
2867 if (tp
->link_config
.advertising
& ADVERTISED_100baseT_Half
)
2868 new_adv
|= ADVERTISE_100HALF
;
2869 if (tp
->link_config
.advertising
& ADVERTISED_100baseT_Full
)
2870 new_adv
|= ADVERTISE_100FULL
;
2872 new_adv
|= tg3_advert_flowctrl_1000T(tp
->link_config
.flowctrl
);
2874 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
2876 if (tp
->link_config
.advertising
&
2877 (ADVERTISED_1000baseT_Half
| ADVERTISED_1000baseT_Full
)) {
2879 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Half
)
2880 new_adv
|= MII_TG3_CTRL_ADV_1000_HALF
;
2881 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Full
)
2882 new_adv
|= MII_TG3_CTRL_ADV_1000_FULL
;
2883 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
) &&
2884 (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
2885 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
))
2886 new_adv
|= (MII_TG3_CTRL_AS_MASTER
|
2887 MII_TG3_CTRL_ENABLE_AS_MASTER
);
2888 tg3_writephy(tp
, MII_TG3_CTRL
, new_adv
);
2890 tg3_writephy(tp
, MII_TG3_CTRL
, 0);
2893 new_adv
= tg3_advert_flowctrl_1000T(tp
->link_config
.flowctrl
);
2894 new_adv
|= ADVERTISE_CSMA
;
2896 /* Asking for a specific link mode. */
2897 if (tp
->link_config
.speed
== SPEED_1000
) {
2898 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
2900 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
2901 new_adv
= MII_TG3_CTRL_ADV_1000_FULL
;
2903 new_adv
= MII_TG3_CTRL_ADV_1000_HALF
;
2904 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
2905 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
)
2906 new_adv
|= (MII_TG3_CTRL_AS_MASTER
|
2907 MII_TG3_CTRL_ENABLE_AS_MASTER
);
2909 if (tp
->link_config
.speed
== SPEED_100
) {
2910 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
2911 new_adv
|= ADVERTISE_100FULL
;
2913 new_adv
|= ADVERTISE_100HALF
;
2915 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
2916 new_adv
|= ADVERTISE_10FULL
;
2918 new_adv
|= ADVERTISE_10HALF
;
2920 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
2925 tg3_writephy(tp
, MII_TG3_CTRL
, new_adv
);
2928 if (tp
->link_config
.autoneg
== AUTONEG_DISABLE
&&
2929 tp
->link_config
.speed
!= SPEED_INVALID
) {
2930 u32 bmcr
, orig_bmcr
;
2932 tp
->link_config
.active_speed
= tp
->link_config
.speed
;
2933 tp
->link_config
.active_duplex
= tp
->link_config
.duplex
;
2936 switch (tp
->link_config
.speed
) {
2942 bmcr
|= BMCR_SPEED100
;
2946 bmcr
|= TG3_BMCR_SPEED1000
;
2950 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
2951 bmcr
|= BMCR_FULLDPLX
;
2953 if (!tg3_readphy(tp
, MII_BMCR
, &orig_bmcr
) &&
2954 (bmcr
!= orig_bmcr
)) {
2955 tg3_writephy(tp
, MII_BMCR
, BMCR_LOOPBACK
);
2956 for (i
= 0; i
< 1500; i
++) {
2960 if (tg3_readphy(tp
, MII_BMSR
, &tmp
) ||
2961 tg3_readphy(tp
, MII_BMSR
, &tmp
))
2963 if (!(tmp
& BMSR_LSTATUS
)) {
2968 tg3_writephy(tp
, MII_BMCR
, bmcr
);
2972 tg3_writephy(tp
, MII_BMCR
,
2973 BMCR_ANENABLE
| BMCR_ANRESTART
);
2977 static int tg3_init_5401phy_dsp(struct tg3
*tp
)
2981 /* Turn off tap power management. */
2982 /* Set Extended packet length bit */
2983 err
= tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4c20);
2985 err
|= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x0012);
2986 err
|= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x1804);
2988 err
|= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x0013);
2989 err
|= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x1204);
2991 err
|= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8006);
2992 err
|= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0132);
2994 err
|= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8006);
2995 err
|= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0232);
2997 err
|= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x201f);
2998 err
|= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0a20);
3005 static int tg3_copper_is_advertising_all(struct tg3
*tp
, u32 mask
)
3007 u32 adv_reg
, all_mask
= 0;
3009 if (mask
& ADVERTISED_10baseT_Half
)
3010 all_mask
|= ADVERTISE_10HALF
;
3011 if (mask
& ADVERTISED_10baseT_Full
)
3012 all_mask
|= ADVERTISE_10FULL
;
3013 if (mask
& ADVERTISED_100baseT_Half
)
3014 all_mask
|= ADVERTISE_100HALF
;
3015 if (mask
& ADVERTISED_100baseT_Full
)
3016 all_mask
|= ADVERTISE_100FULL
;
3018 if (tg3_readphy(tp
, MII_ADVERTISE
, &adv_reg
))
3021 if ((adv_reg
& all_mask
) != all_mask
)
3023 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)) {
3027 if (mask
& ADVERTISED_1000baseT_Half
)
3028 all_mask
|= ADVERTISE_1000HALF
;
3029 if (mask
& ADVERTISED_1000baseT_Full
)
3030 all_mask
|= ADVERTISE_1000FULL
;
3032 if (tg3_readphy(tp
, MII_TG3_CTRL
, &tg3_ctrl
))
3035 if ((tg3_ctrl
& all_mask
) != all_mask
)
3041 static int tg3_adv_1000T_flowctrl_ok(struct tg3
*tp
, u32
*lcladv
, u32
*rmtadv
)
3045 if (tg3_readphy(tp
, MII_ADVERTISE
, lcladv
))
3048 curadv
= *lcladv
& (ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
3049 reqadv
= tg3_advert_flowctrl_1000T(tp
->link_config
.flowctrl
);
3051 if (tp
->link_config
.active_duplex
== DUPLEX_FULL
) {
3052 if (curadv
!= reqadv
)
3055 if (tp
->tg3_flags
& TG3_FLAG_PAUSE_AUTONEG
)
3056 tg3_readphy(tp
, MII_LPA
, rmtadv
);
3058 /* Reprogram the advertisement register, even if it
3059 * does not affect the current link. If the link
3060 * gets renegotiated in the future, we can save an
3061 * additional renegotiation cycle by advertising
3062 * it correctly in the first place.
3064 if (curadv
!= reqadv
) {
3065 *lcladv
&= ~(ADVERTISE_PAUSE_CAP
|
3066 ADVERTISE_PAUSE_ASYM
);
3067 tg3_writephy(tp
, MII_ADVERTISE
, *lcladv
| reqadv
);
3074 static int tg3_setup_copper_phy(struct tg3
*tp
, int force_reset
)
3076 int current_link_up
;
3078 u32 lcl_adv
, rmt_adv
;
3086 (MAC_STATUS_SYNC_CHANGED
|
3087 MAC_STATUS_CFG_CHANGED
|
3088 MAC_STATUS_MI_COMPLETION
|
3089 MAC_STATUS_LNKSTATE_CHANGED
));
3092 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
3094 (tp
->mi_mode
& ~MAC_MI_MODE_AUTO_POLL
));
3098 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x02);
3100 /* Some third-party PHYs need to be reset on link going
3103 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
3104 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
3105 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) &&
3106 netif_carrier_ok(tp
->dev
)) {
3107 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3108 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
3109 !(bmsr
& BMSR_LSTATUS
))
3115 if ((tp
->phy_id
& TG3_PHY_ID_MASK
) == TG3_PHY_ID_BCM5401
) {
3116 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3117 if (tg3_readphy(tp
, MII_BMSR
, &bmsr
) ||
3118 !(tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
))
3121 if (!(bmsr
& BMSR_LSTATUS
)) {
3122 err
= tg3_init_5401phy_dsp(tp
);
3126 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3127 for (i
= 0; i
< 1000; i
++) {
3129 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
3130 (bmsr
& BMSR_LSTATUS
)) {
3136 if ((tp
->phy_id
& TG3_PHY_ID_REV_MASK
) ==
3137 TG3_PHY_REV_BCM5401_B0
&&
3138 !(bmsr
& BMSR_LSTATUS
) &&
3139 tp
->link_config
.active_speed
== SPEED_1000
) {
3140 err
= tg3_phy_reset(tp
);
3142 err
= tg3_init_5401phy_dsp(tp
);
3147 } else if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
3148 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
) {
3149 /* 5701 {A0,B0} CRC bug workaround */
3150 tg3_writephy(tp
, 0x15, 0x0a75);
3151 tg3_writephy(tp
, 0x1c, 0x8c68);
3152 tg3_writephy(tp
, 0x1c, 0x8d68);
3153 tg3_writephy(tp
, 0x1c, 0x8c68);
3156 /* Clear pending interrupts... */
3157 tg3_readphy(tp
, MII_TG3_ISTAT
, &dummy
);
3158 tg3_readphy(tp
, MII_TG3_ISTAT
, &dummy
);
3160 if (tp
->tg3_flags
& TG3_FLAG_USE_MI_INTERRUPT
)
3161 tg3_writephy(tp
, MII_TG3_IMASK
, ~MII_TG3_INT_LINKCHG
);
3162 else if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
))
3163 tg3_writephy(tp
, MII_TG3_IMASK
, ~0);
3165 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
3166 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
3167 if (tp
->led_ctrl
== LED_CTRL_MODE_PHY_1
)
3168 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
3169 MII_TG3_EXT_CTRL_LNK3_LED_MODE
);
3171 tg3_writephy(tp
, MII_TG3_EXT_CTRL
, 0);
3174 current_link_up
= 0;
3175 current_speed
= SPEED_INVALID
;
3176 current_duplex
= DUPLEX_INVALID
;
3178 if (tp
->tg3_flags2
& TG3_FLG2_CAPACITIVE_COUPLING
) {
3181 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4007);
3182 tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &val
);
3183 if (!(val
& (1 << 10))) {
3185 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, val
);
3191 for (i
= 0; i
< 100; i
++) {
3192 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3193 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
3194 (bmsr
& BMSR_LSTATUS
))
3199 if (bmsr
& BMSR_LSTATUS
) {
3202 tg3_readphy(tp
, MII_TG3_AUX_STAT
, &aux_stat
);
3203 for (i
= 0; i
< 2000; i
++) {
3205 if (!tg3_readphy(tp
, MII_TG3_AUX_STAT
, &aux_stat
) &&
3210 tg3_aux_stat_to_speed_duplex(tp
, aux_stat
,
3215 for (i
= 0; i
< 200; i
++) {
3216 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
3217 if (tg3_readphy(tp
, MII_BMCR
, &bmcr
))
3219 if (bmcr
&& bmcr
!= 0x7fff)
3227 tp
->link_config
.active_speed
= current_speed
;
3228 tp
->link_config
.active_duplex
= current_duplex
;
3230 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) {
3231 if ((bmcr
& BMCR_ANENABLE
) &&
3232 tg3_copper_is_advertising_all(tp
,
3233 tp
->link_config
.advertising
)) {
3234 if (tg3_adv_1000T_flowctrl_ok(tp
, &lcl_adv
,
3236 current_link_up
= 1;
3239 if (!(bmcr
& BMCR_ANENABLE
) &&
3240 tp
->link_config
.speed
== current_speed
&&
3241 tp
->link_config
.duplex
== current_duplex
&&
3242 tp
->link_config
.flowctrl
==
3243 tp
->link_config
.active_flowctrl
) {
3244 current_link_up
= 1;
3248 if (current_link_up
== 1 &&
3249 tp
->link_config
.active_duplex
== DUPLEX_FULL
)
3250 tg3_setup_flow_control(tp
, lcl_adv
, rmt_adv
);
3254 if (current_link_up
== 0 || tp
->link_config
.phy_is_low_power
) {
3257 tg3_phy_copper_begin(tp
);
3259 tg3_readphy(tp
, MII_BMSR
, &tmp
);
3260 if (!tg3_readphy(tp
, MII_BMSR
, &tmp
) &&
3261 (tmp
& BMSR_LSTATUS
))
3262 current_link_up
= 1;
3265 tp
->mac_mode
&= ~MAC_MODE_PORT_MODE_MASK
;
3266 if (current_link_up
== 1) {
3267 if (tp
->link_config
.active_speed
== SPEED_100
||
3268 tp
->link_config
.active_speed
== SPEED_10
)
3269 tp
->mac_mode
|= MAC_MODE_PORT_MODE_MII
;
3271 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
3272 } else if (tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
)
3273 tp
->mac_mode
|= MAC_MODE_PORT_MODE_MII
;
3275 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
3277 tp
->mac_mode
&= ~MAC_MODE_HALF_DUPLEX
;
3278 if (tp
->link_config
.active_duplex
== DUPLEX_HALF
)
3279 tp
->mac_mode
|= MAC_MODE_HALF_DUPLEX
;
3281 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) {
3282 if (current_link_up
== 1 &&
3283 tg3_5700_link_polarity(tp
, tp
->link_config
.active_speed
))
3284 tp
->mac_mode
|= MAC_MODE_LINK_POLARITY
;
3286 tp
->mac_mode
&= ~MAC_MODE_LINK_POLARITY
;
3289 /* ??? Without this setting Netgear GA302T PHY does not
3290 * ??? send/receive packets...
3292 if ((tp
->phy_id
& TG3_PHY_ID_MASK
) == TG3_PHY_ID_BCM5411
&&
3293 tp
->pci_chip_rev_id
== CHIPREV_ID_5700_ALTIMA
) {
3294 tp
->mi_mode
|= MAC_MI_MODE_AUTO_POLL
;
3295 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
3299 tw32_f(MAC_MODE
, tp
->mac_mode
);
3302 if (tp
->tg3_flags
& TG3_FLAG_USE_LINKCHG_REG
) {
3303 /* Polled via timer. */
3304 tw32_f(MAC_EVENT
, 0);
3306 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
3310 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
&&
3311 current_link_up
== 1 &&
3312 tp
->link_config
.active_speed
== SPEED_1000
&&
3313 ((tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) ||
3314 (tp
->tg3_flags
& TG3_FLAG_PCI_HIGH_SPEED
))) {
3317 (MAC_STATUS_SYNC_CHANGED
|
3318 MAC_STATUS_CFG_CHANGED
));
3321 NIC_SRAM_FIRMWARE_MBOX
,
3322 NIC_SRAM_FIRMWARE_MBOX_MAGIC2
);
3325 /* Prevent send BD corruption. */
3326 if (tp
->tg3_flags3
& TG3_FLG3_CLKREQ_BUG
) {
3327 u16 oldlnkctl
, newlnkctl
;
3329 pci_read_config_word(tp
->pdev
,
3330 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
3332 if (tp
->link_config
.active_speed
== SPEED_100
||
3333 tp
->link_config
.active_speed
== SPEED_10
)
3334 newlnkctl
= oldlnkctl
& ~PCI_EXP_LNKCTL_CLKREQ_EN
;
3336 newlnkctl
= oldlnkctl
| PCI_EXP_LNKCTL_CLKREQ_EN
;
3337 if (newlnkctl
!= oldlnkctl
)
3338 pci_write_config_word(tp
->pdev
,
3339 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
3343 if (current_link_up
!= netif_carrier_ok(tp
->dev
)) {
3344 if (current_link_up
)
3345 netif_carrier_on(tp
->dev
);
3347 netif_carrier_off(tp
->dev
);
3348 tg3_link_report(tp
);
3354 struct tg3_fiber_aneginfo
{
3356 #define ANEG_STATE_UNKNOWN 0
3357 #define ANEG_STATE_AN_ENABLE 1
3358 #define ANEG_STATE_RESTART_INIT 2
3359 #define ANEG_STATE_RESTART 3
3360 #define ANEG_STATE_DISABLE_LINK_OK 4
3361 #define ANEG_STATE_ABILITY_DETECT_INIT 5
3362 #define ANEG_STATE_ABILITY_DETECT 6
3363 #define ANEG_STATE_ACK_DETECT_INIT 7
3364 #define ANEG_STATE_ACK_DETECT 8
3365 #define ANEG_STATE_COMPLETE_ACK_INIT 9
3366 #define ANEG_STATE_COMPLETE_ACK 10
3367 #define ANEG_STATE_IDLE_DETECT_INIT 11
3368 #define ANEG_STATE_IDLE_DETECT 12
3369 #define ANEG_STATE_LINK_OK 13
3370 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3371 #define ANEG_STATE_NEXT_PAGE_WAIT 15
3374 #define MR_AN_ENABLE 0x00000001
3375 #define MR_RESTART_AN 0x00000002
3376 #define MR_AN_COMPLETE 0x00000004
3377 #define MR_PAGE_RX 0x00000008
3378 #define MR_NP_LOADED 0x00000010
3379 #define MR_TOGGLE_TX 0x00000020
3380 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
3381 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
3382 #define MR_LP_ADV_SYM_PAUSE 0x00000100
3383 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
3384 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3385 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3386 #define MR_LP_ADV_NEXT_PAGE 0x00001000
3387 #define MR_TOGGLE_RX 0x00002000
3388 #define MR_NP_RX 0x00004000
3390 #define MR_LINK_OK 0x80000000
3392 unsigned long link_time
, cur_time
;
3394 u32 ability_match_cfg
;
3395 int ability_match_count
;
3397 char ability_match
, idle_match
, ack_match
;
3399 u32 txconfig
, rxconfig
;
3400 #define ANEG_CFG_NP 0x00000080
3401 #define ANEG_CFG_ACK 0x00000040
3402 #define ANEG_CFG_RF2 0x00000020
3403 #define ANEG_CFG_RF1 0x00000010
3404 #define ANEG_CFG_PS2 0x00000001
3405 #define ANEG_CFG_PS1 0x00008000
3406 #define ANEG_CFG_HD 0x00004000
3407 #define ANEG_CFG_FD 0x00002000
3408 #define ANEG_CFG_INVAL 0x00001f06
3413 #define ANEG_TIMER_ENAB 2
3414 #define ANEG_FAILED -1
3416 #define ANEG_STATE_SETTLE_TIME 10000
3418 static int tg3_fiber_aneg_smachine(struct tg3
*tp
,
3419 struct tg3_fiber_aneginfo
*ap
)
3422 unsigned long delta
;
3426 if (ap
->state
== ANEG_STATE_UNKNOWN
) {
3430 ap
->ability_match_cfg
= 0;
3431 ap
->ability_match_count
= 0;
3432 ap
->ability_match
= 0;
3438 if (tr32(MAC_STATUS
) & MAC_STATUS_RCVD_CFG
) {
3439 rx_cfg_reg
= tr32(MAC_RX_AUTO_NEG
);
3441 if (rx_cfg_reg
!= ap
->ability_match_cfg
) {
3442 ap
->ability_match_cfg
= rx_cfg_reg
;
3443 ap
->ability_match
= 0;
3444 ap
->ability_match_count
= 0;
3446 if (++ap
->ability_match_count
> 1) {
3447 ap
->ability_match
= 1;
3448 ap
->ability_match_cfg
= rx_cfg_reg
;
3451 if (rx_cfg_reg
& ANEG_CFG_ACK
)
3459 ap
->ability_match_cfg
= 0;
3460 ap
->ability_match_count
= 0;
3461 ap
->ability_match
= 0;
3467 ap
->rxconfig
= rx_cfg_reg
;
3470 switch (ap
->state
) {
3471 case ANEG_STATE_UNKNOWN
:
3472 if (ap
->flags
& (MR_AN_ENABLE
| MR_RESTART_AN
))
3473 ap
->state
= ANEG_STATE_AN_ENABLE
;
3476 case ANEG_STATE_AN_ENABLE
:
3477 ap
->flags
&= ~(MR_AN_COMPLETE
| MR_PAGE_RX
);
3478 if (ap
->flags
& MR_AN_ENABLE
) {
3481 ap
->ability_match_cfg
= 0;
3482 ap
->ability_match_count
= 0;
3483 ap
->ability_match
= 0;
3487 ap
->state
= ANEG_STATE_RESTART_INIT
;
3489 ap
->state
= ANEG_STATE_DISABLE_LINK_OK
;
3493 case ANEG_STATE_RESTART_INIT
:
3494 ap
->link_time
= ap
->cur_time
;
3495 ap
->flags
&= ~(MR_NP_LOADED
);
3497 tw32(MAC_TX_AUTO_NEG
, 0);
3498 tp
->mac_mode
|= MAC_MODE_SEND_CONFIGS
;
3499 tw32_f(MAC_MODE
, tp
->mac_mode
);
3502 ret
= ANEG_TIMER_ENAB
;
3503 ap
->state
= ANEG_STATE_RESTART
;
3506 case ANEG_STATE_RESTART
:
3507 delta
= ap
->cur_time
- ap
->link_time
;
3508 if (delta
> ANEG_STATE_SETTLE_TIME
)
3509 ap
->state
= ANEG_STATE_ABILITY_DETECT_INIT
;
3511 ret
= ANEG_TIMER_ENAB
;
3514 case ANEG_STATE_DISABLE_LINK_OK
:
3518 case ANEG_STATE_ABILITY_DETECT_INIT
:
3519 ap
->flags
&= ~(MR_TOGGLE_TX
);
3520 ap
->txconfig
= ANEG_CFG_FD
;
3521 flowctrl
= tg3_advert_flowctrl_1000X(tp
->link_config
.flowctrl
);
3522 if (flowctrl
& ADVERTISE_1000XPAUSE
)
3523 ap
->txconfig
|= ANEG_CFG_PS1
;
3524 if (flowctrl
& ADVERTISE_1000XPSE_ASYM
)
3525 ap
->txconfig
|= ANEG_CFG_PS2
;
3526 tw32(MAC_TX_AUTO_NEG
, ap
->txconfig
);
3527 tp
->mac_mode
|= MAC_MODE_SEND_CONFIGS
;
3528 tw32_f(MAC_MODE
, tp
->mac_mode
);
3531 ap
->state
= ANEG_STATE_ABILITY_DETECT
;
3534 case ANEG_STATE_ABILITY_DETECT
:
3535 if (ap
->ability_match
!= 0 && ap
->rxconfig
!= 0)
3536 ap
->state
= ANEG_STATE_ACK_DETECT_INIT
;
3539 case ANEG_STATE_ACK_DETECT_INIT
:
3540 ap
->txconfig
|= ANEG_CFG_ACK
;
3541 tw32(MAC_TX_AUTO_NEG
, ap
->txconfig
);
3542 tp
->mac_mode
|= MAC_MODE_SEND_CONFIGS
;
3543 tw32_f(MAC_MODE
, tp
->mac_mode
);
3546 ap
->state
= ANEG_STATE_ACK_DETECT
;
3549 case ANEG_STATE_ACK_DETECT
:
3550 if (ap
->ack_match
!= 0) {
3551 if ((ap
->rxconfig
& ~ANEG_CFG_ACK
) ==
3552 (ap
->ability_match_cfg
& ~ANEG_CFG_ACK
)) {
3553 ap
->state
= ANEG_STATE_COMPLETE_ACK_INIT
;
3555 ap
->state
= ANEG_STATE_AN_ENABLE
;
3557 } else if (ap
->ability_match
!= 0 &&
3558 ap
->rxconfig
== 0) {
3559 ap
->state
= ANEG_STATE_AN_ENABLE
;
3563 case ANEG_STATE_COMPLETE_ACK_INIT
:
3564 if (ap
->rxconfig
& ANEG_CFG_INVAL
) {
3568 ap
->flags
&= ~(MR_LP_ADV_FULL_DUPLEX
|
3569 MR_LP_ADV_HALF_DUPLEX
|
3570 MR_LP_ADV_SYM_PAUSE
|
3571 MR_LP_ADV_ASYM_PAUSE
|
3572 MR_LP_ADV_REMOTE_FAULT1
|
3573 MR_LP_ADV_REMOTE_FAULT2
|
3574 MR_LP_ADV_NEXT_PAGE
|
3577 if (ap
->rxconfig
& ANEG_CFG_FD
)
3578 ap
->flags
|= MR_LP_ADV_FULL_DUPLEX
;
3579 if (ap
->rxconfig
& ANEG_CFG_HD
)
3580 ap
->flags
|= MR_LP_ADV_HALF_DUPLEX
;
3581 if (ap
->rxconfig
& ANEG_CFG_PS1
)
3582 ap
->flags
|= MR_LP_ADV_SYM_PAUSE
;
3583 if (ap
->rxconfig
& ANEG_CFG_PS2
)
3584 ap
->flags
|= MR_LP_ADV_ASYM_PAUSE
;
3585 if (ap
->rxconfig
& ANEG_CFG_RF1
)
3586 ap
->flags
|= MR_LP_ADV_REMOTE_FAULT1
;
3587 if (ap
->rxconfig
& ANEG_CFG_RF2
)
3588 ap
->flags
|= MR_LP_ADV_REMOTE_FAULT2
;
3589 if (ap
->rxconfig
& ANEG_CFG_NP
)
3590 ap
->flags
|= MR_LP_ADV_NEXT_PAGE
;
3592 ap
->link_time
= ap
->cur_time
;
3594 ap
->flags
^= (MR_TOGGLE_TX
);
3595 if (ap
->rxconfig
& 0x0008)
3596 ap
->flags
|= MR_TOGGLE_RX
;
3597 if (ap
->rxconfig
& ANEG_CFG_NP
)
3598 ap
->flags
|= MR_NP_RX
;
3599 ap
->flags
|= MR_PAGE_RX
;
3601 ap
->state
= ANEG_STATE_COMPLETE_ACK
;
3602 ret
= ANEG_TIMER_ENAB
;
3605 case ANEG_STATE_COMPLETE_ACK
:
3606 if (ap
->ability_match
!= 0 &&
3607 ap
->rxconfig
== 0) {
3608 ap
->state
= ANEG_STATE_AN_ENABLE
;
3611 delta
= ap
->cur_time
- ap
->link_time
;
3612 if (delta
> ANEG_STATE_SETTLE_TIME
) {
3613 if (!(ap
->flags
& (MR_LP_ADV_NEXT_PAGE
))) {
3614 ap
->state
= ANEG_STATE_IDLE_DETECT_INIT
;
3616 if ((ap
->txconfig
& ANEG_CFG_NP
) == 0 &&
3617 !(ap
->flags
& MR_NP_RX
)) {
3618 ap
->state
= ANEG_STATE_IDLE_DETECT_INIT
;
3626 case ANEG_STATE_IDLE_DETECT_INIT
:
3627 ap
->link_time
= ap
->cur_time
;
3628 tp
->mac_mode
&= ~MAC_MODE_SEND_CONFIGS
;
3629 tw32_f(MAC_MODE
, tp
->mac_mode
);
3632 ap
->state
= ANEG_STATE_IDLE_DETECT
;
3633 ret
= ANEG_TIMER_ENAB
;
3636 case ANEG_STATE_IDLE_DETECT
:
3637 if (ap
->ability_match
!= 0 &&
3638 ap
->rxconfig
== 0) {
3639 ap
->state
= ANEG_STATE_AN_ENABLE
;
3642 delta
= ap
->cur_time
- ap
->link_time
;
3643 if (delta
> ANEG_STATE_SETTLE_TIME
) {
3644 /* XXX another gem from the Broadcom driver :( */
3645 ap
->state
= ANEG_STATE_LINK_OK
;
3649 case ANEG_STATE_LINK_OK
:
3650 ap
->flags
|= (MR_AN_COMPLETE
| MR_LINK_OK
);
3654 case ANEG_STATE_NEXT_PAGE_WAIT_INIT
:
3655 /* ??? unimplemented */
3658 case ANEG_STATE_NEXT_PAGE_WAIT
:
3659 /* ??? unimplemented */
3670 static int fiber_autoneg(struct tg3
*tp
, u32
*txflags
, u32
*rxflags
)
3673 struct tg3_fiber_aneginfo aninfo
;
3674 int status
= ANEG_FAILED
;
3678 tw32_f(MAC_TX_AUTO_NEG
, 0);
3680 tmp
= tp
->mac_mode
& ~MAC_MODE_PORT_MODE_MASK
;
3681 tw32_f(MAC_MODE
, tmp
| MAC_MODE_PORT_MODE_GMII
);
3684 tw32_f(MAC_MODE
, tp
->mac_mode
| MAC_MODE_SEND_CONFIGS
);
3687 memset(&aninfo
, 0, sizeof(aninfo
));
3688 aninfo
.flags
|= MR_AN_ENABLE
;
3689 aninfo
.state
= ANEG_STATE_UNKNOWN
;
3690 aninfo
.cur_time
= 0;
3692 while (++tick
< 195000) {
3693 status
= tg3_fiber_aneg_smachine(tp
, &aninfo
);
3694 if (status
== ANEG_DONE
|| status
== ANEG_FAILED
)
3700 tp
->mac_mode
&= ~MAC_MODE_SEND_CONFIGS
;
3701 tw32_f(MAC_MODE
, tp
->mac_mode
);
3704 *txflags
= aninfo
.txconfig
;
3705 *rxflags
= aninfo
.flags
;
3707 if (status
== ANEG_DONE
&&
3708 (aninfo
.flags
& (MR_AN_COMPLETE
| MR_LINK_OK
|
3709 MR_LP_ADV_FULL_DUPLEX
)))
3715 static void tg3_init_bcm8002(struct tg3
*tp
)
3717 u32 mac_status
= tr32(MAC_STATUS
);
3720 /* Reset when initting first time or we have a link. */
3721 if ((tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
) &&
3722 !(mac_status
& MAC_STATUS_PCS_SYNCED
))
3725 /* Set PLL lock range. */
3726 tg3_writephy(tp
, 0x16, 0x8007);
3729 tg3_writephy(tp
, MII_BMCR
, BMCR_RESET
);
3731 /* Wait for reset to complete. */
3732 /* XXX schedule_timeout() ... */
3733 for (i
= 0; i
< 500; i
++)
3736 /* Config mode; select PMA/Ch 1 regs. */
3737 tg3_writephy(tp
, 0x10, 0x8411);
3739 /* Enable auto-lock and comdet, select txclk for tx. */
3740 tg3_writephy(tp
, 0x11, 0x0a10);
3742 tg3_writephy(tp
, 0x18, 0x00a0);
3743 tg3_writephy(tp
, 0x16, 0x41ff);
3745 /* Assert and deassert POR. */
3746 tg3_writephy(tp
, 0x13, 0x0400);
3748 tg3_writephy(tp
, 0x13, 0x0000);
3750 tg3_writephy(tp
, 0x11, 0x0a50);
3752 tg3_writephy(tp
, 0x11, 0x0a10);
3754 /* Wait for signal to stabilize */
3755 /* XXX schedule_timeout() ... */
3756 for (i
= 0; i
< 15000; i
++)
3759 /* Deselect the channel register so we can read the PHYID
3762 tg3_writephy(tp
, 0x10, 0x8011);
3765 static int tg3_setup_fiber_hw_autoneg(struct tg3
*tp
, u32 mac_status
)
3768 u32 sg_dig_ctrl
, sg_dig_status
;
3769 u32 serdes_cfg
, expected_sg_dig_ctrl
;
3770 int workaround
, port_a
;
3771 int current_link_up
;
3774 expected_sg_dig_ctrl
= 0;
3777 current_link_up
= 0;
3779 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5704_A0
&&
3780 tp
->pci_chip_rev_id
!= CHIPREV_ID_5704_A1
) {
3782 if (tr32(TG3PCI_DUAL_MAC_CTRL
) & DUAL_MAC_CTRL_ID
)
3785 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3786 /* preserve bits 20-23 for voltage regulator */
3787 serdes_cfg
= tr32(MAC_SERDES_CFG
) & 0x00f06fff;
3790 sg_dig_ctrl
= tr32(SG_DIG_CTRL
);
3792 if (tp
->link_config
.autoneg
!= AUTONEG_ENABLE
) {
3793 if (sg_dig_ctrl
& SG_DIG_USING_HW_AUTONEG
) {
3795 u32 val
= serdes_cfg
;
3801 tw32_f(MAC_SERDES_CFG
, val
);
3804 tw32_f(SG_DIG_CTRL
, SG_DIG_COMMON_SETUP
);
3806 if (mac_status
& MAC_STATUS_PCS_SYNCED
) {
3807 tg3_setup_flow_control(tp
, 0, 0);
3808 current_link_up
= 1;
3813 /* Want auto-negotiation. */
3814 expected_sg_dig_ctrl
= SG_DIG_USING_HW_AUTONEG
| SG_DIG_COMMON_SETUP
;
3816 flowctrl
= tg3_advert_flowctrl_1000X(tp
->link_config
.flowctrl
);
3817 if (flowctrl
& ADVERTISE_1000XPAUSE
)
3818 expected_sg_dig_ctrl
|= SG_DIG_PAUSE_CAP
;
3819 if (flowctrl
& ADVERTISE_1000XPSE_ASYM
)
3820 expected_sg_dig_ctrl
|= SG_DIG_ASYM_PAUSE
;
3822 if (sg_dig_ctrl
!= expected_sg_dig_ctrl
) {
3823 if ((tp
->tg3_flags2
& TG3_FLG2_PARALLEL_DETECT
) &&
3824 tp
->serdes_counter
&&
3825 ((mac_status
& (MAC_STATUS_PCS_SYNCED
|
3826 MAC_STATUS_RCVD_CFG
)) ==
3827 MAC_STATUS_PCS_SYNCED
)) {
3828 tp
->serdes_counter
--;
3829 current_link_up
= 1;
3834 tw32_f(MAC_SERDES_CFG
, serdes_cfg
| 0xc011000);
3835 tw32_f(SG_DIG_CTRL
, expected_sg_dig_ctrl
| SG_DIG_SOFT_RESET
);
3837 tw32_f(SG_DIG_CTRL
, expected_sg_dig_ctrl
);
3839 tp
->serdes_counter
= SERDES_AN_TIMEOUT_5704S
;
3840 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
3841 } else if (mac_status
& (MAC_STATUS_PCS_SYNCED
|
3842 MAC_STATUS_SIGNAL_DET
)) {
3843 sg_dig_status
= tr32(SG_DIG_STATUS
);
3844 mac_status
= tr32(MAC_STATUS
);
3846 if ((sg_dig_status
& SG_DIG_AUTONEG_COMPLETE
) &&
3847 (mac_status
& MAC_STATUS_PCS_SYNCED
)) {
3848 u32 local_adv
= 0, remote_adv
= 0;
3850 if (sg_dig_ctrl
& SG_DIG_PAUSE_CAP
)
3851 local_adv
|= ADVERTISE_1000XPAUSE
;
3852 if (sg_dig_ctrl
& SG_DIG_ASYM_PAUSE
)
3853 local_adv
|= ADVERTISE_1000XPSE_ASYM
;
3855 if (sg_dig_status
& SG_DIG_PARTNER_PAUSE_CAPABLE
)
3856 remote_adv
|= LPA_1000XPAUSE
;
3857 if (sg_dig_status
& SG_DIG_PARTNER_ASYM_PAUSE
)
3858 remote_adv
|= LPA_1000XPAUSE_ASYM
;
3860 tg3_setup_flow_control(tp
, local_adv
, remote_adv
);
3861 current_link_up
= 1;
3862 tp
->serdes_counter
= 0;
3863 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
3864 } else if (!(sg_dig_status
& SG_DIG_AUTONEG_COMPLETE
)) {
3865 if (tp
->serdes_counter
)
3866 tp
->serdes_counter
--;
3869 u32 val
= serdes_cfg
;
3876 tw32_f(MAC_SERDES_CFG
, val
);
3879 tw32_f(SG_DIG_CTRL
, SG_DIG_COMMON_SETUP
);
3882 /* Link parallel detection - link is up */
3883 /* only if we have PCS_SYNC and not */
3884 /* receiving config code words */
3885 mac_status
= tr32(MAC_STATUS
);
3886 if ((mac_status
& MAC_STATUS_PCS_SYNCED
) &&
3887 !(mac_status
& MAC_STATUS_RCVD_CFG
)) {
3888 tg3_setup_flow_control(tp
, 0, 0);
3889 current_link_up
= 1;
3891 TG3_FLG2_PARALLEL_DETECT
;
3892 tp
->serdes_counter
=
3893 SERDES_PARALLEL_DET_TIMEOUT
;
3895 goto restart_autoneg
;
3899 tp
->serdes_counter
= SERDES_AN_TIMEOUT_5704S
;
3900 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
3904 return current_link_up
;
3907 static int tg3_setup_fiber_by_hand(struct tg3
*tp
, u32 mac_status
)
3909 int current_link_up
= 0;
3911 if (!(mac_status
& MAC_STATUS_PCS_SYNCED
))
3914 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) {
3915 u32 txflags
, rxflags
;
3918 if (fiber_autoneg(tp
, &txflags
, &rxflags
)) {
3919 u32 local_adv
= 0, remote_adv
= 0;
3921 if (txflags
& ANEG_CFG_PS1
)
3922 local_adv
|= ADVERTISE_1000XPAUSE
;
3923 if (txflags
& ANEG_CFG_PS2
)
3924 local_adv
|= ADVERTISE_1000XPSE_ASYM
;
3926 if (rxflags
& MR_LP_ADV_SYM_PAUSE
)
3927 remote_adv
|= LPA_1000XPAUSE
;
3928 if (rxflags
& MR_LP_ADV_ASYM_PAUSE
)
3929 remote_adv
|= LPA_1000XPAUSE_ASYM
;
3931 tg3_setup_flow_control(tp
, local_adv
, remote_adv
);
3933 current_link_up
= 1;
3935 for (i
= 0; i
< 30; i
++) {
3938 (MAC_STATUS_SYNC_CHANGED
|
3939 MAC_STATUS_CFG_CHANGED
));
3941 if ((tr32(MAC_STATUS
) &
3942 (MAC_STATUS_SYNC_CHANGED
|
3943 MAC_STATUS_CFG_CHANGED
)) == 0)
3947 mac_status
= tr32(MAC_STATUS
);
3948 if (current_link_up
== 0 &&
3949 (mac_status
& MAC_STATUS_PCS_SYNCED
) &&
3950 !(mac_status
& MAC_STATUS_RCVD_CFG
))
3951 current_link_up
= 1;
3953 tg3_setup_flow_control(tp
, 0, 0);
3955 /* Forcing 1000FD link up. */
3956 current_link_up
= 1;
3958 tw32_f(MAC_MODE
, (tp
->mac_mode
| MAC_MODE_SEND_CONFIGS
));
3961 tw32_f(MAC_MODE
, tp
->mac_mode
);
3966 return current_link_up
;
3969 static int tg3_setup_fiber_phy(struct tg3
*tp
, int force_reset
)
3972 u16 orig_active_speed
;
3973 u8 orig_active_duplex
;
3975 int current_link_up
;
3978 orig_pause_cfg
= tp
->link_config
.active_flowctrl
;
3979 orig_active_speed
= tp
->link_config
.active_speed
;
3980 orig_active_duplex
= tp
->link_config
.active_duplex
;
3982 if (!(tp
->tg3_flags2
& TG3_FLG2_HW_AUTONEG
) &&
3983 netif_carrier_ok(tp
->dev
) &&
3984 (tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
)) {
3985 mac_status
= tr32(MAC_STATUS
);
3986 mac_status
&= (MAC_STATUS_PCS_SYNCED
|
3987 MAC_STATUS_SIGNAL_DET
|
3988 MAC_STATUS_CFG_CHANGED
|
3989 MAC_STATUS_RCVD_CFG
);
3990 if (mac_status
== (MAC_STATUS_PCS_SYNCED
|
3991 MAC_STATUS_SIGNAL_DET
)) {
3992 tw32_f(MAC_STATUS
, (MAC_STATUS_SYNC_CHANGED
|
3993 MAC_STATUS_CFG_CHANGED
));
3998 tw32_f(MAC_TX_AUTO_NEG
, 0);
4000 tp
->mac_mode
&= ~(MAC_MODE_PORT_MODE_MASK
| MAC_MODE_HALF_DUPLEX
);
4001 tp
->mac_mode
|= MAC_MODE_PORT_MODE_TBI
;
4002 tw32_f(MAC_MODE
, tp
->mac_mode
);
4005 if (tp
->phy_id
== TG3_PHY_ID_BCM8002
)
4006 tg3_init_bcm8002(tp
);
4008 /* Enable link change event even when serdes polling. */
4009 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
4012 current_link_up
= 0;
4013 mac_status
= tr32(MAC_STATUS
);
4015 if (tp
->tg3_flags2
& TG3_FLG2_HW_AUTONEG
)
4016 current_link_up
= tg3_setup_fiber_hw_autoneg(tp
, mac_status
);
4018 current_link_up
= tg3_setup_fiber_by_hand(tp
, mac_status
);
4020 tp
->napi
[0].hw_status
->status
=
4021 (SD_STATUS_UPDATED
|
4022 (tp
->napi
[0].hw_status
->status
& ~SD_STATUS_LINK_CHG
));
4024 for (i
= 0; i
< 100; i
++) {
4025 tw32_f(MAC_STATUS
, (MAC_STATUS_SYNC_CHANGED
|
4026 MAC_STATUS_CFG_CHANGED
));
4028 if ((tr32(MAC_STATUS
) & (MAC_STATUS_SYNC_CHANGED
|
4029 MAC_STATUS_CFG_CHANGED
|
4030 MAC_STATUS_LNKSTATE_CHANGED
)) == 0)
4034 mac_status
= tr32(MAC_STATUS
);
4035 if ((mac_status
& MAC_STATUS_PCS_SYNCED
) == 0) {
4036 current_link_up
= 0;
4037 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
&&
4038 tp
->serdes_counter
== 0) {
4039 tw32_f(MAC_MODE
, (tp
->mac_mode
|
4040 MAC_MODE_SEND_CONFIGS
));
4042 tw32_f(MAC_MODE
, tp
->mac_mode
);
4046 if (current_link_up
== 1) {
4047 tp
->link_config
.active_speed
= SPEED_1000
;
4048 tp
->link_config
.active_duplex
= DUPLEX_FULL
;
4049 tw32(MAC_LED_CTRL
, (tp
->led_ctrl
|
4050 LED_CTRL_LNKLED_OVERRIDE
|
4051 LED_CTRL_1000MBPS_ON
));
4053 tp
->link_config
.active_speed
= SPEED_INVALID
;
4054 tp
->link_config
.active_duplex
= DUPLEX_INVALID
;
4055 tw32(MAC_LED_CTRL
, (tp
->led_ctrl
|
4056 LED_CTRL_LNKLED_OVERRIDE
|
4057 LED_CTRL_TRAFFIC_OVERRIDE
));
4060 if (current_link_up
!= netif_carrier_ok(tp
->dev
)) {
4061 if (current_link_up
)
4062 netif_carrier_on(tp
->dev
);
4064 netif_carrier_off(tp
->dev
);
4065 tg3_link_report(tp
);
4067 u32 now_pause_cfg
= tp
->link_config
.active_flowctrl
;
4068 if (orig_pause_cfg
!= now_pause_cfg
||
4069 orig_active_speed
!= tp
->link_config
.active_speed
||
4070 orig_active_duplex
!= tp
->link_config
.active_duplex
)
4071 tg3_link_report(tp
);
4077 static int tg3_setup_fiber_mii_phy(struct tg3
*tp
, int force_reset
)
4079 int current_link_up
, err
= 0;
4083 u32 local_adv
, remote_adv
;
4085 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
4086 tw32_f(MAC_MODE
, tp
->mac_mode
);
4092 (MAC_STATUS_SYNC_CHANGED
|
4093 MAC_STATUS_CFG_CHANGED
|
4094 MAC_STATUS_MI_COMPLETION
|
4095 MAC_STATUS_LNKSTATE_CHANGED
));
4101 current_link_up
= 0;
4102 current_speed
= SPEED_INVALID
;
4103 current_duplex
= DUPLEX_INVALID
;
4105 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
4106 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
4107 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
) {
4108 if (tr32(MAC_TX_STATUS
) & TX_STATUS_LINK_UP
)
4109 bmsr
|= BMSR_LSTATUS
;
4111 bmsr
&= ~BMSR_LSTATUS
;
4114 err
|= tg3_readphy(tp
, MII_BMCR
, &bmcr
);
4116 if ((tp
->link_config
.autoneg
== AUTONEG_ENABLE
) && !force_reset
&&
4117 (tp
->tg3_flags2
& TG3_FLG2_PARALLEL_DETECT
)) {
4118 /* do nothing, just check for link up at the end */
4119 } else if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) {
4122 err
|= tg3_readphy(tp
, MII_ADVERTISE
, &adv
);
4123 new_adv
= adv
& ~(ADVERTISE_1000XFULL
| ADVERTISE_1000XHALF
|
4124 ADVERTISE_1000XPAUSE
|
4125 ADVERTISE_1000XPSE_ASYM
|
4128 new_adv
|= tg3_advert_flowctrl_1000X(tp
->link_config
.flowctrl
);
4130 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Half
)
4131 new_adv
|= ADVERTISE_1000XHALF
;
4132 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Full
)
4133 new_adv
|= ADVERTISE_1000XFULL
;
4135 if ((new_adv
!= adv
) || !(bmcr
& BMCR_ANENABLE
)) {
4136 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
4137 bmcr
|= BMCR_ANENABLE
| BMCR_ANRESTART
;
4138 tg3_writephy(tp
, MII_BMCR
, bmcr
);
4140 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
4141 tp
->serdes_counter
= SERDES_AN_TIMEOUT_5714S
;
4142 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
4149 bmcr
&= ~BMCR_SPEED1000
;
4150 new_bmcr
= bmcr
& ~(BMCR_ANENABLE
| BMCR_FULLDPLX
);
4152 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
4153 new_bmcr
|= BMCR_FULLDPLX
;
4155 if (new_bmcr
!= bmcr
) {
4156 /* BMCR_SPEED1000 is a reserved bit that needs
4157 * to be set on write.
4159 new_bmcr
|= BMCR_SPEED1000
;
4161 /* Force a linkdown */
4162 if (netif_carrier_ok(tp
->dev
)) {
4165 err
|= tg3_readphy(tp
, MII_ADVERTISE
, &adv
);
4166 adv
&= ~(ADVERTISE_1000XFULL
|
4167 ADVERTISE_1000XHALF
|
4169 tg3_writephy(tp
, MII_ADVERTISE
, adv
);
4170 tg3_writephy(tp
, MII_BMCR
, bmcr
|
4174 netif_carrier_off(tp
->dev
);
4176 tg3_writephy(tp
, MII_BMCR
, new_bmcr
);
4178 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
4179 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
4180 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
4182 if (tr32(MAC_TX_STATUS
) & TX_STATUS_LINK_UP
)
4183 bmsr
|= BMSR_LSTATUS
;
4185 bmsr
&= ~BMSR_LSTATUS
;
4187 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
4191 if (bmsr
& BMSR_LSTATUS
) {
4192 current_speed
= SPEED_1000
;
4193 current_link_up
= 1;
4194 if (bmcr
& BMCR_FULLDPLX
)
4195 current_duplex
= DUPLEX_FULL
;
4197 current_duplex
= DUPLEX_HALF
;
4202 if (bmcr
& BMCR_ANENABLE
) {
4205 err
|= tg3_readphy(tp
, MII_ADVERTISE
, &local_adv
);
4206 err
|= tg3_readphy(tp
, MII_LPA
, &remote_adv
);
4207 common
= local_adv
& remote_adv
;
4208 if (common
& (ADVERTISE_1000XHALF
|
4209 ADVERTISE_1000XFULL
)) {
4210 if (common
& ADVERTISE_1000XFULL
)
4211 current_duplex
= DUPLEX_FULL
;
4213 current_duplex
= DUPLEX_HALF
;
4214 } else if (!(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
4215 /* Link is up via parallel detect */
4217 current_link_up
= 0;
4222 if (current_link_up
== 1 && current_duplex
== DUPLEX_FULL
)
4223 tg3_setup_flow_control(tp
, local_adv
, remote_adv
);
4225 tp
->mac_mode
&= ~MAC_MODE_HALF_DUPLEX
;
4226 if (tp
->link_config
.active_duplex
== DUPLEX_HALF
)
4227 tp
->mac_mode
|= MAC_MODE_HALF_DUPLEX
;
4229 tw32_f(MAC_MODE
, tp
->mac_mode
);
4232 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
4234 tp
->link_config
.active_speed
= current_speed
;
4235 tp
->link_config
.active_duplex
= current_duplex
;
4237 if (current_link_up
!= netif_carrier_ok(tp
->dev
)) {
4238 if (current_link_up
)
4239 netif_carrier_on(tp
->dev
);
4241 netif_carrier_off(tp
->dev
);
4242 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
4244 tg3_link_report(tp
);
4249 static void tg3_serdes_parallel_detect(struct tg3
*tp
)
4251 if (tp
->serdes_counter
) {
4252 /* Give autoneg time to complete. */
4253 tp
->serdes_counter
--;
4257 if (!netif_carrier_ok(tp
->dev
) &&
4258 (tp
->link_config
.autoneg
== AUTONEG_ENABLE
)) {
4261 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
4262 if (bmcr
& BMCR_ANENABLE
) {
4265 /* Select shadow register 0x1f */
4266 tg3_writephy(tp
, 0x1c, 0x7c00);
4267 tg3_readphy(tp
, 0x1c, &phy1
);
4269 /* Select expansion interrupt status register */
4270 tg3_writephy(tp
, 0x17, 0x0f01);
4271 tg3_readphy(tp
, 0x15, &phy2
);
4272 tg3_readphy(tp
, 0x15, &phy2
);
4274 if ((phy1
& 0x10) && !(phy2
& 0x20)) {
4275 /* We have signal detect and not receiving
4276 * config code words, link is up by parallel
4280 bmcr
&= ~BMCR_ANENABLE
;
4281 bmcr
|= BMCR_SPEED1000
| BMCR_FULLDPLX
;
4282 tg3_writephy(tp
, MII_BMCR
, bmcr
);
4283 tp
->tg3_flags2
|= TG3_FLG2_PARALLEL_DETECT
;
4286 } else if (netif_carrier_ok(tp
->dev
) &&
4287 (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) &&
4288 (tp
->tg3_flags2
& TG3_FLG2_PARALLEL_DETECT
)) {
4291 /* Select expansion interrupt status register */
4292 tg3_writephy(tp
, 0x17, 0x0f01);
4293 tg3_readphy(tp
, 0x15, &phy2
);
4297 /* Config code words received, turn on autoneg. */
4298 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
4299 tg3_writephy(tp
, MII_BMCR
, bmcr
| BMCR_ANENABLE
);
4301 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
4307 static int tg3_setup_phy(struct tg3
*tp
, int force_reset
)
4311 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)
4312 err
= tg3_setup_fiber_phy(tp
, force_reset
);
4313 else if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
)
4314 err
= tg3_setup_fiber_mii_phy(tp
, force_reset
);
4316 err
= tg3_setup_copper_phy(tp
, force_reset
);
4318 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
) {
4321 val
= tr32(TG3_CPMU_CLCK_STAT
) & CPMU_CLCK_STAT_MAC_CLCK_MASK
;
4322 if (val
== CPMU_CLCK_STAT_MAC_CLCK_62_5
)
4324 else if (val
== CPMU_CLCK_STAT_MAC_CLCK_6_25
)
4329 val
= tr32(GRC_MISC_CFG
) & ~GRC_MISC_CFG_PRESCALAR_MASK
;
4330 val
|= (scale
<< GRC_MISC_CFG_PRESCALAR_SHIFT
);
4331 tw32(GRC_MISC_CFG
, val
);
4334 if (tp
->link_config
.active_speed
== SPEED_1000
&&
4335 tp
->link_config
.active_duplex
== DUPLEX_HALF
)
4336 tw32(MAC_TX_LENGTHS
,
4337 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
4338 (6 << TX_LENGTHS_IPG_SHIFT
) |
4339 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT
)));
4341 tw32(MAC_TX_LENGTHS
,
4342 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
4343 (6 << TX_LENGTHS_IPG_SHIFT
) |
4344 (32 << TX_LENGTHS_SLOT_TIME_SHIFT
)));
4346 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
4347 if (netif_carrier_ok(tp
->dev
)) {
4348 tw32(HOSTCC_STAT_COAL_TICKS
,
4349 tp
->coal
.stats_block_coalesce_usecs
);
4351 tw32(HOSTCC_STAT_COAL_TICKS
, 0);
4355 if (tp
->tg3_flags
& TG3_FLAG_ASPM_WORKAROUND
) {
4356 u32 val
= tr32(PCIE_PWR_MGMT_THRESH
);
4357 if (!netif_carrier_ok(tp
->dev
))
4358 val
= (val
& ~PCIE_PWR_MGMT_L1_THRESH_MSK
) |
4361 val
|= PCIE_PWR_MGMT_L1_THRESH_MSK
;
4362 tw32(PCIE_PWR_MGMT_THRESH
, val
);
4368 /* This is called whenever we suspect that the system chipset is re-
4369 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4370 * is bogus tx completions. We try to recover by setting the
4371 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4374 static void tg3_tx_recover(struct tg3
*tp
)
4376 BUG_ON((tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
) ||
4377 tp
->write32_tx_mbox
== tg3_write_indirect_mbox
);
4379 netdev_warn(tp
->dev
,
4380 "The system may be re-ordering memory-mapped I/O "
4381 "cycles to the network device, attempting to recover. "
4382 "Please report the problem to the driver maintainer "
4383 "and include system chipset information.\n");
4385 spin_lock(&tp
->lock
);
4386 tp
->tg3_flags
|= TG3_FLAG_TX_RECOVERY_PENDING
;
4387 spin_unlock(&tp
->lock
);
4390 static inline u32
tg3_tx_avail(struct tg3_napi
*tnapi
)
4393 return tnapi
->tx_pending
-
4394 ((tnapi
->tx_prod
- tnapi
->tx_cons
) & (TG3_TX_RING_SIZE
- 1));
4397 /* Tigon3 never reports partial packet sends. So we do not
4398 * need special logic to handle SKBs that have not had all
4399 * of their frags sent yet, like SunGEM does.
4401 static void tg3_tx(struct tg3_napi
*tnapi
)
4403 struct tg3
*tp
= tnapi
->tp
;
4404 u32 hw_idx
= tnapi
->hw_status
->idx
[0].tx_consumer
;
4405 u32 sw_idx
= tnapi
->tx_cons
;
4406 struct netdev_queue
*txq
;
4407 int index
= tnapi
- tp
->napi
;
4409 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)
4412 txq
= netdev_get_tx_queue(tp
->dev
, index
);
4414 while (sw_idx
!= hw_idx
) {
4415 struct ring_info
*ri
= &tnapi
->tx_buffers
[sw_idx
];
4416 struct sk_buff
*skb
= ri
->skb
;
4419 if (unlikely(skb
== NULL
)) {
4424 pci_unmap_single(tp
->pdev
,
4425 dma_unmap_addr(ri
, mapping
),
4431 sw_idx
= NEXT_TX(sw_idx
);
4433 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
4434 ri
= &tnapi
->tx_buffers
[sw_idx
];
4435 if (unlikely(ri
->skb
!= NULL
|| sw_idx
== hw_idx
))
4438 pci_unmap_page(tp
->pdev
,
4439 dma_unmap_addr(ri
, mapping
),
4440 skb_shinfo(skb
)->frags
[i
].size
,
4442 sw_idx
= NEXT_TX(sw_idx
);
4447 if (unlikely(tx_bug
)) {
4453 tnapi
->tx_cons
= sw_idx
;
4455 /* Need to make the tx_cons update visible to tg3_start_xmit()
4456 * before checking for netif_queue_stopped(). Without the
4457 * memory barrier, there is a small possibility that tg3_start_xmit()
4458 * will miss it and cause the queue to be stopped forever.
4462 if (unlikely(netif_tx_queue_stopped(txq
) &&
4463 (tg3_tx_avail(tnapi
) > TG3_TX_WAKEUP_THRESH(tnapi
)))) {
4464 __netif_tx_lock(txq
, smp_processor_id());
4465 if (netif_tx_queue_stopped(txq
) &&
4466 (tg3_tx_avail(tnapi
) > TG3_TX_WAKEUP_THRESH(tnapi
)))
4467 netif_tx_wake_queue(txq
);
4468 __netif_tx_unlock(txq
);
4472 static void tg3_rx_skb_free(struct tg3
*tp
, struct ring_info
*ri
, u32 map_sz
)
4477 pci_unmap_single(tp
->pdev
, dma_unmap_addr(ri
, mapping
),
4478 map_sz
, PCI_DMA_FROMDEVICE
);
4479 dev_kfree_skb_any(ri
->skb
);
4483 /* Returns size of skb allocated or < 0 on error.
4485 * We only need to fill in the address because the other members
4486 * of the RX descriptor are invariant, see tg3_init_rings.
4488 * Note the purposeful assymetry of cpu vs. chip accesses. For
4489 * posting buffers we only dirty the first cache line of the RX
4490 * descriptor (containing the address). Whereas for the RX status
4491 * buffers the cpu only reads the last cacheline of the RX descriptor
4492 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4494 static int tg3_alloc_rx_skb(struct tg3
*tp
, struct tg3_rx_prodring_set
*tpr
,
4495 u32 opaque_key
, u32 dest_idx_unmasked
)
4497 struct tg3_rx_buffer_desc
*desc
;
4498 struct ring_info
*map
, *src_map
;
4499 struct sk_buff
*skb
;
4501 int skb_size
, dest_idx
;
4504 switch (opaque_key
) {
4505 case RXD_OPAQUE_RING_STD
:
4506 dest_idx
= dest_idx_unmasked
% TG3_RX_RING_SIZE
;
4507 desc
= &tpr
->rx_std
[dest_idx
];
4508 map
= &tpr
->rx_std_buffers
[dest_idx
];
4509 skb_size
= tp
->rx_pkt_map_sz
;
4512 case RXD_OPAQUE_RING_JUMBO
:
4513 dest_idx
= dest_idx_unmasked
% TG3_RX_JUMBO_RING_SIZE
;
4514 desc
= &tpr
->rx_jmb
[dest_idx
].std
;
4515 map
= &tpr
->rx_jmb_buffers
[dest_idx
];
4516 skb_size
= TG3_RX_JMB_MAP_SZ
;
4523 /* Do not overwrite any of the map or rp information
4524 * until we are sure we can commit to a new buffer.
4526 * Callers depend upon this behavior and assume that
4527 * we leave everything unchanged if we fail.
4529 skb
= netdev_alloc_skb(tp
->dev
, skb_size
+ tp
->rx_offset
);
4533 skb_reserve(skb
, tp
->rx_offset
);
4535 mapping
= pci_map_single(tp
->pdev
, skb
->data
, skb_size
,
4536 PCI_DMA_FROMDEVICE
);
4537 if (pci_dma_mapping_error(tp
->pdev
, mapping
)) {
4543 dma_unmap_addr_set(map
, mapping
, mapping
);
4545 desc
->addr_hi
= ((u64
)mapping
>> 32);
4546 desc
->addr_lo
= ((u64
)mapping
& 0xffffffff);
4551 /* We only need to move over in the address because the other
4552 * members of the RX descriptor are invariant. See notes above
4553 * tg3_alloc_rx_skb for full details.
4555 static void tg3_recycle_rx(struct tg3_napi
*tnapi
,
4556 struct tg3_rx_prodring_set
*dpr
,
4557 u32 opaque_key
, int src_idx
,
4558 u32 dest_idx_unmasked
)
4560 struct tg3
*tp
= tnapi
->tp
;
4561 struct tg3_rx_buffer_desc
*src_desc
, *dest_desc
;
4562 struct ring_info
*src_map
, *dest_map
;
4563 struct tg3_rx_prodring_set
*spr
= &tp
->prodring
[0];
4566 switch (opaque_key
) {
4567 case RXD_OPAQUE_RING_STD
:
4568 dest_idx
= dest_idx_unmasked
% TG3_RX_RING_SIZE
;
4569 dest_desc
= &dpr
->rx_std
[dest_idx
];
4570 dest_map
= &dpr
->rx_std_buffers
[dest_idx
];
4571 src_desc
= &spr
->rx_std
[src_idx
];
4572 src_map
= &spr
->rx_std_buffers
[src_idx
];
4575 case RXD_OPAQUE_RING_JUMBO
:
4576 dest_idx
= dest_idx_unmasked
% TG3_RX_JUMBO_RING_SIZE
;
4577 dest_desc
= &dpr
->rx_jmb
[dest_idx
].std
;
4578 dest_map
= &dpr
->rx_jmb_buffers
[dest_idx
];
4579 src_desc
= &spr
->rx_jmb
[src_idx
].std
;
4580 src_map
= &spr
->rx_jmb_buffers
[src_idx
];
4587 dest_map
->skb
= src_map
->skb
;
4588 dma_unmap_addr_set(dest_map
, mapping
,
4589 dma_unmap_addr(src_map
, mapping
));
4590 dest_desc
->addr_hi
= src_desc
->addr_hi
;
4591 dest_desc
->addr_lo
= src_desc
->addr_lo
;
4593 /* Ensure that the update to the skb happens after the physical
4594 * addresses have been transferred to the new BD location.
4598 src_map
->skb
= NULL
;
4601 /* The RX ring scheme is composed of multiple rings which post fresh
4602 * buffers to the chip, and one special ring the chip uses to report
4603 * status back to the host.
4605 * The special ring reports the status of received packets to the
4606 * host. The chip does not write into the original descriptor the
4607 * RX buffer was obtained from. The chip simply takes the original
4608 * descriptor as provided by the host, updates the status and length
4609 * field, then writes this into the next status ring entry.
4611 * Each ring the host uses to post buffers to the chip is described
4612 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4613 * it is first placed into the on-chip ram. When the packet's length
4614 * is known, it walks down the TG3_BDINFO entries to select the ring.
4615 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4616 * which is within the range of the new packet's length is chosen.
4618 * The "separate ring for rx status" scheme may sound queer, but it makes
4619 * sense from a cache coherency perspective. If only the host writes
4620 * to the buffer post rings, and only the chip writes to the rx status
4621 * rings, then cache lines never move beyond shared-modified state.
4622 * If both the host and chip were to write into the same ring, cache line
4623 * eviction could occur since both entities want it in an exclusive state.
4625 static int tg3_rx(struct tg3_napi
*tnapi
, int budget
)
4627 struct tg3
*tp
= tnapi
->tp
;
4628 u32 work_mask
, rx_std_posted
= 0;
4629 u32 std_prod_idx
, jmb_prod_idx
;
4630 u32 sw_idx
= tnapi
->rx_rcb_ptr
;
4633 struct tg3_rx_prodring_set
*tpr
= tnapi
->prodring
;
4635 hw_idx
= *(tnapi
->rx_rcb_prod_idx
);
4637 * We need to order the read of hw_idx and the read of
4638 * the opaque cookie.
4643 std_prod_idx
= tpr
->rx_std_prod_idx
;
4644 jmb_prod_idx
= tpr
->rx_jmb_prod_idx
;
4645 while (sw_idx
!= hw_idx
&& budget
> 0) {
4646 struct ring_info
*ri
;
4647 struct tg3_rx_buffer_desc
*desc
= &tnapi
->rx_rcb
[sw_idx
];
4649 struct sk_buff
*skb
;
4650 dma_addr_t dma_addr
;
4651 u32 opaque_key
, desc_idx
, *post_ptr
;
4652 bool hw_vlan __maybe_unused
= false;
4653 u16 vtag __maybe_unused
= 0;
4655 desc_idx
= desc
->opaque
& RXD_OPAQUE_INDEX_MASK
;
4656 opaque_key
= desc
->opaque
& RXD_OPAQUE_RING_MASK
;
4657 if (opaque_key
== RXD_OPAQUE_RING_STD
) {
4658 ri
= &tp
->prodring
[0].rx_std_buffers
[desc_idx
];
4659 dma_addr
= dma_unmap_addr(ri
, mapping
);
4661 post_ptr
= &std_prod_idx
;
4663 } else if (opaque_key
== RXD_OPAQUE_RING_JUMBO
) {
4664 ri
= &tp
->prodring
[0].rx_jmb_buffers
[desc_idx
];
4665 dma_addr
= dma_unmap_addr(ri
, mapping
);
4667 post_ptr
= &jmb_prod_idx
;
4669 goto next_pkt_nopost
;
4671 work_mask
|= opaque_key
;
4673 if ((desc
->err_vlan
& RXD_ERR_MASK
) != 0 &&
4674 (desc
->err_vlan
!= RXD_ERR_ODD_NIBBLE_RCVD_MII
)) {
4676 tg3_recycle_rx(tnapi
, tpr
, opaque_key
,
4677 desc_idx
, *post_ptr
);
4679 /* Other statistics kept track of by card. */
4680 tp
->net_stats
.rx_dropped
++;
4684 len
= ((desc
->idx_len
& RXD_LEN_MASK
) >> RXD_LEN_SHIFT
) -
4687 if (len
> TG3_RX_COPY_THRESH(tp
)) {
4690 skb_size
= tg3_alloc_rx_skb(tp
, tpr
, opaque_key
,
4695 pci_unmap_single(tp
->pdev
, dma_addr
, skb_size
,
4696 PCI_DMA_FROMDEVICE
);
4698 /* Ensure that the update to the skb happens
4699 * after the usage of the old DMA mapping.
4707 struct sk_buff
*copy_skb
;
4709 tg3_recycle_rx(tnapi
, tpr
, opaque_key
,
4710 desc_idx
, *post_ptr
);
4712 copy_skb
= netdev_alloc_skb(tp
->dev
, len
+ VLAN_HLEN
+
4714 if (copy_skb
== NULL
)
4715 goto drop_it_no_recycle
;
4717 skb_reserve(copy_skb
, TG3_RAW_IP_ALIGN
+ VLAN_HLEN
);
4718 skb_put(copy_skb
, len
);
4719 pci_dma_sync_single_for_cpu(tp
->pdev
, dma_addr
, len
, PCI_DMA_FROMDEVICE
);
4720 skb_copy_from_linear_data(skb
, copy_skb
->data
, len
);
4721 pci_dma_sync_single_for_device(tp
->pdev
, dma_addr
, len
, PCI_DMA_FROMDEVICE
);
4723 /* We'll reuse the original ring buffer. */
4727 if ((tp
->tg3_flags
& TG3_FLAG_RX_CHECKSUMS
) &&
4728 (desc
->type_flags
& RXD_FLAG_TCPUDP_CSUM
) &&
4729 (((desc
->ip_tcp_csum
& RXD_TCPCSUM_MASK
)
4730 >> RXD_TCPCSUM_SHIFT
) == 0xffff))
4731 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
4733 skb
->ip_summed
= CHECKSUM_NONE
;
4735 skb
->protocol
= eth_type_trans(skb
, tp
->dev
);
4737 if (len
> (tp
->dev
->mtu
+ ETH_HLEN
) &&
4738 skb
->protocol
!= htons(ETH_P_8021Q
)) {
4743 if (desc
->type_flags
& RXD_FLAG_VLAN
&&
4744 !(tp
->rx_mode
& RX_MODE_KEEP_VLAN_TAG
)) {
4745 vtag
= desc
->err_vlan
& RXD_VLAN_MASK
;
4746 #if TG3_VLAN_TAG_USED
4752 struct vlan_ethhdr
*ve
= (struct vlan_ethhdr
*)
4753 __skb_push(skb
, VLAN_HLEN
);
4755 memmove(ve
, skb
->data
+ VLAN_HLEN
,
4757 ve
->h_vlan_proto
= htons(ETH_P_8021Q
);
4758 ve
->h_vlan_TCI
= htons(vtag
);
4762 #if TG3_VLAN_TAG_USED
4764 vlan_gro_receive(&tnapi
->napi
, tp
->vlgrp
, vtag
, skb
);
4767 napi_gro_receive(&tnapi
->napi
, skb
);
4775 if (unlikely(rx_std_posted
>= tp
->rx_std_max_post
)) {
4776 tpr
->rx_std_prod_idx
= std_prod_idx
% TG3_RX_RING_SIZE
;
4777 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG
,
4778 tpr
->rx_std_prod_idx
);
4779 work_mask
&= ~RXD_OPAQUE_RING_STD
;
4784 sw_idx
&= (TG3_RX_RCB_RING_SIZE(tp
) - 1);
4786 /* Refresh hw_idx to see if there is new work */
4787 if (sw_idx
== hw_idx
) {
4788 hw_idx
= *(tnapi
->rx_rcb_prod_idx
);
4793 /* ACK the status ring. */
4794 tnapi
->rx_rcb_ptr
= sw_idx
;
4795 tw32_rx_mbox(tnapi
->consmbox
, sw_idx
);
4797 /* Refill RX ring(s). */
4798 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_RSS
)) {
4799 if (work_mask
& RXD_OPAQUE_RING_STD
) {
4800 tpr
->rx_std_prod_idx
= std_prod_idx
% TG3_RX_RING_SIZE
;
4801 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG
,
4802 tpr
->rx_std_prod_idx
);
4804 if (work_mask
& RXD_OPAQUE_RING_JUMBO
) {
4805 tpr
->rx_jmb_prod_idx
= jmb_prod_idx
%
4806 TG3_RX_JUMBO_RING_SIZE
;
4807 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG
,
4808 tpr
->rx_jmb_prod_idx
);
4811 } else if (work_mask
) {
4812 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4813 * updated before the producer indices can be updated.
4817 tpr
->rx_std_prod_idx
= std_prod_idx
% TG3_RX_RING_SIZE
;
4818 tpr
->rx_jmb_prod_idx
= jmb_prod_idx
% TG3_RX_JUMBO_RING_SIZE
;
4820 if (tnapi
!= &tp
->napi
[1])
4821 napi_schedule(&tp
->napi
[1].napi
);
4827 static void tg3_poll_link(struct tg3
*tp
)
4829 /* handle link change and other phy events */
4830 if (!(tp
->tg3_flags
&
4831 (TG3_FLAG_USE_LINKCHG_REG
|
4832 TG3_FLAG_POLL_SERDES
))) {
4833 struct tg3_hw_status
*sblk
= tp
->napi
[0].hw_status
;
4835 if (sblk
->status
& SD_STATUS_LINK_CHG
) {
4836 sblk
->status
= SD_STATUS_UPDATED
|
4837 (sblk
->status
& ~SD_STATUS_LINK_CHG
);
4838 spin_lock(&tp
->lock
);
4839 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
4841 (MAC_STATUS_SYNC_CHANGED
|
4842 MAC_STATUS_CFG_CHANGED
|
4843 MAC_STATUS_MI_COMPLETION
|
4844 MAC_STATUS_LNKSTATE_CHANGED
));
4847 tg3_setup_phy(tp
, 0);
4848 spin_unlock(&tp
->lock
);
4853 static int tg3_rx_prodring_xfer(struct tg3
*tp
,
4854 struct tg3_rx_prodring_set
*dpr
,
4855 struct tg3_rx_prodring_set
*spr
)
4857 u32 si
, di
, cpycnt
, src_prod_idx
;
4861 src_prod_idx
= spr
->rx_std_prod_idx
;
4863 /* Make sure updates to the rx_std_buffers[] entries and the
4864 * standard producer index are seen in the correct order.
4868 if (spr
->rx_std_cons_idx
== src_prod_idx
)
4871 if (spr
->rx_std_cons_idx
< src_prod_idx
)
4872 cpycnt
= src_prod_idx
- spr
->rx_std_cons_idx
;
4874 cpycnt
= TG3_RX_RING_SIZE
- spr
->rx_std_cons_idx
;
4876 cpycnt
= min(cpycnt
, TG3_RX_RING_SIZE
- dpr
->rx_std_prod_idx
);
4878 si
= spr
->rx_std_cons_idx
;
4879 di
= dpr
->rx_std_prod_idx
;
4881 for (i
= di
; i
< di
+ cpycnt
; i
++) {
4882 if (dpr
->rx_std_buffers
[i
].skb
) {
4892 /* Ensure that updates to the rx_std_buffers ring and the
4893 * shadowed hardware producer ring from tg3_recycle_skb() are
4894 * ordered correctly WRT the skb check above.
4898 memcpy(&dpr
->rx_std_buffers
[di
],
4899 &spr
->rx_std_buffers
[si
],
4900 cpycnt
* sizeof(struct ring_info
));
4902 for (i
= 0; i
< cpycnt
; i
++, di
++, si
++) {
4903 struct tg3_rx_buffer_desc
*sbd
, *dbd
;
4904 sbd
= &spr
->rx_std
[si
];
4905 dbd
= &dpr
->rx_std
[di
];
4906 dbd
->addr_hi
= sbd
->addr_hi
;
4907 dbd
->addr_lo
= sbd
->addr_lo
;
4910 spr
->rx_std_cons_idx
= (spr
->rx_std_cons_idx
+ cpycnt
) %
4912 dpr
->rx_std_prod_idx
= (dpr
->rx_std_prod_idx
+ cpycnt
) %
4917 src_prod_idx
= spr
->rx_jmb_prod_idx
;
4919 /* Make sure updates to the rx_jmb_buffers[] entries and
4920 * the jumbo producer index are seen in the correct order.
4924 if (spr
->rx_jmb_cons_idx
== src_prod_idx
)
4927 if (spr
->rx_jmb_cons_idx
< src_prod_idx
)
4928 cpycnt
= src_prod_idx
- spr
->rx_jmb_cons_idx
;
4930 cpycnt
= TG3_RX_JUMBO_RING_SIZE
- spr
->rx_jmb_cons_idx
;
4932 cpycnt
= min(cpycnt
,
4933 TG3_RX_JUMBO_RING_SIZE
- dpr
->rx_jmb_prod_idx
);
4935 si
= spr
->rx_jmb_cons_idx
;
4936 di
= dpr
->rx_jmb_prod_idx
;
4938 for (i
= di
; i
< di
+ cpycnt
; i
++) {
4939 if (dpr
->rx_jmb_buffers
[i
].skb
) {
4949 /* Ensure that updates to the rx_jmb_buffers ring and the
4950 * shadowed hardware producer ring from tg3_recycle_skb() are
4951 * ordered correctly WRT the skb check above.
4955 memcpy(&dpr
->rx_jmb_buffers
[di
],
4956 &spr
->rx_jmb_buffers
[si
],
4957 cpycnt
* sizeof(struct ring_info
));
4959 for (i
= 0; i
< cpycnt
; i
++, di
++, si
++) {
4960 struct tg3_rx_buffer_desc
*sbd
, *dbd
;
4961 sbd
= &spr
->rx_jmb
[si
].std
;
4962 dbd
= &dpr
->rx_jmb
[di
].std
;
4963 dbd
->addr_hi
= sbd
->addr_hi
;
4964 dbd
->addr_lo
= sbd
->addr_lo
;
4967 spr
->rx_jmb_cons_idx
= (spr
->rx_jmb_cons_idx
+ cpycnt
) %
4968 TG3_RX_JUMBO_RING_SIZE
;
4969 dpr
->rx_jmb_prod_idx
= (dpr
->rx_jmb_prod_idx
+ cpycnt
) %
4970 TG3_RX_JUMBO_RING_SIZE
;
4976 static int tg3_poll_work(struct tg3_napi
*tnapi
, int work_done
, int budget
)
4978 struct tg3
*tp
= tnapi
->tp
;
4980 /* run TX completion thread */
4981 if (tnapi
->hw_status
->idx
[0].tx_consumer
!= tnapi
->tx_cons
) {
4983 if (unlikely(tp
->tg3_flags
& TG3_FLAG_TX_RECOVERY_PENDING
))
4987 /* run RX thread, within the bounds set by NAPI.
4988 * All RX "locking" is done by ensuring outside
4989 * code synchronizes with tg3->napi.poll()
4991 if (*(tnapi
->rx_rcb_prod_idx
) != tnapi
->rx_rcb_ptr
)
4992 work_done
+= tg3_rx(tnapi
, budget
- work_done
);
4994 if ((tp
->tg3_flags3
& TG3_FLG3_ENABLE_RSS
) && tnapi
== &tp
->napi
[1]) {
4995 struct tg3_rx_prodring_set
*dpr
= &tp
->prodring
[0];
4997 u32 std_prod_idx
= dpr
->rx_std_prod_idx
;
4998 u32 jmb_prod_idx
= dpr
->rx_jmb_prod_idx
;
5000 for (i
= 1; i
< tp
->irq_cnt
; i
++)
5001 err
|= tg3_rx_prodring_xfer(tp
, dpr
,
5002 tp
->napi
[i
].prodring
);
5006 if (std_prod_idx
!= dpr
->rx_std_prod_idx
)
5007 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG
,
5008 dpr
->rx_std_prod_idx
);
5010 if (jmb_prod_idx
!= dpr
->rx_jmb_prod_idx
)
5011 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG
,
5012 dpr
->rx_jmb_prod_idx
);
5017 tw32_f(HOSTCC_MODE
, tp
->coal_now
);
5023 static int tg3_poll_msix(struct napi_struct
*napi
, int budget
)
5025 struct tg3_napi
*tnapi
= container_of(napi
, struct tg3_napi
, napi
);
5026 struct tg3
*tp
= tnapi
->tp
;
5028 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
5031 work_done
= tg3_poll_work(tnapi
, work_done
, budget
);
5033 if (unlikely(tp
->tg3_flags
& TG3_FLAG_TX_RECOVERY_PENDING
))
5036 if (unlikely(work_done
>= budget
))
5039 /* tp->last_tag is used in tg3_int_reenable() below
5040 * to tell the hw how much work has been processed,
5041 * so we must read it before checking for more work.
5043 tnapi
->last_tag
= sblk
->status_tag
;
5044 tnapi
->last_irq_tag
= tnapi
->last_tag
;
5047 /* check for RX/TX work to do */
5048 if (likely(sblk
->idx
[0].tx_consumer
== tnapi
->tx_cons
&&
5049 *(tnapi
->rx_rcb_prod_idx
) == tnapi
->rx_rcb_ptr
)) {
5050 napi_complete(napi
);
5051 /* Reenable interrupts. */
5052 tw32_mailbox(tnapi
->int_mbox
, tnapi
->last_tag
<< 24);
5061 /* work_done is guaranteed to be less than budget. */
5062 napi_complete(napi
);
5063 schedule_work(&tp
->reset_task
);
5067 static int tg3_poll(struct napi_struct
*napi
, int budget
)
5069 struct tg3_napi
*tnapi
= container_of(napi
, struct tg3_napi
, napi
);
5070 struct tg3
*tp
= tnapi
->tp
;
5072 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
5077 work_done
= tg3_poll_work(tnapi
, work_done
, budget
);
5079 if (unlikely(tp
->tg3_flags
& TG3_FLAG_TX_RECOVERY_PENDING
))
5082 if (unlikely(work_done
>= budget
))
5085 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) {
5086 /* tp->last_tag is used in tg3_int_reenable() below
5087 * to tell the hw how much work has been processed,
5088 * so we must read it before checking for more work.
5090 tnapi
->last_tag
= sblk
->status_tag
;
5091 tnapi
->last_irq_tag
= tnapi
->last_tag
;
5094 sblk
->status
&= ~SD_STATUS_UPDATED
;
5096 if (likely(!tg3_has_work(tnapi
))) {
5097 napi_complete(napi
);
5098 tg3_int_reenable(tnapi
);
5106 /* work_done is guaranteed to be less than budget. */
5107 napi_complete(napi
);
5108 schedule_work(&tp
->reset_task
);
5112 static void tg3_irq_quiesce(struct tg3
*tp
)
5116 BUG_ON(tp
->irq_sync
);
5121 for (i
= 0; i
< tp
->irq_cnt
; i
++)
5122 synchronize_irq(tp
->napi
[i
].irq_vec
);
5125 static inline int tg3_irq_sync(struct tg3
*tp
)
5127 return tp
->irq_sync
;
5130 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5131 * If irq_sync is non-zero, then the IRQ handler must be synchronized
5132 * with as well. Most of the time, this is not necessary except when
5133 * shutting down the device.
5135 static inline void tg3_full_lock(struct tg3
*tp
, int irq_sync
)
5137 spin_lock_bh(&tp
->lock
);
5139 tg3_irq_quiesce(tp
);
5142 static inline void tg3_full_unlock(struct tg3
*tp
)
5144 spin_unlock_bh(&tp
->lock
);
5147 /* One-shot MSI handler - Chip automatically disables interrupt
5148 * after sending MSI so driver doesn't have to do it.
5150 static irqreturn_t
tg3_msi_1shot(int irq
, void *dev_id
)
5152 struct tg3_napi
*tnapi
= dev_id
;
5153 struct tg3
*tp
= tnapi
->tp
;
5155 prefetch(tnapi
->hw_status
);
5157 prefetch(&tnapi
->rx_rcb
[tnapi
->rx_rcb_ptr
]);
5159 if (likely(!tg3_irq_sync(tp
)))
5160 napi_schedule(&tnapi
->napi
);
5165 /* MSI ISR - No need to check for interrupt sharing and no need to
5166 * flush status block and interrupt mailbox. PCI ordering rules
5167 * guarantee that MSI will arrive after the status block.
5169 static irqreturn_t
tg3_msi(int irq
, void *dev_id
)
5171 struct tg3_napi
*tnapi
= dev_id
;
5172 struct tg3
*tp
= tnapi
->tp
;
5174 prefetch(tnapi
->hw_status
);
5176 prefetch(&tnapi
->rx_rcb
[tnapi
->rx_rcb_ptr
]);
5178 * Writing any value to intr-mbox-0 clears PCI INTA# and
5179 * chip-internal interrupt pending events.
5180 * Writing non-zero to intr-mbox-0 additional tells the
5181 * NIC to stop sending us irqs, engaging "in-intr-handler"
5184 tw32_mailbox(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0x00000001);
5185 if (likely(!tg3_irq_sync(tp
)))
5186 napi_schedule(&tnapi
->napi
);
5188 return IRQ_RETVAL(1);
5191 static irqreturn_t
tg3_interrupt(int irq
, void *dev_id
)
5193 struct tg3_napi
*tnapi
= dev_id
;
5194 struct tg3
*tp
= tnapi
->tp
;
5195 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
5196 unsigned int handled
= 1;
5198 /* In INTx mode, it is possible for the interrupt to arrive at
5199 * the CPU before the status block posted prior to the interrupt.
5200 * Reading the PCI State register will confirm whether the
5201 * interrupt is ours and will flush the status block.
5203 if (unlikely(!(sblk
->status
& SD_STATUS_UPDATED
))) {
5204 if ((tp
->tg3_flags
& TG3_FLAG_CHIP_RESETTING
) ||
5205 (tr32(TG3PCI_PCISTATE
) & PCISTATE_INT_NOT_ACTIVE
)) {
5212 * Writing any value to intr-mbox-0 clears PCI INTA# and
5213 * chip-internal interrupt pending events.
5214 * Writing non-zero to intr-mbox-0 additional tells the
5215 * NIC to stop sending us irqs, engaging "in-intr-handler"
5218 * Flush the mailbox to de-assert the IRQ immediately to prevent
5219 * spurious interrupts. The flush impacts performance but
5220 * excessive spurious interrupts can be worse in some cases.
5222 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0x00000001);
5223 if (tg3_irq_sync(tp
))
5225 sblk
->status
&= ~SD_STATUS_UPDATED
;
5226 if (likely(tg3_has_work(tnapi
))) {
5227 prefetch(&tnapi
->rx_rcb
[tnapi
->rx_rcb_ptr
]);
5228 napi_schedule(&tnapi
->napi
);
5230 /* No work, shared interrupt perhaps? re-enable
5231 * interrupts, and flush that PCI write
5233 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
,
5237 return IRQ_RETVAL(handled
);
5240 static irqreturn_t
tg3_interrupt_tagged(int irq
, void *dev_id
)
5242 struct tg3_napi
*tnapi
= dev_id
;
5243 struct tg3
*tp
= tnapi
->tp
;
5244 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
5245 unsigned int handled
= 1;
5247 /* In INTx mode, it is possible for the interrupt to arrive at
5248 * the CPU before the status block posted prior to the interrupt.
5249 * Reading the PCI State register will confirm whether the
5250 * interrupt is ours and will flush the status block.
5252 if (unlikely(sblk
->status_tag
== tnapi
->last_irq_tag
)) {
5253 if ((tp
->tg3_flags
& TG3_FLAG_CHIP_RESETTING
) ||
5254 (tr32(TG3PCI_PCISTATE
) & PCISTATE_INT_NOT_ACTIVE
)) {
5261 * writing any value to intr-mbox-0 clears PCI INTA# and
5262 * chip-internal interrupt pending events.
5263 * writing non-zero to intr-mbox-0 additional tells the
5264 * NIC to stop sending us irqs, engaging "in-intr-handler"
5267 * Flush the mailbox to de-assert the IRQ immediately to prevent
5268 * spurious interrupts. The flush impacts performance but
5269 * excessive spurious interrupts can be worse in some cases.
5271 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0x00000001);
5274 * In a shared interrupt configuration, sometimes other devices'
5275 * interrupts will scream. We record the current status tag here
5276 * so that the above check can report that the screaming interrupts
5277 * are unhandled. Eventually they will be silenced.
5279 tnapi
->last_irq_tag
= sblk
->status_tag
;
5281 if (tg3_irq_sync(tp
))
5284 prefetch(&tnapi
->rx_rcb
[tnapi
->rx_rcb_ptr
]);
5286 napi_schedule(&tnapi
->napi
);
5289 return IRQ_RETVAL(handled
);
5292 /* ISR for interrupt test */
5293 static irqreturn_t
tg3_test_isr(int irq
, void *dev_id
)
5295 struct tg3_napi
*tnapi
= dev_id
;
5296 struct tg3
*tp
= tnapi
->tp
;
5297 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
5299 if ((sblk
->status
& SD_STATUS_UPDATED
) ||
5300 !(tr32(TG3PCI_PCISTATE
) & PCISTATE_INT_NOT_ACTIVE
)) {
5301 tg3_disable_ints(tp
);
5302 return IRQ_RETVAL(1);
5304 return IRQ_RETVAL(0);
5307 static int tg3_init_hw(struct tg3
*, int);
5308 static int tg3_halt(struct tg3
*, int, int);
5310 /* Restart hardware after configuration changes, self-test, etc.
5311 * Invoked with tp->lock held.
5313 static int tg3_restart_hw(struct tg3
*tp
, int reset_phy
)
5314 __releases(tp
->lock
)
5315 __acquires(tp
->lock
)
5319 err
= tg3_init_hw(tp
, reset_phy
);
5322 "Failed to re-initialize device, aborting\n");
5323 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
5324 tg3_full_unlock(tp
);
5325 del_timer_sync(&tp
->timer
);
5327 tg3_napi_enable(tp
);
5329 tg3_full_lock(tp
, 0);
5334 #ifdef CONFIG_NET_POLL_CONTROLLER
5335 static void tg3_poll_controller(struct net_device
*dev
)
5338 struct tg3
*tp
= netdev_priv(dev
);
5340 for (i
= 0; i
< tp
->irq_cnt
; i
++)
5341 tg3_interrupt(tp
->napi
[i
].irq_vec
, &tp
->napi
[i
]);
5345 static void tg3_reset_task(struct work_struct
*work
)
5347 struct tg3
*tp
= container_of(work
, struct tg3
, reset_task
);
5349 unsigned int restart_timer
;
5351 tg3_full_lock(tp
, 0);
5353 if (!netif_running(tp
->dev
)) {
5354 tg3_full_unlock(tp
);
5358 tg3_full_unlock(tp
);
5364 tg3_full_lock(tp
, 1);
5366 restart_timer
= tp
->tg3_flags2
& TG3_FLG2_RESTART_TIMER
;
5367 tp
->tg3_flags2
&= ~TG3_FLG2_RESTART_TIMER
;
5369 if (tp
->tg3_flags
& TG3_FLAG_TX_RECOVERY_PENDING
) {
5370 tp
->write32_tx_mbox
= tg3_write32_tx_mbox
;
5371 tp
->write32_rx_mbox
= tg3_write_flush_reg32
;
5372 tp
->tg3_flags
|= TG3_FLAG_MBOX_WRITE_REORDER
;
5373 tp
->tg3_flags
&= ~TG3_FLAG_TX_RECOVERY_PENDING
;
5376 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 0);
5377 err
= tg3_init_hw(tp
, 1);
5381 tg3_netif_start(tp
);
5384 mod_timer(&tp
->timer
, jiffies
+ 1);
5387 tg3_full_unlock(tp
);
5393 static void tg3_dump_short_state(struct tg3
*tp
)
5395 netdev_err(tp
->dev
, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5396 tr32(MAC_TX_STATUS
), tr32(MAC_RX_STATUS
));
5397 netdev_err(tp
->dev
, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5398 tr32(RDMAC_STATUS
), tr32(WDMAC_STATUS
));
5401 static void tg3_tx_timeout(struct net_device
*dev
)
5403 struct tg3
*tp
= netdev_priv(dev
);
5405 if (netif_msg_tx_err(tp
)) {
5406 netdev_err(dev
, "transmit timed out, resetting\n");
5407 tg3_dump_short_state(tp
);
5410 schedule_work(&tp
->reset_task
);
5413 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5414 static inline int tg3_4g_overflow_test(dma_addr_t mapping
, int len
)
5416 u32 base
= (u32
) mapping
& 0xffffffff;
5418 return ((base
> 0xffffdcc0) &&
5419 (base
+ len
+ 8 < base
));
5422 /* Test for DMA addresses > 40-bit */
5423 static inline int tg3_40bit_overflow_test(struct tg3
*tp
, dma_addr_t mapping
,
5426 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5427 if (tp
->tg3_flags
& TG3_FLAG_40BIT_DMA_BUG
)
5428 return (((u64
) mapping
+ len
) > DMA_BIT_MASK(40));
5435 static void tg3_set_txd(struct tg3_napi
*, int, dma_addr_t
, int, u32
, u32
);
5437 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5438 static int tigon3_dma_hwbug_workaround(struct tg3_napi
*tnapi
,
5439 struct sk_buff
*skb
, u32 last_plus_one
,
5440 u32
*start
, u32 base_flags
, u32 mss
)
5442 struct tg3
*tp
= tnapi
->tp
;
5443 struct sk_buff
*new_skb
;
5444 dma_addr_t new_addr
= 0;
5448 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
)
5449 new_skb
= skb_copy(skb
, GFP_ATOMIC
);
5451 int more_headroom
= 4 - ((unsigned long)skb
->data
& 3);
5453 new_skb
= skb_copy_expand(skb
,
5454 skb_headroom(skb
) + more_headroom
,
5455 skb_tailroom(skb
), GFP_ATOMIC
);
5461 /* New SKB is guaranteed to be linear. */
5463 new_addr
= pci_map_single(tp
->pdev
, new_skb
->data
, new_skb
->len
,
5465 /* Make sure the mapping succeeded */
5466 if (pci_dma_mapping_error(tp
->pdev
, new_addr
)) {
5468 dev_kfree_skb(new_skb
);
5471 /* Make sure new skb does not cross any 4G boundaries.
5472 * Drop the packet if it does.
5474 } else if ((tp
->tg3_flags3
& TG3_FLG3_4G_DMA_BNDRY_BUG
) &&
5475 tg3_4g_overflow_test(new_addr
, new_skb
->len
)) {
5476 pci_unmap_single(tp
->pdev
, new_addr
, new_skb
->len
,
5479 dev_kfree_skb(new_skb
);
5482 tg3_set_txd(tnapi
, entry
, new_addr
, new_skb
->len
,
5483 base_flags
, 1 | (mss
<< 1));
5484 *start
= NEXT_TX(entry
);
5488 /* Now clean up the sw ring entries. */
5490 while (entry
!= last_plus_one
) {
5494 len
= skb_headlen(skb
);
5496 len
= skb_shinfo(skb
)->frags
[i
-1].size
;
5498 pci_unmap_single(tp
->pdev
,
5499 dma_unmap_addr(&tnapi
->tx_buffers
[entry
],
5501 len
, PCI_DMA_TODEVICE
);
5503 tnapi
->tx_buffers
[entry
].skb
= new_skb
;
5504 dma_unmap_addr_set(&tnapi
->tx_buffers
[entry
], mapping
,
5507 tnapi
->tx_buffers
[entry
].skb
= NULL
;
5509 entry
= NEXT_TX(entry
);
5518 static void tg3_set_txd(struct tg3_napi
*tnapi
, int entry
,
5519 dma_addr_t mapping
, int len
, u32 flags
,
5522 struct tg3_tx_buffer_desc
*txd
= &tnapi
->tx_ring
[entry
];
5523 int is_end
= (mss_and_is_end
& 0x1);
5524 u32 mss
= (mss_and_is_end
>> 1);
5528 flags
|= TXD_FLAG_END
;
5529 if (flags
& TXD_FLAG_VLAN
) {
5530 vlan_tag
= flags
>> 16;
5533 vlan_tag
|= (mss
<< TXD_MSS_SHIFT
);
5535 txd
->addr_hi
= ((u64
) mapping
>> 32);
5536 txd
->addr_lo
= ((u64
) mapping
& 0xffffffff);
5537 txd
->len_flags
= (len
<< TXD_LEN_SHIFT
) | flags
;
5538 txd
->vlan_tag
= vlan_tag
<< TXD_VLAN_TAG_SHIFT
;
5541 /* hard_start_xmit for devices that don't have any bugs and
5542 * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5544 static netdev_tx_t
tg3_start_xmit(struct sk_buff
*skb
,
5545 struct net_device
*dev
)
5547 struct tg3
*tp
= netdev_priv(dev
);
5548 u32 len
, entry
, base_flags
, mss
;
5550 struct tg3_napi
*tnapi
;
5551 struct netdev_queue
*txq
;
5552 unsigned int i
, last
;
5554 txq
= netdev_get_tx_queue(dev
, skb_get_queue_mapping(skb
));
5555 tnapi
= &tp
->napi
[skb_get_queue_mapping(skb
)];
5556 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)
5559 /* We are running in BH disabled context with netif_tx_lock
5560 * and TX reclaim runs via tp->napi.poll inside of a software
5561 * interrupt. Furthermore, IRQ processing runs lockless so we have
5562 * no IRQ context deadlocks to worry about either. Rejoice!
5564 if (unlikely(tg3_tx_avail(tnapi
) <= (skb_shinfo(skb
)->nr_frags
+ 1))) {
5565 if (!netif_tx_queue_stopped(txq
)) {
5566 netif_tx_stop_queue(txq
);
5568 /* This is a hard error, log it. */
5570 "BUG! Tx Ring full when queue awake!\n");
5572 return NETDEV_TX_BUSY
;
5575 entry
= tnapi
->tx_prod
;
5577 mss
= skb_shinfo(skb
)->gso_size
;
5579 int tcp_opt_len
, ip_tcp_len
;
5582 if (skb_header_cloned(skb
) &&
5583 pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
)) {
5588 if (skb_shinfo(skb
)->gso_type
& SKB_GSO_TCPV6
)
5589 hdrlen
= skb_headlen(skb
) - ETH_HLEN
;
5591 struct iphdr
*iph
= ip_hdr(skb
);
5593 tcp_opt_len
= tcp_optlen(skb
);
5594 ip_tcp_len
= ip_hdrlen(skb
) + sizeof(struct tcphdr
);
5597 iph
->tot_len
= htons(mss
+ ip_tcp_len
+ tcp_opt_len
);
5598 hdrlen
= ip_tcp_len
+ tcp_opt_len
;
5601 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO_3
) {
5602 mss
|= (hdrlen
& 0xc) << 12;
5604 base_flags
|= 0x00000010;
5605 base_flags
|= (hdrlen
& 0x3e0) << 5;
5609 base_flags
|= (TXD_FLAG_CPU_PRE_DMA
|
5610 TXD_FLAG_CPU_POST_DMA
);
5612 tcp_hdr(skb
)->check
= 0;
5614 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
5615 base_flags
|= TXD_FLAG_TCPUDP_CSUM
;
5618 #if TG3_VLAN_TAG_USED
5619 if (tp
->vlgrp
!= NULL
&& vlan_tx_tag_present(skb
))
5620 base_flags
|= (TXD_FLAG_VLAN
|
5621 (vlan_tx_tag_get(skb
) << 16));
5624 len
= skb_headlen(skb
);
5626 /* Queue skb data, a.k.a. the main skb fragment. */
5627 mapping
= pci_map_single(tp
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
5628 if (pci_dma_mapping_error(tp
->pdev
, mapping
)) {
5633 tnapi
->tx_buffers
[entry
].skb
= skb
;
5634 dma_unmap_addr_set(&tnapi
->tx_buffers
[entry
], mapping
, mapping
);
5636 if ((tp
->tg3_flags3
& TG3_FLG3_USE_JUMBO_BDFLAG
) &&
5637 !mss
&& skb
->len
> ETH_DATA_LEN
)
5638 base_flags
|= TXD_FLAG_JMB_PKT
;
5640 tg3_set_txd(tnapi
, entry
, mapping
, len
, base_flags
,
5641 (skb_shinfo(skb
)->nr_frags
== 0) | (mss
<< 1));
5643 entry
= NEXT_TX(entry
);
5645 /* Now loop through additional data fragments, and queue them. */
5646 if (skb_shinfo(skb
)->nr_frags
> 0) {
5647 last
= skb_shinfo(skb
)->nr_frags
- 1;
5648 for (i
= 0; i
<= last
; i
++) {
5649 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
5652 mapping
= pci_map_page(tp
->pdev
,
5655 len
, PCI_DMA_TODEVICE
);
5656 if (pci_dma_mapping_error(tp
->pdev
, mapping
))
5659 tnapi
->tx_buffers
[entry
].skb
= NULL
;
5660 dma_unmap_addr_set(&tnapi
->tx_buffers
[entry
], mapping
,
5663 tg3_set_txd(tnapi
, entry
, mapping
, len
,
5664 base_flags
, (i
== last
) | (mss
<< 1));
5666 entry
= NEXT_TX(entry
);
5670 /* Packets are ready, update Tx producer idx local and on card. */
5671 tw32_tx_mbox(tnapi
->prodmbox
, entry
);
5673 tnapi
->tx_prod
= entry
;
5674 if (unlikely(tg3_tx_avail(tnapi
) <= (MAX_SKB_FRAGS
+ 1))) {
5675 netif_tx_stop_queue(txq
);
5676 if (tg3_tx_avail(tnapi
) > TG3_TX_WAKEUP_THRESH(tnapi
))
5677 netif_tx_wake_queue(txq
);
5683 return NETDEV_TX_OK
;
5687 entry
= tnapi
->tx_prod
;
5688 tnapi
->tx_buffers
[entry
].skb
= NULL
;
5689 pci_unmap_single(tp
->pdev
,
5690 dma_unmap_addr(&tnapi
->tx_buffers
[entry
], mapping
),
5693 for (i
= 0; i
<= last
; i
++) {
5694 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
5695 entry
= NEXT_TX(entry
);
5697 pci_unmap_page(tp
->pdev
,
5698 dma_unmap_addr(&tnapi
->tx_buffers
[entry
],
5700 frag
->size
, PCI_DMA_TODEVICE
);
5704 return NETDEV_TX_OK
;
5707 static netdev_tx_t
tg3_start_xmit_dma_bug(struct sk_buff
*,
5708 struct net_device
*);
5710 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5711 * TSO header is greater than 80 bytes.
5713 static int tg3_tso_bug(struct tg3
*tp
, struct sk_buff
*skb
)
5715 struct sk_buff
*segs
, *nskb
;
5716 u32 frag_cnt_est
= skb_shinfo(skb
)->gso_segs
* 3;
5718 /* Estimate the number of fragments in the worst case */
5719 if (unlikely(tg3_tx_avail(&tp
->napi
[0]) <= frag_cnt_est
)) {
5720 netif_stop_queue(tp
->dev
);
5721 if (tg3_tx_avail(&tp
->napi
[0]) <= frag_cnt_est
)
5722 return NETDEV_TX_BUSY
;
5724 netif_wake_queue(tp
->dev
);
5727 segs
= skb_gso_segment(skb
, tp
->dev
->features
& ~NETIF_F_TSO
);
5729 goto tg3_tso_bug_end
;
5735 tg3_start_xmit_dma_bug(nskb
, tp
->dev
);
5741 return NETDEV_TX_OK
;
5744 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5745 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5747 static netdev_tx_t
tg3_start_xmit_dma_bug(struct sk_buff
*skb
,
5748 struct net_device
*dev
)
5750 struct tg3
*tp
= netdev_priv(dev
);
5751 u32 len
, entry
, base_flags
, mss
;
5752 int would_hit_hwbug
;
5754 struct tg3_napi
*tnapi
;
5755 struct netdev_queue
*txq
;
5756 unsigned int i
, last
;
5758 txq
= netdev_get_tx_queue(dev
, skb_get_queue_mapping(skb
));
5759 tnapi
= &tp
->napi
[skb_get_queue_mapping(skb
)];
5760 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)
5763 /* We are running in BH disabled context with netif_tx_lock
5764 * and TX reclaim runs via tp->napi.poll inside of a software
5765 * interrupt. Furthermore, IRQ processing runs lockless so we have
5766 * no IRQ context deadlocks to worry about either. Rejoice!
5768 if (unlikely(tg3_tx_avail(tnapi
) <= (skb_shinfo(skb
)->nr_frags
+ 1))) {
5769 if (!netif_tx_queue_stopped(txq
)) {
5770 netif_tx_stop_queue(txq
);
5772 /* This is a hard error, log it. */
5774 "BUG! Tx Ring full when queue awake!\n");
5776 return NETDEV_TX_BUSY
;
5779 entry
= tnapi
->tx_prod
;
5781 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
5782 base_flags
|= TXD_FLAG_TCPUDP_CSUM
;
5784 mss
= skb_shinfo(skb
)->gso_size
;
5787 u32 tcp_opt_len
, hdr_len
;
5789 if (skb_header_cloned(skb
) &&
5790 pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
)) {
5796 tcp_opt_len
= tcp_optlen(skb
);
5798 if (skb_shinfo(skb
)->gso_type
& SKB_GSO_TCPV6
) {
5799 hdr_len
= skb_headlen(skb
) - ETH_HLEN
;
5803 ip_tcp_len
= ip_hdrlen(skb
) + sizeof(struct tcphdr
);
5804 hdr_len
= ip_tcp_len
+ tcp_opt_len
;
5807 iph
->tot_len
= htons(mss
+ hdr_len
);
5810 if (unlikely((ETH_HLEN
+ hdr_len
) > 80) &&
5811 (tp
->tg3_flags2
& TG3_FLG2_TSO_BUG
))
5812 return tg3_tso_bug(tp
, skb
);
5814 base_flags
|= (TXD_FLAG_CPU_PRE_DMA
|
5815 TXD_FLAG_CPU_POST_DMA
);
5817 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
) {
5818 tcp_hdr(skb
)->check
= 0;
5819 base_flags
&= ~TXD_FLAG_TCPUDP_CSUM
;
5821 tcp_hdr(skb
)->check
= ~csum_tcpudp_magic(iph
->saddr
,
5826 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO_3
) {
5827 mss
|= (hdr_len
& 0xc) << 12;
5829 base_flags
|= 0x00000010;
5830 base_flags
|= (hdr_len
& 0x3e0) << 5;
5831 } else if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO_2
)
5832 mss
|= hdr_len
<< 9;
5833 else if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO_1
) ||
5834 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
5835 if (tcp_opt_len
|| iph
->ihl
> 5) {
5838 tsflags
= (iph
->ihl
- 5) + (tcp_opt_len
>> 2);
5839 mss
|= (tsflags
<< 11);
5842 if (tcp_opt_len
|| iph
->ihl
> 5) {
5845 tsflags
= (iph
->ihl
- 5) + (tcp_opt_len
>> 2);
5846 base_flags
|= tsflags
<< 12;
5850 #if TG3_VLAN_TAG_USED
5851 if (tp
->vlgrp
!= NULL
&& vlan_tx_tag_present(skb
))
5852 base_flags
|= (TXD_FLAG_VLAN
|
5853 (vlan_tx_tag_get(skb
) << 16));
5856 if ((tp
->tg3_flags3
& TG3_FLG3_USE_JUMBO_BDFLAG
) &&
5857 !mss
&& skb
->len
> ETH_DATA_LEN
)
5858 base_flags
|= TXD_FLAG_JMB_PKT
;
5860 len
= skb_headlen(skb
);
5862 mapping
= pci_map_single(tp
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
5863 if (pci_dma_mapping_error(tp
->pdev
, mapping
)) {
5868 tnapi
->tx_buffers
[entry
].skb
= skb
;
5869 dma_unmap_addr_set(&tnapi
->tx_buffers
[entry
], mapping
, mapping
);
5871 would_hit_hwbug
= 0;
5873 if ((tp
->tg3_flags3
& TG3_FLG3_SHORT_DMA_BUG
) && len
<= 8)
5874 would_hit_hwbug
= 1;
5876 if ((tp
->tg3_flags3
& TG3_FLG3_4G_DMA_BNDRY_BUG
) &&
5877 tg3_4g_overflow_test(mapping
, len
))
5878 would_hit_hwbug
= 1;
5880 if ((tp
->tg3_flags3
& TG3_FLG3_40BIT_DMA_LIMIT_BUG
) &&
5881 tg3_40bit_overflow_test(tp
, mapping
, len
))
5882 would_hit_hwbug
= 1;
5884 if (tp
->tg3_flags3
& TG3_FLG3_5701_DMA_BUG
)
5885 would_hit_hwbug
= 1;
5887 tg3_set_txd(tnapi
, entry
, mapping
, len
, base_flags
,
5888 (skb_shinfo(skb
)->nr_frags
== 0) | (mss
<< 1));
5890 entry
= NEXT_TX(entry
);
5892 /* Now loop through additional data fragments, and queue them. */
5893 if (skb_shinfo(skb
)->nr_frags
> 0) {
5894 last
= skb_shinfo(skb
)->nr_frags
- 1;
5895 for (i
= 0; i
<= last
; i
++) {
5896 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
5899 mapping
= pci_map_page(tp
->pdev
,
5902 len
, PCI_DMA_TODEVICE
);
5904 tnapi
->tx_buffers
[entry
].skb
= NULL
;
5905 dma_unmap_addr_set(&tnapi
->tx_buffers
[entry
], mapping
,
5907 if (pci_dma_mapping_error(tp
->pdev
, mapping
))
5910 if ((tp
->tg3_flags3
& TG3_FLG3_SHORT_DMA_BUG
) &&
5912 would_hit_hwbug
= 1;
5914 if ((tp
->tg3_flags3
& TG3_FLG3_4G_DMA_BNDRY_BUG
) &&
5915 tg3_4g_overflow_test(mapping
, len
))
5916 would_hit_hwbug
= 1;
5918 if ((tp
->tg3_flags3
& TG3_FLG3_40BIT_DMA_LIMIT_BUG
) &&
5919 tg3_40bit_overflow_test(tp
, mapping
, len
))
5920 would_hit_hwbug
= 1;
5922 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
5923 tg3_set_txd(tnapi
, entry
, mapping
, len
,
5924 base_flags
, (i
== last
)|(mss
<< 1));
5926 tg3_set_txd(tnapi
, entry
, mapping
, len
,
5927 base_flags
, (i
== last
));
5929 entry
= NEXT_TX(entry
);
5933 if (would_hit_hwbug
) {
5934 u32 last_plus_one
= entry
;
5937 start
= entry
- 1 - skb_shinfo(skb
)->nr_frags
;
5938 start
&= (TG3_TX_RING_SIZE
- 1);
5940 /* If the workaround fails due to memory/mapping
5941 * failure, silently drop this packet.
5943 if (tigon3_dma_hwbug_workaround(tnapi
, skb
, last_plus_one
,
5944 &start
, base_flags
, mss
))
5950 /* Packets are ready, update Tx producer idx local and on card. */
5951 tw32_tx_mbox(tnapi
->prodmbox
, entry
);
5953 tnapi
->tx_prod
= entry
;
5954 if (unlikely(tg3_tx_avail(tnapi
) <= (MAX_SKB_FRAGS
+ 1))) {
5955 netif_tx_stop_queue(txq
);
5956 if (tg3_tx_avail(tnapi
) > TG3_TX_WAKEUP_THRESH(tnapi
))
5957 netif_tx_wake_queue(txq
);
5963 return NETDEV_TX_OK
;
5967 entry
= tnapi
->tx_prod
;
5968 tnapi
->tx_buffers
[entry
].skb
= NULL
;
5969 pci_unmap_single(tp
->pdev
,
5970 dma_unmap_addr(&tnapi
->tx_buffers
[entry
], mapping
),
5973 for (i
= 0; i
<= last
; i
++) {
5974 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
5975 entry
= NEXT_TX(entry
);
5977 pci_unmap_page(tp
->pdev
,
5978 dma_unmap_addr(&tnapi
->tx_buffers
[entry
],
5980 frag
->size
, PCI_DMA_TODEVICE
);
5984 return NETDEV_TX_OK
;
5987 static inline void tg3_set_mtu(struct net_device
*dev
, struct tg3
*tp
,
5992 if (new_mtu
> ETH_DATA_LEN
) {
5993 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) {
5994 tp
->tg3_flags2
&= ~TG3_FLG2_TSO_CAPABLE
;
5995 ethtool_op_set_tso(dev
, 0);
5997 tp
->tg3_flags
|= TG3_FLAG_JUMBO_RING_ENABLE
;
6000 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)
6001 tp
->tg3_flags2
|= TG3_FLG2_TSO_CAPABLE
;
6002 tp
->tg3_flags
&= ~TG3_FLAG_JUMBO_RING_ENABLE
;
6006 static int tg3_change_mtu(struct net_device
*dev
, int new_mtu
)
6008 struct tg3
*tp
= netdev_priv(dev
);
6011 if (new_mtu
< TG3_MIN_MTU
|| new_mtu
> TG3_MAX_MTU(tp
))
6014 if (!netif_running(dev
)) {
6015 /* We'll just catch it later when the
6018 tg3_set_mtu(dev
, tp
, new_mtu
);
6026 tg3_full_lock(tp
, 1);
6028 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
6030 tg3_set_mtu(dev
, tp
, new_mtu
);
6032 err
= tg3_restart_hw(tp
, 0);
6035 tg3_netif_start(tp
);
6037 tg3_full_unlock(tp
);
6045 static void tg3_rx_prodring_free(struct tg3
*tp
,
6046 struct tg3_rx_prodring_set
*tpr
)
6050 if (tpr
!= &tp
->prodring
[0]) {
6051 for (i
= tpr
->rx_std_cons_idx
; i
!= tpr
->rx_std_prod_idx
;
6052 i
= (i
+ 1) % TG3_RX_RING_SIZE
)
6053 tg3_rx_skb_free(tp
, &tpr
->rx_std_buffers
[i
],
6056 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) {
6057 for (i
= tpr
->rx_jmb_cons_idx
;
6058 i
!= tpr
->rx_jmb_prod_idx
;
6059 i
= (i
+ 1) % TG3_RX_JUMBO_RING_SIZE
) {
6060 tg3_rx_skb_free(tp
, &tpr
->rx_jmb_buffers
[i
],
6068 for (i
= 0; i
< TG3_RX_RING_SIZE
; i
++)
6069 tg3_rx_skb_free(tp
, &tpr
->rx_std_buffers
[i
],
6072 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) {
6073 for (i
= 0; i
< TG3_RX_JUMBO_RING_SIZE
; i
++)
6074 tg3_rx_skb_free(tp
, &tpr
->rx_jmb_buffers
[i
],
6079 /* Initialize rx rings for packet processing.
6081 * The chip has been shut down and the driver detached from
6082 * the networking, so no interrupts or new tx packets will
6083 * end up in the driver. tp->{tx,}lock are held and thus
6086 static int tg3_rx_prodring_alloc(struct tg3
*tp
,
6087 struct tg3_rx_prodring_set
*tpr
)
6089 u32 i
, rx_pkt_dma_sz
;
6091 tpr
->rx_std_cons_idx
= 0;
6092 tpr
->rx_std_prod_idx
= 0;
6093 tpr
->rx_jmb_cons_idx
= 0;
6094 tpr
->rx_jmb_prod_idx
= 0;
6096 if (tpr
!= &tp
->prodring
[0]) {
6097 memset(&tpr
->rx_std_buffers
[0], 0, TG3_RX_STD_BUFF_RING_SIZE
);
6098 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
)
6099 memset(&tpr
->rx_jmb_buffers
[0], 0,
6100 TG3_RX_JMB_BUFF_RING_SIZE
);
6104 /* Zero out all descriptors. */
6105 memset(tpr
->rx_std
, 0, TG3_RX_RING_BYTES
);
6107 rx_pkt_dma_sz
= TG3_RX_STD_DMA_SZ
;
6108 if ((tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) &&
6109 tp
->dev
->mtu
> ETH_DATA_LEN
)
6110 rx_pkt_dma_sz
= TG3_RX_JMB_DMA_SZ
;
6111 tp
->rx_pkt_map_sz
= TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz
);
6113 /* Initialize invariants of the rings, we only set this
6114 * stuff once. This works because the card does not
6115 * write into the rx buffer posting rings.
6117 for (i
= 0; i
< TG3_RX_RING_SIZE
; i
++) {
6118 struct tg3_rx_buffer_desc
*rxd
;
6120 rxd
= &tpr
->rx_std
[i
];
6121 rxd
->idx_len
= rx_pkt_dma_sz
<< RXD_LEN_SHIFT
;
6122 rxd
->type_flags
= (RXD_FLAG_END
<< RXD_FLAGS_SHIFT
);
6123 rxd
->opaque
= (RXD_OPAQUE_RING_STD
|
6124 (i
<< RXD_OPAQUE_INDEX_SHIFT
));
6127 /* Now allocate fresh SKBs for each rx ring. */
6128 for (i
= 0; i
< tp
->rx_pending
; i
++) {
6129 if (tg3_alloc_rx_skb(tp
, tpr
, RXD_OPAQUE_RING_STD
, i
) < 0) {
6130 netdev_warn(tp
->dev
,
6131 "Using a smaller RX standard ring. Only "
6132 "%d out of %d buffers were allocated "
6133 "successfully\n", i
, tp
->rx_pending
);
6141 if (!(tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
))
6144 memset(tpr
->rx_jmb
, 0, TG3_RX_JUMBO_RING_BYTES
);
6146 if (!(tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
))
6149 for (i
= 0; i
< TG3_RX_JUMBO_RING_SIZE
; i
++) {
6150 struct tg3_rx_buffer_desc
*rxd
;
6152 rxd
= &tpr
->rx_jmb
[i
].std
;
6153 rxd
->idx_len
= TG3_RX_JMB_DMA_SZ
<< RXD_LEN_SHIFT
;
6154 rxd
->type_flags
= (RXD_FLAG_END
<< RXD_FLAGS_SHIFT
) |
6156 rxd
->opaque
= (RXD_OPAQUE_RING_JUMBO
|
6157 (i
<< RXD_OPAQUE_INDEX_SHIFT
));
6160 for (i
= 0; i
< tp
->rx_jumbo_pending
; i
++) {
6161 if (tg3_alloc_rx_skb(tp
, tpr
, RXD_OPAQUE_RING_JUMBO
, i
) < 0) {
6162 netdev_warn(tp
->dev
,
6163 "Using a smaller RX jumbo ring. Only %d "
6164 "out of %d buffers were allocated "
6165 "successfully\n", i
, tp
->rx_jumbo_pending
);
6168 tp
->rx_jumbo_pending
= i
;
6177 tg3_rx_prodring_free(tp
, tpr
);
6181 static void tg3_rx_prodring_fini(struct tg3
*tp
,
6182 struct tg3_rx_prodring_set
*tpr
)
6184 kfree(tpr
->rx_std_buffers
);
6185 tpr
->rx_std_buffers
= NULL
;
6186 kfree(tpr
->rx_jmb_buffers
);
6187 tpr
->rx_jmb_buffers
= NULL
;
6189 pci_free_consistent(tp
->pdev
, TG3_RX_RING_BYTES
,
6190 tpr
->rx_std
, tpr
->rx_std_mapping
);
6194 pci_free_consistent(tp
->pdev
, TG3_RX_JUMBO_RING_BYTES
,
6195 tpr
->rx_jmb
, tpr
->rx_jmb_mapping
);
6200 static int tg3_rx_prodring_init(struct tg3
*tp
,
6201 struct tg3_rx_prodring_set
*tpr
)
6203 tpr
->rx_std_buffers
= kzalloc(TG3_RX_STD_BUFF_RING_SIZE
, GFP_KERNEL
);
6204 if (!tpr
->rx_std_buffers
)
6207 tpr
->rx_std
= pci_alloc_consistent(tp
->pdev
, TG3_RX_RING_BYTES
,
6208 &tpr
->rx_std_mapping
);
6212 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) {
6213 tpr
->rx_jmb_buffers
= kzalloc(TG3_RX_JMB_BUFF_RING_SIZE
,
6215 if (!tpr
->rx_jmb_buffers
)
6218 tpr
->rx_jmb
= pci_alloc_consistent(tp
->pdev
,
6219 TG3_RX_JUMBO_RING_BYTES
,
6220 &tpr
->rx_jmb_mapping
);
6228 tg3_rx_prodring_fini(tp
, tpr
);
6232 /* Free up pending packets in all rx/tx rings.
6234 * The chip has been shut down and the driver detached from
6235 * the networking, so no interrupts or new tx packets will
6236 * end up in the driver. tp->{tx,}lock is not held and we are not
6237 * in an interrupt context and thus may sleep.
6239 static void tg3_free_rings(struct tg3
*tp
)
6243 for (j
= 0; j
< tp
->irq_cnt
; j
++) {
6244 struct tg3_napi
*tnapi
= &tp
->napi
[j
];
6246 tg3_rx_prodring_free(tp
, &tp
->prodring
[j
]);
6248 if (!tnapi
->tx_buffers
)
6251 for (i
= 0; i
< TG3_TX_RING_SIZE
; ) {
6252 struct ring_info
*txp
;
6253 struct sk_buff
*skb
;
6256 txp
= &tnapi
->tx_buffers
[i
];
6264 pci_unmap_single(tp
->pdev
,
6265 dma_unmap_addr(txp
, mapping
),
6272 for (k
= 0; k
< skb_shinfo(skb
)->nr_frags
; k
++) {
6273 txp
= &tnapi
->tx_buffers
[i
& (TG3_TX_RING_SIZE
- 1)];
6274 pci_unmap_page(tp
->pdev
,
6275 dma_unmap_addr(txp
, mapping
),
6276 skb_shinfo(skb
)->frags
[k
].size
,
6281 dev_kfree_skb_any(skb
);
6286 /* Initialize tx/rx rings for packet processing.
6288 * The chip has been shut down and the driver detached from
6289 * the networking, so no interrupts or new tx packets will
6290 * end up in the driver. tp->{tx,}lock are held and thus
6293 static int tg3_init_rings(struct tg3
*tp
)
6297 /* Free up all the SKBs. */
6300 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
6301 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
6303 tnapi
->last_tag
= 0;
6304 tnapi
->last_irq_tag
= 0;
6305 tnapi
->hw_status
->status
= 0;
6306 tnapi
->hw_status
->status_tag
= 0;
6307 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
6312 memset(tnapi
->tx_ring
, 0, TG3_TX_RING_BYTES
);
6314 tnapi
->rx_rcb_ptr
= 0;
6316 memset(tnapi
->rx_rcb
, 0, TG3_RX_RCB_RING_BYTES(tp
));
6318 if (tg3_rx_prodring_alloc(tp
, &tp
->prodring
[i
])) {
6328 * Must not be invoked with interrupt sources disabled and
6329 * the hardware shutdown down.
6331 static void tg3_free_consistent(struct tg3
*tp
)
6335 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
6336 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
6338 if (tnapi
->tx_ring
) {
6339 pci_free_consistent(tp
->pdev
, TG3_TX_RING_BYTES
,
6340 tnapi
->tx_ring
, tnapi
->tx_desc_mapping
);
6341 tnapi
->tx_ring
= NULL
;
6344 kfree(tnapi
->tx_buffers
);
6345 tnapi
->tx_buffers
= NULL
;
6347 if (tnapi
->rx_rcb
) {
6348 pci_free_consistent(tp
->pdev
, TG3_RX_RCB_RING_BYTES(tp
),
6350 tnapi
->rx_rcb_mapping
);
6351 tnapi
->rx_rcb
= NULL
;
6354 if (tnapi
->hw_status
) {
6355 pci_free_consistent(tp
->pdev
, TG3_HW_STATUS_SIZE
,
6357 tnapi
->status_mapping
);
6358 tnapi
->hw_status
= NULL
;
6363 pci_free_consistent(tp
->pdev
, sizeof(struct tg3_hw_stats
),
6364 tp
->hw_stats
, tp
->stats_mapping
);
6365 tp
->hw_stats
= NULL
;
6368 for (i
= 0; i
< tp
->irq_cnt
; i
++)
6369 tg3_rx_prodring_fini(tp
, &tp
->prodring
[i
]);
6373 * Must not be invoked with interrupt sources disabled and
6374 * the hardware shutdown down. Can sleep.
6376 static int tg3_alloc_consistent(struct tg3
*tp
)
6380 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
6381 if (tg3_rx_prodring_init(tp
, &tp
->prodring
[i
]))
6385 tp
->hw_stats
= pci_alloc_consistent(tp
->pdev
,
6386 sizeof(struct tg3_hw_stats
),
6387 &tp
->stats_mapping
);
6391 memset(tp
->hw_stats
, 0, sizeof(struct tg3_hw_stats
));
6393 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
6394 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
6395 struct tg3_hw_status
*sblk
;
6397 tnapi
->hw_status
= pci_alloc_consistent(tp
->pdev
,
6399 &tnapi
->status_mapping
);
6400 if (!tnapi
->hw_status
)
6403 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
6404 sblk
= tnapi
->hw_status
;
6406 /* If multivector TSS is enabled, vector 0 does not handle
6407 * tx interrupts. Don't allocate any resources for it.
6409 if ((!i
&& !(tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)) ||
6410 (i
&& (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
))) {
6411 tnapi
->tx_buffers
= kzalloc(sizeof(struct ring_info
) *
6414 if (!tnapi
->tx_buffers
)
6417 tnapi
->tx_ring
= pci_alloc_consistent(tp
->pdev
,
6419 &tnapi
->tx_desc_mapping
);
6420 if (!tnapi
->tx_ring
)
6425 * When RSS is enabled, the status block format changes
6426 * slightly. The "rx_jumbo_consumer", "reserved",
6427 * and "rx_mini_consumer" members get mapped to the
6428 * other three rx return ring producer indexes.
6432 tnapi
->rx_rcb_prod_idx
= &sblk
->idx
[0].rx_producer
;
6435 tnapi
->rx_rcb_prod_idx
= &sblk
->rx_jumbo_consumer
;
6438 tnapi
->rx_rcb_prod_idx
= &sblk
->reserved
;
6441 tnapi
->rx_rcb_prod_idx
= &sblk
->rx_mini_consumer
;
6445 tnapi
->prodring
= &tp
->prodring
[i
];
6448 * If multivector RSS is enabled, vector 0 does not handle
6449 * rx or tx interrupts. Don't allocate any resources for it.
6451 if (!i
&& (tp
->tg3_flags3
& TG3_FLG3_ENABLE_RSS
))
6454 tnapi
->rx_rcb
= pci_alloc_consistent(tp
->pdev
,
6455 TG3_RX_RCB_RING_BYTES(tp
),
6456 &tnapi
->rx_rcb_mapping
);
6460 memset(tnapi
->rx_rcb
, 0, TG3_RX_RCB_RING_BYTES(tp
));
6466 tg3_free_consistent(tp
);
6470 #define MAX_WAIT_CNT 1000
6472 /* To stop a block, clear the enable bit and poll till it
6473 * clears. tp->lock is held.
6475 static int tg3_stop_block(struct tg3
*tp
, unsigned long ofs
, u32 enable_bit
, int silent
)
6480 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
6487 /* We can't enable/disable these bits of the
6488 * 5705/5750, just say success.
6501 for (i
= 0; i
< MAX_WAIT_CNT
; i
++) {
6504 if ((val
& enable_bit
) == 0)
6508 if (i
== MAX_WAIT_CNT
&& !silent
) {
6509 dev_err(&tp
->pdev
->dev
,
6510 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6518 /* tp->lock is held. */
6519 static int tg3_abort_hw(struct tg3
*tp
, int silent
)
6523 tg3_disable_ints(tp
);
6525 tp
->rx_mode
&= ~RX_MODE_ENABLE
;
6526 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
6529 err
= tg3_stop_block(tp
, RCVBDI_MODE
, RCVBDI_MODE_ENABLE
, silent
);
6530 err
|= tg3_stop_block(tp
, RCVLPC_MODE
, RCVLPC_MODE_ENABLE
, silent
);
6531 err
|= tg3_stop_block(tp
, RCVLSC_MODE
, RCVLSC_MODE_ENABLE
, silent
);
6532 err
|= tg3_stop_block(tp
, RCVDBDI_MODE
, RCVDBDI_MODE_ENABLE
, silent
);
6533 err
|= tg3_stop_block(tp
, RCVDCC_MODE
, RCVDCC_MODE_ENABLE
, silent
);
6534 err
|= tg3_stop_block(tp
, RCVCC_MODE
, RCVCC_MODE_ENABLE
, silent
);
6536 err
|= tg3_stop_block(tp
, SNDBDS_MODE
, SNDBDS_MODE_ENABLE
, silent
);
6537 err
|= tg3_stop_block(tp
, SNDBDI_MODE
, SNDBDI_MODE_ENABLE
, silent
);
6538 err
|= tg3_stop_block(tp
, SNDDATAI_MODE
, SNDDATAI_MODE_ENABLE
, silent
);
6539 err
|= tg3_stop_block(tp
, RDMAC_MODE
, RDMAC_MODE_ENABLE
, silent
);
6540 err
|= tg3_stop_block(tp
, SNDDATAC_MODE
, SNDDATAC_MODE_ENABLE
, silent
);
6541 err
|= tg3_stop_block(tp
, DMAC_MODE
, DMAC_MODE_ENABLE
, silent
);
6542 err
|= tg3_stop_block(tp
, SNDBDC_MODE
, SNDBDC_MODE_ENABLE
, silent
);
6544 tp
->mac_mode
&= ~MAC_MODE_TDE_ENABLE
;
6545 tw32_f(MAC_MODE
, tp
->mac_mode
);
6548 tp
->tx_mode
&= ~TX_MODE_ENABLE
;
6549 tw32_f(MAC_TX_MODE
, tp
->tx_mode
);
6551 for (i
= 0; i
< MAX_WAIT_CNT
; i
++) {
6553 if (!(tr32(MAC_TX_MODE
) & TX_MODE_ENABLE
))
6556 if (i
>= MAX_WAIT_CNT
) {
6557 dev_err(&tp
->pdev
->dev
,
6558 "%s timed out, TX_MODE_ENABLE will not clear "
6559 "MAC_TX_MODE=%08x\n", __func__
, tr32(MAC_TX_MODE
));
6563 err
|= tg3_stop_block(tp
, HOSTCC_MODE
, HOSTCC_MODE_ENABLE
, silent
);
6564 err
|= tg3_stop_block(tp
, WDMAC_MODE
, WDMAC_MODE_ENABLE
, silent
);
6565 err
|= tg3_stop_block(tp
, MBFREE_MODE
, MBFREE_MODE_ENABLE
, silent
);
6567 tw32(FTQ_RESET
, 0xffffffff);
6568 tw32(FTQ_RESET
, 0x00000000);
6570 err
|= tg3_stop_block(tp
, BUFMGR_MODE
, BUFMGR_MODE_ENABLE
, silent
);
6571 err
|= tg3_stop_block(tp
, MEMARB_MODE
, MEMARB_MODE_ENABLE
, silent
);
6573 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
6574 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
6575 if (tnapi
->hw_status
)
6576 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
6579 memset(tp
->hw_stats
, 0, sizeof(struct tg3_hw_stats
));
6584 static void tg3_ape_send_event(struct tg3
*tp
, u32 event
)
6589 apedata
= tg3_ape_read32(tp
, TG3_APE_SEG_SIG
);
6590 if (apedata
!= APE_SEG_SIG_MAGIC
)
6593 apedata
= tg3_ape_read32(tp
, TG3_APE_FW_STATUS
);
6594 if (!(apedata
& APE_FW_STATUS_READY
))
6597 /* Wait for up to 1 millisecond for APE to service previous event. */
6598 for (i
= 0; i
< 10; i
++) {
6599 if (tg3_ape_lock(tp
, TG3_APE_LOCK_MEM
))
6602 apedata
= tg3_ape_read32(tp
, TG3_APE_EVENT_STATUS
);
6604 if (!(apedata
& APE_EVENT_STATUS_EVENT_PENDING
))
6605 tg3_ape_write32(tp
, TG3_APE_EVENT_STATUS
,
6606 event
| APE_EVENT_STATUS_EVENT_PENDING
);
6608 tg3_ape_unlock(tp
, TG3_APE_LOCK_MEM
);
6610 if (!(apedata
& APE_EVENT_STATUS_EVENT_PENDING
))
6616 if (!(apedata
& APE_EVENT_STATUS_EVENT_PENDING
))
6617 tg3_ape_write32(tp
, TG3_APE_EVENT
, APE_EVENT_1
);
6620 static void tg3_ape_driver_state_change(struct tg3
*tp
, int kind
)
6625 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
))
6629 case RESET_KIND_INIT
:
6630 tg3_ape_write32(tp
, TG3_APE_HOST_SEG_SIG
,
6631 APE_HOST_SEG_SIG_MAGIC
);
6632 tg3_ape_write32(tp
, TG3_APE_HOST_SEG_LEN
,
6633 APE_HOST_SEG_LEN_MAGIC
);
6634 apedata
= tg3_ape_read32(tp
, TG3_APE_HOST_INIT_COUNT
);
6635 tg3_ape_write32(tp
, TG3_APE_HOST_INIT_COUNT
, ++apedata
);
6636 tg3_ape_write32(tp
, TG3_APE_HOST_DRIVER_ID
,
6637 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM
, TG3_MIN_NUM
));
6638 tg3_ape_write32(tp
, TG3_APE_HOST_BEHAVIOR
,
6639 APE_HOST_BEHAV_NO_PHYLOCK
);
6641 event
= APE_EVENT_STATUS_STATE_START
;
6643 case RESET_KIND_SHUTDOWN
:
6644 /* With the interface we are currently using,
6645 * APE does not track driver state. Wiping
6646 * out the HOST SEGMENT SIGNATURE forces
6647 * the APE to assume OS absent status.
6649 tg3_ape_write32(tp
, TG3_APE_HOST_SEG_SIG
, 0x0);
6651 event
= APE_EVENT_STATUS_STATE_UNLOAD
;
6653 case RESET_KIND_SUSPEND
:
6654 event
= APE_EVENT_STATUS_STATE_SUSPEND
;
6660 event
|= APE_EVENT_STATUS_DRIVER_EVNT
| APE_EVENT_STATUS_STATE_CHNGE
;
6662 tg3_ape_send_event(tp
, event
);
6665 /* tp->lock is held. */
6666 static void tg3_write_sig_pre_reset(struct tg3
*tp
, int kind
)
6668 tg3_write_mem(tp
, NIC_SRAM_FIRMWARE_MBOX
,
6669 NIC_SRAM_FIRMWARE_MBOX_MAGIC1
);
6671 if (tp
->tg3_flags2
& TG3_FLG2_ASF_NEW_HANDSHAKE
) {
6673 case RESET_KIND_INIT
:
6674 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6678 case RESET_KIND_SHUTDOWN
:
6679 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6683 case RESET_KIND_SUSPEND
:
6684 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6693 if (kind
== RESET_KIND_INIT
||
6694 kind
== RESET_KIND_SUSPEND
)
6695 tg3_ape_driver_state_change(tp
, kind
);
6698 /* tp->lock is held. */
6699 static void tg3_write_sig_post_reset(struct tg3
*tp
, int kind
)
6701 if (tp
->tg3_flags2
& TG3_FLG2_ASF_NEW_HANDSHAKE
) {
6703 case RESET_KIND_INIT
:
6704 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6705 DRV_STATE_START_DONE
);
6708 case RESET_KIND_SHUTDOWN
:
6709 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6710 DRV_STATE_UNLOAD_DONE
);
6718 if (kind
== RESET_KIND_SHUTDOWN
)
6719 tg3_ape_driver_state_change(tp
, kind
);
6722 /* tp->lock is held. */
6723 static void tg3_write_sig_legacy(struct tg3
*tp
, int kind
)
6725 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) {
6727 case RESET_KIND_INIT
:
6728 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6732 case RESET_KIND_SHUTDOWN
:
6733 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6737 case RESET_KIND_SUSPEND
:
6738 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6748 static int tg3_poll_fw(struct tg3
*tp
)
6753 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
6754 /* Wait up to 20ms for init done. */
6755 for (i
= 0; i
< 200; i
++) {
6756 if (tr32(VCPU_STATUS
) & VCPU_STATUS_INIT_DONE
)
6763 /* Wait for firmware initialization to complete. */
6764 for (i
= 0; i
< 100000; i
++) {
6765 tg3_read_mem(tp
, NIC_SRAM_FIRMWARE_MBOX
, &val
);
6766 if (val
== ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1
)
6771 /* Chip might not be fitted with firmware. Some Sun onboard
6772 * parts are configured like that. So don't signal the timeout
6773 * of the above loop as an error, but do report the lack of
6774 * running firmware once.
6777 !(tp
->tg3_flags2
& TG3_FLG2_NO_FWARE_REPORTED
)) {
6778 tp
->tg3_flags2
|= TG3_FLG2_NO_FWARE_REPORTED
;
6780 netdev_info(tp
->dev
, "No firmware running\n");
6783 if (tp
->pci_chip_rev_id
== CHIPREV_ID_57765_A0
) {
6784 /* The 57765 A0 needs a little more
6785 * time to do some important work.
6793 /* Save PCI command register before chip reset */
6794 static void tg3_save_pci_state(struct tg3
*tp
)
6796 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &tp
->pci_cmd
);
6799 /* Restore PCI state after chip reset */
6800 static void tg3_restore_pci_state(struct tg3
*tp
)
6804 /* Re-enable indirect register accesses. */
6805 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
6806 tp
->misc_host_ctrl
);
6808 /* Set MAX PCI retry to zero. */
6809 val
= (PCISTATE_ROM_ENABLE
| PCISTATE_ROM_RETRY_ENABLE
);
6810 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
&&
6811 (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
))
6812 val
|= PCISTATE_RETRY_SAME_DMA
;
6813 /* Allow reads and writes to the APE register and memory space. */
6814 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
6815 val
|= PCISTATE_ALLOW_APE_CTLSPC_WR
|
6816 PCISTATE_ALLOW_APE_SHMEM_WR
|
6817 PCISTATE_ALLOW_APE_PSPACE_WR
;
6818 pci_write_config_dword(tp
->pdev
, TG3PCI_PCISTATE
, val
);
6820 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, tp
->pci_cmd
);
6822 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5785
) {
6823 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)
6824 pcie_set_readrq(tp
->pdev
, 4096);
6826 pci_write_config_byte(tp
->pdev
, PCI_CACHE_LINE_SIZE
,
6827 tp
->pci_cacheline_sz
);
6828 pci_write_config_byte(tp
->pdev
, PCI_LATENCY_TIMER
,
6833 /* Make sure PCI-X relaxed ordering bit is clear. */
6834 if (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) {
6837 pci_read_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
6839 pcix_cmd
&= ~PCI_X_CMD_ERO
;
6840 pci_write_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
6844 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) {
6846 /* Chip reset on 5780 will reset MSI enable bit,
6847 * so need to restore it.
6849 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
6852 pci_read_config_word(tp
->pdev
,
6853 tp
->msi_cap
+ PCI_MSI_FLAGS
,
6855 pci_write_config_word(tp
->pdev
,
6856 tp
->msi_cap
+ PCI_MSI_FLAGS
,
6857 ctrl
| PCI_MSI_FLAGS_ENABLE
);
6858 val
= tr32(MSGINT_MODE
);
6859 tw32(MSGINT_MODE
, val
| MSGINT_MODE_ENABLE
);
6864 static void tg3_stop_fw(struct tg3
*);
6866 /* tp->lock is held. */
6867 static int tg3_chip_reset(struct tg3
*tp
)
6870 void (*write_op
)(struct tg3
*, u32
, u32
);
6875 tg3_ape_lock(tp
, TG3_APE_LOCK_GRC
);
6877 /* No matching tg3_nvram_unlock() after this because
6878 * chip reset below will undo the nvram lock.
6880 tp
->nvram_lock_cnt
= 0;
6882 /* GRC_MISC_CFG core clock reset will clear the memory
6883 * enable bit in PCI register 4 and the MSI enable bit
6884 * on some chips, so we save relevant registers here.
6886 tg3_save_pci_state(tp
);
6888 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
||
6889 (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
))
6890 tw32(GRC_FASTBOOT_PC
, 0);
6893 * We must avoid the readl() that normally takes place.
6894 * It locks machines, causes machine checks, and other
6895 * fun things. So, temporarily disable the 5701
6896 * hardware workaround, while we do the reset.
6898 write_op
= tp
->write32
;
6899 if (write_op
== tg3_write_flush_reg32
)
6900 tp
->write32
= tg3_write32
;
6902 /* Prevent the irq handler from reading or writing PCI registers
6903 * during chip reset when the memory enable bit in the PCI command
6904 * register may be cleared. The chip does not generate interrupt
6905 * at this time, but the irq handler may still be called due to irq
6906 * sharing or irqpoll.
6908 tp
->tg3_flags
|= TG3_FLAG_CHIP_RESETTING
;
6909 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
6910 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
6911 if (tnapi
->hw_status
) {
6912 tnapi
->hw_status
->status
= 0;
6913 tnapi
->hw_status
->status_tag
= 0;
6915 tnapi
->last_tag
= 0;
6916 tnapi
->last_irq_tag
= 0;
6920 for (i
= 0; i
< tp
->irq_cnt
; i
++)
6921 synchronize_irq(tp
->napi
[i
].irq_vec
);
6923 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
) {
6924 val
= tr32(TG3_PCIE_LNKCTL
) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN
;
6925 tw32(TG3_PCIE_LNKCTL
, val
| TG3_PCIE_LNKCTL_L1_PLL_PD_DIS
);
6929 val
= GRC_MISC_CFG_CORECLK_RESET
;
6931 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
6932 if (tr32(0x7e2c) == 0x60) {
6935 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
) {
6936 tw32(GRC_MISC_CFG
, (1 << 29));
6941 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
6942 tw32(VCPU_STATUS
, tr32(VCPU_STATUS
) | VCPU_STATUS_DRV_RESET
);
6943 tw32(GRC_VCPU_EXT_CTRL
,
6944 tr32(GRC_VCPU_EXT_CTRL
) & ~GRC_VCPU_EXT_CTRL_HALT_CPU
);
6947 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
6948 val
|= GRC_MISC_CFG_KEEP_GPHY_POWER
;
6949 tw32(GRC_MISC_CFG
, val
);
6951 /* restore 5701 hardware bug workaround write method */
6952 tp
->write32
= write_op
;
6954 /* Unfortunately, we have to delay before the PCI read back.
6955 * Some 575X chips even will not respond to a PCI cfg access
6956 * when the reset command is given to the chip.
6958 * How do these hardware designers expect things to work
6959 * properly if the PCI write is posted for a long period
6960 * of time? It is always necessary to have some method by
6961 * which a register read back can occur to push the write
6962 * out which does the reset.
6964 * For most tg3 variants the trick below was working.
6969 /* Flush PCI posted writes. The normal MMIO registers
6970 * are inaccessible at this time so this is the only
6971 * way to make this reliably (actually, this is no longer
6972 * the case, see above). I tried to use indirect
6973 * register read/write but this upset some 5701 variants.
6975 pci_read_config_dword(tp
->pdev
, PCI_COMMAND
, &val
);
6979 if ((tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) && tp
->pcie_cap
) {
6982 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5750_A0
) {
6986 /* Wait for link training to complete. */
6987 for (i
= 0; i
< 5000; i
++)
6990 pci_read_config_dword(tp
->pdev
, 0xc4, &cfg_val
);
6991 pci_write_config_dword(tp
->pdev
, 0xc4,
6992 cfg_val
| (1 << 15));
6995 /* Clear the "no snoop" and "relaxed ordering" bits. */
6996 pci_read_config_word(tp
->pdev
,
6997 tp
->pcie_cap
+ PCI_EXP_DEVCTL
,
6999 val16
&= ~(PCI_EXP_DEVCTL_RELAX_EN
|
7000 PCI_EXP_DEVCTL_NOSNOOP_EN
);
7002 * Older PCIe devices only support the 128 byte
7003 * MPS setting. Enforce the restriction.
7005 if (!(tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) ||
7006 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
))
7007 val16
&= ~PCI_EXP_DEVCTL_PAYLOAD
;
7008 pci_write_config_word(tp
->pdev
,
7009 tp
->pcie_cap
+ PCI_EXP_DEVCTL
,
7012 pcie_set_readrq(tp
->pdev
, 4096);
7014 /* Clear error status */
7015 pci_write_config_word(tp
->pdev
,
7016 tp
->pcie_cap
+ PCI_EXP_DEVSTA
,
7017 PCI_EXP_DEVSTA_CED
|
7018 PCI_EXP_DEVSTA_NFED
|
7019 PCI_EXP_DEVSTA_FED
|
7020 PCI_EXP_DEVSTA_URD
);
7023 tg3_restore_pci_state(tp
);
7025 tp
->tg3_flags
&= ~TG3_FLAG_CHIP_RESETTING
;
7028 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)
7029 val
= tr32(MEMARB_MODE
);
7030 tw32(MEMARB_MODE
, val
| MEMARB_MODE_ENABLE
);
7032 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5750_A3
) {
7034 tw32(0x5000, 0x400);
7037 tw32(GRC_MODE
, tp
->grc_mode
);
7039 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A0
) {
7042 tw32(0xc4, val
| (1 << 15));
7045 if ((tp
->nic_sram_data_cfg
& NIC_SRAM_DATA_CFG_MINI_PCI
) != 0 &&
7046 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
7047 tp
->pci_clock_ctrl
|= CLOCK_CTRL_CLKRUN_OENABLE
;
7048 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A0
)
7049 tp
->pci_clock_ctrl
|= CLOCK_CTRL_FORCE_CLKRUN
;
7050 tw32(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
);
7053 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
7054 tp
->mac_mode
= MAC_MODE_PORT_MODE_TBI
;
7055 tw32_f(MAC_MODE
, tp
->mac_mode
);
7056 } else if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
) {
7057 tp
->mac_mode
= MAC_MODE_PORT_MODE_GMII
;
7058 tw32_f(MAC_MODE
, tp
->mac_mode
);
7059 } else if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
7060 tp
->mac_mode
&= (MAC_MODE_APE_TX_EN
| MAC_MODE_APE_RX_EN
);
7061 if (tp
->mac_mode
& MAC_MODE_APE_TX_EN
)
7062 tp
->mac_mode
|= MAC_MODE_TDE_ENABLE
;
7063 tw32_f(MAC_MODE
, tp
->mac_mode
);
7065 tw32_f(MAC_MODE
, 0);
7068 tg3_ape_unlock(tp
, TG3_APE_LOCK_GRC
);
7070 err
= tg3_poll_fw(tp
);
7076 if ((tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) &&
7077 tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
&&
7078 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5785
&&
7079 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5717
&&
7080 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5719
&&
7081 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_57765
) {
7084 tw32(0x7c00, val
| (1 << 25));
7087 /* Reprobe ASF enable state. */
7088 tp
->tg3_flags
&= ~TG3_FLAG_ENABLE_ASF
;
7089 tp
->tg3_flags2
&= ~TG3_FLG2_ASF_NEW_HANDSHAKE
;
7090 tg3_read_mem(tp
, NIC_SRAM_DATA_SIG
, &val
);
7091 if (val
== NIC_SRAM_DATA_SIG_MAGIC
) {
7094 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG
, &nic_cfg
);
7095 if (nic_cfg
& NIC_SRAM_DATA_CFG_ASF_ENABLE
) {
7096 tp
->tg3_flags
|= TG3_FLAG_ENABLE_ASF
;
7097 tp
->last_event_jiffies
= jiffies
;
7098 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
7099 tp
->tg3_flags2
|= TG3_FLG2_ASF_NEW_HANDSHAKE
;
7106 /* tp->lock is held. */
7107 static void tg3_stop_fw(struct tg3
*tp
)
7109 if ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) &&
7110 !(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)) {
7111 /* Wait for RX cpu to ACK the previous event. */
7112 tg3_wait_for_event_ack(tp
);
7114 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_MBOX
, FWCMD_NICDRV_PAUSE_FW
);
7116 tg3_generate_fw_event(tp
);
7118 /* Wait for RX cpu to ACK this event. */
7119 tg3_wait_for_event_ack(tp
);
7123 /* tp->lock is held. */
7124 static int tg3_halt(struct tg3
*tp
, int kind
, int silent
)
7130 tg3_write_sig_pre_reset(tp
, kind
);
7132 tg3_abort_hw(tp
, silent
);
7133 err
= tg3_chip_reset(tp
);
7135 __tg3_set_mac_addr(tp
, 0);
7137 tg3_write_sig_legacy(tp
, kind
);
7138 tg3_write_sig_post_reset(tp
, kind
);
7146 #define RX_CPU_SCRATCH_BASE 0x30000
7147 #define RX_CPU_SCRATCH_SIZE 0x04000
7148 #define TX_CPU_SCRATCH_BASE 0x34000
7149 #define TX_CPU_SCRATCH_SIZE 0x04000
7151 /* tp->lock is held. */
7152 static int tg3_halt_cpu(struct tg3
*tp
, u32 offset
)
7156 BUG_ON(offset
== TX_CPU_BASE
&&
7157 (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
));
7159 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
7160 u32 val
= tr32(GRC_VCPU_EXT_CTRL
);
7162 tw32(GRC_VCPU_EXT_CTRL
, val
| GRC_VCPU_EXT_CTRL_HALT_CPU
);
7165 if (offset
== RX_CPU_BASE
) {
7166 for (i
= 0; i
< 10000; i
++) {
7167 tw32(offset
+ CPU_STATE
, 0xffffffff);
7168 tw32(offset
+ CPU_MODE
, CPU_MODE_HALT
);
7169 if (tr32(offset
+ CPU_MODE
) & CPU_MODE_HALT
)
7173 tw32(offset
+ CPU_STATE
, 0xffffffff);
7174 tw32_f(offset
+ CPU_MODE
, CPU_MODE_HALT
);
7177 for (i
= 0; i
< 10000; i
++) {
7178 tw32(offset
+ CPU_STATE
, 0xffffffff);
7179 tw32(offset
+ CPU_MODE
, CPU_MODE_HALT
);
7180 if (tr32(offset
+ CPU_MODE
) & CPU_MODE_HALT
)
7186 netdev_err(tp
->dev
, "%s timed out, %s CPU\n",
7187 __func__
, offset
== RX_CPU_BASE
? "RX" : "TX");
7191 /* Clear firmware's nvram arbitration. */
7192 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
)
7193 tw32(NVRAM_SWARB
, SWARB_REQ_CLR0
);
7198 unsigned int fw_base
;
7199 unsigned int fw_len
;
7200 const __be32
*fw_data
;
7203 /* tp->lock is held. */
7204 static int tg3_load_firmware_cpu(struct tg3
*tp
, u32 cpu_base
, u32 cpu_scratch_base
,
7205 int cpu_scratch_size
, struct fw_info
*info
)
7207 int err
, lock_err
, i
;
7208 void (*write_op
)(struct tg3
*, u32
, u32
);
7210 if (cpu_base
== TX_CPU_BASE
&&
7211 (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
7213 "%s: Trying to load TX cpu firmware which is 5705\n",
7218 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
7219 write_op
= tg3_write_mem
;
7221 write_op
= tg3_write_indirect_reg32
;
7223 /* It is possible that bootcode is still loading at this point.
7224 * Get the nvram lock first before halting the cpu.
7226 lock_err
= tg3_nvram_lock(tp
);
7227 err
= tg3_halt_cpu(tp
, cpu_base
);
7229 tg3_nvram_unlock(tp
);
7233 for (i
= 0; i
< cpu_scratch_size
; i
+= sizeof(u32
))
7234 write_op(tp
, cpu_scratch_base
+ i
, 0);
7235 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
7236 tw32(cpu_base
+ CPU_MODE
, tr32(cpu_base
+CPU_MODE
)|CPU_MODE_HALT
);
7237 for (i
= 0; i
< (info
->fw_len
/ sizeof(u32
)); i
++)
7238 write_op(tp
, (cpu_scratch_base
+
7239 (info
->fw_base
& 0xffff) +
7241 be32_to_cpu(info
->fw_data
[i
]));
7249 /* tp->lock is held. */
7250 static int tg3_load_5701_a0_firmware_fix(struct tg3
*tp
)
7252 struct fw_info info
;
7253 const __be32
*fw_data
;
7256 fw_data
= (void *)tp
->fw
->data
;
7258 /* Firmware blob starts with version numbers, followed by
7259 start address and length. We are setting complete length.
7260 length = end_address_of_bss - start_address_of_text.
7261 Remainder is the blob to be loaded contiguously
7262 from start address. */
7264 info
.fw_base
= be32_to_cpu(fw_data
[1]);
7265 info
.fw_len
= tp
->fw
->size
- 12;
7266 info
.fw_data
= &fw_data
[3];
7268 err
= tg3_load_firmware_cpu(tp
, RX_CPU_BASE
,
7269 RX_CPU_SCRATCH_BASE
, RX_CPU_SCRATCH_SIZE
,
7274 err
= tg3_load_firmware_cpu(tp
, TX_CPU_BASE
,
7275 TX_CPU_SCRATCH_BASE
, TX_CPU_SCRATCH_SIZE
,
7280 /* Now startup only the RX cpu. */
7281 tw32(RX_CPU_BASE
+ CPU_STATE
, 0xffffffff);
7282 tw32_f(RX_CPU_BASE
+ CPU_PC
, info
.fw_base
);
7284 for (i
= 0; i
< 5; i
++) {
7285 if (tr32(RX_CPU_BASE
+ CPU_PC
) == info
.fw_base
)
7287 tw32(RX_CPU_BASE
+ CPU_STATE
, 0xffffffff);
7288 tw32(RX_CPU_BASE
+ CPU_MODE
, CPU_MODE_HALT
);
7289 tw32_f(RX_CPU_BASE
+ CPU_PC
, info
.fw_base
);
7293 netdev_err(tp
->dev
, "%s fails to set RX CPU PC, is %08x "
7294 "should be %08x\n", __func__
,
7295 tr32(RX_CPU_BASE
+ CPU_PC
), info
.fw_base
);
7298 tw32(RX_CPU_BASE
+ CPU_STATE
, 0xffffffff);
7299 tw32_f(RX_CPU_BASE
+ CPU_MODE
, 0x00000000);
7304 /* 5705 needs a special version of the TSO firmware. */
7306 /* tp->lock is held. */
7307 static int tg3_load_tso_firmware(struct tg3
*tp
)
7309 struct fw_info info
;
7310 const __be32
*fw_data
;
7311 unsigned long cpu_base
, cpu_scratch_base
, cpu_scratch_size
;
7314 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
7317 fw_data
= (void *)tp
->fw
->data
;
7319 /* Firmware blob starts with version numbers, followed by
7320 start address and length. We are setting complete length.
7321 length = end_address_of_bss - start_address_of_text.
7322 Remainder is the blob to be loaded contiguously
7323 from start address. */
7325 info
.fw_base
= be32_to_cpu(fw_data
[1]);
7326 cpu_scratch_size
= tp
->fw_len
;
7327 info
.fw_len
= tp
->fw
->size
- 12;
7328 info
.fw_data
= &fw_data
[3];
7330 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
7331 cpu_base
= RX_CPU_BASE
;
7332 cpu_scratch_base
= NIC_SRAM_MBUF_POOL_BASE5705
;
7334 cpu_base
= TX_CPU_BASE
;
7335 cpu_scratch_base
= TX_CPU_SCRATCH_BASE
;
7336 cpu_scratch_size
= TX_CPU_SCRATCH_SIZE
;
7339 err
= tg3_load_firmware_cpu(tp
, cpu_base
,
7340 cpu_scratch_base
, cpu_scratch_size
,
7345 /* Now startup the cpu. */
7346 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
7347 tw32_f(cpu_base
+ CPU_PC
, info
.fw_base
);
7349 for (i
= 0; i
< 5; i
++) {
7350 if (tr32(cpu_base
+ CPU_PC
) == info
.fw_base
)
7352 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
7353 tw32(cpu_base
+ CPU_MODE
, CPU_MODE_HALT
);
7354 tw32_f(cpu_base
+ CPU_PC
, info
.fw_base
);
7359 "%s fails to set CPU PC, is %08x should be %08x\n",
7360 __func__
, tr32(cpu_base
+ CPU_PC
), info
.fw_base
);
7363 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
7364 tw32_f(cpu_base
+ CPU_MODE
, 0x00000000);
7369 static int tg3_set_mac_addr(struct net_device
*dev
, void *p
)
7371 struct tg3
*tp
= netdev_priv(dev
);
7372 struct sockaddr
*addr
= p
;
7373 int err
= 0, skip_mac_1
= 0;
7375 if (!is_valid_ether_addr(addr
->sa_data
))
7378 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
7380 if (!netif_running(dev
))
7383 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) {
7384 u32 addr0_high
, addr0_low
, addr1_high
, addr1_low
;
7386 addr0_high
= tr32(MAC_ADDR_0_HIGH
);
7387 addr0_low
= tr32(MAC_ADDR_0_LOW
);
7388 addr1_high
= tr32(MAC_ADDR_1_HIGH
);
7389 addr1_low
= tr32(MAC_ADDR_1_LOW
);
7391 /* Skip MAC addr 1 if ASF is using it. */
7392 if ((addr0_high
!= addr1_high
|| addr0_low
!= addr1_low
) &&
7393 !(addr1_high
== 0 && addr1_low
== 0))
7396 spin_lock_bh(&tp
->lock
);
7397 __tg3_set_mac_addr(tp
, skip_mac_1
);
7398 spin_unlock_bh(&tp
->lock
);
7403 /* tp->lock is held. */
7404 static void tg3_set_bdinfo(struct tg3
*tp
, u32 bdinfo_addr
,
7405 dma_addr_t mapping
, u32 maxlen_flags
,
7409 (bdinfo_addr
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_HIGH
),
7410 ((u64
) mapping
>> 32));
7412 (bdinfo_addr
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_LOW
),
7413 ((u64
) mapping
& 0xffffffff));
7415 (bdinfo_addr
+ TG3_BDINFO_MAXLEN_FLAGS
),
7418 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
7420 (bdinfo_addr
+ TG3_BDINFO_NIC_ADDR
),
7424 static void __tg3_set_rx_mode(struct net_device
*);
7425 static void __tg3_set_coalesce(struct tg3
*tp
, struct ethtool_coalesce
*ec
)
7429 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)) {
7430 tw32(HOSTCC_TXCOL_TICKS
, ec
->tx_coalesce_usecs
);
7431 tw32(HOSTCC_TXMAX_FRAMES
, ec
->tx_max_coalesced_frames
);
7432 tw32(HOSTCC_TXCOAL_MAXF_INT
, ec
->tx_max_coalesced_frames_irq
);
7434 tw32(HOSTCC_TXCOL_TICKS
, 0);
7435 tw32(HOSTCC_TXMAX_FRAMES
, 0);
7436 tw32(HOSTCC_TXCOAL_MAXF_INT
, 0);
7439 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_RSS
)) {
7440 tw32(HOSTCC_RXCOL_TICKS
, ec
->rx_coalesce_usecs
);
7441 tw32(HOSTCC_RXMAX_FRAMES
, ec
->rx_max_coalesced_frames
);
7442 tw32(HOSTCC_RXCOAL_MAXF_INT
, ec
->rx_max_coalesced_frames_irq
);
7444 tw32(HOSTCC_RXCOL_TICKS
, 0);
7445 tw32(HOSTCC_RXMAX_FRAMES
, 0);
7446 tw32(HOSTCC_RXCOAL_MAXF_INT
, 0);
7449 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
7450 u32 val
= ec
->stats_block_coalesce_usecs
;
7452 tw32(HOSTCC_RXCOAL_TICK_INT
, ec
->rx_coalesce_usecs_irq
);
7453 tw32(HOSTCC_TXCOAL_TICK_INT
, ec
->tx_coalesce_usecs_irq
);
7455 if (!netif_carrier_ok(tp
->dev
))
7458 tw32(HOSTCC_STAT_COAL_TICKS
, val
);
7461 for (i
= 0; i
< tp
->irq_cnt
- 1; i
++) {
7464 reg
= HOSTCC_RXCOL_TICKS_VEC1
+ i
* 0x18;
7465 tw32(reg
, ec
->rx_coalesce_usecs
);
7466 reg
= HOSTCC_RXMAX_FRAMES_VEC1
+ i
* 0x18;
7467 tw32(reg
, ec
->rx_max_coalesced_frames
);
7468 reg
= HOSTCC_RXCOAL_MAXF_INT_VEC1
+ i
* 0x18;
7469 tw32(reg
, ec
->rx_max_coalesced_frames_irq
);
7471 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
) {
7472 reg
= HOSTCC_TXCOL_TICKS_VEC1
+ i
* 0x18;
7473 tw32(reg
, ec
->tx_coalesce_usecs
);
7474 reg
= HOSTCC_TXMAX_FRAMES_VEC1
+ i
* 0x18;
7475 tw32(reg
, ec
->tx_max_coalesced_frames
);
7476 reg
= HOSTCC_TXCOAL_MAXF_INT_VEC1
+ i
* 0x18;
7477 tw32(reg
, ec
->tx_max_coalesced_frames_irq
);
7481 for (; i
< tp
->irq_max
- 1; i
++) {
7482 tw32(HOSTCC_RXCOL_TICKS_VEC1
+ i
* 0x18, 0);
7483 tw32(HOSTCC_RXMAX_FRAMES_VEC1
+ i
* 0x18, 0);
7484 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1
+ i
* 0x18, 0);
7486 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
) {
7487 tw32(HOSTCC_TXCOL_TICKS_VEC1
+ i
* 0x18, 0);
7488 tw32(HOSTCC_TXMAX_FRAMES_VEC1
+ i
* 0x18, 0);
7489 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1
+ i
* 0x18, 0);
7494 /* tp->lock is held. */
7495 static void tg3_rings_reset(struct tg3
*tp
)
7498 u32 stblk
, txrcb
, rxrcb
, limit
;
7499 struct tg3_napi
*tnapi
= &tp
->napi
[0];
7501 /* Disable all transmit rings but the first. */
7502 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
7503 limit
= NIC_SRAM_SEND_RCB
+ TG3_BDINFO_SIZE
* 16;
7504 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
7505 limit
= NIC_SRAM_SEND_RCB
+ TG3_BDINFO_SIZE
* 2;
7507 limit
= NIC_SRAM_SEND_RCB
+ TG3_BDINFO_SIZE
;
7509 for (txrcb
= NIC_SRAM_SEND_RCB
+ TG3_BDINFO_SIZE
;
7510 txrcb
< limit
; txrcb
+= TG3_BDINFO_SIZE
)
7511 tg3_write_mem(tp
, txrcb
+ TG3_BDINFO_MAXLEN_FLAGS
,
7512 BDINFO_FLAGS_DISABLED
);
7515 /* Disable all receive return rings but the first. */
7516 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
7517 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
)
7518 limit
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
* 17;
7519 else if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
7520 limit
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
* 16;
7521 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
||
7522 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
7523 limit
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
* 4;
7525 limit
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
;
7527 for (rxrcb
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
;
7528 rxrcb
< limit
; rxrcb
+= TG3_BDINFO_SIZE
)
7529 tg3_write_mem(tp
, rxrcb
+ TG3_BDINFO_MAXLEN_FLAGS
,
7530 BDINFO_FLAGS_DISABLED
);
7532 /* Disable interrupts */
7533 tw32_mailbox_f(tp
->napi
[0].int_mbox
, 1);
7535 /* Zero mailbox registers. */
7536 if (tp
->tg3_flags
& TG3_FLAG_SUPPORT_MSIX
) {
7537 for (i
= 1; i
< TG3_IRQ_MAX_VECS
; i
++) {
7538 tp
->napi
[i
].tx_prod
= 0;
7539 tp
->napi
[i
].tx_cons
= 0;
7540 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)
7541 tw32_mailbox(tp
->napi
[i
].prodmbox
, 0);
7542 tw32_rx_mbox(tp
->napi
[i
].consmbox
, 0);
7543 tw32_mailbox_f(tp
->napi
[i
].int_mbox
, 1);
7545 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
))
7546 tw32_mailbox(tp
->napi
[0].prodmbox
, 0);
7548 tp
->napi
[0].tx_prod
= 0;
7549 tp
->napi
[0].tx_cons
= 0;
7550 tw32_mailbox(tp
->napi
[0].prodmbox
, 0);
7551 tw32_rx_mbox(tp
->napi
[0].consmbox
, 0);
7554 /* Make sure the NIC-based send BD rings are disabled. */
7555 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
7556 u32 mbox
= MAILBOX_SNDNIC_PROD_IDX_0
+ TG3_64BIT_REG_LOW
;
7557 for (i
= 0; i
< 16; i
++)
7558 tw32_tx_mbox(mbox
+ i
* 8, 0);
7561 txrcb
= NIC_SRAM_SEND_RCB
;
7562 rxrcb
= NIC_SRAM_RCV_RET_RCB
;
7564 /* Clear status block in ram. */
7565 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
7567 /* Set status block DMA address */
7568 tw32(HOSTCC_STATUS_BLK_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
7569 ((u64
) tnapi
->status_mapping
>> 32));
7570 tw32(HOSTCC_STATUS_BLK_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
7571 ((u64
) tnapi
->status_mapping
& 0xffffffff));
7573 if (tnapi
->tx_ring
) {
7574 tg3_set_bdinfo(tp
, txrcb
, tnapi
->tx_desc_mapping
,
7575 (TG3_TX_RING_SIZE
<<
7576 BDINFO_FLAGS_MAXLEN_SHIFT
),
7577 NIC_SRAM_TX_BUFFER_DESC
);
7578 txrcb
+= TG3_BDINFO_SIZE
;
7581 if (tnapi
->rx_rcb
) {
7582 tg3_set_bdinfo(tp
, rxrcb
, tnapi
->rx_rcb_mapping
,
7583 (TG3_RX_RCB_RING_SIZE(tp
) <<
7584 BDINFO_FLAGS_MAXLEN_SHIFT
), 0);
7585 rxrcb
+= TG3_BDINFO_SIZE
;
7588 stblk
= HOSTCC_STATBLCK_RING1
;
7590 for (i
= 1, tnapi
++; i
< tp
->irq_cnt
; i
++, tnapi
++) {
7591 u64 mapping
= (u64
)tnapi
->status_mapping
;
7592 tw32(stblk
+ TG3_64BIT_REG_HIGH
, mapping
>> 32);
7593 tw32(stblk
+ TG3_64BIT_REG_LOW
, mapping
& 0xffffffff);
7595 /* Clear status block in ram. */
7596 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
7598 if (tnapi
->tx_ring
) {
7599 tg3_set_bdinfo(tp
, txrcb
, tnapi
->tx_desc_mapping
,
7600 (TG3_TX_RING_SIZE
<<
7601 BDINFO_FLAGS_MAXLEN_SHIFT
),
7602 NIC_SRAM_TX_BUFFER_DESC
);
7603 txrcb
+= TG3_BDINFO_SIZE
;
7606 tg3_set_bdinfo(tp
, rxrcb
, tnapi
->rx_rcb_mapping
,
7607 (TG3_RX_RCB_RING_SIZE(tp
) <<
7608 BDINFO_FLAGS_MAXLEN_SHIFT
), 0);
7611 rxrcb
+= TG3_BDINFO_SIZE
;
7615 /* tp->lock is held. */
7616 static int tg3_reset_hw(struct tg3
*tp
, int reset_phy
)
7618 u32 val
, rdmac_mode
;
7620 struct tg3_rx_prodring_set
*tpr
= &tp
->prodring
[0];
7622 tg3_disable_ints(tp
);
7626 tg3_write_sig_pre_reset(tp
, RESET_KIND_INIT
);
7628 if (tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
)
7629 tg3_abort_hw(tp
, 1);
7634 err
= tg3_chip_reset(tp
);
7638 tg3_write_sig_legacy(tp
, RESET_KIND_INIT
);
7640 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
) {
7641 val
= tr32(TG3_CPMU_CTRL
);
7642 val
&= ~(CPMU_CTRL_LINK_AWARE_MODE
| CPMU_CTRL_LINK_IDLE_MODE
);
7643 tw32(TG3_CPMU_CTRL
, val
);
7645 val
= tr32(TG3_CPMU_LSPD_10MB_CLK
);
7646 val
&= ~CPMU_LSPD_10MB_MACCLK_MASK
;
7647 val
|= CPMU_LSPD_10MB_MACCLK_6_25
;
7648 tw32(TG3_CPMU_LSPD_10MB_CLK
, val
);
7650 val
= tr32(TG3_CPMU_LNK_AWARE_PWRMD
);
7651 val
&= ~CPMU_LNK_AWARE_MACCLK_MASK
;
7652 val
|= CPMU_LNK_AWARE_MACCLK_6_25
;
7653 tw32(TG3_CPMU_LNK_AWARE_PWRMD
, val
);
7655 val
= tr32(TG3_CPMU_HST_ACC
);
7656 val
&= ~CPMU_HST_ACC_MACCLK_MASK
;
7657 val
|= CPMU_HST_ACC_MACCLK_6_25
;
7658 tw32(TG3_CPMU_HST_ACC
, val
);
7661 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
) {
7662 val
= tr32(PCIE_PWR_MGMT_THRESH
) & ~PCIE_PWR_MGMT_L1_THRESH_MSK
;
7663 val
|= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN
|
7664 PCIE_PWR_MGMT_L1_THRESH_4MS
;
7665 tw32(PCIE_PWR_MGMT_THRESH
, val
);
7667 val
= tr32(TG3_PCIE_EIDLE_DELAY
) & ~TG3_PCIE_EIDLE_DELAY_MASK
;
7668 tw32(TG3_PCIE_EIDLE_DELAY
, val
| TG3_PCIE_EIDLE_DELAY_13_CLKS
);
7670 tw32(TG3_CORR_ERR_STAT
, TG3_CORR_ERR_STAT_CLEAR
);
7672 val
= tr32(TG3_PCIE_LNKCTL
) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN
;
7673 tw32(TG3_PCIE_LNKCTL
, val
| TG3_PCIE_LNKCTL_L1_PLL_PD_DIS
);
7676 if (tp
->tg3_flags3
& TG3_FLG3_L1PLLPD_EN
) {
7677 u32 grc_mode
= tr32(GRC_MODE
);
7679 /* Access the lower 1K of PL PCIE block registers. */
7680 val
= grc_mode
& ~GRC_MODE_PCIE_PORT_MASK
;
7681 tw32(GRC_MODE
, val
| GRC_MODE_PCIE_PL_SEL
);
7683 val
= tr32(TG3_PCIE_TLDLPL_PORT
+ TG3_PCIE_PL_LO_PHYCTL1
);
7684 tw32(TG3_PCIE_TLDLPL_PORT
+ TG3_PCIE_PL_LO_PHYCTL1
,
7685 val
| TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN
);
7687 tw32(GRC_MODE
, grc_mode
);
7690 if (tp
->pci_chip_rev_id
== CHIPREV_ID_57765_A0
) {
7691 u32 grc_mode
= tr32(GRC_MODE
);
7693 /* Access the lower 1K of PL PCIE block registers. */
7694 val
= grc_mode
& ~GRC_MODE_PCIE_PORT_MASK
;
7695 tw32(GRC_MODE
, val
| GRC_MODE_PCIE_PL_SEL
);
7697 val
= tr32(TG3_PCIE_TLDLPL_PORT
+ TG3_PCIE_PL_LO_PHYCTL5
);
7698 tw32(TG3_PCIE_TLDLPL_PORT
+ TG3_PCIE_PL_LO_PHYCTL5
,
7699 val
| TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ
);
7701 tw32(GRC_MODE
, grc_mode
);
7703 val
= tr32(TG3_CPMU_LSPD_10MB_CLK
);
7704 val
&= ~CPMU_LSPD_10MB_MACCLK_MASK
;
7705 val
|= CPMU_LSPD_10MB_MACCLK_6_25
;
7706 tw32(TG3_CPMU_LSPD_10MB_CLK
, val
);
7709 /* This works around an issue with Athlon chipsets on
7710 * B3 tigon3 silicon. This bit has no effect on any
7711 * other revision. But do not set this on PCI Express
7712 * chips and don't even touch the clocks if the CPMU is present.
7714 if (!(tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
)) {
7715 if (!(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
))
7716 tp
->pci_clock_ctrl
|= CLOCK_CTRL_DELAY_PCI_GRANT
;
7717 tw32_f(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
);
7720 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
&&
7721 (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
)) {
7722 val
= tr32(TG3PCI_PCISTATE
);
7723 val
|= PCISTATE_RETRY_SAME_DMA
;
7724 tw32(TG3PCI_PCISTATE
, val
);
7727 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
7728 /* Allow reads and writes to the
7729 * APE register and memory space.
7731 val
= tr32(TG3PCI_PCISTATE
);
7732 val
|= PCISTATE_ALLOW_APE_CTLSPC_WR
|
7733 PCISTATE_ALLOW_APE_SHMEM_WR
|
7734 PCISTATE_ALLOW_APE_PSPACE_WR
;
7735 tw32(TG3PCI_PCISTATE
, val
);
7738 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5704_BX
) {
7739 /* Enable some hw fixes. */
7740 val
= tr32(TG3PCI_MSI_DATA
);
7741 val
|= (1 << 26) | (1 << 28) | (1 << 29);
7742 tw32(TG3PCI_MSI_DATA
, val
);
7745 /* Descriptor ring init may make accesses to the
7746 * NIC SRAM area to setup the TX descriptors, so we
7747 * can only do this after the hardware has been
7748 * successfully reset.
7750 err
= tg3_init_rings(tp
);
7754 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
7755 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
||
7756 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
) {
7757 val
= tr32(TG3PCI_DMA_RW_CTRL
) &
7758 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT
;
7759 if (tp
->pci_chip_rev_id
== CHIPREV_ID_57765_A0
)
7760 val
&= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK
;
7761 tw32(TG3PCI_DMA_RW_CTRL
, val
| tp
->dma_rwctrl
);
7762 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5784
&&
7763 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5761
) {
7764 /* This value is determined during the probe time DMA
7765 * engine test, tg3_test_dma.
7767 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
7770 tp
->grc_mode
&= ~(GRC_MODE_HOST_SENDBDS
|
7771 GRC_MODE_4X_NIC_SEND_RINGS
|
7772 GRC_MODE_NO_TX_PHDR_CSUM
|
7773 GRC_MODE_NO_RX_PHDR_CSUM
);
7774 tp
->grc_mode
|= GRC_MODE_HOST_SENDBDS
;
7776 /* Pseudo-header checksum is done by hardware logic and not
7777 * the offload processers, so make the chip do the pseudo-
7778 * header checksums on receive. For transmit it is more
7779 * convenient to do the pseudo-header checksum in software
7780 * as Linux does that on transmit for us in all cases.
7782 tp
->grc_mode
|= GRC_MODE_NO_TX_PHDR_CSUM
;
7786 (GRC_MODE_IRQ_ON_MAC_ATTN
| GRC_MODE_HOST_STACKUP
));
7788 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7789 val
= tr32(GRC_MISC_CFG
);
7791 val
|= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT
);
7792 tw32(GRC_MISC_CFG
, val
);
7794 /* Initialize MBUF/DESC pool. */
7795 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) {
7797 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5705
) {
7798 tw32(BUFMGR_MB_POOL_ADDR
, NIC_SRAM_MBUF_POOL_BASE
);
7799 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
)
7800 tw32(BUFMGR_MB_POOL_SIZE
, NIC_SRAM_MBUF_POOL_SIZE64
);
7802 tw32(BUFMGR_MB_POOL_SIZE
, NIC_SRAM_MBUF_POOL_SIZE96
);
7803 tw32(BUFMGR_DMA_DESC_POOL_ADDR
, NIC_SRAM_DMA_DESC_POOL_BASE
);
7804 tw32(BUFMGR_DMA_DESC_POOL_SIZE
, NIC_SRAM_DMA_DESC_POOL_SIZE
);
7805 } else if (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) {
7808 fw_len
= tp
->fw_len
;
7809 fw_len
= (fw_len
+ (0x80 - 1)) & ~(0x80 - 1);
7810 tw32(BUFMGR_MB_POOL_ADDR
,
7811 NIC_SRAM_MBUF_POOL_BASE5705
+ fw_len
);
7812 tw32(BUFMGR_MB_POOL_SIZE
,
7813 NIC_SRAM_MBUF_POOL_SIZE5705
- fw_len
- 0xa00);
7816 if (tp
->dev
->mtu
<= ETH_DATA_LEN
) {
7817 tw32(BUFMGR_MB_RDMA_LOW_WATER
,
7818 tp
->bufmgr_config
.mbuf_read_dma_low_water
);
7819 tw32(BUFMGR_MB_MACRX_LOW_WATER
,
7820 tp
->bufmgr_config
.mbuf_mac_rx_low_water
);
7821 tw32(BUFMGR_MB_HIGH_WATER
,
7822 tp
->bufmgr_config
.mbuf_high_water
);
7824 tw32(BUFMGR_MB_RDMA_LOW_WATER
,
7825 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
);
7826 tw32(BUFMGR_MB_MACRX_LOW_WATER
,
7827 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
);
7828 tw32(BUFMGR_MB_HIGH_WATER
,
7829 tp
->bufmgr_config
.mbuf_high_water_jumbo
);
7831 tw32(BUFMGR_DMA_LOW_WATER
,
7832 tp
->bufmgr_config
.dma_low_water
);
7833 tw32(BUFMGR_DMA_HIGH_WATER
,
7834 tp
->bufmgr_config
.dma_high_water
);
7836 tw32(BUFMGR_MODE
, BUFMGR_MODE_ENABLE
| BUFMGR_MODE_ATTN_ENABLE
);
7837 for (i
= 0; i
< 2000; i
++) {
7838 if (tr32(BUFMGR_MODE
) & BUFMGR_MODE_ENABLE
)
7843 netdev_err(tp
->dev
, "%s cannot enable BUFMGR\n", __func__
);
7847 /* Setup replenish threshold. */
7848 val
= tp
->rx_pending
/ 8;
7851 else if (val
> tp
->rx_std_max_post
)
7852 val
= tp
->rx_std_max_post
;
7853 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
7854 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5906_A1
)
7855 tw32(ISO_PKT_TX
, (tr32(ISO_PKT_TX
) & ~0x3) | 0x2);
7857 if (val
> (TG3_RX_INTERNAL_RING_SZ_5906
/ 2))
7858 val
= TG3_RX_INTERNAL_RING_SZ_5906
/ 2;
7861 tw32(RCVBDI_STD_THRESH
, val
);
7863 /* Initialize TG3_BDINFO's at:
7864 * RCVDBDI_STD_BD: standard eth size rx ring
7865 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7866 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7869 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7870 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7871 * ring attribute flags
7872 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7874 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7875 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7877 * The size of each ring is fixed in the firmware, but the location is
7880 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
7881 ((u64
) tpr
->rx_std_mapping
>> 32));
7882 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
7883 ((u64
) tpr
->rx_std_mapping
& 0xffffffff));
7884 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5717
&&
7885 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5719
)
7886 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_NIC_ADDR
,
7887 NIC_SRAM_RX_BUFFER_DESC
);
7889 /* Disable the mini ring */
7890 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
7891 tw32(RCVDBDI_MINI_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
7892 BDINFO_FLAGS_DISABLED
);
7894 /* Program the jumbo buffer descriptor ring control
7895 * blocks on those devices that have them.
7897 if ((tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) &&
7898 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
7899 /* Setup replenish threshold. */
7900 tw32(RCVBDI_JUMBO_THRESH
, tp
->rx_jumbo_pending
/ 8);
7902 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
) {
7903 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
7904 ((u64
) tpr
->rx_jmb_mapping
>> 32));
7905 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
7906 ((u64
) tpr
->rx_jmb_mapping
& 0xffffffff));
7907 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
7908 (RX_JUMBO_MAX_SIZE
<< BDINFO_FLAGS_MAXLEN_SHIFT
) |
7909 BDINFO_FLAGS_USE_EXT_RECV
);
7910 if (!(tp
->tg3_flags3
& TG3_FLG3_USE_JUMBO_BDFLAG
) ||
7911 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
7912 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_NIC_ADDR
,
7913 NIC_SRAM_RX_JUMBO_BUFFER_DESC
);
7915 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
7916 BDINFO_FLAGS_DISABLED
);
7919 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
7920 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
||
7921 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
7922 val
= (RX_STD_MAX_SIZE_5705
<< BDINFO_FLAGS_MAXLEN_SHIFT
) |
7923 (TG3_RX_STD_DMA_SZ
<< 2);
7925 val
= TG3_RX_STD_DMA_SZ
<< BDINFO_FLAGS_MAXLEN_SHIFT
;
7927 val
= RX_STD_MAX_SIZE_5705
<< BDINFO_FLAGS_MAXLEN_SHIFT
;
7929 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_MAXLEN_FLAGS
, val
);
7931 tpr
->rx_std_prod_idx
= tp
->rx_pending
;
7932 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG
, tpr
->rx_std_prod_idx
);
7934 tpr
->rx_jmb_prod_idx
= (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
) ?
7935 tp
->rx_jumbo_pending
: 0;
7936 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG
, tpr
->rx_jmb_prod_idx
);
7938 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
7939 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
||
7940 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
) {
7941 tw32(STD_REPLENISH_LWM
, 32);
7942 tw32(JMB_REPLENISH_LWM
, 16);
7945 tg3_rings_reset(tp
);
7947 /* Initialize MAC address and backoff seed. */
7948 __tg3_set_mac_addr(tp
, 0);
7950 /* MTU + ethernet header + FCS + optional VLAN tag */
7951 tw32(MAC_RX_MTU_SIZE
,
7952 tp
->dev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
+ VLAN_HLEN
);
7954 /* The slot time is changed by tg3_setup_phy if we
7955 * run at gigabit with half duplex.
7957 tw32(MAC_TX_LENGTHS
,
7958 (2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
7959 (6 << TX_LENGTHS_IPG_SHIFT
) |
7960 (32 << TX_LENGTHS_SLOT_TIME_SHIFT
));
7962 /* Receive rules. */
7963 tw32(MAC_RCV_RULE_CFG
, RCV_RULE_CFG_DEFAULT_CLASS
);
7964 tw32(RCVLPC_CONFIG
, 0x0181);
7966 /* Calculate RDMAC_MODE setting early, we need it to determine
7967 * the RCVLPC_STATE_ENABLE mask.
7969 rdmac_mode
= (RDMAC_MODE_ENABLE
| RDMAC_MODE_TGTABORT_ENAB
|
7970 RDMAC_MODE_MSTABORT_ENAB
| RDMAC_MODE_PARITYERR_ENAB
|
7971 RDMAC_MODE_ADDROFLOW_ENAB
| RDMAC_MODE_FIFOOFLOW_ENAB
|
7972 RDMAC_MODE_FIFOURUN_ENAB
| RDMAC_MODE_FIFOOREAD_ENAB
|
7973 RDMAC_MODE_LNGREAD_ENAB
);
7975 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
7976 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
)
7977 rdmac_mode
|= RDMAC_MODE_MULT_DMA_RD_DIS
;
7979 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
7980 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
7981 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
7982 rdmac_mode
|= RDMAC_MODE_BD_SBD_CRPT_ENAB
|
7983 RDMAC_MODE_MBUF_RBD_CRPT_ENAB
|
7984 RDMAC_MODE_MBUF_SBD_CRPT_ENAB
;
7986 /* If statement applies to 5705 and 5750 PCI devices only */
7987 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
7988 tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A0
) ||
7989 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
)) {
7990 if (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
&&
7991 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
7992 rdmac_mode
|= RDMAC_MODE_FIFO_SIZE_128
;
7993 } else if (!(tr32(TG3PCI_PCISTATE
) & PCISTATE_BUS_SPEED_HIGH
) &&
7994 !(tp
->tg3_flags2
& TG3_FLG2_IS_5788
)) {
7995 rdmac_mode
|= RDMAC_MODE_FIFO_LONG_BURST
;
7999 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)
8000 rdmac_mode
|= RDMAC_MODE_FIFO_LONG_BURST
;
8002 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
8003 rdmac_mode
|= RDMAC_MODE_IPV4_LSO_EN
;
8005 if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO_3
) ||
8006 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
8007 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
8008 rdmac_mode
|= RDMAC_MODE_IPV6_LSO_EN
;
8010 /* Receive/send statistics. */
8011 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) {
8012 val
= tr32(RCVLPC_STATS_ENABLE
);
8013 val
&= ~RCVLPC_STATSENAB_DACK_FIX
;
8014 tw32(RCVLPC_STATS_ENABLE
, val
);
8015 } else if ((rdmac_mode
& RDMAC_MODE_FIFO_SIZE_128
) &&
8016 (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
)) {
8017 val
= tr32(RCVLPC_STATS_ENABLE
);
8018 val
&= ~RCVLPC_STATSENAB_LNGBRST_RFIX
;
8019 tw32(RCVLPC_STATS_ENABLE
, val
);
8021 tw32(RCVLPC_STATS_ENABLE
, 0xffffff);
8023 tw32(RCVLPC_STATSCTRL
, RCVLPC_STATSCTRL_ENABLE
);
8024 tw32(SNDDATAI_STATSENAB
, 0xffffff);
8025 tw32(SNDDATAI_STATSCTRL
,
8026 (SNDDATAI_SCTRL_ENABLE
|
8027 SNDDATAI_SCTRL_FASTUPD
));
8029 /* Setup host coalescing engine. */
8030 tw32(HOSTCC_MODE
, 0);
8031 for (i
= 0; i
< 2000; i
++) {
8032 if (!(tr32(HOSTCC_MODE
) & HOSTCC_MODE_ENABLE
))
8037 __tg3_set_coalesce(tp
, &tp
->coal
);
8039 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
8040 /* Status/statistics block address. See tg3_timer,
8041 * the tg3_periodic_fetch_stats call there, and
8042 * tg3_get_stats to see how this works for 5705/5750 chips.
8044 tw32(HOSTCC_STATS_BLK_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
8045 ((u64
) tp
->stats_mapping
>> 32));
8046 tw32(HOSTCC_STATS_BLK_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
8047 ((u64
) tp
->stats_mapping
& 0xffffffff));
8048 tw32(HOSTCC_STATS_BLK_NIC_ADDR
, NIC_SRAM_STATS_BLK
);
8050 tw32(HOSTCC_STATUS_BLK_NIC_ADDR
, NIC_SRAM_STATUS_BLK
);
8052 /* Clear statistics and status block memory areas */
8053 for (i
= NIC_SRAM_STATS_BLK
;
8054 i
< NIC_SRAM_STATUS_BLK
+ TG3_HW_STATUS_SIZE
;
8056 tg3_write_mem(tp
, i
, 0);
8061 tw32(HOSTCC_MODE
, HOSTCC_MODE_ENABLE
| tp
->coalesce_mode
);
8063 tw32(RCVCC_MODE
, RCVCC_MODE_ENABLE
| RCVCC_MODE_ATTN_ENABLE
);
8064 tw32(RCVLPC_MODE
, RCVLPC_MODE_ENABLE
);
8065 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
8066 tw32(RCVLSC_MODE
, RCVLSC_MODE_ENABLE
| RCVLSC_MODE_ATTN_ENABLE
);
8068 if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
) {
8069 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
8070 /* reset to prevent losing 1st rx packet intermittently */
8071 tw32_f(MAC_RX_MODE
, RX_MODE_RESET
);
8075 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
8076 tp
->mac_mode
&= MAC_MODE_APE_TX_EN
| MAC_MODE_APE_RX_EN
;
8079 tp
->mac_mode
|= MAC_MODE_TXSTAT_ENABLE
| MAC_MODE_RXSTAT_ENABLE
|
8080 MAC_MODE_TDE_ENABLE
| MAC_MODE_RDE_ENABLE
| MAC_MODE_FHDE_ENABLE
;
8081 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
8082 !(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) &&
8083 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
)
8084 tp
->mac_mode
|= MAC_MODE_LINK_POLARITY
;
8085 tw32_f(MAC_MODE
, tp
->mac_mode
| MAC_MODE_RXSTAT_CLEAR
| MAC_MODE_TXSTAT_CLEAR
);
8088 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8089 * If TG3_FLG2_IS_NIC is zero, we should read the
8090 * register to preserve the GPIO settings for LOMs. The GPIOs,
8091 * whether used as inputs or outputs, are set by boot code after
8094 if (!(tp
->tg3_flags2
& TG3_FLG2_IS_NIC
)) {
8097 gpio_mask
= GRC_LCLCTRL_GPIO_OE0
| GRC_LCLCTRL_GPIO_OE1
|
8098 GRC_LCLCTRL_GPIO_OE2
| GRC_LCLCTRL_GPIO_OUTPUT0
|
8099 GRC_LCLCTRL_GPIO_OUTPUT1
| GRC_LCLCTRL_GPIO_OUTPUT2
;
8101 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
)
8102 gpio_mask
|= GRC_LCLCTRL_GPIO_OE3
|
8103 GRC_LCLCTRL_GPIO_OUTPUT3
;
8105 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
)
8106 gpio_mask
|= GRC_LCLCTRL_GPIO_UART_SEL
;
8108 tp
->grc_local_ctrl
&= ~gpio_mask
;
8109 tp
->grc_local_ctrl
|= tr32(GRC_LOCAL_CTRL
) & gpio_mask
;
8111 /* GPIO1 must be driven high for eeprom write protect */
8112 if (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
)
8113 tp
->grc_local_ctrl
|= (GRC_LCLCTRL_GPIO_OE1
|
8114 GRC_LCLCTRL_GPIO_OUTPUT1
);
8116 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
);
8119 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSIX
) {
8120 val
= tr32(MSGINT_MODE
);
8121 val
|= MSGINT_MODE_MULTIVEC_EN
| MSGINT_MODE_ENABLE
;
8122 tw32(MSGINT_MODE
, val
);
8125 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
8126 tw32_f(DMAC_MODE
, DMAC_MODE_ENABLE
);
8130 val
= (WDMAC_MODE_ENABLE
| WDMAC_MODE_TGTABORT_ENAB
|
8131 WDMAC_MODE_MSTABORT_ENAB
| WDMAC_MODE_PARITYERR_ENAB
|
8132 WDMAC_MODE_ADDROFLOW_ENAB
| WDMAC_MODE_FIFOOFLOW_ENAB
|
8133 WDMAC_MODE_FIFOURUN_ENAB
| WDMAC_MODE_FIFOOREAD_ENAB
|
8134 WDMAC_MODE_LNGREAD_ENAB
);
8136 /* If statement applies to 5705 and 5750 PCI devices only */
8137 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
8138 tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A0
) ||
8139 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
) {
8140 if ((tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) &&
8141 (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A1
||
8142 tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A2
)) {
8144 } else if (!(tr32(TG3PCI_PCISTATE
) & PCISTATE_BUS_SPEED_HIGH
) &&
8145 !(tp
->tg3_flags2
& TG3_FLG2_IS_5788
) &&
8146 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)) {
8147 val
|= WDMAC_MODE_RX_ACCEL
;
8151 /* Enable host coalescing bug fix */
8152 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
8153 val
|= WDMAC_MODE_STATUS_TAG_FIX
;
8155 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
8156 val
|= WDMAC_MODE_BURST_ALL_DATA
;
8158 tw32_f(WDMAC_MODE
, val
);
8161 if (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) {
8164 pci_read_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
8166 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
) {
8167 pcix_cmd
&= ~PCI_X_CMD_MAX_READ
;
8168 pcix_cmd
|= PCI_X_CMD_READ_2K
;
8169 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
8170 pcix_cmd
&= ~(PCI_X_CMD_MAX_SPLIT
| PCI_X_CMD_MAX_READ
);
8171 pcix_cmd
|= PCI_X_CMD_READ_2K
;
8173 pci_write_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
8177 tw32_f(RDMAC_MODE
, rdmac_mode
);
8180 tw32(RCVDCC_MODE
, RCVDCC_MODE_ENABLE
| RCVDCC_MODE_ATTN_ENABLE
);
8181 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
8182 tw32(MBFREE_MODE
, MBFREE_MODE_ENABLE
);
8184 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
)
8186 SNDDATAC_MODE_ENABLE
| SNDDATAC_MODE_CDELAY
);
8188 tw32(SNDDATAC_MODE
, SNDDATAC_MODE_ENABLE
);
8190 tw32(SNDBDC_MODE
, SNDBDC_MODE_ENABLE
| SNDBDC_MODE_ATTN_ENABLE
);
8191 tw32(RCVBDI_MODE
, RCVBDI_MODE_ENABLE
| RCVBDI_MODE_RCB_ATTN_ENAB
);
8192 tw32(RCVDBDI_MODE
, RCVDBDI_MODE_ENABLE
| RCVDBDI_MODE_INV_RING_SZ
);
8193 tw32(SNDDATAI_MODE
, SNDDATAI_MODE_ENABLE
);
8194 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
8195 tw32(SNDDATAI_MODE
, SNDDATAI_MODE_ENABLE
| 0x8);
8196 val
= SNDBDI_MODE_ENABLE
| SNDBDI_MODE_ATTN_ENABLE
;
8197 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)
8198 val
|= SNDBDI_MODE_MULTI_TXQ_EN
;
8199 tw32(SNDBDI_MODE
, val
);
8200 tw32(SNDBDS_MODE
, SNDBDS_MODE_ENABLE
| SNDBDS_MODE_ATTN_ENABLE
);
8202 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
) {
8203 err
= tg3_load_5701_a0_firmware_fix(tp
);
8208 if (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) {
8209 err
= tg3_load_tso_firmware(tp
);
8214 tp
->tx_mode
= TX_MODE_ENABLE
;
8215 if ((tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) ||
8216 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
8217 tp
->tx_mode
|= TX_MODE_MBUF_LOCKUP_FIX
;
8218 tw32_f(MAC_TX_MODE
, tp
->tx_mode
);
8221 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_RSS
) {
8222 u32 reg
= MAC_RSS_INDIR_TBL_0
;
8223 u8
*ent
= (u8
*)&val
;
8225 /* Setup the indirection table */
8226 for (i
= 0; i
< TG3_RSS_INDIR_TBL_SIZE
; i
++) {
8227 int idx
= i
% sizeof(val
);
8229 ent
[idx
] = i
% (tp
->irq_cnt
- 1);
8230 if (idx
== sizeof(val
) - 1) {
8236 /* Setup the "secret" hash key. */
8237 tw32(MAC_RSS_HASH_KEY_0
, 0x5f865437);
8238 tw32(MAC_RSS_HASH_KEY_1
, 0xe4ac62cc);
8239 tw32(MAC_RSS_HASH_KEY_2
, 0x50103a45);
8240 tw32(MAC_RSS_HASH_KEY_3
, 0x36621985);
8241 tw32(MAC_RSS_HASH_KEY_4
, 0xbf14c0e8);
8242 tw32(MAC_RSS_HASH_KEY_5
, 0x1bc27a1e);
8243 tw32(MAC_RSS_HASH_KEY_6
, 0x84f4b556);
8244 tw32(MAC_RSS_HASH_KEY_7
, 0x094ea6fe);
8245 tw32(MAC_RSS_HASH_KEY_8
, 0x7dda01e7);
8246 tw32(MAC_RSS_HASH_KEY_9
, 0xc04d7481);
8249 tp
->rx_mode
= RX_MODE_ENABLE
;
8250 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
8251 tp
->rx_mode
|= RX_MODE_IPV6_CSUM_ENABLE
;
8253 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_RSS
)
8254 tp
->rx_mode
|= RX_MODE_RSS_ENABLE
|
8255 RX_MODE_RSS_ITBL_HASH_BITS_7
|
8256 RX_MODE_RSS_IPV6_HASH_EN
|
8257 RX_MODE_RSS_TCP_IPV6_HASH_EN
|
8258 RX_MODE_RSS_IPV4_HASH_EN
|
8259 RX_MODE_RSS_TCP_IPV4_HASH_EN
;
8261 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
8264 tw32(MAC_LED_CTRL
, tp
->led_ctrl
);
8266 tw32(MAC_MI_STAT
, MAC_MI_STAT_LNKSTAT_ATTN_ENAB
);
8267 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
8268 tw32_f(MAC_RX_MODE
, RX_MODE_RESET
);
8271 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
8274 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
8275 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) &&
8276 !(tp
->tg3_flags2
& TG3_FLG2_SERDES_PREEMPHASIS
)) {
8277 /* Set drive transmission level to 1.2V */
8278 /* only if the signal pre-emphasis bit is not set */
8279 val
= tr32(MAC_SERDES_CFG
);
8282 tw32(MAC_SERDES_CFG
, val
);
8284 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5703_A1
)
8285 tw32(MAC_SERDES_CFG
, 0x616000);
8288 /* Prevent chip from dropping frames when flow control
8291 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
8295 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME
, val
);
8297 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
&&
8298 (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)) {
8299 /* Use hardware link auto-negotiation */
8300 tp
->tg3_flags2
|= TG3_FLG2_HW_AUTONEG
;
8303 if ((tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
) &&
8304 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
)) {
8307 tmp
= tr32(SERDES_RX_CTRL
);
8308 tw32(SERDES_RX_CTRL
, tmp
| SERDES_RX_SIG_DETECT
);
8309 tp
->grc_local_ctrl
&= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT
;
8310 tp
->grc_local_ctrl
|= GRC_LCLCTRL_USE_SIG_DETECT
;
8311 tw32(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
);
8314 if (!(tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
)) {
8315 if (tp
->link_config
.phy_is_low_power
) {
8316 tp
->link_config
.phy_is_low_power
= 0;
8317 tp
->link_config
.speed
= tp
->link_config
.orig_speed
;
8318 tp
->link_config
.duplex
= tp
->link_config
.orig_duplex
;
8319 tp
->link_config
.autoneg
= tp
->link_config
.orig_autoneg
;
8322 err
= tg3_setup_phy(tp
, 0);
8326 if (!(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) &&
8327 !(tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
)) {
8330 /* Clear CRC stats. */
8331 if (!tg3_readphy(tp
, MII_TG3_TEST1
, &tmp
)) {
8332 tg3_writephy(tp
, MII_TG3_TEST1
,
8333 tmp
| MII_TG3_TEST1_CRC_EN
);
8334 tg3_readphy(tp
, 0x14, &tmp
);
8339 __tg3_set_rx_mode(tp
->dev
);
8341 /* Initialize receive rules. */
8342 tw32(MAC_RCV_RULE_0
, 0xc2000000 & RCV_RULE_DISABLE_MASK
);
8343 tw32(MAC_RCV_VALUE_0
, 0xffffffff & RCV_RULE_DISABLE_MASK
);
8344 tw32(MAC_RCV_RULE_1
, 0x86000004 & RCV_RULE_DISABLE_MASK
);
8345 tw32(MAC_RCV_VALUE_1
, 0xffffffff & RCV_RULE_DISABLE_MASK
);
8347 if ((tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
8348 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
8352 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)
8356 tw32(MAC_RCV_RULE_15
, 0); tw32(MAC_RCV_VALUE_15
, 0);
8358 tw32(MAC_RCV_RULE_14
, 0); tw32(MAC_RCV_VALUE_14
, 0);
8360 tw32(MAC_RCV_RULE_13
, 0); tw32(MAC_RCV_VALUE_13
, 0);
8362 tw32(MAC_RCV_RULE_12
, 0); tw32(MAC_RCV_VALUE_12
, 0);
8364 tw32(MAC_RCV_RULE_11
, 0); tw32(MAC_RCV_VALUE_11
, 0);
8366 tw32(MAC_RCV_RULE_10
, 0); tw32(MAC_RCV_VALUE_10
, 0);
8368 tw32(MAC_RCV_RULE_9
, 0); tw32(MAC_RCV_VALUE_9
, 0);
8370 tw32(MAC_RCV_RULE_8
, 0); tw32(MAC_RCV_VALUE_8
, 0);
8372 tw32(MAC_RCV_RULE_7
, 0); tw32(MAC_RCV_VALUE_7
, 0);
8374 tw32(MAC_RCV_RULE_6
, 0); tw32(MAC_RCV_VALUE_6
, 0);
8376 tw32(MAC_RCV_RULE_5
, 0); tw32(MAC_RCV_VALUE_5
, 0);
8378 tw32(MAC_RCV_RULE_4
, 0); tw32(MAC_RCV_VALUE_4
, 0);
8380 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
8382 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
8390 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
8391 /* Write our heartbeat update interval to APE. */
8392 tg3_ape_write32(tp
, TG3_APE_HOST_HEARTBEAT_INT_MS
,
8393 APE_HOST_HEARTBEAT_INT_DISABLE
);
8395 tg3_write_sig_post_reset(tp
, RESET_KIND_INIT
);
8400 /* Called at device open time to get the chip ready for
8401 * packet processing. Invoked with tp->lock held.
8403 static int tg3_init_hw(struct tg3
*tp
, int reset_phy
)
8405 tg3_switch_clocks(tp
);
8407 tw32(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
8409 return tg3_reset_hw(tp
, reset_phy
);
8412 #define TG3_STAT_ADD32(PSTAT, REG) \
8413 do { u32 __val = tr32(REG); \
8414 (PSTAT)->low += __val; \
8415 if ((PSTAT)->low < __val) \
8416 (PSTAT)->high += 1; \
8419 static void tg3_periodic_fetch_stats(struct tg3
*tp
)
8421 struct tg3_hw_stats
*sp
= tp
->hw_stats
;
8423 if (!netif_carrier_ok(tp
->dev
))
8426 TG3_STAT_ADD32(&sp
->tx_octets
, MAC_TX_STATS_OCTETS
);
8427 TG3_STAT_ADD32(&sp
->tx_collisions
, MAC_TX_STATS_COLLISIONS
);
8428 TG3_STAT_ADD32(&sp
->tx_xon_sent
, MAC_TX_STATS_XON_SENT
);
8429 TG3_STAT_ADD32(&sp
->tx_xoff_sent
, MAC_TX_STATS_XOFF_SENT
);
8430 TG3_STAT_ADD32(&sp
->tx_mac_errors
, MAC_TX_STATS_MAC_ERRORS
);
8431 TG3_STAT_ADD32(&sp
->tx_single_collisions
, MAC_TX_STATS_SINGLE_COLLISIONS
);
8432 TG3_STAT_ADD32(&sp
->tx_mult_collisions
, MAC_TX_STATS_MULT_COLLISIONS
);
8433 TG3_STAT_ADD32(&sp
->tx_deferred
, MAC_TX_STATS_DEFERRED
);
8434 TG3_STAT_ADD32(&sp
->tx_excessive_collisions
, MAC_TX_STATS_EXCESSIVE_COL
);
8435 TG3_STAT_ADD32(&sp
->tx_late_collisions
, MAC_TX_STATS_LATE_COL
);
8436 TG3_STAT_ADD32(&sp
->tx_ucast_packets
, MAC_TX_STATS_UCAST
);
8437 TG3_STAT_ADD32(&sp
->tx_mcast_packets
, MAC_TX_STATS_MCAST
);
8438 TG3_STAT_ADD32(&sp
->tx_bcast_packets
, MAC_TX_STATS_BCAST
);
8440 TG3_STAT_ADD32(&sp
->rx_octets
, MAC_RX_STATS_OCTETS
);
8441 TG3_STAT_ADD32(&sp
->rx_fragments
, MAC_RX_STATS_FRAGMENTS
);
8442 TG3_STAT_ADD32(&sp
->rx_ucast_packets
, MAC_RX_STATS_UCAST
);
8443 TG3_STAT_ADD32(&sp
->rx_mcast_packets
, MAC_RX_STATS_MCAST
);
8444 TG3_STAT_ADD32(&sp
->rx_bcast_packets
, MAC_RX_STATS_BCAST
);
8445 TG3_STAT_ADD32(&sp
->rx_fcs_errors
, MAC_RX_STATS_FCS_ERRORS
);
8446 TG3_STAT_ADD32(&sp
->rx_align_errors
, MAC_RX_STATS_ALIGN_ERRORS
);
8447 TG3_STAT_ADD32(&sp
->rx_xon_pause_rcvd
, MAC_RX_STATS_XON_PAUSE_RECVD
);
8448 TG3_STAT_ADD32(&sp
->rx_xoff_pause_rcvd
, MAC_RX_STATS_XOFF_PAUSE_RECVD
);
8449 TG3_STAT_ADD32(&sp
->rx_mac_ctrl_rcvd
, MAC_RX_STATS_MAC_CTRL_RECVD
);
8450 TG3_STAT_ADD32(&sp
->rx_xoff_entered
, MAC_RX_STATS_XOFF_ENTERED
);
8451 TG3_STAT_ADD32(&sp
->rx_frame_too_long_errors
, MAC_RX_STATS_FRAME_TOO_LONG
);
8452 TG3_STAT_ADD32(&sp
->rx_jabbers
, MAC_RX_STATS_JABBERS
);
8453 TG3_STAT_ADD32(&sp
->rx_undersize_packets
, MAC_RX_STATS_UNDERSIZE
);
8455 TG3_STAT_ADD32(&sp
->rxbds_empty
, RCVLPC_NO_RCV_BD_CNT
);
8456 TG3_STAT_ADD32(&sp
->rx_discards
, RCVLPC_IN_DISCARDS_CNT
);
8457 TG3_STAT_ADD32(&sp
->rx_errors
, RCVLPC_IN_ERRORS_CNT
);
8460 static void tg3_timer(unsigned long __opaque
)
8462 struct tg3
*tp
= (struct tg3
*) __opaque
;
8467 spin_lock(&tp
->lock
);
8469 if (!(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)) {
8470 /* All of this garbage is because when using non-tagged
8471 * IRQ status the mailbox/status_block protocol the chip
8472 * uses with the cpu is race prone.
8474 if (tp
->napi
[0].hw_status
->status
& SD_STATUS_UPDATED
) {
8475 tw32(GRC_LOCAL_CTRL
,
8476 tp
->grc_local_ctrl
| GRC_LCLCTRL_SETINT
);
8478 tw32(HOSTCC_MODE
, tp
->coalesce_mode
|
8479 HOSTCC_MODE_ENABLE
| HOSTCC_MODE_NOW
);
8482 if (!(tr32(WDMAC_MODE
) & WDMAC_MODE_ENABLE
)) {
8483 tp
->tg3_flags2
|= TG3_FLG2_RESTART_TIMER
;
8484 spin_unlock(&tp
->lock
);
8485 schedule_work(&tp
->reset_task
);
8490 /* This part only runs once per second. */
8491 if (!--tp
->timer_counter
) {
8492 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
8493 tg3_periodic_fetch_stats(tp
);
8495 if (tp
->tg3_flags
& TG3_FLAG_USE_LINKCHG_REG
) {
8499 mac_stat
= tr32(MAC_STATUS
);
8502 if (tp
->tg3_flags
& TG3_FLAG_USE_MI_INTERRUPT
) {
8503 if (mac_stat
& MAC_STATUS_MI_INTERRUPT
)
8505 } else if (mac_stat
& MAC_STATUS_LNKSTATE_CHANGED
)
8509 tg3_setup_phy(tp
, 0);
8510 } else if (tp
->tg3_flags
& TG3_FLAG_POLL_SERDES
) {
8511 u32 mac_stat
= tr32(MAC_STATUS
);
8514 if (netif_carrier_ok(tp
->dev
) &&
8515 (mac_stat
& MAC_STATUS_LNKSTATE_CHANGED
)) {
8518 if (!netif_carrier_ok(tp
->dev
) &&
8519 (mac_stat
& (MAC_STATUS_PCS_SYNCED
|
8520 MAC_STATUS_SIGNAL_DET
))) {
8524 if (!tp
->serdes_counter
) {
8527 ~MAC_MODE_PORT_MODE_MASK
));
8529 tw32_f(MAC_MODE
, tp
->mac_mode
);
8532 tg3_setup_phy(tp
, 0);
8534 } else if ((tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
) &&
8535 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
8536 tg3_serdes_parallel_detect(tp
);
8539 tp
->timer_counter
= tp
->timer_multiplier
;
8542 /* Heartbeat is only sent once every 2 seconds.
8544 * The heartbeat is to tell the ASF firmware that the host
8545 * driver is still alive. In the event that the OS crashes,
8546 * ASF needs to reset the hardware to free up the FIFO space
8547 * that may be filled with rx packets destined for the host.
8548 * If the FIFO is full, ASF will no longer function properly.
8550 * Unintended resets have been reported on real time kernels
8551 * where the timer doesn't run on time. Netpoll will also have
8554 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8555 * to check the ring condition when the heartbeat is expiring
8556 * before doing the reset. This will prevent most unintended
8559 if (!--tp
->asf_counter
) {
8560 if ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) &&
8561 !(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)) {
8562 tg3_wait_for_event_ack(tp
);
8564 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_MBOX
,
8565 FWCMD_NICDRV_ALIVE3
);
8566 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_LEN_MBOX
, 4);
8567 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
,
8568 TG3_FW_UPDATE_TIMEOUT_SEC
);
8570 tg3_generate_fw_event(tp
);
8572 tp
->asf_counter
= tp
->asf_multiplier
;
8575 spin_unlock(&tp
->lock
);
8578 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
8579 add_timer(&tp
->timer
);
8582 static int tg3_request_irq(struct tg3
*tp
, int irq_num
)
8585 unsigned long flags
;
8587 struct tg3_napi
*tnapi
= &tp
->napi
[irq_num
];
8589 if (tp
->irq_cnt
== 1)
8590 name
= tp
->dev
->name
;
8592 name
= &tnapi
->irq_lbl
[0];
8593 snprintf(name
, IFNAMSIZ
, "%s-%d", tp
->dev
->name
, irq_num
);
8594 name
[IFNAMSIZ
-1] = 0;
8597 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI_OR_MSIX
) {
8599 if (tp
->tg3_flags2
& TG3_FLG2_1SHOT_MSI
)
8601 flags
= IRQF_SAMPLE_RANDOM
;
8604 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)
8605 fn
= tg3_interrupt_tagged
;
8606 flags
= IRQF_SHARED
| IRQF_SAMPLE_RANDOM
;
8609 return request_irq(tnapi
->irq_vec
, fn
, flags
, name
, tnapi
);
8612 static int tg3_test_interrupt(struct tg3
*tp
)
8614 struct tg3_napi
*tnapi
= &tp
->napi
[0];
8615 struct net_device
*dev
= tp
->dev
;
8616 int err
, i
, intr_ok
= 0;
8619 if (!netif_running(dev
))
8622 tg3_disable_ints(tp
);
8624 free_irq(tnapi
->irq_vec
, tnapi
);
8627 * Turn off MSI one shot mode. Otherwise this test has no
8628 * observable way to know whether the interrupt was delivered.
8630 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
8631 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
||
8632 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
) &&
8633 (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
)) {
8634 val
= tr32(MSGINT_MODE
) | MSGINT_MODE_ONE_SHOT_DISABLE
;
8635 tw32(MSGINT_MODE
, val
);
8638 err
= request_irq(tnapi
->irq_vec
, tg3_test_isr
,
8639 IRQF_SHARED
| IRQF_SAMPLE_RANDOM
, dev
->name
, tnapi
);
8643 tnapi
->hw_status
->status
&= ~SD_STATUS_UPDATED
;
8644 tg3_enable_ints(tp
);
8646 tw32_f(HOSTCC_MODE
, tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
|
8649 for (i
= 0; i
< 5; i
++) {
8650 u32 int_mbox
, misc_host_ctrl
;
8652 int_mbox
= tr32_mailbox(tnapi
->int_mbox
);
8653 misc_host_ctrl
= tr32(TG3PCI_MISC_HOST_CTRL
);
8655 if ((int_mbox
!= 0) ||
8656 (misc_host_ctrl
& MISC_HOST_CTRL_MASK_PCI_INT
)) {
8664 tg3_disable_ints(tp
);
8666 free_irq(tnapi
->irq_vec
, tnapi
);
8668 err
= tg3_request_irq(tp
, 0);
8674 /* Reenable MSI one shot mode. */
8675 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
8676 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
||
8677 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
) &&
8678 (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
)) {
8679 val
= tr32(MSGINT_MODE
) & ~MSGINT_MODE_ONE_SHOT_DISABLE
;
8680 tw32(MSGINT_MODE
, val
);
8688 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8689 * successfully restored
8691 static int tg3_test_msi(struct tg3
*tp
)
8696 if (!(tp
->tg3_flags2
& TG3_FLG2_USING_MSI
))
8699 /* Turn off SERR reporting in case MSI terminates with Master
8702 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
8703 pci_write_config_word(tp
->pdev
, PCI_COMMAND
,
8704 pci_cmd
& ~PCI_COMMAND_SERR
);
8706 err
= tg3_test_interrupt(tp
);
8708 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
8713 /* other failures */
8717 /* MSI test failed, go back to INTx mode */
8718 netdev_warn(tp
->dev
, "No interrupt was generated using MSI. Switching "
8719 "to INTx mode. Please report this failure to the PCI "
8720 "maintainer and include system chipset information\n");
8722 free_irq(tp
->napi
[0].irq_vec
, &tp
->napi
[0]);
8724 pci_disable_msi(tp
->pdev
);
8726 tp
->tg3_flags2
&= ~TG3_FLG2_USING_MSI
;
8727 tp
->napi
[0].irq_vec
= tp
->pdev
->irq
;
8729 err
= tg3_request_irq(tp
, 0);
8733 /* Need to reset the chip because the MSI cycle may have terminated
8734 * with Master Abort.
8736 tg3_full_lock(tp
, 1);
8738 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
8739 err
= tg3_init_hw(tp
, 1);
8741 tg3_full_unlock(tp
);
8744 free_irq(tp
->napi
[0].irq_vec
, &tp
->napi
[0]);
8749 static int tg3_request_firmware(struct tg3
*tp
)
8751 const __be32
*fw_data
;
8753 if (request_firmware(&tp
->fw
, tp
->fw_needed
, &tp
->pdev
->dev
)) {
8754 netdev_err(tp
->dev
, "Failed to load firmware \"%s\"\n",
8759 fw_data
= (void *)tp
->fw
->data
;
8761 /* Firmware blob starts with version numbers, followed by
8762 * start address and _full_ length including BSS sections
8763 * (which must be longer than the actual data, of course
8766 tp
->fw_len
= be32_to_cpu(fw_data
[2]); /* includes bss */
8767 if (tp
->fw_len
< (tp
->fw
->size
- 12)) {
8768 netdev_err(tp
->dev
, "bogus length %d in \"%s\"\n",
8769 tp
->fw_len
, tp
->fw_needed
);
8770 release_firmware(tp
->fw
);
8775 /* We no longer need firmware; we have it. */
8776 tp
->fw_needed
= NULL
;
8780 static bool tg3_enable_msix(struct tg3
*tp
)
8782 int i
, rc
, cpus
= num_online_cpus();
8783 struct msix_entry msix_ent
[tp
->irq_max
];
8786 /* Just fallback to the simpler MSI mode. */
8790 * We want as many rx rings enabled as there are cpus.
8791 * The first MSIX vector only deals with link interrupts, etc,
8792 * so we add one to the number of vectors we are requesting.
8794 tp
->irq_cnt
= min_t(unsigned, cpus
+ 1, tp
->irq_max
);
8796 for (i
= 0; i
< tp
->irq_max
; i
++) {
8797 msix_ent
[i
].entry
= i
;
8798 msix_ent
[i
].vector
= 0;
8801 rc
= pci_enable_msix(tp
->pdev
, msix_ent
, tp
->irq_cnt
);
8804 } else if (rc
!= 0) {
8805 if (pci_enable_msix(tp
->pdev
, msix_ent
, rc
))
8807 netdev_notice(tp
->dev
, "Requested %d MSI-X vectors, received %d\n",
8812 for (i
= 0; i
< tp
->irq_max
; i
++)
8813 tp
->napi
[i
].irq_vec
= msix_ent
[i
].vector
;
8815 tp
->dev
->real_num_tx_queues
= 1;
8816 if (tp
->irq_cnt
> 1) {
8817 tp
->tg3_flags3
|= TG3_FLG3_ENABLE_RSS
;
8819 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
8820 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
) {
8821 tp
->tg3_flags3
|= TG3_FLG3_ENABLE_TSS
;
8822 tp
->dev
->real_num_tx_queues
= tp
->irq_cnt
- 1;
8829 static void tg3_ints_init(struct tg3
*tp
)
8831 if ((tp
->tg3_flags
& TG3_FLAG_SUPPORT_MSI_OR_MSIX
) &&
8832 !(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)) {
8833 /* All MSI supporting chips should support tagged
8834 * status. Assert that this is the case.
8836 netdev_warn(tp
->dev
,
8837 "MSI without TAGGED_STATUS? Not using MSI\n");
8841 if ((tp
->tg3_flags
& TG3_FLAG_SUPPORT_MSIX
) && tg3_enable_msix(tp
))
8842 tp
->tg3_flags2
|= TG3_FLG2_USING_MSIX
;
8843 else if ((tp
->tg3_flags
& TG3_FLAG_SUPPORT_MSI
) &&
8844 pci_enable_msi(tp
->pdev
) == 0)
8845 tp
->tg3_flags2
|= TG3_FLG2_USING_MSI
;
8847 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI_OR_MSIX
) {
8848 u32 msi_mode
= tr32(MSGINT_MODE
);
8849 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSIX
)
8850 msi_mode
|= MSGINT_MODE_MULTIVEC_EN
;
8851 tw32(MSGINT_MODE
, msi_mode
| MSGINT_MODE_ENABLE
);
8854 if (!(tp
->tg3_flags2
& TG3_FLG2_USING_MSIX
)) {
8856 tp
->napi
[0].irq_vec
= tp
->pdev
->irq
;
8857 tp
->dev
->real_num_tx_queues
= 1;
8861 static void tg3_ints_fini(struct tg3
*tp
)
8863 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSIX
)
8864 pci_disable_msix(tp
->pdev
);
8865 else if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
)
8866 pci_disable_msi(tp
->pdev
);
8867 tp
->tg3_flags2
&= ~TG3_FLG2_USING_MSI_OR_MSIX
;
8868 tp
->tg3_flags3
&= ~TG3_FLG3_ENABLE_RSS
;
8871 static int tg3_open(struct net_device
*dev
)
8873 struct tg3
*tp
= netdev_priv(dev
);
8876 if (tp
->fw_needed
) {
8877 err
= tg3_request_firmware(tp
);
8878 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
) {
8882 netdev_warn(tp
->dev
, "TSO capability disabled\n");
8883 tp
->tg3_flags2
&= ~TG3_FLG2_TSO_CAPABLE
;
8884 } else if (!(tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
)) {
8885 netdev_notice(tp
->dev
, "TSO capability restored\n");
8886 tp
->tg3_flags2
|= TG3_FLG2_TSO_CAPABLE
;
8890 netif_carrier_off(tp
->dev
);
8892 err
= tg3_set_power_state(tp
, PCI_D0
);
8896 tg3_full_lock(tp
, 0);
8898 tg3_disable_ints(tp
);
8899 tp
->tg3_flags
&= ~TG3_FLAG_INIT_COMPLETE
;
8901 tg3_full_unlock(tp
);
8904 * Setup interrupts first so we know how
8905 * many NAPI resources to allocate
8909 /* The placement of this call is tied
8910 * to the setup and use of Host TX descriptors.
8912 err
= tg3_alloc_consistent(tp
);
8916 tg3_napi_enable(tp
);
8918 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
8919 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
8920 err
= tg3_request_irq(tp
, i
);
8922 for (i
--; i
>= 0; i
--)
8923 free_irq(tnapi
->irq_vec
, tnapi
);
8931 tg3_full_lock(tp
, 0);
8933 err
= tg3_init_hw(tp
, 1);
8935 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
8938 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)
8939 tp
->timer_offset
= HZ
;
8941 tp
->timer_offset
= HZ
/ 10;
8943 BUG_ON(tp
->timer_offset
> HZ
);
8944 tp
->timer_counter
= tp
->timer_multiplier
=
8945 (HZ
/ tp
->timer_offset
);
8946 tp
->asf_counter
= tp
->asf_multiplier
=
8947 ((HZ
/ tp
->timer_offset
) * 2);
8949 init_timer(&tp
->timer
);
8950 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
8951 tp
->timer
.data
= (unsigned long) tp
;
8952 tp
->timer
.function
= tg3_timer
;
8955 tg3_full_unlock(tp
);
8960 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
8961 err
= tg3_test_msi(tp
);
8964 tg3_full_lock(tp
, 0);
8965 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
8967 tg3_full_unlock(tp
);
8972 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5717
&&
8973 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5719
&&
8974 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_57765
&&
8975 (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) &&
8976 (tp
->tg3_flags2
& TG3_FLG2_1SHOT_MSI
)) {
8977 u32 val
= tr32(PCIE_TRANSACTION_CFG
);
8979 tw32(PCIE_TRANSACTION_CFG
,
8980 val
| PCIE_TRANS_CFG_1SHOT_MSI
);
8986 tg3_full_lock(tp
, 0);
8988 add_timer(&tp
->timer
);
8989 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
8990 tg3_enable_ints(tp
);
8992 tg3_full_unlock(tp
);
8994 netif_tx_start_all_queues(dev
);
8999 for (i
= tp
->irq_cnt
- 1; i
>= 0; i
--) {
9000 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
9001 free_irq(tnapi
->irq_vec
, tnapi
);
9005 tg3_napi_disable(tp
);
9006 tg3_free_consistent(tp
);
9013 static struct rtnl_link_stats64
*tg3_get_stats64(struct net_device
*,
9014 struct rtnl_link_stats64
*);
9015 static struct tg3_ethtool_stats
*tg3_get_estats(struct tg3
*);
9017 static int tg3_close(struct net_device
*dev
)
9020 struct tg3
*tp
= netdev_priv(dev
);
9022 tg3_napi_disable(tp
);
9023 cancel_work_sync(&tp
->reset_task
);
9025 netif_tx_stop_all_queues(dev
);
9027 del_timer_sync(&tp
->timer
);
9031 tg3_full_lock(tp
, 1);
9033 tg3_disable_ints(tp
);
9035 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
9037 tp
->tg3_flags
&= ~TG3_FLAG_INIT_COMPLETE
;
9039 tg3_full_unlock(tp
);
9041 for (i
= tp
->irq_cnt
- 1; i
>= 0; i
--) {
9042 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
9043 free_irq(tnapi
->irq_vec
, tnapi
);
9048 tg3_get_stats64(tp
->dev
, &tp
->net_stats_prev
);
9050 memcpy(&tp
->estats_prev
, tg3_get_estats(tp
),
9051 sizeof(tp
->estats_prev
));
9053 tg3_free_consistent(tp
);
9055 tg3_set_power_state(tp
, PCI_D3hot
);
9057 netif_carrier_off(tp
->dev
);
9062 static inline u64
get_stat64(tg3_stat64_t
*val
)
9064 return ((u64
)val
->high
<< 32) | ((u64
)val
->low
);
9067 static u64
calc_crc_errors(struct tg3
*tp
)
9069 struct tg3_hw_stats
*hw_stats
= tp
->hw_stats
;
9071 if (!(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) &&
9072 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
9073 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)) {
9076 spin_lock_bh(&tp
->lock
);
9077 if (!tg3_readphy(tp
, MII_TG3_TEST1
, &val
)) {
9078 tg3_writephy(tp
, MII_TG3_TEST1
,
9079 val
| MII_TG3_TEST1_CRC_EN
);
9080 tg3_readphy(tp
, 0x14, &val
);
9083 spin_unlock_bh(&tp
->lock
);
9085 tp
->phy_crc_errors
+= val
;
9087 return tp
->phy_crc_errors
;
9090 return get_stat64(&hw_stats
->rx_fcs_errors
);
9093 #define ESTAT_ADD(member) \
9094 estats->member = old_estats->member + \
9095 get_stat64(&hw_stats->member)
9097 static struct tg3_ethtool_stats
*tg3_get_estats(struct tg3
*tp
)
9099 struct tg3_ethtool_stats
*estats
= &tp
->estats
;
9100 struct tg3_ethtool_stats
*old_estats
= &tp
->estats_prev
;
9101 struct tg3_hw_stats
*hw_stats
= tp
->hw_stats
;
9106 ESTAT_ADD(rx_octets
);
9107 ESTAT_ADD(rx_fragments
);
9108 ESTAT_ADD(rx_ucast_packets
);
9109 ESTAT_ADD(rx_mcast_packets
);
9110 ESTAT_ADD(rx_bcast_packets
);
9111 ESTAT_ADD(rx_fcs_errors
);
9112 ESTAT_ADD(rx_align_errors
);
9113 ESTAT_ADD(rx_xon_pause_rcvd
);
9114 ESTAT_ADD(rx_xoff_pause_rcvd
);
9115 ESTAT_ADD(rx_mac_ctrl_rcvd
);
9116 ESTAT_ADD(rx_xoff_entered
);
9117 ESTAT_ADD(rx_frame_too_long_errors
);
9118 ESTAT_ADD(rx_jabbers
);
9119 ESTAT_ADD(rx_undersize_packets
);
9120 ESTAT_ADD(rx_in_length_errors
);
9121 ESTAT_ADD(rx_out_length_errors
);
9122 ESTAT_ADD(rx_64_or_less_octet_packets
);
9123 ESTAT_ADD(rx_65_to_127_octet_packets
);
9124 ESTAT_ADD(rx_128_to_255_octet_packets
);
9125 ESTAT_ADD(rx_256_to_511_octet_packets
);
9126 ESTAT_ADD(rx_512_to_1023_octet_packets
);
9127 ESTAT_ADD(rx_1024_to_1522_octet_packets
);
9128 ESTAT_ADD(rx_1523_to_2047_octet_packets
);
9129 ESTAT_ADD(rx_2048_to_4095_octet_packets
);
9130 ESTAT_ADD(rx_4096_to_8191_octet_packets
);
9131 ESTAT_ADD(rx_8192_to_9022_octet_packets
);
9133 ESTAT_ADD(tx_octets
);
9134 ESTAT_ADD(tx_collisions
);
9135 ESTAT_ADD(tx_xon_sent
);
9136 ESTAT_ADD(tx_xoff_sent
);
9137 ESTAT_ADD(tx_flow_control
);
9138 ESTAT_ADD(tx_mac_errors
);
9139 ESTAT_ADD(tx_single_collisions
);
9140 ESTAT_ADD(tx_mult_collisions
);
9141 ESTAT_ADD(tx_deferred
);
9142 ESTAT_ADD(tx_excessive_collisions
);
9143 ESTAT_ADD(tx_late_collisions
);
9144 ESTAT_ADD(tx_collide_2times
);
9145 ESTAT_ADD(tx_collide_3times
);
9146 ESTAT_ADD(tx_collide_4times
);
9147 ESTAT_ADD(tx_collide_5times
);
9148 ESTAT_ADD(tx_collide_6times
);
9149 ESTAT_ADD(tx_collide_7times
);
9150 ESTAT_ADD(tx_collide_8times
);
9151 ESTAT_ADD(tx_collide_9times
);
9152 ESTAT_ADD(tx_collide_10times
);
9153 ESTAT_ADD(tx_collide_11times
);
9154 ESTAT_ADD(tx_collide_12times
);
9155 ESTAT_ADD(tx_collide_13times
);
9156 ESTAT_ADD(tx_collide_14times
);
9157 ESTAT_ADD(tx_collide_15times
);
9158 ESTAT_ADD(tx_ucast_packets
);
9159 ESTAT_ADD(tx_mcast_packets
);
9160 ESTAT_ADD(tx_bcast_packets
);
9161 ESTAT_ADD(tx_carrier_sense_errors
);
9162 ESTAT_ADD(tx_discards
);
9163 ESTAT_ADD(tx_errors
);
9165 ESTAT_ADD(dma_writeq_full
);
9166 ESTAT_ADD(dma_write_prioq_full
);
9167 ESTAT_ADD(rxbds_empty
);
9168 ESTAT_ADD(rx_discards
);
9169 ESTAT_ADD(rx_errors
);
9170 ESTAT_ADD(rx_threshold_hit
);
9172 ESTAT_ADD(dma_readq_full
);
9173 ESTAT_ADD(dma_read_prioq_full
);
9174 ESTAT_ADD(tx_comp_queue_full
);
9176 ESTAT_ADD(ring_set_send_prod_index
);
9177 ESTAT_ADD(ring_status_update
);
9178 ESTAT_ADD(nic_irqs
);
9179 ESTAT_ADD(nic_avoided_irqs
);
9180 ESTAT_ADD(nic_tx_threshold_hit
);
9185 static struct rtnl_link_stats64
*tg3_get_stats64(struct net_device
*dev
,
9186 struct rtnl_link_stats64
*stats
)
9188 struct tg3
*tp
= netdev_priv(dev
);
9189 struct rtnl_link_stats64
*old_stats
= &tp
->net_stats_prev
;
9190 struct tg3_hw_stats
*hw_stats
= tp
->hw_stats
;
9195 stats
->rx_packets
= old_stats
->rx_packets
+
9196 get_stat64(&hw_stats
->rx_ucast_packets
) +
9197 get_stat64(&hw_stats
->rx_mcast_packets
) +
9198 get_stat64(&hw_stats
->rx_bcast_packets
);
9200 stats
->tx_packets
= old_stats
->tx_packets
+
9201 get_stat64(&hw_stats
->tx_ucast_packets
) +
9202 get_stat64(&hw_stats
->tx_mcast_packets
) +
9203 get_stat64(&hw_stats
->tx_bcast_packets
);
9205 stats
->rx_bytes
= old_stats
->rx_bytes
+
9206 get_stat64(&hw_stats
->rx_octets
);
9207 stats
->tx_bytes
= old_stats
->tx_bytes
+
9208 get_stat64(&hw_stats
->tx_octets
);
9210 stats
->rx_errors
= old_stats
->rx_errors
+
9211 get_stat64(&hw_stats
->rx_errors
);
9212 stats
->tx_errors
= old_stats
->tx_errors
+
9213 get_stat64(&hw_stats
->tx_errors
) +
9214 get_stat64(&hw_stats
->tx_mac_errors
) +
9215 get_stat64(&hw_stats
->tx_carrier_sense_errors
) +
9216 get_stat64(&hw_stats
->tx_discards
);
9218 stats
->multicast
= old_stats
->multicast
+
9219 get_stat64(&hw_stats
->rx_mcast_packets
);
9220 stats
->collisions
= old_stats
->collisions
+
9221 get_stat64(&hw_stats
->tx_collisions
);
9223 stats
->rx_length_errors
= old_stats
->rx_length_errors
+
9224 get_stat64(&hw_stats
->rx_frame_too_long_errors
) +
9225 get_stat64(&hw_stats
->rx_undersize_packets
);
9227 stats
->rx_over_errors
= old_stats
->rx_over_errors
+
9228 get_stat64(&hw_stats
->rxbds_empty
);
9229 stats
->rx_frame_errors
= old_stats
->rx_frame_errors
+
9230 get_stat64(&hw_stats
->rx_align_errors
);
9231 stats
->tx_aborted_errors
= old_stats
->tx_aborted_errors
+
9232 get_stat64(&hw_stats
->tx_discards
);
9233 stats
->tx_carrier_errors
= old_stats
->tx_carrier_errors
+
9234 get_stat64(&hw_stats
->tx_carrier_sense_errors
);
9236 stats
->rx_crc_errors
= old_stats
->rx_crc_errors
+
9237 calc_crc_errors(tp
);
9239 stats
->rx_missed_errors
= old_stats
->rx_missed_errors
+
9240 get_stat64(&hw_stats
->rx_discards
);
9245 static inline u32
calc_crc(unsigned char *buf
, int len
)
9253 for (j
= 0; j
< len
; j
++) {
9256 for (k
= 0; k
< 8; k
++) {
9269 static void tg3_set_multi(struct tg3
*tp
, unsigned int accept_all
)
9271 /* accept or reject all multicast frames */
9272 tw32(MAC_HASH_REG_0
, accept_all
? 0xffffffff : 0);
9273 tw32(MAC_HASH_REG_1
, accept_all
? 0xffffffff : 0);
9274 tw32(MAC_HASH_REG_2
, accept_all
? 0xffffffff : 0);
9275 tw32(MAC_HASH_REG_3
, accept_all
? 0xffffffff : 0);
9278 static void __tg3_set_rx_mode(struct net_device
*dev
)
9280 struct tg3
*tp
= netdev_priv(dev
);
9283 rx_mode
= tp
->rx_mode
& ~(RX_MODE_PROMISC
|
9284 RX_MODE_KEEP_VLAN_TAG
);
9286 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9289 #if TG3_VLAN_TAG_USED
9291 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
9292 rx_mode
|= RX_MODE_KEEP_VLAN_TAG
;
9294 /* By definition, VLAN is disabled always in this
9297 if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
9298 rx_mode
|= RX_MODE_KEEP_VLAN_TAG
;
9301 if (dev
->flags
& IFF_PROMISC
) {
9302 /* Promiscuous mode. */
9303 rx_mode
|= RX_MODE_PROMISC
;
9304 } else if (dev
->flags
& IFF_ALLMULTI
) {
9305 /* Accept all multicast. */
9306 tg3_set_multi(tp
, 1);
9307 } else if (netdev_mc_empty(dev
)) {
9308 /* Reject all multicast. */
9309 tg3_set_multi(tp
, 0);
9311 /* Accept one or more multicast(s). */
9312 struct netdev_hw_addr
*ha
;
9313 u32 mc_filter
[4] = { 0, };
9318 netdev_for_each_mc_addr(ha
, dev
) {
9319 crc
= calc_crc(ha
->addr
, ETH_ALEN
);
9321 regidx
= (bit
& 0x60) >> 5;
9323 mc_filter
[regidx
] |= (1 << bit
);
9326 tw32(MAC_HASH_REG_0
, mc_filter
[0]);
9327 tw32(MAC_HASH_REG_1
, mc_filter
[1]);
9328 tw32(MAC_HASH_REG_2
, mc_filter
[2]);
9329 tw32(MAC_HASH_REG_3
, mc_filter
[3]);
9332 if (rx_mode
!= tp
->rx_mode
) {
9333 tp
->rx_mode
= rx_mode
;
9334 tw32_f(MAC_RX_MODE
, rx_mode
);
9339 static void tg3_set_rx_mode(struct net_device
*dev
)
9341 struct tg3
*tp
= netdev_priv(dev
);
9343 if (!netif_running(dev
))
9346 tg3_full_lock(tp
, 0);
9347 __tg3_set_rx_mode(dev
);
9348 tg3_full_unlock(tp
);
9351 #define TG3_REGDUMP_LEN (32 * 1024)
9353 static int tg3_get_regs_len(struct net_device
*dev
)
9355 return TG3_REGDUMP_LEN
;
9358 static void tg3_get_regs(struct net_device
*dev
,
9359 struct ethtool_regs
*regs
, void *_p
)
9362 struct tg3
*tp
= netdev_priv(dev
);
9368 memset(p
, 0, TG3_REGDUMP_LEN
);
9370 if (tp
->link_config
.phy_is_low_power
)
9373 tg3_full_lock(tp
, 0);
9375 #define __GET_REG32(reg) (*(p)++ = tr32(reg))
9376 #define GET_REG32_LOOP(base, len) \
9377 do { p = (u32 *)(orig_p + (base)); \
9378 for (i = 0; i < len; i += 4) \
9379 __GET_REG32((base) + i); \
9381 #define GET_REG32_1(reg) \
9382 do { p = (u32 *)(orig_p + (reg)); \
9383 __GET_REG32((reg)); \
9386 GET_REG32_LOOP(TG3PCI_VENDOR
, 0xb0);
9387 GET_REG32_LOOP(MAILBOX_INTERRUPT_0
, 0x200);
9388 GET_REG32_LOOP(MAC_MODE
, 0x4f0);
9389 GET_REG32_LOOP(SNDDATAI_MODE
, 0xe0);
9390 GET_REG32_1(SNDDATAC_MODE
);
9391 GET_REG32_LOOP(SNDBDS_MODE
, 0x80);
9392 GET_REG32_LOOP(SNDBDI_MODE
, 0x48);
9393 GET_REG32_1(SNDBDC_MODE
);
9394 GET_REG32_LOOP(RCVLPC_MODE
, 0x20);
9395 GET_REG32_LOOP(RCVLPC_SELLST_BASE
, 0x15c);
9396 GET_REG32_LOOP(RCVDBDI_MODE
, 0x0c);
9397 GET_REG32_LOOP(RCVDBDI_JUMBO_BD
, 0x3c);
9398 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0
, 0x44);
9399 GET_REG32_1(RCVDCC_MODE
);
9400 GET_REG32_LOOP(RCVBDI_MODE
, 0x20);
9401 GET_REG32_LOOP(RCVCC_MODE
, 0x14);
9402 GET_REG32_LOOP(RCVLSC_MODE
, 0x08);
9403 GET_REG32_1(MBFREE_MODE
);
9404 GET_REG32_LOOP(HOSTCC_MODE
, 0x100);
9405 GET_REG32_LOOP(MEMARB_MODE
, 0x10);
9406 GET_REG32_LOOP(BUFMGR_MODE
, 0x58);
9407 GET_REG32_LOOP(RDMAC_MODE
, 0x08);
9408 GET_REG32_LOOP(WDMAC_MODE
, 0x08);
9409 GET_REG32_1(RX_CPU_MODE
);
9410 GET_REG32_1(RX_CPU_STATE
);
9411 GET_REG32_1(RX_CPU_PGMCTR
);
9412 GET_REG32_1(RX_CPU_HWBKPT
);
9413 GET_REG32_1(TX_CPU_MODE
);
9414 GET_REG32_1(TX_CPU_STATE
);
9415 GET_REG32_1(TX_CPU_PGMCTR
);
9416 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0
, 0x110);
9417 GET_REG32_LOOP(FTQ_RESET
, 0x120);
9418 GET_REG32_LOOP(MSGINT_MODE
, 0x0c);
9419 GET_REG32_1(DMAC_MODE
);
9420 GET_REG32_LOOP(GRC_MODE
, 0x4c);
9421 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
)
9422 GET_REG32_LOOP(NVRAM_CMD
, 0x24);
9425 #undef GET_REG32_LOOP
9428 tg3_full_unlock(tp
);
9431 static int tg3_get_eeprom_len(struct net_device
*dev
)
9433 struct tg3
*tp
= netdev_priv(dev
);
9435 return tp
->nvram_size
;
9438 static int tg3_get_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
, u8
*data
)
9440 struct tg3
*tp
= netdev_priv(dev
);
9443 u32 i
, offset
, len
, b_offset
, b_count
;
9446 if (tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
)
9449 if (tp
->link_config
.phy_is_low_power
)
9452 offset
= eeprom
->offset
;
9456 eeprom
->magic
= TG3_EEPROM_MAGIC
;
9459 /* adjustments to start on required 4 byte boundary */
9460 b_offset
= offset
& 3;
9461 b_count
= 4 - b_offset
;
9462 if (b_count
> len
) {
9463 /* i.e. offset=1 len=2 */
9466 ret
= tg3_nvram_read_be32(tp
, offset
-b_offset
, &val
);
9469 memcpy(data
, ((char *)&val
) + b_offset
, b_count
);
9472 eeprom
->len
+= b_count
;
9475 /* read bytes upto the last 4 byte boundary */
9476 pd
= &data
[eeprom
->len
];
9477 for (i
= 0; i
< (len
- (len
& 3)); i
+= 4) {
9478 ret
= tg3_nvram_read_be32(tp
, offset
+ i
, &val
);
9483 memcpy(pd
+ i
, &val
, 4);
9488 /* read last bytes not ending on 4 byte boundary */
9489 pd
= &data
[eeprom
->len
];
9491 b_offset
= offset
+ len
- b_count
;
9492 ret
= tg3_nvram_read_be32(tp
, b_offset
, &val
);
9495 memcpy(pd
, &val
, b_count
);
9496 eeprom
->len
+= b_count
;
9501 static int tg3_nvram_write_block(struct tg3
*tp
, u32 offset
, u32 len
, u8
*buf
);
9503 static int tg3_set_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
, u8
*data
)
9505 struct tg3
*tp
= netdev_priv(dev
);
9507 u32 offset
, len
, b_offset
, odd_len
;
9511 if (tp
->link_config
.phy_is_low_power
)
9514 if ((tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) ||
9515 eeprom
->magic
!= TG3_EEPROM_MAGIC
)
9518 offset
= eeprom
->offset
;
9521 if ((b_offset
= (offset
& 3))) {
9522 /* adjustments to start on required 4 byte boundary */
9523 ret
= tg3_nvram_read_be32(tp
, offset
-b_offset
, &start
);
9534 /* adjustments to end on required 4 byte boundary */
9536 len
= (len
+ 3) & ~3;
9537 ret
= tg3_nvram_read_be32(tp
, offset
+len
-4, &end
);
9543 if (b_offset
|| odd_len
) {
9544 buf
= kmalloc(len
, GFP_KERNEL
);
9548 memcpy(buf
, &start
, 4);
9550 memcpy(buf
+len
-4, &end
, 4);
9551 memcpy(buf
+ b_offset
, data
, eeprom
->len
);
9554 ret
= tg3_nvram_write_block(tp
, offset
, len
, buf
);
9562 static int tg3_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
9564 struct tg3
*tp
= netdev_priv(dev
);
9566 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
9567 struct phy_device
*phydev
;
9568 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
9570 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
9571 return phy_ethtool_gset(phydev
, cmd
);
9574 cmd
->supported
= (SUPPORTED_Autoneg
);
9576 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
))
9577 cmd
->supported
|= (SUPPORTED_1000baseT_Half
|
9578 SUPPORTED_1000baseT_Full
);
9580 if (!(tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
)) {
9581 cmd
->supported
|= (SUPPORTED_100baseT_Half
|
9582 SUPPORTED_100baseT_Full
|
9583 SUPPORTED_10baseT_Half
|
9584 SUPPORTED_10baseT_Full
|
9586 cmd
->port
= PORT_TP
;
9588 cmd
->supported
|= SUPPORTED_FIBRE
;
9589 cmd
->port
= PORT_FIBRE
;
9592 cmd
->advertising
= tp
->link_config
.advertising
;
9593 if (netif_running(dev
)) {
9594 cmd
->speed
= tp
->link_config
.active_speed
;
9595 cmd
->duplex
= tp
->link_config
.active_duplex
;
9597 cmd
->phy_address
= tp
->phy_addr
;
9598 cmd
->transceiver
= XCVR_INTERNAL
;
9599 cmd
->autoneg
= tp
->link_config
.autoneg
;
9605 static int tg3_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
9607 struct tg3
*tp
= netdev_priv(dev
);
9609 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
9610 struct phy_device
*phydev
;
9611 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
9613 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
9614 return phy_ethtool_sset(phydev
, cmd
);
9617 if (cmd
->autoneg
!= AUTONEG_ENABLE
&&
9618 cmd
->autoneg
!= AUTONEG_DISABLE
)
9621 if (cmd
->autoneg
== AUTONEG_DISABLE
&&
9622 cmd
->duplex
!= DUPLEX_FULL
&&
9623 cmd
->duplex
!= DUPLEX_HALF
)
9626 if (cmd
->autoneg
== AUTONEG_ENABLE
) {
9627 u32 mask
= ADVERTISED_Autoneg
|
9629 ADVERTISED_Asym_Pause
;
9631 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
))
9632 mask
|= ADVERTISED_1000baseT_Half
|
9633 ADVERTISED_1000baseT_Full
;
9635 if (!(tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
))
9636 mask
|= ADVERTISED_100baseT_Half
|
9637 ADVERTISED_100baseT_Full
|
9638 ADVERTISED_10baseT_Half
|
9639 ADVERTISED_10baseT_Full
|
9642 mask
|= ADVERTISED_FIBRE
;
9644 if (cmd
->advertising
& ~mask
)
9647 mask
&= (ADVERTISED_1000baseT_Half
|
9648 ADVERTISED_1000baseT_Full
|
9649 ADVERTISED_100baseT_Half
|
9650 ADVERTISED_100baseT_Full
|
9651 ADVERTISED_10baseT_Half
|
9652 ADVERTISED_10baseT_Full
);
9654 cmd
->advertising
&= mask
;
9656 if (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
) {
9657 if (cmd
->speed
!= SPEED_1000
)
9660 if (cmd
->duplex
!= DUPLEX_FULL
)
9663 if (cmd
->speed
!= SPEED_100
&&
9664 cmd
->speed
!= SPEED_10
)
9669 tg3_full_lock(tp
, 0);
9671 tp
->link_config
.autoneg
= cmd
->autoneg
;
9672 if (cmd
->autoneg
== AUTONEG_ENABLE
) {
9673 tp
->link_config
.advertising
= (cmd
->advertising
|
9674 ADVERTISED_Autoneg
);
9675 tp
->link_config
.speed
= SPEED_INVALID
;
9676 tp
->link_config
.duplex
= DUPLEX_INVALID
;
9678 tp
->link_config
.advertising
= 0;
9679 tp
->link_config
.speed
= cmd
->speed
;
9680 tp
->link_config
.duplex
= cmd
->duplex
;
9683 tp
->link_config
.orig_speed
= tp
->link_config
.speed
;
9684 tp
->link_config
.orig_duplex
= tp
->link_config
.duplex
;
9685 tp
->link_config
.orig_autoneg
= tp
->link_config
.autoneg
;
9687 if (netif_running(dev
))
9688 tg3_setup_phy(tp
, 1);
9690 tg3_full_unlock(tp
);
9695 static void tg3_get_drvinfo(struct net_device
*dev
, struct ethtool_drvinfo
*info
)
9697 struct tg3
*tp
= netdev_priv(dev
);
9699 strcpy(info
->driver
, DRV_MODULE_NAME
);
9700 strcpy(info
->version
, DRV_MODULE_VERSION
);
9701 strcpy(info
->fw_version
, tp
->fw_ver
);
9702 strcpy(info
->bus_info
, pci_name(tp
->pdev
));
9705 static void tg3_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
9707 struct tg3
*tp
= netdev_priv(dev
);
9709 if ((tp
->tg3_flags
& TG3_FLAG_WOL_CAP
) &&
9710 device_can_wakeup(&tp
->pdev
->dev
))
9711 wol
->supported
= WAKE_MAGIC
;
9715 if ((tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
) &&
9716 device_can_wakeup(&tp
->pdev
->dev
))
9717 wol
->wolopts
= WAKE_MAGIC
;
9718 memset(&wol
->sopass
, 0, sizeof(wol
->sopass
));
9721 static int tg3_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
9723 struct tg3
*tp
= netdev_priv(dev
);
9724 struct device
*dp
= &tp
->pdev
->dev
;
9726 if (wol
->wolopts
& ~WAKE_MAGIC
)
9728 if ((wol
->wolopts
& WAKE_MAGIC
) &&
9729 !((tp
->tg3_flags
& TG3_FLAG_WOL_CAP
) && device_can_wakeup(dp
)))
9732 spin_lock_bh(&tp
->lock
);
9733 if (wol
->wolopts
& WAKE_MAGIC
) {
9734 tp
->tg3_flags
|= TG3_FLAG_WOL_ENABLE
;
9735 device_set_wakeup_enable(dp
, true);
9737 tp
->tg3_flags
&= ~TG3_FLAG_WOL_ENABLE
;
9738 device_set_wakeup_enable(dp
, false);
9740 spin_unlock_bh(&tp
->lock
);
9745 static u32
tg3_get_msglevel(struct net_device
*dev
)
9747 struct tg3
*tp
= netdev_priv(dev
);
9748 return tp
->msg_enable
;
9751 static void tg3_set_msglevel(struct net_device
*dev
, u32 value
)
9753 struct tg3
*tp
= netdev_priv(dev
);
9754 tp
->msg_enable
= value
;
9757 static int tg3_set_tso(struct net_device
*dev
, u32 value
)
9759 struct tg3
*tp
= netdev_priv(dev
);
9761 if (!(tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
)) {
9766 if ((dev
->features
& NETIF_F_IPV6_CSUM
) &&
9767 ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO_2
) ||
9768 (tp
->tg3_flags2
& TG3_FLG2_HW_TSO_3
))) {
9770 dev
->features
|= NETIF_F_TSO6
;
9771 if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO_3
) ||
9772 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
9773 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
9774 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
) ||
9775 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
9776 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
9777 dev
->features
|= NETIF_F_TSO_ECN
;
9779 dev
->features
&= ~(NETIF_F_TSO6
| NETIF_F_TSO_ECN
);
9781 return ethtool_op_set_tso(dev
, value
);
9784 static int tg3_nway_reset(struct net_device
*dev
)
9786 struct tg3
*tp
= netdev_priv(dev
);
9789 if (!netif_running(dev
))
9792 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)
9795 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
9796 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
9798 r
= phy_start_aneg(tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
]);
9802 spin_lock_bh(&tp
->lock
);
9804 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
9805 if (!tg3_readphy(tp
, MII_BMCR
, &bmcr
) &&
9806 ((bmcr
& BMCR_ANENABLE
) ||
9807 (tp
->tg3_flags2
& TG3_FLG2_PARALLEL_DETECT
))) {
9808 tg3_writephy(tp
, MII_BMCR
, bmcr
| BMCR_ANRESTART
|
9812 spin_unlock_bh(&tp
->lock
);
9818 static void tg3_get_ringparam(struct net_device
*dev
, struct ethtool_ringparam
*ering
)
9820 struct tg3
*tp
= netdev_priv(dev
);
9822 ering
->rx_max_pending
= TG3_RX_RING_SIZE
- 1;
9823 ering
->rx_mini_max_pending
= 0;
9824 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
)
9825 ering
->rx_jumbo_max_pending
= TG3_RX_JUMBO_RING_SIZE
- 1;
9827 ering
->rx_jumbo_max_pending
= 0;
9829 ering
->tx_max_pending
= TG3_TX_RING_SIZE
- 1;
9831 ering
->rx_pending
= tp
->rx_pending
;
9832 ering
->rx_mini_pending
= 0;
9833 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
)
9834 ering
->rx_jumbo_pending
= tp
->rx_jumbo_pending
;
9836 ering
->rx_jumbo_pending
= 0;
9838 ering
->tx_pending
= tp
->napi
[0].tx_pending
;
9841 static int tg3_set_ringparam(struct net_device
*dev
, struct ethtool_ringparam
*ering
)
9843 struct tg3
*tp
= netdev_priv(dev
);
9844 int i
, irq_sync
= 0, err
= 0;
9846 if ((ering
->rx_pending
> TG3_RX_RING_SIZE
- 1) ||
9847 (ering
->rx_jumbo_pending
> TG3_RX_JUMBO_RING_SIZE
- 1) ||
9848 (ering
->tx_pending
> TG3_TX_RING_SIZE
- 1) ||
9849 (ering
->tx_pending
<= MAX_SKB_FRAGS
) ||
9850 ((tp
->tg3_flags2
& TG3_FLG2_TSO_BUG
) &&
9851 (ering
->tx_pending
<= (MAX_SKB_FRAGS
* 3))))
9854 if (netif_running(dev
)) {
9860 tg3_full_lock(tp
, irq_sync
);
9862 tp
->rx_pending
= ering
->rx_pending
;
9864 if ((tp
->tg3_flags2
& TG3_FLG2_MAX_RXPEND_64
) &&
9865 tp
->rx_pending
> 63)
9866 tp
->rx_pending
= 63;
9867 tp
->rx_jumbo_pending
= ering
->rx_jumbo_pending
;
9869 for (i
= 0; i
< TG3_IRQ_MAX_VECS
; i
++)
9870 tp
->napi
[i
].tx_pending
= ering
->tx_pending
;
9872 if (netif_running(dev
)) {
9873 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
9874 err
= tg3_restart_hw(tp
, 1);
9876 tg3_netif_start(tp
);
9879 tg3_full_unlock(tp
);
9881 if (irq_sync
&& !err
)
9887 static void tg3_get_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
*epause
)
9889 struct tg3
*tp
= netdev_priv(dev
);
9891 epause
->autoneg
= (tp
->tg3_flags
& TG3_FLAG_PAUSE_AUTONEG
) != 0;
9893 if (tp
->link_config
.active_flowctrl
& FLOW_CTRL_RX
)
9894 epause
->rx_pause
= 1;
9896 epause
->rx_pause
= 0;
9898 if (tp
->link_config
.active_flowctrl
& FLOW_CTRL_TX
)
9899 epause
->tx_pause
= 1;
9901 epause
->tx_pause
= 0;
9904 static int tg3_set_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
*epause
)
9906 struct tg3
*tp
= netdev_priv(dev
);
9909 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
9911 struct phy_device
*phydev
;
9913 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
9915 if (!(phydev
->supported
& SUPPORTED_Pause
) ||
9916 (!(phydev
->supported
& SUPPORTED_Asym_Pause
) &&
9917 ((epause
->rx_pause
&& !epause
->tx_pause
) ||
9918 (!epause
->rx_pause
&& epause
->tx_pause
))))
9921 tp
->link_config
.flowctrl
= 0;
9922 if (epause
->rx_pause
) {
9923 tp
->link_config
.flowctrl
|= FLOW_CTRL_RX
;
9925 if (epause
->tx_pause
) {
9926 tp
->link_config
.flowctrl
|= FLOW_CTRL_TX
;
9927 newadv
= ADVERTISED_Pause
;
9929 newadv
= ADVERTISED_Pause
|
9930 ADVERTISED_Asym_Pause
;
9931 } else if (epause
->tx_pause
) {
9932 tp
->link_config
.flowctrl
|= FLOW_CTRL_TX
;
9933 newadv
= ADVERTISED_Asym_Pause
;
9937 if (epause
->autoneg
)
9938 tp
->tg3_flags
|= TG3_FLAG_PAUSE_AUTONEG
;
9940 tp
->tg3_flags
&= ~TG3_FLAG_PAUSE_AUTONEG
;
9942 if (tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
) {
9943 u32 oldadv
= phydev
->advertising
&
9944 (ADVERTISED_Pause
| ADVERTISED_Asym_Pause
);
9945 if (oldadv
!= newadv
) {
9946 phydev
->advertising
&=
9947 ~(ADVERTISED_Pause
|
9948 ADVERTISED_Asym_Pause
);
9949 phydev
->advertising
|= newadv
;
9950 if (phydev
->autoneg
) {
9952 * Always renegotiate the link to
9953 * inform our link partner of our
9954 * flow control settings, even if the
9955 * flow control is forced. Let
9956 * tg3_adjust_link() do the final
9957 * flow control setup.
9959 return phy_start_aneg(phydev
);
9963 if (!epause
->autoneg
)
9964 tg3_setup_flow_control(tp
, 0, 0);
9966 tp
->link_config
.orig_advertising
&=
9967 ~(ADVERTISED_Pause
|
9968 ADVERTISED_Asym_Pause
);
9969 tp
->link_config
.orig_advertising
|= newadv
;
9974 if (netif_running(dev
)) {
9979 tg3_full_lock(tp
, irq_sync
);
9981 if (epause
->autoneg
)
9982 tp
->tg3_flags
|= TG3_FLAG_PAUSE_AUTONEG
;
9984 tp
->tg3_flags
&= ~TG3_FLAG_PAUSE_AUTONEG
;
9985 if (epause
->rx_pause
)
9986 tp
->link_config
.flowctrl
|= FLOW_CTRL_RX
;
9988 tp
->link_config
.flowctrl
&= ~FLOW_CTRL_RX
;
9989 if (epause
->tx_pause
)
9990 tp
->link_config
.flowctrl
|= FLOW_CTRL_TX
;
9992 tp
->link_config
.flowctrl
&= ~FLOW_CTRL_TX
;
9994 if (netif_running(dev
)) {
9995 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
9996 err
= tg3_restart_hw(tp
, 1);
9998 tg3_netif_start(tp
);
10001 tg3_full_unlock(tp
);
10007 static u32
tg3_get_rx_csum(struct net_device
*dev
)
10009 struct tg3
*tp
= netdev_priv(dev
);
10010 return (tp
->tg3_flags
& TG3_FLAG_RX_CHECKSUMS
) != 0;
10013 static int tg3_set_rx_csum(struct net_device
*dev
, u32 data
)
10015 struct tg3
*tp
= netdev_priv(dev
);
10017 if (tp
->tg3_flags
& TG3_FLAG_BROKEN_CHECKSUMS
) {
10023 spin_lock_bh(&tp
->lock
);
10025 tp
->tg3_flags
|= TG3_FLAG_RX_CHECKSUMS
;
10027 tp
->tg3_flags
&= ~TG3_FLAG_RX_CHECKSUMS
;
10028 spin_unlock_bh(&tp
->lock
);
10033 static int tg3_set_tx_csum(struct net_device
*dev
, u32 data
)
10035 struct tg3
*tp
= netdev_priv(dev
);
10037 if (tp
->tg3_flags
& TG3_FLAG_BROKEN_CHECKSUMS
) {
10043 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
10044 ethtool_op_set_tx_ipv6_csum(dev
, data
);
10046 ethtool_op_set_tx_csum(dev
, data
);
10051 static int tg3_get_sset_count(struct net_device
*dev
, int sset
)
10055 return TG3_NUM_TEST
;
10057 return TG3_NUM_STATS
;
10059 return -EOPNOTSUPP
;
10063 static void tg3_get_strings(struct net_device
*dev
, u32 stringset
, u8
*buf
)
10065 switch (stringset
) {
10067 memcpy(buf
, ðtool_stats_keys
, sizeof(ethtool_stats_keys
));
10070 memcpy(buf
, ðtool_test_keys
, sizeof(ethtool_test_keys
));
10073 WARN_ON(1); /* we need a WARN() */
10078 static int tg3_phys_id(struct net_device
*dev
, u32 data
)
10080 struct tg3
*tp
= netdev_priv(dev
);
10083 if (!netif_running(tp
->dev
))
10087 data
= UINT_MAX
/ 2;
10089 for (i
= 0; i
< (data
* 2); i
++) {
10091 tw32(MAC_LED_CTRL
, LED_CTRL_LNKLED_OVERRIDE
|
10092 LED_CTRL_1000MBPS_ON
|
10093 LED_CTRL_100MBPS_ON
|
10094 LED_CTRL_10MBPS_ON
|
10095 LED_CTRL_TRAFFIC_OVERRIDE
|
10096 LED_CTRL_TRAFFIC_BLINK
|
10097 LED_CTRL_TRAFFIC_LED
);
10100 tw32(MAC_LED_CTRL
, LED_CTRL_LNKLED_OVERRIDE
|
10101 LED_CTRL_TRAFFIC_OVERRIDE
);
10103 if (msleep_interruptible(500))
10106 tw32(MAC_LED_CTRL
, tp
->led_ctrl
);
10110 static void tg3_get_ethtool_stats(struct net_device
*dev
,
10111 struct ethtool_stats
*estats
, u64
*tmp_stats
)
10113 struct tg3
*tp
= netdev_priv(dev
);
10114 memcpy(tmp_stats
, tg3_get_estats(tp
), sizeof(tp
->estats
));
10117 #define NVRAM_TEST_SIZE 0x100
10118 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
10119 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
10120 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
10121 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10122 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10124 static int tg3_test_nvram(struct tg3
*tp
)
10128 int i
, j
, k
, err
= 0, size
;
10130 if (tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
)
10133 if (tg3_nvram_read(tp
, 0, &magic
) != 0)
10136 if (magic
== TG3_EEPROM_MAGIC
)
10137 size
= NVRAM_TEST_SIZE
;
10138 else if ((magic
& TG3_EEPROM_MAGIC_FW_MSK
) == TG3_EEPROM_MAGIC_FW
) {
10139 if ((magic
& TG3_EEPROM_SB_FORMAT_MASK
) ==
10140 TG3_EEPROM_SB_FORMAT_1
) {
10141 switch (magic
& TG3_EEPROM_SB_REVISION_MASK
) {
10142 case TG3_EEPROM_SB_REVISION_0
:
10143 size
= NVRAM_SELFBOOT_FORMAT1_0_SIZE
;
10145 case TG3_EEPROM_SB_REVISION_2
:
10146 size
= NVRAM_SELFBOOT_FORMAT1_2_SIZE
;
10148 case TG3_EEPROM_SB_REVISION_3
:
10149 size
= NVRAM_SELFBOOT_FORMAT1_3_SIZE
;
10156 } else if ((magic
& TG3_EEPROM_MAGIC_HW_MSK
) == TG3_EEPROM_MAGIC_HW
)
10157 size
= NVRAM_SELFBOOT_HW_SIZE
;
10161 buf
= kmalloc(size
, GFP_KERNEL
);
10166 for (i
= 0, j
= 0; i
< size
; i
+= 4, j
++) {
10167 err
= tg3_nvram_read_be32(tp
, i
, &buf
[j
]);
10174 /* Selfboot format */
10175 magic
= be32_to_cpu(buf
[0]);
10176 if ((magic
& TG3_EEPROM_MAGIC_FW_MSK
) ==
10177 TG3_EEPROM_MAGIC_FW
) {
10178 u8
*buf8
= (u8
*) buf
, csum8
= 0;
10180 if ((magic
& TG3_EEPROM_SB_REVISION_MASK
) ==
10181 TG3_EEPROM_SB_REVISION_2
) {
10182 /* For rev 2, the csum doesn't include the MBA. */
10183 for (i
= 0; i
< TG3_EEPROM_SB_F1R2_MBA_OFF
; i
++)
10185 for (i
= TG3_EEPROM_SB_F1R2_MBA_OFF
+ 4; i
< size
; i
++)
10188 for (i
= 0; i
< size
; i
++)
10201 if ((magic
& TG3_EEPROM_MAGIC_HW_MSK
) ==
10202 TG3_EEPROM_MAGIC_HW
) {
10203 u8 data
[NVRAM_SELFBOOT_DATA_SIZE
];
10204 u8 parity
[NVRAM_SELFBOOT_DATA_SIZE
];
10205 u8
*buf8
= (u8
*) buf
;
10207 /* Separate the parity bits and the data bytes. */
10208 for (i
= 0, j
= 0, k
= 0; i
< NVRAM_SELFBOOT_HW_SIZE
; i
++) {
10209 if ((i
== 0) || (i
== 8)) {
10213 for (l
= 0, msk
= 0x80; l
< 7; l
++, msk
>>= 1)
10214 parity
[k
++] = buf8
[i
] & msk
;
10216 } else if (i
== 16) {
10220 for (l
= 0, msk
= 0x20; l
< 6; l
++, msk
>>= 1)
10221 parity
[k
++] = buf8
[i
] & msk
;
10224 for (l
= 0, msk
= 0x80; l
< 8; l
++, msk
>>= 1)
10225 parity
[k
++] = buf8
[i
] & msk
;
10228 data
[j
++] = buf8
[i
];
10232 for (i
= 0; i
< NVRAM_SELFBOOT_DATA_SIZE
; i
++) {
10233 u8 hw8
= hweight8(data
[i
]);
10235 if ((hw8
& 0x1) && parity
[i
])
10237 else if (!(hw8
& 0x1) && !parity
[i
])
10244 /* Bootstrap checksum at offset 0x10 */
10245 csum
= calc_crc((unsigned char *) buf
, 0x10);
10246 if (csum
!= be32_to_cpu(buf
[0x10/4]))
10249 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10250 csum
= calc_crc((unsigned char *) &buf
[0x74/4], 0x88);
10251 if (csum
!= be32_to_cpu(buf
[0xfc/4]))
10261 #define TG3_SERDES_TIMEOUT_SEC 2
10262 #define TG3_COPPER_TIMEOUT_SEC 6
10264 static int tg3_test_link(struct tg3
*tp
)
10268 if (!netif_running(tp
->dev
))
10271 if (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
)
10272 max
= TG3_SERDES_TIMEOUT_SEC
;
10274 max
= TG3_COPPER_TIMEOUT_SEC
;
10276 for (i
= 0; i
< max
; i
++) {
10277 if (netif_carrier_ok(tp
->dev
))
10280 if (msleep_interruptible(1000))
10287 /* Only test the commonly used registers */
10288 static int tg3_test_registers(struct tg3
*tp
)
10290 int i
, is_5705
, is_5750
;
10291 u32 offset
, read_mask
, write_mask
, val
, save_val
, read_val
;
10295 #define TG3_FL_5705 0x1
10296 #define TG3_FL_NOT_5705 0x2
10297 #define TG3_FL_NOT_5788 0x4
10298 #define TG3_FL_NOT_5750 0x8
10302 /* MAC Control Registers */
10303 { MAC_MODE
, TG3_FL_NOT_5705
,
10304 0x00000000, 0x00ef6f8c },
10305 { MAC_MODE
, TG3_FL_5705
,
10306 0x00000000, 0x01ef6b8c },
10307 { MAC_STATUS
, TG3_FL_NOT_5705
,
10308 0x03800107, 0x00000000 },
10309 { MAC_STATUS
, TG3_FL_5705
,
10310 0x03800100, 0x00000000 },
10311 { MAC_ADDR_0_HIGH
, 0x0000,
10312 0x00000000, 0x0000ffff },
10313 { MAC_ADDR_0_LOW
, 0x0000,
10314 0x00000000, 0xffffffff },
10315 { MAC_RX_MTU_SIZE
, 0x0000,
10316 0x00000000, 0x0000ffff },
10317 { MAC_TX_MODE
, 0x0000,
10318 0x00000000, 0x00000070 },
10319 { MAC_TX_LENGTHS
, 0x0000,
10320 0x00000000, 0x00003fff },
10321 { MAC_RX_MODE
, TG3_FL_NOT_5705
,
10322 0x00000000, 0x000007fc },
10323 { MAC_RX_MODE
, TG3_FL_5705
,
10324 0x00000000, 0x000007dc },
10325 { MAC_HASH_REG_0
, 0x0000,
10326 0x00000000, 0xffffffff },
10327 { MAC_HASH_REG_1
, 0x0000,
10328 0x00000000, 0xffffffff },
10329 { MAC_HASH_REG_2
, 0x0000,
10330 0x00000000, 0xffffffff },
10331 { MAC_HASH_REG_3
, 0x0000,
10332 0x00000000, 0xffffffff },
10334 /* Receive Data and Receive BD Initiator Control Registers. */
10335 { RCVDBDI_JUMBO_BD
+0, TG3_FL_NOT_5705
,
10336 0x00000000, 0xffffffff },
10337 { RCVDBDI_JUMBO_BD
+4, TG3_FL_NOT_5705
,
10338 0x00000000, 0xffffffff },
10339 { RCVDBDI_JUMBO_BD
+8, TG3_FL_NOT_5705
,
10340 0x00000000, 0x00000003 },
10341 { RCVDBDI_JUMBO_BD
+0xc, TG3_FL_NOT_5705
,
10342 0x00000000, 0xffffffff },
10343 { RCVDBDI_STD_BD
+0, 0x0000,
10344 0x00000000, 0xffffffff },
10345 { RCVDBDI_STD_BD
+4, 0x0000,
10346 0x00000000, 0xffffffff },
10347 { RCVDBDI_STD_BD
+8, 0x0000,
10348 0x00000000, 0xffff0002 },
10349 { RCVDBDI_STD_BD
+0xc, 0x0000,
10350 0x00000000, 0xffffffff },
10352 /* Receive BD Initiator Control Registers. */
10353 { RCVBDI_STD_THRESH
, TG3_FL_NOT_5705
,
10354 0x00000000, 0xffffffff },
10355 { RCVBDI_STD_THRESH
, TG3_FL_5705
,
10356 0x00000000, 0x000003ff },
10357 { RCVBDI_JUMBO_THRESH
, TG3_FL_NOT_5705
,
10358 0x00000000, 0xffffffff },
10360 /* Host Coalescing Control Registers. */
10361 { HOSTCC_MODE
, TG3_FL_NOT_5705
,
10362 0x00000000, 0x00000004 },
10363 { HOSTCC_MODE
, TG3_FL_5705
,
10364 0x00000000, 0x000000f6 },
10365 { HOSTCC_RXCOL_TICKS
, TG3_FL_NOT_5705
,
10366 0x00000000, 0xffffffff },
10367 { HOSTCC_RXCOL_TICKS
, TG3_FL_5705
,
10368 0x00000000, 0x000003ff },
10369 { HOSTCC_TXCOL_TICKS
, TG3_FL_NOT_5705
,
10370 0x00000000, 0xffffffff },
10371 { HOSTCC_TXCOL_TICKS
, TG3_FL_5705
,
10372 0x00000000, 0x000003ff },
10373 { HOSTCC_RXMAX_FRAMES
, TG3_FL_NOT_5705
,
10374 0x00000000, 0xffffffff },
10375 { HOSTCC_RXMAX_FRAMES
, TG3_FL_5705
| TG3_FL_NOT_5788
,
10376 0x00000000, 0x000000ff },
10377 { HOSTCC_TXMAX_FRAMES
, TG3_FL_NOT_5705
,
10378 0x00000000, 0xffffffff },
10379 { HOSTCC_TXMAX_FRAMES
, TG3_FL_5705
| TG3_FL_NOT_5788
,
10380 0x00000000, 0x000000ff },
10381 { HOSTCC_RXCOAL_TICK_INT
, TG3_FL_NOT_5705
,
10382 0x00000000, 0xffffffff },
10383 { HOSTCC_TXCOAL_TICK_INT
, TG3_FL_NOT_5705
,
10384 0x00000000, 0xffffffff },
10385 { HOSTCC_RXCOAL_MAXF_INT
, TG3_FL_NOT_5705
,
10386 0x00000000, 0xffffffff },
10387 { HOSTCC_RXCOAL_MAXF_INT
, TG3_FL_5705
| TG3_FL_NOT_5788
,
10388 0x00000000, 0x000000ff },
10389 { HOSTCC_TXCOAL_MAXF_INT
, TG3_FL_NOT_5705
,
10390 0x00000000, 0xffffffff },
10391 { HOSTCC_TXCOAL_MAXF_INT
, TG3_FL_5705
| TG3_FL_NOT_5788
,
10392 0x00000000, 0x000000ff },
10393 { HOSTCC_STAT_COAL_TICKS
, TG3_FL_NOT_5705
,
10394 0x00000000, 0xffffffff },
10395 { HOSTCC_STATS_BLK_HOST_ADDR
, TG3_FL_NOT_5705
,
10396 0x00000000, 0xffffffff },
10397 { HOSTCC_STATS_BLK_HOST_ADDR
+4, TG3_FL_NOT_5705
,
10398 0x00000000, 0xffffffff },
10399 { HOSTCC_STATUS_BLK_HOST_ADDR
, 0x0000,
10400 0x00000000, 0xffffffff },
10401 { HOSTCC_STATUS_BLK_HOST_ADDR
+4, 0x0000,
10402 0x00000000, 0xffffffff },
10403 { HOSTCC_STATS_BLK_NIC_ADDR
, 0x0000,
10404 0xffffffff, 0x00000000 },
10405 { HOSTCC_STATUS_BLK_NIC_ADDR
, 0x0000,
10406 0xffffffff, 0x00000000 },
10408 /* Buffer Manager Control Registers. */
10409 { BUFMGR_MB_POOL_ADDR
, TG3_FL_NOT_5750
,
10410 0x00000000, 0x007fff80 },
10411 { BUFMGR_MB_POOL_SIZE
, TG3_FL_NOT_5750
,
10412 0x00000000, 0x007fffff },
10413 { BUFMGR_MB_RDMA_LOW_WATER
, 0x0000,
10414 0x00000000, 0x0000003f },
10415 { BUFMGR_MB_MACRX_LOW_WATER
, 0x0000,
10416 0x00000000, 0x000001ff },
10417 { BUFMGR_MB_HIGH_WATER
, 0x0000,
10418 0x00000000, 0x000001ff },
10419 { BUFMGR_DMA_DESC_POOL_ADDR
, TG3_FL_NOT_5705
,
10420 0xffffffff, 0x00000000 },
10421 { BUFMGR_DMA_DESC_POOL_SIZE
, TG3_FL_NOT_5705
,
10422 0xffffffff, 0x00000000 },
10424 /* Mailbox Registers */
10425 { GRCMBOX_RCVSTD_PROD_IDX
+4, 0x0000,
10426 0x00000000, 0x000001ff },
10427 { GRCMBOX_RCVJUMBO_PROD_IDX
+4, TG3_FL_NOT_5705
,
10428 0x00000000, 0x000001ff },
10429 { GRCMBOX_RCVRET_CON_IDX_0
+4, 0x0000,
10430 0x00000000, 0x000007ff },
10431 { GRCMBOX_SNDHOST_PROD_IDX_0
+4, 0x0000,
10432 0x00000000, 0x000001ff },
10434 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10437 is_5705
= is_5750
= 0;
10438 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
10440 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
10444 for (i
= 0; reg_tbl
[i
].offset
!= 0xffff; i
++) {
10445 if (is_5705
&& (reg_tbl
[i
].flags
& TG3_FL_NOT_5705
))
10448 if (!is_5705
&& (reg_tbl
[i
].flags
& TG3_FL_5705
))
10451 if ((tp
->tg3_flags2
& TG3_FLG2_IS_5788
) &&
10452 (reg_tbl
[i
].flags
& TG3_FL_NOT_5788
))
10455 if (is_5750
&& (reg_tbl
[i
].flags
& TG3_FL_NOT_5750
))
10458 offset
= (u32
) reg_tbl
[i
].offset
;
10459 read_mask
= reg_tbl
[i
].read_mask
;
10460 write_mask
= reg_tbl
[i
].write_mask
;
10462 /* Save the original register content */
10463 save_val
= tr32(offset
);
10465 /* Determine the read-only value. */
10466 read_val
= save_val
& read_mask
;
10468 /* Write zero to the register, then make sure the read-only bits
10469 * are not changed and the read/write bits are all zeros.
10473 val
= tr32(offset
);
10475 /* Test the read-only and read/write bits. */
10476 if (((val
& read_mask
) != read_val
) || (val
& write_mask
))
10479 /* Write ones to all the bits defined by RdMask and WrMask, then
10480 * make sure the read-only bits are not changed and the
10481 * read/write bits are all ones.
10483 tw32(offset
, read_mask
| write_mask
);
10485 val
= tr32(offset
);
10487 /* Test the read-only bits. */
10488 if ((val
& read_mask
) != read_val
)
10491 /* Test the read/write bits. */
10492 if ((val
& write_mask
) != write_mask
)
10495 tw32(offset
, save_val
);
10501 if (netif_msg_hw(tp
))
10502 netdev_err(tp
->dev
,
10503 "Register test failed at offset %x\n", offset
);
10504 tw32(offset
, save_val
);
10508 static int tg3_do_mem_test(struct tg3
*tp
, u32 offset
, u32 len
)
10510 static const u32 test_pattern
[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10514 for (i
= 0; i
< ARRAY_SIZE(test_pattern
); i
++) {
10515 for (j
= 0; j
< len
; j
+= 4) {
10518 tg3_write_mem(tp
, offset
+ j
, test_pattern
[i
]);
10519 tg3_read_mem(tp
, offset
+ j
, &val
);
10520 if (val
!= test_pattern
[i
])
10527 static int tg3_test_memory(struct tg3
*tp
)
10529 static struct mem_entry
{
10532 } mem_tbl_570x
[] = {
10533 { 0x00000000, 0x00b50},
10534 { 0x00002000, 0x1c000},
10535 { 0xffffffff, 0x00000}
10536 }, mem_tbl_5705
[] = {
10537 { 0x00000100, 0x0000c},
10538 { 0x00000200, 0x00008},
10539 { 0x00004000, 0x00800},
10540 { 0x00006000, 0x01000},
10541 { 0x00008000, 0x02000},
10542 { 0x00010000, 0x0e000},
10543 { 0xffffffff, 0x00000}
10544 }, mem_tbl_5755
[] = {
10545 { 0x00000200, 0x00008},
10546 { 0x00004000, 0x00800},
10547 { 0x00006000, 0x00800},
10548 { 0x00008000, 0x02000},
10549 { 0x00010000, 0x0c000},
10550 { 0xffffffff, 0x00000}
10551 }, mem_tbl_5906
[] = {
10552 { 0x00000200, 0x00008},
10553 { 0x00004000, 0x00400},
10554 { 0x00006000, 0x00400},
10555 { 0x00008000, 0x01000},
10556 { 0x00010000, 0x01000},
10557 { 0xffffffff, 0x00000}
10558 }, mem_tbl_5717
[] = {
10559 { 0x00000200, 0x00008},
10560 { 0x00010000, 0x0a000},
10561 { 0x00020000, 0x13c00},
10562 { 0xffffffff, 0x00000}
10563 }, mem_tbl_57765
[] = {
10564 { 0x00000200, 0x00008},
10565 { 0x00004000, 0x00800},
10566 { 0x00006000, 0x09800},
10567 { 0x00010000, 0x0a000},
10568 { 0xffffffff, 0x00000}
10570 struct mem_entry
*mem_tbl
;
10574 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
10575 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
)
10576 mem_tbl
= mem_tbl_5717
;
10577 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
10578 mem_tbl
= mem_tbl_57765
;
10579 else if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
10580 mem_tbl
= mem_tbl_5755
;
10581 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
10582 mem_tbl
= mem_tbl_5906
;
10583 else if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
10584 mem_tbl
= mem_tbl_5705
;
10586 mem_tbl
= mem_tbl_570x
;
10588 for (i
= 0; mem_tbl
[i
].offset
!= 0xffffffff; i
++) {
10589 err
= tg3_do_mem_test(tp
, mem_tbl
[i
].offset
, mem_tbl
[i
].len
);
10597 #define TG3_MAC_LOOPBACK 0
10598 #define TG3_PHY_LOOPBACK 1
10600 static int tg3_run_loopback(struct tg3
*tp
, int loopback_mode
)
10602 u32 mac_mode
, rx_start_idx
, rx_idx
, tx_idx
, opaque_key
;
10603 u32 desc_idx
, coal_now
;
10604 struct sk_buff
*skb
, *rx_skb
;
10607 int num_pkts
, tx_len
, rx_len
, i
, err
;
10608 struct tg3_rx_buffer_desc
*desc
;
10609 struct tg3_napi
*tnapi
, *rnapi
;
10610 struct tg3_rx_prodring_set
*tpr
= &tp
->prodring
[0];
10612 tnapi
= &tp
->napi
[0];
10613 rnapi
= &tp
->napi
[0];
10614 if (tp
->irq_cnt
> 1) {
10615 rnapi
= &tp
->napi
[1];
10616 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)
10617 tnapi
= &tp
->napi
[1];
10619 coal_now
= tnapi
->coal_now
| rnapi
->coal_now
;
10621 if (loopback_mode
== TG3_MAC_LOOPBACK
) {
10622 /* HW errata - mac loopback fails in some cases on 5780.
10623 * Normal traffic and PHY loopback are not affected by
10626 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5780
)
10629 mac_mode
= (tp
->mac_mode
& ~MAC_MODE_PORT_MODE_MASK
) |
10630 MAC_MODE_PORT_INT_LPBACK
;
10631 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
10632 mac_mode
|= MAC_MODE_LINK_POLARITY
;
10633 if (tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)
10634 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
10636 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
10637 tw32(MAC_MODE
, mac_mode
);
10638 } else if (loopback_mode
== TG3_PHY_LOOPBACK
) {
10641 if (tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
) {
10642 tg3_phy_fet_toggle_apd(tp
, false);
10643 val
= BMCR_LOOPBACK
| BMCR_FULLDPLX
| BMCR_SPEED100
;
10645 val
= BMCR_LOOPBACK
| BMCR_FULLDPLX
| BMCR_SPEED1000
;
10647 tg3_phy_toggle_automdix(tp
, 0);
10649 tg3_writephy(tp
, MII_BMCR
, val
);
10652 mac_mode
= tp
->mac_mode
& ~MAC_MODE_PORT_MODE_MASK
;
10653 if (tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
) {
10654 tg3_writephy(tp
, MII_TG3_FET_PTEST
,
10655 MII_TG3_FET_PTEST_FRC_TX_LINK
|
10656 MII_TG3_FET_PTEST_FRC_TX_LOCK
);
10657 /* The write needs to be flushed for the AC131 */
10658 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
10659 tg3_readphy(tp
, MII_TG3_FET_PTEST
, &val
);
10660 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
10662 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
10664 /* reset to prevent losing 1st rx packet intermittently */
10665 if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
) {
10666 tw32_f(MAC_RX_MODE
, RX_MODE_RESET
);
10668 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
10670 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) {
10671 u32 masked_phy_id
= tp
->phy_id
& TG3_PHY_ID_MASK
;
10672 if (masked_phy_id
== TG3_PHY_ID_BCM5401
)
10673 mac_mode
&= ~MAC_MODE_LINK_POLARITY
;
10674 else if (masked_phy_id
== TG3_PHY_ID_BCM5411
)
10675 mac_mode
|= MAC_MODE_LINK_POLARITY
;
10676 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
10677 MII_TG3_EXT_CTRL_LNK3_LED_MODE
);
10679 tw32(MAC_MODE
, mac_mode
);
10687 skb
= netdev_alloc_skb(tp
->dev
, tx_len
);
10691 tx_data
= skb_put(skb
, tx_len
);
10692 memcpy(tx_data
, tp
->dev
->dev_addr
, 6);
10693 memset(tx_data
+ 6, 0x0, 8);
10695 tw32(MAC_RX_MTU_SIZE
, tx_len
+ 4);
10697 for (i
= 14; i
< tx_len
; i
++)
10698 tx_data
[i
] = (u8
) (i
& 0xff);
10700 map
= pci_map_single(tp
->pdev
, skb
->data
, tx_len
, PCI_DMA_TODEVICE
);
10701 if (pci_dma_mapping_error(tp
->pdev
, map
)) {
10702 dev_kfree_skb(skb
);
10706 tw32_f(HOSTCC_MODE
, tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
|
10711 rx_start_idx
= rnapi
->hw_status
->idx
[0].rx_producer
;
10715 tg3_set_txd(tnapi
, tnapi
->tx_prod
, map
, tx_len
, 0, 1);
10720 tw32_tx_mbox(tnapi
->prodmbox
, tnapi
->tx_prod
);
10721 tr32_mailbox(tnapi
->prodmbox
);
10725 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
10726 for (i
= 0; i
< 35; i
++) {
10727 tw32_f(HOSTCC_MODE
, tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
|
10732 tx_idx
= tnapi
->hw_status
->idx
[0].tx_consumer
;
10733 rx_idx
= rnapi
->hw_status
->idx
[0].rx_producer
;
10734 if ((tx_idx
== tnapi
->tx_prod
) &&
10735 (rx_idx
== (rx_start_idx
+ num_pkts
)))
10739 pci_unmap_single(tp
->pdev
, map
, tx_len
, PCI_DMA_TODEVICE
);
10740 dev_kfree_skb(skb
);
10742 if (tx_idx
!= tnapi
->tx_prod
)
10745 if (rx_idx
!= rx_start_idx
+ num_pkts
)
10748 desc
= &rnapi
->rx_rcb
[rx_start_idx
];
10749 desc_idx
= desc
->opaque
& RXD_OPAQUE_INDEX_MASK
;
10750 opaque_key
= desc
->opaque
& RXD_OPAQUE_RING_MASK
;
10751 if (opaque_key
!= RXD_OPAQUE_RING_STD
)
10754 if ((desc
->err_vlan
& RXD_ERR_MASK
) != 0 &&
10755 (desc
->err_vlan
!= RXD_ERR_ODD_NIBBLE_RCVD_MII
))
10758 rx_len
= ((desc
->idx_len
& RXD_LEN_MASK
) >> RXD_LEN_SHIFT
) - 4;
10759 if (rx_len
!= tx_len
)
10762 rx_skb
= tpr
->rx_std_buffers
[desc_idx
].skb
;
10764 map
= dma_unmap_addr(&tpr
->rx_std_buffers
[desc_idx
], mapping
);
10765 pci_dma_sync_single_for_cpu(tp
->pdev
, map
, rx_len
, PCI_DMA_FROMDEVICE
);
10767 for (i
= 14; i
< tx_len
; i
++) {
10768 if (*(rx_skb
->data
+ i
) != (u8
) (i
& 0xff))
10773 /* tg3_free_rings will unmap and free the rx_skb */
10778 #define TG3_MAC_LOOPBACK_FAILED 1
10779 #define TG3_PHY_LOOPBACK_FAILED 2
10780 #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
10781 TG3_PHY_LOOPBACK_FAILED)
10783 static int tg3_test_loopback(struct tg3
*tp
)
10788 if (!netif_running(tp
->dev
))
10789 return TG3_LOOPBACK_FAILED
;
10791 err
= tg3_reset_hw(tp
, 1);
10793 return TG3_LOOPBACK_FAILED
;
10795 /* Turn off gphy autopowerdown. */
10796 if (tp
->tg3_flags3
& TG3_FLG3_PHY_ENABLE_APD
)
10797 tg3_phy_toggle_apd(tp
, false);
10799 if (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) {
10803 tw32(TG3_CPMU_MUTEX_REQ
, CPMU_MUTEX_REQ_DRIVER
);
10805 /* Wait for up to 40 microseconds to acquire lock. */
10806 for (i
= 0; i
< 4; i
++) {
10807 status
= tr32(TG3_CPMU_MUTEX_GNT
);
10808 if (status
== CPMU_MUTEX_GNT_DRIVER
)
10813 if (status
!= CPMU_MUTEX_GNT_DRIVER
)
10814 return TG3_LOOPBACK_FAILED
;
10816 /* Turn off link-based power management. */
10817 cpmuctrl
= tr32(TG3_CPMU_CTRL
);
10818 tw32(TG3_CPMU_CTRL
,
10819 cpmuctrl
& ~(CPMU_CTRL_LINK_SPEED_MODE
|
10820 CPMU_CTRL_LINK_AWARE_MODE
));
10823 if (tg3_run_loopback(tp
, TG3_MAC_LOOPBACK
))
10824 err
|= TG3_MAC_LOOPBACK_FAILED
;
10826 if (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) {
10827 tw32(TG3_CPMU_CTRL
, cpmuctrl
);
10829 /* Release the mutex */
10830 tw32(TG3_CPMU_MUTEX_GNT
, CPMU_MUTEX_GNT_DRIVER
);
10833 if (!(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) &&
10834 !(tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
)) {
10835 if (tg3_run_loopback(tp
, TG3_PHY_LOOPBACK
))
10836 err
|= TG3_PHY_LOOPBACK_FAILED
;
10839 /* Re-enable gphy autopowerdown. */
10840 if (tp
->tg3_flags3
& TG3_FLG3_PHY_ENABLE_APD
)
10841 tg3_phy_toggle_apd(tp
, true);
10846 static void tg3_self_test(struct net_device
*dev
, struct ethtool_test
*etest
,
10849 struct tg3
*tp
= netdev_priv(dev
);
10851 if (tp
->link_config
.phy_is_low_power
)
10852 tg3_set_power_state(tp
, PCI_D0
);
10854 memset(data
, 0, sizeof(u64
) * TG3_NUM_TEST
);
10856 if (tg3_test_nvram(tp
) != 0) {
10857 etest
->flags
|= ETH_TEST_FL_FAILED
;
10860 if (tg3_test_link(tp
) != 0) {
10861 etest
->flags
|= ETH_TEST_FL_FAILED
;
10864 if (etest
->flags
& ETH_TEST_FL_OFFLINE
) {
10865 int err
, err2
= 0, irq_sync
= 0;
10867 if (netif_running(dev
)) {
10869 tg3_netif_stop(tp
);
10873 tg3_full_lock(tp
, irq_sync
);
10875 tg3_halt(tp
, RESET_KIND_SUSPEND
, 1);
10876 err
= tg3_nvram_lock(tp
);
10877 tg3_halt_cpu(tp
, RX_CPU_BASE
);
10878 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
10879 tg3_halt_cpu(tp
, TX_CPU_BASE
);
10881 tg3_nvram_unlock(tp
);
10883 if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
)
10886 if (tg3_test_registers(tp
) != 0) {
10887 etest
->flags
|= ETH_TEST_FL_FAILED
;
10890 if (tg3_test_memory(tp
) != 0) {
10891 etest
->flags
|= ETH_TEST_FL_FAILED
;
10894 if ((data
[4] = tg3_test_loopback(tp
)) != 0)
10895 etest
->flags
|= ETH_TEST_FL_FAILED
;
10897 tg3_full_unlock(tp
);
10899 if (tg3_test_interrupt(tp
) != 0) {
10900 etest
->flags
|= ETH_TEST_FL_FAILED
;
10904 tg3_full_lock(tp
, 0);
10906 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
10907 if (netif_running(dev
)) {
10908 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
10909 err2
= tg3_restart_hw(tp
, 1);
10911 tg3_netif_start(tp
);
10914 tg3_full_unlock(tp
);
10916 if (irq_sync
&& !err2
)
10919 if (tp
->link_config
.phy_is_low_power
)
10920 tg3_set_power_state(tp
, PCI_D3hot
);
10924 static int tg3_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
10926 struct mii_ioctl_data
*data
= if_mii(ifr
);
10927 struct tg3
*tp
= netdev_priv(dev
);
10930 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
10931 struct phy_device
*phydev
;
10932 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
10934 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
10935 return phy_mii_ioctl(phydev
, ifr
, cmd
);
10940 data
->phy_id
= tp
->phy_addr
;
10943 case SIOCGMIIREG
: {
10946 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)
10947 break; /* We have no PHY */
10949 if (tp
->link_config
.phy_is_low_power
)
10952 spin_lock_bh(&tp
->lock
);
10953 err
= tg3_readphy(tp
, data
->reg_num
& 0x1f, &mii_regval
);
10954 spin_unlock_bh(&tp
->lock
);
10956 data
->val_out
= mii_regval
;
10962 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)
10963 break; /* We have no PHY */
10965 if (tp
->link_config
.phy_is_low_power
)
10968 spin_lock_bh(&tp
->lock
);
10969 err
= tg3_writephy(tp
, data
->reg_num
& 0x1f, data
->val_in
);
10970 spin_unlock_bh(&tp
->lock
);
10978 return -EOPNOTSUPP
;
10981 #if TG3_VLAN_TAG_USED
10982 static void tg3_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*grp
)
10984 struct tg3
*tp
= netdev_priv(dev
);
10986 if (!netif_running(dev
)) {
10991 tg3_netif_stop(tp
);
10993 tg3_full_lock(tp
, 0);
10997 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10998 __tg3_set_rx_mode(dev
);
11000 tg3_netif_start(tp
);
11002 tg3_full_unlock(tp
);
11006 static int tg3_get_coalesce(struct net_device
*dev
, struct ethtool_coalesce
*ec
)
11008 struct tg3
*tp
= netdev_priv(dev
);
11010 memcpy(ec
, &tp
->coal
, sizeof(*ec
));
11014 static int tg3_set_coalesce(struct net_device
*dev
, struct ethtool_coalesce
*ec
)
11016 struct tg3
*tp
= netdev_priv(dev
);
11017 u32 max_rxcoal_tick_int
= 0, max_txcoal_tick_int
= 0;
11018 u32 max_stat_coal_ticks
= 0, min_stat_coal_ticks
= 0;
11020 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
11021 max_rxcoal_tick_int
= MAX_RXCOAL_TICK_INT
;
11022 max_txcoal_tick_int
= MAX_TXCOAL_TICK_INT
;
11023 max_stat_coal_ticks
= MAX_STAT_COAL_TICKS
;
11024 min_stat_coal_ticks
= MIN_STAT_COAL_TICKS
;
11027 if ((ec
->rx_coalesce_usecs
> MAX_RXCOL_TICKS
) ||
11028 (ec
->tx_coalesce_usecs
> MAX_TXCOL_TICKS
) ||
11029 (ec
->rx_max_coalesced_frames
> MAX_RXMAX_FRAMES
) ||
11030 (ec
->tx_max_coalesced_frames
> MAX_TXMAX_FRAMES
) ||
11031 (ec
->rx_coalesce_usecs_irq
> max_rxcoal_tick_int
) ||
11032 (ec
->tx_coalesce_usecs_irq
> max_txcoal_tick_int
) ||
11033 (ec
->rx_max_coalesced_frames_irq
> MAX_RXCOAL_MAXF_INT
) ||
11034 (ec
->tx_max_coalesced_frames_irq
> MAX_TXCOAL_MAXF_INT
) ||
11035 (ec
->stats_block_coalesce_usecs
> max_stat_coal_ticks
) ||
11036 (ec
->stats_block_coalesce_usecs
< min_stat_coal_ticks
))
11039 /* No rx interrupts will be generated if both are zero */
11040 if ((ec
->rx_coalesce_usecs
== 0) &&
11041 (ec
->rx_max_coalesced_frames
== 0))
11044 /* No tx interrupts will be generated if both are zero */
11045 if ((ec
->tx_coalesce_usecs
== 0) &&
11046 (ec
->tx_max_coalesced_frames
== 0))
11049 /* Only copy relevant parameters, ignore all others. */
11050 tp
->coal
.rx_coalesce_usecs
= ec
->rx_coalesce_usecs
;
11051 tp
->coal
.tx_coalesce_usecs
= ec
->tx_coalesce_usecs
;
11052 tp
->coal
.rx_max_coalesced_frames
= ec
->rx_max_coalesced_frames
;
11053 tp
->coal
.tx_max_coalesced_frames
= ec
->tx_max_coalesced_frames
;
11054 tp
->coal
.rx_coalesce_usecs_irq
= ec
->rx_coalesce_usecs_irq
;
11055 tp
->coal
.tx_coalesce_usecs_irq
= ec
->tx_coalesce_usecs_irq
;
11056 tp
->coal
.rx_max_coalesced_frames_irq
= ec
->rx_max_coalesced_frames_irq
;
11057 tp
->coal
.tx_max_coalesced_frames_irq
= ec
->tx_max_coalesced_frames_irq
;
11058 tp
->coal
.stats_block_coalesce_usecs
= ec
->stats_block_coalesce_usecs
;
11060 if (netif_running(dev
)) {
11061 tg3_full_lock(tp
, 0);
11062 __tg3_set_coalesce(tp
, &tp
->coal
);
11063 tg3_full_unlock(tp
);
11068 static const struct ethtool_ops tg3_ethtool_ops
= {
11069 .get_settings
= tg3_get_settings
,
11070 .set_settings
= tg3_set_settings
,
11071 .get_drvinfo
= tg3_get_drvinfo
,
11072 .get_regs_len
= tg3_get_regs_len
,
11073 .get_regs
= tg3_get_regs
,
11074 .get_wol
= tg3_get_wol
,
11075 .set_wol
= tg3_set_wol
,
11076 .get_msglevel
= tg3_get_msglevel
,
11077 .set_msglevel
= tg3_set_msglevel
,
11078 .nway_reset
= tg3_nway_reset
,
11079 .get_link
= ethtool_op_get_link
,
11080 .get_eeprom_len
= tg3_get_eeprom_len
,
11081 .get_eeprom
= tg3_get_eeprom
,
11082 .set_eeprom
= tg3_set_eeprom
,
11083 .get_ringparam
= tg3_get_ringparam
,
11084 .set_ringparam
= tg3_set_ringparam
,
11085 .get_pauseparam
= tg3_get_pauseparam
,
11086 .set_pauseparam
= tg3_set_pauseparam
,
11087 .get_rx_csum
= tg3_get_rx_csum
,
11088 .set_rx_csum
= tg3_set_rx_csum
,
11089 .set_tx_csum
= tg3_set_tx_csum
,
11090 .set_sg
= ethtool_op_set_sg
,
11091 .set_tso
= tg3_set_tso
,
11092 .self_test
= tg3_self_test
,
11093 .get_strings
= tg3_get_strings
,
11094 .phys_id
= tg3_phys_id
,
11095 .get_ethtool_stats
= tg3_get_ethtool_stats
,
11096 .get_coalesce
= tg3_get_coalesce
,
11097 .set_coalesce
= tg3_set_coalesce
,
11098 .get_sset_count
= tg3_get_sset_count
,
11101 static void __devinit
tg3_get_eeprom_size(struct tg3
*tp
)
11103 u32 cursize
, val
, magic
;
11105 tp
->nvram_size
= EEPROM_CHIP_SIZE
;
11107 if (tg3_nvram_read(tp
, 0, &magic
) != 0)
11110 if ((magic
!= TG3_EEPROM_MAGIC
) &&
11111 ((magic
& TG3_EEPROM_MAGIC_FW_MSK
) != TG3_EEPROM_MAGIC_FW
) &&
11112 ((magic
& TG3_EEPROM_MAGIC_HW_MSK
) != TG3_EEPROM_MAGIC_HW
))
11116 * Size the chip by reading offsets at increasing powers of two.
11117 * When we encounter our validation signature, we know the addressing
11118 * has wrapped around, and thus have our chip size.
11122 while (cursize
< tp
->nvram_size
) {
11123 if (tg3_nvram_read(tp
, cursize
, &val
) != 0)
11132 tp
->nvram_size
= cursize
;
11135 static void __devinit
tg3_get_nvram_size(struct tg3
*tp
)
11139 if ((tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) ||
11140 tg3_nvram_read(tp
, 0, &val
) != 0)
11143 /* Selfboot format */
11144 if (val
!= TG3_EEPROM_MAGIC
) {
11145 tg3_get_eeprom_size(tp
);
11149 if (tg3_nvram_read(tp
, 0xf0, &val
) == 0) {
11151 /* This is confusing. We want to operate on the
11152 * 16-bit value at offset 0xf2. The tg3_nvram_read()
11153 * call will read from NVRAM and byteswap the data
11154 * according to the byteswapping settings for all
11155 * other register accesses. This ensures the data we
11156 * want will always reside in the lower 16-bits.
11157 * However, the data in NVRAM is in LE format, which
11158 * means the data from the NVRAM read will always be
11159 * opposite the endianness of the CPU. The 16-bit
11160 * byteswap then brings the data to CPU endianness.
11162 tp
->nvram_size
= swab16((u16
)(val
& 0x0000ffff)) * 1024;
11166 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
11169 static void __devinit
tg3_get_nvram_info(struct tg3
*tp
)
11173 nvcfg1
= tr32(NVRAM_CFG1
);
11174 if (nvcfg1
& NVRAM_CFG1_FLASHIF_ENAB
) {
11175 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11177 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
11178 tw32(NVRAM_CFG1
, nvcfg1
);
11181 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
) ||
11182 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
11183 switch (nvcfg1
& NVRAM_CFG1_VENDOR_MASK
) {
11184 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED
:
11185 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11186 tp
->nvram_pagesize
= ATMEL_AT45DB0X1B_PAGE_SIZE
;
11187 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11189 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED
:
11190 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11191 tp
->nvram_pagesize
= ATMEL_AT25F512_PAGE_SIZE
;
11193 case FLASH_VENDOR_ATMEL_EEPROM
:
11194 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11195 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
11196 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11198 case FLASH_VENDOR_ST
:
11199 tp
->nvram_jedecnum
= JEDEC_ST
;
11200 tp
->nvram_pagesize
= ST_M45PEX0_PAGE_SIZE
;
11201 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11203 case FLASH_VENDOR_SAIFUN
:
11204 tp
->nvram_jedecnum
= JEDEC_SAIFUN
;
11205 tp
->nvram_pagesize
= SAIFUN_SA25F0XX_PAGE_SIZE
;
11207 case FLASH_VENDOR_SST_SMALL
:
11208 case FLASH_VENDOR_SST_LARGE
:
11209 tp
->nvram_jedecnum
= JEDEC_SST
;
11210 tp
->nvram_pagesize
= SST_25VF0X0_PAGE_SIZE
;
11214 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11215 tp
->nvram_pagesize
= ATMEL_AT45DB0X1B_PAGE_SIZE
;
11216 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11220 static void __devinit
tg3_nvram_get_pagesize(struct tg3
*tp
, u32 nvmcfg1
)
11222 switch (nvmcfg1
& NVRAM_CFG1_5752PAGE_SIZE_MASK
) {
11223 case FLASH_5752PAGE_SIZE_256
:
11224 tp
->nvram_pagesize
= 256;
11226 case FLASH_5752PAGE_SIZE_512
:
11227 tp
->nvram_pagesize
= 512;
11229 case FLASH_5752PAGE_SIZE_1K
:
11230 tp
->nvram_pagesize
= 1024;
11232 case FLASH_5752PAGE_SIZE_2K
:
11233 tp
->nvram_pagesize
= 2048;
11235 case FLASH_5752PAGE_SIZE_4K
:
11236 tp
->nvram_pagesize
= 4096;
11238 case FLASH_5752PAGE_SIZE_264
:
11239 tp
->nvram_pagesize
= 264;
11241 case FLASH_5752PAGE_SIZE_528
:
11242 tp
->nvram_pagesize
= 528;
11247 static void __devinit
tg3_get_5752_nvram_info(struct tg3
*tp
)
11251 nvcfg1
= tr32(NVRAM_CFG1
);
11253 /* NVRAM protection for TPM */
11254 if (nvcfg1
& (1 << 27))
11255 tp
->tg3_flags3
|= TG3_FLG3_PROTECTED_NVRAM
;
11257 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11258 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ
:
11259 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ
:
11260 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11261 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11263 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
11264 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11265 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11266 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11268 case FLASH_5752VENDOR_ST_M45PE10
:
11269 case FLASH_5752VENDOR_ST_M45PE20
:
11270 case FLASH_5752VENDOR_ST_M45PE40
:
11271 tp
->nvram_jedecnum
= JEDEC_ST
;
11272 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11273 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11277 if (tp
->tg3_flags2
& TG3_FLG2_FLASH
) {
11278 tg3_nvram_get_pagesize(tp
, nvcfg1
);
11280 /* For eeprom, set pagesize to maximum eeprom size */
11281 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
11283 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
11284 tw32(NVRAM_CFG1
, nvcfg1
);
11288 static void __devinit
tg3_get_5755_nvram_info(struct tg3
*tp
)
11290 u32 nvcfg1
, protect
= 0;
11292 nvcfg1
= tr32(NVRAM_CFG1
);
11294 /* NVRAM protection for TPM */
11295 if (nvcfg1
& (1 << 27)) {
11296 tp
->tg3_flags3
|= TG3_FLG3_PROTECTED_NVRAM
;
11300 nvcfg1
&= NVRAM_CFG1_5752VENDOR_MASK
;
11302 case FLASH_5755VENDOR_ATMEL_FLASH_1
:
11303 case FLASH_5755VENDOR_ATMEL_FLASH_2
:
11304 case FLASH_5755VENDOR_ATMEL_FLASH_3
:
11305 case FLASH_5755VENDOR_ATMEL_FLASH_5
:
11306 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11307 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11308 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11309 tp
->nvram_pagesize
= 264;
11310 if (nvcfg1
== FLASH_5755VENDOR_ATMEL_FLASH_1
||
11311 nvcfg1
== FLASH_5755VENDOR_ATMEL_FLASH_5
)
11312 tp
->nvram_size
= (protect
? 0x3e200 :
11313 TG3_NVRAM_SIZE_512KB
);
11314 else if (nvcfg1
== FLASH_5755VENDOR_ATMEL_FLASH_2
)
11315 tp
->nvram_size
= (protect
? 0x1f200 :
11316 TG3_NVRAM_SIZE_256KB
);
11318 tp
->nvram_size
= (protect
? 0x1f200 :
11319 TG3_NVRAM_SIZE_128KB
);
11321 case FLASH_5752VENDOR_ST_M45PE10
:
11322 case FLASH_5752VENDOR_ST_M45PE20
:
11323 case FLASH_5752VENDOR_ST_M45PE40
:
11324 tp
->nvram_jedecnum
= JEDEC_ST
;
11325 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11326 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11327 tp
->nvram_pagesize
= 256;
11328 if (nvcfg1
== FLASH_5752VENDOR_ST_M45PE10
)
11329 tp
->nvram_size
= (protect
?
11330 TG3_NVRAM_SIZE_64KB
:
11331 TG3_NVRAM_SIZE_128KB
);
11332 else if (nvcfg1
== FLASH_5752VENDOR_ST_M45PE20
)
11333 tp
->nvram_size
= (protect
?
11334 TG3_NVRAM_SIZE_64KB
:
11335 TG3_NVRAM_SIZE_256KB
);
11337 tp
->nvram_size
= (protect
?
11338 TG3_NVRAM_SIZE_128KB
:
11339 TG3_NVRAM_SIZE_512KB
);
11344 static void __devinit
tg3_get_5787_nvram_info(struct tg3
*tp
)
11348 nvcfg1
= tr32(NVRAM_CFG1
);
11350 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11351 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ
:
11352 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ
:
11353 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ
:
11354 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ
:
11355 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11356 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11357 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
11359 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
11360 tw32(NVRAM_CFG1
, nvcfg1
);
11362 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
11363 case FLASH_5755VENDOR_ATMEL_FLASH_1
:
11364 case FLASH_5755VENDOR_ATMEL_FLASH_2
:
11365 case FLASH_5755VENDOR_ATMEL_FLASH_3
:
11366 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11367 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11368 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11369 tp
->nvram_pagesize
= 264;
11371 case FLASH_5752VENDOR_ST_M45PE10
:
11372 case FLASH_5752VENDOR_ST_M45PE20
:
11373 case FLASH_5752VENDOR_ST_M45PE40
:
11374 tp
->nvram_jedecnum
= JEDEC_ST
;
11375 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11376 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11377 tp
->nvram_pagesize
= 256;
11382 static void __devinit
tg3_get_5761_nvram_info(struct tg3
*tp
)
11384 u32 nvcfg1
, protect
= 0;
11386 nvcfg1
= tr32(NVRAM_CFG1
);
11388 /* NVRAM protection for TPM */
11389 if (nvcfg1
& (1 << 27)) {
11390 tp
->tg3_flags3
|= TG3_FLG3_PROTECTED_NVRAM
;
11394 nvcfg1
&= NVRAM_CFG1_5752VENDOR_MASK
;
11396 case FLASH_5761VENDOR_ATMEL_ADB021D
:
11397 case FLASH_5761VENDOR_ATMEL_ADB041D
:
11398 case FLASH_5761VENDOR_ATMEL_ADB081D
:
11399 case FLASH_5761VENDOR_ATMEL_ADB161D
:
11400 case FLASH_5761VENDOR_ATMEL_MDB021D
:
11401 case FLASH_5761VENDOR_ATMEL_MDB041D
:
11402 case FLASH_5761VENDOR_ATMEL_MDB081D
:
11403 case FLASH_5761VENDOR_ATMEL_MDB161D
:
11404 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11405 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11406 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11407 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
11408 tp
->nvram_pagesize
= 256;
11410 case FLASH_5761VENDOR_ST_A_M45PE20
:
11411 case FLASH_5761VENDOR_ST_A_M45PE40
:
11412 case FLASH_5761VENDOR_ST_A_M45PE80
:
11413 case FLASH_5761VENDOR_ST_A_M45PE16
:
11414 case FLASH_5761VENDOR_ST_M_M45PE20
:
11415 case FLASH_5761VENDOR_ST_M_M45PE40
:
11416 case FLASH_5761VENDOR_ST_M_M45PE80
:
11417 case FLASH_5761VENDOR_ST_M_M45PE16
:
11418 tp
->nvram_jedecnum
= JEDEC_ST
;
11419 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11420 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11421 tp
->nvram_pagesize
= 256;
11426 tp
->nvram_size
= tr32(NVRAM_ADDR_LOCKOUT
);
11429 case FLASH_5761VENDOR_ATMEL_ADB161D
:
11430 case FLASH_5761VENDOR_ATMEL_MDB161D
:
11431 case FLASH_5761VENDOR_ST_A_M45PE16
:
11432 case FLASH_5761VENDOR_ST_M_M45PE16
:
11433 tp
->nvram_size
= TG3_NVRAM_SIZE_2MB
;
11435 case FLASH_5761VENDOR_ATMEL_ADB081D
:
11436 case FLASH_5761VENDOR_ATMEL_MDB081D
:
11437 case FLASH_5761VENDOR_ST_A_M45PE80
:
11438 case FLASH_5761VENDOR_ST_M_M45PE80
:
11439 tp
->nvram_size
= TG3_NVRAM_SIZE_1MB
;
11441 case FLASH_5761VENDOR_ATMEL_ADB041D
:
11442 case FLASH_5761VENDOR_ATMEL_MDB041D
:
11443 case FLASH_5761VENDOR_ST_A_M45PE40
:
11444 case FLASH_5761VENDOR_ST_M_M45PE40
:
11445 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
11447 case FLASH_5761VENDOR_ATMEL_ADB021D
:
11448 case FLASH_5761VENDOR_ATMEL_MDB021D
:
11449 case FLASH_5761VENDOR_ST_A_M45PE20
:
11450 case FLASH_5761VENDOR_ST_M_M45PE20
:
11451 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
11457 static void __devinit
tg3_get_5906_nvram_info(struct tg3
*tp
)
11459 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11460 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11461 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
11464 static void __devinit
tg3_get_57780_nvram_info(struct tg3
*tp
)
11468 nvcfg1
= tr32(NVRAM_CFG1
);
11470 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11471 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ
:
11472 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ
:
11473 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11474 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11475 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
11477 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
11478 tw32(NVRAM_CFG1
, nvcfg1
);
11480 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
11481 case FLASH_57780VENDOR_ATMEL_AT45DB011D
:
11482 case FLASH_57780VENDOR_ATMEL_AT45DB011B
:
11483 case FLASH_57780VENDOR_ATMEL_AT45DB021D
:
11484 case FLASH_57780VENDOR_ATMEL_AT45DB021B
:
11485 case FLASH_57780VENDOR_ATMEL_AT45DB041D
:
11486 case FLASH_57780VENDOR_ATMEL_AT45DB041B
:
11487 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11488 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11489 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11491 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11492 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
11493 case FLASH_57780VENDOR_ATMEL_AT45DB011D
:
11494 case FLASH_57780VENDOR_ATMEL_AT45DB011B
:
11495 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
11497 case FLASH_57780VENDOR_ATMEL_AT45DB021D
:
11498 case FLASH_57780VENDOR_ATMEL_AT45DB021B
:
11499 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
11501 case FLASH_57780VENDOR_ATMEL_AT45DB041D
:
11502 case FLASH_57780VENDOR_ATMEL_AT45DB041B
:
11503 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
11507 case FLASH_5752VENDOR_ST_M45PE10
:
11508 case FLASH_5752VENDOR_ST_M45PE20
:
11509 case FLASH_5752VENDOR_ST_M45PE40
:
11510 tp
->nvram_jedecnum
= JEDEC_ST
;
11511 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11512 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11514 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11515 case FLASH_5752VENDOR_ST_M45PE10
:
11516 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
11518 case FLASH_5752VENDOR_ST_M45PE20
:
11519 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
11521 case FLASH_5752VENDOR_ST_M45PE40
:
11522 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
11527 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM
;
11531 tg3_nvram_get_pagesize(tp
, nvcfg1
);
11532 if (tp
->nvram_pagesize
!= 264 && tp
->nvram_pagesize
!= 528)
11533 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
11537 static void __devinit
tg3_get_5717_nvram_info(struct tg3
*tp
)
11541 nvcfg1
= tr32(NVRAM_CFG1
);
11543 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11544 case FLASH_5717VENDOR_ATMEL_EEPROM
:
11545 case FLASH_5717VENDOR_MICRO_EEPROM
:
11546 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11547 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11548 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
11550 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
11551 tw32(NVRAM_CFG1
, nvcfg1
);
11553 case FLASH_5717VENDOR_ATMEL_MDB011D
:
11554 case FLASH_5717VENDOR_ATMEL_ADB011B
:
11555 case FLASH_5717VENDOR_ATMEL_ADB011D
:
11556 case FLASH_5717VENDOR_ATMEL_MDB021D
:
11557 case FLASH_5717VENDOR_ATMEL_ADB021B
:
11558 case FLASH_5717VENDOR_ATMEL_ADB021D
:
11559 case FLASH_5717VENDOR_ATMEL_45USPT
:
11560 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11561 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11562 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11564 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11565 case FLASH_5717VENDOR_ATMEL_MDB021D
:
11566 case FLASH_5717VENDOR_ATMEL_ADB021B
:
11567 case FLASH_5717VENDOR_ATMEL_ADB021D
:
11568 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
11571 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
11575 case FLASH_5717VENDOR_ST_M_M25PE10
:
11576 case FLASH_5717VENDOR_ST_A_M25PE10
:
11577 case FLASH_5717VENDOR_ST_M_M45PE10
:
11578 case FLASH_5717VENDOR_ST_A_M45PE10
:
11579 case FLASH_5717VENDOR_ST_M_M25PE20
:
11580 case FLASH_5717VENDOR_ST_A_M25PE20
:
11581 case FLASH_5717VENDOR_ST_M_M45PE20
:
11582 case FLASH_5717VENDOR_ST_A_M45PE20
:
11583 case FLASH_5717VENDOR_ST_25USPT
:
11584 case FLASH_5717VENDOR_ST_45USPT
:
11585 tp
->nvram_jedecnum
= JEDEC_ST
;
11586 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11587 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11589 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11590 case FLASH_5717VENDOR_ST_M_M25PE20
:
11591 case FLASH_5717VENDOR_ST_A_M25PE20
:
11592 case FLASH_5717VENDOR_ST_M_M45PE20
:
11593 case FLASH_5717VENDOR_ST_A_M45PE20
:
11594 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
11597 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
11602 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM
;
11606 tg3_nvram_get_pagesize(tp
, nvcfg1
);
11607 if (tp
->nvram_pagesize
!= 264 && tp
->nvram_pagesize
!= 528)
11608 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
11611 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11612 static void __devinit
tg3_nvram_init(struct tg3
*tp
)
11614 tw32_f(GRC_EEPROM_ADDR
,
11615 (EEPROM_ADDR_FSM_RESET
|
11616 (EEPROM_DEFAULT_CLOCK_PERIOD
<<
11617 EEPROM_ADDR_CLKPERD_SHIFT
)));
11621 /* Enable seeprom accesses. */
11622 tw32_f(GRC_LOCAL_CTRL
,
11623 tr32(GRC_LOCAL_CTRL
) | GRC_LCLCTRL_AUTO_SEEPROM
);
11626 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
11627 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
) {
11628 tp
->tg3_flags
|= TG3_FLAG_NVRAM
;
11630 if (tg3_nvram_lock(tp
)) {
11631 netdev_warn(tp
->dev
,
11632 "Cannot get nvram lock, %s failed\n",
11636 tg3_enable_nvram_access(tp
);
11638 tp
->nvram_size
= 0;
11640 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
)
11641 tg3_get_5752_nvram_info(tp
);
11642 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
)
11643 tg3_get_5755_nvram_info(tp
);
11644 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5787
||
11645 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
11646 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
11647 tg3_get_5787_nvram_info(tp
);
11648 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
)
11649 tg3_get_5761_nvram_info(tp
);
11650 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
11651 tg3_get_5906_nvram_info(tp
);
11652 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
||
11653 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
11654 tg3_get_57780_nvram_info(tp
);
11655 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
11656 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
)
11657 tg3_get_5717_nvram_info(tp
);
11659 tg3_get_nvram_info(tp
);
11661 if (tp
->nvram_size
== 0)
11662 tg3_get_nvram_size(tp
);
11664 tg3_disable_nvram_access(tp
);
11665 tg3_nvram_unlock(tp
);
11668 tp
->tg3_flags
&= ~(TG3_FLAG_NVRAM
| TG3_FLAG_NVRAM_BUFFERED
);
11670 tg3_get_eeprom_size(tp
);
11674 static int tg3_nvram_write_block_using_eeprom(struct tg3
*tp
,
11675 u32 offset
, u32 len
, u8
*buf
)
11680 for (i
= 0; i
< len
; i
+= 4) {
11686 memcpy(&data
, buf
+ i
, 4);
11689 * The SEEPROM interface expects the data to always be opposite
11690 * the native endian format. We accomplish this by reversing
11691 * all the operations that would have been performed on the
11692 * data from a call to tg3_nvram_read_be32().
11694 tw32(GRC_EEPROM_DATA
, swab32(be32_to_cpu(data
)));
11696 val
= tr32(GRC_EEPROM_ADDR
);
11697 tw32(GRC_EEPROM_ADDR
, val
| EEPROM_ADDR_COMPLETE
);
11699 val
&= ~(EEPROM_ADDR_ADDR_MASK
| EEPROM_ADDR_DEVID_MASK
|
11701 tw32(GRC_EEPROM_ADDR
, val
|
11702 (0 << EEPROM_ADDR_DEVID_SHIFT
) |
11703 (addr
& EEPROM_ADDR_ADDR_MASK
) |
11704 EEPROM_ADDR_START
|
11705 EEPROM_ADDR_WRITE
);
11707 for (j
= 0; j
< 1000; j
++) {
11708 val
= tr32(GRC_EEPROM_ADDR
);
11710 if (val
& EEPROM_ADDR_COMPLETE
)
11714 if (!(val
& EEPROM_ADDR_COMPLETE
)) {
11723 /* offset and length are dword aligned */
11724 static int tg3_nvram_write_block_unbuffered(struct tg3
*tp
, u32 offset
, u32 len
,
11728 u32 pagesize
= tp
->nvram_pagesize
;
11729 u32 pagemask
= pagesize
- 1;
11733 tmp
= kmalloc(pagesize
, GFP_KERNEL
);
11739 u32 phy_addr
, page_off
, size
;
11741 phy_addr
= offset
& ~pagemask
;
11743 for (j
= 0; j
< pagesize
; j
+= 4) {
11744 ret
= tg3_nvram_read_be32(tp
, phy_addr
+ j
,
11745 (__be32
*) (tmp
+ j
));
11752 page_off
= offset
& pagemask
;
11759 memcpy(tmp
+ page_off
, buf
, size
);
11761 offset
= offset
+ (pagesize
- page_off
);
11763 tg3_enable_nvram_access(tp
);
11766 * Before we can erase the flash page, we need
11767 * to issue a special "write enable" command.
11769 nvram_cmd
= NVRAM_CMD_WREN
| NVRAM_CMD_GO
| NVRAM_CMD_DONE
;
11771 if (tg3_nvram_exec_cmd(tp
, nvram_cmd
))
11774 /* Erase the target page */
11775 tw32(NVRAM_ADDR
, phy_addr
);
11777 nvram_cmd
= NVRAM_CMD_GO
| NVRAM_CMD_DONE
| NVRAM_CMD_WR
|
11778 NVRAM_CMD_FIRST
| NVRAM_CMD_LAST
| NVRAM_CMD_ERASE
;
11780 if (tg3_nvram_exec_cmd(tp
, nvram_cmd
))
11783 /* Issue another write enable to start the write. */
11784 nvram_cmd
= NVRAM_CMD_WREN
| NVRAM_CMD_GO
| NVRAM_CMD_DONE
;
11786 if (tg3_nvram_exec_cmd(tp
, nvram_cmd
))
11789 for (j
= 0; j
< pagesize
; j
+= 4) {
11792 data
= *((__be32
*) (tmp
+ j
));
11794 tw32(NVRAM_WRDATA
, be32_to_cpu(data
));
11796 tw32(NVRAM_ADDR
, phy_addr
+ j
);
11798 nvram_cmd
= NVRAM_CMD_GO
| NVRAM_CMD_DONE
|
11802 nvram_cmd
|= NVRAM_CMD_FIRST
;
11803 else if (j
== (pagesize
- 4))
11804 nvram_cmd
|= NVRAM_CMD_LAST
;
11806 if ((ret
= tg3_nvram_exec_cmd(tp
, nvram_cmd
)))
11813 nvram_cmd
= NVRAM_CMD_WRDI
| NVRAM_CMD_GO
| NVRAM_CMD_DONE
;
11814 tg3_nvram_exec_cmd(tp
, nvram_cmd
);
11821 /* offset and length are dword aligned */
11822 static int tg3_nvram_write_block_buffered(struct tg3
*tp
, u32 offset
, u32 len
,
11827 for (i
= 0; i
< len
; i
+= 4, offset
+= 4) {
11828 u32 page_off
, phy_addr
, nvram_cmd
;
11831 memcpy(&data
, buf
+ i
, 4);
11832 tw32(NVRAM_WRDATA
, be32_to_cpu(data
));
11834 page_off
= offset
% tp
->nvram_pagesize
;
11836 phy_addr
= tg3_nvram_phys_addr(tp
, offset
);
11838 tw32(NVRAM_ADDR
, phy_addr
);
11840 nvram_cmd
= NVRAM_CMD_GO
| NVRAM_CMD_DONE
| NVRAM_CMD_WR
;
11842 if (page_off
== 0 || i
== 0)
11843 nvram_cmd
|= NVRAM_CMD_FIRST
;
11844 if (page_off
== (tp
->nvram_pagesize
- 4))
11845 nvram_cmd
|= NVRAM_CMD_LAST
;
11847 if (i
== (len
- 4))
11848 nvram_cmd
|= NVRAM_CMD_LAST
;
11850 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5752
&&
11851 !(tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) &&
11852 (tp
->nvram_jedecnum
== JEDEC_ST
) &&
11853 (nvram_cmd
& NVRAM_CMD_FIRST
)) {
11855 if ((ret
= tg3_nvram_exec_cmd(tp
,
11856 NVRAM_CMD_WREN
| NVRAM_CMD_GO
|
11861 if (!(tp
->tg3_flags2
& TG3_FLG2_FLASH
)) {
11862 /* We always do complete word writes to eeprom. */
11863 nvram_cmd
|= (NVRAM_CMD_FIRST
| NVRAM_CMD_LAST
);
11866 if ((ret
= tg3_nvram_exec_cmd(tp
, nvram_cmd
)))
11872 /* offset and length are dword aligned */
11873 static int tg3_nvram_write_block(struct tg3
*tp
, u32 offset
, u32 len
, u8
*buf
)
11877 if (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
) {
11878 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
&
11879 ~GRC_LCLCTRL_GPIO_OUTPUT1
);
11883 if (!(tp
->tg3_flags
& TG3_FLAG_NVRAM
)) {
11884 ret
= tg3_nvram_write_block_using_eeprom(tp
, offset
, len
, buf
);
11888 ret
= tg3_nvram_lock(tp
);
11892 tg3_enable_nvram_access(tp
);
11893 if ((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
11894 !(tp
->tg3_flags3
& TG3_FLG3_PROTECTED_NVRAM
))
11895 tw32(NVRAM_WRITE1
, 0x406);
11897 grc_mode
= tr32(GRC_MODE
);
11898 tw32(GRC_MODE
, grc_mode
| GRC_MODE_NVRAM_WR_ENABLE
);
11900 if ((tp
->tg3_flags
& TG3_FLAG_NVRAM_BUFFERED
) ||
11901 !(tp
->tg3_flags2
& TG3_FLG2_FLASH
)) {
11903 ret
= tg3_nvram_write_block_buffered(tp
, offset
, len
,
11906 ret
= tg3_nvram_write_block_unbuffered(tp
, offset
, len
,
11910 grc_mode
= tr32(GRC_MODE
);
11911 tw32(GRC_MODE
, grc_mode
& ~GRC_MODE_NVRAM_WR_ENABLE
);
11913 tg3_disable_nvram_access(tp
);
11914 tg3_nvram_unlock(tp
);
11917 if (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
) {
11918 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
);
11925 struct subsys_tbl_ent
{
11926 u16 subsys_vendor
, subsys_devid
;
11930 static struct subsys_tbl_ent subsys_id_to_phy_id
[] __devinitdata
= {
11931 /* Broadcom boards. */
11932 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11933 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6
, TG3_PHY_ID_BCM5401
},
11934 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11935 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5
, TG3_PHY_ID_BCM5701
},
11936 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11937 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6
, TG3_PHY_ID_BCM8002
},
11938 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11939 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9
, 0 },
11940 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11941 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1
, TG3_PHY_ID_BCM5701
},
11942 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11943 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8
, TG3_PHY_ID_BCM5701
},
11944 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11945 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7
, 0 },
11946 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11947 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10
, TG3_PHY_ID_BCM5701
},
11948 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11949 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12
, TG3_PHY_ID_BCM5701
},
11950 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11951 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1
, TG3_PHY_ID_BCM5703
},
11952 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11953 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2
, TG3_PHY_ID_BCM5703
},
11956 { TG3PCI_SUBVENDOR_ID_3COM
,
11957 TG3PCI_SUBDEVICE_ID_3COM_3C996T
, TG3_PHY_ID_BCM5401
},
11958 { TG3PCI_SUBVENDOR_ID_3COM
,
11959 TG3PCI_SUBDEVICE_ID_3COM_3C996BT
, TG3_PHY_ID_BCM5701
},
11960 { TG3PCI_SUBVENDOR_ID_3COM
,
11961 TG3PCI_SUBDEVICE_ID_3COM_3C996SX
, 0 },
11962 { TG3PCI_SUBVENDOR_ID_3COM
,
11963 TG3PCI_SUBDEVICE_ID_3COM_3C1000T
, TG3_PHY_ID_BCM5701
},
11964 { TG3PCI_SUBVENDOR_ID_3COM
,
11965 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01
, TG3_PHY_ID_BCM5701
},
11968 { TG3PCI_SUBVENDOR_ID_DELL
,
11969 TG3PCI_SUBDEVICE_ID_DELL_VIPER
, TG3_PHY_ID_BCM5401
},
11970 { TG3PCI_SUBVENDOR_ID_DELL
,
11971 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR
, TG3_PHY_ID_BCM5401
},
11972 { TG3PCI_SUBVENDOR_ID_DELL
,
11973 TG3PCI_SUBDEVICE_ID_DELL_MERLOT
, TG3_PHY_ID_BCM5411
},
11974 { TG3PCI_SUBVENDOR_ID_DELL
,
11975 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT
, TG3_PHY_ID_BCM5411
},
11977 /* Compaq boards. */
11978 { TG3PCI_SUBVENDOR_ID_COMPAQ
,
11979 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE
, TG3_PHY_ID_BCM5701
},
11980 { TG3PCI_SUBVENDOR_ID_COMPAQ
,
11981 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2
, TG3_PHY_ID_BCM5701
},
11982 { TG3PCI_SUBVENDOR_ID_COMPAQ
,
11983 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING
, 0 },
11984 { TG3PCI_SUBVENDOR_ID_COMPAQ
,
11985 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780
, TG3_PHY_ID_BCM5701
},
11986 { TG3PCI_SUBVENDOR_ID_COMPAQ
,
11987 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2
, TG3_PHY_ID_BCM5701
},
11990 { TG3PCI_SUBVENDOR_ID_IBM
,
11991 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2
, 0 }
11994 static struct subsys_tbl_ent
* __devinit
tg3_lookup_by_subsys(struct tg3
*tp
)
11998 for (i
= 0; i
< ARRAY_SIZE(subsys_id_to_phy_id
); i
++) {
11999 if ((subsys_id_to_phy_id
[i
].subsys_vendor
==
12000 tp
->pdev
->subsystem_vendor
) &&
12001 (subsys_id_to_phy_id
[i
].subsys_devid
==
12002 tp
->pdev
->subsystem_device
))
12003 return &subsys_id_to_phy_id
[i
];
12008 static void __devinit
tg3_get_eeprom_hw_cfg(struct tg3
*tp
)
12013 /* On some early chips the SRAM cannot be accessed in D3hot state,
12014 * so need make sure we're in D0.
12016 pci_read_config_word(tp
->pdev
, tp
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
12017 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
12018 pci_write_config_word(tp
->pdev
, tp
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
12021 /* Make sure register accesses (indirect or otherwise)
12022 * will function correctly.
12024 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
12025 tp
->misc_host_ctrl
);
12027 /* The memory arbiter has to be enabled in order for SRAM accesses
12028 * to succeed. Normally on powerup the tg3 chip firmware will make
12029 * sure it is enabled, but other entities such as system netboot
12030 * code might disable it.
12032 val
= tr32(MEMARB_MODE
);
12033 tw32(MEMARB_MODE
, val
| MEMARB_MODE_ENABLE
);
12035 tp
->phy_id
= TG3_PHY_ID_INVALID
;
12036 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
12038 /* Assume an onboard device and WOL capable by default. */
12039 tp
->tg3_flags
|= TG3_FLAG_EEPROM_WRITE_PROT
| TG3_FLAG_WOL_CAP
;
12041 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
12042 if (!(tr32(PCIE_TRANSACTION_CFG
) & PCIE_TRANS_CFG_LOM
)) {
12043 tp
->tg3_flags
&= ~TG3_FLAG_EEPROM_WRITE_PROT
;
12044 tp
->tg3_flags2
|= TG3_FLG2_IS_NIC
;
12046 val
= tr32(VCPU_CFGSHDW
);
12047 if (val
& VCPU_CFGSHDW_ASPM_DBNC
)
12048 tp
->tg3_flags
|= TG3_FLAG_ASPM_WORKAROUND
;
12049 if ((val
& VCPU_CFGSHDW_WOL_ENABLE
) &&
12050 (val
& VCPU_CFGSHDW_WOL_MAGPKT
))
12051 tp
->tg3_flags
|= TG3_FLAG_WOL_ENABLE
;
12055 tg3_read_mem(tp
, NIC_SRAM_DATA_SIG
, &val
);
12056 if (val
== NIC_SRAM_DATA_SIG_MAGIC
) {
12057 u32 nic_cfg
, led_cfg
;
12058 u32 nic_phy_id
, ver
, cfg2
= 0, cfg4
= 0, eeprom_phy_id
;
12059 int eeprom_phy_serdes
= 0;
12061 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG
, &nic_cfg
);
12062 tp
->nic_sram_data_cfg
= nic_cfg
;
12064 tg3_read_mem(tp
, NIC_SRAM_DATA_VER
, &ver
);
12065 ver
>>= NIC_SRAM_DATA_VER_SHIFT
;
12066 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
) &&
12067 (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
) &&
12068 (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5703
) &&
12069 (ver
> 0) && (ver
< 0x100))
12070 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG_2
, &cfg2
);
12072 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
12073 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG_4
, &cfg4
);
12075 if ((nic_cfg
& NIC_SRAM_DATA_CFG_PHY_TYPE_MASK
) ==
12076 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER
)
12077 eeprom_phy_serdes
= 1;
12079 tg3_read_mem(tp
, NIC_SRAM_DATA_PHY_ID
, &nic_phy_id
);
12080 if (nic_phy_id
!= 0) {
12081 u32 id1
= nic_phy_id
& NIC_SRAM_DATA_PHY_ID1_MASK
;
12082 u32 id2
= nic_phy_id
& NIC_SRAM_DATA_PHY_ID2_MASK
;
12084 eeprom_phy_id
= (id1
>> 16) << 10;
12085 eeprom_phy_id
|= (id2
& 0xfc00) << 16;
12086 eeprom_phy_id
|= (id2
& 0x03ff) << 0;
12090 tp
->phy_id
= eeprom_phy_id
;
12091 if (eeprom_phy_serdes
) {
12092 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
12093 tp
->tg3_flags2
|= TG3_FLG2_PHY_SERDES
;
12095 tp
->tg3_flags2
|= TG3_FLG2_MII_SERDES
;
12098 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
12099 led_cfg
= cfg2
& (NIC_SRAM_DATA_CFG_LED_MODE_MASK
|
12100 SHASTA_EXT_LED_MODE_MASK
);
12102 led_cfg
= nic_cfg
& NIC_SRAM_DATA_CFG_LED_MODE_MASK
;
12106 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1
:
12107 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
12110 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2
:
12111 tp
->led_ctrl
= LED_CTRL_MODE_PHY_2
;
12114 case NIC_SRAM_DATA_CFG_LED_MODE_MAC
:
12115 tp
->led_ctrl
= LED_CTRL_MODE_MAC
;
12117 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12118 * read on some older 5700/5701 bootcode.
12120 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
12122 GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
12124 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
12128 case SHASTA_EXT_LED_SHARED
:
12129 tp
->led_ctrl
= LED_CTRL_MODE_SHARED
;
12130 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
&&
12131 tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A1
)
12132 tp
->led_ctrl
|= (LED_CTRL_MODE_PHY_1
|
12133 LED_CTRL_MODE_PHY_2
);
12136 case SHASTA_EXT_LED_MAC
:
12137 tp
->led_ctrl
= LED_CTRL_MODE_SHASTA_MAC
;
12140 case SHASTA_EXT_LED_COMBO
:
12141 tp
->led_ctrl
= LED_CTRL_MODE_COMBO
;
12142 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
)
12143 tp
->led_ctrl
|= (LED_CTRL_MODE_PHY_1
|
12144 LED_CTRL_MODE_PHY_2
);
12149 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
12150 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) &&
12151 tp
->pdev
->subsystem_vendor
== PCI_VENDOR_ID_DELL
)
12152 tp
->led_ctrl
= LED_CTRL_MODE_PHY_2
;
12154 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
)
12155 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
12157 if (nic_cfg
& NIC_SRAM_DATA_CFG_EEPROM_WP
) {
12158 tp
->tg3_flags
|= TG3_FLAG_EEPROM_WRITE_PROT
;
12159 if ((tp
->pdev
->subsystem_vendor
==
12160 PCI_VENDOR_ID_ARIMA
) &&
12161 (tp
->pdev
->subsystem_device
== 0x205a ||
12162 tp
->pdev
->subsystem_device
== 0x2063))
12163 tp
->tg3_flags
&= ~TG3_FLAG_EEPROM_WRITE_PROT
;
12165 tp
->tg3_flags
&= ~TG3_FLAG_EEPROM_WRITE_PROT
;
12166 tp
->tg3_flags2
|= TG3_FLG2_IS_NIC
;
12169 if (nic_cfg
& NIC_SRAM_DATA_CFG_ASF_ENABLE
) {
12170 tp
->tg3_flags
|= TG3_FLAG_ENABLE_ASF
;
12171 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
12172 tp
->tg3_flags2
|= TG3_FLG2_ASF_NEW_HANDSHAKE
;
12175 if ((nic_cfg
& NIC_SRAM_DATA_CFG_APE_ENABLE
) &&
12176 (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
))
12177 tp
->tg3_flags3
|= TG3_FLG3_ENABLE_APE
;
12179 if (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
&&
12180 !(nic_cfg
& NIC_SRAM_DATA_CFG_FIBER_WOL
))
12181 tp
->tg3_flags
&= ~TG3_FLAG_WOL_CAP
;
12183 if ((tp
->tg3_flags
& TG3_FLAG_WOL_CAP
) &&
12184 (nic_cfg
& NIC_SRAM_DATA_CFG_WOL_ENABLE
))
12185 tp
->tg3_flags
|= TG3_FLAG_WOL_ENABLE
;
12187 if (cfg2
& (1 << 17))
12188 tp
->tg3_flags2
|= TG3_FLG2_CAPACITIVE_COUPLING
;
12190 /* serdes signal pre-emphasis in register 0x590 set by */
12191 /* bootcode if bit 18 is set */
12192 if (cfg2
& (1 << 18))
12193 tp
->tg3_flags2
|= TG3_FLG2_SERDES_PREEMPHASIS
;
12195 if (((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
12196 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
)) &&
12197 (cfg2
& NIC_SRAM_DATA_CFG_2_APD_EN
))
12198 tp
->tg3_flags3
|= TG3_FLG3_PHY_ENABLE_APD
;
12200 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
12203 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG_3
, &cfg3
);
12204 if (cfg3
& NIC_SRAM_ASPM_DEBOUNCE
)
12205 tp
->tg3_flags
|= TG3_FLAG_ASPM_WORKAROUND
;
12208 if (cfg4
& NIC_SRAM_RGMII_INBAND_DISABLE
)
12209 tp
->tg3_flags3
|= TG3_FLG3_RGMII_INBAND_DISABLE
;
12210 if (cfg4
& NIC_SRAM_RGMII_EXT_IBND_RX_EN
)
12211 tp
->tg3_flags3
|= TG3_FLG3_RGMII_EXT_IBND_RX_EN
;
12212 if (cfg4
& NIC_SRAM_RGMII_EXT_IBND_TX_EN
)
12213 tp
->tg3_flags3
|= TG3_FLG3_RGMII_EXT_IBND_TX_EN
;
12216 device_init_wakeup(&tp
->pdev
->dev
, tp
->tg3_flags
& TG3_FLAG_WOL_CAP
);
12217 device_set_wakeup_enable(&tp
->pdev
->dev
,
12218 tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
);
12221 static int __devinit
tg3_issue_otp_command(struct tg3
*tp
, u32 cmd
)
12226 tw32(OTP_CTRL
, cmd
| OTP_CTRL_OTP_CMD_START
);
12227 tw32(OTP_CTRL
, cmd
);
12229 /* Wait for up to 1 ms for command to execute. */
12230 for (i
= 0; i
< 100; i
++) {
12231 val
= tr32(OTP_STATUS
);
12232 if (val
& OTP_STATUS_CMD_DONE
)
12237 return (val
& OTP_STATUS_CMD_DONE
) ? 0 : -EBUSY
;
12240 /* Read the gphy configuration from the OTP region of the chip. The gphy
12241 * configuration is a 32-bit value that straddles the alignment boundary.
12242 * We do two 32-bit reads and then shift and merge the results.
12244 static u32 __devinit
tg3_read_otp_phycfg(struct tg3
*tp
)
12246 u32 bhalf_otp
, thalf_otp
;
12248 tw32(OTP_MODE
, OTP_MODE_OTP_THRU_GRC
);
12250 if (tg3_issue_otp_command(tp
, OTP_CTRL_OTP_CMD_INIT
))
12253 tw32(OTP_ADDRESS
, OTP_ADDRESS_MAGIC1
);
12255 if (tg3_issue_otp_command(tp
, OTP_CTRL_OTP_CMD_READ
))
12258 thalf_otp
= tr32(OTP_READ_DATA
);
12260 tw32(OTP_ADDRESS
, OTP_ADDRESS_MAGIC2
);
12262 if (tg3_issue_otp_command(tp
, OTP_CTRL_OTP_CMD_READ
))
12265 bhalf_otp
= tr32(OTP_READ_DATA
);
12267 return ((thalf_otp
& 0x0000ffff) << 16) | (bhalf_otp
>> 16);
12270 static int __devinit
tg3_phy_probe(struct tg3
*tp
)
12272 u32 hw_phy_id_1
, hw_phy_id_2
;
12273 u32 hw_phy_id
, hw_phy_id_masked
;
12276 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
)
12277 return tg3_phy_init(tp
);
12279 /* Reading the PHY ID register can conflict with ASF
12280 * firmware access to the PHY hardware.
12283 if ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) ||
12284 (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)) {
12285 hw_phy_id
= hw_phy_id_masked
= TG3_PHY_ID_INVALID
;
12287 /* Now read the physical PHY_ID from the chip and verify
12288 * that it is sane. If it doesn't look good, we fall back
12289 * to either the hard-coded table based PHY_ID and failing
12290 * that the value found in the eeprom area.
12292 err
|= tg3_readphy(tp
, MII_PHYSID1
, &hw_phy_id_1
);
12293 err
|= tg3_readphy(tp
, MII_PHYSID2
, &hw_phy_id_2
);
12295 hw_phy_id
= (hw_phy_id_1
& 0xffff) << 10;
12296 hw_phy_id
|= (hw_phy_id_2
& 0xfc00) << 16;
12297 hw_phy_id
|= (hw_phy_id_2
& 0x03ff) << 0;
12299 hw_phy_id_masked
= hw_phy_id
& TG3_PHY_ID_MASK
;
12302 if (!err
&& TG3_KNOWN_PHY_ID(hw_phy_id_masked
)) {
12303 tp
->phy_id
= hw_phy_id
;
12304 if (hw_phy_id_masked
== TG3_PHY_ID_BCM8002
)
12305 tp
->tg3_flags2
|= TG3_FLG2_PHY_SERDES
;
12307 tp
->tg3_flags2
&= ~TG3_FLG2_PHY_SERDES
;
12309 if (tp
->phy_id
!= TG3_PHY_ID_INVALID
) {
12310 /* Do nothing, phy ID already set up in
12311 * tg3_get_eeprom_hw_cfg().
12314 struct subsys_tbl_ent
*p
;
12316 /* No eeprom signature? Try the hardcoded
12317 * subsys device table.
12319 p
= tg3_lookup_by_subsys(tp
);
12323 tp
->phy_id
= p
->phy_id
;
12325 tp
->phy_id
== TG3_PHY_ID_BCM8002
)
12326 tp
->tg3_flags2
|= TG3_FLG2_PHY_SERDES
;
12330 if (!(tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
) &&
12331 !(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) &&
12332 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)) {
12333 u32 bmsr
, adv_reg
, tg3_ctrl
, mask
;
12335 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
12336 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
12337 (bmsr
& BMSR_LSTATUS
))
12338 goto skip_phy_reset
;
12340 err
= tg3_phy_reset(tp
);
12344 adv_reg
= (ADVERTISE_10HALF
| ADVERTISE_10FULL
|
12345 ADVERTISE_100HALF
| ADVERTISE_100FULL
|
12346 ADVERTISE_CSMA
| ADVERTISE_PAUSE_CAP
);
12348 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)) {
12349 tg3_ctrl
= (MII_TG3_CTRL_ADV_1000_HALF
|
12350 MII_TG3_CTRL_ADV_1000_FULL
);
12351 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
12352 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
)
12353 tg3_ctrl
|= (MII_TG3_CTRL_AS_MASTER
|
12354 MII_TG3_CTRL_ENABLE_AS_MASTER
);
12357 mask
= (ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
12358 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
|
12359 ADVERTISED_1000baseT_Half
| ADVERTISED_1000baseT_Full
);
12360 if (!tg3_copper_is_advertising_all(tp
, mask
)) {
12361 tg3_writephy(tp
, MII_ADVERTISE
, adv_reg
);
12363 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
))
12364 tg3_writephy(tp
, MII_TG3_CTRL
, tg3_ctrl
);
12366 tg3_writephy(tp
, MII_BMCR
,
12367 BMCR_ANENABLE
| BMCR_ANRESTART
);
12369 tg3_phy_set_wirespeed(tp
);
12371 tg3_writephy(tp
, MII_ADVERTISE
, adv_reg
);
12372 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
))
12373 tg3_writephy(tp
, MII_TG3_CTRL
, tg3_ctrl
);
12377 if ((tp
->phy_id
& TG3_PHY_ID_MASK
) == TG3_PHY_ID_BCM5401
) {
12378 err
= tg3_init_5401phy_dsp(tp
);
12382 err
= tg3_init_5401phy_dsp(tp
);
12385 if (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
)
12386 tp
->link_config
.advertising
=
12387 (ADVERTISED_1000baseT_Half
|
12388 ADVERTISED_1000baseT_Full
|
12389 ADVERTISED_Autoneg
|
12391 if (tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)
12392 tp
->link_config
.advertising
&=
12393 ~(ADVERTISED_1000baseT_Half
|
12394 ADVERTISED_1000baseT_Full
);
12399 static void __devinit
tg3_read_vpd(struct tg3
*tp
)
12401 u8 vpd_data
[TG3_NVM_VPD_LEN
];
12402 unsigned int block_end
, rosize
, len
;
12406 if ((tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) ||
12407 tg3_nvram_read(tp
, 0x0, &magic
))
12408 goto out_not_found
;
12410 if (magic
== TG3_EEPROM_MAGIC
) {
12411 for (i
= 0; i
< TG3_NVM_VPD_LEN
; i
+= 4) {
12414 /* The data is in little-endian format in NVRAM.
12415 * Use the big-endian read routines to preserve
12416 * the byte order as it exists in NVRAM.
12418 if (tg3_nvram_read_be32(tp
, TG3_NVM_VPD_OFF
+ i
, &tmp
))
12419 goto out_not_found
;
12421 memcpy(&vpd_data
[i
], &tmp
, sizeof(tmp
));
12425 unsigned int pos
= 0;
12427 for (; pos
< TG3_NVM_VPD_LEN
&& i
< 3; i
++, pos
+= cnt
) {
12428 cnt
= pci_read_vpd(tp
->pdev
, pos
,
12429 TG3_NVM_VPD_LEN
- pos
,
12431 if (cnt
== -ETIMEDOUT
|| -EINTR
)
12434 goto out_not_found
;
12436 if (pos
!= TG3_NVM_VPD_LEN
)
12437 goto out_not_found
;
12440 i
= pci_vpd_find_tag(vpd_data
, 0, TG3_NVM_VPD_LEN
,
12441 PCI_VPD_LRDT_RO_DATA
);
12443 goto out_not_found
;
12445 rosize
= pci_vpd_lrdt_size(&vpd_data
[i
]);
12446 block_end
= i
+ PCI_VPD_LRDT_TAG_SIZE
+ rosize
;
12447 i
+= PCI_VPD_LRDT_TAG_SIZE
;
12449 if (block_end
> TG3_NVM_VPD_LEN
)
12450 goto out_not_found
;
12452 j
= pci_vpd_find_info_keyword(vpd_data
, i
, rosize
,
12453 PCI_VPD_RO_KEYWORD_MFR_ID
);
12455 len
= pci_vpd_info_field_size(&vpd_data
[j
]);
12457 j
+= PCI_VPD_INFO_FLD_HDR_SIZE
;
12458 if (j
+ len
> block_end
|| len
!= 4 ||
12459 memcmp(&vpd_data
[j
], "1028", 4))
12462 j
= pci_vpd_find_info_keyword(vpd_data
, i
, rosize
,
12463 PCI_VPD_RO_KEYWORD_VENDOR0
);
12467 len
= pci_vpd_info_field_size(&vpd_data
[j
]);
12469 j
+= PCI_VPD_INFO_FLD_HDR_SIZE
;
12470 if (j
+ len
> block_end
)
12473 memcpy(tp
->fw_ver
, &vpd_data
[j
], len
);
12474 strncat(tp
->fw_ver
, " bc ", TG3_NVM_VPD_LEN
- len
- 1);
12478 i
= pci_vpd_find_info_keyword(vpd_data
, i
, rosize
,
12479 PCI_VPD_RO_KEYWORD_PARTNO
);
12481 goto out_not_found
;
12483 len
= pci_vpd_info_field_size(&vpd_data
[i
]);
12485 i
+= PCI_VPD_INFO_FLD_HDR_SIZE
;
12486 if (len
> TG3_BPN_SIZE
||
12487 (len
+ i
) > TG3_NVM_VPD_LEN
)
12488 goto out_not_found
;
12490 memcpy(tp
->board_part_number
, &vpd_data
[i
], len
);
12495 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
12496 strcpy(tp
->board_part_number
, "BCM95906");
12497 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
&&
12498 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57780
)
12499 strcpy(tp
->board_part_number
, "BCM57780");
12500 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
&&
12501 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57760
)
12502 strcpy(tp
->board_part_number
, "BCM57760");
12503 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
&&
12504 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57790
)
12505 strcpy(tp
->board_part_number
, "BCM57790");
12506 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
&&
12507 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57788
)
12508 strcpy(tp
->board_part_number
, "BCM57788");
12509 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
&&
12510 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57761
)
12511 strcpy(tp
->board_part_number
, "BCM57761");
12512 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
&&
12513 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57765
)
12514 strcpy(tp
->board_part_number
, "BCM57765");
12515 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
&&
12516 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57781
)
12517 strcpy(tp
->board_part_number
, "BCM57781");
12518 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
&&
12519 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57785
)
12520 strcpy(tp
->board_part_number
, "BCM57785");
12521 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
&&
12522 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57791
)
12523 strcpy(tp
->board_part_number
, "BCM57791");
12524 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
&&
12525 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57795
)
12526 strcpy(tp
->board_part_number
, "BCM57795");
12528 strcpy(tp
->board_part_number
, "none");
12531 static int __devinit
tg3_fw_img_is_valid(struct tg3
*tp
, u32 offset
)
12535 if (tg3_nvram_read(tp
, offset
, &val
) ||
12536 (val
& 0xfc000000) != 0x0c000000 ||
12537 tg3_nvram_read(tp
, offset
+ 4, &val
) ||
12544 static void __devinit
tg3_read_bc_ver(struct tg3
*tp
)
12546 u32 val
, offset
, start
, ver_offset
;
12548 bool newver
= false;
12550 if (tg3_nvram_read(tp
, 0xc, &offset
) ||
12551 tg3_nvram_read(tp
, 0x4, &start
))
12554 offset
= tg3_nvram_logical_addr(tp
, offset
);
12556 if (tg3_nvram_read(tp
, offset
, &val
))
12559 if ((val
& 0xfc000000) == 0x0c000000) {
12560 if (tg3_nvram_read(tp
, offset
+ 4, &val
))
12567 dst_off
= strlen(tp
->fw_ver
);
12570 if (TG3_VER_SIZE
- dst_off
< 16 ||
12571 tg3_nvram_read(tp
, offset
+ 8, &ver_offset
))
12574 offset
= offset
+ ver_offset
- start
;
12575 for (i
= 0; i
< 16; i
+= 4) {
12577 if (tg3_nvram_read_be32(tp
, offset
+ i
, &v
))
12580 memcpy(tp
->fw_ver
+ dst_off
+ i
, &v
, sizeof(v
));
12585 if (tg3_nvram_read(tp
, TG3_NVM_PTREV_BCVER
, &ver_offset
))
12588 major
= (ver_offset
& TG3_NVM_BCVER_MAJMSK
) >>
12589 TG3_NVM_BCVER_MAJSFT
;
12590 minor
= ver_offset
& TG3_NVM_BCVER_MINMSK
;
12591 snprintf(&tp
->fw_ver
[dst_off
], TG3_VER_SIZE
- dst_off
,
12592 "v%d.%02d", major
, minor
);
12596 static void __devinit
tg3_read_hwsb_ver(struct tg3
*tp
)
12598 u32 val
, major
, minor
;
12600 /* Use native endian representation */
12601 if (tg3_nvram_read(tp
, TG3_NVM_HWSB_CFG1
, &val
))
12604 major
= (val
& TG3_NVM_HWSB_CFG1_MAJMSK
) >>
12605 TG3_NVM_HWSB_CFG1_MAJSFT
;
12606 minor
= (val
& TG3_NVM_HWSB_CFG1_MINMSK
) >>
12607 TG3_NVM_HWSB_CFG1_MINSFT
;
12609 snprintf(&tp
->fw_ver
[0], 32, "sb v%d.%02d", major
, minor
);
12612 static void __devinit
tg3_read_sb_ver(struct tg3
*tp
, u32 val
)
12614 u32 offset
, major
, minor
, build
;
12616 strncat(tp
->fw_ver
, "sb", TG3_VER_SIZE
- strlen(tp
->fw_ver
) - 1);
12618 if ((val
& TG3_EEPROM_SB_FORMAT_MASK
) != TG3_EEPROM_SB_FORMAT_1
)
12621 switch (val
& TG3_EEPROM_SB_REVISION_MASK
) {
12622 case TG3_EEPROM_SB_REVISION_0
:
12623 offset
= TG3_EEPROM_SB_F1R0_EDH_OFF
;
12625 case TG3_EEPROM_SB_REVISION_2
:
12626 offset
= TG3_EEPROM_SB_F1R2_EDH_OFF
;
12628 case TG3_EEPROM_SB_REVISION_3
:
12629 offset
= TG3_EEPROM_SB_F1R3_EDH_OFF
;
12631 case TG3_EEPROM_SB_REVISION_4
:
12632 offset
= TG3_EEPROM_SB_F1R4_EDH_OFF
;
12634 case TG3_EEPROM_SB_REVISION_5
:
12635 offset
= TG3_EEPROM_SB_F1R5_EDH_OFF
;
12641 if (tg3_nvram_read(tp
, offset
, &val
))
12644 build
= (val
& TG3_EEPROM_SB_EDH_BLD_MASK
) >>
12645 TG3_EEPROM_SB_EDH_BLD_SHFT
;
12646 major
= (val
& TG3_EEPROM_SB_EDH_MAJ_MASK
) >>
12647 TG3_EEPROM_SB_EDH_MAJ_SHFT
;
12648 minor
= val
& TG3_EEPROM_SB_EDH_MIN_MASK
;
12650 if (minor
> 99 || build
> 26)
12653 offset
= strlen(tp
->fw_ver
);
12654 snprintf(&tp
->fw_ver
[offset
], TG3_VER_SIZE
- offset
,
12655 " v%d.%02d", major
, minor
);
12658 offset
= strlen(tp
->fw_ver
);
12659 if (offset
< TG3_VER_SIZE
- 1)
12660 tp
->fw_ver
[offset
] = 'a' + build
- 1;
12664 static void __devinit
tg3_read_mgmtfw_ver(struct tg3
*tp
)
12666 u32 val
, offset
, start
;
12669 for (offset
= TG3_NVM_DIR_START
;
12670 offset
< TG3_NVM_DIR_END
;
12671 offset
+= TG3_NVM_DIRENT_SIZE
) {
12672 if (tg3_nvram_read(tp
, offset
, &val
))
12675 if ((val
>> TG3_NVM_DIRTYPE_SHIFT
) == TG3_NVM_DIRTYPE_ASFINI
)
12679 if (offset
== TG3_NVM_DIR_END
)
12682 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
12683 start
= 0x08000000;
12684 else if (tg3_nvram_read(tp
, offset
- 4, &start
))
12687 if (tg3_nvram_read(tp
, offset
+ 4, &offset
) ||
12688 !tg3_fw_img_is_valid(tp
, offset
) ||
12689 tg3_nvram_read(tp
, offset
+ 8, &val
))
12692 offset
+= val
- start
;
12694 vlen
= strlen(tp
->fw_ver
);
12696 tp
->fw_ver
[vlen
++] = ',';
12697 tp
->fw_ver
[vlen
++] = ' ';
12699 for (i
= 0; i
< 4; i
++) {
12701 if (tg3_nvram_read_be32(tp
, offset
, &v
))
12704 offset
+= sizeof(v
);
12706 if (vlen
> TG3_VER_SIZE
- sizeof(v
)) {
12707 memcpy(&tp
->fw_ver
[vlen
], &v
, TG3_VER_SIZE
- vlen
);
12711 memcpy(&tp
->fw_ver
[vlen
], &v
, sizeof(v
));
12716 static void __devinit
tg3_read_dash_ver(struct tg3
*tp
)
12721 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) ||
12722 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
12725 apedata
= tg3_ape_read32(tp
, TG3_APE_SEG_SIG
);
12726 if (apedata
!= APE_SEG_SIG_MAGIC
)
12729 apedata
= tg3_ape_read32(tp
, TG3_APE_FW_STATUS
);
12730 if (!(apedata
& APE_FW_STATUS_READY
))
12733 apedata
= tg3_ape_read32(tp
, TG3_APE_FW_VERSION
);
12735 vlen
= strlen(tp
->fw_ver
);
12737 snprintf(&tp
->fw_ver
[vlen
], TG3_VER_SIZE
- vlen
, " DASH v%d.%d.%d.%d",
12738 (apedata
& APE_FW_VERSION_MAJMSK
) >> APE_FW_VERSION_MAJSFT
,
12739 (apedata
& APE_FW_VERSION_MINMSK
) >> APE_FW_VERSION_MINSFT
,
12740 (apedata
& APE_FW_VERSION_REVMSK
) >> APE_FW_VERSION_REVSFT
,
12741 (apedata
& APE_FW_VERSION_BLDMSK
));
12744 static void __devinit
tg3_read_fw_ver(struct tg3
*tp
)
12747 bool vpd_vers
= false;
12749 if (tp
->fw_ver
[0] != 0)
12752 if (tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) {
12753 strcat(tp
->fw_ver
, "sb");
12757 if (tg3_nvram_read(tp
, 0, &val
))
12760 if (val
== TG3_EEPROM_MAGIC
)
12761 tg3_read_bc_ver(tp
);
12762 else if ((val
& TG3_EEPROM_MAGIC_FW_MSK
) == TG3_EEPROM_MAGIC_FW
)
12763 tg3_read_sb_ver(tp
, val
);
12764 else if ((val
& TG3_EEPROM_MAGIC_HW_MSK
) == TG3_EEPROM_MAGIC_HW
)
12765 tg3_read_hwsb_ver(tp
);
12769 if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) ||
12770 (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) || vpd_vers
)
12773 tg3_read_mgmtfw_ver(tp
);
12776 tp
->fw_ver
[TG3_VER_SIZE
- 1] = 0;
12779 static struct pci_dev
* __devinit
tg3_find_peer(struct tg3
*);
12781 static void inline vlan_features_add(struct net_device
*dev
, unsigned long flags
)
12783 #if TG3_VLAN_TAG_USED
12784 dev
->vlan_features
|= flags
;
12788 static int __devinit
tg3_get_invariants(struct tg3
*tp
)
12790 static struct pci_device_id write_reorder_chipsets
[] = {
12791 { PCI_DEVICE(PCI_VENDOR_ID_AMD
,
12792 PCI_DEVICE_ID_AMD_FE_GATE_700C
) },
12793 { PCI_DEVICE(PCI_VENDOR_ID_AMD
,
12794 PCI_DEVICE_ID_AMD_8131_BRIDGE
) },
12795 { PCI_DEVICE(PCI_VENDOR_ID_VIA
,
12796 PCI_DEVICE_ID_VIA_8385_0
) },
12800 u32 pci_state_reg
, grc_misc_cfg
;
12805 /* Force memory write invalidate off. If we leave it on,
12806 * then on 5700_BX chips we have to enable a workaround.
12807 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12808 * to match the cacheline size. The Broadcom driver have this
12809 * workaround but turns MWI off all the times so never uses
12810 * it. This seems to suggest that the workaround is insufficient.
12812 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
12813 pci_cmd
&= ~PCI_COMMAND_INVALIDATE
;
12814 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
12816 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12817 * has the register indirect write enable bit set before
12818 * we try to access any of the MMIO registers. It is also
12819 * critical that the PCI-X hw workaround situation is decided
12820 * before that as well.
12822 pci_read_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
12825 tp
->pci_chip_rev_id
= (misc_ctrl_reg
>>
12826 MISC_HOST_CTRL_CHIPREV_SHIFT
);
12827 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_USE_PROD_ID_REG
) {
12828 u32 prod_id_asic_rev
;
12830 if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5717
||
12831 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5718
||
12832 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5724
||
12833 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5719
)
12834 pci_read_config_dword(tp
->pdev
,
12835 TG3PCI_GEN2_PRODID_ASICREV
,
12836 &prod_id_asic_rev
);
12837 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57781
||
12838 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57785
||
12839 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57761
||
12840 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57765
||
12841 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57791
||
12842 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57795
)
12843 pci_read_config_dword(tp
->pdev
,
12844 TG3PCI_GEN15_PRODID_ASICREV
,
12845 &prod_id_asic_rev
);
12847 pci_read_config_dword(tp
->pdev
, TG3PCI_PRODID_ASICREV
,
12848 &prod_id_asic_rev
);
12850 tp
->pci_chip_rev_id
= prod_id_asic_rev
;
12853 /* Wrong chip ID in 5752 A0. This code can be removed later
12854 * as A0 is not in production.
12856 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5752_A0_HW
)
12857 tp
->pci_chip_rev_id
= CHIPREV_ID_5752_A0
;
12859 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12860 * we need to disable memory and use config. cycles
12861 * only to access all registers. The 5702/03 chips
12862 * can mistakenly decode the special cycles from the
12863 * ICH chipsets as memory write cycles, causing corruption
12864 * of register and memory space. Only certain ICH bridges
12865 * will drive special cycles with non-zero data during the
12866 * address phase which can fall within the 5703's address
12867 * range. This is not an ICH bug as the PCI spec allows
12868 * non-zero address during special cycles. However, only
12869 * these ICH bridges are known to drive non-zero addresses
12870 * during special cycles.
12872 * Since special cycles do not cross PCI bridges, we only
12873 * enable this workaround if the 5703 is on the secondary
12874 * bus of these ICH bridges.
12876 if ((tp
->pci_chip_rev_id
== CHIPREV_ID_5703_A1
) ||
12877 (tp
->pci_chip_rev_id
== CHIPREV_ID_5703_A2
)) {
12878 static struct tg3_dev_id
{
12882 } ich_chipsets
[] = {
12883 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AA_8
,
12885 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AB_8
,
12887 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_11
,
12889 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_6
,
12893 struct tg3_dev_id
*pci_id
= &ich_chipsets
[0];
12894 struct pci_dev
*bridge
= NULL
;
12896 while (pci_id
->vendor
!= 0) {
12897 bridge
= pci_get_device(pci_id
->vendor
, pci_id
->device
,
12903 if (pci_id
->rev
!= PCI_ANY_ID
) {
12904 if (bridge
->revision
> pci_id
->rev
)
12907 if (bridge
->subordinate
&&
12908 (bridge
->subordinate
->number
==
12909 tp
->pdev
->bus
->number
)) {
12911 tp
->tg3_flags2
|= TG3_FLG2_ICH_WORKAROUND
;
12912 pci_dev_put(bridge
);
12918 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)) {
12919 static struct tg3_dev_id
{
12922 } bridge_chipsets
[] = {
12923 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_0
},
12924 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_1
},
12927 struct tg3_dev_id
*pci_id
= &bridge_chipsets
[0];
12928 struct pci_dev
*bridge
= NULL
;
12930 while (pci_id
->vendor
!= 0) {
12931 bridge
= pci_get_device(pci_id
->vendor
,
12938 if (bridge
->subordinate
&&
12939 (bridge
->subordinate
->number
<=
12940 tp
->pdev
->bus
->number
) &&
12941 (bridge
->subordinate
->subordinate
>=
12942 tp
->pdev
->bus
->number
)) {
12943 tp
->tg3_flags3
|= TG3_FLG3_5701_DMA_BUG
;
12944 pci_dev_put(bridge
);
12950 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12951 * DMA addresses > 40-bit. This bridge may have other additional
12952 * 57xx devices behind it in some 4-port NIC designs for example.
12953 * Any tg3 device found behind the bridge will also need the 40-bit
12956 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5780
||
12957 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
) {
12958 tp
->tg3_flags2
|= TG3_FLG2_5780_CLASS
;
12959 tp
->tg3_flags
|= TG3_FLAG_40BIT_DMA_BUG
;
12960 tp
->msi_cap
= pci_find_capability(tp
->pdev
, PCI_CAP_ID_MSI
);
12962 struct pci_dev
*bridge
= NULL
;
12965 bridge
= pci_get_device(PCI_VENDOR_ID_SERVERWORKS
,
12966 PCI_DEVICE_ID_SERVERWORKS_EPB
,
12968 if (bridge
&& bridge
->subordinate
&&
12969 (bridge
->subordinate
->number
<=
12970 tp
->pdev
->bus
->number
) &&
12971 (bridge
->subordinate
->subordinate
>=
12972 tp
->pdev
->bus
->number
)) {
12973 tp
->tg3_flags
|= TG3_FLAG_40BIT_DMA_BUG
;
12974 pci_dev_put(bridge
);
12980 /* Initialize misc host control in PCI block. */
12981 tp
->misc_host_ctrl
|= (misc_ctrl_reg
&
12982 MISC_HOST_CTRL_CHIPREV
);
12983 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
12984 tp
->misc_host_ctrl
);
12986 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
12987 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
||
12988 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
)
12989 tp
->pdev_peer
= tg3_find_peer(tp
);
12991 /* Intentionally exclude ASIC_REV_5906 */
12992 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
||
12993 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5787
||
12994 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
12995 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
12996 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
12997 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
||
12998 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
12999 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
||
13000 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
13001 tp
->tg3_flags3
|= TG3_FLG3_5755_PLUS
;
13003 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
||
13004 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
||
13005 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
||
13006 (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) ||
13007 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
13008 tp
->tg3_flags2
|= TG3_FLG2_5750_PLUS
;
13010 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) ||
13011 (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
))
13012 tp
->tg3_flags2
|= TG3_FLG2_5705_PLUS
;
13014 /* 5700 B0 chips do not support checksumming correctly due
13015 * to hardware bugs.
13017 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5700_B0
)
13018 tp
->tg3_flags
|= TG3_FLAG_BROKEN_CHECKSUMS
;
13020 unsigned long features
= NETIF_F_IP_CSUM
| NETIF_F_SG
| NETIF_F_GRO
;
13022 tp
->tg3_flags
|= TG3_FLAG_RX_CHECKSUMS
;
13023 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
13024 features
|= NETIF_F_IPV6_CSUM
;
13025 tp
->dev
->features
|= features
;
13026 vlan_features_add(tp
->dev
, features
);
13029 /* Determine TSO capabilities */
13030 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
13031 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
||
13032 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
13033 tp
->tg3_flags2
|= TG3_FLG2_HW_TSO_3
;
13034 else if ((tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) ||
13035 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
13036 tp
->tg3_flags2
|= TG3_FLG2_HW_TSO_2
;
13037 else if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) {
13038 tp
->tg3_flags2
|= TG3_FLG2_HW_TSO_1
| TG3_FLG2_TSO_BUG
;
13039 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
&&
13040 tp
->pci_chip_rev_id
>= CHIPREV_ID_5750_C2
)
13041 tp
->tg3_flags2
&= ~TG3_FLG2_TSO_BUG
;
13042 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
13043 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
&&
13044 tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A0
) {
13045 tp
->tg3_flags2
|= TG3_FLG2_TSO_BUG
;
13046 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
)
13047 tp
->fw_needed
= FIRMWARE_TG3TSO5
;
13049 tp
->fw_needed
= FIRMWARE_TG3TSO
;
13054 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) {
13055 tp
->tg3_flags
|= TG3_FLAG_SUPPORT_MSI
;
13056 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_AX
||
13057 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_BX
||
13058 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
&&
13059 tp
->pci_chip_rev_id
<= CHIPREV_ID_5714_A2
&&
13060 tp
->pdev_peer
== tp
->pdev
))
13061 tp
->tg3_flags
&= ~TG3_FLAG_SUPPORT_MSI
;
13063 if ((tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) ||
13064 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
13065 tp
->tg3_flags2
|= TG3_FLG2_1SHOT_MSI
;
13068 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
13069 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
||
13070 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
) {
13071 tp
->tg3_flags
|= TG3_FLAG_SUPPORT_MSIX
;
13072 tp
->irq_max
= TG3_IRQ_MAX_VECS
;
13076 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
13077 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
||
13078 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
13079 tp
->tg3_flags3
|= TG3_FLG3_SHORT_DMA_BUG
;
13080 else if (!(tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)) {
13081 tp
->tg3_flags3
|= TG3_FLG3_4G_DMA_BNDRY_BUG
;
13082 tp
->tg3_flags3
|= TG3_FLG3_40BIT_DMA_LIMIT_BUG
;
13085 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
13086 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
||
13087 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
13088 tp
->tg3_flags3
|= TG3_FLG3_USE_JUMBO_BDFLAG
;
13090 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) ||
13091 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) ||
13092 (tp
->tg3_flags3
& TG3_FLG3_USE_JUMBO_BDFLAG
))
13093 tp
->tg3_flags
|= TG3_FLAG_JUMBO_CAPABLE
;
13095 pci_read_config_dword(tp
->pdev
, TG3PCI_PCISTATE
,
13098 tp
->pcie_cap
= pci_find_capability(tp
->pdev
, PCI_CAP_ID_EXP
);
13099 if (tp
->pcie_cap
!= 0) {
13102 tp
->tg3_flags2
|= TG3_FLG2_PCI_EXPRESS
;
13104 pcie_set_readrq(tp
->pdev
, 4096);
13106 pci_read_config_word(tp
->pdev
,
13107 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
13109 if (lnkctl
& PCI_EXP_LNKCTL_CLKREQ_EN
) {
13110 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
13111 tp
->tg3_flags2
&= ~TG3_FLG2_HW_TSO_2
;
13112 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
13113 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
13114 tp
->pci_chip_rev_id
== CHIPREV_ID_57780_A0
||
13115 tp
->pci_chip_rev_id
== CHIPREV_ID_57780_A1
)
13116 tp
->tg3_flags3
|= TG3_FLG3_CLKREQ_BUG
;
13117 } else if (tp
->pci_chip_rev_id
== CHIPREV_ID_5717_A0
) {
13118 tp
->tg3_flags3
|= TG3_FLG3_L1PLLPD_EN
;
13120 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
) {
13121 tp
->tg3_flags2
|= TG3_FLG2_PCI_EXPRESS
;
13122 } else if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) ||
13123 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
13124 tp
->pcix_cap
= pci_find_capability(tp
->pdev
, PCI_CAP_ID_PCIX
);
13125 if (!tp
->pcix_cap
) {
13126 dev_err(&tp
->pdev
->dev
,
13127 "Cannot find PCI-X capability, aborting\n");
13131 if (!(pci_state_reg
& PCISTATE_CONV_PCI_MODE
))
13132 tp
->tg3_flags
|= TG3_FLAG_PCIX_MODE
;
13135 /* If we have an AMD 762 or VIA K8T800 chipset, write
13136 * reordering to the mailbox registers done by the host
13137 * controller can cause major troubles. We read back from
13138 * every mailbox register write to force the writes to be
13139 * posted to the chip in order.
13141 if (pci_dev_present(write_reorder_chipsets
) &&
13142 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
))
13143 tp
->tg3_flags
|= TG3_FLAG_MBOX_WRITE_REORDER
;
13145 pci_read_config_byte(tp
->pdev
, PCI_CACHE_LINE_SIZE
,
13146 &tp
->pci_cacheline_sz
);
13147 pci_read_config_byte(tp
->pdev
, PCI_LATENCY_TIMER
,
13148 &tp
->pci_lat_timer
);
13149 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
&&
13150 tp
->pci_lat_timer
< 64) {
13151 tp
->pci_lat_timer
= 64;
13152 pci_write_config_byte(tp
->pdev
, PCI_LATENCY_TIMER
,
13153 tp
->pci_lat_timer
);
13156 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5700_BX
) {
13157 /* 5700 BX chips need to have their TX producer index
13158 * mailboxes written twice to workaround a bug.
13160 tp
->tg3_flags
|= TG3_FLAG_TXD_MBOX_HWBUG
;
13162 /* If we are in PCI-X mode, enable register write workaround.
13164 * The workaround is to use indirect register accesses
13165 * for all chip writes not to mailbox registers.
13167 if (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) {
13170 tp
->tg3_flags
|= TG3_FLAG_PCIX_TARGET_HWBUG
;
13172 /* The chip can have it's power management PCI config
13173 * space registers clobbered due to this bug.
13174 * So explicitly force the chip into D0 here.
13176 pci_read_config_dword(tp
->pdev
,
13177 tp
->pm_cap
+ PCI_PM_CTRL
,
13179 pm_reg
&= ~PCI_PM_CTRL_STATE_MASK
;
13180 pm_reg
|= PCI_PM_CTRL_PME_ENABLE
| 0 /* D0 */;
13181 pci_write_config_dword(tp
->pdev
,
13182 tp
->pm_cap
+ PCI_PM_CTRL
,
13185 /* Also, force SERR#/PERR# in PCI command. */
13186 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
13187 pci_cmd
|= PCI_COMMAND_PARITY
| PCI_COMMAND_SERR
;
13188 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
13192 if ((pci_state_reg
& PCISTATE_BUS_SPEED_HIGH
) != 0)
13193 tp
->tg3_flags
|= TG3_FLAG_PCI_HIGH_SPEED
;
13194 if ((pci_state_reg
& PCISTATE_BUS_32BIT
) != 0)
13195 tp
->tg3_flags
|= TG3_FLAG_PCI_32BIT
;
13197 /* Chip-specific fixup from Broadcom driver */
13198 if ((tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
) &&
13199 (!(pci_state_reg
& PCISTATE_RETRY_SAME_DMA
))) {
13200 pci_state_reg
|= PCISTATE_RETRY_SAME_DMA
;
13201 pci_write_config_dword(tp
->pdev
, TG3PCI_PCISTATE
, pci_state_reg
);
13204 /* Default fast path register access methods */
13205 tp
->read32
= tg3_read32
;
13206 tp
->write32
= tg3_write32
;
13207 tp
->read32_mbox
= tg3_read32
;
13208 tp
->write32_mbox
= tg3_write32
;
13209 tp
->write32_tx_mbox
= tg3_write32
;
13210 tp
->write32_rx_mbox
= tg3_write32
;
13212 /* Various workaround register access methods */
13213 if (tp
->tg3_flags
& TG3_FLAG_PCIX_TARGET_HWBUG
)
13214 tp
->write32
= tg3_write_indirect_reg32
;
13215 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
||
13216 ((tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) &&
13217 tp
->pci_chip_rev_id
== CHIPREV_ID_5750_A0
)) {
13219 * Back to back register writes can cause problems on these
13220 * chips, the workaround is to read back all reg writes
13221 * except those to mailbox regs.
13223 * See tg3_write_indirect_reg32().
13225 tp
->write32
= tg3_write_flush_reg32
;
13228 if ((tp
->tg3_flags
& TG3_FLAG_TXD_MBOX_HWBUG
) ||
13229 (tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
)) {
13230 tp
->write32_tx_mbox
= tg3_write32_tx_mbox
;
13231 if (tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
)
13232 tp
->write32_rx_mbox
= tg3_write_flush_reg32
;
13235 if (tp
->tg3_flags2
& TG3_FLG2_ICH_WORKAROUND
) {
13236 tp
->read32
= tg3_read_indirect_reg32
;
13237 tp
->write32
= tg3_write_indirect_reg32
;
13238 tp
->read32_mbox
= tg3_read_indirect_mbox
;
13239 tp
->write32_mbox
= tg3_write_indirect_mbox
;
13240 tp
->write32_tx_mbox
= tg3_write_indirect_mbox
;
13241 tp
->write32_rx_mbox
= tg3_write_indirect_mbox
;
13246 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
13247 pci_cmd
&= ~PCI_COMMAND_MEMORY
;
13248 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
13250 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
13251 tp
->read32_mbox
= tg3_read32_mbox_5906
;
13252 tp
->write32_mbox
= tg3_write32_mbox_5906
;
13253 tp
->write32_tx_mbox
= tg3_write32_mbox_5906
;
13254 tp
->write32_rx_mbox
= tg3_write32_mbox_5906
;
13257 if (tp
->write32
== tg3_write_indirect_reg32
||
13258 ((tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) &&
13259 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
13260 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)))
13261 tp
->tg3_flags
|= TG3_FLAG_SRAM_USE_CONFIG
;
13263 /* Get eeprom hw config before calling tg3_set_power_state().
13264 * In particular, the TG3_FLG2_IS_NIC flag must be
13265 * determined before calling tg3_set_power_state() so that
13266 * we know whether or not to switch out of Vaux power.
13267 * When the flag is set, it means that GPIO1 is used for eeprom
13268 * write protect and also implies that it is a LOM where GPIOs
13269 * are not used to switch power.
13271 tg3_get_eeprom_hw_cfg(tp
);
13273 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
13274 /* Allow reads and writes to the
13275 * APE register and memory space.
13277 pci_state_reg
|= PCISTATE_ALLOW_APE_CTLSPC_WR
|
13278 PCISTATE_ALLOW_APE_SHMEM_WR
|
13279 PCISTATE_ALLOW_APE_PSPACE_WR
;
13280 pci_write_config_dword(tp
->pdev
, TG3PCI_PCISTATE
,
13284 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
13285 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
13286 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
13287 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
||
13288 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
13289 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
||
13290 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
13291 tp
->tg3_flags
|= TG3_FLAG_CPMU_PRESENT
;
13293 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13294 * GPIO1 driven high will bring 5700's external PHY out of reset.
13295 * It is also used as eeprom write protect on LOMs.
13297 tp
->grc_local_ctrl
= GRC_LCLCTRL_INT_ON_ATTN
| GRC_LCLCTRL_AUTO_SEEPROM
;
13298 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) ||
13299 (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
))
13300 tp
->grc_local_ctrl
|= (GRC_LCLCTRL_GPIO_OE1
|
13301 GRC_LCLCTRL_GPIO_OUTPUT1
);
13302 /* Unused GPIO3 must be driven as output on 5752 because there
13303 * are no pull-up resistors on unused GPIO pins.
13305 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
)
13306 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE3
;
13308 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
||
13309 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
||
13310 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
13311 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_UART_SEL
;
13313 if (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5761
||
13314 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5761S
) {
13315 /* Turn off the debug UART. */
13316 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_UART_SEL
;
13317 if (tp
->tg3_flags2
& TG3_FLG2_IS_NIC
)
13318 /* Keep VMain power. */
13319 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE0
|
13320 GRC_LCLCTRL_GPIO_OUTPUT0
;
13323 /* Force the chip into D0. */
13324 err
= tg3_set_power_state(tp
, PCI_D0
);
13326 dev_err(&tp
->pdev
->dev
, "Transition to D0 failed\n");
13330 /* Derive initial jumbo mode from MTU assigned in
13331 * ether_setup() via the alloc_etherdev() call
13333 if (tp
->dev
->mtu
> ETH_DATA_LEN
&&
13334 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
13335 tp
->tg3_flags
|= TG3_FLAG_JUMBO_RING_ENABLE
;
13337 /* Determine WakeOnLan speed to use. */
13338 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
13339 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
13340 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
||
13341 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B2
) {
13342 tp
->tg3_flags
&= ~(TG3_FLAG_WOL_SPEED_100MB
);
13344 tp
->tg3_flags
|= TG3_FLAG_WOL_SPEED_100MB
;
13347 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
13348 tp
->tg3_flags3
|= TG3_FLG3_PHY_IS_FET
;
13350 /* A few boards don't want Ethernet@WireSpeed phy feature */
13351 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) ||
13352 ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) &&
13353 (tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A0
) &&
13354 (tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A1
)) ||
13355 (tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
) ||
13356 (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
))
13357 tp
->tg3_flags2
|= TG3_FLG2_NO_ETH_WIRE_SPEED
;
13359 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5703_AX
||
13360 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5704_AX
)
13361 tp
->tg3_flags2
|= TG3_FLG2_PHY_ADC_BUG
;
13362 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
)
13363 tp
->tg3_flags2
|= TG3_FLG2_PHY_5704_A0_BUG
;
13365 if ((tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
13366 !(tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
) &&
13367 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5785
&&
13368 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_57780
&&
13369 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5717
&&
13370 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5719
&&
13371 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_57765
) {
13372 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
||
13373 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5787
||
13374 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
13375 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
) {
13376 if (tp
->pdev
->device
!= PCI_DEVICE_ID_TIGON3_5756
&&
13377 tp
->pdev
->device
!= PCI_DEVICE_ID_TIGON3_5722
)
13378 tp
->tg3_flags2
|= TG3_FLG2_PHY_JITTER_BUG
;
13379 if (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5755M
)
13380 tp
->tg3_flags2
|= TG3_FLG2_PHY_ADJUST_TRIM
;
13382 tp
->tg3_flags2
|= TG3_FLG2_PHY_BER_BUG
;
13385 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
13386 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
) {
13387 tp
->phy_otp
= tg3_read_otp_phycfg(tp
);
13388 if (tp
->phy_otp
== 0)
13389 tp
->phy_otp
= TG3_OTP_DEFAULT
;
13392 if (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
)
13393 tp
->mi_mode
= MAC_MI_MODE_500KHZ_CONST
;
13395 tp
->mi_mode
= MAC_MI_MODE_BASE
;
13397 tp
->coalesce_mode
= 0;
13398 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5700_AX
&&
13399 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5700_BX
)
13400 tp
->coalesce_mode
|= HOSTCC_MODE_32BYTE
;
13402 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
13403 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
13404 tp
->tg3_flags3
|= TG3_FLG3_USE_PHYLIB
;
13406 err
= tg3_mdio_init(tp
);
13410 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
&&
13411 tp
->pci_chip_rev_id
!= CHIPREV_ID_5717_A0
)
13414 /* Initialize data/descriptor byte/word swapping. */
13415 val
= tr32(GRC_MODE
);
13416 val
&= GRC_MODE_HOST_STACKUP
;
13417 tw32(GRC_MODE
, val
| tp
->grc_mode
);
13419 tg3_switch_clocks(tp
);
13421 /* Clear this out for sanity. */
13422 tw32(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
13424 pci_read_config_dword(tp
->pdev
, TG3PCI_PCISTATE
,
13426 if ((pci_state_reg
& PCISTATE_CONV_PCI_MODE
) == 0 &&
13427 (tp
->tg3_flags
& TG3_FLAG_PCIX_TARGET_HWBUG
) == 0) {
13428 u32 chiprevid
= GET_CHIP_REV_ID(tp
->misc_host_ctrl
);
13430 if (chiprevid
== CHIPREV_ID_5701_A0
||
13431 chiprevid
== CHIPREV_ID_5701_B0
||
13432 chiprevid
== CHIPREV_ID_5701_B2
||
13433 chiprevid
== CHIPREV_ID_5701_B5
) {
13434 void __iomem
*sram_base
;
13436 /* Write some dummy words into the SRAM status block
13437 * area, see if it reads back correctly. If the return
13438 * value is bad, force enable the PCIX workaround.
13440 sram_base
= tp
->regs
+ NIC_SRAM_WIN_BASE
+ NIC_SRAM_STATS_BLK
;
13442 writel(0x00000000, sram_base
);
13443 writel(0x00000000, sram_base
+ 4);
13444 writel(0xffffffff, sram_base
+ 4);
13445 if (readl(sram_base
) != 0x00000000)
13446 tp
->tg3_flags
|= TG3_FLAG_PCIX_TARGET_HWBUG
;
13451 tg3_nvram_init(tp
);
13453 grc_misc_cfg
= tr32(GRC_MISC_CFG
);
13454 grc_misc_cfg
&= GRC_MISC_CFG_BOARD_ID_MASK
;
13456 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
13457 (grc_misc_cfg
== GRC_MISC_CFG_BOARD_ID_5788
||
13458 grc_misc_cfg
== GRC_MISC_CFG_BOARD_ID_5788M
))
13459 tp
->tg3_flags2
|= TG3_FLG2_IS_5788
;
13461 if (!(tp
->tg3_flags2
& TG3_FLG2_IS_5788
) &&
13462 (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
))
13463 tp
->tg3_flags
|= TG3_FLAG_TAGGED_STATUS
;
13464 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) {
13465 tp
->coalesce_mode
|= (HOSTCC_MODE_CLRTICK_RXBD
|
13466 HOSTCC_MODE_CLRTICK_TXBD
);
13468 tp
->misc_host_ctrl
|= MISC_HOST_CTRL_TAGGED_STATUS
;
13469 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
13470 tp
->misc_host_ctrl
);
13473 /* Preserve the APE MAC_MODE bits */
13474 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
13475 tp
->mac_mode
= tr32(MAC_MODE
) |
13476 MAC_MODE_APE_TX_EN
| MAC_MODE_APE_RX_EN
;
13478 tp
->mac_mode
= TG3_DEF_MAC_MODE
;
13480 /* these are limited to 10/100 only */
13481 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
&&
13482 (grc_misc_cfg
== 0x8000 || grc_misc_cfg
== 0x4000)) ||
13483 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
13484 tp
->pdev
->vendor
== PCI_VENDOR_ID_BROADCOM
&&
13485 (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5901
||
13486 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5901_2
||
13487 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5705F
)) ||
13488 (tp
->pdev
->vendor
== PCI_VENDOR_ID_BROADCOM
&&
13489 (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5751F
||
13490 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5753F
||
13491 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5787F
)) ||
13492 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57790
||
13493 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57791
||
13494 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57795
||
13495 (tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
))
13496 tp
->tg3_flags
|= TG3_FLAG_10_100_ONLY
;
13498 err
= tg3_phy_probe(tp
);
13500 dev_err(&tp
->pdev
->dev
, "phy probe failed, err %d\n", err
);
13501 /* ... but do not return immediately ... */
13506 tg3_read_fw_ver(tp
);
13508 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
13509 tp
->tg3_flags
&= ~TG3_FLAG_USE_MI_INTERRUPT
;
13511 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
)
13512 tp
->tg3_flags
|= TG3_FLAG_USE_MI_INTERRUPT
;
13514 tp
->tg3_flags
&= ~TG3_FLAG_USE_MI_INTERRUPT
;
13517 /* 5700 {AX,BX} chips have a broken status block link
13518 * change bit implementation, so we must use the
13519 * status register in those cases.
13521 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
)
13522 tp
->tg3_flags
|= TG3_FLAG_USE_LINKCHG_REG
;
13524 tp
->tg3_flags
&= ~TG3_FLAG_USE_LINKCHG_REG
;
13526 /* The led_ctrl is set during tg3_phy_probe, here we might
13527 * have to force the link status polling mechanism based
13528 * upon subsystem IDs.
13530 if (tp
->pdev
->subsystem_vendor
== PCI_VENDOR_ID_DELL
&&
13531 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
&&
13532 !(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)) {
13533 tp
->tg3_flags
|= (TG3_FLAG_USE_MI_INTERRUPT
|
13534 TG3_FLAG_USE_LINKCHG_REG
);
13537 /* For all SERDES we poll the MAC status register. */
13538 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)
13539 tp
->tg3_flags
|= TG3_FLAG_POLL_SERDES
;
13541 tp
->tg3_flags
&= ~TG3_FLAG_POLL_SERDES
;
13543 tp
->rx_offset
= NET_IP_ALIGN
+ TG3_RX_HEADROOM
;
13544 tp
->rx_copy_thresh
= TG3_RX_COPY_THRESHOLD
;
13545 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
&&
13546 (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) != 0) {
13547 tp
->rx_offset
-= NET_IP_ALIGN
;
13548 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
13549 tp
->rx_copy_thresh
= ~(u16
)0;
13553 tp
->rx_std_max_post
= TG3_RX_RING_SIZE
;
13555 /* Increment the rx prod index on the rx std ring by at most
13556 * 8 for these chips to workaround hw errata.
13558 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
||
13559 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
||
13560 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
)
13561 tp
->rx_std_max_post
= 8;
13563 if (tp
->tg3_flags
& TG3_FLAG_ASPM_WORKAROUND
)
13564 tp
->pwrmgmt_thresh
= tr32(PCIE_PWR_MGMT_THRESH
) &
13565 PCIE_PWR_MGMT_L1_THRESH_MSK
;
13570 #ifdef CONFIG_SPARC
13571 static int __devinit
tg3_get_macaddr_sparc(struct tg3
*tp
)
13573 struct net_device
*dev
= tp
->dev
;
13574 struct pci_dev
*pdev
= tp
->pdev
;
13575 struct device_node
*dp
= pci_device_to_OF_node(pdev
);
13576 const unsigned char *addr
;
13579 addr
= of_get_property(dp
, "local-mac-address", &len
);
13580 if (addr
&& len
== 6) {
13581 memcpy(dev
->dev_addr
, addr
, 6);
13582 memcpy(dev
->perm_addr
, dev
->dev_addr
, 6);
13588 static int __devinit
tg3_get_default_macaddr_sparc(struct tg3
*tp
)
13590 struct net_device
*dev
= tp
->dev
;
13592 memcpy(dev
->dev_addr
, idprom
->id_ethaddr
, 6);
13593 memcpy(dev
->perm_addr
, idprom
->id_ethaddr
, 6);
13598 static int __devinit
tg3_get_device_address(struct tg3
*tp
)
13600 struct net_device
*dev
= tp
->dev
;
13601 u32 hi
, lo
, mac_offset
;
13604 #ifdef CONFIG_SPARC
13605 if (!tg3_get_macaddr_sparc(tp
))
13610 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) ||
13611 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
13612 if (tr32(TG3PCI_DUAL_MAC_CTRL
) & DUAL_MAC_CTRL_ID
)
13614 if (tg3_nvram_lock(tp
))
13615 tw32_f(NVRAM_CMD
, NVRAM_CMD_RESET
);
13617 tg3_nvram_unlock(tp
);
13618 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
13619 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
) {
13620 if (PCI_FUNC(tp
->pdev
->devfn
) & 1)
13622 if (PCI_FUNC(tp
->pdev
->devfn
) > 1)
13623 mac_offset
+= 0x18c;
13624 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
13627 /* First try to get it from MAC address mailbox. */
13628 tg3_read_mem(tp
, NIC_SRAM_MAC_ADDR_HIGH_MBOX
, &hi
);
13629 if ((hi
>> 16) == 0x484b) {
13630 dev
->dev_addr
[0] = (hi
>> 8) & 0xff;
13631 dev
->dev_addr
[1] = (hi
>> 0) & 0xff;
13633 tg3_read_mem(tp
, NIC_SRAM_MAC_ADDR_LOW_MBOX
, &lo
);
13634 dev
->dev_addr
[2] = (lo
>> 24) & 0xff;
13635 dev
->dev_addr
[3] = (lo
>> 16) & 0xff;
13636 dev
->dev_addr
[4] = (lo
>> 8) & 0xff;
13637 dev
->dev_addr
[5] = (lo
>> 0) & 0xff;
13639 /* Some old bootcode may report a 0 MAC address in SRAM */
13640 addr_ok
= is_valid_ether_addr(&dev
->dev_addr
[0]);
13643 /* Next, try NVRAM. */
13644 if (!(tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) &&
13645 !tg3_nvram_read_be32(tp
, mac_offset
+ 0, &hi
) &&
13646 !tg3_nvram_read_be32(tp
, mac_offset
+ 4, &lo
)) {
13647 memcpy(&dev
->dev_addr
[0], ((char *)&hi
) + 2, 2);
13648 memcpy(&dev
->dev_addr
[2], (char *)&lo
, sizeof(lo
));
13650 /* Finally just fetch it out of the MAC control regs. */
13652 hi
= tr32(MAC_ADDR_0_HIGH
);
13653 lo
= tr32(MAC_ADDR_0_LOW
);
13655 dev
->dev_addr
[5] = lo
& 0xff;
13656 dev
->dev_addr
[4] = (lo
>> 8) & 0xff;
13657 dev
->dev_addr
[3] = (lo
>> 16) & 0xff;
13658 dev
->dev_addr
[2] = (lo
>> 24) & 0xff;
13659 dev
->dev_addr
[1] = hi
& 0xff;
13660 dev
->dev_addr
[0] = (hi
>> 8) & 0xff;
13664 if (!is_valid_ether_addr(&dev
->dev_addr
[0])) {
13665 #ifdef CONFIG_SPARC
13666 if (!tg3_get_default_macaddr_sparc(tp
))
13671 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
13675 #define BOUNDARY_SINGLE_CACHELINE 1
13676 #define BOUNDARY_MULTI_CACHELINE 2
13678 static u32 __devinit
tg3_calc_dma_bndry(struct tg3
*tp
, u32 val
)
13680 int cacheline_size
;
13684 pci_read_config_byte(tp
->pdev
, PCI_CACHE_LINE_SIZE
, &byte
);
13686 cacheline_size
= 1024;
13688 cacheline_size
= (int) byte
* 4;
13690 /* On 5703 and later chips, the boundary bits have no
13693 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
13694 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
&&
13695 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
))
13698 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13699 goal
= BOUNDARY_MULTI_CACHELINE
;
13701 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13702 goal
= BOUNDARY_SINGLE_CACHELINE
;
13708 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
13709 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
||
13710 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
) {
13711 val
= goal
? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT
;
13718 /* PCI controllers on most RISC systems tend to disconnect
13719 * when a device tries to burst across a cache-line boundary.
13720 * Therefore, letting tg3 do so just wastes PCI bandwidth.
13722 * Unfortunately, for PCI-E there are only limited
13723 * write-side controls for this, and thus for reads
13724 * we will still get the disconnects. We'll also waste
13725 * these PCI cycles for both read and write for chips
13726 * other than 5700 and 5701 which do not implement the
13729 if ((tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) &&
13730 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)) {
13731 switch (cacheline_size
) {
13736 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
13737 val
|= (DMA_RWCTRL_READ_BNDRY_128_PCIX
|
13738 DMA_RWCTRL_WRITE_BNDRY_128_PCIX
);
13740 val
|= (DMA_RWCTRL_READ_BNDRY_384_PCIX
|
13741 DMA_RWCTRL_WRITE_BNDRY_384_PCIX
);
13746 val
|= (DMA_RWCTRL_READ_BNDRY_256_PCIX
|
13747 DMA_RWCTRL_WRITE_BNDRY_256_PCIX
);
13751 val
|= (DMA_RWCTRL_READ_BNDRY_384_PCIX
|
13752 DMA_RWCTRL_WRITE_BNDRY_384_PCIX
);
13755 } else if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
13756 switch (cacheline_size
) {
13760 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
13761 val
&= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE
;
13762 val
|= DMA_RWCTRL_WRITE_BNDRY_64_PCIE
;
13768 val
&= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE
;
13769 val
|= DMA_RWCTRL_WRITE_BNDRY_128_PCIE
;
13773 switch (cacheline_size
) {
13775 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
13776 val
|= (DMA_RWCTRL_READ_BNDRY_16
|
13777 DMA_RWCTRL_WRITE_BNDRY_16
);
13782 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
13783 val
|= (DMA_RWCTRL_READ_BNDRY_32
|
13784 DMA_RWCTRL_WRITE_BNDRY_32
);
13789 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
13790 val
|= (DMA_RWCTRL_READ_BNDRY_64
|
13791 DMA_RWCTRL_WRITE_BNDRY_64
);
13796 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
13797 val
|= (DMA_RWCTRL_READ_BNDRY_128
|
13798 DMA_RWCTRL_WRITE_BNDRY_128
);
13803 val
|= (DMA_RWCTRL_READ_BNDRY_256
|
13804 DMA_RWCTRL_WRITE_BNDRY_256
);
13807 val
|= (DMA_RWCTRL_READ_BNDRY_512
|
13808 DMA_RWCTRL_WRITE_BNDRY_512
);
13812 val
|= (DMA_RWCTRL_READ_BNDRY_1024
|
13813 DMA_RWCTRL_WRITE_BNDRY_1024
);
13822 static int __devinit
tg3_do_test_dma(struct tg3
*tp
, u32
*buf
, dma_addr_t buf_dma
, int size
, int to_device
)
13824 struct tg3_internal_buffer_desc test_desc
;
13825 u32 sram_dma_descs
;
13828 sram_dma_descs
= NIC_SRAM_DMA_DESC_POOL_BASE
;
13830 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ
, 0);
13831 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ
, 0);
13832 tw32(RDMAC_STATUS
, 0);
13833 tw32(WDMAC_STATUS
, 0);
13835 tw32(BUFMGR_MODE
, 0);
13836 tw32(FTQ_RESET
, 0);
13838 test_desc
.addr_hi
= ((u64
) buf_dma
) >> 32;
13839 test_desc
.addr_lo
= buf_dma
& 0xffffffff;
13840 test_desc
.nic_mbuf
= 0x00002100;
13841 test_desc
.len
= size
;
13844 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13845 * the *second* time the tg3 driver was getting loaded after an
13848 * Broadcom tells me:
13849 * ...the DMA engine is connected to the GRC block and a DMA
13850 * reset may affect the GRC block in some unpredictable way...
13851 * The behavior of resets to individual blocks has not been tested.
13853 * Broadcom noted the GRC reset will also reset all sub-components.
13856 test_desc
.cqid_sqid
= (13 << 8) | 2;
13858 tw32_f(RDMAC_MODE
, RDMAC_MODE_ENABLE
);
13861 test_desc
.cqid_sqid
= (16 << 8) | 7;
13863 tw32_f(WDMAC_MODE
, WDMAC_MODE_ENABLE
);
13866 test_desc
.flags
= 0x00000005;
13868 for (i
= 0; i
< (sizeof(test_desc
) / sizeof(u32
)); i
++) {
13871 val
= *(((u32
*)&test_desc
) + i
);
13872 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
,
13873 sram_dma_descs
+ (i
* sizeof(u32
)));
13874 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_DATA
, val
);
13876 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, 0);
13879 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ
, sram_dma_descs
);
13881 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ
, sram_dma_descs
);
13884 for (i
= 0; i
< 40; i
++) {
13888 val
= tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ
);
13890 val
= tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ
);
13891 if ((val
& 0xffff) == sram_dma_descs
) {
13902 #define TEST_BUFFER_SIZE 0x2000
13904 static int __devinit
tg3_test_dma(struct tg3
*tp
)
13906 dma_addr_t buf_dma
;
13907 u32
*buf
, saved_dma_rwctrl
;
13910 buf
= pci_alloc_consistent(tp
->pdev
, TEST_BUFFER_SIZE
, &buf_dma
);
13916 tp
->dma_rwctrl
= ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT
) |
13917 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT
));
13919 tp
->dma_rwctrl
= tg3_calc_dma_bndry(tp
, tp
->dma_rwctrl
);
13921 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
13922 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
||
13923 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
13926 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
13927 /* DMA read watermark not used on PCIE */
13928 tp
->dma_rwctrl
|= 0x00180000;
13929 } else if (!(tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
)) {
13930 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
||
13931 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
)
13932 tp
->dma_rwctrl
|= 0x003f0000;
13934 tp
->dma_rwctrl
|= 0x003f000f;
13936 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
13937 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
13938 u32 ccval
= (tr32(TG3PCI_CLOCK_CTRL
) & 0x1f);
13939 u32 read_water
= 0x7;
13941 /* If the 5704 is behind the EPB bridge, we can
13942 * do the less restrictive ONE_DMA workaround for
13943 * better performance.
13945 if ((tp
->tg3_flags
& TG3_FLAG_40BIT_DMA_BUG
) &&
13946 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
)
13947 tp
->dma_rwctrl
|= 0x8000;
13948 else if (ccval
== 0x6 || ccval
== 0x7)
13949 tp
->dma_rwctrl
|= DMA_RWCTRL_ONE_DMA
;
13951 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
)
13953 /* Set bit 23 to enable PCIX hw bug fix */
13955 (read_water
<< DMA_RWCTRL_READ_WATER_SHIFT
) |
13956 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT
) |
13958 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5780
) {
13959 /* 5780 always in PCIX mode */
13960 tp
->dma_rwctrl
|= 0x00144000;
13961 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
) {
13962 /* 5714 always in PCIX mode */
13963 tp
->dma_rwctrl
|= 0x00148000;
13965 tp
->dma_rwctrl
|= 0x001b000f;
13969 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
13970 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
)
13971 tp
->dma_rwctrl
&= 0xfffffff0;
13973 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
13974 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
13975 /* Remove this if it causes problems for some boards. */
13976 tp
->dma_rwctrl
|= DMA_RWCTRL_USE_MEM_READ_MULT
;
13978 /* On 5700/5701 chips, we need to set this bit.
13979 * Otherwise the chip will issue cacheline transactions
13980 * to streamable DMA memory with not all the byte
13981 * enables turned on. This is an error on several
13982 * RISC PCI controllers, in particular sparc64.
13984 * On 5703/5704 chips, this bit has been reassigned
13985 * a different meaning. In particular, it is used
13986 * on those chips to enable a PCI-X workaround.
13988 tp
->dma_rwctrl
|= DMA_RWCTRL_ASSERT_ALL_BE
;
13991 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
13994 /* Unneeded, already done by tg3_get_invariants. */
13995 tg3_switch_clocks(tp
);
13998 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
13999 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
)
14002 /* It is best to perform DMA test with maximum write burst size
14003 * to expose the 5700/5701 write DMA bug.
14005 saved_dma_rwctrl
= tp
->dma_rwctrl
;
14006 tp
->dma_rwctrl
&= ~DMA_RWCTRL_WRITE_BNDRY_MASK
;
14007 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
14012 for (i
= 0; i
< TEST_BUFFER_SIZE
/ sizeof(u32
); i
++)
14015 /* Send the buffer to the chip. */
14016 ret
= tg3_do_test_dma(tp
, buf
, buf_dma
, TEST_BUFFER_SIZE
, 1);
14018 dev_err(&tp
->pdev
->dev
,
14019 "%s: Buffer write failed. err = %d\n",
14025 /* validate data reached card RAM correctly. */
14026 for (i
= 0; i
< TEST_BUFFER_SIZE
/ sizeof(u32
); i
++) {
14028 tg3_read_mem(tp
, 0x2100 + (i
*4), &val
);
14029 if (le32_to_cpu(val
) != p
[i
]) {
14030 dev_err(&tp
->pdev
->dev
,
14031 "%s: Buffer corrupted on device! "
14032 "(%d != %d)\n", __func__
, val
, i
);
14033 /* ret = -ENODEV here? */
14038 /* Now read it back. */
14039 ret
= tg3_do_test_dma(tp
, buf
, buf_dma
, TEST_BUFFER_SIZE
, 0);
14041 dev_err(&tp
->pdev
->dev
, "%s: Buffer read failed. "
14042 "err = %d\n", __func__
, ret
);
14047 for (i
= 0; i
< TEST_BUFFER_SIZE
/ sizeof(u32
); i
++) {
14051 if ((tp
->dma_rwctrl
& DMA_RWCTRL_WRITE_BNDRY_MASK
) !=
14052 DMA_RWCTRL_WRITE_BNDRY_16
) {
14053 tp
->dma_rwctrl
&= ~DMA_RWCTRL_WRITE_BNDRY_MASK
;
14054 tp
->dma_rwctrl
|= DMA_RWCTRL_WRITE_BNDRY_16
;
14055 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
14058 dev_err(&tp
->pdev
->dev
,
14059 "%s: Buffer corrupted on read back! "
14060 "(%d != %d)\n", __func__
, p
[i
], i
);
14066 if (i
== (TEST_BUFFER_SIZE
/ sizeof(u32
))) {
14072 if ((tp
->dma_rwctrl
& DMA_RWCTRL_WRITE_BNDRY_MASK
) !=
14073 DMA_RWCTRL_WRITE_BNDRY_16
) {
14074 static struct pci_device_id dma_wait_state_chipsets
[] = {
14075 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
,
14076 PCI_DEVICE_ID_APPLE_UNI_N_PCI15
) },
14080 /* DMA test passed without adjusting DMA boundary,
14081 * now look for chipsets that are known to expose the
14082 * DMA bug without failing the test.
14084 if (pci_dev_present(dma_wait_state_chipsets
)) {
14085 tp
->dma_rwctrl
&= ~DMA_RWCTRL_WRITE_BNDRY_MASK
;
14086 tp
->dma_rwctrl
|= DMA_RWCTRL_WRITE_BNDRY_16
;
14088 /* Safe to use the calculated DMA boundary. */
14089 tp
->dma_rwctrl
= saved_dma_rwctrl
;
14092 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
14096 pci_free_consistent(tp
->pdev
, TEST_BUFFER_SIZE
, buf
, buf_dma
);
14101 static void __devinit
tg3_init_link_config(struct tg3
*tp
)
14103 tp
->link_config
.advertising
=
14104 (ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
14105 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
|
14106 ADVERTISED_1000baseT_Half
| ADVERTISED_1000baseT_Full
|
14107 ADVERTISED_Autoneg
| ADVERTISED_MII
);
14108 tp
->link_config
.speed
= SPEED_INVALID
;
14109 tp
->link_config
.duplex
= DUPLEX_INVALID
;
14110 tp
->link_config
.autoneg
= AUTONEG_ENABLE
;
14111 tp
->link_config
.active_speed
= SPEED_INVALID
;
14112 tp
->link_config
.active_duplex
= DUPLEX_INVALID
;
14113 tp
->link_config
.phy_is_low_power
= 0;
14114 tp
->link_config
.orig_speed
= SPEED_INVALID
;
14115 tp
->link_config
.orig_duplex
= DUPLEX_INVALID
;
14116 tp
->link_config
.orig_autoneg
= AUTONEG_INVALID
;
14119 static void __devinit
tg3_init_bufmgr_config(struct tg3
*tp
)
14121 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
14122 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
||
14123 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
) {
14124 tp
->bufmgr_config
.mbuf_read_dma_low_water
=
14125 DEFAULT_MB_RDMA_LOW_WATER_5705
;
14126 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
14127 DEFAULT_MB_MACRX_LOW_WATER_57765
;
14128 tp
->bufmgr_config
.mbuf_high_water
=
14129 DEFAULT_MB_HIGH_WATER_57765
;
14131 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
=
14132 DEFAULT_MB_RDMA_LOW_WATER_5705
;
14133 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
=
14134 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765
;
14135 tp
->bufmgr_config
.mbuf_high_water_jumbo
=
14136 DEFAULT_MB_HIGH_WATER_JUMBO_57765
;
14137 } else if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
14138 tp
->bufmgr_config
.mbuf_read_dma_low_water
=
14139 DEFAULT_MB_RDMA_LOW_WATER_5705
;
14140 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
14141 DEFAULT_MB_MACRX_LOW_WATER_5705
;
14142 tp
->bufmgr_config
.mbuf_high_water
=
14143 DEFAULT_MB_HIGH_WATER_5705
;
14144 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
14145 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
14146 DEFAULT_MB_MACRX_LOW_WATER_5906
;
14147 tp
->bufmgr_config
.mbuf_high_water
=
14148 DEFAULT_MB_HIGH_WATER_5906
;
14151 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
=
14152 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780
;
14153 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
=
14154 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780
;
14155 tp
->bufmgr_config
.mbuf_high_water_jumbo
=
14156 DEFAULT_MB_HIGH_WATER_JUMBO_5780
;
14158 tp
->bufmgr_config
.mbuf_read_dma_low_water
=
14159 DEFAULT_MB_RDMA_LOW_WATER
;
14160 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
14161 DEFAULT_MB_MACRX_LOW_WATER
;
14162 tp
->bufmgr_config
.mbuf_high_water
=
14163 DEFAULT_MB_HIGH_WATER
;
14165 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
=
14166 DEFAULT_MB_RDMA_LOW_WATER_JUMBO
;
14167 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
=
14168 DEFAULT_MB_MACRX_LOW_WATER_JUMBO
;
14169 tp
->bufmgr_config
.mbuf_high_water_jumbo
=
14170 DEFAULT_MB_HIGH_WATER_JUMBO
;
14173 tp
->bufmgr_config
.dma_low_water
= DEFAULT_DMA_LOW_WATER
;
14174 tp
->bufmgr_config
.dma_high_water
= DEFAULT_DMA_HIGH_WATER
;
14177 static char * __devinit
tg3_phy_string(struct tg3
*tp
)
14179 switch (tp
->phy_id
& TG3_PHY_ID_MASK
) {
14180 case TG3_PHY_ID_BCM5400
: return "5400";
14181 case TG3_PHY_ID_BCM5401
: return "5401";
14182 case TG3_PHY_ID_BCM5411
: return "5411";
14183 case TG3_PHY_ID_BCM5701
: return "5701";
14184 case TG3_PHY_ID_BCM5703
: return "5703";
14185 case TG3_PHY_ID_BCM5704
: return "5704";
14186 case TG3_PHY_ID_BCM5705
: return "5705";
14187 case TG3_PHY_ID_BCM5750
: return "5750";
14188 case TG3_PHY_ID_BCM5752
: return "5752";
14189 case TG3_PHY_ID_BCM5714
: return "5714";
14190 case TG3_PHY_ID_BCM5780
: return "5780";
14191 case TG3_PHY_ID_BCM5755
: return "5755";
14192 case TG3_PHY_ID_BCM5787
: return "5787";
14193 case TG3_PHY_ID_BCM5784
: return "5784";
14194 case TG3_PHY_ID_BCM5756
: return "5722/5756";
14195 case TG3_PHY_ID_BCM5906
: return "5906";
14196 case TG3_PHY_ID_BCM5761
: return "5761";
14197 case TG3_PHY_ID_BCM5718C
: return "5718C";
14198 case TG3_PHY_ID_BCM5718S
: return "5718S";
14199 case TG3_PHY_ID_BCM57765
: return "57765";
14200 case TG3_PHY_ID_BCM5719C
: return "5719C";
14201 case TG3_PHY_ID_BCM8002
: return "8002/serdes";
14202 case 0: return "serdes";
14203 default: return "unknown";
14207 static char * __devinit
tg3_bus_string(struct tg3
*tp
, char *str
)
14209 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
14210 strcpy(str
, "PCI Express");
14212 } else if (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) {
14213 u32 clock_ctrl
= tr32(TG3PCI_CLOCK_CTRL
) & 0x1f;
14215 strcpy(str
, "PCIX:");
14217 if ((clock_ctrl
== 7) ||
14218 ((tr32(GRC_MISC_CFG
) & GRC_MISC_CFG_BOARD_ID_MASK
) ==
14219 GRC_MISC_CFG_BOARD_ID_5704CIOBE
))
14220 strcat(str
, "133MHz");
14221 else if (clock_ctrl
== 0)
14222 strcat(str
, "33MHz");
14223 else if (clock_ctrl
== 2)
14224 strcat(str
, "50MHz");
14225 else if (clock_ctrl
== 4)
14226 strcat(str
, "66MHz");
14227 else if (clock_ctrl
== 6)
14228 strcat(str
, "100MHz");
14230 strcpy(str
, "PCI:");
14231 if (tp
->tg3_flags
& TG3_FLAG_PCI_HIGH_SPEED
)
14232 strcat(str
, "66MHz");
14234 strcat(str
, "33MHz");
14236 if (tp
->tg3_flags
& TG3_FLAG_PCI_32BIT
)
14237 strcat(str
, ":32-bit");
14239 strcat(str
, ":64-bit");
14243 static struct pci_dev
* __devinit
tg3_find_peer(struct tg3
*tp
)
14245 struct pci_dev
*peer
;
14246 unsigned int func
, devnr
= tp
->pdev
->devfn
& ~7;
14248 for (func
= 0; func
< 8; func
++) {
14249 peer
= pci_get_slot(tp
->pdev
->bus
, devnr
| func
);
14250 if (peer
&& peer
!= tp
->pdev
)
14254 /* 5704 can be configured in single-port mode, set peer to
14255 * tp->pdev in that case.
14263 * We don't need to keep the refcount elevated; there's no way
14264 * to remove one half of this device without removing the other
14271 static void __devinit
tg3_init_coal(struct tg3
*tp
)
14273 struct ethtool_coalesce
*ec
= &tp
->coal
;
14275 memset(ec
, 0, sizeof(*ec
));
14276 ec
->cmd
= ETHTOOL_GCOALESCE
;
14277 ec
->rx_coalesce_usecs
= LOW_RXCOL_TICKS
;
14278 ec
->tx_coalesce_usecs
= LOW_TXCOL_TICKS
;
14279 ec
->rx_max_coalesced_frames
= LOW_RXMAX_FRAMES
;
14280 ec
->tx_max_coalesced_frames
= LOW_TXMAX_FRAMES
;
14281 ec
->rx_coalesce_usecs_irq
= DEFAULT_RXCOAL_TICK_INT
;
14282 ec
->tx_coalesce_usecs_irq
= DEFAULT_TXCOAL_TICK_INT
;
14283 ec
->rx_max_coalesced_frames_irq
= DEFAULT_RXCOAL_MAXF_INT
;
14284 ec
->tx_max_coalesced_frames_irq
= DEFAULT_TXCOAL_MAXF_INT
;
14285 ec
->stats_block_coalesce_usecs
= DEFAULT_STAT_COAL_TICKS
;
14287 if (tp
->coalesce_mode
& (HOSTCC_MODE_CLRTICK_RXBD
|
14288 HOSTCC_MODE_CLRTICK_TXBD
)) {
14289 ec
->rx_coalesce_usecs
= LOW_RXCOL_TICKS_CLRTCKS
;
14290 ec
->rx_coalesce_usecs_irq
= DEFAULT_RXCOAL_TICK_INT_CLRTCKS
;
14291 ec
->tx_coalesce_usecs
= LOW_TXCOL_TICKS_CLRTCKS
;
14292 ec
->tx_coalesce_usecs_irq
= DEFAULT_TXCOAL_TICK_INT_CLRTCKS
;
14295 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
14296 ec
->rx_coalesce_usecs_irq
= 0;
14297 ec
->tx_coalesce_usecs_irq
= 0;
14298 ec
->stats_block_coalesce_usecs
= 0;
14302 static const struct net_device_ops tg3_netdev_ops
= {
14303 .ndo_open
= tg3_open
,
14304 .ndo_stop
= tg3_close
,
14305 .ndo_start_xmit
= tg3_start_xmit
,
14306 .ndo_get_stats64
= tg3_get_stats64
,
14307 .ndo_validate_addr
= eth_validate_addr
,
14308 .ndo_set_multicast_list
= tg3_set_rx_mode
,
14309 .ndo_set_mac_address
= tg3_set_mac_addr
,
14310 .ndo_do_ioctl
= tg3_ioctl
,
14311 .ndo_tx_timeout
= tg3_tx_timeout
,
14312 .ndo_change_mtu
= tg3_change_mtu
,
14313 #if TG3_VLAN_TAG_USED
14314 .ndo_vlan_rx_register
= tg3_vlan_rx_register
,
14316 #ifdef CONFIG_NET_POLL_CONTROLLER
14317 .ndo_poll_controller
= tg3_poll_controller
,
14321 static const struct net_device_ops tg3_netdev_ops_dma_bug
= {
14322 .ndo_open
= tg3_open
,
14323 .ndo_stop
= tg3_close
,
14324 .ndo_start_xmit
= tg3_start_xmit_dma_bug
,
14325 .ndo_get_stats64
= tg3_get_stats64
,
14326 .ndo_validate_addr
= eth_validate_addr
,
14327 .ndo_set_multicast_list
= tg3_set_rx_mode
,
14328 .ndo_set_mac_address
= tg3_set_mac_addr
,
14329 .ndo_do_ioctl
= tg3_ioctl
,
14330 .ndo_tx_timeout
= tg3_tx_timeout
,
14331 .ndo_change_mtu
= tg3_change_mtu
,
14332 #if TG3_VLAN_TAG_USED
14333 .ndo_vlan_rx_register
= tg3_vlan_rx_register
,
14335 #ifdef CONFIG_NET_POLL_CONTROLLER
14336 .ndo_poll_controller
= tg3_poll_controller
,
14340 static int __devinit
tg3_init_one(struct pci_dev
*pdev
,
14341 const struct pci_device_id
*ent
)
14343 struct net_device
*dev
;
14345 int i
, err
, pm_cap
;
14346 u32 sndmbx
, rcvmbx
, intmbx
;
14348 u64 dma_mask
, persist_dma_mask
;
14350 printk_once(KERN_INFO
"%s\n", version
);
14352 err
= pci_enable_device(pdev
);
14354 dev_err(&pdev
->dev
, "Cannot enable PCI device, aborting\n");
14358 err
= pci_request_regions(pdev
, DRV_MODULE_NAME
);
14360 dev_err(&pdev
->dev
, "Cannot obtain PCI resources, aborting\n");
14361 goto err_out_disable_pdev
;
14364 pci_set_master(pdev
);
14366 /* Find power-management capability. */
14367 pm_cap
= pci_find_capability(pdev
, PCI_CAP_ID_PM
);
14369 dev_err(&pdev
->dev
,
14370 "Cannot find Power Management capability, aborting\n");
14372 goto err_out_free_res
;
14375 dev
= alloc_etherdev_mq(sizeof(*tp
), TG3_IRQ_MAX_VECS
);
14377 dev_err(&pdev
->dev
, "Etherdev alloc failed, aborting\n");
14379 goto err_out_free_res
;
14382 SET_NETDEV_DEV(dev
, &pdev
->dev
);
14384 #if TG3_VLAN_TAG_USED
14385 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
14388 tp
= netdev_priv(dev
);
14391 tp
->pm_cap
= pm_cap
;
14392 tp
->rx_mode
= TG3_DEF_RX_MODE
;
14393 tp
->tx_mode
= TG3_DEF_TX_MODE
;
14396 tp
->msg_enable
= tg3_debug
;
14398 tp
->msg_enable
= TG3_DEF_MSG_ENABLE
;
14400 /* The word/byte swap controls here control register access byte
14401 * swapping. DMA data byte swapping is controlled in the GRC_MODE
14404 tp
->misc_host_ctrl
=
14405 MISC_HOST_CTRL_MASK_PCI_INT
|
14406 MISC_HOST_CTRL_WORD_SWAP
|
14407 MISC_HOST_CTRL_INDIR_ACCESS
|
14408 MISC_HOST_CTRL_PCISTATE_RW
;
14410 /* The NONFRM (non-frame) byte/word swap controls take effect
14411 * on descriptor entries, anything which isn't packet data.
14413 * The StrongARM chips on the board (one for tx, one for rx)
14414 * are running in big-endian mode.
14416 tp
->grc_mode
= (GRC_MODE_WSWAP_DATA
| GRC_MODE_BSWAP_DATA
|
14417 GRC_MODE_WSWAP_NONFRM_DATA
);
14418 #ifdef __BIG_ENDIAN
14419 tp
->grc_mode
|= GRC_MODE_BSWAP_NONFRM_DATA
;
14421 spin_lock_init(&tp
->lock
);
14422 spin_lock_init(&tp
->indirect_lock
);
14423 INIT_WORK(&tp
->reset_task
, tg3_reset_task
);
14425 tp
->regs
= pci_ioremap_bar(pdev
, BAR_0
);
14427 dev_err(&pdev
->dev
, "Cannot map device registers, aborting\n");
14429 goto err_out_free_dev
;
14432 tg3_init_link_config(tp
);
14434 tp
->rx_pending
= TG3_DEF_RX_RING_PENDING
;
14435 tp
->rx_jumbo_pending
= TG3_DEF_RX_JUMBO_RING_PENDING
;
14437 dev
->ethtool_ops
= &tg3_ethtool_ops
;
14438 dev
->watchdog_timeo
= TG3_TX_TIMEOUT
;
14439 dev
->irq
= pdev
->irq
;
14441 err
= tg3_get_invariants(tp
);
14443 dev_err(&pdev
->dev
,
14444 "Problem fetching invariants of chip, aborting\n");
14445 goto err_out_iounmap
;
14448 if ((tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) &&
14449 tp
->pci_chip_rev_id
!= CHIPREV_ID_5717_A0
&&
14450 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5719
)
14451 dev
->netdev_ops
= &tg3_netdev_ops
;
14453 dev
->netdev_ops
= &tg3_netdev_ops_dma_bug
;
14456 /* The EPB bridge inside 5714, 5715, and 5780 and any
14457 * device behind the EPB cannot support DMA addresses > 40-bit.
14458 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14459 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14460 * do DMA address check in tg3_start_xmit().
14462 if (tp
->tg3_flags2
& TG3_FLG2_IS_5788
)
14463 persist_dma_mask
= dma_mask
= DMA_BIT_MASK(32);
14464 else if (tp
->tg3_flags
& TG3_FLAG_40BIT_DMA_BUG
) {
14465 persist_dma_mask
= dma_mask
= DMA_BIT_MASK(40);
14466 #ifdef CONFIG_HIGHMEM
14467 dma_mask
= DMA_BIT_MASK(64);
14470 persist_dma_mask
= dma_mask
= DMA_BIT_MASK(64);
14472 /* Configure DMA attributes. */
14473 if (dma_mask
> DMA_BIT_MASK(32)) {
14474 err
= pci_set_dma_mask(pdev
, dma_mask
);
14476 dev
->features
|= NETIF_F_HIGHDMA
;
14477 err
= pci_set_consistent_dma_mask(pdev
,
14480 dev_err(&pdev
->dev
, "Unable to obtain 64 bit "
14481 "DMA for consistent allocations\n");
14482 goto err_out_iounmap
;
14486 if (err
|| dma_mask
== DMA_BIT_MASK(32)) {
14487 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
14489 dev_err(&pdev
->dev
,
14490 "No usable DMA configuration, aborting\n");
14491 goto err_out_iounmap
;
14495 tg3_init_bufmgr_config(tp
);
14497 /* Selectively allow TSO based on operating conditions */
14498 if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO
) ||
14499 (tp
->fw_needed
&& !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)))
14500 tp
->tg3_flags2
|= TG3_FLG2_TSO_CAPABLE
;
14502 tp
->tg3_flags2
&= ~(TG3_FLG2_TSO_CAPABLE
| TG3_FLG2_TSO_BUG
);
14503 tp
->fw_needed
= NULL
;
14506 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
)
14507 tp
->fw_needed
= FIRMWARE_TG3
;
14509 /* TSO is on by default on chips that support hardware TSO.
14510 * Firmware TSO on older chips gives lower performance, so it
14511 * is off by default, but can be enabled using ethtool.
14513 if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO
) &&
14514 (dev
->features
& NETIF_F_IP_CSUM
)) {
14515 dev
->features
|= NETIF_F_TSO
;
14516 vlan_features_add(dev
, NETIF_F_TSO
);
14518 if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO_2
) ||
14519 (tp
->tg3_flags2
& TG3_FLG2_HW_TSO_3
)) {
14520 if (dev
->features
& NETIF_F_IPV6_CSUM
) {
14521 dev
->features
|= NETIF_F_TSO6
;
14522 vlan_features_add(dev
, NETIF_F_TSO6
);
14524 if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO_3
) ||
14525 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
14526 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
14527 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
) ||
14528 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
14529 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
) {
14530 dev
->features
|= NETIF_F_TSO_ECN
;
14531 vlan_features_add(dev
, NETIF_F_TSO_ECN
);
14535 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A1
&&
14536 !(tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) &&
14537 !(tr32(TG3PCI_PCISTATE
) & PCISTATE_BUS_SPEED_HIGH
)) {
14538 tp
->tg3_flags2
|= TG3_FLG2_MAX_RXPEND_64
;
14539 tp
->rx_pending
= 63;
14542 err
= tg3_get_device_address(tp
);
14544 dev_err(&pdev
->dev
,
14545 "Could not obtain valid ethernet address, aborting\n");
14546 goto err_out_iounmap
;
14549 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
14550 tp
->aperegs
= pci_ioremap_bar(pdev
, BAR_2
);
14551 if (!tp
->aperegs
) {
14552 dev_err(&pdev
->dev
,
14553 "Cannot map APE registers, aborting\n");
14555 goto err_out_iounmap
;
14558 tg3_ape_lock_init(tp
);
14560 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)
14561 tg3_read_dash_ver(tp
);
14565 * Reset chip in case UNDI or EFI driver did not shutdown
14566 * DMA self test will enable WDMAC and we'll see (spurious)
14567 * pending DMA on the PCI bus at that point.
14569 if ((tr32(HOSTCC_MODE
) & HOSTCC_MODE_ENABLE
) ||
14570 (tr32(WDMAC_MODE
) & WDMAC_MODE_ENABLE
)) {
14571 tw32(MEMARB_MODE
, MEMARB_MODE_ENABLE
);
14572 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
14575 err
= tg3_test_dma(tp
);
14577 dev_err(&pdev
->dev
, "DMA engine test failed, aborting\n");
14578 goto err_out_apeunmap
;
14581 /* flow control autonegotiation is default behavior */
14582 tp
->tg3_flags
|= TG3_FLAG_PAUSE_AUTONEG
;
14583 tp
->link_config
.flowctrl
= FLOW_CTRL_TX
| FLOW_CTRL_RX
;
14585 intmbx
= MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
;
14586 rcvmbx
= MAILBOX_RCVRET_CON_IDX_0
+ TG3_64BIT_REG_LOW
;
14587 sndmbx
= MAILBOX_SNDHOST_PROD_IDX_0
+ TG3_64BIT_REG_LOW
;
14588 for (i
= 0; i
< TG3_IRQ_MAX_VECS
; i
++) {
14589 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
14592 tnapi
->tx_pending
= TG3_DEF_TX_RING_PENDING
;
14594 tnapi
->int_mbox
= intmbx
;
14600 tnapi
->consmbox
= rcvmbx
;
14601 tnapi
->prodmbox
= sndmbx
;
14604 tnapi
->coal_now
= HOSTCC_MODE_COAL_VEC1_NOW
<< (i
- 1);
14605 netif_napi_add(dev
, &tnapi
->napi
, tg3_poll_msix
, 64);
14607 tnapi
->coal_now
= HOSTCC_MODE_NOW
;
14608 netif_napi_add(dev
, &tnapi
->napi
, tg3_poll
, 64);
14611 if (!(tp
->tg3_flags
& TG3_FLAG_SUPPORT_MSIX
))
14615 * If we support MSIX, we'll be using RSS. If we're using
14616 * RSS, the first vector only handles link interrupts and the
14617 * remaining vectors handle rx and tx interrupts. Reuse the
14618 * mailbox values for the next iteration. The values we setup
14619 * above are still useful for the single vectored mode.
14634 pci_set_drvdata(pdev
, dev
);
14636 err
= register_netdev(dev
);
14638 dev_err(&pdev
->dev
, "Cannot register net device, aborting\n");
14639 goto err_out_apeunmap
;
14642 netdev_info(dev
, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14643 tp
->board_part_number
,
14644 tp
->pci_chip_rev_id
,
14645 tg3_bus_string(tp
, str
),
14648 if (tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
) {
14649 struct phy_device
*phydev
;
14650 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
14652 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14653 phydev
->drv
->name
, dev_name(&phydev
->dev
));
14655 netdev_info(dev
, "attached PHY is %s (%s Ethernet) "
14656 "(WireSpeed[%d])\n", tg3_phy_string(tp
),
14657 ((tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
) ? "10/100Base-TX" :
14658 ((tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
) ? "1000Base-SX" :
14659 "10/100/1000Base-T")),
14660 (tp
->tg3_flags2
& TG3_FLG2_NO_ETH_WIRE_SPEED
) == 0);
14662 netdev_info(dev
, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14663 (tp
->tg3_flags
& TG3_FLAG_RX_CHECKSUMS
) != 0,
14664 (tp
->tg3_flags
& TG3_FLAG_USE_LINKCHG_REG
) != 0,
14665 (tp
->tg3_flags
& TG3_FLAG_USE_MI_INTERRUPT
) != 0,
14666 (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) != 0,
14667 (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) != 0);
14668 netdev_info(dev
, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14670 pdev
->dma_mask
== DMA_BIT_MASK(32) ? 32 :
14671 ((u64
)pdev
->dma_mask
) == DMA_BIT_MASK(40) ? 40 : 64);
14677 iounmap(tp
->aperegs
);
14678 tp
->aperegs
= NULL
;
14691 pci_release_regions(pdev
);
14693 err_out_disable_pdev
:
14694 pci_disable_device(pdev
);
14695 pci_set_drvdata(pdev
, NULL
);
14699 static void __devexit
tg3_remove_one(struct pci_dev
*pdev
)
14701 struct net_device
*dev
= pci_get_drvdata(pdev
);
14704 struct tg3
*tp
= netdev_priv(dev
);
14707 release_firmware(tp
->fw
);
14709 flush_scheduled_work();
14711 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
14716 unregister_netdev(dev
);
14718 iounmap(tp
->aperegs
);
14719 tp
->aperegs
= NULL
;
14726 pci_release_regions(pdev
);
14727 pci_disable_device(pdev
);
14728 pci_set_drvdata(pdev
, NULL
);
14732 static int tg3_suspend(struct pci_dev
*pdev
, pm_message_t state
)
14734 struct net_device
*dev
= pci_get_drvdata(pdev
);
14735 struct tg3
*tp
= netdev_priv(dev
);
14736 pci_power_t target_state
;
14739 /* PCI register 4 needs to be saved whether netif_running() or not.
14740 * MSI address and data need to be saved if using MSI and
14743 pci_save_state(pdev
);
14745 if (!netif_running(dev
))
14748 flush_scheduled_work();
14750 tg3_netif_stop(tp
);
14752 del_timer_sync(&tp
->timer
);
14754 tg3_full_lock(tp
, 1);
14755 tg3_disable_ints(tp
);
14756 tg3_full_unlock(tp
);
14758 netif_device_detach(dev
);
14760 tg3_full_lock(tp
, 0);
14761 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
14762 tp
->tg3_flags
&= ~TG3_FLAG_INIT_COMPLETE
;
14763 tg3_full_unlock(tp
);
14765 target_state
= pdev
->pm_cap
? pci_target_state(pdev
) : PCI_D3hot
;
14767 err
= tg3_set_power_state(tp
, target_state
);
14771 tg3_full_lock(tp
, 0);
14773 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
14774 err2
= tg3_restart_hw(tp
, 1);
14778 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
14779 add_timer(&tp
->timer
);
14781 netif_device_attach(dev
);
14782 tg3_netif_start(tp
);
14785 tg3_full_unlock(tp
);
14794 static int tg3_resume(struct pci_dev
*pdev
)
14796 struct net_device
*dev
= pci_get_drvdata(pdev
);
14797 struct tg3
*tp
= netdev_priv(dev
);
14800 pci_restore_state(tp
->pdev
);
14802 if (!netif_running(dev
))
14805 err
= tg3_set_power_state(tp
, PCI_D0
);
14809 netif_device_attach(dev
);
14811 tg3_full_lock(tp
, 0);
14813 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
14814 err
= tg3_restart_hw(tp
, 1);
14818 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
14819 add_timer(&tp
->timer
);
14821 tg3_netif_start(tp
);
14824 tg3_full_unlock(tp
);
14832 static struct pci_driver tg3_driver
= {
14833 .name
= DRV_MODULE_NAME
,
14834 .id_table
= tg3_pci_tbl
,
14835 .probe
= tg3_init_one
,
14836 .remove
= __devexit_p(tg3_remove_one
),
14837 .suspend
= tg3_suspend
,
14838 .resume
= tg3_resume
14841 static int __init
tg3_init(void)
14843 return pci_register_driver(&tg3_driver
);
14846 static void __exit
tg3_cleanup(void)
14848 pci_unregister_driver(&tg3_driver
);
14851 module_init(tg3_init
);
14852 module_exit(tg3_cleanup
);