2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2010 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
28 #include <linux/init.h>
29 #include <linux/ioport.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/ethtool.h>
35 #include <linux/mii.h>
36 #include <linux/phy.h>
37 #include <linux/brcmphy.h>
38 #include <linux/if_vlan.h>
40 #include <linux/tcp.h>
41 #include <linux/workqueue.h>
42 #include <linux/prefetch.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/firmware.h>
46 #include <net/checksum.h>
49 #include <asm/system.h>
51 #include <asm/byteorder.h>
52 #include <asm/uaccess.h>
55 #include <asm/idprom.h>
62 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
63 #define TG3_VLAN_TAG_USED 1
65 #define TG3_VLAN_TAG_USED 0
70 #define DRV_MODULE_NAME "tg3"
72 #define TG3_MIN_NUM 114
73 #define DRV_MODULE_VERSION \
74 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
75 #define DRV_MODULE_RELDATE "September 30, 2010"
77 #define TG3_DEF_MAC_MODE 0
78 #define TG3_DEF_RX_MODE 0
79 #define TG3_DEF_TX_MODE 0
80 #define TG3_DEF_MSG_ENABLE \
90 /* length of time before we decide the hardware is borked,
91 * and dev->tx_timeout() should be called to fix the problem
93 #define TG3_TX_TIMEOUT (5 * HZ)
95 /* hardware minimum and maximum for a single frame's data payload */
96 #define TG3_MIN_MTU 60
97 #define TG3_MAX_MTU(tp) \
98 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
100 /* These numbers seem to be hard coded in the NIC firmware somehow.
101 * You can't change the ring sizes, but you can change where you place
102 * them in the NIC onboard memory.
104 #define TG3_RX_STD_RING_SIZE(tp) \
105 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || \
106 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) ? \
107 RX_STD_MAX_SIZE_5717 : 512)
108 #define TG3_DEF_RX_RING_PENDING 200
109 #define TG3_RX_JMB_RING_SIZE(tp) \
110 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || \
111 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) ? \
113 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
114 #define TG3_RSS_INDIR_TBL_SIZE 128
116 /* Do not place this n-ring entries value into the tp struct itself,
117 * we really want to expose these constants to GCC so that modulo et
118 * al. operations are done with shifts and masks instead of with
119 * hw multiply/modulo instructions. Another solution would be to
120 * replace things like '% foo' with '& (foo - 1)'.
123 #define TG3_TX_RING_SIZE 512
124 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
126 #define TG3_RX_STD_RING_BYTES(tp) \
127 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
128 #define TG3_RX_JMB_RING_BYTES(tp) \
129 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
130 #define TG3_RX_RCB_RING_BYTES(tp) \
131 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
132 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
134 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
136 #define TG3_RX_DMA_ALIGN 16
137 #define TG3_RX_HEADROOM ALIGN(VLAN_HLEN, TG3_RX_DMA_ALIGN)
139 #define TG3_DMA_BYTE_ENAB 64
141 #define TG3_RX_STD_DMA_SZ 1536
142 #define TG3_RX_JMB_DMA_SZ 9046
144 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
146 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
147 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
149 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
150 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
152 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
153 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
155 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
156 * that are at least dword aligned when used in PCIX mode. The driver
157 * works around this bug by double copying the packet. This workaround
158 * is built into the normal double copy length check for efficiency.
160 * However, the double copy is only necessary on those architectures
161 * where unaligned memory accesses are inefficient. For those architectures
162 * where unaligned memory accesses incur little penalty, we can reintegrate
163 * the 5701 in the normal rx path. Doing so saves a device structure
164 * dereference by hardcoding the double copy threshold in place.
166 #define TG3_RX_COPY_THRESHOLD 256
167 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
168 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
170 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
173 /* minimum number of free TX descriptors required to wake up TX process */
174 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
176 #define TG3_RAW_IP_ALIGN 2
178 /* number of ETHTOOL_GSTATS u64's */
179 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
181 #define TG3_NUM_TEST 6
183 #define TG3_FW_UPDATE_TIMEOUT_SEC 5
185 #define FIRMWARE_TG3 "tigon/tg3.bin"
186 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
187 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
189 static char version
[] __devinitdata
=
190 DRV_MODULE_NAME
".c:v" DRV_MODULE_VERSION
" (" DRV_MODULE_RELDATE
")";
192 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
193 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
194 MODULE_LICENSE("GPL");
195 MODULE_VERSION(DRV_MODULE_VERSION
);
196 MODULE_FIRMWARE(FIRMWARE_TG3
);
197 MODULE_FIRMWARE(FIRMWARE_TG3TSO
);
198 MODULE_FIRMWARE(FIRMWARE_TG3TSO5
);
200 static int tg3_debug
= -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
201 module_param(tg3_debug
, int, 0);
202 MODULE_PARM_DESC(tg3_debug
, "Tigon3 bitmapped debugging message enable value");
204 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl
) = {
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5700
)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5701
)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702
)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5703
)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5704
)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702FE
)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705
)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705_2
)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705M
)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705M_2
)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702X
)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5703X
)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5704S
)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702A3
)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5703A3
)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5782
)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5788
)},
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5789
)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5901
)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5901_2
)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5704S_2
)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705F
)},
227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5721
)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5722
)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5751
)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5751M
)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5751F
)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5752
)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5752M
)},
234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5753
)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5753M
)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5753F
)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5754
)},
238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5754M
)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5755
)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5755M
)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5756
)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5786
)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5787
)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5787M
)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5787F
)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5714
)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5714S
)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5715
)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5715S
)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5780
)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5780S
)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5781
)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5906
)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5906M
)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5784
)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5764
)},
257 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5723
)},
258 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5761
)},
259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5761E
)},
260 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5761S
)},
261 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5761SE
)},
262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5785_G
)},
263 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5785_F
)},
264 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57780
)},
265 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57760
)},
266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57790
)},
267 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57788
)},
268 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5717
)},
269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5718
)},
270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57781
)},
271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57785
)},
272 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57761
)},
273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57765
)},
274 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57791
)},
275 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57795
)},
276 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5719
)},
277 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, PCI_DEVICE_ID_SYSKONNECT_9DXX
)},
278 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, PCI_DEVICE_ID_SYSKONNECT_9MXX
)},
279 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC1000
)},
280 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC1001
)},
281 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC1003
)},
282 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC9100
)},
283 {PCI_DEVICE(PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_TIGON3
)},
287 MODULE_DEVICE_TABLE(pci
, tg3_pci_tbl
);
289 static const struct {
290 const char string
[ETH_GSTRING_LEN
];
291 } ethtool_stats_keys
[TG3_NUM_STATS
] = {
294 { "rx_ucast_packets" },
295 { "rx_mcast_packets" },
296 { "rx_bcast_packets" },
298 { "rx_align_errors" },
299 { "rx_xon_pause_rcvd" },
300 { "rx_xoff_pause_rcvd" },
301 { "rx_mac_ctrl_rcvd" },
302 { "rx_xoff_entered" },
303 { "rx_frame_too_long_errors" },
305 { "rx_undersize_packets" },
306 { "rx_in_length_errors" },
307 { "rx_out_length_errors" },
308 { "rx_64_or_less_octet_packets" },
309 { "rx_65_to_127_octet_packets" },
310 { "rx_128_to_255_octet_packets" },
311 { "rx_256_to_511_octet_packets" },
312 { "rx_512_to_1023_octet_packets" },
313 { "rx_1024_to_1522_octet_packets" },
314 { "rx_1523_to_2047_octet_packets" },
315 { "rx_2048_to_4095_octet_packets" },
316 { "rx_4096_to_8191_octet_packets" },
317 { "rx_8192_to_9022_octet_packets" },
324 { "tx_flow_control" },
326 { "tx_single_collisions" },
327 { "tx_mult_collisions" },
329 { "tx_excessive_collisions" },
330 { "tx_late_collisions" },
331 { "tx_collide_2times" },
332 { "tx_collide_3times" },
333 { "tx_collide_4times" },
334 { "tx_collide_5times" },
335 { "tx_collide_6times" },
336 { "tx_collide_7times" },
337 { "tx_collide_8times" },
338 { "tx_collide_9times" },
339 { "tx_collide_10times" },
340 { "tx_collide_11times" },
341 { "tx_collide_12times" },
342 { "tx_collide_13times" },
343 { "tx_collide_14times" },
344 { "tx_collide_15times" },
345 { "tx_ucast_packets" },
346 { "tx_mcast_packets" },
347 { "tx_bcast_packets" },
348 { "tx_carrier_sense_errors" },
352 { "dma_writeq_full" },
353 { "dma_write_prioq_full" },
357 { "rx_threshold_hit" },
359 { "dma_readq_full" },
360 { "dma_read_prioq_full" },
361 { "tx_comp_queue_full" },
363 { "ring_set_send_prod_index" },
364 { "ring_status_update" },
366 { "nic_avoided_irqs" },
367 { "nic_tx_threshold_hit" }
370 static const struct {
371 const char string
[ETH_GSTRING_LEN
];
372 } ethtool_test_keys
[TG3_NUM_TEST
] = {
373 { "nvram test (online) " },
374 { "link test (online) " },
375 { "register test (offline)" },
376 { "memory test (offline)" },
377 { "loopback test (offline)" },
378 { "interrupt test (offline)" },
381 static void tg3_write32(struct tg3
*tp
, u32 off
, u32 val
)
383 writel(val
, tp
->regs
+ off
);
386 static u32
tg3_read32(struct tg3
*tp
, u32 off
)
388 return readl(tp
->regs
+ off
);
391 static void tg3_ape_write32(struct tg3
*tp
, u32 off
, u32 val
)
393 writel(val
, tp
->aperegs
+ off
);
396 static u32
tg3_ape_read32(struct tg3
*tp
, u32 off
)
398 return readl(tp
->aperegs
+ off
);
401 static void tg3_write_indirect_reg32(struct tg3
*tp
, u32 off
, u32 val
)
405 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
406 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
);
407 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, val
);
408 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
411 static void tg3_write_flush_reg32(struct tg3
*tp
, u32 off
, u32 val
)
413 writel(val
, tp
->regs
+ off
);
414 readl(tp
->regs
+ off
);
417 static u32
tg3_read_indirect_reg32(struct tg3
*tp
, u32 off
)
422 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
423 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
);
424 pci_read_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, &val
);
425 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
429 static void tg3_write_indirect_mbox(struct tg3
*tp
, u32 off
, u32 val
)
433 if (off
== (MAILBOX_RCVRET_CON_IDX_0
+ TG3_64BIT_REG_LOW
)) {
434 pci_write_config_dword(tp
->pdev
, TG3PCI_RCV_RET_RING_CON_IDX
+
435 TG3_64BIT_REG_LOW
, val
);
438 if (off
== TG3_RX_STD_PROD_IDX_REG
) {
439 pci_write_config_dword(tp
->pdev
, TG3PCI_STD_RING_PROD_IDX
+
440 TG3_64BIT_REG_LOW
, val
);
444 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
445 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
+ 0x5600);
446 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, val
);
447 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
449 /* In indirect mode when disabling interrupts, we also need
450 * to clear the interrupt bit in the GRC local ctrl register.
452 if ((off
== (MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
)) &&
454 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_LOCAL_CTRL
,
455 tp
->grc_local_ctrl
|GRC_LCLCTRL_CLEARINT
);
459 static u32
tg3_read_indirect_mbox(struct tg3
*tp
, u32 off
)
464 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
465 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
+ 0x5600);
466 pci_read_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, &val
);
467 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
471 /* usec_wait specifies the wait time in usec when writing to certain registers
472 * where it is unsafe to read back the register without some delay.
473 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
474 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
476 static void _tw32_flush(struct tg3
*tp
, u32 off
, u32 val
, u32 usec_wait
)
478 if ((tp
->tg3_flags
& TG3_FLAG_PCIX_TARGET_HWBUG
) ||
479 (tp
->tg3_flags2
& TG3_FLG2_ICH_WORKAROUND
))
480 /* Non-posted methods */
481 tp
->write32(tp
, off
, val
);
484 tg3_write32(tp
, off
, val
);
489 /* Wait again after the read for the posted method to guarantee that
490 * the wait time is met.
496 static inline void tw32_mailbox_flush(struct tg3
*tp
, u32 off
, u32 val
)
498 tp
->write32_mbox(tp
, off
, val
);
499 if (!(tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
) &&
500 !(tp
->tg3_flags2
& TG3_FLG2_ICH_WORKAROUND
))
501 tp
->read32_mbox(tp
, off
);
504 static void tg3_write32_tx_mbox(struct tg3
*tp
, u32 off
, u32 val
)
506 void __iomem
*mbox
= tp
->regs
+ off
;
508 if (tp
->tg3_flags
& TG3_FLAG_TXD_MBOX_HWBUG
)
510 if (tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
)
514 static u32
tg3_read32_mbox_5906(struct tg3
*tp
, u32 off
)
516 return readl(tp
->regs
+ off
+ GRCMBOX_BASE
);
519 static void tg3_write32_mbox_5906(struct tg3
*tp
, u32 off
, u32 val
)
521 writel(val
, tp
->regs
+ off
+ GRCMBOX_BASE
);
524 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
525 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
526 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
527 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
528 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
530 #define tw32(reg, val) tp->write32(tp, reg, val)
531 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
532 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
533 #define tr32(reg) tp->read32(tp, reg)
535 static void tg3_write_mem(struct tg3
*tp
, u32 off
, u32 val
)
539 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) &&
540 (off
>= NIC_SRAM_STATS_BLK
) && (off
< NIC_SRAM_TX_BUFFER_DESC
))
543 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
544 if (tp
->tg3_flags
& TG3_FLAG_SRAM_USE_CONFIG
) {
545 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, off
);
546 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_DATA
, val
);
548 /* Always leave this as zero. */
549 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, 0);
551 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, off
);
552 tw32_f(TG3PCI_MEM_WIN_DATA
, val
);
554 /* Always leave this as zero. */
555 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
557 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
560 static void tg3_read_mem(struct tg3
*tp
, u32 off
, u32
*val
)
564 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) &&
565 (off
>= NIC_SRAM_STATS_BLK
) && (off
< NIC_SRAM_TX_BUFFER_DESC
)) {
570 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
571 if (tp
->tg3_flags
& TG3_FLAG_SRAM_USE_CONFIG
) {
572 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, off
);
573 pci_read_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_DATA
, val
);
575 /* Always leave this as zero. */
576 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, 0);
578 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, off
);
579 *val
= tr32(TG3PCI_MEM_WIN_DATA
);
581 /* Always leave this as zero. */
582 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
584 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
587 static void tg3_ape_lock_init(struct tg3
*tp
)
592 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
)
593 regbase
= TG3_APE_LOCK_GRANT
;
595 regbase
= TG3_APE_PER_LOCK_GRANT
;
597 /* Make sure the driver hasn't any stale locks. */
598 for (i
= 0; i
< 8; i
++)
599 tg3_ape_write32(tp
, regbase
+ 4 * i
, APE_LOCK_GRANT_DRIVER
);
602 static int tg3_ape_lock(struct tg3
*tp
, int locknum
)
606 u32 status
, req
, gnt
;
608 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
))
612 case TG3_APE_LOCK_GRC
:
613 case TG3_APE_LOCK_MEM
:
619 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
) {
620 req
= TG3_APE_LOCK_REQ
;
621 gnt
= TG3_APE_LOCK_GRANT
;
623 req
= TG3_APE_PER_LOCK_REQ
;
624 gnt
= TG3_APE_PER_LOCK_GRANT
;
629 tg3_ape_write32(tp
, req
+ off
, APE_LOCK_REQ_DRIVER
);
631 /* Wait for up to 1 millisecond to acquire lock. */
632 for (i
= 0; i
< 100; i
++) {
633 status
= tg3_ape_read32(tp
, gnt
+ off
);
634 if (status
== APE_LOCK_GRANT_DRIVER
)
639 if (status
!= APE_LOCK_GRANT_DRIVER
) {
640 /* Revoke the lock request. */
641 tg3_ape_write32(tp
, gnt
+ off
,
642 APE_LOCK_GRANT_DRIVER
);
650 static void tg3_ape_unlock(struct tg3
*tp
, int locknum
)
654 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
))
658 case TG3_APE_LOCK_GRC
:
659 case TG3_APE_LOCK_MEM
:
665 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
)
666 gnt
= TG3_APE_LOCK_GRANT
;
668 gnt
= TG3_APE_PER_LOCK_GRANT
;
670 tg3_ape_write32(tp
, gnt
+ 4 * locknum
, APE_LOCK_GRANT_DRIVER
);
673 static void tg3_disable_ints(struct tg3
*tp
)
677 tw32(TG3PCI_MISC_HOST_CTRL
,
678 (tp
->misc_host_ctrl
| MISC_HOST_CTRL_MASK_PCI_INT
));
679 for (i
= 0; i
< tp
->irq_max
; i
++)
680 tw32_mailbox_f(tp
->napi
[i
].int_mbox
, 0x00000001);
683 static void tg3_enable_ints(struct tg3
*tp
)
690 tw32(TG3PCI_MISC_HOST_CTRL
,
691 (tp
->misc_host_ctrl
& ~MISC_HOST_CTRL_MASK_PCI_INT
));
693 tp
->coal_now
= tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
;
694 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
695 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
697 tw32_mailbox_f(tnapi
->int_mbox
, tnapi
->last_tag
<< 24);
698 if (tp
->tg3_flags2
& TG3_FLG2_1SHOT_MSI
)
699 tw32_mailbox_f(tnapi
->int_mbox
, tnapi
->last_tag
<< 24);
701 tp
->coal_now
|= tnapi
->coal_now
;
704 /* Force an initial interrupt */
705 if (!(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) &&
706 (tp
->napi
[0].hw_status
->status
& SD_STATUS_UPDATED
))
707 tw32(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
| GRC_LCLCTRL_SETINT
);
709 tw32(HOSTCC_MODE
, tp
->coal_now
);
711 tp
->coal_now
&= ~(tp
->napi
[0].coal_now
| tp
->napi
[1].coal_now
);
714 static inline unsigned int tg3_has_work(struct tg3_napi
*tnapi
)
716 struct tg3
*tp
= tnapi
->tp
;
717 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
718 unsigned int work_exists
= 0;
720 /* check for phy events */
721 if (!(tp
->tg3_flags
&
722 (TG3_FLAG_USE_LINKCHG_REG
|
723 TG3_FLAG_POLL_SERDES
))) {
724 if (sblk
->status
& SD_STATUS_LINK_CHG
)
727 /* check for RX/TX work to do */
728 if (sblk
->idx
[0].tx_consumer
!= tnapi
->tx_cons
||
729 *(tnapi
->rx_rcb_prod_idx
) != tnapi
->rx_rcb_ptr
)
736 * similar to tg3_enable_ints, but it accurately determines whether there
737 * is new work pending and can return without flushing the PIO write
738 * which reenables interrupts
740 static void tg3_int_reenable(struct tg3_napi
*tnapi
)
742 struct tg3
*tp
= tnapi
->tp
;
744 tw32_mailbox(tnapi
->int_mbox
, tnapi
->last_tag
<< 24);
747 /* When doing tagged status, this work check is unnecessary.
748 * The last_tag we write above tells the chip which piece of
749 * work we've completed.
751 if (!(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) &&
753 tw32(HOSTCC_MODE
, tp
->coalesce_mode
|
754 HOSTCC_MODE_ENABLE
| tnapi
->coal_now
);
757 static void tg3_switch_clocks(struct tg3
*tp
)
762 if ((tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) ||
763 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
766 clock_ctrl
= tr32(TG3PCI_CLOCK_CTRL
);
768 orig_clock_ctrl
= clock_ctrl
;
769 clock_ctrl
&= (CLOCK_CTRL_FORCE_CLKRUN
|
770 CLOCK_CTRL_CLKRUN_OENABLE
|
772 tp
->pci_clock_ctrl
= clock_ctrl
;
774 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
775 if (orig_clock_ctrl
& CLOCK_CTRL_625_CORE
) {
776 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
777 clock_ctrl
| CLOCK_CTRL_625_CORE
, 40);
779 } else if ((orig_clock_ctrl
& CLOCK_CTRL_44MHZ_CORE
) != 0) {
780 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
782 (CLOCK_CTRL_44MHZ_CORE
| CLOCK_CTRL_ALTCLK
),
784 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
785 clock_ctrl
| (CLOCK_CTRL_ALTCLK
),
788 tw32_wait_f(TG3PCI_CLOCK_CTRL
, clock_ctrl
, 40);
791 #define PHY_BUSY_LOOPS 5000
793 static int tg3_readphy(struct tg3
*tp
, int reg
, u32
*val
)
799 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
801 (tp
->mi_mode
& ~MAC_MI_MODE_AUTO_POLL
));
807 frame_val
= ((tp
->phy_addr
<< MI_COM_PHY_ADDR_SHIFT
) &
808 MI_COM_PHY_ADDR_MASK
);
809 frame_val
|= ((reg
<< MI_COM_REG_ADDR_SHIFT
) &
810 MI_COM_REG_ADDR_MASK
);
811 frame_val
|= (MI_COM_CMD_READ
| MI_COM_START
);
813 tw32_f(MAC_MI_COM
, frame_val
);
815 loops
= PHY_BUSY_LOOPS
;
818 frame_val
= tr32(MAC_MI_COM
);
820 if ((frame_val
& MI_COM_BUSY
) == 0) {
822 frame_val
= tr32(MAC_MI_COM
);
830 *val
= frame_val
& MI_COM_DATA_MASK
;
834 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
835 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
842 static int tg3_writephy(struct tg3
*tp
, int reg
, u32 val
)
848 if ((tp
->phy_flags
& TG3_PHYFLG_IS_FET
) &&
849 (reg
== MII_TG3_CTRL
|| reg
== MII_TG3_AUX_CTRL
))
852 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
854 (tp
->mi_mode
& ~MAC_MI_MODE_AUTO_POLL
));
858 frame_val
= ((tp
->phy_addr
<< MI_COM_PHY_ADDR_SHIFT
) &
859 MI_COM_PHY_ADDR_MASK
);
860 frame_val
|= ((reg
<< MI_COM_REG_ADDR_SHIFT
) &
861 MI_COM_REG_ADDR_MASK
);
862 frame_val
|= (val
& MI_COM_DATA_MASK
);
863 frame_val
|= (MI_COM_CMD_WRITE
| MI_COM_START
);
865 tw32_f(MAC_MI_COM
, frame_val
);
867 loops
= PHY_BUSY_LOOPS
;
870 frame_val
= tr32(MAC_MI_COM
);
871 if ((frame_val
& MI_COM_BUSY
) == 0) {
873 frame_val
= tr32(MAC_MI_COM
);
883 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
884 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
891 static int tg3_bmcr_reset(struct tg3
*tp
)
896 /* OK, reset it, and poll the BMCR_RESET bit until it
897 * clears or we time out.
899 phy_control
= BMCR_RESET
;
900 err
= tg3_writephy(tp
, MII_BMCR
, phy_control
);
906 err
= tg3_readphy(tp
, MII_BMCR
, &phy_control
);
910 if ((phy_control
& BMCR_RESET
) == 0) {
922 static int tg3_mdio_read(struct mii_bus
*bp
, int mii_id
, int reg
)
924 struct tg3
*tp
= bp
->priv
;
927 spin_lock_bh(&tp
->lock
);
929 if (tg3_readphy(tp
, reg
, &val
))
932 spin_unlock_bh(&tp
->lock
);
937 static int tg3_mdio_write(struct mii_bus
*bp
, int mii_id
, int reg
, u16 val
)
939 struct tg3
*tp
= bp
->priv
;
942 spin_lock_bh(&tp
->lock
);
944 if (tg3_writephy(tp
, reg
, val
))
947 spin_unlock_bh(&tp
->lock
);
952 static int tg3_mdio_reset(struct mii_bus
*bp
)
957 static void tg3_mdio_config_5785(struct tg3
*tp
)
960 struct phy_device
*phydev
;
962 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
963 switch (phydev
->drv
->phy_id
& phydev
->drv
->phy_id_mask
) {
964 case PHY_ID_BCM50610
:
965 case PHY_ID_BCM50610M
:
966 val
= MAC_PHYCFG2_50610_LED_MODES
;
968 case PHY_ID_BCMAC131
:
969 val
= MAC_PHYCFG2_AC131_LED_MODES
;
971 case PHY_ID_RTL8211C
:
972 val
= MAC_PHYCFG2_RTL8211C_LED_MODES
;
974 case PHY_ID_RTL8201E
:
975 val
= MAC_PHYCFG2_RTL8201E_LED_MODES
;
981 if (phydev
->interface
!= PHY_INTERFACE_MODE_RGMII
) {
982 tw32(MAC_PHYCFG2
, val
);
984 val
= tr32(MAC_PHYCFG1
);
985 val
&= ~(MAC_PHYCFG1_RGMII_INT
|
986 MAC_PHYCFG1_RXCLK_TO_MASK
| MAC_PHYCFG1_TXCLK_TO_MASK
);
987 val
|= MAC_PHYCFG1_RXCLK_TIMEOUT
| MAC_PHYCFG1_TXCLK_TIMEOUT
;
988 tw32(MAC_PHYCFG1
, val
);
993 if (!(tp
->tg3_flags3
& TG3_FLG3_RGMII_INBAND_DISABLE
))
994 val
|= MAC_PHYCFG2_EMODE_MASK_MASK
|
995 MAC_PHYCFG2_FMODE_MASK_MASK
|
996 MAC_PHYCFG2_GMODE_MASK_MASK
|
997 MAC_PHYCFG2_ACT_MASK_MASK
|
998 MAC_PHYCFG2_QUAL_MASK_MASK
|
999 MAC_PHYCFG2_INBAND_ENABLE
;
1001 tw32(MAC_PHYCFG2
, val
);
1003 val
= tr32(MAC_PHYCFG1
);
1004 val
&= ~(MAC_PHYCFG1_RXCLK_TO_MASK
| MAC_PHYCFG1_TXCLK_TO_MASK
|
1005 MAC_PHYCFG1_RGMII_EXT_RX_DEC
| MAC_PHYCFG1_RGMII_SND_STAT_EN
);
1006 if (!(tp
->tg3_flags3
& TG3_FLG3_RGMII_INBAND_DISABLE
)) {
1007 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_RX_EN
)
1008 val
|= MAC_PHYCFG1_RGMII_EXT_RX_DEC
;
1009 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_TX_EN
)
1010 val
|= MAC_PHYCFG1_RGMII_SND_STAT_EN
;
1012 val
|= MAC_PHYCFG1_RXCLK_TIMEOUT
| MAC_PHYCFG1_TXCLK_TIMEOUT
|
1013 MAC_PHYCFG1_RGMII_INT
| MAC_PHYCFG1_TXC_DRV
;
1014 tw32(MAC_PHYCFG1
, val
);
1016 val
= tr32(MAC_EXT_RGMII_MODE
);
1017 val
&= ~(MAC_RGMII_MODE_RX_INT_B
|
1018 MAC_RGMII_MODE_RX_QUALITY
|
1019 MAC_RGMII_MODE_RX_ACTIVITY
|
1020 MAC_RGMII_MODE_RX_ENG_DET
|
1021 MAC_RGMII_MODE_TX_ENABLE
|
1022 MAC_RGMII_MODE_TX_LOWPWR
|
1023 MAC_RGMII_MODE_TX_RESET
);
1024 if (!(tp
->tg3_flags3
& TG3_FLG3_RGMII_INBAND_DISABLE
)) {
1025 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_RX_EN
)
1026 val
|= MAC_RGMII_MODE_RX_INT_B
|
1027 MAC_RGMII_MODE_RX_QUALITY
|
1028 MAC_RGMII_MODE_RX_ACTIVITY
|
1029 MAC_RGMII_MODE_RX_ENG_DET
;
1030 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_TX_EN
)
1031 val
|= MAC_RGMII_MODE_TX_ENABLE
|
1032 MAC_RGMII_MODE_TX_LOWPWR
|
1033 MAC_RGMII_MODE_TX_RESET
;
1035 tw32(MAC_EXT_RGMII_MODE
, val
);
1038 static void tg3_mdio_start(struct tg3
*tp
)
1040 tp
->mi_mode
&= ~MAC_MI_MODE_AUTO_POLL
;
1041 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
1044 if ((tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_INITED
) &&
1045 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
1046 tg3_mdio_config_5785(tp
);
1049 static int tg3_mdio_init(struct tg3
*tp
)
1053 struct phy_device
*phydev
;
1055 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
1056 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
) {
1059 tp
->phy_addr
= PCI_FUNC(tp
->pdev
->devfn
) + 1;
1061 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5717_A0
)
1062 is_serdes
= tr32(SG_DIG_STATUS
) & SG_DIG_IS_SERDES
;
1064 is_serdes
= tr32(TG3_CPMU_PHY_STRAP
) &
1065 TG3_CPMU_PHY_STRAP_IS_SERDES
;
1069 tp
->phy_addr
= TG3_PHY_MII_ADDR
;
1073 if (!(tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) ||
1074 (tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_INITED
))
1077 tp
->mdio_bus
= mdiobus_alloc();
1078 if (tp
->mdio_bus
== NULL
)
1081 tp
->mdio_bus
->name
= "tg3 mdio bus";
1082 snprintf(tp
->mdio_bus
->id
, MII_BUS_ID_SIZE
, "%x",
1083 (tp
->pdev
->bus
->number
<< 8) | tp
->pdev
->devfn
);
1084 tp
->mdio_bus
->priv
= tp
;
1085 tp
->mdio_bus
->parent
= &tp
->pdev
->dev
;
1086 tp
->mdio_bus
->read
= &tg3_mdio_read
;
1087 tp
->mdio_bus
->write
= &tg3_mdio_write
;
1088 tp
->mdio_bus
->reset
= &tg3_mdio_reset
;
1089 tp
->mdio_bus
->phy_mask
= ~(1 << TG3_PHY_MII_ADDR
);
1090 tp
->mdio_bus
->irq
= &tp
->mdio_irq
[0];
1092 for (i
= 0; i
< PHY_MAX_ADDR
; i
++)
1093 tp
->mdio_bus
->irq
[i
] = PHY_POLL
;
1095 /* The bus registration will look for all the PHYs on the mdio bus.
1096 * Unfortunately, it does not ensure the PHY is powered up before
1097 * accessing the PHY ID registers. A chip reset is the
1098 * quickest way to bring the device back to an operational state..
1100 if (tg3_readphy(tp
, MII_BMCR
, ®
) || (reg
& BMCR_PDOWN
))
1103 i
= mdiobus_register(tp
->mdio_bus
);
1105 dev_warn(&tp
->pdev
->dev
, "mdiobus_reg failed (0x%x)\n", i
);
1106 mdiobus_free(tp
->mdio_bus
);
1110 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
1112 if (!phydev
|| !phydev
->drv
) {
1113 dev_warn(&tp
->pdev
->dev
, "No PHY devices\n");
1114 mdiobus_unregister(tp
->mdio_bus
);
1115 mdiobus_free(tp
->mdio_bus
);
1119 switch (phydev
->drv
->phy_id
& phydev
->drv
->phy_id_mask
) {
1120 case PHY_ID_BCM57780
:
1121 phydev
->interface
= PHY_INTERFACE_MODE_GMII
;
1122 phydev
->dev_flags
|= PHY_BRCM_AUTO_PWRDWN_ENABLE
;
1124 case PHY_ID_BCM50610
:
1125 case PHY_ID_BCM50610M
:
1126 phydev
->dev_flags
|= PHY_BRCM_CLEAR_RGMII_MODE
|
1127 PHY_BRCM_RX_REFCLK_UNUSED
|
1128 PHY_BRCM_DIS_TXCRXC_NOENRGY
|
1129 PHY_BRCM_AUTO_PWRDWN_ENABLE
;
1130 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_INBAND_DISABLE
)
1131 phydev
->dev_flags
|= PHY_BRCM_STD_IBND_DISABLE
;
1132 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_RX_EN
)
1133 phydev
->dev_flags
|= PHY_BRCM_EXT_IBND_RX_ENABLE
;
1134 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_TX_EN
)
1135 phydev
->dev_flags
|= PHY_BRCM_EXT_IBND_TX_ENABLE
;
1137 case PHY_ID_RTL8211C
:
1138 phydev
->interface
= PHY_INTERFACE_MODE_RGMII
;
1140 case PHY_ID_RTL8201E
:
1141 case PHY_ID_BCMAC131
:
1142 phydev
->interface
= PHY_INTERFACE_MODE_MII
;
1143 phydev
->dev_flags
|= PHY_BRCM_AUTO_PWRDWN_ENABLE
;
1144 tp
->phy_flags
|= TG3_PHYFLG_IS_FET
;
1148 tp
->tg3_flags3
|= TG3_FLG3_MDIOBUS_INITED
;
1150 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
1151 tg3_mdio_config_5785(tp
);
1156 static void tg3_mdio_fini(struct tg3
*tp
)
1158 if (tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_INITED
) {
1159 tp
->tg3_flags3
&= ~TG3_FLG3_MDIOBUS_INITED
;
1160 mdiobus_unregister(tp
->mdio_bus
);
1161 mdiobus_free(tp
->mdio_bus
);
1165 /* tp->lock is held. */
1166 static inline void tg3_generate_fw_event(struct tg3
*tp
)
1170 val
= tr32(GRC_RX_CPU_EVENT
);
1171 val
|= GRC_RX_CPU_DRIVER_EVENT
;
1172 tw32_f(GRC_RX_CPU_EVENT
, val
);
1174 tp
->last_event_jiffies
= jiffies
;
1177 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1179 /* tp->lock is held. */
1180 static void tg3_wait_for_event_ack(struct tg3
*tp
)
1183 unsigned int delay_cnt
;
1186 /* If enough time has passed, no wait is necessary. */
1187 time_remain
= (long)(tp
->last_event_jiffies
+ 1 +
1188 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC
)) -
1190 if (time_remain
< 0)
1193 /* Check if we can shorten the wait time. */
1194 delay_cnt
= jiffies_to_usecs(time_remain
);
1195 if (delay_cnt
> TG3_FW_EVENT_TIMEOUT_USEC
)
1196 delay_cnt
= TG3_FW_EVENT_TIMEOUT_USEC
;
1197 delay_cnt
= (delay_cnt
>> 3) + 1;
1199 for (i
= 0; i
< delay_cnt
; i
++) {
1200 if (!(tr32(GRC_RX_CPU_EVENT
) & GRC_RX_CPU_DRIVER_EVENT
))
1206 /* tp->lock is held. */
1207 static void tg3_ump_link_report(struct tg3
*tp
)
1212 if (!(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) ||
1213 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
1216 tg3_wait_for_event_ack(tp
);
1218 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_MBOX
, FWCMD_NICDRV_LINK_UPDATE
);
1220 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_LEN_MBOX
, 14);
1223 if (!tg3_readphy(tp
, MII_BMCR
, ®
))
1225 if (!tg3_readphy(tp
, MII_BMSR
, ®
))
1226 val
|= (reg
& 0xffff);
1227 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
, val
);
1230 if (!tg3_readphy(tp
, MII_ADVERTISE
, ®
))
1232 if (!tg3_readphy(tp
, MII_LPA
, ®
))
1233 val
|= (reg
& 0xffff);
1234 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
+ 4, val
);
1237 if (!(tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
)) {
1238 if (!tg3_readphy(tp
, MII_CTRL1000
, ®
))
1240 if (!tg3_readphy(tp
, MII_STAT1000
, ®
))
1241 val
|= (reg
& 0xffff);
1243 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
+ 8, val
);
1245 if (!tg3_readphy(tp
, MII_PHYADDR
, ®
))
1249 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
+ 12, val
);
1251 tg3_generate_fw_event(tp
);
1254 static void tg3_link_report(struct tg3
*tp
)
1256 if (!netif_carrier_ok(tp
->dev
)) {
1257 netif_info(tp
, link
, tp
->dev
, "Link is down\n");
1258 tg3_ump_link_report(tp
);
1259 } else if (netif_msg_link(tp
)) {
1260 netdev_info(tp
->dev
, "Link is up at %d Mbps, %s duplex\n",
1261 (tp
->link_config
.active_speed
== SPEED_1000
?
1263 (tp
->link_config
.active_speed
== SPEED_100
?
1265 (tp
->link_config
.active_duplex
== DUPLEX_FULL
?
1268 netdev_info(tp
->dev
, "Flow control is %s for TX and %s for RX\n",
1269 (tp
->link_config
.active_flowctrl
& FLOW_CTRL_TX
) ?
1271 (tp
->link_config
.active_flowctrl
& FLOW_CTRL_RX
) ?
1273 tg3_ump_link_report(tp
);
1277 static u16
tg3_advert_flowctrl_1000T(u8 flow_ctrl
)
1281 if ((flow_ctrl
& FLOW_CTRL_TX
) && (flow_ctrl
& FLOW_CTRL_RX
))
1282 miireg
= ADVERTISE_PAUSE_CAP
;
1283 else if (flow_ctrl
& FLOW_CTRL_TX
)
1284 miireg
= ADVERTISE_PAUSE_ASYM
;
1285 else if (flow_ctrl
& FLOW_CTRL_RX
)
1286 miireg
= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
1293 static u16
tg3_advert_flowctrl_1000X(u8 flow_ctrl
)
1297 if ((flow_ctrl
& FLOW_CTRL_TX
) && (flow_ctrl
& FLOW_CTRL_RX
))
1298 miireg
= ADVERTISE_1000XPAUSE
;
1299 else if (flow_ctrl
& FLOW_CTRL_TX
)
1300 miireg
= ADVERTISE_1000XPSE_ASYM
;
1301 else if (flow_ctrl
& FLOW_CTRL_RX
)
1302 miireg
= ADVERTISE_1000XPAUSE
| ADVERTISE_1000XPSE_ASYM
;
1309 static u8
tg3_resolve_flowctrl_1000X(u16 lcladv
, u16 rmtadv
)
1313 if (lcladv
& ADVERTISE_1000XPAUSE
) {
1314 if (lcladv
& ADVERTISE_1000XPSE_ASYM
) {
1315 if (rmtadv
& LPA_1000XPAUSE
)
1316 cap
= FLOW_CTRL_TX
| FLOW_CTRL_RX
;
1317 else if (rmtadv
& LPA_1000XPAUSE_ASYM
)
1320 if (rmtadv
& LPA_1000XPAUSE
)
1321 cap
= FLOW_CTRL_TX
| FLOW_CTRL_RX
;
1323 } else if (lcladv
& ADVERTISE_1000XPSE_ASYM
) {
1324 if ((rmtadv
& LPA_1000XPAUSE
) && (rmtadv
& LPA_1000XPAUSE_ASYM
))
1331 static void tg3_setup_flow_control(struct tg3
*tp
, u32 lcladv
, u32 rmtadv
)
1335 u32 old_rx_mode
= tp
->rx_mode
;
1336 u32 old_tx_mode
= tp
->tx_mode
;
1338 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
)
1339 autoneg
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
]->autoneg
;
1341 autoneg
= tp
->link_config
.autoneg
;
1343 if (autoneg
== AUTONEG_ENABLE
&&
1344 (tp
->tg3_flags
& TG3_FLAG_PAUSE_AUTONEG
)) {
1345 if (tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
)
1346 flowctrl
= tg3_resolve_flowctrl_1000X(lcladv
, rmtadv
);
1348 flowctrl
= mii_resolve_flowctrl_fdx(lcladv
, rmtadv
);
1350 flowctrl
= tp
->link_config
.flowctrl
;
1352 tp
->link_config
.active_flowctrl
= flowctrl
;
1354 if (flowctrl
& FLOW_CTRL_RX
)
1355 tp
->rx_mode
|= RX_MODE_FLOW_CTRL_ENABLE
;
1357 tp
->rx_mode
&= ~RX_MODE_FLOW_CTRL_ENABLE
;
1359 if (old_rx_mode
!= tp
->rx_mode
)
1360 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
1362 if (flowctrl
& FLOW_CTRL_TX
)
1363 tp
->tx_mode
|= TX_MODE_FLOW_CTRL_ENABLE
;
1365 tp
->tx_mode
&= ~TX_MODE_FLOW_CTRL_ENABLE
;
1367 if (old_tx_mode
!= tp
->tx_mode
)
1368 tw32_f(MAC_TX_MODE
, tp
->tx_mode
);
1371 static void tg3_adjust_link(struct net_device
*dev
)
1373 u8 oldflowctrl
, linkmesg
= 0;
1374 u32 mac_mode
, lcl_adv
, rmt_adv
;
1375 struct tg3
*tp
= netdev_priv(dev
);
1376 struct phy_device
*phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
1378 spin_lock_bh(&tp
->lock
);
1380 mac_mode
= tp
->mac_mode
& ~(MAC_MODE_PORT_MODE_MASK
|
1381 MAC_MODE_HALF_DUPLEX
);
1383 oldflowctrl
= tp
->link_config
.active_flowctrl
;
1389 if (phydev
->speed
== SPEED_100
|| phydev
->speed
== SPEED_10
)
1390 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
1391 else if (phydev
->speed
== SPEED_1000
||
1392 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5785
)
1393 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
1395 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
1397 if (phydev
->duplex
== DUPLEX_HALF
)
1398 mac_mode
|= MAC_MODE_HALF_DUPLEX
;
1400 lcl_adv
= tg3_advert_flowctrl_1000T(
1401 tp
->link_config
.flowctrl
);
1404 rmt_adv
= LPA_PAUSE_CAP
;
1405 if (phydev
->asym_pause
)
1406 rmt_adv
|= LPA_PAUSE_ASYM
;
1409 tg3_setup_flow_control(tp
, lcl_adv
, rmt_adv
);
1411 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
1413 if (mac_mode
!= tp
->mac_mode
) {
1414 tp
->mac_mode
= mac_mode
;
1415 tw32_f(MAC_MODE
, tp
->mac_mode
);
1419 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
) {
1420 if (phydev
->speed
== SPEED_10
)
1422 MAC_MI_STAT_10MBPS_MODE
|
1423 MAC_MI_STAT_LNKSTAT_ATTN_ENAB
);
1425 tw32(MAC_MI_STAT
, MAC_MI_STAT_LNKSTAT_ATTN_ENAB
);
1428 if (phydev
->speed
== SPEED_1000
&& phydev
->duplex
== DUPLEX_HALF
)
1429 tw32(MAC_TX_LENGTHS
,
1430 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
1431 (6 << TX_LENGTHS_IPG_SHIFT
) |
1432 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT
)));
1434 tw32(MAC_TX_LENGTHS
,
1435 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
1436 (6 << TX_LENGTHS_IPG_SHIFT
) |
1437 (32 << TX_LENGTHS_SLOT_TIME_SHIFT
)));
1439 if ((phydev
->link
&& tp
->link_config
.active_speed
== SPEED_INVALID
) ||
1440 (!phydev
->link
&& tp
->link_config
.active_speed
!= SPEED_INVALID
) ||
1441 phydev
->speed
!= tp
->link_config
.active_speed
||
1442 phydev
->duplex
!= tp
->link_config
.active_duplex
||
1443 oldflowctrl
!= tp
->link_config
.active_flowctrl
)
1446 tp
->link_config
.active_speed
= phydev
->speed
;
1447 tp
->link_config
.active_duplex
= phydev
->duplex
;
1449 spin_unlock_bh(&tp
->lock
);
1452 tg3_link_report(tp
);
1455 static int tg3_phy_init(struct tg3
*tp
)
1457 struct phy_device
*phydev
;
1459 if (tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
)
1462 /* Bring the PHY back to a known state. */
1465 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
1467 /* Attach the MAC to the PHY. */
1468 phydev
= phy_connect(tp
->dev
, dev_name(&phydev
->dev
), tg3_adjust_link
,
1469 phydev
->dev_flags
, phydev
->interface
);
1470 if (IS_ERR(phydev
)) {
1471 dev_err(&tp
->pdev
->dev
, "Could not attach to PHY\n");
1472 return PTR_ERR(phydev
);
1475 /* Mask with MAC supported features. */
1476 switch (phydev
->interface
) {
1477 case PHY_INTERFACE_MODE_GMII
:
1478 case PHY_INTERFACE_MODE_RGMII
:
1479 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
)) {
1480 phydev
->supported
&= (PHY_GBIT_FEATURES
|
1482 SUPPORTED_Asym_Pause
);
1486 case PHY_INTERFACE_MODE_MII
:
1487 phydev
->supported
&= (PHY_BASIC_FEATURES
|
1489 SUPPORTED_Asym_Pause
);
1492 phy_disconnect(tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
]);
1496 tp
->phy_flags
|= TG3_PHYFLG_IS_CONNECTED
;
1498 phydev
->advertising
= phydev
->supported
;
1503 static void tg3_phy_start(struct tg3
*tp
)
1505 struct phy_device
*phydev
;
1507 if (!(tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
))
1510 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
1512 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
) {
1513 tp
->phy_flags
&= ~TG3_PHYFLG_IS_LOW_POWER
;
1514 phydev
->speed
= tp
->link_config
.orig_speed
;
1515 phydev
->duplex
= tp
->link_config
.orig_duplex
;
1516 phydev
->autoneg
= tp
->link_config
.orig_autoneg
;
1517 phydev
->advertising
= tp
->link_config
.orig_advertising
;
1522 phy_start_aneg(phydev
);
1525 static void tg3_phy_stop(struct tg3
*tp
)
1527 if (!(tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
))
1530 phy_stop(tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
]);
1533 static void tg3_phy_fini(struct tg3
*tp
)
1535 if (tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
) {
1536 phy_disconnect(tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
]);
1537 tp
->phy_flags
&= ~TG3_PHYFLG_IS_CONNECTED
;
1541 static int tg3_phydsp_write(struct tg3
*tp
, u32 reg
, u32 val
)
1545 err
= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, reg
);
1547 err
= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, val
);
1552 static void tg3_phy_fet_toggle_apd(struct tg3
*tp
, bool enable
)
1556 if (!tg3_readphy(tp
, MII_TG3_FET_TEST
, &phytest
)) {
1559 tg3_writephy(tp
, MII_TG3_FET_TEST
,
1560 phytest
| MII_TG3_FET_SHADOW_EN
);
1561 if (!tg3_readphy(tp
, MII_TG3_FET_SHDW_AUXSTAT2
, &phy
)) {
1563 phy
|= MII_TG3_FET_SHDW_AUXSTAT2_APD
;
1565 phy
&= ~MII_TG3_FET_SHDW_AUXSTAT2_APD
;
1566 tg3_writephy(tp
, MII_TG3_FET_SHDW_AUXSTAT2
, phy
);
1568 tg3_writephy(tp
, MII_TG3_FET_TEST
, phytest
);
1572 static void tg3_phy_toggle_apd(struct tg3
*tp
, bool enable
)
1576 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) ||
1577 ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
1578 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
) &&
1579 (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
)))
1582 if (tp
->phy_flags
& TG3_PHYFLG_IS_FET
) {
1583 tg3_phy_fet_toggle_apd(tp
, enable
);
1587 reg
= MII_TG3_MISC_SHDW_WREN
|
1588 MII_TG3_MISC_SHDW_SCR5_SEL
|
1589 MII_TG3_MISC_SHDW_SCR5_LPED
|
1590 MII_TG3_MISC_SHDW_SCR5_DLPTLM
|
1591 MII_TG3_MISC_SHDW_SCR5_SDTL
|
1592 MII_TG3_MISC_SHDW_SCR5_C125OE
;
1593 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5784
|| !enable
)
1594 reg
|= MII_TG3_MISC_SHDW_SCR5_DLLAPD
;
1596 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, reg
);
1599 reg
= MII_TG3_MISC_SHDW_WREN
|
1600 MII_TG3_MISC_SHDW_APD_SEL
|
1601 MII_TG3_MISC_SHDW_APD_WKTM_84MS
;
1603 reg
|= MII_TG3_MISC_SHDW_APD_ENABLE
;
1605 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, reg
);
1608 static void tg3_phy_toggle_automdix(struct tg3
*tp
, int enable
)
1612 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) ||
1613 (tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
))
1616 if (tp
->phy_flags
& TG3_PHYFLG_IS_FET
) {
1619 if (!tg3_readphy(tp
, MII_TG3_FET_TEST
, &ephy
)) {
1620 u32 reg
= MII_TG3_FET_SHDW_MISCCTRL
;
1622 tg3_writephy(tp
, MII_TG3_FET_TEST
,
1623 ephy
| MII_TG3_FET_SHADOW_EN
);
1624 if (!tg3_readphy(tp
, reg
, &phy
)) {
1626 phy
|= MII_TG3_FET_SHDW_MISCCTRL_MDIX
;
1628 phy
&= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX
;
1629 tg3_writephy(tp
, reg
, phy
);
1631 tg3_writephy(tp
, MII_TG3_FET_TEST
, ephy
);
1634 phy
= MII_TG3_AUXCTL_MISC_RDSEL_MISC
|
1635 MII_TG3_AUXCTL_SHDWSEL_MISC
;
1636 if (!tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy
) &&
1637 !tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &phy
)) {
1639 phy
|= MII_TG3_AUXCTL_MISC_FORCE_AMDIX
;
1641 phy
&= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX
;
1642 phy
|= MII_TG3_AUXCTL_MISC_WREN
;
1643 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy
);
1648 static void tg3_phy_set_wirespeed(struct tg3
*tp
)
1652 if (tp
->phy_flags
& TG3_PHYFLG_NO_ETH_WIRE_SPEED
)
1655 if (!tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x7007) &&
1656 !tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &val
))
1657 tg3_writephy(tp
, MII_TG3_AUX_CTRL
,
1658 (val
| (1 << 15) | (1 << 4)));
1661 static void tg3_phy_apply_otp(struct tg3
*tp
)
1670 /* Enable SM_DSP clock and tx 6dB coding. */
1671 phy
= MII_TG3_AUXCTL_SHDWSEL_AUXCTL
|
1672 MII_TG3_AUXCTL_ACTL_SMDSP_ENA
|
1673 MII_TG3_AUXCTL_ACTL_TX_6DB
;
1674 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy
);
1676 phy
= ((otp
& TG3_OTP_AGCTGT_MASK
) >> TG3_OTP_AGCTGT_SHIFT
);
1677 phy
|= MII_TG3_DSP_TAP1_AGCTGT_DFLT
;
1678 tg3_phydsp_write(tp
, MII_TG3_DSP_TAP1
, phy
);
1680 phy
= ((otp
& TG3_OTP_HPFFLTR_MASK
) >> TG3_OTP_HPFFLTR_SHIFT
) |
1681 ((otp
& TG3_OTP_HPFOVER_MASK
) >> TG3_OTP_HPFOVER_SHIFT
);
1682 tg3_phydsp_write(tp
, MII_TG3_DSP_AADJ1CH0
, phy
);
1684 phy
= ((otp
& TG3_OTP_LPFDIS_MASK
) >> TG3_OTP_LPFDIS_SHIFT
);
1685 phy
|= MII_TG3_DSP_AADJ1CH3_ADCCKADJ
;
1686 tg3_phydsp_write(tp
, MII_TG3_DSP_AADJ1CH3
, phy
);
1688 phy
= ((otp
& TG3_OTP_VDAC_MASK
) >> TG3_OTP_VDAC_SHIFT
);
1689 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP75
, phy
);
1691 phy
= ((otp
& TG3_OTP_10BTAMP_MASK
) >> TG3_OTP_10BTAMP_SHIFT
);
1692 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP96
, phy
);
1694 phy
= ((otp
& TG3_OTP_ROFF_MASK
) >> TG3_OTP_ROFF_SHIFT
) |
1695 ((otp
& TG3_OTP_RCOFF_MASK
) >> TG3_OTP_RCOFF_SHIFT
);
1696 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP97
, phy
);
1698 /* Turn off SM_DSP clock. */
1699 phy
= MII_TG3_AUXCTL_SHDWSEL_AUXCTL
|
1700 MII_TG3_AUXCTL_ACTL_TX_6DB
;
1701 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy
);
1704 static int tg3_wait_macro_done(struct tg3
*tp
)
1711 if (!tg3_readphy(tp
, MII_TG3_DSP_CONTROL
, &tmp32
)) {
1712 if ((tmp32
& 0x1000) == 0)
1722 static int tg3_phy_write_and_check_testpat(struct tg3
*tp
, int *resetp
)
1724 static const u32 test_pat
[4][6] = {
1725 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1726 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1727 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1728 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1732 for (chan
= 0; chan
< 4; chan
++) {
1735 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
1736 (chan
* 0x2000) | 0x0200);
1737 tg3_writephy(tp
, MII_TG3_DSP_CONTROL
, 0x0002);
1739 for (i
= 0; i
< 6; i
++)
1740 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
,
1743 tg3_writephy(tp
, MII_TG3_DSP_CONTROL
, 0x0202);
1744 if (tg3_wait_macro_done(tp
)) {
1749 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
1750 (chan
* 0x2000) | 0x0200);
1751 tg3_writephy(tp
, MII_TG3_DSP_CONTROL
, 0x0082);
1752 if (tg3_wait_macro_done(tp
)) {
1757 tg3_writephy(tp
, MII_TG3_DSP_CONTROL
, 0x0802);
1758 if (tg3_wait_macro_done(tp
)) {
1763 for (i
= 0; i
< 6; i
+= 2) {
1766 if (tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &low
) ||
1767 tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &high
) ||
1768 tg3_wait_macro_done(tp
)) {
1774 if (low
!= test_pat
[chan
][i
] ||
1775 high
!= test_pat
[chan
][i
+1]) {
1776 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x000b);
1777 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x4001);
1778 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x4005);
1788 static int tg3_phy_reset_chanpat(struct tg3
*tp
)
1792 for (chan
= 0; chan
< 4; chan
++) {
1795 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
1796 (chan
* 0x2000) | 0x0200);
1797 tg3_writephy(tp
, MII_TG3_DSP_CONTROL
, 0x0002);
1798 for (i
= 0; i
< 6; i
++)
1799 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x000);
1800 tg3_writephy(tp
, MII_TG3_DSP_CONTROL
, 0x0202);
1801 if (tg3_wait_macro_done(tp
))
1808 static int tg3_phy_reset_5703_4_5(struct tg3
*tp
)
1810 u32 reg32
, phy9_orig
;
1811 int retries
, do_phy_reset
, err
;
1817 err
= tg3_bmcr_reset(tp
);
1823 /* Disable transmitter and interrupt. */
1824 if (tg3_readphy(tp
, MII_TG3_EXT_CTRL
, ®32
))
1828 tg3_writephy(tp
, MII_TG3_EXT_CTRL
, reg32
);
1830 /* Set full-duplex, 1000 mbps. */
1831 tg3_writephy(tp
, MII_BMCR
,
1832 BMCR_FULLDPLX
| TG3_BMCR_SPEED1000
);
1834 /* Set to master mode. */
1835 if (tg3_readphy(tp
, MII_TG3_CTRL
, &phy9_orig
))
1838 tg3_writephy(tp
, MII_TG3_CTRL
,
1839 (MII_TG3_CTRL_AS_MASTER
|
1840 MII_TG3_CTRL_ENABLE_AS_MASTER
));
1842 /* Enable SM_DSP_CLOCK and 6dB. */
1843 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
1845 /* Block the PHY control access. */
1846 tg3_phydsp_write(tp
, 0x8005, 0x0800);
1848 err
= tg3_phy_write_and_check_testpat(tp
, &do_phy_reset
);
1851 } while (--retries
);
1853 err
= tg3_phy_reset_chanpat(tp
);
1857 tg3_phydsp_write(tp
, 0x8005, 0x0000);
1859 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8200);
1860 tg3_writephy(tp
, MII_TG3_DSP_CONTROL
, 0x0000);
1862 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
1863 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
1864 /* Set Extended packet length bit for jumbo frames */
1865 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4400);
1867 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
1870 tg3_writephy(tp
, MII_TG3_CTRL
, phy9_orig
);
1872 if (!tg3_readphy(tp
, MII_TG3_EXT_CTRL
, ®32
)) {
1874 tg3_writephy(tp
, MII_TG3_EXT_CTRL
, reg32
);
1881 /* This will reset the tigon3 PHY if there is no valid
1882 * link unless the FORCE argument is non-zero.
1884 static int tg3_phy_reset(struct tg3
*tp
)
1889 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
1890 val
= tr32(GRC_MISC_CFG
);
1891 tw32_f(GRC_MISC_CFG
, val
& ~GRC_MISC_CFG_EPHY_IDDQ
);
1894 err
= tg3_readphy(tp
, MII_BMSR
, &val
);
1895 err
|= tg3_readphy(tp
, MII_BMSR
, &val
);
1899 if (netif_running(tp
->dev
) && netif_carrier_ok(tp
->dev
)) {
1900 netif_carrier_off(tp
->dev
);
1901 tg3_link_report(tp
);
1904 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
1905 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
1906 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
1907 err
= tg3_phy_reset_5703_4_5(tp
);
1914 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
1915 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
) {
1916 cpmuctrl
= tr32(TG3_CPMU_CTRL
);
1917 if (cpmuctrl
& CPMU_CTRL_GPHY_10MB_RXONLY
)
1919 cpmuctrl
& ~CPMU_CTRL_GPHY_10MB_RXONLY
);
1922 err
= tg3_bmcr_reset(tp
);
1926 if (cpmuctrl
& CPMU_CTRL_GPHY_10MB_RXONLY
) {
1927 val
= MII_TG3_DSP_EXP8_AEDW
| MII_TG3_DSP_EXP8_REJ2MHz
;
1928 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP8
, val
);
1930 tw32(TG3_CPMU_CTRL
, cpmuctrl
);
1933 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
||
1934 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5761_AX
) {
1935 val
= tr32(TG3_CPMU_LSPD_1000MB_CLK
);
1936 if ((val
& CPMU_LSPD_1000MB_MACCLK_MASK
) ==
1937 CPMU_LSPD_1000MB_MACCLK_12_5
) {
1938 val
&= ~CPMU_LSPD_1000MB_MACCLK_MASK
;
1940 tw32_f(TG3_CPMU_LSPD_1000MB_CLK
, val
);
1944 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
1945 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
) &&
1946 (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
))
1949 tg3_phy_apply_otp(tp
);
1951 if (tp
->phy_flags
& TG3_PHYFLG_ENABLE_APD
)
1952 tg3_phy_toggle_apd(tp
, true);
1954 tg3_phy_toggle_apd(tp
, false);
1957 if (tp
->phy_flags
& TG3_PHYFLG_ADC_BUG
) {
1958 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
1959 tg3_phydsp_write(tp
, 0x201f, 0x2aaa);
1960 tg3_phydsp_write(tp
, 0x000a, 0x0323);
1961 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
1963 if (tp
->phy_flags
& TG3_PHYFLG_5704_A0_BUG
) {
1964 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, 0x8d68);
1965 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, 0x8d68);
1967 if (tp
->phy_flags
& TG3_PHYFLG_BER_BUG
) {
1968 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
1969 tg3_phydsp_write(tp
, 0x000a, 0x310b);
1970 tg3_phydsp_write(tp
, 0x201f, 0x9506);
1971 tg3_phydsp_write(tp
, 0x401f, 0x14e2);
1972 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
1973 } else if (tp
->phy_flags
& TG3_PHYFLG_JITTER_BUG
) {
1974 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
1975 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x000a);
1976 if (tp
->phy_flags
& TG3_PHYFLG_ADJUST_TRIM
) {
1977 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x110b);
1978 tg3_writephy(tp
, MII_TG3_TEST1
,
1979 MII_TG3_TEST1_TRIM_EN
| 0x4);
1981 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x010b);
1982 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
1984 /* Set Extended packet length bit (bit 14) on all chips that */
1985 /* support jumbo frames */
1986 if ((tp
->phy_id
& TG3_PHY_ID_MASK
) == TG3_PHY_ID_BCM5401
) {
1987 /* Cannot do read-modify-write on 5401 */
1988 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4c20);
1989 } else if (tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) {
1990 /* Set bit 14 with read-modify-write to preserve other bits */
1991 if (!tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0007) &&
1992 !tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &val
))
1993 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, val
| 0x4000);
1996 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1997 * jumbo frames transmission.
1999 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) {
2000 if (!tg3_readphy(tp
, MII_TG3_EXT_CTRL
, &val
))
2001 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
2002 val
| MII_TG3_EXT_CTRL_FIFO_ELASTIC
);
2005 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
2006 /* adjust output voltage */
2007 tg3_writephy(tp
, MII_TG3_FET_PTEST
, 0x12);
2010 tg3_phy_toggle_automdix(tp
, 1);
2011 tg3_phy_set_wirespeed(tp
);
2015 static void tg3_frob_aux_power(struct tg3
*tp
)
2017 struct tg3
*tp_peer
= tp
;
2019 /* The GPIOs do something completely different on 57765. */
2020 if ((tp
->tg3_flags2
& TG3_FLG2_IS_NIC
) == 0 ||
2021 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
||
2022 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
2025 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
2026 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
||
2027 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
) {
2028 struct net_device
*dev_peer
;
2030 dev_peer
= pci_get_drvdata(tp
->pdev_peer
);
2031 /* remove_one() may have been run on the peer. */
2035 tp_peer
= netdev_priv(dev_peer
);
2038 if ((tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
) != 0 ||
2039 (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) != 0 ||
2040 (tp_peer
->tg3_flags
& TG3_FLAG_WOL_ENABLE
) != 0 ||
2041 (tp_peer
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) != 0) {
2042 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2043 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
2044 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2045 (GRC_LCLCTRL_GPIO_OE0
|
2046 GRC_LCLCTRL_GPIO_OE1
|
2047 GRC_LCLCTRL_GPIO_OE2
|
2048 GRC_LCLCTRL_GPIO_OUTPUT0
|
2049 GRC_LCLCTRL_GPIO_OUTPUT1
),
2051 } else if (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5761
||
2052 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5761S
) {
2053 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2054 u32 grc_local_ctrl
= GRC_LCLCTRL_GPIO_OE0
|
2055 GRC_LCLCTRL_GPIO_OE1
|
2056 GRC_LCLCTRL_GPIO_OE2
|
2057 GRC_LCLCTRL_GPIO_OUTPUT0
|
2058 GRC_LCLCTRL_GPIO_OUTPUT1
|
2060 tw32_wait_f(GRC_LOCAL_CTRL
, grc_local_ctrl
, 100);
2062 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OUTPUT2
;
2063 tw32_wait_f(GRC_LOCAL_CTRL
, grc_local_ctrl
, 100);
2065 grc_local_ctrl
&= ~GRC_LCLCTRL_GPIO_OUTPUT0
;
2066 tw32_wait_f(GRC_LOCAL_CTRL
, grc_local_ctrl
, 100);
2069 u32 grc_local_ctrl
= 0;
2071 if (tp_peer
!= tp
&&
2072 (tp_peer
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
) != 0)
2075 /* Workaround to prevent overdrawing Amps. */
2076 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
2078 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE3
;
2079 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2080 grc_local_ctrl
, 100);
2083 /* On 5753 and variants, GPIO2 cannot be used. */
2084 no_gpio2
= tp
->nic_sram_data_cfg
&
2085 NIC_SRAM_DATA_CFG_NO_GPIO2
;
2087 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE0
|
2088 GRC_LCLCTRL_GPIO_OE1
|
2089 GRC_LCLCTRL_GPIO_OE2
|
2090 GRC_LCLCTRL_GPIO_OUTPUT1
|
2091 GRC_LCLCTRL_GPIO_OUTPUT2
;
2093 grc_local_ctrl
&= ~(GRC_LCLCTRL_GPIO_OE2
|
2094 GRC_LCLCTRL_GPIO_OUTPUT2
);
2096 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2097 grc_local_ctrl
, 100);
2099 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OUTPUT0
;
2101 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2102 grc_local_ctrl
, 100);
2105 grc_local_ctrl
&= ~GRC_LCLCTRL_GPIO_OUTPUT2
;
2106 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2107 grc_local_ctrl
, 100);
2111 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
2112 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
) {
2113 if (tp_peer
!= tp
&&
2114 (tp_peer
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
) != 0)
2117 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2118 (GRC_LCLCTRL_GPIO_OE1
|
2119 GRC_LCLCTRL_GPIO_OUTPUT1
), 100);
2121 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2122 GRC_LCLCTRL_GPIO_OE1
, 100);
2124 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2125 (GRC_LCLCTRL_GPIO_OE1
|
2126 GRC_LCLCTRL_GPIO_OUTPUT1
), 100);
2131 static int tg3_5700_link_polarity(struct tg3
*tp
, u32 speed
)
2133 if (tp
->led_ctrl
== LED_CTRL_MODE_PHY_2
)
2135 else if ((tp
->phy_id
& TG3_PHY_ID_MASK
) == TG3_PHY_ID_BCM5411
) {
2136 if (speed
!= SPEED_10
)
2138 } else if (speed
== SPEED_10
)
2144 static int tg3_setup_phy(struct tg3
*, int);
2146 #define RESET_KIND_SHUTDOWN 0
2147 #define RESET_KIND_INIT 1
2148 #define RESET_KIND_SUSPEND 2
2150 static void tg3_write_sig_post_reset(struct tg3
*, int);
2151 static int tg3_halt_cpu(struct tg3
*, u32
);
2153 static void tg3_power_down_phy(struct tg3
*tp
, bool do_low_power
)
2157 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) {
2158 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
2159 u32 sg_dig_ctrl
= tr32(SG_DIG_CTRL
);
2160 u32 serdes_cfg
= tr32(MAC_SERDES_CFG
);
2163 SG_DIG_USING_HW_AUTONEG
| SG_DIG_SOFT_RESET
;
2164 tw32(SG_DIG_CTRL
, sg_dig_ctrl
);
2165 tw32(MAC_SERDES_CFG
, serdes_cfg
| (1 << 15));
2170 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
2172 val
= tr32(GRC_MISC_CFG
);
2173 tw32_f(GRC_MISC_CFG
, val
| GRC_MISC_CFG_EPHY_IDDQ
);
2176 } else if (tp
->phy_flags
& TG3_PHYFLG_IS_FET
) {
2178 if (!tg3_readphy(tp
, MII_TG3_FET_TEST
, &phytest
)) {
2181 tg3_writephy(tp
, MII_ADVERTISE
, 0);
2182 tg3_writephy(tp
, MII_BMCR
,
2183 BMCR_ANENABLE
| BMCR_ANRESTART
);
2185 tg3_writephy(tp
, MII_TG3_FET_TEST
,
2186 phytest
| MII_TG3_FET_SHADOW_EN
);
2187 if (!tg3_readphy(tp
, MII_TG3_FET_SHDW_AUXMODE4
, &phy
)) {
2188 phy
|= MII_TG3_FET_SHDW_AUXMODE4_SBPD
;
2190 MII_TG3_FET_SHDW_AUXMODE4
,
2193 tg3_writephy(tp
, MII_TG3_FET_TEST
, phytest
);
2196 } else if (do_low_power
) {
2197 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
2198 MII_TG3_EXT_CTRL_FORCE_LED_OFF
);
2200 tg3_writephy(tp
, MII_TG3_AUX_CTRL
,
2201 MII_TG3_AUXCTL_SHDWSEL_PWRCTL
|
2202 MII_TG3_AUXCTL_PCTL_100TX_LPWR
|
2203 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE
|
2204 MII_TG3_AUXCTL_PCTL_VREG_11V
);
2207 /* The PHY should not be powered down on some chips because
2210 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2211 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
2212 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5780
&&
2213 (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
)))
2216 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
||
2217 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5761_AX
) {
2218 val
= tr32(TG3_CPMU_LSPD_1000MB_CLK
);
2219 val
&= ~CPMU_LSPD_1000MB_MACCLK_MASK
;
2220 val
|= CPMU_LSPD_1000MB_MACCLK_12_5
;
2221 tw32_f(TG3_CPMU_LSPD_1000MB_CLK
, val
);
2224 tg3_writephy(tp
, MII_BMCR
, BMCR_PDOWN
);
2227 /* tp->lock is held. */
2228 static int tg3_nvram_lock(struct tg3
*tp
)
2230 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
) {
2233 if (tp
->nvram_lock_cnt
== 0) {
2234 tw32(NVRAM_SWARB
, SWARB_REQ_SET1
);
2235 for (i
= 0; i
< 8000; i
++) {
2236 if (tr32(NVRAM_SWARB
) & SWARB_GNT1
)
2241 tw32(NVRAM_SWARB
, SWARB_REQ_CLR1
);
2245 tp
->nvram_lock_cnt
++;
2250 /* tp->lock is held. */
2251 static void tg3_nvram_unlock(struct tg3
*tp
)
2253 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
) {
2254 if (tp
->nvram_lock_cnt
> 0)
2255 tp
->nvram_lock_cnt
--;
2256 if (tp
->nvram_lock_cnt
== 0)
2257 tw32_f(NVRAM_SWARB
, SWARB_REQ_CLR1
);
2261 /* tp->lock is held. */
2262 static void tg3_enable_nvram_access(struct tg3
*tp
)
2264 if ((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
2265 !(tp
->tg3_flags3
& TG3_FLG3_PROTECTED_NVRAM
)) {
2266 u32 nvaccess
= tr32(NVRAM_ACCESS
);
2268 tw32(NVRAM_ACCESS
, nvaccess
| ACCESS_ENABLE
);
2272 /* tp->lock is held. */
2273 static void tg3_disable_nvram_access(struct tg3
*tp
)
2275 if ((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
2276 !(tp
->tg3_flags3
& TG3_FLG3_PROTECTED_NVRAM
)) {
2277 u32 nvaccess
= tr32(NVRAM_ACCESS
);
2279 tw32(NVRAM_ACCESS
, nvaccess
& ~ACCESS_ENABLE
);
2283 static int tg3_nvram_read_using_eeprom(struct tg3
*tp
,
2284 u32 offset
, u32
*val
)
2289 if (offset
> EEPROM_ADDR_ADDR_MASK
|| (offset
% 4) != 0)
2292 tmp
= tr32(GRC_EEPROM_ADDR
) & ~(EEPROM_ADDR_ADDR_MASK
|
2293 EEPROM_ADDR_DEVID_MASK
|
2295 tw32(GRC_EEPROM_ADDR
,
2297 (0 << EEPROM_ADDR_DEVID_SHIFT
) |
2298 ((offset
<< EEPROM_ADDR_ADDR_SHIFT
) &
2299 EEPROM_ADDR_ADDR_MASK
) |
2300 EEPROM_ADDR_READ
| EEPROM_ADDR_START
);
2302 for (i
= 0; i
< 1000; i
++) {
2303 tmp
= tr32(GRC_EEPROM_ADDR
);
2305 if (tmp
& EEPROM_ADDR_COMPLETE
)
2309 if (!(tmp
& EEPROM_ADDR_COMPLETE
))
2312 tmp
= tr32(GRC_EEPROM_DATA
);
2315 * The data will always be opposite the native endian
2316 * format. Perform a blind byteswap to compensate.
2323 #define NVRAM_CMD_TIMEOUT 10000
2325 static int tg3_nvram_exec_cmd(struct tg3
*tp
, u32 nvram_cmd
)
2329 tw32(NVRAM_CMD
, nvram_cmd
);
2330 for (i
= 0; i
< NVRAM_CMD_TIMEOUT
; i
++) {
2332 if (tr32(NVRAM_CMD
) & NVRAM_CMD_DONE
) {
2338 if (i
== NVRAM_CMD_TIMEOUT
)
2344 static u32
tg3_nvram_phys_addr(struct tg3
*tp
, u32 addr
)
2346 if ((tp
->tg3_flags
& TG3_FLAG_NVRAM
) &&
2347 (tp
->tg3_flags
& TG3_FLAG_NVRAM_BUFFERED
) &&
2348 (tp
->tg3_flags2
& TG3_FLG2_FLASH
) &&
2349 !(tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM_ADDR_TRANS
) &&
2350 (tp
->nvram_jedecnum
== JEDEC_ATMEL
))
2352 addr
= ((addr
/ tp
->nvram_pagesize
) <<
2353 ATMEL_AT45DB0X1B_PAGE_POS
) +
2354 (addr
% tp
->nvram_pagesize
);
2359 static u32
tg3_nvram_logical_addr(struct tg3
*tp
, u32 addr
)
2361 if ((tp
->tg3_flags
& TG3_FLAG_NVRAM
) &&
2362 (tp
->tg3_flags
& TG3_FLAG_NVRAM_BUFFERED
) &&
2363 (tp
->tg3_flags2
& TG3_FLG2_FLASH
) &&
2364 !(tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM_ADDR_TRANS
) &&
2365 (tp
->nvram_jedecnum
== JEDEC_ATMEL
))
2367 addr
= ((addr
>> ATMEL_AT45DB0X1B_PAGE_POS
) *
2368 tp
->nvram_pagesize
) +
2369 (addr
& ((1 << ATMEL_AT45DB0X1B_PAGE_POS
) - 1));
2374 /* NOTE: Data read in from NVRAM is byteswapped according to
2375 * the byteswapping settings for all other register accesses.
2376 * tg3 devices are BE devices, so on a BE machine, the data
2377 * returned will be exactly as it is seen in NVRAM. On a LE
2378 * machine, the 32-bit value will be byteswapped.
2380 static int tg3_nvram_read(struct tg3
*tp
, u32 offset
, u32
*val
)
2384 if (!(tp
->tg3_flags
& TG3_FLAG_NVRAM
))
2385 return tg3_nvram_read_using_eeprom(tp
, offset
, val
);
2387 offset
= tg3_nvram_phys_addr(tp
, offset
);
2389 if (offset
> NVRAM_ADDR_MSK
)
2392 ret
= tg3_nvram_lock(tp
);
2396 tg3_enable_nvram_access(tp
);
2398 tw32(NVRAM_ADDR
, offset
);
2399 ret
= tg3_nvram_exec_cmd(tp
, NVRAM_CMD_RD
| NVRAM_CMD_GO
|
2400 NVRAM_CMD_FIRST
| NVRAM_CMD_LAST
| NVRAM_CMD_DONE
);
2403 *val
= tr32(NVRAM_RDDATA
);
2405 tg3_disable_nvram_access(tp
);
2407 tg3_nvram_unlock(tp
);
2412 /* Ensures NVRAM data is in bytestream format. */
2413 static int tg3_nvram_read_be32(struct tg3
*tp
, u32 offset
, __be32
*val
)
2416 int res
= tg3_nvram_read(tp
, offset
, &v
);
2418 *val
= cpu_to_be32(v
);
2422 /* tp->lock is held. */
2423 static void __tg3_set_mac_addr(struct tg3
*tp
, int skip_mac_1
)
2425 u32 addr_high
, addr_low
;
2428 addr_high
= ((tp
->dev
->dev_addr
[0] << 8) |
2429 tp
->dev
->dev_addr
[1]);
2430 addr_low
= ((tp
->dev
->dev_addr
[2] << 24) |
2431 (tp
->dev
->dev_addr
[3] << 16) |
2432 (tp
->dev
->dev_addr
[4] << 8) |
2433 (tp
->dev
->dev_addr
[5] << 0));
2434 for (i
= 0; i
< 4; i
++) {
2435 if (i
== 1 && skip_mac_1
)
2437 tw32(MAC_ADDR_0_HIGH
+ (i
* 8), addr_high
);
2438 tw32(MAC_ADDR_0_LOW
+ (i
* 8), addr_low
);
2441 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
2442 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
2443 for (i
= 0; i
< 12; i
++) {
2444 tw32(MAC_EXTADDR_0_HIGH
+ (i
* 8), addr_high
);
2445 tw32(MAC_EXTADDR_0_LOW
+ (i
* 8), addr_low
);
2449 addr_high
= (tp
->dev
->dev_addr
[0] +
2450 tp
->dev
->dev_addr
[1] +
2451 tp
->dev
->dev_addr
[2] +
2452 tp
->dev
->dev_addr
[3] +
2453 tp
->dev
->dev_addr
[4] +
2454 tp
->dev
->dev_addr
[5]) &
2455 TX_BACKOFF_SEED_MASK
;
2456 tw32(MAC_TX_BACKOFF_SEED
, addr_high
);
2459 static int tg3_set_power_state(struct tg3
*tp
, pci_power_t state
)
2462 bool device_should_wake
, do_low_power
;
2464 /* Make sure register accesses (indirect or otherwise)
2465 * will function correctly.
2467 pci_write_config_dword(tp
->pdev
,
2468 TG3PCI_MISC_HOST_CTRL
,
2469 tp
->misc_host_ctrl
);
2473 pci_enable_wake(tp
->pdev
, state
, false);
2474 pci_set_power_state(tp
->pdev
, PCI_D0
);
2476 /* Switch out of Vaux if it is a NIC */
2477 if (tp
->tg3_flags2
& TG3_FLG2_IS_NIC
)
2478 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
, 100);
2488 netdev_err(tp
->dev
, "Invalid power state (D%d) requested\n",
2493 /* Restore the CLKREQ setting. */
2494 if (tp
->tg3_flags3
& TG3_FLG3_CLKREQ_BUG
) {
2497 pci_read_config_word(tp
->pdev
,
2498 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
2500 lnkctl
|= PCI_EXP_LNKCTL_CLKREQ_EN
;
2501 pci_write_config_word(tp
->pdev
,
2502 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
2506 misc_host_ctrl
= tr32(TG3PCI_MISC_HOST_CTRL
);
2507 tw32(TG3PCI_MISC_HOST_CTRL
,
2508 misc_host_ctrl
| MISC_HOST_CTRL_MASK_PCI_INT
);
2510 device_should_wake
= pci_pme_capable(tp
->pdev
, state
) &&
2511 device_may_wakeup(&tp
->pdev
->dev
) &&
2512 (tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
);
2514 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
2515 do_low_power
= false;
2516 if ((tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
) &&
2517 !(tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)) {
2518 struct phy_device
*phydev
;
2519 u32 phyid
, advertising
;
2521 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
2523 tp
->phy_flags
|= TG3_PHYFLG_IS_LOW_POWER
;
2525 tp
->link_config
.orig_speed
= phydev
->speed
;
2526 tp
->link_config
.orig_duplex
= phydev
->duplex
;
2527 tp
->link_config
.orig_autoneg
= phydev
->autoneg
;
2528 tp
->link_config
.orig_advertising
= phydev
->advertising
;
2530 advertising
= ADVERTISED_TP
|
2532 ADVERTISED_Autoneg
|
2533 ADVERTISED_10baseT_Half
;
2535 if ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) ||
2536 device_should_wake
) {
2537 if (tp
->tg3_flags
& TG3_FLAG_WOL_SPEED_100MB
)
2539 ADVERTISED_100baseT_Half
|
2540 ADVERTISED_100baseT_Full
|
2541 ADVERTISED_10baseT_Full
;
2543 advertising
|= ADVERTISED_10baseT_Full
;
2546 phydev
->advertising
= advertising
;
2548 phy_start_aneg(phydev
);
2550 phyid
= phydev
->drv
->phy_id
& phydev
->drv
->phy_id_mask
;
2551 if (phyid
!= PHY_ID_BCMAC131
) {
2552 phyid
&= PHY_BCM_OUI_MASK
;
2553 if (phyid
== PHY_BCM_OUI_1
||
2554 phyid
== PHY_BCM_OUI_2
||
2555 phyid
== PHY_BCM_OUI_3
)
2556 do_low_power
= true;
2560 do_low_power
= true;
2562 if (!(tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)) {
2563 tp
->phy_flags
|= TG3_PHYFLG_IS_LOW_POWER
;
2564 tp
->link_config
.orig_speed
= tp
->link_config
.speed
;
2565 tp
->link_config
.orig_duplex
= tp
->link_config
.duplex
;
2566 tp
->link_config
.orig_autoneg
= tp
->link_config
.autoneg
;
2569 if (!(tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
)) {
2570 tp
->link_config
.speed
= SPEED_10
;
2571 tp
->link_config
.duplex
= DUPLEX_HALF
;
2572 tp
->link_config
.autoneg
= AUTONEG_ENABLE
;
2573 tg3_setup_phy(tp
, 0);
2577 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
2580 val
= tr32(GRC_VCPU_EXT_CTRL
);
2581 tw32(GRC_VCPU_EXT_CTRL
, val
| GRC_VCPU_EXT_CTRL_DISABLE_WOL
);
2582 } else if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)) {
2586 for (i
= 0; i
< 200; i
++) {
2587 tg3_read_mem(tp
, NIC_SRAM_FW_ASF_STATUS_MBOX
, &val
);
2588 if (val
== ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1
)
2593 if (tp
->tg3_flags
& TG3_FLAG_WOL_CAP
)
2594 tg3_write_mem(tp
, NIC_SRAM_WOL_MBOX
, WOL_SIGNATURE
|
2595 WOL_DRV_STATE_SHUTDOWN
|
2599 if (device_should_wake
) {
2602 if (!(tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
)) {
2604 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x5a);
2608 if (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
)
2609 mac_mode
= MAC_MODE_PORT_MODE_GMII
;
2611 mac_mode
= MAC_MODE_PORT_MODE_MII
;
2613 mac_mode
|= tp
->mac_mode
& MAC_MODE_LINK_POLARITY
;
2614 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
2616 u32 speed
= (tp
->tg3_flags
&
2617 TG3_FLAG_WOL_SPEED_100MB
) ?
2618 SPEED_100
: SPEED_10
;
2619 if (tg3_5700_link_polarity(tp
, speed
))
2620 mac_mode
|= MAC_MODE_LINK_POLARITY
;
2622 mac_mode
&= ~MAC_MODE_LINK_POLARITY
;
2625 mac_mode
= MAC_MODE_PORT_MODE_TBI
;
2628 if (!(tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
))
2629 tw32(MAC_LED_CTRL
, tp
->led_ctrl
);
2631 mac_mode
|= MAC_MODE_MAGIC_PKT_ENABLE
;
2632 if (((tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
2633 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) &&
2634 ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) ||
2635 (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)))
2636 mac_mode
|= MAC_MODE_KEEP_FRAME_IN_WOL
;
2638 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
2639 mac_mode
|= tp
->mac_mode
&
2640 (MAC_MODE_APE_TX_EN
| MAC_MODE_APE_RX_EN
);
2641 if (mac_mode
& MAC_MODE_APE_TX_EN
)
2642 mac_mode
|= MAC_MODE_TDE_ENABLE
;
2645 tw32_f(MAC_MODE
, mac_mode
);
2648 tw32_f(MAC_RX_MODE
, RX_MODE_ENABLE
);
2652 if (!(tp
->tg3_flags
& TG3_FLAG_WOL_SPEED_100MB
) &&
2653 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2654 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)) {
2657 base_val
= tp
->pci_clock_ctrl
;
2658 base_val
|= (CLOCK_CTRL_RXCLK_DISABLE
|
2659 CLOCK_CTRL_TXCLK_DISABLE
);
2661 tw32_wait_f(TG3PCI_CLOCK_CTRL
, base_val
| CLOCK_CTRL_ALTCLK
|
2662 CLOCK_CTRL_PWRDOWN_PLL133
, 40);
2663 } else if ((tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) ||
2664 (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) ||
2665 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)) {
2667 } else if (!((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
2668 (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))) {
2669 u32 newbits1
, newbits2
;
2671 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2672 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
2673 newbits1
= (CLOCK_CTRL_RXCLK_DISABLE
|
2674 CLOCK_CTRL_TXCLK_DISABLE
|
2676 newbits2
= newbits1
| CLOCK_CTRL_44MHZ_CORE
;
2677 } else if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
2678 newbits1
= CLOCK_CTRL_625_CORE
;
2679 newbits2
= newbits1
| CLOCK_CTRL_ALTCLK
;
2681 newbits1
= CLOCK_CTRL_ALTCLK
;
2682 newbits2
= newbits1
| CLOCK_CTRL_44MHZ_CORE
;
2685 tw32_wait_f(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
| newbits1
,
2688 tw32_wait_f(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
| newbits2
,
2691 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
2694 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2695 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
2696 newbits3
= (CLOCK_CTRL_RXCLK_DISABLE
|
2697 CLOCK_CTRL_TXCLK_DISABLE
|
2698 CLOCK_CTRL_44MHZ_CORE
);
2700 newbits3
= CLOCK_CTRL_44MHZ_CORE
;
2703 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
2704 tp
->pci_clock_ctrl
| newbits3
, 40);
2708 if (!(device_should_wake
) &&
2709 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
2710 tg3_power_down_phy(tp
, do_low_power
);
2712 tg3_frob_aux_power(tp
);
2714 /* Workaround for unstable PLL clock */
2715 if ((GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_AX
) ||
2716 (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_BX
)) {
2717 u32 val
= tr32(0x7d00);
2719 val
&= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2721 if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)) {
2724 err
= tg3_nvram_lock(tp
);
2725 tg3_halt_cpu(tp
, RX_CPU_BASE
);
2727 tg3_nvram_unlock(tp
);
2731 tg3_write_sig_post_reset(tp
, RESET_KIND_SHUTDOWN
);
2733 if (device_should_wake
)
2734 pci_enable_wake(tp
->pdev
, state
, true);
2736 /* Finally, set the new power state. */
2737 pci_set_power_state(tp
->pdev
, state
);
2742 static void tg3_aux_stat_to_speed_duplex(struct tg3
*tp
, u32 val
, u16
*speed
, u8
*duplex
)
2744 switch (val
& MII_TG3_AUX_STAT_SPDMASK
) {
2745 case MII_TG3_AUX_STAT_10HALF
:
2747 *duplex
= DUPLEX_HALF
;
2750 case MII_TG3_AUX_STAT_10FULL
:
2752 *duplex
= DUPLEX_FULL
;
2755 case MII_TG3_AUX_STAT_100HALF
:
2757 *duplex
= DUPLEX_HALF
;
2760 case MII_TG3_AUX_STAT_100FULL
:
2762 *duplex
= DUPLEX_FULL
;
2765 case MII_TG3_AUX_STAT_1000HALF
:
2766 *speed
= SPEED_1000
;
2767 *duplex
= DUPLEX_HALF
;
2770 case MII_TG3_AUX_STAT_1000FULL
:
2771 *speed
= SPEED_1000
;
2772 *duplex
= DUPLEX_FULL
;
2776 if (tp
->phy_flags
& TG3_PHYFLG_IS_FET
) {
2777 *speed
= (val
& MII_TG3_AUX_STAT_100
) ? SPEED_100
:
2779 *duplex
= (val
& MII_TG3_AUX_STAT_FULL
) ? DUPLEX_FULL
:
2783 *speed
= SPEED_INVALID
;
2784 *duplex
= DUPLEX_INVALID
;
2789 static void tg3_phy_copper_begin(struct tg3
*tp
)
2794 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
) {
2795 /* Entering low power mode. Disable gigabit and
2796 * 100baseT advertisements.
2798 tg3_writephy(tp
, MII_TG3_CTRL
, 0);
2800 new_adv
= (ADVERTISE_10HALF
| ADVERTISE_10FULL
|
2801 ADVERTISE_CSMA
| ADVERTISE_PAUSE_CAP
);
2802 if (tp
->tg3_flags
& TG3_FLAG_WOL_SPEED_100MB
)
2803 new_adv
|= (ADVERTISE_100HALF
| ADVERTISE_100FULL
);
2805 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
2806 } else if (tp
->link_config
.speed
== SPEED_INVALID
) {
2807 if (tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
)
2808 tp
->link_config
.advertising
&=
2809 ~(ADVERTISED_1000baseT_Half
|
2810 ADVERTISED_1000baseT_Full
);
2812 new_adv
= ADVERTISE_CSMA
;
2813 if (tp
->link_config
.advertising
& ADVERTISED_10baseT_Half
)
2814 new_adv
|= ADVERTISE_10HALF
;
2815 if (tp
->link_config
.advertising
& ADVERTISED_10baseT_Full
)
2816 new_adv
|= ADVERTISE_10FULL
;
2817 if (tp
->link_config
.advertising
& ADVERTISED_100baseT_Half
)
2818 new_adv
|= ADVERTISE_100HALF
;
2819 if (tp
->link_config
.advertising
& ADVERTISED_100baseT_Full
)
2820 new_adv
|= ADVERTISE_100FULL
;
2822 new_adv
|= tg3_advert_flowctrl_1000T(tp
->link_config
.flowctrl
);
2824 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
2826 if (tp
->link_config
.advertising
&
2827 (ADVERTISED_1000baseT_Half
| ADVERTISED_1000baseT_Full
)) {
2829 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Half
)
2830 new_adv
|= MII_TG3_CTRL_ADV_1000_HALF
;
2831 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Full
)
2832 new_adv
|= MII_TG3_CTRL_ADV_1000_FULL
;
2833 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
) &&
2834 (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
2835 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
))
2836 new_adv
|= (MII_TG3_CTRL_AS_MASTER
|
2837 MII_TG3_CTRL_ENABLE_AS_MASTER
);
2838 tg3_writephy(tp
, MII_TG3_CTRL
, new_adv
);
2840 tg3_writephy(tp
, MII_TG3_CTRL
, 0);
2843 new_adv
= tg3_advert_flowctrl_1000T(tp
->link_config
.flowctrl
);
2844 new_adv
|= ADVERTISE_CSMA
;
2846 /* Asking for a specific link mode. */
2847 if (tp
->link_config
.speed
== SPEED_1000
) {
2848 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
2850 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
2851 new_adv
= MII_TG3_CTRL_ADV_1000_FULL
;
2853 new_adv
= MII_TG3_CTRL_ADV_1000_HALF
;
2854 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
2855 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
)
2856 new_adv
|= (MII_TG3_CTRL_AS_MASTER
|
2857 MII_TG3_CTRL_ENABLE_AS_MASTER
);
2859 if (tp
->link_config
.speed
== SPEED_100
) {
2860 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
2861 new_adv
|= ADVERTISE_100FULL
;
2863 new_adv
|= ADVERTISE_100HALF
;
2865 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
2866 new_adv
|= ADVERTISE_10FULL
;
2868 new_adv
|= ADVERTISE_10HALF
;
2870 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
2875 tg3_writephy(tp
, MII_TG3_CTRL
, new_adv
);
2878 if (tp
->link_config
.autoneg
== AUTONEG_DISABLE
&&
2879 tp
->link_config
.speed
!= SPEED_INVALID
) {
2880 u32 bmcr
, orig_bmcr
;
2882 tp
->link_config
.active_speed
= tp
->link_config
.speed
;
2883 tp
->link_config
.active_duplex
= tp
->link_config
.duplex
;
2886 switch (tp
->link_config
.speed
) {
2892 bmcr
|= BMCR_SPEED100
;
2896 bmcr
|= TG3_BMCR_SPEED1000
;
2900 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
2901 bmcr
|= BMCR_FULLDPLX
;
2903 if (!tg3_readphy(tp
, MII_BMCR
, &orig_bmcr
) &&
2904 (bmcr
!= orig_bmcr
)) {
2905 tg3_writephy(tp
, MII_BMCR
, BMCR_LOOPBACK
);
2906 for (i
= 0; i
< 1500; i
++) {
2910 if (tg3_readphy(tp
, MII_BMSR
, &tmp
) ||
2911 tg3_readphy(tp
, MII_BMSR
, &tmp
))
2913 if (!(tmp
& BMSR_LSTATUS
)) {
2918 tg3_writephy(tp
, MII_BMCR
, bmcr
);
2922 tg3_writephy(tp
, MII_BMCR
,
2923 BMCR_ANENABLE
| BMCR_ANRESTART
);
2927 static int tg3_init_5401phy_dsp(struct tg3
*tp
)
2931 /* Turn off tap power management. */
2932 /* Set Extended packet length bit */
2933 err
= tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4c20);
2935 err
|= tg3_phydsp_write(tp
, 0x0012, 0x1804);
2936 err
|= tg3_phydsp_write(tp
, 0x0013, 0x1204);
2937 err
|= tg3_phydsp_write(tp
, 0x8006, 0x0132);
2938 err
|= tg3_phydsp_write(tp
, 0x8006, 0x0232);
2939 err
|= tg3_phydsp_write(tp
, 0x201f, 0x0a20);
2946 static int tg3_copper_is_advertising_all(struct tg3
*tp
, u32 mask
)
2948 u32 adv_reg
, all_mask
= 0;
2950 if (mask
& ADVERTISED_10baseT_Half
)
2951 all_mask
|= ADVERTISE_10HALF
;
2952 if (mask
& ADVERTISED_10baseT_Full
)
2953 all_mask
|= ADVERTISE_10FULL
;
2954 if (mask
& ADVERTISED_100baseT_Half
)
2955 all_mask
|= ADVERTISE_100HALF
;
2956 if (mask
& ADVERTISED_100baseT_Full
)
2957 all_mask
|= ADVERTISE_100FULL
;
2959 if (tg3_readphy(tp
, MII_ADVERTISE
, &adv_reg
))
2962 if ((adv_reg
& all_mask
) != all_mask
)
2964 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
)) {
2968 if (mask
& ADVERTISED_1000baseT_Half
)
2969 all_mask
|= ADVERTISE_1000HALF
;
2970 if (mask
& ADVERTISED_1000baseT_Full
)
2971 all_mask
|= ADVERTISE_1000FULL
;
2973 if (tg3_readphy(tp
, MII_TG3_CTRL
, &tg3_ctrl
))
2976 if ((tg3_ctrl
& all_mask
) != all_mask
)
2982 static int tg3_adv_1000T_flowctrl_ok(struct tg3
*tp
, u32
*lcladv
, u32
*rmtadv
)
2986 if (tg3_readphy(tp
, MII_ADVERTISE
, lcladv
))
2989 curadv
= *lcladv
& (ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
2990 reqadv
= tg3_advert_flowctrl_1000T(tp
->link_config
.flowctrl
);
2992 if (tp
->link_config
.active_duplex
== DUPLEX_FULL
) {
2993 if (curadv
!= reqadv
)
2996 if (tp
->tg3_flags
& TG3_FLAG_PAUSE_AUTONEG
)
2997 tg3_readphy(tp
, MII_LPA
, rmtadv
);
2999 /* Reprogram the advertisement register, even if it
3000 * does not affect the current link. If the link
3001 * gets renegotiated in the future, we can save an
3002 * additional renegotiation cycle by advertising
3003 * it correctly in the first place.
3005 if (curadv
!= reqadv
) {
3006 *lcladv
&= ~(ADVERTISE_PAUSE_CAP
|
3007 ADVERTISE_PAUSE_ASYM
);
3008 tg3_writephy(tp
, MII_ADVERTISE
, *lcladv
| reqadv
);
3015 static int tg3_setup_copper_phy(struct tg3
*tp
, int force_reset
)
3017 int current_link_up
;
3019 u32 lcl_adv
, rmt_adv
;
3027 (MAC_STATUS_SYNC_CHANGED
|
3028 MAC_STATUS_CFG_CHANGED
|
3029 MAC_STATUS_MI_COMPLETION
|
3030 MAC_STATUS_LNKSTATE_CHANGED
));
3033 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
3035 (tp
->mi_mode
& ~MAC_MI_MODE_AUTO_POLL
));
3039 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x02);
3041 /* Some third-party PHYs need to be reset on link going
3044 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
3045 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
3046 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) &&
3047 netif_carrier_ok(tp
->dev
)) {
3048 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3049 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
3050 !(bmsr
& BMSR_LSTATUS
))
3056 if ((tp
->phy_id
& TG3_PHY_ID_MASK
) == TG3_PHY_ID_BCM5401
) {
3057 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3058 if (tg3_readphy(tp
, MII_BMSR
, &bmsr
) ||
3059 !(tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
))
3062 if (!(bmsr
& BMSR_LSTATUS
)) {
3063 err
= tg3_init_5401phy_dsp(tp
);
3067 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3068 for (i
= 0; i
< 1000; i
++) {
3070 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
3071 (bmsr
& BMSR_LSTATUS
)) {
3077 if ((tp
->phy_id
& TG3_PHY_ID_REV_MASK
) ==
3078 TG3_PHY_REV_BCM5401_B0
&&
3079 !(bmsr
& BMSR_LSTATUS
) &&
3080 tp
->link_config
.active_speed
== SPEED_1000
) {
3081 err
= tg3_phy_reset(tp
);
3083 err
= tg3_init_5401phy_dsp(tp
);
3088 } else if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
3089 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
) {
3090 /* 5701 {A0,B0} CRC bug workaround */
3091 tg3_writephy(tp
, 0x15, 0x0a75);
3092 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, 0x8c68);
3093 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, 0x8d68);
3094 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, 0x8c68);
3097 /* Clear pending interrupts... */
3098 tg3_readphy(tp
, MII_TG3_ISTAT
, &val
);
3099 tg3_readphy(tp
, MII_TG3_ISTAT
, &val
);
3101 if (tp
->phy_flags
& TG3_PHYFLG_USE_MI_INTERRUPT
)
3102 tg3_writephy(tp
, MII_TG3_IMASK
, ~MII_TG3_INT_LINKCHG
);
3103 else if (!(tp
->phy_flags
& TG3_PHYFLG_IS_FET
))
3104 tg3_writephy(tp
, MII_TG3_IMASK
, ~0);
3106 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
3107 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
3108 if (tp
->led_ctrl
== LED_CTRL_MODE_PHY_1
)
3109 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
3110 MII_TG3_EXT_CTRL_LNK3_LED_MODE
);
3112 tg3_writephy(tp
, MII_TG3_EXT_CTRL
, 0);
3115 current_link_up
= 0;
3116 current_speed
= SPEED_INVALID
;
3117 current_duplex
= DUPLEX_INVALID
;
3119 if (tp
->phy_flags
& TG3_PHYFLG_CAPACITIVE_COUPLING
) {
3120 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4007);
3121 tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &val
);
3122 if (!(val
& (1 << 10))) {
3124 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, val
);
3130 for (i
= 0; i
< 100; i
++) {
3131 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3132 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
3133 (bmsr
& BMSR_LSTATUS
))
3138 if (bmsr
& BMSR_LSTATUS
) {
3141 tg3_readphy(tp
, MII_TG3_AUX_STAT
, &aux_stat
);
3142 for (i
= 0; i
< 2000; i
++) {
3144 if (!tg3_readphy(tp
, MII_TG3_AUX_STAT
, &aux_stat
) &&
3149 tg3_aux_stat_to_speed_duplex(tp
, aux_stat
,
3154 for (i
= 0; i
< 200; i
++) {
3155 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
3156 if (tg3_readphy(tp
, MII_BMCR
, &bmcr
))
3158 if (bmcr
&& bmcr
!= 0x7fff)
3166 tp
->link_config
.active_speed
= current_speed
;
3167 tp
->link_config
.active_duplex
= current_duplex
;
3169 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) {
3170 if ((bmcr
& BMCR_ANENABLE
) &&
3171 tg3_copper_is_advertising_all(tp
,
3172 tp
->link_config
.advertising
)) {
3173 if (tg3_adv_1000T_flowctrl_ok(tp
, &lcl_adv
,
3175 current_link_up
= 1;
3178 if (!(bmcr
& BMCR_ANENABLE
) &&
3179 tp
->link_config
.speed
== current_speed
&&
3180 tp
->link_config
.duplex
== current_duplex
&&
3181 tp
->link_config
.flowctrl
==
3182 tp
->link_config
.active_flowctrl
) {
3183 current_link_up
= 1;
3187 if (current_link_up
== 1 &&
3188 tp
->link_config
.active_duplex
== DUPLEX_FULL
)
3189 tg3_setup_flow_control(tp
, lcl_adv
, rmt_adv
);
3193 if (current_link_up
== 0 || (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)) {
3194 tg3_phy_copper_begin(tp
);
3196 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3197 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
3198 (bmsr
& BMSR_LSTATUS
))
3199 current_link_up
= 1;
3202 tp
->mac_mode
&= ~MAC_MODE_PORT_MODE_MASK
;
3203 if (current_link_up
== 1) {
3204 if (tp
->link_config
.active_speed
== SPEED_100
||
3205 tp
->link_config
.active_speed
== SPEED_10
)
3206 tp
->mac_mode
|= MAC_MODE_PORT_MODE_MII
;
3208 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
3209 } else if (tp
->phy_flags
& TG3_PHYFLG_IS_FET
)
3210 tp
->mac_mode
|= MAC_MODE_PORT_MODE_MII
;
3212 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
3214 tp
->mac_mode
&= ~MAC_MODE_HALF_DUPLEX
;
3215 if (tp
->link_config
.active_duplex
== DUPLEX_HALF
)
3216 tp
->mac_mode
|= MAC_MODE_HALF_DUPLEX
;
3218 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) {
3219 if (current_link_up
== 1 &&
3220 tg3_5700_link_polarity(tp
, tp
->link_config
.active_speed
))
3221 tp
->mac_mode
|= MAC_MODE_LINK_POLARITY
;
3223 tp
->mac_mode
&= ~MAC_MODE_LINK_POLARITY
;
3226 /* ??? Without this setting Netgear GA302T PHY does not
3227 * ??? send/receive packets...
3229 if ((tp
->phy_id
& TG3_PHY_ID_MASK
) == TG3_PHY_ID_BCM5411
&&
3230 tp
->pci_chip_rev_id
== CHIPREV_ID_5700_ALTIMA
) {
3231 tp
->mi_mode
|= MAC_MI_MODE_AUTO_POLL
;
3232 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
3236 tw32_f(MAC_MODE
, tp
->mac_mode
);
3239 if (tp
->tg3_flags
& TG3_FLAG_USE_LINKCHG_REG
) {
3240 /* Polled via timer. */
3241 tw32_f(MAC_EVENT
, 0);
3243 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
3247 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
&&
3248 current_link_up
== 1 &&
3249 tp
->link_config
.active_speed
== SPEED_1000
&&
3250 ((tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) ||
3251 (tp
->tg3_flags
& TG3_FLAG_PCI_HIGH_SPEED
))) {
3254 (MAC_STATUS_SYNC_CHANGED
|
3255 MAC_STATUS_CFG_CHANGED
));
3258 NIC_SRAM_FIRMWARE_MBOX
,
3259 NIC_SRAM_FIRMWARE_MBOX_MAGIC2
);
3262 /* Prevent send BD corruption. */
3263 if (tp
->tg3_flags3
& TG3_FLG3_CLKREQ_BUG
) {
3264 u16 oldlnkctl
, newlnkctl
;
3266 pci_read_config_word(tp
->pdev
,
3267 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
3269 if (tp
->link_config
.active_speed
== SPEED_100
||
3270 tp
->link_config
.active_speed
== SPEED_10
)
3271 newlnkctl
= oldlnkctl
& ~PCI_EXP_LNKCTL_CLKREQ_EN
;
3273 newlnkctl
= oldlnkctl
| PCI_EXP_LNKCTL_CLKREQ_EN
;
3274 if (newlnkctl
!= oldlnkctl
)
3275 pci_write_config_word(tp
->pdev
,
3276 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
3280 if (current_link_up
!= netif_carrier_ok(tp
->dev
)) {
3281 if (current_link_up
)
3282 netif_carrier_on(tp
->dev
);
3284 netif_carrier_off(tp
->dev
);
3285 tg3_link_report(tp
);
3291 struct tg3_fiber_aneginfo
{
3293 #define ANEG_STATE_UNKNOWN 0
3294 #define ANEG_STATE_AN_ENABLE 1
3295 #define ANEG_STATE_RESTART_INIT 2
3296 #define ANEG_STATE_RESTART 3
3297 #define ANEG_STATE_DISABLE_LINK_OK 4
3298 #define ANEG_STATE_ABILITY_DETECT_INIT 5
3299 #define ANEG_STATE_ABILITY_DETECT 6
3300 #define ANEG_STATE_ACK_DETECT_INIT 7
3301 #define ANEG_STATE_ACK_DETECT 8
3302 #define ANEG_STATE_COMPLETE_ACK_INIT 9
3303 #define ANEG_STATE_COMPLETE_ACK 10
3304 #define ANEG_STATE_IDLE_DETECT_INIT 11
3305 #define ANEG_STATE_IDLE_DETECT 12
3306 #define ANEG_STATE_LINK_OK 13
3307 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3308 #define ANEG_STATE_NEXT_PAGE_WAIT 15
3311 #define MR_AN_ENABLE 0x00000001
3312 #define MR_RESTART_AN 0x00000002
3313 #define MR_AN_COMPLETE 0x00000004
3314 #define MR_PAGE_RX 0x00000008
3315 #define MR_NP_LOADED 0x00000010
3316 #define MR_TOGGLE_TX 0x00000020
3317 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
3318 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
3319 #define MR_LP_ADV_SYM_PAUSE 0x00000100
3320 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
3321 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3322 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3323 #define MR_LP_ADV_NEXT_PAGE 0x00001000
3324 #define MR_TOGGLE_RX 0x00002000
3325 #define MR_NP_RX 0x00004000
3327 #define MR_LINK_OK 0x80000000
3329 unsigned long link_time
, cur_time
;
3331 u32 ability_match_cfg
;
3332 int ability_match_count
;
3334 char ability_match
, idle_match
, ack_match
;
3336 u32 txconfig
, rxconfig
;
3337 #define ANEG_CFG_NP 0x00000080
3338 #define ANEG_CFG_ACK 0x00000040
3339 #define ANEG_CFG_RF2 0x00000020
3340 #define ANEG_CFG_RF1 0x00000010
3341 #define ANEG_CFG_PS2 0x00000001
3342 #define ANEG_CFG_PS1 0x00008000
3343 #define ANEG_CFG_HD 0x00004000
3344 #define ANEG_CFG_FD 0x00002000
3345 #define ANEG_CFG_INVAL 0x00001f06
3350 #define ANEG_TIMER_ENAB 2
3351 #define ANEG_FAILED -1
3353 #define ANEG_STATE_SETTLE_TIME 10000
3355 static int tg3_fiber_aneg_smachine(struct tg3
*tp
,
3356 struct tg3_fiber_aneginfo
*ap
)
3359 unsigned long delta
;
3363 if (ap
->state
== ANEG_STATE_UNKNOWN
) {
3367 ap
->ability_match_cfg
= 0;
3368 ap
->ability_match_count
= 0;
3369 ap
->ability_match
= 0;
3375 if (tr32(MAC_STATUS
) & MAC_STATUS_RCVD_CFG
) {
3376 rx_cfg_reg
= tr32(MAC_RX_AUTO_NEG
);
3378 if (rx_cfg_reg
!= ap
->ability_match_cfg
) {
3379 ap
->ability_match_cfg
= rx_cfg_reg
;
3380 ap
->ability_match
= 0;
3381 ap
->ability_match_count
= 0;
3383 if (++ap
->ability_match_count
> 1) {
3384 ap
->ability_match
= 1;
3385 ap
->ability_match_cfg
= rx_cfg_reg
;
3388 if (rx_cfg_reg
& ANEG_CFG_ACK
)
3396 ap
->ability_match_cfg
= 0;
3397 ap
->ability_match_count
= 0;
3398 ap
->ability_match
= 0;
3404 ap
->rxconfig
= rx_cfg_reg
;
3407 switch (ap
->state
) {
3408 case ANEG_STATE_UNKNOWN
:
3409 if (ap
->flags
& (MR_AN_ENABLE
| MR_RESTART_AN
))
3410 ap
->state
= ANEG_STATE_AN_ENABLE
;
3413 case ANEG_STATE_AN_ENABLE
:
3414 ap
->flags
&= ~(MR_AN_COMPLETE
| MR_PAGE_RX
);
3415 if (ap
->flags
& MR_AN_ENABLE
) {
3418 ap
->ability_match_cfg
= 0;
3419 ap
->ability_match_count
= 0;
3420 ap
->ability_match
= 0;
3424 ap
->state
= ANEG_STATE_RESTART_INIT
;
3426 ap
->state
= ANEG_STATE_DISABLE_LINK_OK
;
3430 case ANEG_STATE_RESTART_INIT
:
3431 ap
->link_time
= ap
->cur_time
;
3432 ap
->flags
&= ~(MR_NP_LOADED
);
3434 tw32(MAC_TX_AUTO_NEG
, 0);
3435 tp
->mac_mode
|= MAC_MODE_SEND_CONFIGS
;
3436 tw32_f(MAC_MODE
, tp
->mac_mode
);
3439 ret
= ANEG_TIMER_ENAB
;
3440 ap
->state
= ANEG_STATE_RESTART
;
3443 case ANEG_STATE_RESTART
:
3444 delta
= ap
->cur_time
- ap
->link_time
;
3445 if (delta
> ANEG_STATE_SETTLE_TIME
)
3446 ap
->state
= ANEG_STATE_ABILITY_DETECT_INIT
;
3448 ret
= ANEG_TIMER_ENAB
;
3451 case ANEG_STATE_DISABLE_LINK_OK
:
3455 case ANEG_STATE_ABILITY_DETECT_INIT
:
3456 ap
->flags
&= ~(MR_TOGGLE_TX
);
3457 ap
->txconfig
= ANEG_CFG_FD
;
3458 flowctrl
= tg3_advert_flowctrl_1000X(tp
->link_config
.flowctrl
);
3459 if (flowctrl
& ADVERTISE_1000XPAUSE
)
3460 ap
->txconfig
|= ANEG_CFG_PS1
;
3461 if (flowctrl
& ADVERTISE_1000XPSE_ASYM
)
3462 ap
->txconfig
|= ANEG_CFG_PS2
;
3463 tw32(MAC_TX_AUTO_NEG
, ap
->txconfig
);
3464 tp
->mac_mode
|= MAC_MODE_SEND_CONFIGS
;
3465 tw32_f(MAC_MODE
, tp
->mac_mode
);
3468 ap
->state
= ANEG_STATE_ABILITY_DETECT
;
3471 case ANEG_STATE_ABILITY_DETECT
:
3472 if (ap
->ability_match
!= 0 && ap
->rxconfig
!= 0)
3473 ap
->state
= ANEG_STATE_ACK_DETECT_INIT
;
3476 case ANEG_STATE_ACK_DETECT_INIT
:
3477 ap
->txconfig
|= ANEG_CFG_ACK
;
3478 tw32(MAC_TX_AUTO_NEG
, ap
->txconfig
);
3479 tp
->mac_mode
|= MAC_MODE_SEND_CONFIGS
;
3480 tw32_f(MAC_MODE
, tp
->mac_mode
);
3483 ap
->state
= ANEG_STATE_ACK_DETECT
;
3486 case ANEG_STATE_ACK_DETECT
:
3487 if (ap
->ack_match
!= 0) {
3488 if ((ap
->rxconfig
& ~ANEG_CFG_ACK
) ==
3489 (ap
->ability_match_cfg
& ~ANEG_CFG_ACK
)) {
3490 ap
->state
= ANEG_STATE_COMPLETE_ACK_INIT
;
3492 ap
->state
= ANEG_STATE_AN_ENABLE
;
3494 } else if (ap
->ability_match
!= 0 &&
3495 ap
->rxconfig
== 0) {
3496 ap
->state
= ANEG_STATE_AN_ENABLE
;
3500 case ANEG_STATE_COMPLETE_ACK_INIT
:
3501 if (ap
->rxconfig
& ANEG_CFG_INVAL
) {
3505 ap
->flags
&= ~(MR_LP_ADV_FULL_DUPLEX
|
3506 MR_LP_ADV_HALF_DUPLEX
|
3507 MR_LP_ADV_SYM_PAUSE
|
3508 MR_LP_ADV_ASYM_PAUSE
|
3509 MR_LP_ADV_REMOTE_FAULT1
|
3510 MR_LP_ADV_REMOTE_FAULT2
|
3511 MR_LP_ADV_NEXT_PAGE
|
3514 if (ap
->rxconfig
& ANEG_CFG_FD
)
3515 ap
->flags
|= MR_LP_ADV_FULL_DUPLEX
;
3516 if (ap
->rxconfig
& ANEG_CFG_HD
)
3517 ap
->flags
|= MR_LP_ADV_HALF_DUPLEX
;
3518 if (ap
->rxconfig
& ANEG_CFG_PS1
)
3519 ap
->flags
|= MR_LP_ADV_SYM_PAUSE
;
3520 if (ap
->rxconfig
& ANEG_CFG_PS2
)
3521 ap
->flags
|= MR_LP_ADV_ASYM_PAUSE
;
3522 if (ap
->rxconfig
& ANEG_CFG_RF1
)
3523 ap
->flags
|= MR_LP_ADV_REMOTE_FAULT1
;
3524 if (ap
->rxconfig
& ANEG_CFG_RF2
)
3525 ap
->flags
|= MR_LP_ADV_REMOTE_FAULT2
;
3526 if (ap
->rxconfig
& ANEG_CFG_NP
)
3527 ap
->flags
|= MR_LP_ADV_NEXT_PAGE
;
3529 ap
->link_time
= ap
->cur_time
;
3531 ap
->flags
^= (MR_TOGGLE_TX
);
3532 if (ap
->rxconfig
& 0x0008)
3533 ap
->flags
|= MR_TOGGLE_RX
;
3534 if (ap
->rxconfig
& ANEG_CFG_NP
)
3535 ap
->flags
|= MR_NP_RX
;
3536 ap
->flags
|= MR_PAGE_RX
;
3538 ap
->state
= ANEG_STATE_COMPLETE_ACK
;
3539 ret
= ANEG_TIMER_ENAB
;
3542 case ANEG_STATE_COMPLETE_ACK
:
3543 if (ap
->ability_match
!= 0 &&
3544 ap
->rxconfig
== 0) {
3545 ap
->state
= ANEG_STATE_AN_ENABLE
;
3548 delta
= ap
->cur_time
- ap
->link_time
;
3549 if (delta
> ANEG_STATE_SETTLE_TIME
) {
3550 if (!(ap
->flags
& (MR_LP_ADV_NEXT_PAGE
))) {
3551 ap
->state
= ANEG_STATE_IDLE_DETECT_INIT
;
3553 if ((ap
->txconfig
& ANEG_CFG_NP
) == 0 &&
3554 !(ap
->flags
& MR_NP_RX
)) {
3555 ap
->state
= ANEG_STATE_IDLE_DETECT_INIT
;
3563 case ANEG_STATE_IDLE_DETECT_INIT
:
3564 ap
->link_time
= ap
->cur_time
;
3565 tp
->mac_mode
&= ~MAC_MODE_SEND_CONFIGS
;
3566 tw32_f(MAC_MODE
, tp
->mac_mode
);
3569 ap
->state
= ANEG_STATE_IDLE_DETECT
;
3570 ret
= ANEG_TIMER_ENAB
;
3573 case ANEG_STATE_IDLE_DETECT
:
3574 if (ap
->ability_match
!= 0 &&
3575 ap
->rxconfig
== 0) {
3576 ap
->state
= ANEG_STATE_AN_ENABLE
;
3579 delta
= ap
->cur_time
- ap
->link_time
;
3580 if (delta
> ANEG_STATE_SETTLE_TIME
) {
3581 /* XXX another gem from the Broadcom driver :( */
3582 ap
->state
= ANEG_STATE_LINK_OK
;
3586 case ANEG_STATE_LINK_OK
:
3587 ap
->flags
|= (MR_AN_COMPLETE
| MR_LINK_OK
);
3591 case ANEG_STATE_NEXT_PAGE_WAIT_INIT
:
3592 /* ??? unimplemented */
3595 case ANEG_STATE_NEXT_PAGE_WAIT
:
3596 /* ??? unimplemented */
3607 static int fiber_autoneg(struct tg3
*tp
, u32
*txflags
, u32
*rxflags
)
3610 struct tg3_fiber_aneginfo aninfo
;
3611 int status
= ANEG_FAILED
;
3615 tw32_f(MAC_TX_AUTO_NEG
, 0);
3617 tmp
= tp
->mac_mode
& ~MAC_MODE_PORT_MODE_MASK
;
3618 tw32_f(MAC_MODE
, tmp
| MAC_MODE_PORT_MODE_GMII
);
3621 tw32_f(MAC_MODE
, tp
->mac_mode
| MAC_MODE_SEND_CONFIGS
);
3624 memset(&aninfo
, 0, sizeof(aninfo
));
3625 aninfo
.flags
|= MR_AN_ENABLE
;
3626 aninfo
.state
= ANEG_STATE_UNKNOWN
;
3627 aninfo
.cur_time
= 0;
3629 while (++tick
< 195000) {
3630 status
= tg3_fiber_aneg_smachine(tp
, &aninfo
);
3631 if (status
== ANEG_DONE
|| status
== ANEG_FAILED
)
3637 tp
->mac_mode
&= ~MAC_MODE_SEND_CONFIGS
;
3638 tw32_f(MAC_MODE
, tp
->mac_mode
);
3641 *txflags
= aninfo
.txconfig
;
3642 *rxflags
= aninfo
.flags
;
3644 if (status
== ANEG_DONE
&&
3645 (aninfo
.flags
& (MR_AN_COMPLETE
| MR_LINK_OK
|
3646 MR_LP_ADV_FULL_DUPLEX
)))
3652 static void tg3_init_bcm8002(struct tg3
*tp
)
3654 u32 mac_status
= tr32(MAC_STATUS
);
3657 /* Reset when initting first time or we have a link. */
3658 if ((tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
) &&
3659 !(mac_status
& MAC_STATUS_PCS_SYNCED
))
3662 /* Set PLL lock range. */
3663 tg3_writephy(tp
, 0x16, 0x8007);
3666 tg3_writephy(tp
, MII_BMCR
, BMCR_RESET
);
3668 /* Wait for reset to complete. */
3669 /* XXX schedule_timeout() ... */
3670 for (i
= 0; i
< 500; i
++)
3673 /* Config mode; select PMA/Ch 1 regs. */
3674 tg3_writephy(tp
, 0x10, 0x8411);
3676 /* Enable auto-lock and comdet, select txclk for tx. */
3677 tg3_writephy(tp
, 0x11, 0x0a10);
3679 tg3_writephy(tp
, 0x18, 0x00a0);
3680 tg3_writephy(tp
, 0x16, 0x41ff);
3682 /* Assert and deassert POR. */
3683 tg3_writephy(tp
, 0x13, 0x0400);
3685 tg3_writephy(tp
, 0x13, 0x0000);
3687 tg3_writephy(tp
, 0x11, 0x0a50);
3689 tg3_writephy(tp
, 0x11, 0x0a10);
3691 /* Wait for signal to stabilize */
3692 /* XXX schedule_timeout() ... */
3693 for (i
= 0; i
< 15000; i
++)
3696 /* Deselect the channel register so we can read the PHYID
3699 tg3_writephy(tp
, 0x10, 0x8011);
3702 static int tg3_setup_fiber_hw_autoneg(struct tg3
*tp
, u32 mac_status
)
3705 u32 sg_dig_ctrl
, sg_dig_status
;
3706 u32 serdes_cfg
, expected_sg_dig_ctrl
;
3707 int workaround
, port_a
;
3708 int current_link_up
;
3711 expected_sg_dig_ctrl
= 0;
3714 current_link_up
= 0;
3716 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5704_A0
&&
3717 tp
->pci_chip_rev_id
!= CHIPREV_ID_5704_A1
) {
3719 if (tr32(TG3PCI_DUAL_MAC_CTRL
) & DUAL_MAC_CTRL_ID
)
3722 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3723 /* preserve bits 20-23 for voltage regulator */
3724 serdes_cfg
= tr32(MAC_SERDES_CFG
) & 0x00f06fff;
3727 sg_dig_ctrl
= tr32(SG_DIG_CTRL
);
3729 if (tp
->link_config
.autoneg
!= AUTONEG_ENABLE
) {
3730 if (sg_dig_ctrl
& SG_DIG_USING_HW_AUTONEG
) {
3732 u32 val
= serdes_cfg
;
3738 tw32_f(MAC_SERDES_CFG
, val
);
3741 tw32_f(SG_DIG_CTRL
, SG_DIG_COMMON_SETUP
);
3743 if (mac_status
& MAC_STATUS_PCS_SYNCED
) {
3744 tg3_setup_flow_control(tp
, 0, 0);
3745 current_link_up
= 1;
3750 /* Want auto-negotiation. */
3751 expected_sg_dig_ctrl
= SG_DIG_USING_HW_AUTONEG
| SG_DIG_COMMON_SETUP
;
3753 flowctrl
= tg3_advert_flowctrl_1000X(tp
->link_config
.flowctrl
);
3754 if (flowctrl
& ADVERTISE_1000XPAUSE
)
3755 expected_sg_dig_ctrl
|= SG_DIG_PAUSE_CAP
;
3756 if (flowctrl
& ADVERTISE_1000XPSE_ASYM
)
3757 expected_sg_dig_ctrl
|= SG_DIG_ASYM_PAUSE
;
3759 if (sg_dig_ctrl
!= expected_sg_dig_ctrl
) {
3760 if ((tp
->phy_flags
& TG3_PHYFLG_PARALLEL_DETECT
) &&
3761 tp
->serdes_counter
&&
3762 ((mac_status
& (MAC_STATUS_PCS_SYNCED
|
3763 MAC_STATUS_RCVD_CFG
)) ==
3764 MAC_STATUS_PCS_SYNCED
)) {
3765 tp
->serdes_counter
--;
3766 current_link_up
= 1;
3771 tw32_f(MAC_SERDES_CFG
, serdes_cfg
| 0xc011000);
3772 tw32_f(SG_DIG_CTRL
, expected_sg_dig_ctrl
| SG_DIG_SOFT_RESET
);
3774 tw32_f(SG_DIG_CTRL
, expected_sg_dig_ctrl
);
3776 tp
->serdes_counter
= SERDES_AN_TIMEOUT_5704S
;
3777 tp
->phy_flags
&= ~TG3_PHYFLG_PARALLEL_DETECT
;
3778 } else if (mac_status
& (MAC_STATUS_PCS_SYNCED
|
3779 MAC_STATUS_SIGNAL_DET
)) {
3780 sg_dig_status
= tr32(SG_DIG_STATUS
);
3781 mac_status
= tr32(MAC_STATUS
);
3783 if ((sg_dig_status
& SG_DIG_AUTONEG_COMPLETE
) &&
3784 (mac_status
& MAC_STATUS_PCS_SYNCED
)) {
3785 u32 local_adv
= 0, remote_adv
= 0;
3787 if (sg_dig_ctrl
& SG_DIG_PAUSE_CAP
)
3788 local_adv
|= ADVERTISE_1000XPAUSE
;
3789 if (sg_dig_ctrl
& SG_DIG_ASYM_PAUSE
)
3790 local_adv
|= ADVERTISE_1000XPSE_ASYM
;
3792 if (sg_dig_status
& SG_DIG_PARTNER_PAUSE_CAPABLE
)
3793 remote_adv
|= LPA_1000XPAUSE
;
3794 if (sg_dig_status
& SG_DIG_PARTNER_ASYM_PAUSE
)
3795 remote_adv
|= LPA_1000XPAUSE_ASYM
;
3797 tg3_setup_flow_control(tp
, local_adv
, remote_adv
);
3798 current_link_up
= 1;
3799 tp
->serdes_counter
= 0;
3800 tp
->phy_flags
&= ~TG3_PHYFLG_PARALLEL_DETECT
;
3801 } else if (!(sg_dig_status
& SG_DIG_AUTONEG_COMPLETE
)) {
3802 if (tp
->serdes_counter
)
3803 tp
->serdes_counter
--;
3806 u32 val
= serdes_cfg
;
3813 tw32_f(MAC_SERDES_CFG
, val
);
3816 tw32_f(SG_DIG_CTRL
, SG_DIG_COMMON_SETUP
);
3819 /* Link parallel detection - link is up */
3820 /* only if we have PCS_SYNC and not */
3821 /* receiving config code words */
3822 mac_status
= tr32(MAC_STATUS
);
3823 if ((mac_status
& MAC_STATUS_PCS_SYNCED
) &&
3824 !(mac_status
& MAC_STATUS_RCVD_CFG
)) {
3825 tg3_setup_flow_control(tp
, 0, 0);
3826 current_link_up
= 1;
3828 TG3_PHYFLG_PARALLEL_DETECT
;
3829 tp
->serdes_counter
=
3830 SERDES_PARALLEL_DET_TIMEOUT
;
3832 goto restart_autoneg
;
3836 tp
->serdes_counter
= SERDES_AN_TIMEOUT_5704S
;
3837 tp
->phy_flags
&= ~TG3_PHYFLG_PARALLEL_DETECT
;
3841 return current_link_up
;
3844 static int tg3_setup_fiber_by_hand(struct tg3
*tp
, u32 mac_status
)
3846 int current_link_up
= 0;
3848 if (!(mac_status
& MAC_STATUS_PCS_SYNCED
))
3851 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) {
3852 u32 txflags
, rxflags
;
3855 if (fiber_autoneg(tp
, &txflags
, &rxflags
)) {
3856 u32 local_adv
= 0, remote_adv
= 0;
3858 if (txflags
& ANEG_CFG_PS1
)
3859 local_adv
|= ADVERTISE_1000XPAUSE
;
3860 if (txflags
& ANEG_CFG_PS2
)
3861 local_adv
|= ADVERTISE_1000XPSE_ASYM
;
3863 if (rxflags
& MR_LP_ADV_SYM_PAUSE
)
3864 remote_adv
|= LPA_1000XPAUSE
;
3865 if (rxflags
& MR_LP_ADV_ASYM_PAUSE
)
3866 remote_adv
|= LPA_1000XPAUSE_ASYM
;
3868 tg3_setup_flow_control(tp
, local_adv
, remote_adv
);
3870 current_link_up
= 1;
3872 for (i
= 0; i
< 30; i
++) {
3875 (MAC_STATUS_SYNC_CHANGED
|
3876 MAC_STATUS_CFG_CHANGED
));
3878 if ((tr32(MAC_STATUS
) &
3879 (MAC_STATUS_SYNC_CHANGED
|
3880 MAC_STATUS_CFG_CHANGED
)) == 0)
3884 mac_status
= tr32(MAC_STATUS
);
3885 if (current_link_up
== 0 &&
3886 (mac_status
& MAC_STATUS_PCS_SYNCED
) &&
3887 !(mac_status
& MAC_STATUS_RCVD_CFG
))
3888 current_link_up
= 1;
3890 tg3_setup_flow_control(tp
, 0, 0);
3892 /* Forcing 1000FD link up. */
3893 current_link_up
= 1;
3895 tw32_f(MAC_MODE
, (tp
->mac_mode
| MAC_MODE_SEND_CONFIGS
));
3898 tw32_f(MAC_MODE
, tp
->mac_mode
);
3903 return current_link_up
;
3906 static int tg3_setup_fiber_phy(struct tg3
*tp
, int force_reset
)
3909 u16 orig_active_speed
;
3910 u8 orig_active_duplex
;
3912 int current_link_up
;
3915 orig_pause_cfg
= tp
->link_config
.active_flowctrl
;
3916 orig_active_speed
= tp
->link_config
.active_speed
;
3917 orig_active_duplex
= tp
->link_config
.active_duplex
;
3919 if (!(tp
->tg3_flags2
& TG3_FLG2_HW_AUTONEG
) &&
3920 netif_carrier_ok(tp
->dev
) &&
3921 (tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
)) {
3922 mac_status
= tr32(MAC_STATUS
);
3923 mac_status
&= (MAC_STATUS_PCS_SYNCED
|
3924 MAC_STATUS_SIGNAL_DET
|
3925 MAC_STATUS_CFG_CHANGED
|
3926 MAC_STATUS_RCVD_CFG
);
3927 if (mac_status
== (MAC_STATUS_PCS_SYNCED
|
3928 MAC_STATUS_SIGNAL_DET
)) {
3929 tw32_f(MAC_STATUS
, (MAC_STATUS_SYNC_CHANGED
|
3930 MAC_STATUS_CFG_CHANGED
));
3935 tw32_f(MAC_TX_AUTO_NEG
, 0);
3937 tp
->mac_mode
&= ~(MAC_MODE_PORT_MODE_MASK
| MAC_MODE_HALF_DUPLEX
);
3938 tp
->mac_mode
|= MAC_MODE_PORT_MODE_TBI
;
3939 tw32_f(MAC_MODE
, tp
->mac_mode
);
3942 if (tp
->phy_id
== TG3_PHY_ID_BCM8002
)
3943 tg3_init_bcm8002(tp
);
3945 /* Enable link change event even when serdes polling. */
3946 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
3949 current_link_up
= 0;
3950 mac_status
= tr32(MAC_STATUS
);
3952 if (tp
->tg3_flags2
& TG3_FLG2_HW_AUTONEG
)
3953 current_link_up
= tg3_setup_fiber_hw_autoneg(tp
, mac_status
);
3955 current_link_up
= tg3_setup_fiber_by_hand(tp
, mac_status
);
3957 tp
->napi
[0].hw_status
->status
=
3958 (SD_STATUS_UPDATED
|
3959 (tp
->napi
[0].hw_status
->status
& ~SD_STATUS_LINK_CHG
));
3961 for (i
= 0; i
< 100; i
++) {
3962 tw32_f(MAC_STATUS
, (MAC_STATUS_SYNC_CHANGED
|
3963 MAC_STATUS_CFG_CHANGED
));
3965 if ((tr32(MAC_STATUS
) & (MAC_STATUS_SYNC_CHANGED
|
3966 MAC_STATUS_CFG_CHANGED
|
3967 MAC_STATUS_LNKSTATE_CHANGED
)) == 0)
3971 mac_status
= tr32(MAC_STATUS
);
3972 if ((mac_status
& MAC_STATUS_PCS_SYNCED
) == 0) {
3973 current_link_up
= 0;
3974 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
&&
3975 tp
->serdes_counter
== 0) {
3976 tw32_f(MAC_MODE
, (tp
->mac_mode
|
3977 MAC_MODE_SEND_CONFIGS
));
3979 tw32_f(MAC_MODE
, tp
->mac_mode
);
3983 if (current_link_up
== 1) {
3984 tp
->link_config
.active_speed
= SPEED_1000
;
3985 tp
->link_config
.active_duplex
= DUPLEX_FULL
;
3986 tw32(MAC_LED_CTRL
, (tp
->led_ctrl
|
3987 LED_CTRL_LNKLED_OVERRIDE
|
3988 LED_CTRL_1000MBPS_ON
));
3990 tp
->link_config
.active_speed
= SPEED_INVALID
;
3991 tp
->link_config
.active_duplex
= DUPLEX_INVALID
;
3992 tw32(MAC_LED_CTRL
, (tp
->led_ctrl
|
3993 LED_CTRL_LNKLED_OVERRIDE
|
3994 LED_CTRL_TRAFFIC_OVERRIDE
));
3997 if (current_link_up
!= netif_carrier_ok(tp
->dev
)) {
3998 if (current_link_up
)
3999 netif_carrier_on(tp
->dev
);
4001 netif_carrier_off(tp
->dev
);
4002 tg3_link_report(tp
);
4004 u32 now_pause_cfg
= tp
->link_config
.active_flowctrl
;
4005 if (orig_pause_cfg
!= now_pause_cfg
||
4006 orig_active_speed
!= tp
->link_config
.active_speed
||
4007 orig_active_duplex
!= tp
->link_config
.active_duplex
)
4008 tg3_link_report(tp
);
4014 static int tg3_setup_fiber_mii_phy(struct tg3
*tp
, int force_reset
)
4016 int current_link_up
, err
= 0;
4020 u32 local_adv
, remote_adv
;
4022 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
4023 tw32_f(MAC_MODE
, tp
->mac_mode
);
4029 (MAC_STATUS_SYNC_CHANGED
|
4030 MAC_STATUS_CFG_CHANGED
|
4031 MAC_STATUS_MI_COMPLETION
|
4032 MAC_STATUS_LNKSTATE_CHANGED
));
4038 current_link_up
= 0;
4039 current_speed
= SPEED_INVALID
;
4040 current_duplex
= DUPLEX_INVALID
;
4042 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
4043 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
4044 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
) {
4045 if (tr32(MAC_TX_STATUS
) & TX_STATUS_LINK_UP
)
4046 bmsr
|= BMSR_LSTATUS
;
4048 bmsr
&= ~BMSR_LSTATUS
;
4051 err
|= tg3_readphy(tp
, MII_BMCR
, &bmcr
);
4053 if ((tp
->link_config
.autoneg
== AUTONEG_ENABLE
) && !force_reset
&&
4054 (tp
->phy_flags
& TG3_PHYFLG_PARALLEL_DETECT
)) {
4055 /* do nothing, just check for link up at the end */
4056 } else if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) {
4059 err
|= tg3_readphy(tp
, MII_ADVERTISE
, &adv
);
4060 new_adv
= adv
& ~(ADVERTISE_1000XFULL
| ADVERTISE_1000XHALF
|
4061 ADVERTISE_1000XPAUSE
|
4062 ADVERTISE_1000XPSE_ASYM
|
4065 new_adv
|= tg3_advert_flowctrl_1000X(tp
->link_config
.flowctrl
);
4067 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Half
)
4068 new_adv
|= ADVERTISE_1000XHALF
;
4069 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Full
)
4070 new_adv
|= ADVERTISE_1000XFULL
;
4072 if ((new_adv
!= adv
) || !(bmcr
& BMCR_ANENABLE
)) {
4073 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
4074 bmcr
|= BMCR_ANENABLE
| BMCR_ANRESTART
;
4075 tg3_writephy(tp
, MII_BMCR
, bmcr
);
4077 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
4078 tp
->serdes_counter
= SERDES_AN_TIMEOUT_5714S
;
4079 tp
->phy_flags
&= ~TG3_PHYFLG_PARALLEL_DETECT
;
4086 bmcr
&= ~BMCR_SPEED1000
;
4087 new_bmcr
= bmcr
& ~(BMCR_ANENABLE
| BMCR_FULLDPLX
);
4089 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
4090 new_bmcr
|= BMCR_FULLDPLX
;
4092 if (new_bmcr
!= bmcr
) {
4093 /* BMCR_SPEED1000 is a reserved bit that needs
4094 * to be set on write.
4096 new_bmcr
|= BMCR_SPEED1000
;
4098 /* Force a linkdown */
4099 if (netif_carrier_ok(tp
->dev
)) {
4102 err
|= tg3_readphy(tp
, MII_ADVERTISE
, &adv
);
4103 adv
&= ~(ADVERTISE_1000XFULL
|
4104 ADVERTISE_1000XHALF
|
4106 tg3_writephy(tp
, MII_ADVERTISE
, adv
);
4107 tg3_writephy(tp
, MII_BMCR
, bmcr
|
4111 netif_carrier_off(tp
->dev
);
4113 tg3_writephy(tp
, MII_BMCR
, new_bmcr
);
4115 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
4116 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
4117 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
4119 if (tr32(MAC_TX_STATUS
) & TX_STATUS_LINK_UP
)
4120 bmsr
|= BMSR_LSTATUS
;
4122 bmsr
&= ~BMSR_LSTATUS
;
4124 tp
->phy_flags
&= ~TG3_PHYFLG_PARALLEL_DETECT
;
4128 if (bmsr
& BMSR_LSTATUS
) {
4129 current_speed
= SPEED_1000
;
4130 current_link_up
= 1;
4131 if (bmcr
& BMCR_FULLDPLX
)
4132 current_duplex
= DUPLEX_FULL
;
4134 current_duplex
= DUPLEX_HALF
;
4139 if (bmcr
& BMCR_ANENABLE
) {
4142 err
|= tg3_readphy(tp
, MII_ADVERTISE
, &local_adv
);
4143 err
|= tg3_readphy(tp
, MII_LPA
, &remote_adv
);
4144 common
= local_adv
& remote_adv
;
4145 if (common
& (ADVERTISE_1000XHALF
|
4146 ADVERTISE_1000XFULL
)) {
4147 if (common
& ADVERTISE_1000XFULL
)
4148 current_duplex
= DUPLEX_FULL
;
4150 current_duplex
= DUPLEX_HALF
;
4151 } else if (!(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
4152 /* Link is up via parallel detect */
4154 current_link_up
= 0;
4159 if (current_link_up
== 1 && current_duplex
== DUPLEX_FULL
)
4160 tg3_setup_flow_control(tp
, local_adv
, remote_adv
);
4162 tp
->mac_mode
&= ~MAC_MODE_HALF_DUPLEX
;
4163 if (tp
->link_config
.active_duplex
== DUPLEX_HALF
)
4164 tp
->mac_mode
|= MAC_MODE_HALF_DUPLEX
;
4166 tw32_f(MAC_MODE
, tp
->mac_mode
);
4169 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
4171 tp
->link_config
.active_speed
= current_speed
;
4172 tp
->link_config
.active_duplex
= current_duplex
;
4174 if (current_link_up
!= netif_carrier_ok(tp
->dev
)) {
4175 if (current_link_up
)
4176 netif_carrier_on(tp
->dev
);
4178 netif_carrier_off(tp
->dev
);
4179 tp
->phy_flags
&= ~TG3_PHYFLG_PARALLEL_DETECT
;
4181 tg3_link_report(tp
);
4186 static void tg3_serdes_parallel_detect(struct tg3
*tp
)
4188 if (tp
->serdes_counter
) {
4189 /* Give autoneg time to complete. */
4190 tp
->serdes_counter
--;
4194 if (!netif_carrier_ok(tp
->dev
) &&
4195 (tp
->link_config
.autoneg
== AUTONEG_ENABLE
)) {
4198 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
4199 if (bmcr
& BMCR_ANENABLE
) {
4202 /* Select shadow register 0x1f */
4203 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, 0x7c00);
4204 tg3_readphy(tp
, MII_TG3_MISC_SHDW
, &phy1
);
4206 /* Select expansion interrupt status register */
4207 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
4208 MII_TG3_DSP_EXP1_INT_STAT
);
4209 tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &phy2
);
4210 tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &phy2
);
4212 if ((phy1
& 0x10) && !(phy2
& 0x20)) {
4213 /* We have signal detect and not receiving
4214 * config code words, link is up by parallel
4218 bmcr
&= ~BMCR_ANENABLE
;
4219 bmcr
|= BMCR_SPEED1000
| BMCR_FULLDPLX
;
4220 tg3_writephy(tp
, MII_BMCR
, bmcr
);
4221 tp
->phy_flags
|= TG3_PHYFLG_PARALLEL_DETECT
;
4224 } else if (netif_carrier_ok(tp
->dev
) &&
4225 (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) &&
4226 (tp
->phy_flags
& TG3_PHYFLG_PARALLEL_DETECT
)) {
4229 /* Select expansion interrupt status register */
4230 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
4231 MII_TG3_DSP_EXP1_INT_STAT
);
4232 tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &phy2
);
4236 /* Config code words received, turn on autoneg. */
4237 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
4238 tg3_writephy(tp
, MII_BMCR
, bmcr
| BMCR_ANENABLE
);
4240 tp
->phy_flags
&= ~TG3_PHYFLG_PARALLEL_DETECT
;
4246 static int tg3_setup_phy(struct tg3
*tp
, int force_reset
)
4250 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
)
4251 err
= tg3_setup_fiber_phy(tp
, force_reset
);
4252 else if (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
)
4253 err
= tg3_setup_fiber_mii_phy(tp
, force_reset
);
4255 err
= tg3_setup_copper_phy(tp
, force_reset
);
4257 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
) {
4260 val
= tr32(TG3_CPMU_CLCK_STAT
) & CPMU_CLCK_STAT_MAC_CLCK_MASK
;
4261 if (val
== CPMU_CLCK_STAT_MAC_CLCK_62_5
)
4263 else if (val
== CPMU_CLCK_STAT_MAC_CLCK_6_25
)
4268 val
= tr32(GRC_MISC_CFG
) & ~GRC_MISC_CFG_PRESCALAR_MASK
;
4269 val
|= (scale
<< GRC_MISC_CFG_PRESCALAR_SHIFT
);
4270 tw32(GRC_MISC_CFG
, val
);
4273 if (tp
->link_config
.active_speed
== SPEED_1000
&&
4274 tp
->link_config
.active_duplex
== DUPLEX_HALF
)
4275 tw32(MAC_TX_LENGTHS
,
4276 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
4277 (6 << TX_LENGTHS_IPG_SHIFT
) |
4278 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT
)));
4280 tw32(MAC_TX_LENGTHS
,
4281 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
4282 (6 << TX_LENGTHS_IPG_SHIFT
) |
4283 (32 << TX_LENGTHS_SLOT_TIME_SHIFT
)));
4285 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
4286 if (netif_carrier_ok(tp
->dev
)) {
4287 tw32(HOSTCC_STAT_COAL_TICKS
,
4288 tp
->coal
.stats_block_coalesce_usecs
);
4290 tw32(HOSTCC_STAT_COAL_TICKS
, 0);
4294 if (tp
->tg3_flags
& TG3_FLAG_ASPM_WORKAROUND
) {
4295 u32 val
= tr32(PCIE_PWR_MGMT_THRESH
);
4296 if (!netif_carrier_ok(tp
->dev
))
4297 val
= (val
& ~PCIE_PWR_MGMT_L1_THRESH_MSK
) |
4300 val
|= PCIE_PWR_MGMT_L1_THRESH_MSK
;
4301 tw32(PCIE_PWR_MGMT_THRESH
, val
);
4307 static inline int tg3_irq_sync(struct tg3
*tp
)
4309 return tp
->irq_sync
;
4312 /* This is called whenever we suspect that the system chipset is re-
4313 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4314 * is bogus tx completions. We try to recover by setting the
4315 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4318 static void tg3_tx_recover(struct tg3
*tp
)
4320 BUG_ON((tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
) ||
4321 tp
->write32_tx_mbox
== tg3_write_indirect_mbox
);
4323 netdev_warn(tp
->dev
,
4324 "The system may be re-ordering memory-mapped I/O "
4325 "cycles to the network device, attempting to recover. "
4326 "Please report the problem to the driver maintainer "
4327 "and include system chipset information.\n");
4329 spin_lock(&tp
->lock
);
4330 tp
->tg3_flags
|= TG3_FLAG_TX_RECOVERY_PENDING
;
4331 spin_unlock(&tp
->lock
);
4334 static inline u32
tg3_tx_avail(struct tg3_napi
*tnapi
)
4336 /* Tell compiler to fetch tx indices from memory. */
4338 return tnapi
->tx_pending
-
4339 ((tnapi
->tx_prod
- tnapi
->tx_cons
) & (TG3_TX_RING_SIZE
- 1));
4342 /* Tigon3 never reports partial packet sends. So we do not
4343 * need special logic to handle SKBs that have not had all
4344 * of their frags sent yet, like SunGEM does.
4346 static void tg3_tx(struct tg3_napi
*tnapi
)
4348 struct tg3
*tp
= tnapi
->tp
;
4349 u32 hw_idx
= tnapi
->hw_status
->idx
[0].tx_consumer
;
4350 u32 sw_idx
= tnapi
->tx_cons
;
4351 struct netdev_queue
*txq
;
4352 int index
= tnapi
- tp
->napi
;
4354 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)
4357 txq
= netdev_get_tx_queue(tp
->dev
, index
);
4359 while (sw_idx
!= hw_idx
) {
4360 struct ring_info
*ri
= &tnapi
->tx_buffers
[sw_idx
];
4361 struct sk_buff
*skb
= ri
->skb
;
4364 if (unlikely(skb
== NULL
)) {
4369 pci_unmap_single(tp
->pdev
,
4370 dma_unmap_addr(ri
, mapping
),
4376 sw_idx
= NEXT_TX(sw_idx
);
4378 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
4379 ri
= &tnapi
->tx_buffers
[sw_idx
];
4380 if (unlikely(ri
->skb
!= NULL
|| sw_idx
== hw_idx
))
4383 pci_unmap_page(tp
->pdev
,
4384 dma_unmap_addr(ri
, mapping
),
4385 skb_shinfo(skb
)->frags
[i
].size
,
4387 sw_idx
= NEXT_TX(sw_idx
);
4392 if (unlikely(tx_bug
)) {
4398 tnapi
->tx_cons
= sw_idx
;
4400 /* Need to make the tx_cons update visible to tg3_start_xmit()
4401 * before checking for netif_queue_stopped(). Without the
4402 * memory barrier, there is a small possibility that tg3_start_xmit()
4403 * will miss it and cause the queue to be stopped forever.
4407 if (unlikely(netif_tx_queue_stopped(txq
) &&
4408 (tg3_tx_avail(tnapi
) > TG3_TX_WAKEUP_THRESH(tnapi
)))) {
4409 __netif_tx_lock(txq
, smp_processor_id());
4410 if (netif_tx_queue_stopped(txq
) &&
4411 (tg3_tx_avail(tnapi
) > TG3_TX_WAKEUP_THRESH(tnapi
)))
4412 netif_tx_wake_queue(txq
);
4413 __netif_tx_unlock(txq
);
4417 static void tg3_rx_skb_free(struct tg3
*tp
, struct ring_info
*ri
, u32 map_sz
)
4422 pci_unmap_single(tp
->pdev
, dma_unmap_addr(ri
, mapping
),
4423 map_sz
, PCI_DMA_FROMDEVICE
);
4424 dev_kfree_skb_any(ri
->skb
);
4428 /* Returns size of skb allocated or < 0 on error.
4430 * We only need to fill in the address because the other members
4431 * of the RX descriptor are invariant, see tg3_init_rings.
4433 * Note the purposeful assymetry of cpu vs. chip accesses. For
4434 * posting buffers we only dirty the first cache line of the RX
4435 * descriptor (containing the address). Whereas for the RX status
4436 * buffers the cpu only reads the last cacheline of the RX descriptor
4437 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4439 static int tg3_alloc_rx_skb(struct tg3
*tp
, struct tg3_rx_prodring_set
*tpr
,
4440 u32 opaque_key
, u32 dest_idx_unmasked
)
4442 struct tg3_rx_buffer_desc
*desc
;
4443 struct ring_info
*map
, *src_map
;
4444 struct sk_buff
*skb
;
4446 int skb_size
, dest_idx
;
4449 switch (opaque_key
) {
4450 case RXD_OPAQUE_RING_STD
:
4451 dest_idx
= dest_idx_unmasked
& tp
->rx_std_ring_mask
;
4452 desc
= &tpr
->rx_std
[dest_idx
];
4453 map
= &tpr
->rx_std_buffers
[dest_idx
];
4454 skb_size
= tp
->rx_pkt_map_sz
;
4457 case RXD_OPAQUE_RING_JUMBO
:
4458 dest_idx
= dest_idx_unmasked
& tp
->rx_jmb_ring_mask
;
4459 desc
= &tpr
->rx_jmb
[dest_idx
].std
;
4460 map
= &tpr
->rx_jmb_buffers
[dest_idx
];
4461 skb_size
= TG3_RX_JMB_MAP_SZ
;
4468 /* Do not overwrite any of the map or rp information
4469 * until we are sure we can commit to a new buffer.
4471 * Callers depend upon this behavior and assume that
4472 * we leave everything unchanged if we fail.
4474 skb
= netdev_alloc_skb(tp
->dev
, skb_size
+ tp
->rx_offset
);
4478 skb_reserve(skb
, tp
->rx_offset
);
4480 mapping
= pci_map_single(tp
->pdev
, skb
->data
, skb_size
,
4481 PCI_DMA_FROMDEVICE
);
4482 if (pci_dma_mapping_error(tp
->pdev
, mapping
)) {
4488 dma_unmap_addr_set(map
, mapping
, mapping
);
4490 desc
->addr_hi
= ((u64
)mapping
>> 32);
4491 desc
->addr_lo
= ((u64
)mapping
& 0xffffffff);
4496 /* We only need to move over in the address because the other
4497 * members of the RX descriptor are invariant. See notes above
4498 * tg3_alloc_rx_skb for full details.
4500 static void tg3_recycle_rx(struct tg3_napi
*tnapi
,
4501 struct tg3_rx_prodring_set
*dpr
,
4502 u32 opaque_key
, int src_idx
,
4503 u32 dest_idx_unmasked
)
4505 struct tg3
*tp
= tnapi
->tp
;
4506 struct tg3_rx_buffer_desc
*src_desc
, *dest_desc
;
4507 struct ring_info
*src_map
, *dest_map
;
4508 struct tg3_rx_prodring_set
*spr
= &tp
->napi
[0].prodring
;
4511 switch (opaque_key
) {
4512 case RXD_OPAQUE_RING_STD
:
4513 dest_idx
= dest_idx_unmasked
& tp
->rx_std_ring_mask
;
4514 dest_desc
= &dpr
->rx_std
[dest_idx
];
4515 dest_map
= &dpr
->rx_std_buffers
[dest_idx
];
4516 src_desc
= &spr
->rx_std
[src_idx
];
4517 src_map
= &spr
->rx_std_buffers
[src_idx
];
4520 case RXD_OPAQUE_RING_JUMBO
:
4521 dest_idx
= dest_idx_unmasked
& tp
->rx_jmb_ring_mask
;
4522 dest_desc
= &dpr
->rx_jmb
[dest_idx
].std
;
4523 dest_map
= &dpr
->rx_jmb_buffers
[dest_idx
];
4524 src_desc
= &spr
->rx_jmb
[src_idx
].std
;
4525 src_map
= &spr
->rx_jmb_buffers
[src_idx
];
4532 dest_map
->skb
= src_map
->skb
;
4533 dma_unmap_addr_set(dest_map
, mapping
,
4534 dma_unmap_addr(src_map
, mapping
));
4535 dest_desc
->addr_hi
= src_desc
->addr_hi
;
4536 dest_desc
->addr_lo
= src_desc
->addr_lo
;
4538 /* Ensure that the update to the skb happens after the physical
4539 * addresses have been transferred to the new BD location.
4543 src_map
->skb
= NULL
;
4546 /* The RX ring scheme is composed of multiple rings which post fresh
4547 * buffers to the chip, and one special ring the chip uses to report
4548 * status back to the host.
4550 * The special ring reports the status of received packets to the
4551 * host. The chip does not write into the original descriptor the
4552 * RX buffer was obtained from. The chip simply takes the original
4553 * descriptor as provided by the host, updates the status and length
4554 * field, then writes this into the next status ring entry.
4556 * Each ring the host uses to post buffers to the chip is described
4557 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4558 * it is first placed into the on-chip ram. When the packet's length
4559 * is known, it walks down the TG3_BDINFO entries to select the ring.
4560 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4561 * which is within the range of the new packet's length is chosen.
4563 * The "separate ring for rx status" scheme may sound queer, but it makes
4564 * sense from a cache coherency perspective. If only the host writes
4565 * to the buffer post rings, and only the chip writes to the rx status
4566 * rings, then cache lines never move beyond shared-modified state.
4567 * If both the host and chip were to write into the same ring, cache line
4568 * eviction could occur since both entities want it in an exclusive state.
4570 static int tg3_rx(struct tg3_napi
*tnapi
, int budget
)
4572 struct tg3
*tp
= tnapi
->tp
;
4573 u32 work_mask
, rx_std_posted
= 0;
4574 u32 std_prod_idx
, jmb_prod_idx
;
4575 u32 sw_idx
= tnapi
->rx_rcb_ptr
;
4578 struct tg3_rx_prodring_set
*tpr
= &tnapi
->prodring
;
4580 hw_idx
= *(tnapi
->rx_rcb_prod_idx
);
4582 * We need to order the read of hw_idx and the read of
4583 * the opaque cookie.
4588 std_prod_idx
= tpr
->rx_std_prod_idx
;
4589 jmb_prod_idx
= tpr
->rx_jmb_prod_idx
;
4590 while (sw_idx
!= hw_idx
&& budget
> 0) {
4591 struct ring_info
*ri
;
4592 struct tg3_rx_buffer_desc
*desc
= &tnapi
->rx_rcb
[sw_idx
];
4594 struct sk_buff
*skb
;
4595 dma_addr_t dma_addr
;
4596 u32 opaque_key
, desc_idx
, *post_ptr
;
4597 bool hw_vlan __maybe_unused
= false;
4598 u16 vtag __maybe_unused
= 0;
4600 desc_idx
= desc
->opaque
& RXD_OPAQUE_INDEX_MASK
;
4601 opaque_key
= desc
->opaque
& RXD_OPAQUE_RING_MASK
;
4602 if (opaque_key
== RXD_OPAQUE_RING_STD
) {
4603 ri
= &tp
->napi
[0].prodring
.rx_std_buffers
[desc_idx
];
4604 dma_addr
= dma_unmap_addr(ri
, mapping
);
4606 post_ptr
= &std_prod_idx
;
4608 } else if (opaque_key
== RXD_OPAQUE_RING_JUMBO
) {
4609 ri
= &tp
->napi
[0].prodring
.rx_jmb_buffers
[desc_idx
];
4610 dma_addr
= dma_unmap_addr(ri
, mapping
);
4612 post_ptr
= &jmb_prod_idx
;
4614 goto next_pkt_nopost
;
4616 work_mask
|= opaque_key
;
4618 if ((desc
->err_vlan
& RXD_ERR_MASK
) != 0 &&
4619 (desc
->err_vlan
!= RXD_ERR_ODD_NIBBLE_RCVD_MII
)) {
4621 tg3_recycle_rx(tnapi
, tpr
, opaque_key
,
4622 desc_idx
, *post_ptr
);
4624 /* Other statistics kept track of by card. */
4625 tp
->net_stats
.rx_dropped
++;
4629 len
= ((desc
->idx_len
& RXD_LEN_MASK
) >> RXD_LEN_SHIFT
) -
4632 if (len
> TG3_RX_COPY_THRESH(tp
)) {
4635 skb_size
= tg3_alloc_rx_skb(tp
, tpr
, opaque_key
,
4640 pci_unmap_single(tp
->pdev
, dma_addr
, skb_size
,
4641 PCI_DMA_FROMDEVICE
);
4643 /* Ensure that the update to the skb happens
4644 * after the usage of the old DMA mapping.
4652 struct sk_buff
*copy_skb
;
4654 tg3_recycle_rx(tnapi
, tpr
, opaque_key
,
4655 desc_idx
, *post_ptr
);
4657 copy_skb
= netdev_alloc_skb(tp
->dev
, len
+ VLAN_HLEN
+
4659 if (copy_skb
== NULL
)
4660 goto drop_it_no_recycle
;
4662 skb_reserve(copy_skb
, TG3_RAW_IP_ALIGN
+ VLAN_HLEN
);
4663 skb_put(copy_skb
, len
);
4664 pci_dma_sync_single_for_cpu(tp
->pdev
, dma_addr
, len
, PCI_DMA_FROMDEVICE
);
4665 skb_copy_from_linear_data(skb
, copy_skb
->data
, len
);
4666 pci_dma_sync_single_for_device(tp
->pdev
, dma_addr
, len
, PCI_DMA_FROMDEVICE
);
4668 /* We'll reuse the original ring buffer. */
4672 if ((tp
->tg3_flags
& TG3_FLAG_RX_CHECKSUMS
) &&
4673 (desc
->type_flags
& RXD_FLAG_TCPUDP_CSUM
) &&
4674 (((desc
->ip_tcp_csum
& RXD_TCPCSUM_MASK
)
4675 >> RXD_TCPCSUM_SHIFT
) == 0xffff))
4676 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
4678 skb_checksum_none_assert(skb
);
4680 skb
->protocol
= eth_type_trans(skb
, tp
->dev
);
4682 if (len
> (tp
->dev
->mtu
+ ETH_HLEN
) &&
4683 skb
->protocol
!= htons(ETH_P_8021Q
)) {
4688 if (desc
->type_flags
& RXD_FLAG_VLAN
&&
4689 !(tp
->rx_mode
& RX_MODE_KEEP_VLAN_TAG
)) {
4690 vtag
= desc
->err_vlan
& RXD_VLAN_MASK
;
4691 #if TG3_VLAN_TAG_USED
4697 struct vlan_ethhdr
*ve
= (struct vlan_ethhdr
*)
4698 __skb_push(skb
, VLAN_HLEN
);
4700 memmove(ve
, skb
->data
+ VLAN_HLEN
,
4702 ve
->h_vlan_proto
= htons(ETH_P_8021Q
);
4703 ve
->h_vlan_TCI
= htons(vtag
);
4707 #if TG3_VLAN_TAG_USED
4709 vlan_gro_receive(&tnapi
->napi
, tp
->vlgrp
, vtag
, skb
);
4712 napi_gro_receive(&tnapi
->napi
, skb
);
4720 if (unlikely(rx_std_posted
>= tp
->rx_std_max_post
)) {
4721 tpr
->rx_std_prod_idx
= std_prod_idx
&
4722 tp
->rx_std_ring_mask
;
4723 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG
,
4724 tpr
->rx_std_prod_idx
);
4725 work_mask
&= ~RXD_OPAQUE_RING_STD
;
4730 sw_idx
&= tp
->rx_ret_ring_mask
;
4732 /* Refresh hw_idx to see if there is new work */
4733 if (sw_idx
== hw_idx
) {
4734 hw_idx
= *(tnapi
->rx_rcb_prod_idx
);
4739 /* ACK the status ring. */
4740 tnapi
->rx_rcb_ptr
= sw_idx
;
4741 tw32_rx_mbox(tnapi
->consmbox
, sw_idx
);
4743 /* Refill RX ring(s). */
4744 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_RSS
)) {
4745 if (work_mask
& RXD_OPAQUE_RING_STD
) {
4746 tpr
->rx_std_prod_idx
= std_prod_idx
&
4747 tp
->rx_std_ring_mask
;
4748 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG
,
4749 tpr
->rx_std_prod_idx
);
4751 if (work_mask
& RXD_OPAQUE_RING_JUMBO
) {
4752 tpr
->rx_jmb_prod_idx
= jmb_prod_idx
&
4753 tp
->rx_jmb_ring_mask
;
4754 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG
,
4755 tpr
->rx_jmb_prod_idx
);
4758 } else if (work_mask
) {
4759 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4760 * updated before the producer indices can be updated.
4764 tpr
->rx_std_prod_idx
= std_prod_idx
& tp
->rx_std_ring_mask
;
4765 tpr
->rx_jmb_prod_idx
= jmb_prod_idx
& tp
->rx_jmb_ring_mask
;
4767 if (tnapi
!= &tp
->napi
[1])
4768 napi_schedule(&tp
->napi
[1].napi
);
4774 static void tg3_poll_link(struct tg3
*tp
)
4776 /* handle link change and other phy events */
4777 if (!(tp
->tg3_flags
&
4778 (TG3_FLAG_USE_LINKCHG_REG
|
4779 TG3_FLAG_POLL_SERDES
))) {
4780 struct tg3_hw_status
*sblk
= tp
->napi
[0].hw_status
;
4782 if (sblk
->status
& SD_STATUS_LINK_CHG
) {
4783 sblk
->status
= SD_STATUS_UPDATED
|
4784 (sblk
->status
& ~SD_STATUS_LINK_CHG
);
4785 spin_lock(&tp
->lock
);
4786 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
4788 (MAC_STATUS_SYNC_CHANGED
|
4789 MAC_STATUS_CFG_CHANGED
|
4790 MAC_STATUS_MI_COMPLETION
|
4791 MAC_STATUS_LNKSTATE_CHANGED
));
4794 tg3_setup_phy(tp
, 0);
4795 spin_unlock(&tp
->lock
);
4800 static int tg3_rx_prodring_xfer(struct tg3
*tp
,
4801 struct tg3_rx_prodring_set
*dpr
,
4802 struct tg3_rx_prodring_set
*spr
)
4804 u32 si
, di
, cpycnt
, src_prod_idx
;
4808 src_prod_idx
= spr
->rx_std_prod_idx
;
4810 /* Make sure updates to the rx_std_buffers[] entries and the
4811 * standard producer index are seen in the correct order.
4815 if (spr
->rx_std_cons_idx
== src_prod_idx
)
4818 if (spr
->rx_std_cons_idx
< src_prod_idx
)
4819 cpycnt
= src_prod_idx
- spr
->rx_std_cons_idx
;
4821 cpycnt
= tp
->rx_std_ring_mask
+ 1 -
4822 spr
->rx_std_cons_idx
;
4824 cpycnt
= min(cpycnt
,
4825 tp
->rx_std_ring_mask
+ 1 - dpr
->rx_std_prod_idx
);
4827 si
= spr
->rx_std_cons_idx
;
4828 di
= dpr
->rx_std_prod_idx
;
4830 for (i
= di
; i
< di
+ cpycnt
; i
++) {
4831 if (dpr
->rx_std_buffers
[i
].skb
) {
4841 /* Ensure that updates to the rx_std_buffers ring and the
4842 * shadowed hardware producer ring from tg3_recycle_skb() are
4843 * ordered correctly WRT the skb check above.
4847 memcpy(&dpr
->rx_std_buffers
[di
],
4848 &spr
->rx_std_buffers
[si
],
4849 cpycnt
* sizeof(struct ring_info
));
4851 for (i
= 0; i
< cpycnt
; i
++, di
++, si
++) {
4852 struct tg3_rx_buffer_desc
*sbd
, *dbd
;
4853 sbd
= &spr
->rx_std
[si
];
4854 dbd
= &dpr
->rx_std
[di
];
4855 dbd
->addr_hi
= sbd
->addr_hi
;
4856 dbd
->addr_lo
= sbd
->addr_lo
;
4859 spr
->rx_std_cons_idx
= (spr
->rx_std_cons_idx
+ cpycnt
) &
4860 tp
->rx_std_ring_mask
;
4861 dpr
->rx_std_prod_idx
= (dpr
->rx_std_prod_idx
+ cpycnt
) &
4862 tp
->rx_std_ring_mask
;
4866 src_prod_idx
= spr
->rx_jmb_prod_idx
;
4868 /* Make sure updates to the rx_jmb_buffers[] entries and
4869 * the jumbo producer index are seen in the correct order.
4873 if (spr
->rx_jmb_cons_idx
== src_prod_idx
)
4876 if (spr
->rx_jmb_cons_idx
< src_prod_idx
)
4877 cpycnt
= src_prod_idx
- spr
->rx_jmb_cons_idx
;
4879 cpycnt
= tp
->rx_jmb_ring_mask
+ 1 -
4880 spr
->rx_jmb_cons_idx
;
4882 cpycnt
= min(cpycnt
,
4883 tp
->rx_jmb_ring_mask
+ 1 - dpr
->rx_jmb_prod_idx
);
4885 si
= spr
->rx_jmb_cons_idx
;
4886 di
= dpr
->rx_jmb_prod_idx
;
4888 for (i
= di
; i
< di
+ cpycnt
; i
++) {
4889 if (dpr
->rx_jmb_buffers
[i
].skb
) {
4899 /* Ensure that updates to the rx_jmb_buffers ring and the
4900 * shadowed hardware producer ring from tg3_recycle_skb() are
4901 * ordered correctly WRT the skb check above.
4905 memcpy(&dpr
->rx_jmb_buffers
[di
],
4906 &spr
->rx_jmb_buffers
[si
],
4907 cpycnt
* sizeof(struct ring_info
));
4909 for (i
= 0; i
< cpycnt
; i
++, di
++, si
++) {
4910 struct tg3_rx_buffer_desc
*sbd
, *dbd
;
4911 sbd
= &spr
->rx_jmb
[si
].std
;
4912 dbd
= &dpr
->rx_jmb
[di
].std
;
4913 dbd
->addr_hi
= sbd
->addr_hi
;
4914 dbd
->addr_lo
= sbd
->addr_lo
;
4917 spr
->rx_jmb_cons_idx
= (spr
->rx_jmb_cons_idx
+ cpycnt
) &
4918 tp
->rx_jmb_ring_mask
;
4919 dpr
->rx_jmb_prod_idx
= (dpr
->rx_jmb_prod_idx
+ cpycnt
) &
4920 tp
->rx_jmb_ring_mask
;
4926 static int tg3_poll_work(struct tg3_napi
*tnapi
, int work_done
, int budget
)
4928 struct tg3
*tp
= tnapi
->tp
;
4930 /* run TX completion thread */
4931 if (tnapi
->hw_status
->idx
[0].tx_consumer
!= tnapi
->tx_cons
) {
4933 if (unlikely(tp
->tg3_flags
& TG3_FLAG_TX_RECOVERY_PENDING
))
4937 /* run RX thread, within the bounds set by NAPI.
4938 * All RX "locking" is done by ensuring outside
4939 * code synchronizes with tg3->napi.poll()
4941 if (*(tnapi
->rx_rcb_prod_idx
) != tnapi
->rx_rcb_ptr
)
4942 work_done
+= tg3_rx(tnapi
, budget
- work_done
);
4944 if ((tp
->tg3_flags3
& TG3_FLG3_ENABLE_RSS
) && tnapi
== &tp
->napi
[1]) {
4945 struct tg3_rx_prodring_set
*dpr
= &tp
->napi
[0].prodring
;
4947 u32 std_prod_idx
= dpr
->rx_std_prod_idx
;
4948 u32 jmb_prod_idx
= dpr
->rx_jmb_prod_idx
;
4950 for (i
= 1; i
< tp
->irq_cnt
; i
++)
4951 err
|= tg3_rx_prodring_xfer(tp
, dpr
,
4952 &tp
->napi
[i
].prodring
);
4956 if (std_prod_idx
!= dpr
->rx_std_prod_idx
)
4957 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG
,
4958 dpr
->rx_std_prod_idx
);
4960 if (jmb_prod_idx
!= dpr
->rx_jmb_prod_idx
)
4961 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG
,
4962 dpr
->rx_jmb_prod_idx
);
4967 tw32_f(HOSTCC_MODE
, tp
->coal_now
);
4973 static int tg3_poll_msix(struct napi_struct
*napi
, int budget
)
4975 struct tg3_napi
*tnapi
= container_of(napi
, struct tg3_napi
, napi
);
4976 struct tg3
*tp
= tnapi
->tp
;
4978 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
4981 work_done
= tg3_poll_work(tnapi
, work_done
, budget
);
4983 if (unlikely(tp
->tg3_flags
& TG3_FLAG_TX_RECOVERY_PENDING
))
4986 if (unlikely(work_done
>= budget
))
4989 /* tp->last_tag is used in tg3_int_reenable() below
4990 * to tell the hw how much work has been processed,
4991 * so we must read it before checking for more work.
4993 tnapi
->last_tag
= sblk
->status_tag
;
4994 tnapi
->last_irq_tag
= tnapi
->last_tag
;
4997 /* check for RX/TX work to do */
4998 if (likely(sblk
->idx
[0].tx_consumer
== tnapi
->tx_cons
&&
4999 *(tnapi
->rx_rcb_prod_idx
) == tnapi
->rx_rcb_ptr
)) {
5000 napi_complete(napi
);
5001 /* Reenable interrupts. */
5002 tw32_mailbox(tnapi
->int_mbox
, tnapi
->last_tag
<< 24);
5011 /* work_done is guaranteed to be less than budget. */
5012 napi_complete(napi
);
5013 schedule_work(&tp
->reset_task
);
5017 static int tg3_poll(struct napi_struct
*napi
, int budget
)
5019 struct tg3_napi
*tnapi
= container_of(napi
, struct tg3_napi
, napi
);
5020 struct tg3
*tp
= tnapi
->tp
;
5022 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
5027 work_done
= tg3_poll_work(tnapi
, work_done
, budget
);
5029 if (unlikely(tp
->tg3_flags
& TG3_FLAG_TX_RECOVERY_PENDING
))
5032 if (unlikely(work_done
>= budget
))
5035 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) {
5036 /* tp->last_tag is used in tg3_int_reenable() below
5037 * to tell the hw how much work has been processed,
5038 * so we must read it before checking for more work.
5040 tnapi
->last_tag
= sblk
->status_tag
;
5041 tnapi
->last_irq_tag
= tnapi
->last_tag
;
5044 sblk
->status
&= ~SD_STATUS_UPDATED
;
5046 if (likely(!tg3_has_work(tnapi
))) {
5047 napi_complete(napi
);
5048 tg3_int_reenable(tnapi
);
5056 /* work_done is guaranteed to be less than budget. */
5057 napi_complete(napi
);
5058 schedule_work(&tp
->reset_task
);
5062 static void tg3_napi_disable(struct tg3
*tp
)
5066 for (i
= tp
->irq_cnt
- 1; i
>= 0; i
--)
5067 napi_disable(&tp
->napi
[i
].napi
);
5070 static void tg3_napi_enable(struct tg3
*tp
)
5074 for (i
= 0; i
< tp
->irq_cnt
; i
++)
5075 napi_enable(&tp
->napi
[i
].napi
);
5078 static void tg3_napi_init(struct tg3
*tp
)
5082 netif_napi_add(tp
->dev
, &tp
->napi
[0].napi
, tg3_poll
, 64);
5083 for (i
= 1; i
< tp
->irq_cnt
; i
++)
5084 netif_napi_add(tp
->dev
, &tp
->napi
[i
].napi
, tg3_poll_msix
, 64);
5087 static void tg3_napi_fini(struct tg3
*tp
)
5091 for (i
= 0; i
< tp
->irq_cnt
; i
++)
5092 netif_napi_del(&tp
->napi
[i
].napi
);
5095 static inline void tg3_netif_stop(struct tg3
*tp
)
5097 tp
->dev
->trans_start
= jiffies
; /* prevent tx timeout */
5098 tg3_napi_disable(tp
);
5099 netif_tx_disable(tp
->dev
);
5102 static inline void tg3_netif_start(struct tg3
*tp
)
5104 /* NOTE: unconditional netif_tx_wake_all_queues is only
5105 * appropriate so long as all callers are assured to
5106 * have free tx slots (such as after tg3_init_hw)
5108 netif_tx_wake_all_queues(tp
->dev
);
5110 tg3_napi_enable(tp
);
5111 tp
->napi
[0].hw_status
->status
|= SD_STATUS_UPDATED
;
5112 tg3_enable_ints(tp
);
5115 static void tg3_irq_quiesce(struct tg3
*tp
)
5119 BUG_ON(tp
->irq_sync
);
5124 for (i
= 0; i
< tp
->irq_cnt
; i
++)
5125 synchronize_irq(tp
->napi
[i
].irq_vec
);
5128 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5129 * If irq_sync is non-zero, then the IRQ handler must be synchronized
5130 * with as well. Most of the time, this is not necessary except when
5131 * shutting down the device.
5133 static inline void tg3_full_lock(struct tg3
*tp
, int irq_sync
)
5135 spin_lock_bh(&tp
->lock
);
5137 tg3_irq_quiesce(tp
);
5140 static inline void tg3_full_unlock(struct tg3
*tp
)
5142 spin_unlock_bh(&tp
->lock
);
5145 /* One-shot MSI handler - Chip automatically disables interrupt
5146 * after sending MSI so driver doesn't have to do it.
5148 static irqreturn_t
tg3_msi_1shot(int irq
, void *dev_id
)
5150 struct tg3_napi
*tnapi
= dev_id
;
5151 struct tg3
*tp
= tnapi
->tp
;
5153 prefetch(tnapi
->hw_status
);
5155 prefetch(&tnapi
->rx_rcb
[tnapi
->rx_rcb_ptr
]);
5157 if (likely(!tg3_irq_sync(tp
)))
5158 napi_schedule(&tnapi
->napi
);
5163 /* MSI ISR - No need to check for interrupt sharing and no need to
5164 * flush status block and interrupt mailbox. PCI ordering rules
5165 * guarantee that MSI will arrive after the status block.
5167 static irqreturn_t
tg3_msi(int irq
, void *dev_id
)
5169 struct tg3_napi
*tnapi
= dev_id
;
5170 struct tg3
*tp
= tnapi
->tp
;
5172 prefetch(tnapi
->hw_status
);
5174 prefetch(&tnapi
->rx_rcb
[tnapi
->rx_rcb_ptr
]);
5176 * Writing any value to intr-mbox-0 clears PCI INTA# and
5177 * chip-internal interrupt pending events.
5178 * Writing non-zero to intr-mbox-0 additional tells the
5179 * NIC to stop sending us irqs, engaging "in-intr-handler"
5182 tw32_mailbox(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0x00000001);
5183 if (likely(!tg3_irq_sync(tp
)))
5184 napi_schedule(&tnapi
->napi
);
5186 return IRQ_RETVAL(1);
5189 static irqreturn_t
tg3_interrupt(int irq
, void *dev_id
)
5191 struct tg3_napi
*tnapi
= dev_id
;
5192 struct tg3
*tp
= tnapi
->tp
;
5193 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
5194 unsigned int handled
= 1;
5196 /* In INTx mode, it is possible for the interrupt to arrive at
5197 * the CPU before the status block posted prior to the interrupt.
5198 * Reading the PCI State register will confirm whether the
5199 * interrupt is ours and will flush the status block.
5201 if (unlikely(!(sblk
->status
& SD_STATUS_UPDATED
))) {
5202 if ((tp
->tg3_flags
& TG3_FLAG_CHIP_RESETTING
) ||
5203 (tr32(TG3PCI_PCISTATE
) & PCISTATE_INT_NOT_ACTIVE
)) {
5210 * Writing any value to intr-mbox-0 clears PCI INTA# and
5211 * chip-internal interrupt pending events.
5212 * Writing non-zero to intr-mbox-0 additional tells the
5213 * NIC to stop sending us irqs, engaging "in-intr-handler"
5216 * Flush the mailbox to de-assert the IRQ immediately to prevent
5217 * spurious interrupts. The flush impacts performance but
5218 * excessive spurious interrupts can be worse in some cases.
5220 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0x00000001);
5221 if (tg3_irq_sync(tp
))
5223 sblk
->status
&= ~SD_STATUS_UPDATED
;
5224 if (likely(tg3_has_work(tnapi
))) {
5225 prefetch(&tnapi
->rx_rcb
[tnapi
->rx_rcb_ptr
]);
5226 napi_schedule(&tnapi
->napi
);
5228 /* No work, shared interrupt perhaps? re-enable
5229 * interrupts, and flush that PCI write
5231 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
,
5235 return IRQ_RETVAL(handled
);
5238 static irqreturn_t
tg3_interrupt_tagged(int irq
, void *dev_id
)
5240 struct tg3_napi
*tnapi
= dev_id
;
5241 struct tg3
*tp
= tnapi
->tp
;
5242 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
5243 unsigned int handled
= 1;
5245 /* In INTx mode, it is possible for the interrupt to arrive at
5246 * the CPU before the status block posted prior to the interrupt.
5247 * Reading the PCI State register will confirm whether the
5248 * interrupt is ours and will flush the status block.
5250 if (unlikely(sblk
->status_tag
== tnapi
->last_irq_tag
)) {
5251 if ((tp
->tg3_flags
& TG3_FLAG_CHIP_RESETTING
) ||
5252 (tr32(TG3PCI_PCISTATE
) & PCISTATE_INT_NOT_ACTIVE
)) {
5259 * writing any value to intr-mbox-0 clears PCI INTA# and
5260 * chip-internal interrupt pending events.
5261 * writing non-zero to intr-mbox-0 additional tells the
5262 * NIC to stop sending us irqs, engaging "in-intr-handler"
5265 * Flush the mailbox to de-assert the IRQ immediately to prevent
5266 * spurious interrupts. The flush impacts performance but
5267 * excessive spurious interrupts can be worse in some cases.
5269 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0x00000001);
5272 * In a shared interrupt configuration, sometimes other devices'
5273 * interrupts will scream. We record the current status tag here
5274 * so that the above check can report that the screaming interrupts
5275 * are unhandled. Eventually they will be silenced.
5277 tnapi
->last_irq_tag
= sblk
->status_tag
;
5279 if (tg3_irq_sync(tp
))
5282 prefetch(&tnapi
->rx_rcb
[tnapi
->rx_rcb_ptr
]);
5284 napi_schedule(&tnapi
->napi
);
5287 return IRQ_RETVAL(handled
);
5290 /* ISR for interrupt test */
5291 static irqreturn_t
tg3_test_isr(int irq
, void *dev_id
)
5293 struct tg3_napi
*tnapi
= dev_id
;
5294 struct tg3
*tp
= tnapi
->tp
;
5295 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
5297 if ((sblk
->status
& SD_STATUS_UPDATED
) ||
5298 !(tr32(TG3PCI_PCISTATE
) & PCISTATE_INT_NOT_ACTIVE
)) {
5299 tg3_disable_ints(tp
);
5300 return IRQ_RETVAL(1);
5302 return IRQ_RETVAL(0);
5305 static int tg3_init_hw(struct tg3
*, int);
5306 static int tg3_halt(struct tg3
*, int, int);
5308 /* Restart hardware after configuration changes, self-test, etc.
5309 * Invoked with tp->lock held.
5311 static int tg3_restart_hw(struct tg3
*tp
, int reset_phy
)
5312 __releases(tp
->lock
)
5313 __acquires(tp
->lock
)
5317 err
= tg3_init_hw(tp
, reset_phy
);
5320 "Failed to re-initialize device, aborting\n");
5321 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
5322 tg3_full_unlock(tp
);
5323 del_timer_sync(&tp
->timer
);
5325 tg3_napi_enable(tp
);
5327 tg3_full_lock(tp
, 0);
5332 #ifdef CONFIG_NET_POLL_CONTROLLER
5333 static void tg3_poll_controller(struct net_device
*dev
)
5336 struct tg3
*tp
= netdev_priv(dev
);
5338 for (i
= 0; i
< tp
->irq_cnt
; i
++)
5339 tg3_interrupt(tp
->napi
[i
].irq_vec
, &tp
->napi
[i
]);
5343 static void tg3_reset_task(struct work_struct
*work
)
5345 struct tg3
*tp
= container_of(work
, struct tg3
, reset_task
);
5347 unsigned int restart_timer
;
5349 tg3_full_lock(tp
, 0);
5351 if (!netif_running(tp
->dev
)) {
5352 tg3_full_unlock(tp
);
5356 tg3_full_unlock(tp
);
5362 tg3_full_lock(tp
, 1);
5364 restart_timer
= tp
->tg3_flags2
& TG3_FLG2_RESTART_TIMER
;
5365 tp
->tg3_flags2
&= ~TG3_FLG2_RESTART_TIMER
;
5367 if (tp
->tg3_flags
& TG3_FLAG_TX_RECOVERY_PENDING
) {
5368 tp
->write32_tx_mbox
= tg3_write32_tx_mbox
;
5369 tp
->write32_rx_mbox
= tg3_write_flush_reg32
;
5370 tp
->tg3_flags
|= TG3_FLAG_MBOX_WRITE_REORDER
;
5371 tp
->tg3_flags
&= ~TG3_FLAG_TX_RECOVERY_PENDING
;
5374 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 0);
5375 err
= tg3_init_hw(tp
, 1);
5379 tg3_netif_start(tp
);
5382 mod_timer(&tp
->timer
, jiffies
+ 1);
5385 tg3_full_unlock(tp
);
5391 static void tg3_dump_short_state(struct tg3
*tp
)
5393 netdev_err(tp
->dev
, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5394 tr32(MAC_TX_STATUS
), tr32(MAC_RX_STATUS
));
5395 netdev_err(tp
->dev
, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5396 tr32(RDMAC_STATUS
), tr32(WDMAC_STATUS
));
5399 static void tg3_tx_timeout(struct net_device
*dev
)
5401 struct tg3
*tp
= netdev_priv(dev
);
5403 if (netif_msg_tx_err(tp
)) {
5404 netdev_err(dev
, "transmit timed out, resetting\n");
5405 tg3_dump_short_state(tp
);
5408 schedule_work(&tp
->reset_task
);
5411 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5412 static inline int tg3_4g_overflow_test(dma_addr_t mapping
, int len
)
5414 u32 base
= (u32
) mapping
& 0xffffffff;
5416 return (base
> 0xffffdcc0) && (base
+ len
+ 8 < base
);
5419 /* Test for DMA addresses > 40-bit */
5420 static inline int tg3_40bit_overflow_test(struct tg3
*tp
, dma_addr_t mapping
,
5423 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5424 if (tp
->tg3_flags
& TG3_FLAG_40BIT_DMA_BUG
)
5425 return ((u64
) mapping
+ len
) > DMA_BIT_MASK(40);
5432 static void tg3_set_txd(struct tg3_napi
*, int, dma_addr_t
, int, u32
, u32
);
5434 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5435 static int tigon3_dma_hwbug_workaround(struct tg3_napi
*tnapi
,
5436 struct sk_buff
*skb
, u32 last_plus_one
,
5437 u32
*start
, u32 base_flags
, u32 mss
)
5439 struct tg3
*tp
= tnapi
->tp
;
5440 struct sk_buff
*new_skb
;
5441 dma_addr_t new_addr
= 0;
5445 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
)
5446 new_skb
= skb_copy(skb
, GFP_ATOMIC
);
5448 int more_headroom
= 4 - ((unsigned long)skb
->data
& 3);
5450 new_skb
= skb_copy_expand(skb
,
5451 skb_headroom(skb
) + more_headroom
,
5452 skb_tailroom(skb
), GFP_ATOMIC
);
5458 /* New SKB is guaranteed to be linear. */
5460 new_addr
= pci_map_single(tp
->pdev
, new_skb
->data
, new_skb
->len
,
5462 /* Make sure the mapping succeeded */
5463 if (pci_dma_mapping_error(tp
->pdev
, new_addr
)) {
5465 dev_kfree_skb(new_skb
);
5468 /* Make sure new skb does not cross any 4G boundaries.
5469 * Drop the packet if it does.
5471 } else if ((tp
->tg3_flags3
& TG3_FLG3_4G_DMA_BNDRY_BUG
) &&
5472 tg3_4g_overflow_test(new_addr
, new_skb
->len
)) {
5473 pci_unmap_single(tp
->pdev
, new_addr
, new_skb
->len
,
5476 dev_kfree_skb(new_skb
);
5479 tg3_set_txd(tnapi
, entry
, new_addr
, new_skb
->len
,
5480 base_flags
, 1 | (mss
<< 1));
5481 *start
= NEXT_TX(entry
);
5485 /* Now clean up the sw ring entries. */
5487 while (entry
!= last_plus_one
) {
5491 len
= skb_headlen(skb
);
5493 len
= skb_shinfo(skb
)->frags
[i
-1].size
;
5495 pci_unmap_single(tp
->pdev
,
5496 dma_unmap_addr(&tnapi
->tx_buffers
[entry
],
5498 len
, PCI_DMA_TODEVICE
);
5500 tnapi
->tx_buffers
[entry
].skb
= new_skb
;
5501 dma_unmap_addr_set(&tnapi
->tx_buffers
[entry
], mapping
,
5504 tnapi
->tx_buffers
[entry
].skb
= NULL
;
5506 entry
= NEXT_TX(entry
);
5515 static void tg3_set_txd(struct tg3_napi
*tnapi
, int entry
,
5516 dma_addr_t mapping
, int len
, u32 flags
,
5519 struct tg3_tx_buffer_desc
*txd
= &tnapi
->tx_ring
[entry
];
5520 int is_end
= (mss_and_is_end
& 0x1);
5521 u32 mss
= (mss_and_is_end
>> 1);
5525 flags
|= TXD_FLAG_END
;
5526 if (flags
& TXD_FLAG_VLAN
) {
5527 vlan_tag
= flags
>> 16;
5530 vlan_tag
|= (mss
<< TXD_MSS_SHIFT
);
5532 txd
->addr_hi
= ((u64
) mapping
>> 32);
5533 txd
->addr_lo
= ((u64
) mapping
& 0xffffffff);
5534 txd
->len_flags
= (len
<< TXD_LEN_SHIFT
) | flags
;
5535 txd
->vlan_tag
= vlan_tag
<< TXD_VLAN_TAG_SHIFT
;
5538 /* hard_start_xmit for devices that don't have any bugs and
5539 * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5541 static netdev_tx_t
tg3_start_xmit(struct sk_buff
*skb
,
5542 struct net_device
*dev
)
5544 struct tg3
*tp
= netdev_priv(dev
);
5545 u32 len
, entry
, base_flags
, mss
;
5547 struct tg3_napi
*tnapi
;
5548 struct netdev_queue
*txq
;
5549 unsigned int i
, last
;
5551 txq
= netdev_get_tx_queue(dev
, skb_get_queue_mapping(skb
));
5552 tnapi
= &tp
->napi
[skb_get_queue_mapping(skb
)];
5553 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)
5556 /* We are running in BH disabled context with netif_tx_lock
5557 * and TX reclaim runs via tp->napi.poll inside of a software
5558 * interrupt. Furthermore, IRQ processing runs lockless so we have
5559 * no IRQ context deadlocks to worry about either. Rejoice!
5561 if (unlikely(tg3_tx_avail(tnapi
) <= (skb_shinfo(skb
)->nr_frags
+ 1))) {
5562 if (!netif_tx_queue_stopped(txq
)) {
5563 netif_tx_stop_queue(txq
);
5565 /* This is a hard error, log it. */
5567 "BUG! Tx Ring full when queue awake!\n");
5569 return NETDEV_TX_BUSY
;
5572 entry
= tnapi
->tx_prod
;
5574 mss
= skb_shinfo(skb
)->gso_size
;
5576 int tcp_opt_len
, ip_tcp_len
;
5579 if (skb_header_cloned(skb
) &&
5580 pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
)) {
5585 if (skb_is_gso_v6(skb
)) {
5586 hdrlen
= skb_headlen(skb
) - ETH_HLEN
;
5588 struct iphdr
*iph
= ip_hdr(skb
);
5590 tcp_opt_len
= tcp_optlen(skb
);
5591 ip_tcp_len
= ip_hdrlen(skb
) + sizeof(struct tcphdr
);
5594 iph
->tot_len
= htons(mss
+ ip_tcp_len
+ tcp_opt_len
);
5595 hdrlen
= ip_tcp_len
+ tcp_opt_len
;
5598 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO_3
) {
5599 mss
|= (hdrlen
& 0xc) << 12;
5601 base_flags
|= 0x00000010;
5602 base_flags
|= (hdrlen
& 0x3e0) << 5;
5606 base_flags
|= (TXD_FLAG_CPU_PRE_DMA
|
5607 TXD_FLAG_CPU_POST_DMA
);
5609 tcp_hdr(skb
)->check
= 0;
5611 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
5612 base_flags
|= TXD_FLAG_TCPUDP_CSUM
;
5615 #if TG3_VLAN_TAG_USED
5616 if (tp
->vlgrp
!= NULL
&& vlan_tx_tag_present(skb
))
5617 base_flags
|= (TXD_FLAG_VLAN
|
5618 (vlan_tx_tag_get(skb
) << 16));
5621 len
= skb_headlen(skb
);
5623 /* Queue skb data, a.k.a. the main skb fragment. */
5624 mapping
= pci_map_single(tp
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
5625 if (pci_dma_mapping_error(tp
->pdev
, mapping
)) {
5630 tnapi
->tx_buffers
[entry
].skb
= skb
;
5631 dma_unmap_addr_set(&tnapi
->tx_buffers
[entry
], mapping
, mapping
);
5633 if ((tp
->tg3_flags3
& TG3_FLG3_USE_JUMBO_BDFLAG
) &&
5634 !mss
&& skb
->len
> ETH_DATA_LEN
)
5635 base_flags
|= TXD_FLAG_JMB_PKT
;
5637 tg3_set_txd(tnapi
, entry
, mapping
, len
, base_flags
,
5638 (skb_shinfo(skb
)->nr_frags
== 0) | (mss
<< 1));
5640 entry
= NEXT_TX(entry
);
5642 /* Now loop through additional data fragments, and queue them. */
5643 if (skb_shinfo(skb
)->nr_frags
> 0) {
5644 last
= skb_shinfo(skb
)->nr_frags
- 1;
5645 for (i
= 0; i
<= last
; i
++) {
5646 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
5649 mapping
= pci_map_page(tp
->pdev
,
5652 len
, PCI_DMA_TODEVICE
);
5653 if (pci_dma_mapping_error(tp
->pdev
, mapping
))
5656 tnapi
->tx_buffers
[entry
].skb
= NULL
;
5657 dma_unmap_addr_set(&tnapi
->tx_buffers
[entry
], mapping
,
5660 tg3_set_txd(tnapi
, entry
, mapping
, len
,
5661 base_flags
, (i
== last
) | (mss
<< 1));
5663 entry
= NEXT_TX(entry
);
5667 /* Packets are ready, update Tx producer idx local and on card. */
5668 tw32_tx_mbox(tnapi
->prodmbox
, entry
);
5670 tnapi
->tx_prod
= entry
;
5671 if (unlikely(tg3_tx_avail(tnapi
) <= (MAX_SKB_FRAGS
+ 1))) {
5672 netif_tx_stop_queue(txq
);
5674 /* netif_tx_stop_queue() must be done before checking
5675 * checking tx index in tg3_tx_avail() below, because in
5676 * tg3_tx(), we update tx index before checking for
5677 * netif_tx_queue_stopped().
5680 if (tg3_tx_avail(tnapi
) > TG3_TX_WAKEUP_THRESH(tnapi
))
5681 netif_tx_wake_queue(txq
);
5687 return NETDEV_TX_OK
;
5691 entry
= tnapi
->tx_prod
;
5692 tnapi
->tx_buffers
[entry
].skb
= NULL
;
5693 pci_unmap_single(tp
->pdev
,
5694 dma_unmap_addr(&tnapi
->tx_buffers
[entry
], mapping
),
5697 for (i
= 0; i
<= last
; i
++) {
5698 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
5699 entry
= NEXT_TX(entry
);
5701 pci_unmap_page(tp
->pdev
,
5702 dma_unmap_addr(&tnapi
->tx_buffers
[entry
],
5704 frag
->size
, PCI_DMA_TODEVICE
);
5708 return NETDEV_TX_OK
;
5711 static netdev_tx_t
tg3_start_xmit_dma_bug(struct sk_buff
*,
5712 struct net_device
*);
5714 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5715 * TSO header is greater than 80 bytes.
5717 static int tg3_tso_bug(struct tg3
*tp
, struct sk_buff
*skb
)
5719 struct sk_buff
*segs
, *nskb
;
5720 u32 frag_cnt_est
= skb_shinfo(skb
)->gso_segs
* 3;
5722 /* Estimate the number of fragments in the worst case */
5723 if (unlikely(tg3_tx_avail(&tp
->napi
[0]) <= frag_cnt_est
)) {
5724 netif_stop_queue(tp
->dev
);
5726 /* netif_tx_stop_queue() must be done before checking
5727 * checking tx index in tg3_tx_avail() below, because in
5728 * tg3_tx(), we update tx index before checking for
5729 * netif_tx_queue_stopped().
5732 if (tg3_tx_avail(&tp
->napi
[0]) <= frag_cnt_est
)
5733 return NETDEV_TX_BUSY
;
5735 netif_wake_queue(tp
->dev
);
5738 segs
= skb_gso_segment(skb
, tp
->dev
->features
& ~NETIF_F_TSO
);
5740 goto tg3_tso_bug_end
;
5746 tg3_start_xmit_dma_bug(nskb
, tp
->dev
);
5752 return NETDEV_TX_OK
;
5755 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5756 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5758 static netdev_tx_t
tg3_start_xmit_dma_bug(struct sk_buff
*skb
,
5759 struct net_device
*dev
)
5761 struct tg3
*tp
= netdev_priv(dev
);
5762 u32 len
, entry
, base_flags
, mss
;
5763 int would_hit_hwbug
;
5765 struct tg3_napi
*tnapi
;
5766 struct netdev_queue
*txq
;
5767 unsigned int i
, last
;
5769 txq
= netdev_get_tx_queue(dev
, skb_get_queue_mapping(skb
));
5770 tnapi
= &tp
->napi
[skb_get_queue_mapping(skb
)];
5771 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)
5774 /* We are running in BH disabled context with netif_tx_lock
5775 * and TX reclaim runs via tp->napi.poll inside of a software
5776 * interrupt. Furthermore, IRQ processing runs lockless so we have
5777 * no IRQ context deadlocks to worry about either. Rejoice!
5779 if (unlikely(tg3_tx_avail(tnapi
) <= (skb_shinfo(skb
)->nr_frags
+ 1))) {
5780 if (!netif_tx_queue_stopped(txq
)) {
5781 netif_tx_stop_queue(txq
);
5783 /* This is a hard error, log it. */
5785 "BUG! Tx Ring full when queue awake!\n");
5787 return NETDEV_TX_BUSY
;
5790 entry
= tnapi
->tx_prod
;
5792 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
5793 base_flags
|= TXD_FLAG_TCPUDP_CSUM
;
5795 mss
= skb_shinfo(skb
)->gso_size
;
5798 u32 tcp_opt_len
, hdr_len
;
5800 if (skb_header_cloned(skb
) &&
5801 pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
)) {
5807 tcp_opt_len
= tcp_optlen(skb
);
5809 if (skb_is_gso_v6(skb
)) {
5810 hdr_len
= skb_headlen(skb
) - ETH_HLEN
;
5814 ip_tcp_len
= ip_hdrlen(skb
) + sizeof(struct tcphdr
);
5815 hdr_len
= ip_tcp_len
+ tcp_opt_len
;
5818 iph
->tot_len
= htons(mss
+ hdr_len
);
5821 if (unlikely((ETH_HLEN
+ hdr_len
) > 80) &&
5822 (tp
->tg3_flags2
& TG3_FLG2_TSO_BUG
))
5823 return tg3_tso_bug(tp
, skb
);
5825 base_flags
|= (TXD_FLAG_CPU_PRE_DMA
|
5826 TXD_FLAG_CPU_POST_DMA
);
5828 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
) {
5829 tcp_hdr(skb
)->check
= 0;
5830 base_flags
&= ~TXD_FLAG_TCPUDP_CSUM
;
5832 tcp_hdr(skb
)->check
= ~csum_tcpudp_magic(iph
->saddr
,
5837 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO_3
) {
5838 mss
|= (hdr_len
& 0xc) << 12;
5840 base_flags
|= 0x00000010;
5841 base_flags
|= (hdr_len
& 0x3e0) << 5;
5842 } else if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO_2
)
5843 mss
|= hdr_len
<< 9;
5844 else if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO_1
) ||
5845 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
5846 if (tcp_opt_len
|| iph
->ihl
> 5) {
5849 tsflags
= (iph
->ihl
- 5) + (tcp_opt_len
>> 2);
5850 mss
|= (tsflags
<< 11);
5853 if (tcp_opt_len
|| iph
->ihl
> 5) {
5856 tsflags
= (iph
->ihl
- 5) + (tcp_opt_len
>> 2);
5857 base_flags
|= tsflags
<< 12;
5861 #if TG3_VLAN_TAG_USED
5862 if (tp
->vlgrp
!= NULL
&& vlan_tx_tag_present(skb
))
5863 base_flags
|= (TXD_FLAG_VLAN
|
5864 (vlan_tx_tag_get(skb
) << 16));
5867 if ((tp
->tg3_flags3
& TG3_FLG3_USE_JUMBO_BDFLAG
) &&
5868 !mss
&& skb
->len
> ETH_DATA_LEN
)
5869 base_flags
|= TXD_FLAG_JMB_PKT
;
5871 len
= skb_headlen(skb
);
5873 mapping
= pci_map_single(tp
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
5874 if (pci_dma_mapping_error(tp
->pdev
, mapping
)) {
5879 tnapi
->tx_buffers
[entry
].skb
= skb
;
5880 dma_unmap_addr_set(&tnapi
->tx_buffers
[entry
], mapping
, mapping
);
5882 would_hit_hwbug
= 0;
5884 if ((tp
->tg3_flags3
& TG3_FLG3_SHORT_DMA_BUG
) && len
<= 8)
5885 would_hit_hwbug
= 1;
5887 if ((tp
->tg3_flags3
& TG3_FLG3_4G_DMA_BNDRY_BUG
) &&
5888 tg3_4g_overflow_test(mapping
, len
))
5889 would_hit_hwbug
= 1;
5891 if ((tp
->tg3_flags3
& TG3_FLG3_40BIT_DMA_LIMIT_BUG
) &&
5892 tg3_40bit_overflow_test(tp
, mapping
, len
))
5893 would_hit_hwbug
= 1;
5895 if (tp
->tg3_flags3
& TG3_FLG3_5701_DMA_BUG
)
5896 would_hit_hwbug
= 1;
5898 tg3_set_txd(tnapi
, entry
, mapping
, len
, base_flags
,
5899 (skb_shinfo(skb
)->nr_frags
== 0) | (mss
<< 1));
5901 entry
= NEXT_TX(entry
);
5903 /* Now loop through additional data fragments, and queue them. */
5904 if (skb_shinfo(skb
)->nr_frags
> 0) {
5905 last
= skb_shinfo(skb
)->nr_frags
- 1;
5906 for (i
= 0; i
<= last
; i
++) {
5907 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
5910 mapping
= pci_map_page(tp
->pdev
,
5913 len
, PCI_DMA_TODEVICE
);
5915 tnapi
->tx_buffers
[entry
].skb
= NULL
;
5916 dma_unmap_addr_set(&tnapi
->tx_buffers
[entry
], mapping
,
5918 if (pci_dma_mapping_error(tp
->pdev
, mapping
))
5921 if ((tp
->tg3_flags3
& TG3_FLG3_SHORT_DMA_BUG
) &&
5923 would_hit_hwbug
= 1;
5925 if ((tp
->tg3_flags3
& TG3_FLG3_4G_DMA_BNDRY_BUG
) &&
5926 tg3_4g_overflow_test(mapping
, len
))
5927 would_hit_hwbug
= 1;
5929 if ((tp
->tg3_flags3
& TG3_FLG3_40BIT_DMA_LIMIT_BUG
) &&
5930 tg3_40bit_overflow_test(tp
, mapping
, len
))
5931 would_hit_hwbug
= 1;
5933 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
5934 tg3_set_txd(tnapi
, entry
, mapping
, len
,
5935 base_flags
, (i
== last
)|(mss
<< 1));
5937 tg3_set_txd(tnapi
, entry
, mapping
, len
,
5938 base_flags
, (i
== last
));
5940 entry
= NEXT_TX(entry
);
5944 if (would_hit_hwbug
) {
5945 u32 last_plus_one
= entry
;
5948 start
= entry
- 1 - skb_shinfo(skb
)->nr_frags
;
5949 start
&= (TG3_TX_RING_SIZE
- 1);
5951 /* If the workaround fails due to memory/mapping
5952 * failure, silently drop this packet.
5954 if (tigon3_dma_hwbug_workaround(tnapi
, skb
, last_plus_one
,
5955 &start
, base_flags
, mss
))
5961 /* Packets are ready, update Tx producer idx local and on card. */
5962 tw32_tx_mbox(tnapi
->prodmbox
, entry
);
5964 tnapi
->tx_prod
= entry
;
5965 if (unlikely(tg3_tx_avail(tnapi
) <= (MAX_SKB_FRAGS
+ 1))) {
5966 netif_tx_stop_queue(txq
);
5968 /* netif_tx_stop_queue() must be done before checking
5969 * checking tx index in tg3_tx_avail() below, because in
5970 * tg3_tx(), we update tx index before checking for
5971 * netif_tx_queue_stopped().
5974 if (tg3_tx_avail(tnapi
) > TG3_TX_WAKEUP_THRESH(tnapi
))
5975 netif_tx_wake_queue(txq
);
5981 return NETDEV_TX_OK
;
5985 entry
= tnapi
->tx_prod
;
5986 tnapi
->tx_buffers
[entry
].skb
= NULL
;
5987 pci_unmap_single(tp
->pdev
,
5988 dma_unmap_addr(&tnapi
->tx_buffers
[entry
], mapping
),
5991 for (i
= 0; i
<= last
; i
++) {
5992 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
5993 entry
= NEXT_TX(entry
);
5995 pci_unmap_page(tp
->pdev
,
5996 dma_unmap_addr(&tnapi
->tx_buffers
[entry
],
5998 frag
->size
, PCI_DMA_TODEVICE
);
6002 return NETDEV_TX_OK
;
6005 static inline void tg3_set_mtu(struct net_device
*dev
, struct tg3
*tp
,
6010 if (new_mtu
> ETH_DATA_LEN
) {
6011 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) {
6012 tp
->tg3_flags2
&= ~TG3_FLG2_TSO_CAPABLE
;
6013 ethtool_op_set_tso(dev
, 0);
6015 tp
->tg3_flags
|= TG3_FLAG_JUMBO_RING_ENABLE
;
6018 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)
6019 tp
->tg3_flags2
|= TG3_FLG2_TSO_CAPABLE
;
6020 tp
->tg3_flags
&= ~TG3_FLAG_JUMBO_RING_ENABLE
;
6024 static int tg3_change_mtu(struct net_device
*dev
, int new_mtu
)
6026 struct tg3
*tp
= netdev_priv(dev
);
6029 if (new_mtu
< TG3_MIN_MTU
|| new_mtu
> TG3_MAX_MTU(tp
))
6032 if (!netif_running(dev
)) {
6033 /* We'll just catch it later when the
6036 tg3_set_mtu(dev
, tp
, new_mtu
);
6044 tg3_full_lock(tp
, 1);
6046 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
6048 tg3_set_mtu(dev
, tp
, new_mtu
);
6050 err
= tg3_restart_hw(tp
, 0);
6053 tg3_netif_start(tp
);
6055 tg3_full_unlock(tp
);
6063 static void tg3_rx_prodring_free(struct tg3
*tp
,
6064 struct tg3_rx_prodring_set
*tpr
)
6068 if (tpr
!= &tp
->napi
[0].prodring
) {
6069 for (i
= tpr
->rx_std_cons_idx
; i
!= tpr
->rx_std_prod_idx
;
6070 i
= (i
+ 1) & tp
->rx_std_ring_mask
)
6071 tg3_rx_skb_free(tp
, &tpr
->rx_std_buffers
[i
],
6074 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) {
6075 for (i
= tpr
->rx_jmb_cons_idx
;
6076 i
!= tpr
->rx_jmb_prod_idx
;
6077 i
= (i
+ 1) & tp
->rx_jmb_ring_mask
) {
6078 tg3_rx_skb_free(tp
, &tpr
->rx_jmb_buffers
[i
],
6086 for (i
= 0; i
<= tp
->rx_std_ring_mask
; i
++)
6087 tg3_rx_skb_free(tp
, &tpr
->rx_std_buffers
[i
],
6090 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) {
6091 for (i
= 0; i
<= tp
->rx_jmb_ring_mask
; i
++)
6092 tg3_rx_skb_free(tp
, &tpr
->rx_jmb_buffers
[i
],
6097 /* Initialize rx rings for packet processing.
6099 * The chip has been shut down and the driver detached from
6100 * the networking, so no interrupts or new tx packets will
6101 * end up in the driver. tp->{tx,}lock are held and thus
6104 static int tg3_rx_prodring_alloc(struct tg3
*tp
,
6105 struct tg3_rx_prodring_set
*tpr
)
6107 u32 i
, rx_pkt_dma_sz
;
6109 tpr
->rx_std_cons_idx
= 0;
6110 tpr
->rx_std_prod_idx
= 0;
6111 tpr
->rx_jmb_cons_idx
= 0;
6112 tpr
->rx_jmb_prod_idx
= 0;
6114 if (tpr
!= &tp
->napi
[0].prodring
) {
6115 memset(&tpr
->rx_std_buffers
[0], 0,
6116 TG3_RX_STD_BUFF_RING_SIZE(tp
));
6117 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
)
6118 memset(&tpr
->rx_jmb_buffers
[0], 0,
6119 TG3_RX_JMB_BUFF_RING_SIZE(tp
));
6123 /* Zero out all descriptors. */
6124 memset(tpr
->rx_std
, 0, TG3_RX_STD_RING_BYTES(tp
));
6126 rx_pkt_dma_sz
= TG3_RX_STD_DMA_SZ
;
6127 if ((tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) &&
6128 tp
->dev
->mtu
> ETH_DATA_LEN
)
6129 rx_pkt_dma_sz
= TG3_RX_JMB_DMA_SZ
;
6130 tp
->rx_pkt_map_sz
= TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz
);
6132 /* Initialize invariants of the rings, we only set this
6133 * stuff once. This works because the card does not
6134 * write into the rx buffer posting rings.
6136 for (i
= 0; i
<= tp
->rx_std_ring_mask
; i
++) {
6137 struct tg3_rx_buffer_desc
*rxd
;
6139 rxd
= &tpr
->rx_std
[i
];
6140 rxd
->idx_len
= rx_pkt_dma_sz
<< RXD_LEN_SHIFT
;
6141 rxd
->type_flags
= (RXD_FLAG_END
<< RXD_FLAGS_SHIFT
);
6142 rxd
->opaque
= (RXD_OPAQUE_RING_STD
|
6143 (i
<< RXD_OPAQUE_INDEX_SHIFT
));
6146 /* Now allocate fresh SKBs for each rx ring. */
6147 for (i
= 0; i
< tp
->rx_pending
; i
++) {
6148 if (tg3_alloc_rx_skb(tp
, tpr
, RXD_OPAQUE_RING_STD
, i
) < 0) {
6149 netdev_warn(tp
->dev
,
6150 "Using a smaller RX standard ring. Only "
6151 "%d out of %d buffers were allocated "
6152 "successfully\n", i
, tp
->rx_pending
);
6160 if (!(tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
))
6163 memset(tpr
->rx_jmb
, 0, TG3_RX_JMB_RING_BYTES(tp
));
6165 if (!(tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
))
6168 for (i
= 0; i
<= tp
->rx_jmb_ring_mask
; i
++) {
6169 struct tg3_rx_buffer_desc
*rxd
;
6171 rxd
= &tpr
->rx_jmb
[i
].std
;
6172 rxd
->idx_len
= TG3_RX_JMB_DMA_SZ
<< RXD_LEN_SHIFT
;
6173 rxd
->type_flags
= (RXD_FLAG_END
<< RXD_FLAGS_SHIFT
) |
6175 rxd
->opaque
= (RXD_OPAQUE_RING_JUMBO
|
6176 (i
<< RXD_OPAQUE_INDEX_SHIFT
));
6179 for (i
= 0; i
< tp
->rx_jumbo_pending
; i
++) {
6180 if (tg3_alloc_rx_skb(tp
, tpr
, RXD_OPAQUE_RING_JUMBO
, i
) < 0) {
6181 netdev_warn(tp
->dev
,
6182 "Using a smaller RX jumbo ring. Only %d "
6183 "out of %d buffers were allocated "
6184 "successfully\n", i
, tp
->rx_jumbo_pending
);
6187 tp
->rx_jumbo_pending
= i
;
6196 tg3_rx_prodring_free(tp
, tpr
);
6200 static void tg3_rx_prodring_fini(struct tg3
*tp
,
6201 struct tg3_rx_prodring_set
*tpr
)
6203 kfree(tpr
->rx_std_buffers
);
6204 tpr
->rx_std_buffers
= NULL
;
6205 kfree(tpr
->rx_jmb_buffers
);
6206 tpr
->rx_jmb_buffers
= NULL
;
6208 pci_free_consistent(tp
->pdev
, TG3_RX_STD_RING_BYTES(tp
),
6209 tpr
->rx_std
, tpr
->rx_std_mapping
);
6213 pci_free_consistent(tp
->pdev
, TG3_RX_JMB_RING_BYTES(tp
),
6214 tpr
->rx_jmb
, tpr
->rx_jmb_mapping
);
6219 static int tg3_rx_prodring_init(struct tg3
*tp
,
6220 struct tg3_rx_prodring_set
*tpr
)
6222 tpr
->rx_std_buffers
= kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp
),
6224 if (!tpr
->rx_std_buffers
)
6227 tpr
->rx_std
= pci_alloc_consistent(tp
->pdev
, TG3_RX_STD_RING_BYTES(tp
),
6228 &tpr
->rx_std_mapping
);
6232 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) {
6233 tpr
->rx_jmb_buffers
= kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp
),
6235 if (!tpr
->rx_jmb_buffers
)
6238 tpr
->rx_jmb
= pci_alloc_consistent(tp
->pdev
,
6239 TG3_RX_JMB_RING_BYTES(tp
),
6240 &tpr
->rx_jmb_mapping
);
6248 tg3_rx_prodring_fini(tp
, tpr
);
6252 /* Free up pending packets in all rx/tx rings.
6254 * The chip has been shut down and the driver detached from
6255 * the networking, so no interrupts or new tx packets will
6256 * end up in the driver. tp->{tx,}lock is not held and we are not
6257 * in an interrupt context and thus may sleep.
6259 static void tg3_free_rings(struct tg3
*tp
)
6263 for (j
= 0; j
< tp
->irq_cnt
; j
++) {
6264 struct tg3_napi
*tnapi
= &tp
->napi
[j
];
6266 tg3_rx_prodring_free(tp
, &tnapi
->prodring
);
6268 if (!tnapi
->tx_buffers
)
6271 for (i
= 0; i
< TG3_TX_RING_SIZE
; ) {
6272 struct ring_info
*txp
;
6273 struct sk_buff
*skb
;
6276 txp
= &tnapi
->tx_buffers
[i
];
6284 pci_unmap_single(tp
->pdev
,
6285 dma_unmap_addr(txp
, mapping
),
6292 for (k
= 0; k
< skb_shinfo(skb
)->nr_frags
; k
++) {
6293 txp
= &tnapi
->tx_buffers
[i
& (TG3_TX_RING_SIZE
- 1)];
6294 pci_unmap_page(tp
->pdev
,
6295 dma_unmap_addr(txp
, mapping
),
6296 skb_shinfo(skb
)->frags
[k
].size
,
6301 dev_kfree_skb_any(skb
);
6306 /* Initialize tx/rx rings for packet processing.
6308 * The chip has been shut down and the driver detached from
6309 * the networking, so no interrupts or new tx packets will
6310 * end up in the driver. tp->{tx,}lock are held and thus
6313 static int tg3_init_rings(struct tg3
*tp
)
6317 /* Free up all the SKBs. */
6320 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
6321 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
6323 tnapi
->last_tag
= 0;
6324 tnapi
->last_irq_tag
= 0;
6325 tnapi
->hw_status
->status
= 0;
6326 tnapi
->hw_status
->status_tag
= 0;
6327 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
6332 memset(tnapi
->tx_ring
, 0, TG3_TX_RING_BYTES
);
6334 tnapi
->rx_rcb_ptr
= 0;
6336 memset(tnapi
->rx_rcb
, 0, TG3_RX_RCB_RING_BYTES(tp
));
6338 if (tg3_rx_prodring_alloc(tp
, &tnapi
->prodring
)) {
6348 * Must not be invoked with interrupt sources disabled and
6349 * the hardware shutdown down.
6351 static void tg3_free_consistent(struct tg3
*tp
)
6355 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
6356 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
6358 if (tnapi
->tx_ring
) {
6359 pci_free_consistent(tp
->pdev
, TG3_TX_RING_BYTES
,
6360 tnapi
->tx_ring
, tnapi
->tx_desc_mapping
);
6361 tnapi
->tx_ring
= NULL
;
6364 kfree(tnapi
->tx_buffers
);
6365 tnapi
->tx_buffers
= NULL
;
6367 if (tnapi
->rx_rcb
) {
6368 pci_free_consistent(tp
->pdev
, TG3_RX_RCB_RING_BYTES(tp
),
6370 tnapi
->rx_rcb_mapping
);
6371 tnapi
->rx_rcb
= NULL
;
6374 tg3_rx_prodring_fini(tp
, &tnapi
->prodring
);
6376 if (tnapi
->hw_status
) {
6377 pci_free_consistent(tp
->pdev
, TG3_HW_STATUS_SIZE
,
6379 tnapi
->status_mapping
);
6380 tnapi
->hw_status
= NULL
;
6385 pci_free_consistent(tp
->pdev
, sizeof(struct tg3_hw_stats
),
6386 tp
->hw_stats
, tp
->stats_mapping
);
6387 tp
->hw_stats
= NULL
;
6392 * Must not be invoked with interrupt sources disabled and
6393 * the hardware shutdown down. Can sleep.
6395 static int tg3_alloc_consistent(struct tg3
*tp
)
6399 tp
->hw_stats
= pci_alloc_consistent(tp
->pdev
,
6400 sizeof(struct tg3_hw_stats
),
6401 &tp
->stats_mapping
);
6405 memset(tp
->hw_stats
, 0, sizeof(struct tg3_hw_stats
));
6407 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
6408 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
6409 struct tg3_hw_status
*sblk
;
6411 tnapi
->hw_status
= pci_alloc_consistent(tp
->pdev
,
6413 &tnapi
->status_mapping
);
6414 if (!tnapi
->hw_status
)
6417 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
6418 sblk
= tnapi
->hw_status
;
6420 if (tg3_rx_prodring_init(tp
, &tnapi
->prodring
))
6423 /* If multivector TSS is enabled, vector 0 does not handle
6424 * tx interrupts. Don't allocate any resources for it.
6426 if ((!i
&& !(tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)) ||
6427 (i
&& (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
))) {
6428 tnapi
->tx_buffers
= kzalloc(sizeof(struct ring_info
) *
6431 if (!tnapi
->tx_buffers
)
6434 tnapi
->tx_ring
= pci_alloc_consistent(tp
->pdev
,
6436 &tnapi
->tx_desc_mapping
);
6437 if (!tnapi
->tx_ring
)
6442 * When RSS is enabled, the status block format changes
6443 * slightly. The "rx_jumbo_consumer", "reserved",
6444 * and "rx_mini_consumer" members get mapped to the
6445 * other three rx return ring producer indexes.
6449 tnapi
->rx_rcb_prod_idx
= &sblk
->idx
[0].rx_producer
;
6452 tnapi
->rx_rcb_prod_idx
= &sblk
->rx_jumbo_consumer
;
6455 tnapi
->rx_rcb_prod_idx
= &sblk
->reserved
;
6458 tnapi
->rx_rcb_prod_idx
= &sblk
->rx_mini_consumer
;
6463 * If multivector RSS is enabled, vector 0 does not handle
6464 * rx or tx interrupts. Don't allocate any resources for it.
6466 if (!i
&& (tp
->tg3_flags3
& TG3_FLG3_ENABLE_RSS
))
6469 tnapi
->rx_rcb
= pci_alloc_consistent(tp
->pdev
,
6470 TG3_RX_RCB_RING_BYTES(tp
),
6471 &tnapi
->rx_rcb_mapping
);
6475 memset(tnapi
->rx_rcb
, 0, TG3_RX_RCB_RING_BYTES(tp
));
6481 tg3_free_consistent(tp
);
6485 #define MAX_WAIT_CNT 1000
6487 /* To stop a block, clear the enable bit and poll till it
6488 * clears. tp->lock is held.
6490 static int tg3_stop_block(struct tg3
*tp
, unsigned long ofs
, u32 enable_bit
, int silent
)
6495 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
6502 /* We can't enable/disable these bits of the
6503 * 5705/5750, just say success.
6516 for (i
= 0; i
< MAX_WAIT_CNT
; i
++) {
6519 if ((val
& enable_bit
) == 0)
6523 if (i
== MAX_WAIT_CNT
&& !silent
) {
6524 dev_err(&tp
->pdev
->dev
,
6525 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6533 /* tp->lock is held. */
6534 static int tg3_abort_hw(struct tg3
*tp
, int silent
)
6538 tg3_disable_ints(tp
);
6540 tp
->rx_mode
&= ~RX_MODE_ENABLE
;
6541 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
6544 err
= tg3_stop_block(tp
, RCVBDI_MODE
, RCVBDI_MODE_ENABLE
, silent
);
6545 err
|= tg3_stop_block(tp
, RCVLPC_MODE
, RCVLPC_MODE_ENABLE
, silent
);
6546 err
|= tg3_stop_block(tp
, RCVLSC_MODE
, RCVLSC_MODE_ENABLE
, silent
);
6547 err
|= tg3_stop_block(tp
, RCVDBDI_MODE
, RCVDBDI_MODE_ENABLE
, silent
);
6548 err
|= tg3_stop_block(tp
, RCVDCC_MODE
, RCVDCC_MODE_ENABLE
, silent
);
6549 err
|= tg3_stop_block(tp
, RCVCC_MODE
, RCVCC_MODE_ENABLE
, silent
);
6551 err
|= tg3_stop_block(tp
, SNDBDS_MODE
, SNDBDS_MODE_ENABLE
, silent
);
6552 err
|= tg3_stop_block(tp
, SNDBDI_MODE
, SNDBDI_MODE_ENABLE
, silent
);
6553 err
|= tg3_stop_block(tp
, SNDDATAI_MODE
, SNDDATAI_MODE_ENABLE
, silent
);
6554 err
|= tg3_stop_block(tp
, RDMAC_MODE
, RDMAC_MODE_ENABLE
, silent
);
6555 err
|= tg3_stop_block(tp
, SNDDATAC_MODE
, SNDDATAC_MODE_ENABLE
, silent
);
6556 err
|= tg3_stop_block(tp
, DMAC_MODE
, DMAC_MODE_ENABLE
, silent
);
6557 err
|= tg3_stop_block(tp
, SNDBDC_MODE
, SNDBDC_MODE_ENABLE
, silent
);
6559 tp
->mac_mode
&= ~MAC_MODE_TDE_ENABLE
;
6560 tw32_f(MAC_MODE
, tp
->mac_mode
);
6563 tp
->tx_mode
&= ~TX_MODE_ENABLE
;
6564 tw32_f(MAC_TX_MODE
, tp
->tx_mode
);
6566 for (i
= 0; i
< MAX_WAIT_CNT
; i
++) {
6568 if (!(tr32(MAC_TX_MODE
) & TX_MODE_ENABLE
))
6571 if (i
>= MAX_WAIT_CNT
) {
6572 dev_err(&tp
->pdev
->dev
,
6573 "%s timed out, TX_MODE_ENABLE will not clear "
6574 "MAC_TX_MODE=%08x\n", __func__
, tr32(MAC_TX_MODE
));
6578 err
|= tg3_stop_block(tp
, HOSTCC_MODE
, HOSTCC_MODE_ENABLE
, silent
);
6579 err
|= tg3_stop_block(tp
, WDMAC_MODE
, WDMAC_MODE_ENABLE
, silent
);
6580 err
|= tg3_stop_block(tp
, MBFREE_MODE
, MBFREE_MODE_ENABLE
, silent
);
6582 tw32(FTQ_RESET
, 0xffffffff);
6583 tw32(FTQ_RESET
, 0x00000000);
6585 err
|= tg3_stop_block(tp
, BUFMGR_MODE
, BUFMGR_MODE_ENABLE
, silent
);
6586 err
|= tg3_stop_block(tp
, MEMARB_MODE
, MEMARB_MODE_ENABLE
, silent
);
6588 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
6589 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
6590 if (tnapi
->hw_status
)
6591 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
6594 memset(tp
->hw_stats
, 0, sizeof(struct tg3_hw_stats
));
6599 static void tg3_ape_send_event(struct tg3
*tp
, u32 event
)
6604 /* NCSI does not support APE events */
6605 if (tp
->tg3_flags3
& TG3_FLG3_APE_HAS_NCSI
)
6608 apedata
= tg3_ape_read32(tp
, TG3_APE_SEG_SIG
);
6609 if (apedata
!= APE_SEG_SIG_MAGIC
)
6612 apedata
= tg3_ape_read32(tp
, TG3_APE_FW_STATUS
);
6613 if (!(apedata
& APE_FW_STATUS_READY
))
6616 /* Wait for up to 1 millisecond for APE to service previous event. */
6617 for (i
= 0; i
< 10; i
++) {
6618 if (tg3_ape_lock(tp
, TG3_APE_LOCK_MEM
))
6621 apedata
= tg3_ape_read32(tp
, TG3_APE_EVENT_STATUS
);
6623 if (!(apedata
& APE_EVENT_STATUS_EVENT_PENDING
))
6624 tg3_ape_write32(tp
, TG3_APE_EVENT_STATUS
,
6625 event
| APE_EVENT_STATUS_EVENT_PENDING
);
6627 tg3_ape_unlock(tp
, TG3_APE_LOCK_MEM
);
6629 if (!(apedata
& APE_EVENT_STATUS_EVENT_PENDING
))
6635 if (!(apedata
& APE_EVENT_STATUS_EVENT_PENDING
))
6636 tg3_ape_write32(tp
, TG3_APE_EVENT
, APE_EVENT_1
);
6639 static void tg3_ape_driver_state_change(struct tg3
*tp
, int kind
)
6644 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
))
6648 case RESET_KIND_INIT
:
6649 tg3_ape_write32(tp
, TG3_APE_HOST_SEG_SIG
,
6650 APE_HOST_SEG_SIG_MAGIC
);
6651 tg3_ape_write32(tp
, TG3_APE_HOST_SEG_LEN
,
6652 APE_HOST_SEG_LEN_MAGIC
);
6653 apedata
= tg3_ape_read32(tp
, TG3_APE_HOST_INIT_COUNT
);
6654 tg3_ape_write32(tp
, TG3_APE_HOST_INIT_COUNT
, ++apedata
);
6655 tg3_ape_write32(tp
, TG3_APE_HOST_DRIVER_ID
,
6656 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM
, TG3_MIN_NUM
));
6657 tg3_ape_write32(tp
, TG3_APE_HOST_BEHAVIOR
,
6658 APE_HOST_BEHAV_NO_PHYLOCK
);
6659 tg3_ape_write32(tp
, TG3_APE_HOST_DRVR_STATE
,
6660 TG3_APE_HOST_DRVR_STATE_START
);
6662 event
= APE_EVENT_STATUS_STATE_START
;
6664 case RESET_KIND_SHUTDOWN
:
6665 /* With the interface we are currently using,
6666 * APE does not track driver state. Wiping
6667 * out the HOST SEGMENT SIGNATURE forces
6668 * the APE to assume OS absent status.
6670 tg3_ape_write32(tp
, TG3_APE_HOST_SEG_SIG
, 0x0);
6672 if (device_may_wakeup(&tp
->pdev
->dev
) &&
6673 (tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
)) {
6674 tg3_ape_write32(tp
, TG3_APE_HOST_WOL_SPEED
,
6675 TG3_APE_HOST_WOL_SPEED_AUTO
);
6676 apedata
= TG3_APE_HOST_DRVR_STATE_WOL
;
6678 apedata
= TG3_APE_HOST_DRVR_STATE_UNLOAD
;
6680 tg3_ape_write32(tp
, TG3_APE_HOST_DRVR_STATE
, apedata
);
6682 event
= APE_EVENT_STATUS_STATE_UNLOAD
;
6684 case RESET_KIND_SUSPEND
:
6685 event
= APE_EVENT_STATUS_STATE_SUSPEND
;
6691 event
|= APE_EVENT_STATUS_DRIVER_EVNT
| APE_EVENT_STATUS_STATE_CHNGE
;
6693 tg3_ape_send_event(tp
, event
);
6696 /* tp->lock is held. */
6697 static void tg3_write_sig_pre_reset(struct tg3
*tp
, int kind
)
6699 tg3_write_mem(tp
, NIC_SRAM_FIRMWARE_MBOX
,
6700 NIC_SRAM_FIRMWARE_MBOX_MAGIC1
);
6702 if (tp
->tg3_flags2
& TG3_FLG2_ASF_NEW_HANDSHAKE
) {
6704 case RESET_KIND_INIT
:
6705 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6709 case RESET_KIND_SHUTDOWN
:
6710 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6714 case RESET_KIND_SUSPEND
:
6715 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6724 if (kind
== RESET_KIND_INIT
||
6725 kind
== RESET_KIND_SUSPEND
)
6726 tg3_ape_driver_state_change(tp
, kind
);
6729 /* tp->lock is held. */
6730 static void tg3_write_sig_post_reset(struct tg3
*tp
, int kind
)
6732 if (tp
->tg3_flags2
& TG3_FLG2_ASF_NEW_HANDSHAKE
) {
6734 case RESET_KIND_INIT
:
6735 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6736 DRV_STATE_START_DONE
);
6739 case RESET_KIND_SHUTDOWN
:
6740 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6741 DRV_STATE_UNLOAD_DONE
);
6749 if (kind
== RESET_KIND_SHUTDOWN
)
6750 tg3_ape_driver_state_change(tp
, kind
);
6753 /* tp->lock is held. */
6754 static void tg3_write_sig_legacy(struct tg3
*tp
, int kind
)
6756 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) {
6758 case RESET_KIND_INIT
:
6759 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6763 case RESET_KIND_SHUTDOWN
:
6764 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6768 case RESET_KIND_SUSPEND
:
6769 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6779 static int tg3_poll_fw(struct tg3
*tp
)
6784 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
6785 /* Wait up to 20ms for init done. */
6786 for (i
= 0; i
< 200; i
++) {
6787 if (tr32(VCPU_STATUS
) & VCPU_STATUS_INIT_DONE
)
6794 /* Wait for firmware initialization to complete. */
6795 for (i
= 0; i
< 100000; i
++) {
6796 tg3_read_mem(tp
, NIC_SRAM_FIRMWARE_MBOX
, &val
);
6797 if (val
== ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1
)
6802 /* Chip might not be fitted with firmware. Some Sun onboard
6803 * parts are configured like that. So don't signal the timeout
6804 * of the above loop as an error, but do report the lack of
6805 * running firmware once.
6808 !(tp
->tg3_flags2
& TG3_FLG2_NO_FWARE_REPORTED
)) {
6809 tp
->tg3_flags2
|= TG3_FLG2_NO_FWARE_REPORTED
;
6811 netdev_info(tp
->dev
, "No firmware running\n");
6814 if (tp
->pci_chip_rev_id
== CHIPREV_ID_57765_A0
) {
6815 /* The 57765 A0 needs a little more
6816 * time to do some important work.
6824 /* Save PCI command register before chip reset */
6825 static void tg3_save_pci_state(struct tg3
*tp
)
6827 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &tp
->pci_cmd
);
6830 /* Restore PCI state after chip reset */
6831 static void tg3_restore_pci_state(struct tg3
*tp
)
6835 /* Re-enable indirect register accesses. */
6836 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
6837 tp
->misc_host_ctrl
);
6839 /* Set MAX PCI retry to zero. */
6840 val
= (PCISTATE_ROM_ENABLE
| PCISTATE_ROM_RETRY_ENABLE
);
6841 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
&&
6842 (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
))
6843 val
|= PCISTATE_RETRY_SAME_DMA
;
6844 /* Allow reads and writes to the APE register and memory space. */
6845 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
6846 val
|= PCISTATE_ALLOW_APE_CTLSPC_WR
|
6847 PCISTATE_ALLOW_APE_SHMEM_WR
|
6848 PCISTATE_ALLOW_APE_PSPACE_WR
;
6849 pci_write_config_dword(tp
->pdev
, TG3PCI_PCISTATE
, val
);
6851 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, tp
->pci_cmd
);
6853 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5785
) {
6854 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)
6855 pcie_set_readrq(tp
->pdev
, 4096);
6857 pci_write_config_byte(tp
->pdev
, PCI_CACHE_LINE_SIZE
,
6858 tp
->pci_cacheline_sz
);
6859 pci_write_config_byte(tp
->pdev
, PCI_LATENCY_TIMER
,
6864 /* Make sure PCI-X relaxed ordering bit is clear. */
6865 if (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) {
6868 pci_read_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
6870 pcix_cmd
&= ~PCI_X_CMD_ERO
;
6871 pci_write_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
6875 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) {
6877 /* Chip reset on 5780 will reset MSI enable bit,
6878 * so need to restore it.
6880 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
6883 pci_read_config_word(tp
->pdev
,
6884 tp
->msi_cap
+ PCI_MSI_FLAGS
,
6886 pci_write_config_word(tp
->pdev
,
6887 tp
->msi_cap
+ PCI_MSI_FLAGS
,
6888 ctrl
| PCI_MSI_FLAGS_ENABLE
);
6889 val
= tr32(MSGINT_MODE
);
6890 tw32(MSGINT_MODE
, val
| MSGINT_MODE_ENABLE
);
6895 static void tg3_stop_fw(struct tg3
*);
6897 /* tp->lock is held. */
6898 static int tg3_chip_reset(struct tg3
*tp
)
6901 void (*write_op
)(struct tg3
*, u32
, u32
);
6906 tg3_ape_lock(tp
, TG3_APE_LOCK_GRC
);
6908 /* No matching tg3_nvram_unlock() after this because
6909 * chip reset below will undo the nvram lock.
6911 tp
->nvram_lock_cnt
= 0;
6913 /* GRC_MISC_CFG core clock reset will clear the memory
6914 * enable bit in PCI register 4 and the MSI enable bit
6915 * on some chips, so we save relevant registers here.
6917 tg3_save_pci_state(tp
);
6919 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
||
6920 (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
))
6921 tw32(GRC_FASTBOOT_PC
, 0);
6924 * We must avoid the readl() that normally takes place.
6925 * It locks machines, causes machine checks, and other
6926 * fun things. So, temporarily disable the 5701
6927 * hardware workaround, while we do the reset.
6929 write_op
= tp
->write32
;
6930 if (write_op
== tg3_write_flush_reg32
)
6931 tp
->write32
= tg3_write32
;
6933 /* Prevent the irq handler from reading or writing PCI registers
6934 * during chip reset when the memory enable bit in the PCI command
6935 * register may be cleared. The chip does not generate interrupt
6936 * at this time, but the irq handler may still be called due to irq
6937 * sharing or irqpoll.
6939 tp
->tg3_flags
|= TG3_FLAG_CHIP_RESETTING
;
6940 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
6941 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
6942 if (tnapi
->hw_status
) {
6943 tnapi
->hw_status
->status
= 0;
6944 tnapi
->hw_status
->status_tag
= 0;
6946 tnapi
->last_tag
= 0;
6947 tnapi
->last_irq_tag
= 0;
6951 for (i
= 0; i
< tp
->irq_cnt
; i
++)
6952 synchronize_irq(tp
->napi
[i
].irq_vec
);
6954 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
) {
6955 val
= tr32(TG3_PCIE_LNKCTL
) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN
;
6956 tw32(TG3_PCIE_LNKCTL
, val
| TG3_PCIE_LNKCTL_L1_PLL_PD_DIS
);
6960 val
= GRC_MISC_CFG_CORECLK_RESET
;
6962 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
6963 /* Force PCIe 1.0a mode */
6964 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5785
&&
6965 !(tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
) &&
6966 tr32(TG3_PCIE_PHY_TSTCTL
) ==
6967 (TG3_PCIE_PHY_TSTCTL_PCIE10
| TG3_PCIE_PHY_TSTCTL_PSCRAM
))
6968 tw32(TG3_PCIE_PHY_TSTCTL
, TG3_PCIE_PHY_TSTCTL_PSCRAM
);
6970 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
) {
6971 tw32(GRC_MISC_CFG
, (1 << 29));
6976 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
6977 tw32(VCPU_STATUS
, tr32(VCPU_STATUS
) | VCPU_STATUS_DRV_RESET
);
6978 tw32(GRC_VCPU_EXT_CTRL
,
6979 tr32(GRC_VCPU_EXT_CTRL
) & ~GRC_VCPU_EXT_CTRL_HALT_CPU
);
6982 /* Manage gphy power for all CPMU absent PCIe devices. */
6983 if ((tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
6984 !(tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
))
6985 val
|= GRC_MISC_CFG_KEEP_GPHY_POWER
;
6987 tw32(GRC_MISC_CFG
, val
);
6989 /* restore 5701 hardware bug workaround write method */
6990 tp
->write32
= write_op
;
6992 /* Unfortunately, we have to delay before the PCI read back.
6993 * Some 575X chips even will not respond to a PCI cfg access
6994 * when the reset command is given to the chip.
6996 * How do these hardware designers expect things to work
6997 * properly if the PCI write is posted for a long period
6998 * of time? It is always necessary to have some method by
6999 * which a register read back can occur to push the write
7000 * out which does the reset.
7002 * For most tg3 variants the trick below was working.
7007 /* Flush PCI posted writes. The normal MMIO registers
7008 * are inaccessible at this time so this is the only
7009 * way to make this reliably (actually, this is no longer
7010 * the case, see above). I tried to use indirect
7011 * register read/write but this upset some 5701 variants.
7013 pci_read_config_dword(tp
->pdev
, PCI_COMMAND
, &val
);
7017 if ((tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) && tp
->pcie_cap
) {
7020 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5750_A0
) {
7024 /* Wait for link training to complete. */
7025 for (i
= 0; i
< 5000; i
++)
7028 pci_read_config_dword(tp
->pdev
, 0xc4, &cfg_val
);
7029 pci_write_config_dword(tp
->pdev
, 0xc4,
7030 cfg_val
| (1 << 15));
7033 /* Clear the "no snoop" and "relaxed ordering" bits. */
7034 pci_read_config_word(tp
->pdev
,
7035 tp
->pcie_cap
+ PCI_EXP_DEVCTL
,
7037 val16
&= ~(PCI_EXP_DEVCTL_RELAX_EN
|
7038 PCI_EXP_DEVCTL_NOSNOOP_EN
);
7040 * Older PCIe devices only support the 128 byte
7041 * MPS setting. Enforce the restriction.
7043 if (!(tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
))
7044 val16
&= ~PCI_EXP_DEVCTL_PAYLOAD
;
7045 pci_write_config_word(tp
->pdev
,
7046 tp
->pcie_cap
+ PCI_EXP_DEVCTL
,
7049 pcie_set_readrq(tp
->pdev
, 4096);
7051 /* Clear error status */
7052 pci_write_config_word(tp
->pdev
,
7053 tp
->pcie_cap
+ PCI_EXP_DEVSTA
,
7054 PCI_EXP_DEVSTA_CED
|
7055 PCI_EXP_DEVSTA_NFED
|
7056 PCI_EXP_DEVSTA_FED
|
7057 PCI_EXP_DEVSTA_URD
);
7060 tg3_restore_pci_state(tp
);
7062 tp
->tg3_flags
&= ~TG3_FLAG_CHIP_RESETTING
;
7065 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)
7066 val
= tr32(MEMARB_MODE
);
7067 tw32(MEMARB_MODE
, val
| MEMARB_MODE_ENABLE
);
7069 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5750_A3
) {
7071 tw32(0x5000, 0x400);
7074 tw32(GRC_MODE
, tp
->grc_mode
);
7076 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A0
) {
7079 tw32(0xc4, val
| (1 << 15));
7082 if ((tp
->nic_sram_data_cfg
& NIC_SRAM_DATA_CFG_MINI_PCI
) != 0 &&
7083 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
7084 tp
->pci_clock_ctrl
|= CLOCK_CTRL_CLKRUN_OENABLE
;
7085 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A0
)
7086 tp
->pci_clock_ctrl
|= CLOCK_CTRL_FORCE_CLKRUN
;
7087 tw32(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
);
7090 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) {
7091 tp
->mac_mode
= MAC_MODE_PORT_MODE_TBI
;
7092 tw32_f(MAC_MODE
, tp
->mac_mode
);
7093 } else if (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
) {
7094 tp
->mac_mode
= MAC_MODE_PORT_MODE_GMII
;
7095 tw32_f(MAC_MODE
, tp
->mac_mode
);
7096 } else if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
7097 tp
->mac_mode
&= (MAC_MODE_APE_TX_EN
| MAC_MODE_APE_RX_EN
);
7098 if (tp
->mac_mode
& MAC_MODE_APE_TX_EN
)
7099 tp
->mac_mode
|= MAC_MODE_TDE_ENABLE
;
7100 tw32_f(MAC_MODE
, tp
->mac_mode
);
7102 tw32_f(MAC_MODE
, 0);
7105 tg3_ape_unlock(tp
, TG3_APE_LOCK_GRC
);
7107 err
= tg3_poll_fw(tp
);
7113 if ((tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) &&
7114 tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
&&
7115 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5785
&&
7116 !(tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
)) {
7119 tw32(0x7c00, val
| (1 << 25));
7122 /* Reprobe ASF enable state. */
7123 tp
->tg3_flags
&= ~TG3_FLAG_ENABLE_ASF
;
7124 tp
->tg3_flags2
&= ~TG3_FLG2_ASF_NEW_HANDSHAKE
;
7125 tg3_read_mem(tp
, NIC_SRAM_DATA_SIG
, &val
);
7126 if (val
== NIC_SRAM_DATA_SIG_MAGIC
) {
7129 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG
, &nic_cfg
);
7130 if (nic_cfg
& NIC_SRAM_DATA_CFG_ASF_ENABLE
) {
7131 tp
->tg3_flags
|= TG3_FLAG_ENABLE_ASF
;
7132 tp
->last_event_jiffies
= jiffies
;
7133 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
7134 tp
->tg3_flags2
|= TG3_FLG2_ASF_NEW_HANDSHAKE
;
7141 /* tp->lock is held. */
7142 static void tg3_stop_fw(struct tg3
*tp
)
7144 if ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) &&
7145 !(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)) {
7146 /* Wait for RX cpu to ACK the previous event. */
7147 tg3_wait_for_event_ack(tp
);
7149 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_MBOX
, FWCMD_NICDRV_PAUSE_FW
);
7151 tg3_generate_fw_event(tp
);
7153 /* Wait for RX cpu to ACK this event. */
7154 tg3_wait_for_event_ack(tp
);
7158 /* tp->lock is held. */
7159 static int tg3_halt(struct tg3
*tp
, int kind
, int silent
)
7165 tg3_write_sig_pre_reset(tp
, kind
);
7167 tg3_abort_hw(tp
, silent
);
7168 err
= tg3_chip_reset(tp
);
7170 __tg3_set_mac_addr(tp
, 0);
7172 tg3_write_sig_legacy(tp
, kind
);
7173 tg3_write_sig_post_reset(tp
, kind
);
7181 #define RX_CPU_SCRATCH_BASE 0x30000
7182 #define RX_CPU_SCRATCH_SIZE 0x04000
7183 #define TX_CPU_SCRATCH_BASE 0x34000
7184 #define TX_CPU_SCRATCH_SIZE 0x04000
7186 /* tp->lock is held. */
7187 static int tg3_halt_cpu(struct tg3
*tp
, u32 offset
)
7191 BUG_ON(offset
== TX_CPU_BASE
&&
7192 (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
));
7194 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
7195 u32 val
= tr32(GRC_VCPU_EXT_CTRL
);
7197 tw32(GRC_VCPU_EXT_CTRL
, val
| GRC_VCPU_EXT_CTRL_HALT_CPU
);
7200 if (offset
== RX_CPU_BASE
) {
7201 for (i
= 0; i
< 10000; i
++) {
7202 tw32(offset
+ CPU_STATE
, 0xffffffff);
7203 tw32(offset
+ CPU_MODE
, CPU_MODE_HALT
);
7204 if (tr32(offset
+ CPU_MODE
) & CPU_MODE_HALT
)
7208 tw32(offset
+ CPU_STATE
, 0xffffffff);
7209 tw32_f(offset
+ CPU_MODE
, CPU_MODE_HALT
);
7212 for (i
= 0; i
< 10000; i
++) {
7213 tw32(offset
+ CPU_STATE
, 0xffffffff);
7214 tw32(offset
+ CPU_MODE
, CPU_MODE_HALT
);
7215 if (tr32(offset
+ CPU_MODE
) & CPU_MODE_HALT
)
7221 netdev_err(tp
->dev
, "%s timed out, %s CPU\n",
7222 __func__
, offset
== RX_CPU_BASE
? "RX" : "TX");
7226 /* Clear firmware's nvram arbitration. */
7227 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
)
7228 tw32(NVRAM_SWARB
, SWARB_REQ_CLR0
);
7233 unsigned int fw_base
;
7234 unsigned int fw_len
;
7235 const __be32
*fw_data
;
7238 /* tp->lock is held. */
7239 static int tg3_load_firmware_cpu(struct tg3
*tp
, u32 cpu_base
, u32 cpu_scratch_base
,
7240 int cpu_scratch_size
, struct fw_info
*info
)
7242 int err
, lock_err
, i
;
7243 void (*write_op
)(struct tg3
*, u32
, u32
);
7245 if (cpu_base
== TX_CPU_BASE
&&
7246 (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
7248 "%s: Trying to load TX cpu firmware which is 5705\n",
7253 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
7254 write_op
= tg3_write_mem
;
7256 write_op
= tg3_write_indirect_reg32
;
7258 /* It is possible that bootcode is still loading at this point.
7259 * Get the nvram lock first before halting the cpu.
7261 lock_err
= tg3_nvram_lock(tp
);
7262 err
= tg3_halt_cpu(tp
, cpu_base
);
7264 tg3_nvram_unlock(tp
);
7268 for (i
= 0; i
< cpu_scratch_size
; i
+= sizeof(u32
))
7269 write_op(tp
, cpu_scratch_base
+ i
, 0);
7270 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
7271 tw32(cpu_base
+ CPU_MODE
, tr32(cpu_base
+CPU_MODE
)|CPU_MODE_HALT
);
7272 for (i
= 0; i
< (info
->fw_len
/ sizeof(u32
)); i
++)
7273 write_op(tp
, (cpu_scratch_base
+
7274 (info
->fw_base
& 0xffff) +
7276 be32_to_cpu(info
->fw_data
[i
]));
7284 /* tp->lock is held. */
7285 static int tg3_load_5701_a0_firmware_fix(struct tg3
*tp
)
7287 struct fw_info info
;
7288 const __be32
*fw_data
;
7291 fw_data
= (void *)tp
->fw
->data
;
7293 /* Firmware blob starts with version numbers, followed by
7294 start address and length. We are setting complete length.
7295 length = end_address_of_bss - start_address_of_text.
7296 Remainder is the blob to be loaded contiguously
7297 from start address. */
7299 info
.fw_base
= be32_to_cpu(fw_data
[1]);
7300 info
.fw_len
= tp
->fw
->size
- 12;
7301 info
.fw_data
= &fw_data
[3];
7303 err
= tg3_load_firmware_cpu(tp
, RX_CPU_BASE
,
7304 RX_CPU_SCRATCH_BASE
, RX_CPU_SCRATCH_SIZE
,
7309 err
= tg3_load_firmware_cpu(tp
, TX_CPU_BASE
,
7310 TX_CPU_SCRATCH_BASE
, TX_CPU_SCRATCH_SIZE
,
7315 /* Now startup only the RX cpu. */
7316 tw32(RX_CPU_BASE
+ CPU_STATE
, 0xffffffff);
7317 tw32_f(RX_CPU_BASE
+ CPU_PC
, info
.fw_base
);
7319 for (i
= 0; i
< 5; i
++) {
7320 if (tr32(RX_CPU_BASE
+ CPU_PC
) == info
.fw_base
)
7322 tw32(RX_CPU_BASE
+ CPU_STATE
, 0xffffffff);
7323 tw32(RX_CPU_BASE
+ CPU_MODE
, CPU_MODE_HALT
);
7324 tw32_f(RX_CPU_BASE
+ CPU_PC
, info
.fw_base
);
7328 netdev_err(tp
->dev
, "%s fails to set RX CPU PC, is %08x "
7329 "should be %08x\n", __func__
,
7330 tr32(RX_CPU_BASE
+ CPU_PC
), info
.fw_base
);
7333 tw32(RX_CPU_BASE
+ CPU_STATE
, 0xffffffff);
7334 tw32_f(RX_CPU_BASE
+ CPU_MODE
, 0x00000000);
7339 /* 5705 needs a special version of the TSO firmware. */
7341 /* tp->lock is held. */
7342 static int tg3_load_tso_firmware(struct tg3
*tp
)
7344 struct fw_info info
;
7345 const __be32
*fw_data
;
7346 unsigned long cpu_base
, cpu_scratch_base
, cpu_scratch_size
;
7349 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
7352 fw_data
= (void *)tp
->fw
->data
;
7354 /* Firmware blob starts with version numbers, followed by
7355 start address and length. We are setting complete length.
7356 length = end_address_of_bss - start_address_of_text.
7357 Remainder is the blob to be loaded contiguously
7358 from start address. */
7360 info
.fw_base
= be32_to_cpu(fw_data
[1]);
7361 cpu_scratch_size
= tp
->fw_len
;
7362 info
.fw_len
= tp
->fw
->size
- 12;
7363 info
.fw_data
= &fw_data
[3];
7365 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
7366 cpu_base
= RX_CPU_BASE
;
7367 cpu_scratch_base
= NIC_SRAM_MBUF_POOL_BASE5705
;
7369 cpu_base
= TX_CPU_BASE
;
7370 cpu_scratch_base
= TX_CPU_SCRATCH_BASE
;
7371 cpu_scratch_size
= TX_CPU_SCRATCH_SIZE
;
7374 err
= tg3_load_firmware_cpu(tp
, cpu_base
,
7375 cpu_scratch_base
, cpu_scratch_size
,
7380 /* Now startup the cpu. */
7381 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
7382 tw32_f(cpu_base
+ CPU_PC
, info
.fw_base
);
7384 for (i
= 0; i
< 5; i
++) {
7385 if (tr32(cpu_base
+ CPU_PC
) == info
.fw_base
)
7387 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
7388 tw32(cpu_base
+ CPU_MODE
, CPU_MODE_HALT
);
7389 tw32_f(cpu_base
+ CPU_PC
, info
.fw_base
);
7394 "%s fails to set CPU PC, is %08x should be %08x\n",
7395 __func__
, tr32(cpu_base
+ CPU_PC
), info
.fw_base
);
7398 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
7399 tw32_f(cpu_base
+ CPU_MODE
, 0x00000000);
7404 static int tg3_set_mac_addr(struct net_device
*dev
, void *p
)
7406 struct tg3
*tp
= netdev_priv(dev
);
7407 struct sockaddr
*addr
= p
;
7408 int err
= 0, skip_mac_1
= 0;
7410 if (!is_valid_ether_addr(addr
->sa_data
))
7413 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
7415 if (!netif_running(dev
))
7418 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) {
7419 u32 addr0_high
, addr0_low
, addr1_high
, addr1_low
;
7421 addr0_high
= tr32(MAC_ADDR_0_HIGH
);
7422 addr0_low
= tr32(MAC_ADDR_0_LOW
);
7423 addr1_high
= tr32(MAC_ADDR_1_HIGH
);
7424 addr1_low
= tr32(MAC_ADDR_1_LOW
);
7426 /* Skip MAC addr 1 if ASF is using it. */
7427 if ((addr0_high
!= addr1_high
|| addr0_low
!= addr1_low
) &&
7428 !(addr1_high
== 0 && addr1_low
== 0))
7431 spin_lock_bh(&tp
->lock
);
7432 __tg3_set_mac_addr(tp
, skip_mac_1
);
7433 spin_unlock_bh(&tp
->lock
);
7438 /* tp->lock is held. */
7439 static void tg3_set_bdinfo(struct tg3
*tp
, u32 bdinfo_addr
,
7440 dma_addr_t mapping
, u32 maxlen_flags
,
7444 (bdinfo_addr
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_HIGH
),
7445 ((u64
) mapping
>> 32));
7447 (bdinfo_addr
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_LOW
),
7448 ((u64
) mapping
& 0xffffffff));
7450 (bdinfo_addr
+ TG3_BDINFO_MAXLEN_FLAGS
),
7453 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
7455 (bdinfo_addr
+ TG3_BDINFO_NIC_ADDR
),
7459 static void __tg3_set_rx_mode(struct net_device
*);
7460 static void __tg3_set_coalesce(struct tg3
*tp
, struct ethtool_coalesce
*ec
)
7464 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)) {
7465 tw32(HOSTCC_TXCOL_TICKS
, ec
->tx_coalesce_usecs
);
7466 tw32(HOSTCC_TXMAX_FRAMES
, ec
->tx_max_coalesced_frames
);
7467 tw32(HOSTCC_TXCOAL_MAXF_INT
, ec
->tx_max_coalesced_frames_irq
);
7469 tw32(HOSTCC_TXCOL_TICKS
, 0);
7470 tw32(HOSTCC_TXMAX_FRAMES
, 0);
7471 tw32(HOSTCC_TXCOAL_MAXF_INT
, 0);
7474 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_RSS
)) {
7475 tw32(HOSTCC_RXCOL_TICKS
, ec
->rx_coalesce_usecs
);
7476 tw32(HOSTCC_RXMAX_FRAMES
, ec
->rx_max_coalesced_frames
);
7477 tw32(HOSTCC_RXCOAL_MAXF_INT
, ec
->rx_max_coalesced_frames_irq
);
7479 tw32(HOSTCC_RXCOL_TICKS
, 0);
7480 tw32(HOSTCC_RXMAX_FRAMES
, 0);
7481 tw32(HOSTCC_RXCOAL_MAXF_INT
, 0);
7484 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
7485 u32 val
= ec
->stats_block_coalesce_usecs
;
7487 tw32(HOSTCC_RXCOAL_TICK_INT
, ec
->rx_coalesce_usecs_irq
);
7488 tw32(HOSTCC_TXCOAL_TICK_INT
, ec
->tx_coalesce_usecs_irq
);
7490 if (!netif_carrier_ok(tp
->dev
))
7493 tw32(HOSTCC_STAT_COAL_TICKS
, val
);
7496 for (i
= 0; i
< tp
->irq_cnt
- 1; i
++) {
7499 reg
= HOSTCC_RXCOL_TICKS_VEC1
+ i
* 0x18;
7500 tw32(reg
, ec
->rx_coalesce_usecs
);
7501 reg
= HOSTCC_RXMAX_FRAMES_VEC1
+ i
* 0x18;
7502 tw32(reg
, ec
->rx_max_coalesced_frames
);
7503 reg
= HOSTCC_RXCOAL_MAXF_INT_VEC1
+ i
* 0x18;
7504 tw32(reg
, ec
->rx_max_coalesced_frames_irq
);
7506 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
) {
7507 reg
= HOSTCC_TXCOL_TICKS_VEC1
+ i
* 0x18;
7508 tw32(reg
, ec
->tx_coalesce_usecs
);
7509 reg
= HOSTCC_TXMAX_FRAMES_VEC1
+ i
* 0x18;
7510 tw32(reg
, ec
->tx_max_coalesced_frames
);
7511 reg
= HOSTCC_TXCOAL_MAXF_INT_VEC1
+ i
* 0x18;
7512 tw32(reg
, ec
->tx_max_coalesced_frames_irq
);
7516 for (; i
< tp
->irq_max
- 1; i
++) {
7517 tw32(HOSTCC_RXCOL_TICKS_VEC1
+ i
* 0x18, 0);
7518 tw32(HOSTCC_RXMAX_FRAMES_VEC1
+ i
* 0x18, 0);
7519 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1
+ i
* 0x18, 0);
7521 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
) {
7522 tw32(HOSTCC_TXCOL_TICKS_VEC1
+ i
* 0x18, 0);
7523 tw32(HOSTCC_TXMAX_FRAMES_VEC1
+ i
* 0x18, 0);
7524 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1
+ i
* 0x18, 0);
7529 /* tp->lock is held. */
7530 static void tg3_rings_reset(struct tg3
*tp
)
7533 u32 stblk
, txrcb
, rxrcb
, limit
;
7534 struct tg3_napi
*tnapi
= &tp
->napi
[0];
7536 /* Disable all transmit rings but the first. */
7537 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
7538 limit
= NIC_SRAM_SEND_RCB
+ TG3_BDINFO_SIZE
* 16;
7539 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
7540 limit
= NIC_SRAM_SEND_RCB
+ TG3_BDINFO_SIZE
* 2;
7542 limit
= NIC_SRAM_SEND_RCB
+ TG3_BDINFO_SIZE
;
7544 for (txrcb
= NIC_SRAM_SEND_RCB
+ TG3_BDINFO_SIZE
;
7545 txrcb
< limit
; txrcb
+= TG3_BDINFO_SIZE
)
7546 tg3_write_mem(tp
, txrcb
+ TG3_BDINFO_MAXLEN_FLAGS
,
7547 BDINFO_FLAGS_DISABLED
);
7550 /* Disable all receive return rings but the first. */
7551 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
7552 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
)
7553 limit
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
* 17;
7554 else if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
7555 limit
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
* 16;
7556 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
||
7557 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
7558 limit
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
* 4;
7560 limit
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
;
7562 for (rxrcb
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
;
7563 rxrcb
< limit
; rxrcb
+= TG3_BDINFO_SIZE
)
7564 tg3_write_mem(tp
, rxrcb
+ TG3_BDINFO_MAXLEN_FLAGS
,
7565 BDINFO_FLAGS_DISABLED
);
7567 /* Disable interrupts */
7568 tw32_mailbox_f(tp
->napi
[0].int_mbox
, 1);
7570 /* Zero mailbox registers. */
7571 if (tp
->tg3_flags
& TG3_FLAG_SUPPORT_MSIX
) {
7572 for (i
= 1; i
< tp
->irq_max
; i
++) {
7573 tp
->napi
[i
].tx_prod
= 0;
7574 tp
->napi
[i
].tx_cons
= 0;
7575 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)
7576 tw32_mailbox(tp
->napi
[i
].prodmbox
, 0);
7577 tw32_rx_mbox(tp
->napi
[i
].consmbox
, 0);
7578 tw32_mailbox_f(tp
->napi
[i
].int_mbox
, 1);
7580 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
))
7581 tw32_mailbox(tp
->napi
[0].prodmbox
, 0);
7583 tp
->napi
[0].tx_prod
= 0;
7584 tp
->napi
[0].tx_cons
= 0;
7585 tw32_mailbox(tp
->napi
[0].prodmbox
, 0);
7586 tw32_rx_mbox(tp
->napi
[0].consmbox
, 0);
7589 /* Make sure the NIC-based send BD rings are disabled. */
7590 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
7591 u32 mbox
= MAILBOX_SNDNIC_PROD_IDX_0
+ TG3_64BIT_REG_LOW
;
7592 for (i
= 0; i
< 16; i
++)
7593 tw32_tx_mbox(mbox
+ i
* 8, 0);
7596 txrcb
= NIC_SRAM_SEND_RCB
;
7597 rxrcb
= NIC_SRAM_RCV_RET_RCB
;
7599 /* Clear status block in ram. */
7600 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
7602 /* Set status block DMA address */
7603 tw32(HOSTCC_STATUS_BLK_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
7604 ((u64
) tnapi
->status_mapping
>> 32));
7605 tw32(HOSTCC_STATUS_BLK_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
7606 ((u64
) tnapi
->status_mapping
& 0xffffffff));
7608 if (tnapi
->tx_ring
) {
7609 tg3_set_bdinfo(tp
, txrcb
, tnapi
->tx_desc_mapping
,
7610 (TG3_TX_RING_SIZE
<<
7611 BDINFO_FLAGS_MAXLEN_SHIFT
),
7612 NIC_SRAM_TX_BUFFER_DESC
);
7613 txrcb
+= TG3_BDINFO_SIZE
;
7616 if (tnapi
->rx_rcb
) {
7617 tg3_set_bdinfo(tp
, rxrcb
, tnapi
->rx_rcb_mapping
,
7618 (tp
->rx_ret_ring_mask
+ 1) <<
7619 BDINFO_FLAGS_MAXLEN_SHIFT
, 0);
7620 rxrcb
+= TG3_BDINFO_SIZE
;
7623 stblk
= HOSTCC_STATBLCK_RING1
;
7625 for (i
= 1, tnapi
++; i
< tp
->irq_cnt
; i
++, tnapi
++) {
7626 u64 mapping
= (u64
)tnapi
->status_mapping
;
7627 tw32(stblk
+ TG3_64BIT_REG_HIGH
, mapping
>> 32);
7628 tw32(stblk
+ TG3_64BIT_REG_LOW
, mapping
& 0xffffffff);
7630 /* Clear status block in ram. */
7631 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
7633 if (tnapi
->tx_ring
) {
7634 tg3_set_bdinfo(tp
, txrcb
, tnapi
->tx_desc_mapping
,
7635 (TG3_TX_RING_SIZE
<<
7636 BDINFO_FLAGS_MAXLEN_SHIFT
),
7637 NIC_SRAM_TX_BUFFER_DESC
);
7638 txrcb
+= TG3_BDINFO_SIZE
;
7641 tg3_set_bdinfo(tp
, rxrcb
, tnapi
->rx_rcb_mapping
,
7642 ((tp
->rx_ret_ring_mask
+ 1) <<
7643 BDINFO_FLAGS_MAXLEN_SHIFT
), 0);
7646 rxrcb
+= TG3_BDINFO_SIZE
;
7650 /* tp->lock is held. */
7651 static int tg3_reset_hw(struct tg3
*tp
, int reset_phy
)
7653 u32 val
, rdmac_mode
;
7655 struct tg3_rx_prodring_set
*tpr
= &tp
->napi
[0].prodring
;
7657 tg3_disable_ints(tp
);
7661 tg3_write_sig_pre_reset(tp
, RESET_KIND_INIT
);
7663 if (tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
)
7664 tg3_abort_hw(tp
, 1);
7669 err
= tg3_chip_reset(tp
);
7673 tg3_write_sig_legacy(tp
, RESET_KIND_INIT
);
7675 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
) {
7676 val
= tr32(TG3_CPMU_CTRL
);
7677 val
&= ~(CPMU_CTRL_LINK_AWARE_MODE
| CPMU_CTRL_LINK_IDLE_MODE
);
7678 tw32(TG3_CPMU_CTRL
, val
);
7680 val
= tr32(TG3_CPMU_LSPD_10MB_CLK
);
7681 val
&= ~CPMU_LSPD_10MB_MACCLK_MASK
;
7682 val
|= CPMU_LSPD_10MB_MACCLK_6_25
;
7683 tw32(TG3_CPMU_LSPD_10MB_CLK
, val
);
7685 val
= tr32(TG3_CPMU_LNK_AWARE_PWRMD
);
7686 val
&= ~CPMU_LNK_AWARE_MACCLK_MASK
;
7687 val
|= CPMU_LNK_AWARE_MACCLK_6_25
;
7688 tw32(TG3_CPMU_LNK_AWARE_PWRMD
, val
);
7690 val
= tr32(TG3_CPMU_HST_ACC
);
7691 val
&= ~CPMU_HST_ACC_MACCLK_MASK
;
7692 val
|= CPMU_HST_ACC_MACCLK_6_25
;
7693 tw32(TG3_CPMU_HST_ACC
, val
);
7696 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
) {
7697 val
= tr32(PCIE_PWR_MGMT_THRESH
) & ~PCIE_PWR_MGMT_L1_THRESH_MSK
;
7698 val
|= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN
|
7699 PCIE_PWR_MGMT_L1_THRESH_4MS
;
7700 tw32(PCIE_PWR_MGMT_THRESH
, val
);
7702 val
= tr32(TG3_PCIE_EIDLE_DELAY
) & ~TG3_PCIE_EIDLE_DELAY_MASK
;
7703 tw32(TG3_PCIE_EIDLE_DELAY
, val
| TG3_PCIE_EIDLE_DELAY_13_CLKS
);
7705 tw32(TG3_CORR_ERR_STAT
, TG3_CORR_ERR_STAT_CLEAR
);
7707 val
= tr32(TG3_PCIE_LNKCTL
) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN
;
7708 tw32(TG3_PCIE_LNKCTL
, val
| TG3_PCIE_LNKCTL_L1_PLL_PD_DIS
);
7711 if (tp
->tg3_flags3
& TG3_FLG3_L1PLLPD_EN
) {
7712 u32 grc_mode
= tr32(GRC_MODE
);
7714 /* Access the lower 1K of PL PCIE block registers. */
7715 val
= grc_mode
& ~GRC_MODE_PCIE_PORT_MASK
;
7716 tw32(GRC_MODE
, val
| GRC_MODE_PCIE_PL_SEL
);
7718 val
= tr32(TG3_PCIE_TLDLPL_PORT
+ TG3_PCIE_PL_LO_PHYCTL1
);
7719 tw32(TG3_PCIE_TLDLPL_PORT
+ TG3_PCIE_PL_LO_PHYCTL1
,
7720 val
| TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN
);
7722 tw32(GRC_MODE
, grc_mode
);
7725 if (tp
->pci_chip_rev_id
== CHIPREV_ID_57765_A0
) {
7726 u32 grc_mode
= tr32(GRC_MODE
);
7728 /* Access the lower 1K of PL PCIE block registers. */
7729 val
= grc_mode
& ~GRC_MODE_PCIE_PORT_MASK
;
7730 tw32(GRC_MODE
, val
| GRC_MODE_PCIE_PL_SEL
);
7732 val
= tr32(TG3_PCIE_TLDLPL_PORT
+ TG3_PCIE_PL_LO_PHYCTL5
);
7733 tw32(TG3_PCIE_TLDLPL_PORT
+ TG3_PCIE_PL_LO_PHYCTL5
,
7734 val
| TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ
);
7736 tw32(GRC_MODE
, grc_mode
);
7738 val
= tr32(TG3_CPMU_LSPD_10MB_CLK
);
7739 val
&= ~CPMU_LSPD_10MB_MACCLK_MASK
;
7740 val
|= CPMU_LSPD_10MB_MACCLK_6_25
;
7741 tw32(TG3_CPMU_LSPD_10MB_CLK
, val
);
7744 /* This works around an issue with Athlon chipsets on
7745 * B3 tigon3 silicon. This bit has no effect on any
7746 * other revision. But do not set this on PCI Express
7747 * chips and don't even touch the clocks if the CPMU is present.
7749 if (!(tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
)) {
7750 if (!(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
))
7751 tp
->pci_clock_ctrl
|= CLOCK_CTRL_DELAY_PCI_GRANT
;
7752 tw32_f(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
);
7755 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
&&
7756 (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
)) {
7757 val
= tr32(TG3PCI_PCISTATE
);
7758 val
|= PCISTATE_RETRY_SAME_DMA
;
7759 tw32(TG3PCI_PCISTATE
, val
);
7762 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
7763 /* Allow reads and writes to the
7764 * APE register and memory space.
7766 val
= tr32(TG3PCI_PCISTATE
);
7767 val
|= PCISTATE_ALLOW_APE_CTLSPC_WR
|
7768 PCISTATE_ALLOW_APE_SHMEM_WR
|
7769 PCISTATE_ALLOW_APE_PSPACE_WR
;
7770 tw32(TG3PCI_PCISTATE
, val
);
7773 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5704_BX
) {
7774 /* Enable some hw fixes. */
7775 val
= tr32(TG3PCI_MSI_DATA
);
7776 val
|= (1 << 26) | (1 << 28) | (1 << 29);
7777 tw32(TG3PCI_MSI_DATA
, val
);
7780 /* Descriptor ring init may make accesses to the
7781 * NIC SRAM area to setup the TX descriptors, so we
7782 * can only do this after the hardware has been
7783 * successfully reset.
7785 err
= tg3_init_rings(tp
);
7789 if (tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
) {
7790 val
= tr32(TG3PCI_DMA_RW_CTRL
) &
7791 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT
;
7792 if (tp
->pci_chip_rev_id
== CHIPREV_ID_57765_A0
)
7793 val
&= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK
;
7794 tw32(TG3PCI_DMA_RW_CTRL
, val
| tp
->dma_rwctrl
);
7795 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5784
&&
7796 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5761
) {
7797 /* This value is determined during the probe time DMA
7798 * engine test, tg3_test_dma.
7800 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
7803 tp
->grc_mode
&= ~(GRC_MODE_HOST_SENDBDS
|
7804 GRC_MODE_4X_NIC_SEND_RINGS
|
7805 GRC_MODE_NO_TX_PHDR_CSUM
|
7806 GRC_MODE_NO_RX_PHDR_CSUM
);
7807 tp
->grc_mode
|= GRC_MODE_HOST_SENDBDS
;
7809 /* Pseudo-header checksum is done by hardware logic and not
7810 * the offload processers, so make the chip do the pseudo-
7811 * header checksums on receive. For transmit it is more
7812 * convenient to do the pseudo-header checksum in software
7813 * as Linux does that on transmit for us in all cases.
7815 tp
->grc_mode
|= GRC_MODE_NO_TX_PHDR_CSUM
;
7819 (GRC_MODE_IRQ_ON_MAC_ATTN
| GRC_MODE_HOST_STACKUP
));
7821 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7822 val
= tr32(GRC_MISC_CFG
);
7824 val
|= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT
);
7825 tw32(GRC_MISC_CFG
, val
);
7827 /* Initialize MBUF/DESC pool. */
7828 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) {
7830 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5705
) {
7831 tw32(BUFMGR_MB_POOL_ADDR
, NIC_SRAM_MBUF_POOL_BASE
);
7832 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
)
7833 tw32(BUFMGR_MB_POOL_SIZE
, NIC_SRAM_MBUF_POOL_SIZE64
);
7835 tw32(BUFMGR_MB_POOL_SIZE
, NIC_SRAM_MBUF_POOL_SIZE96
);
7836 tw32(BUFMGR_DMA_DESC_POOL_ADDR
, NIC_SRAM_DMA_DESC_POOL_BASE
);
7837 tw32(BUFMGR_DMA_DESC_POOL_SIZE
, NIC_SRAM_DMA_DESC_POOL_SIZE
);
7838 } else if (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) {
7841 fw_len
= tp
->fw_len
;
7842 fw_len
= (fw_len
+ (0x80 - 1)) & ~(0x80 - 1);
7843 tw32(BUFMGR_MB_POOL_ADDR
,
7844 NIC_SRAM_MBUF_POOL_BASE5705
+ fw_len
);
7845 tw32(BUFMGR_MB_POOL_SIZE
,
7846 NIC_SRAM_MBUF_POOL_SIZE5705
- fw_len
- 0xa00);
7849 if (tp
->dev
->mtu
<= ETH_DATA_LEN
) {
7850 tw32(BUFMGR_MB_RDMA_LOW_WATER
,
7851 tp
->bufmgr_config
.mbuf_read_dma_low_water
);
7852 tw32(BUFMGR_MB_MACRX_LOW_WATER
,
7853 tp
->bufmgr_config
.mbuf_mac_rx_low_water
);
7854 tw32(BUFMGR_MB_HIGH_WATER
,
7855 tp
->bufmgr_config
.mbuf_high_water
);
7857 tw32(BUFMGR_MB_RDMA_LOW_WATER
,
7858 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
);
7859 tw32(BUFMGR_MB_MACRX_LOW_WATER
,
7860 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
);
7861 tw32(BUFMGR_MB_HIGH_WATER
,
7862 tp
->bufmgr_config
.mbuf_high_water_jumbo
);
7864 tw32(BUFMGR_DMA_LOW_WATER
,
7865 tp
->bufmgr_config
.dma_low_water
);
7866 tw32(BUFMGR_DMA_HIGH_WATER
,
7867 tp
->bufmgr_config
.dma_high_water
);
7869 val
= BUFMGR_MODE_ENABLE
| BUFMGR_MODE_ATTN_ENABLE
;
7870 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
)
7871 val
|= BUFMGR_MODE_NO_TX_UNDERRUN
;
7872 tw32(BUFMGR_MODE
, val
);
7873 for (i
= 0; i
< 2000; i
++) {
7874 if (tr32(BUFMGR_MODE
) & BUFMGR_MODE_ENABLE
)
7879 netdev_err(tp
->dev
, "%s cannot enable BUFMGR\n", __func__
);
7883 /* Setup replenish threshold. */
7884 val
= tp
->rx_pending
/ 8;
7887 else if (val
> tp
->rx_std_max_post
)
7888 val
= tp
->rx_std_max_post
;
7889 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
7890 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5906_A1
)
7891 tw32(ISO_PKT_TX
, (tr32(ISO_PKT_TX
) & ~0x3) | 0x2);
7893 if (val
> (TG3_RX_INTERNAL_RING_SZ_5906
/ 2))
7894 val
= TG3_RX_INTERNAL_RING_SZ_5906
/ 2;
7897 tw32(RCVBDI_STD_THRESH
, val
);
7899 /* Initialize TG3_BDINFO's at:
7900 * RCVDBDI_STD_BD: standard eth size rx ring
7901 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7902 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7905 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7906 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7907 * ring attribute flags
7908 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7910 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7911 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7913 * The size of each ring is fixed in the firmware, but the location is
7916 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
7917 ((u64
) tpr
->rx_std_mapping
>> 32));
7918 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
7919 ((u64
) tpr
->rx_std_mapping
& 0xffffffff));
7920 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5717
&&
7921 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5719
)
7922 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_NIC_ADDR
,
7923 NIC_SRAM_RX_BUFFER_DESC
);
7925 /* Disable the mini ring */
7926 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
7927 tw32(RCVDBDI_MINI_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
7928 BDINFO_FLAGS_DISABLED
);
7930 /* Program the jumbo buffer descriptor ring control
7931 * blocks on those devices that have them.
7933 if ((tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) &&
7934 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
7935 /* Setup replenish threshold. */
7936 tw32(RCVBDI_JUMBO_THRESH
, tp
->rx_jumbo_pending
/ 8);
7938 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
) {
7939 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
7940 ((u64
) tpr
->rx_jmb_mapping
>> 32));
7941 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
7942 ((u64
) tpr
->rx_jmb_mapping
& 0xffffffff));
7943 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
7944 (RX_JUMBO_MAX_SIZE
<< BDINFO_FLAGS_MAXLEN_SHIFT
) |
7945 BDINFO_FLAGS_USE_EXT_RECV
);
7946 if (!(tp
->tg3_flags3
& TG3_FLG3_USE_JUMBO_BDFLAG
) ||
7947 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
7948 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_NIC_ADDR
,
7949 NIC_SRAM_RX_JUMBO_BUFFER_DESC
);
7951 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
7952 BDINFO_FLAGS_DISABLED
);
7955 if (tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
) {
7956 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
7957 val
= RX_STD_MAX_SIZE_5705
;
7959 val
= RX_STD_MAX_SIZE_5717
;
7960 val
<<= BDINFO_FLAGS_MAXLEN_SHIFT
;
7961 val
|= (TG3_RX_STD_DMA_SZ
<< 2);
7963 val
= TG3_RX_STD_DMA_SZ
<< BDINFO_FLAGS_MAXLEN_SHIFT
;
7965 val
= RX_STD_MAX_SIZE_5705
<< BDINFO_FLAGS_MAXLEN_SHIFT
;
7967 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_MAXLEN_FLAGS
, val
);
7969 tpr
->rx_std_prod_idx
= tp
->rx_pending
;
7970 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG
, tpr
->rx_std_prod_idx
);
7972 tpr
->rx_jmb_prod_idx
= (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
) ?
7973 tp
->rx_jumbo_pending
: 0;
7974 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG
, tpr
->rx_jmb_prod_idx
);
7976 if (tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
) {
7977 tw32(STD_REPLENISH_LWM
, 32);
7978 tw32(JMB_REPLENISH_LWM
, 16);
7981 tg3_rings_reset(tp
);
7983 /* Initialize MAC address and backoff seed. */
7984 __tg3_set_mac_addr(tp
, 0);
7986 /* MTU + ethernet header + FCS + optional VLAN tag */
7987 tw32(MAC_RX_MTU_SIZE
,
7988 tp
->dev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
+ VLAN_HLEN
);
7990 /* The slot time is changed by tg3_setup_phy if we
7991 * run at gigabit with half duplex.
7993 tw32(MAC_TX_LENGTHS
,
7994 (2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
7995 (6 << TX_LENGTHS_IPG_SHIFT
) |
7996 (32 << TX_LENGTHS_SLOT_TIME_SHIFT
));
7998 /* Receive rules. */
7999 tw32(MAC_RCV_RULE_CFG
, RCV_RULE_CFG_DEFAULT_CLASS
);
8000 tw32(RCVLPC_CONFIG
, 0x0181);
8002 /* Calculate RDMAC_MODE setting early, we need it to determine
8003 * the RCVLPC_STATE_ENABLE mask.
8005 rdmac_mode
= (RDMAC_MODE_ENABLE
| RDMAC_MODE_TGTABORT_ENAB
|
8006 RDMAC_MODE_MSTABORT_ENAB
| RDMAC_MODE_PARITYERR_ENAB
|
8007 RDMAC_MODE_ADDROFLOW_ENAB
| RDMAC_MODE_FIFOOFLOW_ENAB
|
8008 RDMAC_MODE_FIFOURUN_ENAB
| RDMAC_MODE_FIFOOREAD_ENAB
|
8009 RDMAC_MODE_LNGREAD_ENAB
);
8011 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
8012 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
)
8013 rdmac_mode
|= RDMAC_MODE_MULT_DMA_RD_DIS
;
8015 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
8016 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
8017 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
8018 rdmac_mode
|= RDMAC_MODE_BD_SBD_CRPT_ENAB
|
8019 RDMAC_MODE_MBUF_RBD_CRPT_ENAB
|
8020 RDMAC_MODE_MBUF_SBD_CRPT_ENAB
;
8022 /* If statement applies to 5705 and 5750 PCI devices only */
8023 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
8024 tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A0
) ||
8025 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
)) {
8026 if (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
&&
8027 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
8028 rdmac_mode
|= RDMAC_MODE_FIFO_SIZE_128
;
8029 } else if (!(tr32(TG3PCI_PCISTATE
) & PCISTATE_BUS_SPEED_HIGH
) &&
8030 !(tp
->tg3_flags2
& TG3_FLG2_IS_5788
)) {
8031 rdmac_mode
|= RDMAC_MODE_FIFO_LONG_BURST
;
8035 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)
8036 rdmac_mode
|= RDMAC_MODE_FIFO_LONG_BURST
;
8038 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
8039 rdmac_mode
|= RDMAC_MODE_IPV4_LSO_EN
;
8041 if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO_3
) ||
8042 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
8043 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
8044 rdmac_mode
|= RDMAC_MODE_IPV6_LSO_EN
;
8046 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
8047 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
8048 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
8049 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
||
8050 (tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
)) {
8051 val
= tr32(TG3_RDMA_RSRVCTRL_REG
);
8052 tw32(TG3_RDMA_RSRVCTRL_REG
,
8053 val
| TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX
);
8056 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
) {
8057 val
= tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL
);
8058 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL
, val
|
8059 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K
|
8060 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K
);
8063 /* Receive/send statistics. */
8064 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) {
8065 val
= tr32(RCVLPC_STATS_ENABLE
);
8066 val
&= ~RCVLPC_STATSENAB_DACK_FIX
;
8067 tw32(RCVLPC_STATS_ENABLE
, val
);
8068 } else if ((rdmac_mode
& RDMAC_MODE_FIFO_SIZE_128
) &&
8069 (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
)) {
8070 val
= tr32(RCVLPC_STATS_ENABLE
);
8071 val
&= ~RCVLPC_STATSENAB_LNGBRST_RFIX
;
8072 tw32(RCVLPC_STATS_ENABLE
, val
);
8074 tw32(RCVLPC_STATS_ENABLE
, 0xffffff);
8076 tw32(RCVLPC_STATSCTRL
, RCVLPC_STATSCTRL_ENABLE
);
8077 tw32(SNDDATAI_STATSENAB
, 0xffffff);
8078 tw32(SNDDATAI_STATSCTRL
,
8079 (SNDDATAI_SCTRL_ENABLE
|
8080 SNDDATAI_SCTRL_FASTUPD
));
8082 /* Setup host coalescing engine. */
8083 tw32(HOSTCC_MODE
, 0);
8084 for (i
= 0; i
< 2000; i
++) {
8085 if (!(tr32(HOSTCC_MODE
) & HOSTCC_MODE_ENABLE
))
8090 __tg3_set_coalesce(tp
, &tp
->coal
);
8092 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
8093 /* Status/statistics block address. See tg3_timer,
8094 * the tg3_periodic_fetch_stats call there, and
8095 * tg3_get_stats to see how this works for 5705/5750 chips.
8097 tw32(HOSTCC_STATS_BLK_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
8098 ((u64
) tp
->stats_mapping
>> 32));
8099 tw32(HOSTCC_STATS_BLK_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
8100 ((u64
) tp
->stats_mapping
& 0xffffffff));
8101 tw32(HOSTCC_STATS_BLK_NIC_ADDR
, NIC_SRAM_STATS_BLK
);
8103 tw32(HOSTCC_STATUS_BLK_NIC_ADDR
, NIC_SRAM_STATUS_BLK
);
8105 /* Clear statistics and status block memory areas */
8106 for (i
= NIC_SRAM_STATS_BLK
;
8107 i
< NIC_SRAM_STATUS_BLK
+ TG3_HW_STATUS_SIZE
;
8109 tg3_write_mem(tp
, i
, 0);
8114 tw32(HOSTCC_MODE
, HOSTCC_MODE_ENABLE
| tp
->coalesce_mode
);
8116 tw32(RCVCC_MODE
, RCVCC_MODE_ENABLE
| RCVCC_MODE_ATTN_ENABLE
);
8117 tw32(RCVLPC_MODE
, RCVLPC_MODE_ENABLE
);
8118 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
8119 tw32(RCVLSC_MODE
, RCVLSC_MODE_ENABLE
| RCVLSC_MODE_ATTN_ENABLE
);
8121 if (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
) {
8122 tp
->phy_flags
&= ~TG3_PHYFLG_PARALLEL_DETECT
;
8123 /* reset to prevent losing 1st rx packet intermittently */
8124 tw32_f(MAC_RX_MODE
, RX_MODE_RESET
);
8128 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
8129 tp
->mac_mode
&= MAC_MODE_APE_TX_EN
| MAC_MODE_APE_RX_EN
;
8132 tp
->mac_mode
|= MAC_MODE_TXSTAT_ENABLE
| MAC_MODE_RXSTAT_ENABLE
|
8133 MAC_MODE_TDE_ENABLE
| MAC_MODE_RDE_ENABLE
| MAC_MODE_FHDE_ENABLE
;
8134 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
8135 !(tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) &&
8136 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
)
8137 tp
->mac_mode
|= MAC_MODE_LINK_POLARITY
;
8138 tw32_f(MAC_MODE
, tp
->mac_mode
| MAC_MODE_RXSTAT_CLEAR
| MAC_MODE_TXSTAT_CLEAR
);
8141 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8142 * If TG3_FLG2_IS_NIC is zero, we should read the
8143 * register to preserve the GPIO settings for LOMs. The GPIOs,
8144 * whether used as inputs or outputs, are set by boot code after
8147 if (!(tp
->tg3_flags2
& TG3_FLG2_IS_NIC
)) {
8150 gpio_mask
= GRC_LCLCTRL_GPIO_OE0
| GRC_LCLCTRL_GPIO_OE1
|
8151 GRC_LCLCTRL_GPIO_OE2
| GRC_LCLCTRL_GPIO_OUTPUT0
|
8152 GRC_LCLCTRL_GPIO_OUTPUT1
| GRC_LCLCTRL_GPIO_OUTPUT2
;
8154 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
)
8155 gpio_mask
|= GRC_LCLCTRL_GPIO_OE3
|
8156 GRC_LCLCTRL_GPIO_OUTPUT3
;
8158 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
)
8159 gpio_mask
|= GRC_LCLCTRL_GPIO_UART_SEL
;
8161 tp
->grc_local_ctrl
&= ~gpio_mask
;
8162 tp
->grc_local_ctrl
|= tr32(GRC_LOCAL_CTRL
) & gpio_mask
;
8164 /* GPIO1 must be driven high for eeprom write protect */
8165 if (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
)
8166 tp
->grc_local_ctrl
|= (GRC_LCLCTRL_GPIO_OE1
|
8167 GRC_LCLCTRL_GPIO_OUTPUT1
);
8169 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
);
8172 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSIX
) {
8173 val
= tr32(MSGINT_MODE
);
8174 val
|= MSGINT_MODE_MULTIVEC_EN
| MSGINT_MODE_ENABLE
;
8175 tw32(MSGINT_MODE
, val
);
8178 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
8179 tw32_f(DMAC_MODE
, DMAC_MODE_ENABLE
);
8183 val
= (WDMAC_MODE_ENABLE
| WDMAC_MODE_TGTABORT_ENAB
|
8184 WDMAC_MODE_MSTABORT_ENAB
| WDMAC_MODE_PARITYERR_ENAB
|
8185 WDMAC_MODE_ADDROFLOW_ENAB
| WDMAC_MODE_FIFOOFLOW_ENAB
|
8186 WDMAC_MODE_FIFOURUN_ENAB
| WDMAC_MODE_FIFOOREAD_ENAB
|
8187 WDMAC_MODE_LNGREAD_ENAB
);
8189 /* If statement applies to 5705 and 5750 PCI devices only */
8190 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
8191 tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A0
) ||
8192 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
) {
8193 if ((tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) &&
8194 (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A1
||
8195 tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A2
)) {
8197 } else if (!(tr32(TG3PCI_PCISTATE
) & PCISTATE_BUS_SPEED_HIGH
) &&
8198 !(tp
->tg3_flags2
& TG3_FLG2_IS_5788
) &&
8199 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)) {
8200 val
|= WDMAC_MODE_RX_ACCEL
;
8204 /* Enable host coalescing bug fix */
8205 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
8206 val
|= WDMAC_MODE_STATUS_TAG_FIX
;
8208 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
8209 val
|= WDMAC_MODE_BURST_ALL_DATA
;
8211 tw32_f(WDMAC_MODE
, val
);
8214 if (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) {
8217 pci_read_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
8219 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
) {
8220 pcix_cmd
&= ~PCI_X_CMD_MAX_READ
;
8221 pcix_cmd
|= PCI_X_CMD_READ_2K
;
8222 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
8223 pcix_cmd
&= ~(PCI_X_CMD_MAX_SPLIT
| PCI_X_CMD_MAX_READ
);
8224 pcix_cmd
|= PCI_X_CMD_READ_2K
;
8226 pci_write_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
8230 tw32_f(RDMAC_MODE
, rdmac_mode
);
8233 tw32(RCVDCC_MODE
, RCVDCC_MODE_ENABLE
| RCVDCC_MODE_ATTN_ENABLE
);
8234 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
8235 tw32(MBFREE_MODE
, MBFREE_MODE_ENABLE
);
8237 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
)
8239 SNDDATAC_MODE_ENABLE
| SNDDATAC_MODE_CDELAY
);
8241 tw32(SNDDATAC_MODE
, SNDDATAC_MODE_ENABLE
);
8243 tw32(SNDBDC_MODE
, SNDBDC_MODE_ENABLE
| SNDBDC_MODE_ATTN_ENABLE
);
8244 tw32(RCVBDI_MODE
, RCVBDI_MODE_ENABLE
| RCVBDI_MODE_RCB_ATTN_ENAB
);
8245 val
= RCVDBDI_MODE_ENABLE
| RCVDBDI_MODE_INV_RING_SZ
;
8246 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
8247 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
)
8248 val
|= RCVDBDI_MODE_LRG_RING_SZ
;
8249 tw32(RCVDBDI_MODE
, val
);
8250 tw32(SNDDATAI_MODE
, SNDDATAI_MODE_ENABLE
);
8251 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
8252 tw32(SNDDATAI_MODE
, SNDDATAI_MODE_ENABLE
| 0x8);
8253 val
= SNDBDI_MODE_ENABLE
| SNDBDI_MODE_ATTN_ENABLE
;
8254 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)
8255 val
|= SNDBDI_MODE_MULTI_TXQ_EN
;
8256 tw32(SNDBDI_MODE
, val
);
8257 tw32(SNDBDS_MODE
, SNDBDS_MODE_ENABLE
| SNDBDS_MODE_ATTN_ENABLE
);
8259 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
) {
8260 err
= tg3_load_5701_a0_firmware_fix(tp
);
8265 if (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) {
8266 err
= tg3_load_tso_firmware(tp
);
8271 tp
->tx_mode
= TX_MODE_ENABLE
;
8272 if ((tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) ||
8273 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
8274 tp
->tx_mode
|= TX_MODE_MBUF_LOCKUP_FIX
;
8275 tw32_f(MAC_TX_MODE
, tp
->tx_mode
);
8278 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_RSS
) {
8279 u32 reg
= MAC_RSS_INDIR_TBL_0
;
8280 u8
*ent
= (u8
*)&val
;
8282 /* Setup the indirection table */
8283 for (i
= 0; i
< TG3_RSS_INDIR_TBL_SIZE
; i
++) {
8284 int idx
= i
% sizeof(val
);
8286 ent
[idx
] = i
% (tp
->irq_cnt
- 1);
8287 if (idx
== sizeof(val
) - 1) {
8293 /* Setup the "secret" hash key. */
8294 tw32(MAC_RSS_HASH_KEY_0
, 0x5f865437);
8295 tw32(MAC_RSS_HASH_KEY_1
, 0xe4ac62cc);
8296 tw32(MAC_RSS_HASH_KEY_2
, 0x50103a45);
8297 tw32(MAC_RSS_HASH_KEY_3
, 0x36621985);
8298 tw32(MAC_RSS_HASH_KEY_4
, 0xbf14c0e8);
8299 tw32(MAC_RSS_HASH_KEY_5
, 0x1bc27a1e);
8300 tw32(MAC_RSS_HASH_KEY_6
, 0x84f4b556);
8301 tw32(MAC_RSS_HASH_KEY_7
, 0x094ea6fe);
8302 tw32(MAC_RSS_HASH_KEY_8
, 0x7dda01e7);
8303 tw32(MAC_RSS_HASH_KEY_9
, 0xc04d7481);
8306 tp
->rx_mode
= RX_MODE_ENABLE
;
8307 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
8308 tp
->rx_mode
|= RX_MODE_IPV6_CSUM_ENABLE
;
8310 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_RSS
)
8311 tp
->rx_mode
|= RX_MODE_RSS_ENABLE
|
8312 RX_MODE_RSS_ITBL_HASH_BITS_7
|
8313 RX_MODE_RSS_IPV6_HASH_EN
|
8314 RX_MODE_RSS_TCP_IPV6_HASH_EN
|
8315 RX_MODE_RSS_IPV4_HASH_EN
|
8316 RX_MODE_RSS_TCP_IPV4_HASH_EN
;
8318 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
8321 tw32(MAC_LED_CTRL
, tp
->led_ctrl
);
8323 tw32(MAC_MI_STAT
, MAC_MI_STAT_LNKSTAT_ATTN_ENAB
);
8324 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) {
8325 tw32_f(MAC_RX_MODE
, RX_MODE_RESET
);
8328 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
8331 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) {
8332 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) &&
8333 !(tp
->phy_flags
& TG3_PHYFLG_SERDES_PREEMPHASIS
)) {
8334 /* Set drive transmission level to 1.2V */
8335 /* only if the signal pre-emphasis bit is not set */
8336 val
= tr32(MAC_SERDES_CFG
);
8339 tw32(MAC_SERDES_CFG
, val
);
8341 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5703_A1
)
8342 tw32(MAC_SERDES_CFG
, 0x616000);
8345 /* Prevent chip from dropping frames when flow control
8348 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
8352 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME
, val
);
8354 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
&&
8355 (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
)) {
8356 /* Use hardware link auto-negotiation */
8357 tp
->tg3_flags2
|= TG3_FLG2_HW_AUTONEG
;
8360 if ((tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
) &&
8361 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
)) {
8364 tmp
= tr32(SERDES_RX_CTRL
);
8365 tw32(SERDES_RX_CTRL
, tmp
| SERDES_RX_SIG_DETECT
);
8366 tp
->grc_local_ctrl
&= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT
;
8367 tp
->grc_local_ctrl
|= GRC_LCLCTRL_USE_SIG_DETECT
;
8368 tw32(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
);
8371 if (!(tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
)) {
8372 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
) {
8373 tp
->phy_flags
&= ~TG3_PHYFLG_IS_LOW_POWER
;
8374 tp
->link_config
.speed
= tp
->link_config
.orig_speed
;
8375 tp
->link_config
.duplex
= tp
->link_config
.orig_duplex
;
8376 tp
->link_config
.autoneg
= tp
->link_config
.orig_autoneg
;
8379 err
= tg3_setup_phy(tp
, 0);
8383 if (!(tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) &&
8384 !(tp
->phy_flags
& TG3_PHYFLG_IS_FET
)) {
8387 /* Clear CRC stats. */
8388 if (!tg3_readphy(tp
, MII_TG3_TEST1
, &tmp
)) {
8389 tg3_writephy(tp
, MII_TG3_TEST1
,
8390 tmp
| MII_TG3_TEST1_CRC_EN
);
8391 tg3_readphy(tp
, MII_TG3_RXR_COUNTERS
, &tmp
);
8396 __tg3_set_rx_mode(tp
->dev
);
8398 /* Initialize receive rules. */
8399 tw32(MAC_RCV_RULE_0
, 0xc2000000 & RCV_RULE_DISABLE_MASK
);
8400 tw32(MAC_RCV_VALUE_0
, 0xffffffff & RCV_RULE_DISABLE_MASK
);
8401 tw32(MAC_RCV_RULE_1
, 0x86000004 & RCV_RULE_DISABLE_MASK
);
8402 tw32(MAC_RCV_VALUE_1
, 0xffffffff & RCV_RULE_DISABLE_MASK
);
8404 if ((tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
8405 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
8409 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)
8413 tw32(MAC_RCV_RULE_15
, 0); tw32(MAC_RCV_VALUE_15
, 0);
8415 tw32(MAC_RCV_RULE_14
, 0); tw32(MAC_RCV_VALUE_14
, 0);
8417 tw32(MAC_RCV_RULE_13
, 0); tw32(MAC_RCV_VALUE_13
, 0);
8419 tw32(MAC_RCV_RULE_12
, 0); tw32(MAC_RCV_VALUE_12
, 0);
8421 tw32(MAC_RCV_RULE_11
, 0); tw32(MAC_RCV_VALUE_11
, 0);
8423 tw32(MAC_RCV_RULE_10
, 0); tw32(MAC_RCV_VALUE_10
, 0);
8425 tw32(MAC_RCV_RULE_9
, 0); tw32(MAC_RCV_VALUE_9
, 0);
8427 tw32(MAC_RCV_RULE_8
, 0); tw32(MAC_RCV_VALUE_8
, 0);
8429 tw32(MAC_RCV_RULE_7
, 0); tw32(MAC_RCV_VALUE_7
, 0);
8431 tw32(MAC_RCV_RULE_6
, 0); tw32(MAC_RCV_VALUE_6
, 0);
8433 tw32(MAC_RCV_RULE_5
, 0); tw32(MAC_RCV_VALUE_5
, 0);
8435 tw32(MAC_RCV_RULE_4
, 0); tw32(MAC_RCV_VALUE_4
, 0);
8437 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
8439 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
8447 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
8448 /* Write our heartbeat update interval to APE. */
8449 tg3_ape_write32(tp
, TG3_APE_HOST_HEARTBEAT_INT_MS
,
8450 APE_HOST_HEARTBEAT_INT_DISABLE
);
8452 tg3_write_sig_post_reset(tp
, RESET_KIND_INIT
);
8457 /* Called at device open time to get the chip ready for
8458 * packet processing. Invoked with tp->lock held.
8460 static int tg3_init_hw(struct tg3
*tp
, int reset_phy
)
8462 tg3_switch_clocks(tp
);
8464 tw32(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
8466 return tg3_reset_hw(tp
, reset_phy
);
8469 #define TG3_STAT_ADD32(PSTAT, REG) \
8470 do { u32 __val = tr32(REG); \
8471 (PSTAT)->low += __val; \
8472 if ((PSTAT)->low < __val) \
8473 (PSTAT)->high += 1; \
8476 static void tg3_periodic_fetch_stats(struct tg3
*tp
)
8478 struct tg3_hw_stats
*sp
= tp
->hw_stats
;
8480 if (!netif_carrier_ok(tp
->dev
))
8483 TG3_STAT_ADD32(&sp
->tx_octets
, MAC_TX_STATS_OCTETS
);
8484 TG3_STAT_ADD32(&sp
->tx_collisions
, MAC_TX_STATS_COLLISIONS
);
8485 TG3_STAT_ADD32(&sp
->tx_xon_sent
, MAC_TX_STATS_XON_SENT
);
8486 TG3_STAT_ADD32(&sp
->tx_xoff_sent
, MAC_TX_STATS_XOFF_SENT
);
8487 TG3_STAT_ADD32(&sp
->tx_mac_errors
, MAC_TX_STATS_MAC_ERRORS
);
8488 TG3_STAT_ADD32(&sp
->tx_single_collisions
, MAC_TX_STATS_SINGLE_COLLISIONS
);
8489 TG3_STAT_ADD32(&sp
->tx_mult_collisions
, MAC_TX_STATS_MULT_COLLISIONS
);
8490 TG3_STAT_ADD32(&sp
->tx_deferred
, MAC_TX_STATS_DEFERRED
);
8491 TG3_STAT_ADD32(&sp
->tx_excessive_collisions
, MAC_TX_STATS_EXCESSIVE_COL
);
8492 TG3_STAT_ADD32(&sp
->tx_late_collisions
, MAC_TX_STATS_LATE_COL
);
8493 TG3_STAT_ADD32(&sp
->tx_ucast_packets
, MAC_TX_STATS_UCAST
);
8494 TG3_STAT_ADD32(&sp
->tx_mcast_packets
, MAC_TX_STATS_MCAST
);
8495 TG3_STAT_ADD32(&sp
->tx_bcast_packets
, MAC_TX_STATS_BCAST
);
8497 TG3_STAT_ADD32(&sp
->rx_octets
, MAC_RX_STATS_OCTETS
);
8498 TG3_STAT_ADD32(&sp
->rx_fragments
, MAC_RX_STATS_FRAGMENTS
);
8499 TG3_STAT_ADD32(&sp
->rx_ucast_packets
, MAC_RX_STATS_UCAST
);
8500 TG3_STAT_ADD32(&sp
->rx_mcast_packets
, MAC_RX_STATS_MCAST
);
8501 TG3_STAT_ADD32(&sp
->rx_bcast_packets
, MAC_RX_STATS_BCAST
);
8502 TG3_STAT_ADD32(&sp
->rx_fcs_errors
, MAC_RX_STATS_FCS_ERRORS
);
8503 TG3_STAT_ADD32(&sp
->rx_align_errors
, MAC_RX_STATS_ALIGN_ERRORS
);
8504 TG3_STAT_ADD32(&sp
->rx_xon_pause_rcvd
, MAC_RX_STATS_XON_PAUSE_RECVD
);
8505 TG3_STAT_ADD32(&sp
->rx_xoff_pause_rcvd
, MAC_RX_STATS_XOFF_PAUSE_RECVD
);
8506 TG3_STAT_ADD32(&sp
->rx_mac_ctrl_rcvd
, MAC_RX_STATS_MAC_CTRL_RECVD
);
8507 TG3_STAT_ADD32(&sp
->rx_xoff_entered
, MAC_RX_STATS_XOFF_ENTERED
);
8508 TG3_STAT_ADD32(&sp
->rx_frame_too_long_errors
, MAC_RX_STATS_FRAME_TOO_LONG
);
8509 TG3_STAT_ADD32(&sp
->rx_jabbers
, MAC_RX_STATS_JABBERS
);
8510 TG3_STAT_ADD32(&sp
->rx_undersize_packets
, MAC_RX_STATS_UNDERSIZE
);
8512 TG3_STAT_ADD32(&sp
->rxbds_empty
, RCVLPC_NO_RCV_BD_CNT
);
8513 TG3_STAT_ADD32(&sp
->rx_discards
, RCVLPC_IN_DISCARDS_CNT
);
8514 TG3_STAT_ADD32(&sp
->rx_errors
, RCVLPC_IN_ERRORS_CNT
);
8517 static void tg3_timer(unsigned long __opaque
)
8519 struct tg3
*tp
= (struct tg3
*) __opaque
;
8524 spin_lock(&tp
->lock
);
8526 if (!(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)) {
8527 /* All of this garbage is because when using non-tagged
8528 * IRQ status the mailbox/status_block protocol the chip
8529 * uses with the cpu is race prone.
8531 if (tp
->napi
[0].hw_status
->status
& SD_STATUS_UPDATED
) {
8532 tw32(GRC_LOCAL_CTRL
,
8533 tp
->grc_local_ctrl
| GRC_LCLCTRL_SETINT
);
8535 tw32(HOSTCC_MODE
, tp
->coalesce_mode
|
8536 HOSTCC_MODE_ENABLE
| HOSTCC_MODE_NOW
);
8539 if (!(tr32(WDMAC_MODE
) & WDMAC_MODE_ENABLE
)) {
8540 tp
->tg3_flags2
|= TG3_FLG2_RESTART_TIMER
;
8541 spin_unlock(&tp
->lock
);
8542 schedule_work(&tp
->reset_task
);
8547 /* This part only runs once per second. */
8548 if (!--tp
->timer_counter
) {
8549 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
8550 tg3_periodic_fetch_stats(tp
);
8552 if (tp
->tg3_flags
& TG3_FLAG_USE_LINKCHG_REG
) {
8556 mac_stat
= tr32(MAC_STATUS
);
8559 if (tp
->phy_flags
& TG3_PHYFLG_USE_MI_INTERRUPT
) {
8560 if (mac_stat
& MAC_STATUS_MI_INTERRUPT
)
8562 } else if (mac_stat
& MAC_STATUS_LNKSTATE_CHANGED
)
8566 tg3_setup_phy(tp
, 0);
8567 } else if (tp
->tg3_flags
& TG3_FLAG_POLL_SERDES
) {
8568 u32 mac_stat
= tr32(MAC_STATUS
);
8571 if (netif_carrier_ok(tp
->dev
) &&
8572 (mac_stat
& MAC_STATUS_LNKSTATE_CHANGED
)) {
8575 if (!netif_carrier_ok(tp
->dev
) &&
8576 (mac_stat
& (MAC_STATUS_PCS_SYNCED
|
8577 MAC_STATUS_SIGNAL_DET
))) {
8581 if (!tp
->serdes_counter
) {
8584 ~MAC_MODE_PORT_MODE_MASK
));
8586 tw32_f(MAC_MODE
, tp
->mac_mode
);
8589 tg3_setup_phy(tp
, 0);
8591 } else if ((tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
) &&
8592 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
8593 tg3_serdes_parallel_detect(tp
);
8596 tp
->timer_counter
= tp
->timer_multiplier
;
8599 /* Heartbeat is only sent once every 2 seconds.
8601 * The heartbeat is to tell the ASF firmware that the host
8602 * driver is still alive. In the event that the OS crashes,
8603 * ASF needs to reset the hardware to free up the FIFO space
8604 * that may be filled with rx packets destined for the host.
8605 * If the FIFO is full, ASF will no longer function properly.
8607 * Unintended resets have been reported on real time kernels
8608 * where the timer doesn't run on time. Netpoll will also have
8611 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8612 * to check the ring condition when the heartbeat is expiring
8613 * before doing the reset. This will prevent most unintended
8616 if (!--tp
->asf_counter
) {
8617 if ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) &&
8618 !(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)) {
8619 tg3_wait_for_event_ack(tp
);
8621 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_MBOX
,
8622 FWCMD_NICDRV_ALIVE3
);
8623 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_LEN_MBOX
, 4);
8624 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
,
8625 TG3_FW_UPDATE_TIMEOUT_SEC
);
8627 tg3_generate_fw_event(tp
);
8629 tp
->asf_counter
= tp
->asf_multiplier
;
8632 spin_unlock(&tp
->lock
);
8635 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
8636 add_timer(&tp
->timer
);
8639 static int tg3_request_irq(struct tg3
*tp
, int irq_num
)
8642 unsigned long flags
;
8644 struct tg3_napi
*tnapi
= &tp
->napi
[irq_num
];
8646 if (tp
->irq_cnt
== 1)
8647 name
= tp
->dev
->name
;
8649 name
= &tnapi
->irq_lbl
[0];
8650 snprintf(name
, IFNAMSIZ
, "%s-%d", tp
->dev
->name
, irq_num
);
8651 name
[IFNAMSIZ
-1] = 0;
8654 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI_OR_MSIX
) {
8656 if (tp
->tg3_flags2
& TG3_FLG2_1SHOT_MSI
)
8658 flags
= IRQF_SAMPLE_RANDOM
;
8661 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)
8662 fn
= tg3_interrupt_tagged
;
8663 flags
= IRQF_SHARED
| IRQF_SAMPLE_RANDOM
;
8666 return request_irq(tnapi
->irq_vec
, fn
, flags
, name
, tnapi
);
8669 static int tg3_test_interrupt(struct tg3
*tp
)
8671 struct tg3_napi
*tnapi
= &tp
->napi
[0];
8672 struct net_device
*dev
= tp
->dev
;
8673 int err
, i
, intr_ok
= 0;
8676 if (!netif_running(dev
))
8679 tg3_disable_ints(tp
);
8681 free_irq(tnapi
->irq_vec
, tnapi
);
8684 * Turn off MSI one shot mode. Otherwise this test has no
8685 * observable way to know whether the interrupt was delivered.
8687 if ((tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
) &&
8688 (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
)) {
8689 val
= tr32(MSGINT_MODE
) | MSGINT_MODE_ONE_SHOT_DISABLE
;
8690 tw32(MSGINT_MODE
, val
);
8693 err
= request_irq(tnapi
->irq_vec
, tg3_test_isr
,
8694 IRQF_SHARED
| IRQF_SAMPLE_RANDOM
, dev
->name
, tnapi
);
8698 tnapi
->hw_status
->status
&= ~SD_STATUS_UPDATED
;
8699 tg3_enable_ints(tp
);
8701 tw32_f(HOSTCC_MODE
, tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
|
8704 for (i
= 0; i
< 5; i
++) {
8705 u32 int_mbox
, misc_host_ctrl
;
8707 int_mbox
= tr32_mailbox(tnapi
->int_mbox
);
8708 misc_host_ctrl
= tr32(TG3PCI_MISC_HOST_CTRL
);
8710 if ((int_mbox
!= 0) ||
8711 (misc_host_ctrl
& MISC_HOST_CTRL_MASK_PCI_INT
)) {
8719 tg3_disable_ints(tp
);
8721 free_irq(tnapi
->irq_vec
, tnapi
);
8723 err
= tg3_request_irq(tp
, 0);
8729 /* Reenable MSI one shot mode. */
8730 if ((tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
) &&
8731 (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
)) {
8732 val
= tr32(MSGINT_MODE
) & ~MSGINT_MODE_ONE_SHOT_DISABLE
;
8733 tw32(MSGINT_MODE
, val
);
8741 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8742 * successfully restored
8744 static int tg3_test_msi(struct tg3
*tp
)
8749 if (!(tp
->tg3_flags2
& TG3_FLG2_USING_MSI
))
8752 /* Turn off SERR reporting in case MSI terminates with Master
8755 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
8756 pci_write_config_word(tp
->pdev
, PCI_COMMAND
,
8757 pci_cmd
& ~PCI_COMMAND_SERR
);
8759 err
= tg3_test_interrupt(tp
);
8761 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
8766 /* other failures */
8770 /* MSI test failed, go back to INTx mode */
8771 netdev_warn(tp
->dev
, "No interrupt was generated using MSI. Switching "
8772 "to INTx mode. Please report this failure to the PCI "
8773 "maintainer and include system chipset information\n");
8775 free_irq(tp
->napi
[0].irq_vec
, &tp
->napi
[0]);
8777 pci_disable_msi(tp
->pdev
);
8779 tp
->tg3_flags2
&= ~TG3_FLG2_USING_MSI
;
8780 tp
->napi
[0].irq_vec
= tp
->pdev
->irq
;
8782 err
= tg3_request_irq(tp
, 0);
8786 /* Need to reset the chip because the MSI cycle may have terminated
8787 * with Master Abort.
8789 tg3_full_lock(tp
, 1);
8791 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
8792 err
= tg3_init_hw(tp
, 1);
8794 tg3_full_unlock(tp
);
8797 free_irq(tp
->napi
[0].irq_vec
, &tp
->napi
[0]);
8802 static int tg3_request_firmware(struct tg3
*tp
)
8804 const __be32
*fw_data
;
8806 if (request_firmware(&tp
->fw
, tp
->fw_needed
, &tp
->pdev
->dev
)) {
8807 netdev_err(tp
->dev
, "Failed to load firmware \"%s\"\n",
8812 fw_data
= (void *)tp
->fw
->data
;
8814 /* Firmware blob starts with version numbers, followed by
8815 * start address and _full_ length including BSS sections
8816 * (which must be longer than the actual data, of course
8819 tp
->fw_len
= be32_to_cpu(fw_data
[2]); /* includes bss */
8820 if (tp
->fw_len
< (tp
->fw
->size
- 12)) {
8821 netdev_err(tp
->dev
, "bogus length %d in \"%s\"\n",
8822 tp
->fw_len
, tp
->fw_needed
);
8823 release_firmware(tp
->fw
);
8828 /* We no longer need firmware; we have it. */
8829 tp
->fw_needed
= NULL
;
8833 static bool tg3_enable_msix(struct tg3
*tp
)
8835 int i
, rc
, cpus
= num_online_cpus();
8836 struct msix_entry msix_ent
[tp
->irq_max
];
8839 /* Just fallback to the simpler MSI mode. */
8843 * We want as many rx rings enabled as there are cpus.
8844 * The first MSIX vector only deals with link interrupts, etc,
8845 * so we add one to the number of vectors we are requesting.
8847 tp
->irq_cnt
= min_t(unsigned, cpus
+ 1, tp
->irq_max
);
8849 for (i
= 0; i
< tp
->irq_max
; i
++) {
8850 msix_ent
[i
].entry
= i
;
8851 msix_ent
[i
].vector
= 0;
8854 rc
= pci_enable_msix(tp
->pdev
, msix_ent
, tp
->irq_cnt
);
8857 } else if (rc
!= 0) {
8858 if (pci_enable_msix(tp
->pdev
, msix_ent
, rc
))
8860 netdev_notice(tp
->dev
, "Requested %d MSI-X vectors, received %d\n",
8865 for (i
= 0; i
< tp
->irq_max
; i
++)
8866 tp
->napi
[i
].irq_vec
= msix_ent
[i
].vector
;
8868 netif_set_real_num_tx_queues(tp
->dev
, 1);
8869 rc
= tp
->irq_cnt
> 1 ? tp
->irq_cnt
- 1 : 1;
8870 if (netif_set_real_num_rx_queues(tp
->dev
, rc
)) {
8871 pci_disable_msix(tp
->pdev
);
8874 if (tp
->irq_cnt
> 1)
8875 tp
->tg3_flags3
|= TG3_FLG3_ENABLE_RSS
;
8880 static void tg3_ints_init(struct tg3
*tp
)
8882 if ((tp
->tg3_flags
& TG3_FLAG_SUPPORT_MSI_OR_MSIX
) &&
8883 !(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)) {
8884 /* All MSI supporting chips should support tagged
8885 * status. Assert that this is the case.
8887 netdev_warn(tp
->dev
,
8888 "MSI without TAGGED_STATUS? Not using MSI\n");
8892 if ((tp
->tg3_flags
& TG3_FLAG_SUPPORT_MSIX
) && tg3_enable_msix(tp
))
8893 tp
->tg3_flags2
|= TG3_FLG2_USING_MSIX
;
8894 else if ((tp
->tg3_flags
& TG3_FLAG_SUPPORT_MSI
) &&
8895 pci_enable_msi(tp
->pdev
) == 0)
8896 tp
->tg3_flags2
|= TG3_FLG2_USING_MSI
;
8898 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI_OR_MSIX
) {
8899 u32 msi_mode
= tr32(MSGINT_MODE
);
8900 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSIX
)
8901 msi_mode
|= MSGINT_MODE_MULTIVEC_EN
;
8902 tw32(MSGINT_MODE
, msi_mode
| MSGINT_MODE_ENABLE
);
8905 if (!(tp
->tg3_flags2
& TG3_FLG2_USING_MSIX
)) {
8907 tp
->napi
[0].irq_vec
= tp
->pdev
->irq
;
8908 netif_set_real_num_tx_queues(tp
->dev
, 1);
8912 static void tg3_ints_fini(struct tg3
*tp
)
8914 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSIX
)
8915 pci_disable_msix(tp
->pdev
);
8916 else if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
)
8917 pci_disable_msi(tp
->pdev
);
8918 tp
->tg3_flags2
&= ~TG3_FLG2_USING_MSI_OR_MSIX
;
8919 tp
->tg3_flags3
&= ~(TG3_FLG3_ENABLE_RSS
| TG3_FLG3_ENABLE_TSS
);
8922 static int tg3_open(struct net_device
*dev
)
8924 struct tg3
*tp
= netdev_priv(dev
);
8927 if (tp
->fw_needed
) {
8928 err
= tg3_request_firmware(tp
);
8929 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
) {
8933 netdev_warn(tp
->dev
, "TSO capability disabled\n");
8934 tp
->tg3_flags2
&= ~TG3_FLG2_TSO_CAPABLE
;
8935 } else if (!(tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
)) {
8936 netdev_notice(tp
->dev
, "TSO capability restored\n");
8937 tp
->tg3_flags2
|= TG3_FLG2_TSO_CAPABLE
;
8941 netif_carrier_off(tp
->dev
);
8943 err
= tg3_set_power_state(tp
, PCI_D0
);
8947 tg3_full_lock(tp
, 0);
8949 tg3_disable_ints(tp
);
8950 tp
->tg3_flags
&= ~TG3_FLAG_INIT_COMPLETE
;
8952 tg3_full_unlock(tp
);
8955 * Setup interrupts first so we know how
8956 * many NAPI resources to allocate
8960 /* The placement of this call is tied
8961 * to the setup and use of Host TX descriptors.
8963 err
= tg3_alloc_consistent(tp
);
8969 tg3_napi_enable(tp
);
8971 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
8972 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
8973 err
= tg3_request_irq(tp
, i
);
8975 for (i
--; i
>= 0; i
--)
8976 free_irq(tnapi
->irq_vec
, tnapi
);
8984 tg3_full_lock(tp
, 0);
8986 err
= tg3_init_hw(tp
, 1);
8988 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
8991 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)
8992 tp
->timer_offset
= HZ
;
8994 tp
->timer_offset
= HZ
/ 10;
8996 BUG_ON(tp
->timer_offset
> HZ
);
8997 tp
->timer_counter
= tp
->timer_multiplier
=
8998 (HZ
/ tp
->timer_offset
);
8999 tp
->asf_counter
= tp
->asf_multiplier
=
9000 ((HZ
/ tp
->timer_offset
) * 2);
9002 init_timer(&tp
->timer
);
9003 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
9004 tp
->timer
.data
= (unsigned long) tp
;
9005 tp
->timer
.function
= tg3_timer
;
9008 tg3_full_unlock(tp
);
9013 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
9014 err
= tg3_test_msi(tp
);
9017 tg3_full_lock(tp
, 0);
9018 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
9020 tg3_full_unlock(tp
);
9025 if (!(tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
) &&
9026 (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
)) {
9027 u32 val
= tr32(PCIE_TRANSACTION_CFG
);
9029 tw32(PCIE_TRANSACTION_CFG
,
9030 val
| PCIE_TRANS_CFG_1SHOT_MSI
);
9036 tg3_full_lock(tp
, 0);
9038 add_timer(&tp
->timer
);
9039 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
9040 tg3_enable_ints(tp
);
9042 tg3_full_unlock(tp
);
9044 netif_tx_start_all_queues(dev
);
9049 for (i
= tp
->irq_cnt
- 1; i
>= 0; i
--) {
9050 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
9051 free_irq(tnapi
->irq_vec
, tnapi
);
9055 tg3_napi_disable(tp
);
9057 tg3_free_consistent(tp
);
9064 static struct rtnl_link_stats64
*tg3_get_stats64(struct net_device
*,
9065 struct rtnl_link_stats64
*);
9066 static struct tg3_ethtool_stats
*tg3_get_estats(struct tg3
*);
9068 static int tg3_close(struct net_device
*dev
)
9071 struct tg3
*tp
= netdev_priv(dev
);
9073 tg3_napi_disable(tp
);
9074 cancel_work_sync(&tp
->reset_task
);
9076 netif_tx_stop_all_queues(dev
);
9078 del_timer_sync(&tp
->timer
);
9082 tg3_full_lock(tp
, 1);
9084 tg3_disable_ints(tp
);
9086 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
9088 tp
->tg3_flags
&= ~TG3_FLAG_INIT_COMPLETE
;
9090 tg3_full_unlock(tp
);
9092 for (i
= tp
->irq_cnt
- 1; i
>= 0; i
--) {
9093 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
9094 free_irq(tnapi
->irq_vec
, tnapi
);
9099 tg3_get_stats64(tp
->dev
, &tp
->net_stats_prev
);
9101 memcpy(&tp
->estats_prev
, tg3_get_estats(tp
),
9102 sizeof(tp
->estats_prev
));
9106 tg3_free_consistent(tp
);
9108 tg3_set_power_state(tp
, PCI_D3hot
);
9110 netif_carrier_off(tp
->dev
);
9115 static inline u64
get_stat64(tg3_stat64_t
*val
)
9117 return ((u64
)val
->high
<< 32) | ((u64
)val
->low
);
9120 static u64
calc_crc_errors(struct tg3
*tp
)
9122 struct tg3_hw_stats
*hw_stats
= tp
->hw_stats
;
9124 if (!(tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) &&
9125 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
9126 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)) {
9129 spin_lock_bh(&tp
->lock
);
9130 if (!tg3_readphy(tp
, MII_TG3_TEST1
, &val
)) {
9131 tg3_writephy(tp
, MII_TG3_TEST1
,
9132 val
| MII_TG3_TEST1_CRC_EN
);
9133 tg3_readphy(tp
, MII_TG3_RXR_COUNTERS
, &val
);
9136 spin_unlock_bh(&tp
->lock
);
9138 tp
->phy_crc_errors
+= val
;
9140 return tp
->phy_crc_errors
;
9143 return get_stat64(&hw_stats
->rx_fcs_errors
);
9146 #define ESTAT_ADD(member) \
9147 estats->member = old_estats->member + \
9148 get_stat64(&hw_stats->member)
9150 static struct tg3_ethtool_stats
*tg3_get_estats(struct tg3
*tp
)
9152 struct tg3_ethtool_stats
*estats
= &tp
->estats
;
9153 struct tg3_ethtool_stats
*old_estats
= &tp
->estats_prev
;
9154 struct tg3_hw_stats
*hw_stats
= tp
->hw_stats
;
9159 ESTAT_ADD(rx_octets
);
9160 ESTAT_ADD(rx_fragments
);
9161 ESTAT_ADD(rx_ucast_packets
);
9162 ESTAT_ADD(rx_mcast_packets
);
9163 ESTAT_ADD(rx_bcast_packets
);
9164 ESTAT_ADD(rx_fcs_errors
);
9165 ESTAT_ADD(rx_align_errors
);
9166 ESTAT_ADD(rx_xon_pause_rcvd
);
9167 ESTAT_ADD(rx_xoff_pause_rcvd
);
9168 ESTAT_ADD(rx_mac_ctrl_rcvd
);
9169 ESTAT_ADD(rx_xoff_entered
);
9170 ESTAT_ADD(rx_frame_too_long_errors
);
9171 ESTAT_ADD(rx_jabbers
);
9172 ESTAT_ADD(rx_undersize_packets
);
9173 ESTAT_ADD(rx_in_length_errors
);
9174 ESTAT_ADD(rx_out_length_errors
);
9175 ESTAT_ADD(rx_64_or_less_octet_packets
);
9176 ESTAT_ADD(rx_65_to_127_octet_packets
);
9177 ESTAT_ADD(rx_128_to_255_octet_packets
);
9178 ESTAT_ADD(rx_256_to_511_octet_packets
);
9179 ESTAT_ADD(rx_512_to_1023_octet_packets
);
9180 ESTAT_ADD(rx_1024_to_1522_octet_packets
);
9181 ESTAT_ADD(rx_1523_to_2047_octet_packets
);
9182 ESTAT_ADD(rx_2048_to_4095_octet_packets
);
9183 ESTAT_ADD(rx_4096_to_8191_octet_packets
);
9184 ESTAT_ADD(rx_8192_to_9022_octet_packets
);
9186 ESTAT_ADD(tx_octets
);
9187 ESTAT_ADD(tx_collisions
);
9188 ESTAT_ADD(tx_xon_sent
);
9189 ESTAT_ADD(tx_xoff_sent
);
9190 ESTAT_ADD(tx_flow_control
);
9191 ESTAT_ADD(tx_mac_errors
);
9192 ESTAT_ADD(tx_single_collisions
);
9193 ESTAT_ADD(tx_mult_collisions
);
9194 ESTAT_ADD(tx_deferred
);
9195 ESTAT_ADD(tx_excessive_collisions
);
9196 ESTAT_ADD(tx_late_collisions
);
9197 ESTAT_ADD(tx_collide_2times
);
9198 ESTAT_ADD(tx_collide_3times
);
9199 ESTAT_ADD(tx_collide_4times
);
9200 ESTAT_ADD(tx_collide_5times
);
9201 ESTAT_ADD(tx_collide_6times
);
9202 ESTAT_ADD(tx_collide_7times
);
9203 ESTAT_ADD(tx_collide_8times
);
9204 ESTAT_ADD(tx_collide_9times
);
9205 ESTAT_ADD(tx_collide_10times
);
9206 ESTAT_ADD(tx_collide_11times
);
9207 ESTAT_ADD(tx_collide_12times
);
9208 ESTAT_ADD(tx_collide_13times
);
9209 ESTAT_ADD(tx_collide_14times
);
9210 ESTAT_ADD(tx_collide_15times
);
9211 ESTAT_ADD(tx_ucast_packets
);
9212 ESTAT_ADD(tx_mcast_packets
);
9213 ESTAT_ADD(tx_bcast_packets
);
9214 ESTAT_ADD(tx_carrier_sense_errors
);
9215 ESTAT_ADD(tx_discards
);
9216 ESTAT_ADD(tx_errors
);
9218 ESTAT_ADD(dma_writeq_full
);
9219 ESTAT_ADD(dma_write_prioq_full
);
9220 ESTAT_ADD(rxbds_empty
);
9221 ESTAT_ADD(rx_discards
);
9222 ESTAT_ADD(rx_errors
);
9223 ESTAT_ADD(rx_threshold_hit
);
9225 ESTAT_ADD(dma_readq_full
);
9226 ESTAT_ADD(dma_read_prioq_full
);
9227 ESTAT_ADD(tx_comp_queue_full
);
9229 ESTAT_ADD(ring_set_send_prod_index
);
9230 ESTAT_ADD(ring_status_update
);
9231 ESTAT_ADD(nic_irqs
);
9232 ESTAT_ADD(nic_avoided_irqs
);
9233 ESTAT_ADD(nic_tx_threshold_hit
);
9238 static struct rtnl_link_stats64
*tg3_get_stats64(struct net_device
*dev
,
9239 struct rtnl_link_stats64
*stats
)
9241 struct tg3
*tp
= netdev_priv(dev
);
9242 struct rtnl_link_stats64
*old_stats
= &tp
->net_stats_prev
;
9243 struct tg3_hw_stats
*hw_stats
= tp
->hw_stats
;
9248 stats
->rx_packets
= old_stats
->rx_packets
+
9249 get_stat64(&hw_stats
->rx_ucast_packets
) +
9250 get_stat64(&hw_stats
->rx_mcast_packets
) +
9251 get_stat64(&hw_stats
->rx_bcast_packets
);
9253 stats
->tx_packets
= old_stats
->tx_packets
+
9254 get_stat64(&hw_stats
->tx_ucast_packets
) +
9255 get_stat64(&hw_stats
->tx_mcast_packets
) +
9256 get_stat64(&hw_stats
->tx_bcast_packets
);
9258 stats
->rx_bytes
= old_stats
->rx_bytes
+
9259 get_stat64(&hw_stats
->rx_octets
);
9260 stats
->tx_bytes
= old_stats
->tx_bytes
+
9261 get_stat64(&hw_stats
->tx_octets
);
9263 stats
->rx_errors
= old_stats
->rx_errors
+
9264 get_stat64(&hw_stats
->rx_errors
);
9265 stats
->tx_errors
= old_stats
->tx_errors
+
9266 get_stat64(&hw_stats
->tx_errors
) +
9267 get_stat64(&hw_stats
->tx_mac_errors
) +
9268 get_stat64(&hw_stats
->tx_carrier_sense_errors
) +
9269 get_stat64(&hw_stats
->tx_discards
);
9271 stats
->multicast
= old_stats
->multicast
+
9272 get_stat64(&hw_stats
->rx_mcast_packets
);
9273 stats
->collisions
= old_stats
->collisions
+
9274 get_stat64(&hw_stats
->tx_collisions
);
9276 stats
->rx_length_errors
= old_stats
->rx_length_errors
+
9277 get_stat64(&hw_stats
->rx_frame_too_long_errors
) +
9278 get_stat64(&hw_stats
->rx_undersize_packets
);
9280 stats
->rx_over_errors
= old_stats
->rx_over_errors
+
9281 get_stat64(&hw_stats
->rxbds_empty
);
9282 stats
->rx_frame_errors
= old_stats
->rx_frame_errors
+
9283 get_stat64(&hw_stats
->rx_align_errors
);
9284 stats
->tx_aborted_errors
= old_stats
->tx_aborted_errors
+
9285 get_stat64(&hw_stats
->tx_discards
);
9286 stats
->tx_carrier_errors
= old_stats
->tx_carrier_errors
+
9287 get_stat64(&hw_stats
->tx_carrier_sense_errors
);
9289 stats
->rx_crc_errors
= old_stats
->rx_crc_errors
+
9290 calc_crc_errors(tp
);
9292 stats
->rx_missed_errors
= old_stats
->rx_missed_errors
+
9293 get_stat64(&hw_stats
->rx_discards
);
9298 static inline u32
calc_crc(unsigned char *buf
, int len
)
9306 for (j
= 0; j
< len
; j
++) {
9309 for (k
= 0; k
< 8; k
++) {
9322 static void tg3_set_multi(struct tg3
*tp
, unsigned int accept_all
)
9324 /* accept or reject all multicast frames */
9325 tw32(MAC_HASH_REG_0
, accept_all
? 0xffffffff : 0);
9326 tw32(MAC_HASH_REG_1
, accept_all
? 0xffffffff : 0);
9327 tw32(MAC_HASH_REG_2
, accept_all
? 0xffffffff : 0);
9328 tw32(MAC_HASH_REG_3
, accept_all
? 0xffffffff : 0);
9331 static void __tg3_set_rx_mode(struct net_device
*dev
)
9333 struct tg3
*tp
= netdev_priv(dev
);
9336 rx_mode
= tp
->rx_mode
& ~(RX_MODE_PROMISC
|
9337 RX_MODE_KEEP_VLAN_TAG
);
9339 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9342 #if TG3_VLAN_TAG_USED
9344 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
9345 rx_mode
|= RX_MODE_KEEP_VLAN_TAG
;
9347 /* By definition, VLAN is disabled always in this
9350 if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
9351 rx_mode
|= RX_MODE_KEEP_VLAN_TAG
;
9354 if (dev
->flags
& IFF_PROMISC
) {
9355 /* Promiscuous mode. */
9356 rx_mode
|= RX_MODE_PROMISC
;
9357 } else if (dev
->flags
& IFF_ALLMULTI
) {
9358 /* Accept all multicast. */
9359 tg3_set_multi(tp
, 1);
9360 } else if (netdev_mc_empty(dev
)) {
9361 /* Reject all multicast. */
9362 tg3_set_multi(tp
, 0);
9364 /* Accept one or more multicast(s). */
9365 struct netdev_hw_addr
*ha
;
9366 u32 mc_filter
[4] = { 0, };
9371 netdev_for_each_mc_addr(ha
, dev
) {
9372 crc
= calc_crc(ha
->addr
, ETH_ALEN
);
9374 regidx
= (bit
& 0x60) >> 5;
9376 mc_filter
[regidx
] |= (1 << bit
);
9379 tw32(MAC_HASH_REG_0
, mc_filter
[0]);
9380 tw32(MAC_HASH_REG_1
, mc_filter
[1]);
9381 tw32(MAC_HASH_REG_2
, mc_filter
[2]);
9382 tw32(MAC_HASH_REG_3
, mc_filter
[3]);
9385 if (rx_mode
!= tp
->rx_mode
) {
9386 tp
->rx_mode
= rx_mode
;
9387 tw32_f(MAC_RX_MODE
, rx_mode
);
9392 static void tg3_set_rx_mode(struct net_device
*dev
)
9394 struct tg3
*tp
= netdev_priv(dev
);
9396 if (!netif_running(dev
))
9399 tg3_full_lock(tp
, 0);
9400 __tg3_set_rx_mode(dev
);
9401 tg3_full_unlock(tp
);
9404 #define TG3_REGDUMP_LEN (32 * 1024)
9406 static int tg3_get_regs_len(struct net_device
*dev
)
9408 return TG3_REGDUMP_LEN
;
9411 static void tg3_get_regs(struct net_device
*dev
,
9412 struct ethtool_regs
*regs
, void *_p
)
9415 struct tg3
*tp
= netdev_priv(dev
);
9421 memset(p
, 0, TG3_REGDUMP_LEN
);
9423 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)
9426 tg3_full_lock(tp
, 0);
9428 #define __GET_REG32(reg) (*(p)++ = tr32(reg))
9429 #define GET_REG32_LOOP(base, len) \
9430 do { p = (u32 *)(orig_p + (base)); \
9431 for (i = 0; i < len; i += 4) \
9432 __GET_REG32((base) + i); \
9434 #define GET_REG32_1(reg) \
9435 do { p = (u32 *)(orig_p + (reg)); \
9436 __GET_REG32((reg)); \
9439 GET_REG32_LOOP(TG3PCI_VENDOR
, 0xb0);
9440 GET_REG32_LOOP(MAILBOX_INTERRUPT_0
, 0x200);
9441 GET_REG32_LOOP(MAC_MODE
, 0x4f0);
9442 GET_REG32_LOOP(SNDDATAI_MODE
, 0xe0);
9443 GET_REG32_1(SNDDATAC_MODE
);
9444 GET_REG32_LOOP(SNDBDS_MODE
, 0x80);
9445 GET_REG32_LOOP(SNDBDI_MODE
, 0x48);
9446 GET_REG32_1(SNDBDC_MODE
);
9447 GET_REG32_LOOP(RCVLPC_MODE
, 0x20);
9448 GET_REG32_LOOP(RCVLPC_SELLST_BASE
, 0x15c);
9449 GET_REG32_LOOP(RCVDBDI_MODE
, 0x0c);
9450 GET_REG32_LOOP(RCVDBDI_JUMBO_BD
, 0x3c);
9451 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0
, 0x44);
9452 GET_REG32_1(RCVDCC_MODE
);
9453 GET_REG32_LOOP(RCVBDI_MODE
, 0x20);
9454 GET_REG32_LOOP(RCVCC_MODE
, 0x14);
9455 GET_REG32_LOOP(RCVLSC_MODE
, 0x08);
9456 GET_REG32_1(MBFREE_MODE
);
9457 GET_REG32_LOOP(HOSTCC_MODE
, 0x100);
9458 GET_REG32_LOOP(MEMARB_MODE
, 0x10);
9459 GET_REG32_LOOP(BUFMGR_MODE
, 0x58);
9460 GET_REG32_LOOP(RDMAC_MODE
, 0x08);
9461 GET_REG32_LOOP(WDMAC_MODE
, 0x08);
9462 GET_REG32_1(RX_CPU_MODE
);
9463 GET_REG32_1(RX_CPU_STATE
);
9464 GET_REG32_1(RX_CPU_PGMCTR
);
9465 GET_REG32_1(RX_CPU_HWBKPT
);
9466 GET_REG32_1(TX_CPU_MODE
);
9467 GET_REG32_1(TX_CPU_STATE
);
9468 GET_REG32_1(TX_CPU_PGMCTR
);
9469 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0
, 0x110);
9470 GET_REG32_LOOP(FTQ_RESET
, 0x120);
9471 GET_REG32_LOOP(MSGINT_MODE
, 0x0c);
9472 GET_REG32_1(DMAC_MODE
);
9473 GET_REG32_LOOP(GRC_MODE
, 0x4c);
9474 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
)
9475 GET_REG32_LOOP(NVRAM_CMD
, 0x24);
9478 #undef GET_REG32_LOOP
9481 tg3_full_unlock(tp
);
9484 static int tg3_get_eeprom_len(struct net_device
*dev
)
9486 struct tg3
*tp
= netdev_priv(dev
);
9488 return tp
->nvram_size
;
9491 static int tg3_get_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
, u8
*data
)
9493 struct tg3
*tp
= netdev_priv(dev
);
9496 u32 i
, offset
, len
, b_offset
, b_count
;
9499 if (tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
)
9502 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)
9505 offset
= eeprom
->offset
;
9509 eeprom
->magic
= TG3_EEPROM_MAGIC
;
9512 /* adjustments to start on required 4 byte boundary */
9513 b_offset
= offset
& 3;
9514 b_count
= 4 - b_offset
;
9515 if (b_count
> len
) {
9516 /* i.e. offset=1 len=2 */
9519 ret
= tg3_nvram_read_be32(tp
, offset
-b_offset
, &val
);
9522 memcpy(data
, ((char *)&val
) + b_offset
, b_count
);
9525 eeprom
->len
+= b_count
;
9528 /* read bytes upto the last 4 byte boundary */
9529 pd
= &data
[eeprom
->len
];
9530 for (i
= 0; i
< (len
- (len
& 3)); i
+= 4) {
9531 ret
= tg3_nvram_read_be32(tp
, offset
+ i
, &val
);
9536 memcpy(pd
+ i
, &val
, 4);
9541 /* read last bytes not ending on 4 byte boundary */
9542 pd
= &data
[eeprom
->len
];
9544 b_offset
= offset
+ len
- b_count
;
9545 ret
= tg3_nvram_read_be32(tp
, b_offset
, &val
);
9548 memcpy(pd
, &val
, b_count
);
9549 eeprom
->len
+= b_count
;
9554 static int tg3_nvram_write_block(struct tg3
*tp
, u32 offset
, u32 len
, u8
*buf
);
9556 static int tg3_set_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
, u8
*data
)
9558 struct tg3
*tp
= netdev_priv(dev
);
9560 u32 offset
, len
, b_offset
, odd_len
;
9564 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)
9567 if ((tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) ||
9568 eeprom
->magic
!= TG3_EEPROM_MAGIC
)
9571 offset
= eeprom
->offset
;
9574 if ((b_offset
= (offset
& 3))) {
9575 /* adjustments to start on required 4 byte boundary */
9576 ret
= tg3_nvram_read_be32(tp
, offset
-b_offset
, &start
);
9587 /* adjustments to end on required 4 byte boundary */
9589 len
= (len
+ 3) & ~3;
9590 ret
= tg3_nvram_read_be32(tp
, offset
+len
-4, &end
);
9596 if (b_offset
|| odd_len
) {
9597 buf
= kmalloc(len
, GFP_KERNEL
);
9601 memcpy(buf
, &start
, 4);
9603 memcpy(buf
+len
-4, &end
, 4);
9604 memcpy(buf
+ b_offset
, data
, eeprom
->len
);
9607 ret
= tg3_nvram_write_block(tp
, offset
, len
, buf
);
9615 static int tg3_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
9617 struct tg3
*tp
= netdev_priv(dev
);
9619 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
9620 struct phy_device
*phydev
;
9621 if (!(tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
))
9623 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
9624 return phy_ethtool_gset(phydev
, cmd
);
9627 cmd
->supported
= (SUPPORTED_Autoneg
);
9629 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
))
9630 cmd
->supported
|= (SUPPORTED_1000baseT_Half
|
9631 SUPPORTED_1000baseT_Full
);
9633 if (!(tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
)) {
9634 cmd
->supported
|= (SUPPORTED_100baseT_Half
|
9635 SUPPORTED_100baseT_Full
|
9636 SUPPORTED_10baseT_Half
|
9637 SUPPORTED_10baseT_Full
|
9639 cmd
->port
= PORT_TP
;
9641 cmd
->supported
|= SUPPORTED_FIBRE
;
9642 cmd
->port
= PORT_FIBRE
;
9645 cmd
->advertising
= tp
->link_config
.advertising
;
9646 if (netif_running(dev
)) {
9647 cmd
->speed
= tp
->link_config
.active_speed
;
9648 cmd
->duplex
= tp
->link_config
.active_duplex
;
9650 cmd
->phy_address
= tp
->phy_addr
;
9651 cmd
->transceiver
= XCVR_INTERNAL
;
9652 cmd
->autoneg
= tp
->link_config
.autoneg
;
9658 static int tg3_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
9660 struct tg3
*tp
= netdev_priv(dev
);
9662 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
9663 struct phy_device
*phydev
;
9664 if (!(tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
))
9666 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
9667 return phy_ethtool_sset(phydev
, cmd
);
9670 if (cmd
->autoneg
!= AUTONEG_ENABLE
&&
9671 cmd
->autoneg
!= AUTONEG_DISABLE
)
9674 if (cmd
->autoneg
== AUTONEG_DISABLE
&&
9675 cmd
->duplex
!= DUPLEX_FULL
&&
9676 cmd
->duplex
!= DUPLEX_HALF
)
9679 if (cmd
->autoneg
== AUTONEG_ENABLE
) {
9680 u32 mask
= ADVERTISED_Autoneg
|
9682 ADVERTISED_Asym_Pause
;
9684 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
))
9685 mask
|= ADVERTISED_1000baseT_Half
|
9686 ADVERTISED_1000baseT_Full
;
9688 if (!(tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
))
9689 mask
|= ADVERTISED_100baseT_Half
|
9690 ADVERTISED_100baseT_Full
|
9691 ADVERTISED_10baseT_Half
|
9692 ADVERTISED_10baseT_Full
|
9695 mask
|= ADVERTISED_FIBRE
;
9697 if (cmd
->advertising
& ~mask
)
9700 mask
&= (ADVERTISED_1000baseT_Half
|
9701 ADVERTISED_1000baseT_Full
|
9702 ADVERTISED_100baseT_Half
|
9703 ADVERTISED_100baseT_Full
|
9704 ADVERTISED_10baseT_Half
|
9705 ADVERTISED_10baseT_Full
);
9707 cmd
->advertising
&= mask
;
9709 if (tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
) {
9710 if (cmd
->speed
!= SPEED_1000
)
9713 if (cmd
->duplex
!= DUPLEX_FULL
)
9716 if (cmd
->speed
!= SPEED_100
&&
9717 cmd
->speed
!= SPEED_10
)
9722 tg3_full_lock(tp
, 0);
9724 tp
->link_config
.autoneg
= cmd
->autoneg
;
9725 if (cmd
->autoneg
== AUTONEG_ENABLE
) {
9726 tp
->link_config
.advertising
= (cmd
->advertising
|
9727 ADVERTISED_Autoneg
);
9728 tp
->link_config
.speed
= SPEED_INVALID
;
9729 tp
->link_config
.duplex
= DUPLEX_INVALID
;
9731 tp
->link_config
.advertising
= 0;
9732 tp
->link_config
.speed
= cmd
->speed
;
9733 tp
->link_config
.duplex
= cmd
->duplex
;
9736 tp
->link_config
.orig_speed
= tp
->link_config
.speed
;
9737 tp
->link_config
.orig_duplex
= tp
->link_config
.duplex
;
9738 tp
->link_config
.orig_autoneg
= tp
->link_config
.autoneg
;
9740 if (netif_running(dev
))
9741 tg3_setup_phy(tp
, 1);
9743 tg3_full_unlock(tp
);
9748 static void tg3_get_drvinfo(struct net_device
*dev
, struct ethtool_drvinfo
*info
)
9750 struct tg3
*tp
= netdev_priv(dev
);
9752 strcpy(info
->driver
, DRV_MODULE_NAME
);
9753 strcpy(info
->version
, DRV_MODULE_VERSION
);
9754 strcpy(info
->fw_version
, tp
->fw_ver
);
9755 strcpy(info
->bus_info
, pci_name(tp
->pdev
));
9758 static void tg3_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
9760 struct tg3
*tp
= netdev_priv(dev
);
9762 if ((tp
->tg3_flags
& TG3_FLAG_WOL_CAP
) &&
9763 device_can_wakeup(&tp
->pdev
->dev
))
9764 wol
->supported
= WAKE_MAGIC
;
9768 if ((tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
) &&
9769 device_can_wakeup(&tp
->pdev
->dev
))
9770 wol
->wolopts
= WAKE_MAGIC
;
9771 memset(&wol
->sopass
, 0, sizeof(wol
->sopass
));
9774 static int tg3_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
9776 struct tg3
*tp
= netdev_priv(dev
);
9777 struct device
*dp
= &tp
->pdev
->dev
;
9779 if (wol
->wolopts
& ~WAKE_MAGIC
)
9781 if ((wol
->wolopts
& WAKE_MAGIC
) &&
9782 !((tp
->tg3_flags
& TG3_FLAG_WOL_CAP
) && device_can_wakeup(dp
)))
9785 spin_lock_bh(&tp
->lock
);
9786 if (wol
->wolopts
& WAKE_MAGIC
) {
9787 tp
->tg3_flags
|= TG3_FLAG_WOL_ENABLE
;
9788 device_set_wakeup_enable(dp
, true);
9790 tp
->tg3_flags
&= ~TG3_FLAG_WOL_ENABLE
;
9791 device_set_wakeup_enable(dp
, false);
9793 spin_unlock_bh(&tp
->lock
);
9798 static u32
tg3_get_msglevel(struct net_device
*dev
)
9800 struct tg3
*tp
= netdev_priv(dev
);
9801 return tp
->msg_enable
;
9804 static void tg3_set_msglevel(struct net_device
*dev
, u32 value
)
9806 struct tg3
*tp
= netdev_priv(dev
);
9807 tp
->msg_enable
= value
;
9810 static int tg3_set_tso(struct net_device
*dev
, u32 value
)
9812 struct tg3
*tp
= netdev_priv(dev
);
9814 if (!(tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
)) {
9819 if ((dev
->features
& NETIF_F_IPV6_CSUM
) &&
9820 ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO_2
) ||
9821 (tp
->tg3_flags2
& TG3_FLG2_HW_TSO_3
))) {
9823 dev
->features
|= NETIF_F_TSO6
;
9824 if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO_3
) ||
9825 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
9826 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
9827 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
) ||
9828 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
9829 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
9830 dev
->features
|= NETIF_F_TSO_ECN
;
9832 dev
->features
&= ~(NETIF_F_TSO6
| NETIF_F_TSO_ECN
);
9834 return ethtool_op_set_tso(dev
, value
);
9837 static int tg3_nway_reset(struct net_device
*dev
)
9839 struct tg3
*tp
= netdev_priv(dev
);
9842 if (!netif_running(dev
))
9845 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
)
9848 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
9849 if (!(tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
))
9851 r
= phy_start_aneg(tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
]);
9855 spin_lock_bh(&tp
->lock
);
9857 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
9858 if (!tg3_readphy(tp
, MII_BMCR
, &bmcr
) &&
9859 ((bmcr
& BMCR_ANENABLE
) ||
9860 (tp
->phy_flags
& TG3_PHYFLG_PARALLEL_DETECT
))) {
9861 tg3_writephy(tp
, MII_BMCR
, bmcr
| BMCR_ANRESTART
|
9865 spin_unlock_bh(&tp
->lock
);
9871 static void tg3_get_ringparam(struct net_device
*dev
, struct ethtool_ringparam
*ering
)
9873 struct tg3
*tp
= netdev_priv(dev
);
9875 ering
->rx_max_pending
= tp
->rx_std_ring_mask
;
9876 ering
->rx_mini_max_pending
= 0;
9877 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
)
9878 ering
->rx_jumbo_max_pending
= tp
->rx_jmb_ring_mask
;
9880 ering
->rx_jumbo_max_pending
= 0;
9882 ering
->tx_max_pending
= TG3_TX_RING_SIZE
- 1;
9884 ering
->rx_pending
= tp
->rx_pending
;
9885 ering
->rx_mini_pending
= 0;
9886 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
)
9887 ering
->rx_jumbo_pending
= tp
->rx_jumbo_pending
;
9889 ering
->rx_jumbo_pending
= 0;
9891 ering
->tx_pending
= tp
->napi
[0].tx_pending
;
9894 static int tg3_set_ringparam(struct net_device
*dev
, struct ethtool_ringparam
*ering
)
9896 struct tg3
*tp
= netdev_priv(dev
);
9897 int i
, irq_sync
= 0, err
= 0;
9899 if ((ering
->rx_pending
> tp
->rx_std_ring_mask
) ||
9900 (ering
->rx_jumbo_pending
> tp
->rx_jmb_ring_mask
) ||
9901 (ering
->tx_pending
> TG3_TX_RING_SIZE
- 1) ||
9902 (ering
->tx_pending
<= MAX_SKB_FRAGS
) ||
9903 ((tp
->tg3_flags2
& TG3_FLG2_TSO_BUG
) &&
9904 (ering
->tx_pending
<= (MAX_SKB_FRAGS
* 3))))
9907 if (netif_running(dev
)) {
9913 tg3_full_lock(tp
, irq_sync
);
9915 tp
->rx_pending
= ering
->rx_pending
;
9917 if ((tp
->tg3_flags2
& TG3_FLG2_MAX_RXPEND_64
) &&
9918 tp
->rx_pending
> 63)
9919 tp
->rx_pending
= 63;
9920 tp
->rx_jumbo_pending
= ering
->rx_jumbo_pending
;
9922 for (i
= 0; i
< tp
->irq_max
; i
++)
9923 tp
->napi
[i
].tx_pending
= ering
->tx_pending
;
9925 if (netif_running(dev
)) {
9926 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
9927 err
= tg3_restart_hw(tp
, 1);
9929 tg3_netif_start(tp
);
9932 tg3_full_unlock(tp
);
9934 if (irq_sync
&& !err
)
9940 static void tg3_get_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
*epause
)
9942 struct tg3
*tp
= netdev_priv(dev
);
9944 epause
->autoneg
= (tp
->tg3_flags
& TG3_FLAG_PAUSE_AUTONEG
) != 0;
9946 if (tp
->link_config
.active_flowctrl
& FLOW_CTRL_RX
)
9947 epause
->rx_pause
= 1;
9949 epause
->rx_pause
= 0;
9951 if (tp
->link_config
.active_flowctrl
& FLOW_CTRL_TX
)
9952 epause
->tx_pause
= 1;
9954 epause
->tx_pause
= 0;
9957 static int tg3_set_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
*epause
)
9959 struct tg3
*tp
= netdev_priv(dev
);
9962 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
9964 struct phy_device
*phydev
;
9966 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
9968 if (!(phydev
->supported
& SUPPORTED_Pause
) ||
9969 (!(phydev
->supported
& SUPPORTED_Asym_Pause
) &&
9970 ((epause
->rx_pause
&& !epause
->tx_pause
) ||
9971 (!epause
->rx_pause
&& epause
->tx_pause
))))
9974 tp
->link_config
.flowctrl
= 0;
9975 if (epause
->rx_pause
) {
9976 tp
->link_config
.flowctrl
|= FLOW_CTRL_RX
;
9978 if (epause
->tx_pause
) {
9979 tp
->link_config
.flowctrl
|= FLOW_CTRL_TX
;
9980 newadv
= ADVERTISED_Pause
;
9982 newadv
= ADVERTISED_Pause
|
9983 ADVERTISED_Asym_Pause
;
9984 } else if (epause
->tx_pause
) {
9985 tp
->link_config
.flowctrl
|= FLOW_CTRL_TX
;
9986 newadv
= ADVERTISED_Asym_Pause
;
9990 if (epause
->autoneg
)
9991 tp
->tg3_flags
|= TG3_FLAG_PAUSE_AUTONEG
;
9993 tp
->tg3_flags
&= ~TG3_FLAG_PAUSE_AUTONEG
;
9995 if (tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
) {
9996 u32 oldadv
= phydev
->advertising
&
9997 (ADVERTISED_Pause
| ADVERTISED_Asym_Pause
);
9998 if (oldadv
!= newadv
) {
9999 phydev
->advertising
&=
10000 ~(ADVERTISED_Pause
|
10001 ADVERTISED_Asym_Pause
);
10002 phydev
->advertising
|= newadv
;
10003 if (phydev
->autoneg
) {
10005 * Always renegotiate the link to
10006 * inform our link partner of our
10007 * flow control settings, even if the
10008 * flow control is forced. Let
10009 * tg3_adjust_link() do the final
10010 * flow control setup.
10012 return phy_start_aneg(phydev
);
10016 if (!epause
->autoneg
)
10017 tg3_setup_flow_control(tp
, 0, 0);
10019 tp
->link_config
.orig_advertising
&=
10020 ~(ADVERTISED_Pause
|
10021 ADVERTISED_Asym_Pause
);
10022 tp
->link_config
.orig_advertising
|= newadv
;
10027 if (netif_running(dev
)) {
10028 tg3_netif_stop(tp
);
10032 tg3_full_lock(tp
, irq_sync
);
10034 if (epause
->autoneg
)
10035 tp
->tg3_flags
|= TG3_FLAG_PAUSE_AUTONEG
;
10037 tp
->tg3_flags
&= ~TG3_FLAG_PAUSE_AUTONEG
;
10038 if (epause
->rx_pause
)
10039 tp
->link_config
.flowctrl
|= FLOW_CTRL_RX
;
10041 tp
->link_config
.flowctrl
&= ~FLOW_CTRL_RX
;
10042 if (epause
->tx_pause
)
10043 tp
->link_config
.flowctrl
|= FLOW_CTRL_TX
;
10045 tp
->link_config
.flowctrl
&= ~FLOW_CTRL_TX
;
10047 if (netif_running(dev
)) {
10048 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
10049 err
= tg3_restart_hw(tp
, 1);
10051 tg3_netif_start(tp
);
10054 tg3_full_unlock(tp
);
10060 static u32
tg3_get_rx_csum(struct net_device
*dev
)
10062 struct tg3
*tp
= netdev_priv(dev
);
10063 return (tp
->tg3_flags
& TG3_FLAG_RX_CHECKSUMS
) != 0;
10066 static int tg3_set_rx_csum(struct net_device
*dev
, u32 data
)
10068 struct tg3
*tp
= netdev_priv(dev
);
10070 if (tp
->tg3_flags
& TG3_FLAG_BROKEN_CHECKSUMS
) {
10076 spin_lock_bh(&tp
->lock
);
10078 tp
->tg3_flags
|= TG3_FLAG_RX_CHECKSUMS
;
10080 tp
->tg3_flags
&= ~TG3_FLAG_RX_CHECKSUMS
;
10081 spin_unlock_bh(&tp
->lock
);
10086 static int tg3_set_tx_csum(struct net_device
*dev
, u32 data
)
10088 struct tg3
*tp
= netdev_priv(dev
);
10090 if (tp
->tg3_flags
& TG3_FLAG_BROKEN_CHECKSUMS
) {
10096 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
10097 ethtool_op_set_tx_ipv6_csum(dev
, data
);
10099 ethtool_op_set_tx_csum(dev
, data
);
10104 static int tg3_get_sset_count(struct net_device
*dev
, int sset
)
10108 return TG3_NUM_TEST
;
10110 return TG3_NUM_STATS
;
10112 return -EOPNOTSUPP
;
10116 static void tg3_get_strings(struct net_device
*dev
, u32 stringset
, u8
*buf
)
10118 switch (stringset
) {
10120 memcpy(buf
, ðtool_stats_keys
, sizeof(ethtool_stats_keys
));
10123 memcpy(buf
, ðtool_test_keys
, sizeof(ethtool_test_keys
));
10126 WARN_ON(1); /* we need a WARN() */
10131 static int tg3_phys_id(struct net_device
*dev
, u32 data
)
10133 struct tg3
*tp
= netdev_priv(dev
);
10136 if (!netif_running(tp
->dev
))
10140 data
= UINT_MAX
/ 2;
10142 for (i
= 0; i
< (data
* 2); i
++) {
10144 tw32(MAC_LED_CTRL
, LED_CTRL_LNKLED_OVERRIDE
|
10145 LED_CTRL_1000MBPS_ON
|
10146 LED_CTRL_100MBPS_ON
|
10147 LED_CTRL_10MBPS_ON
|
10148 LED_CTRL_TRAFFIC_OVERRIDE
|
10149 LED_CTRL_TRAFFIC_BLINK
|
10150 LED_CTRL_TRAFFIC_LED
);
10153 tw32(MAC_LED_CTRL
, LED_CTRL_LNKLED_OVERRIDE
|
10154 LED_CTRL_TRAFFIC_OVERRIDE
);
10156 if (msleep_interruptible(500))
10159 tw32(MAC_LED_CTRL
, tp
->led_ctrl
);
10163 static void tg3_get_ethtool_stats(struct net_device
*dev
,
10164 struct ethtool_stats
*estats
, u64
*tmp_stats
)
10166 struct tg3
*tp
= netdev_priv(dev
);
10167 memcpy(tmp_stats
, tg3_get_estats(tp
), sizeof(tp
->estats
));
10170 #define NVRAM_TEST_SIZE 0x100
10171 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
10172 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
10173 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
10174 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10175 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10177 static int tg3_test_nvram(struct tg3
*tp
)
10181 int i
, j
, k
, err
= 0, size
;
10183 if (tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
)
10186 if (tg3_nvram_read(tp
, 0, &magic
) != 0)
10189 if (magic
== TG3_EEPROM_MAGIC
)
10190 size
= NVRAM_TEST_SIZE
;
10191 else if ((magic
& TG3_EEPROM_MAGIC_FW_MSK
) == TG3_EEPROM_MAGIC_FW
) {
10192 if ((magic
& TG3_EEPROM_SB_FORMAT_MASK
) ==
10193 TG3_EEPROM_SB_FORMAT_1
) {
10194 switch (magic
& TG3_EEPROM_SB_REVISION_MASK
) {
10195 case TG3_EEPROM_SB_REVISION_0
:
10196 size
= NVRAM_SELFBOOT_FORMAT1_0_SIZE
;
10198 case TG3_EEPROM_SB_REVISION_2
:
10199 size
= NVRAM_SELFBOOT_FORMAT1_2_SIZE
;
10201 case TG3_EEPROM_SB_REVISION_3
:
10202 size
= NVRAM_SELFBOOT_FORMAT1_3_SIZE
;
10209 } else if ((magic
& TG3_EEPROM_MAGIC_HW_MSK
) == TG3_EEPROM_MAGIC_HW
)
10210 size
= NVRAM_SELFBOOT_HW_SIZE
;
10214 buf
= kmalloc(size
, GFP_KERNEL
);
10219 for (i
= 0, j
= 0; i
< size
; i
+= 4, j
++) {
10220 err
= tg3_nvram_read_be32(tp
, i
, &buf
[j
]);
10227 /* Selfboot format */
10228 magic
= be32_to_cpu(buf
[0]);
10229 if ((magic
& TG3_EEPROM_MAGIC_FW_MSK
) ==
10230 TG3_EEPROM_MAGIC_FW
) {
10231 u8
*buf8
= (u8
*) buf
, csum8
= 0;
10233 if ((magic
& TG3_EEPROM_SB_REVISION_MASK
) ==
10234 TG3_EEPROM_SB_REVISION_2
) {
10235 /* For rev 2, the csum doesn't include the MBA. */
10236 for (i
= 0; i
< TG3_EEPROM_SB_F1R2_MBA_OFF
; i
++)
10238 for (i
= TG3_EEPROM_SB_F1R2_MBA_OFF
+ 4; i
< size
; i
++)
10241 for (i
= 0; i
< size
; i
++)
10254 if ((magic
& TG3_EEPROM_MAGIC_HW_MSK
) ==
10255 TG3_EEPROM_MAGIC_HW
) {
10256 u8 data
[NVRAM_SELFBOOT_DATA_SIZE
];
10257 u8 parity
[NVRAM_SELFBOOT_DATA_SIZE
];
10258 u8
*buf8
= (u8
*) buf
;
10260 /* Separate the parity bits and the data bytes. */
10261 for (i
= 0, j
= 0, k
= 0; i
< NVRAM_SELFBOOT_HW_SIZE
; i
++) {
10262 if ((i
== 0) || (i
== 8)) {
10266 for (l
= 0, msk
= 0x80; l
< 7; l
++, msk
>>= 1)
10267 parity
[k
++] = buf8
[i
] & msk
;
10269 } else if (i
== 16) {
10273 for (l
= 0, msk
= 0x20; l
< 6; l
++, msk
>>= 1)
10274 parity
[k
++] = buf8
[i
] & msk
;
10277 for (l
= 0, msk
= 0x80; l
< 8; l
++, msk
>>= 1)
10278 parity
[k
++] = buf8
[i
] & msk
;
10281 data
[j
++] = buf8
[i
];
10285 for (i
= 0; i
< NVRAM_SELFBOOT_DATA_SIZE
; i
++) {
10286 u8 hw8
= hweight8(data
[i
]);
10288 if ((hw8
& 0x1) && parity
[i
])
10290 else if (!(hw8
& 0x1) && !parity
[i
])
10297 /* Bootstrap checksum at offset 0x10 */
10298 csum
= calc_crc((unsigned char *) buf
, 0x10);
10299 if (csum
!= be32_to_cpu(buf
[0x10/4]))
10302 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10303 csum
= calc_crc((unsigned char *) &buf
[0x74/4], 0x88);
10304 if (csum
!= be32_to_cpu(buf
[0xfc/4]))
10314 #define TG3_SERDES_TIMEOUT_SEC 2
10315 #define TG3_COPPER_TIMEOUT_SEC 6
10317 static int tg3_test_link(struct tg3
*tp
)
10321 if (!netif_running(tp
->dev
))
10324 if (tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
)
10325 max
= TG3_SERDES_TIMEOUT_SEC
;
10327 max
= TG3_COPPER_TIMEOUT_SEC
;
10329 for (i
= 0; i
< max
; i
++) {
10330 if (netif_carrier_ok(tp
->dev
))
10333 if (msleep_interruptible(1000))
10340 /* Only test the commonly used registers */
10341 static int tg3_test_registers(struct tg3
*tp
)
10343 int i
, is_5705
, is_5750
;
10344 u32 offset
, read_mask
, write_mask
, val
, save_val
, read_val
;
10348 #define TG3_FL_5705 0x1
10349 #define TG3_FL_NOT_5705 0x2
10350 #define TG3_FL_NOT_5788 0x4
10351 #define TG3_FL_NOT_5750 0x8
10355 /* MAC Control Registers */
10356 { MAC_MODE
, TG3_FL_NOT_5705
,
10357 0x00000000, 0x00ef6f8c },
10358 { MAC_MODE
, TG3_FL_5705
,
10359 0x00000000, 0x01ef6b8c },
10360 { MAC_STATUS
, TG3_FL_NOT_5705
,
10361 0x03800107, 0x00000000 },
10362 { MAC_STATUS
, TG3_FL_5705
,
10363 0x03800100, 0x00000000 },
10364 { MAC_ADDR_0_HIGH
, 0x0000,
10365 0x00000000, 0x0000ffff },
10366 { MAC_ADDR_0_LOW
, 0x0000,
10367 0x00000000, 0xffffffff },
10368 { MAC_RX_MTU_SIZE
, 0x0000,
10369 0x00000000, 0x0000ffff },
10370 { MAC_TX_MODE
, 0x0000,
10371 0x00000000, 0x00000070 },
10372 { MAC_TX_LENGTHS
, 0x0000,
10373 0x00000000, 0x00003fff },
10374 { MAC_RX_MODE
, TG3_FL_NOT_5705
,
10375 0x00000000, 0x000007fc },
10376 { MAC_RX_MODE
, TG3_FL_5705
,
10377 0x00000000, 0x000007dc },
10378 { MAC_HASH_REG_0
, 0x0000,
10379 0x00000000, 0xffffffff },
10380 { MAC_HASH_REG_1
, 0x0000,
10381 0x00000000, 0xffffffff },
10382 { MAC_HASH_REG_2
, 0x0000,
10383 0x00000000, 0xffffffff },
10384 { MAC_HASH_REG_3
, 0x0000,
10385 0x00000000, 0xffffffff },
10387 /* Receive Data and Receive BD Initiator Control Registers. */
10388 { RCVDBDI_JUMBO_BD
+0, TG3_FL_NOT_5705
,
10389 0x00000000, 0xffffffff },
10390 { RCVDBDI_JUMBO_BD
+4, TG3_FL_NOT_5705
,
10391 0x00000000, 0xffffffff },
10392 { RCVDBDI_JUMBO_BD
+8, TG3_FL_NOT_5705
,
10393 0x00000000, 0x00000003 },
10394 { RCVDBDI_JUMBO_BD
+0xc, TG3_FL_NOT_5705
,
10395 0x00000000, 0xffffffff },
10396 { RCVDBDI_STD_BD
+0, 0x0000,
10397 0x00000000, 0xffffffff },
10398 { RCVDBDI_STD_BD
+4, 0x0000,
10399 0x00000000, 0xffffffff },
10400 { RCVDBDI_STD_BD
+8, 0x0000,
10401 0x00000000, 0xffff0002 },
10402 { RCVDBDI_STD_BD
+0xc, 0x0000,
10403 0x00000000, 0xffffffff },
10405 /* Receive BD Initiator Control Registers. */
10406 { RCVBDI_STD_THRESH
, TG3_FL_NOT_5705
,
10407 0x00000000, 0xffffffff },
10408 { RCVBDI_STD_THRESH
, TG3_FL_5705
,
10409 0x00000000, 0x000003ff },
10410 { RCVBDI_JUMBO_THRESH
, TG3_FL_NOT_5705
,
10411 0x00000000, 0xffffffff },
10413 /* Host Coalescing Control Registers. */
10414 { HOSTCC_MODE
, TG3_FL_NOT_5705
,
10415 0x00000000, 0x00000004 },
10416 { HOSTCC_MODE
, TG3_FL_5705
,
10417 0x00000000, 0x000000f6 },
10418 { HOSTCC_RXCOL_TICKS
, TG3_FL_NOT_5705
,
10419 0x00000000, 0xffffffff },
10420 { HOSTCC_RXCOL_TICKS
, TG3_FL_5705
,
10421 0x00000000, 0x000003ff },
10422 { HOSTCC_TXCOL_TICKS
, TG3_FL_NOT_5705
,
10423 0x00000000, 0xffffffff },
10424 { HOSTCC_TXCOL_TICKS
, TG3_FL_5705
,
10425 0x00000000, 0x000003ff },
10426 { HOSTCC_RXMAX_FRAMES
, TG3_FL_NOT_5705
,
10427 0x00000000, 0xffffffff },
10428 { HOSTCC_RXMAX_FRAMES
, TG3_FL_5705
| TG3_FL_NOT_5788
,
10429 0x00000000, 0x000000ff },
10430 { HOSTCC_TXMAX_FRAMES
, TG3_FL_NOT_5705
,
10431 0x00000000, 0xffffffff },
10432 { HOSTCC_TXMAX_FRAMES
, TG3_FL_5705
| TG3_FL_NOT_5788
,
10433 0x00000000, 0x000000ff },
10434 { HOSTCC_RXCOAL_TICK_INT
, TG3_FL_NOT_5705
,
10435 0x00000000, 0xffffffff },
10436 { HOSTCC_TXCOAL_TICK_INT
, TG3_FL_NOT_5705
,
10437 0x00000000, 0xffffffff },
10438 { HOSTCC_RXCOAL_MAXF_INT
, TG3_FL_NOT_5705
,
10439 0x00000000, 0xffffffff },
10440 { HOSTCC_RXCOAL_MAXF_INT
, TG3_FL_5705
| TG3_FL_NOT_5788
,
10441 0x00000000, 0x000000ff },
10442 { HOSTCC_TXCOAL_MAXF_INT
, TG3_FL_NOT_5705
,
10443 0x00000000, 0xffffffff },
10444 { HOSTCC_TXCOAL_MAXF_INT
, TG3_FL_5705
| TG3_FL_NOT_5788
,
10445 0x00000000, 0x000000ff },
10446 { HOSTCC_STAT_COAL_TICKS
, TG3_FL_NOT_5705
,
10447 0x00000000, 0xffffffff },
10448 { HOSTCC_STATS_BLK_HOST_ADDR
, TG3_FL_NOT_5705
,
10449 0x00000000, 0xffffffff },
10450 { HOSTCC_STATS_BLK_HOST_ADDR
+4, TG3_FL_NOT_5705
,
10451 0x00000000, 0xffffffff },
10452 { HOSTCC_STATUS_BLK_HOST_ADDR
, 0x0000,
10453 0x00000000, 0xffffffff },
10454 { HOSTCC_STATUS_BLK_HOST_ADDR
+4, 0x0000,
10455 0x00000000, 0xffffffff },
10456 { HOSTCC_STATS_BLK_NIC_ADDR
, 0x0000,
10457 0xffffffff, 0x00000000 },
10458 { HOSTCC_STATUS_BLK_NIC_ADDR
, 0x0000,
10459 0xffffffff, 0x00000000 },
10461 /* Buffer Manager Control Registers. */
10462 { BUFMGR_MB_POOL_ADDR
, TG3_FL_NOT_5750
,
10463 0x00000000, 0x007fff80 },
10464 { BUFMGR_MB_POOL_SIZE
, TG3_FL_NOT_5750
,
10465 0x00000000, 0x007fffff },
10466 { BUFMGR_MB_RDMA_LOW_WATER
, 0x0000,
10467 0x00000000, 0x0000003f },
10468 { BUFMGR_MB_MACRX_LOW_WATER
, 0x0000,
10469 0x00000000, 0x000001ff },
10470 { BUFMGR_MB_HIGH_WATER
, 0x0000,
10471 0x00000000, 0x000001ff },
10472 { BUFMGR_DMA_DESC_POOL_ADDR
, TG3_FL_NOT_5705
,
10473 0xffffffff, 0x00000000 },
10474 { BUFMGR_DMA_DESC_POOL_SIZE
, TG3_FL_NOT_5705
,
10475 0xffffffff, 0x00000000 },
10477 /* Mailbox Registers */
10478 { GRCMBOX_RCVSTD_PROD_IDX
+4, 0x0000,
10479 0x00000000, 0x000001ff },
10480 { GRCMBOX_RCVJUMBO_PROD_IDX
+4, TG3_FL_NOT_5705
,
10481 0x00000000, 0x000001ff },
10482 { GRCMBOX_RCVRET_CON_IDX_0
+4, 0x0000,
10483 0x00000000, 0x000007ff },
10484 { GRCMBOX_SNDHOST_PROD_IDX_0
+4, 0x0000,
10485 0x00000000, 0x000001ff },
10487 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10490 is_5705
= is_5750
= 0;
10491 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
10493 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
10497 for (i
= 0; reg_tbl
[i
].offset
!= 0xffff; i
++) {
10498 if (is_5705
&& (reg_tbl
[i
].flags
& TG3_FL_NOT_5705
))
10501 if (!is_5705
&& (reg_tbl
[i
].flags
& TG3_FL_5705
))
10504 if ((tp
->tg3_flags2
& TG3_FLG2_IS_5788
) &&
10505 (reg_tbl
[i
].flags
& TG3_FL_NOT_5788
))
10508 if (is_5750
&& (reg_tbl
[i
].flags
& TG3_FL_NOT_5750
))
10511 offset
= (u32
) reg_tbl
[i
].offset
;
10512 read_mask
= reg_tbl
[i
].read_mask
;
10513 write_mask
= reg_tbl
[i
].write_mask
;
10515 /* Save the original register content */
10516 save_val
= tr32(offset
);
10518 /* Determine the read-only value. */
10519 read_val
= save_val
& read_mask
;
10521 /* Write zero to the register, then make sure the read-only bits
10522 * are not changed and the read/write bits are all zeros.
10526 val
= tr32(offset
);
10528 /* Test the read-only and read/write bits. */
10529 if (((val
& read_mask
) != read_val
) || (val
& write_mask
))
10532 /* Write ones to all the bits defined by RdMask and WrMask, then
10533 * make sure the read-only bits are not changed and the
10534 * read/write bits are all ones.
10536 tw32(offset
, read_mask
| write_mask
);
10538 val
= tr32(offset
);
10540 /* Test the read-only bits. */
10541 if ((val
& read_mask
) != read_val
)
10544 /* Test the read/write bits. */
10545 if ((val
& write_mask
) != write_mask
)
10548 tw32(offset
, save_val
);
10554 if (netif_msg_hw(tp
))
10555 netdev_err(tp
->dev
,
10556 "Register test failed at offset %x\n", offset
);
10557 tw32(offset
, save_val
);
10561 static int tg3_do_mem_test(struct tg3
*tp
, u32 offset
, u32 len
)
10563 static const u32 test_pattern
[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10567 for (i
= 0; i
< ARRAY_SIZE(test_pattern
); i
++) {
10568 for (j
= 0; j
< len
; j
+= 4) {
10571 tg3_write_mem(tp
, offset
+ j
, test_pattern
[i
]);
10572 tg3_read_mem(tp
, offset
+ j
, &val
);
10573 if (val
!= test_pattern
[i
])
10580 static int tg3_test_memory(struct tg3
*tp
)
10582 static struct mem_entry
{
10585 } mem_tbl_570x
[] = {
10586 { 0x00000000, 0x00b50},
10587 { 0x00002000, 0x1c000},
10588 { 0xffffffff, 0x00000}
10589 }, mem_tbl_5705
[] = {
10590 { 0x00000100, 0x0000c},
10591 { 0x00000200, 0x00008},
10592 { 0x00004000, 0x00800},
10593 { 0x00006000, 0x01000},
10594 { 0x00008000, 0x02000},
10595 { 0x00010000, 0x0e000},
10596 { 0xffffffff, 0x00000}
10597 }, mem_tbl_5755
[] = {
10598 { 0x00000200, 0x00008},
10599 { 0x00004000, 0x00800},
10600 { 0x00006000, 0x00800},
10601 { 0x00008000, 0x02000},
10602 { 0x00010000, 0x0c000},
10603 { 0xffffffff, 0x00000}
10604 }, mem_tbl_5906
[] = {
10605 { 0x00000200, 0x00008},
10606 { 0x00004000, 0x00400},
10607 { 0x00006000, 0x00400},
10608 { 0x00008000, 0x01000},
10609 { 0x00010000, 0x01000},
10610 { 0xffffffff, 0x00000}
10611 }, mem_tbl_5717
[] = {
10612 { 0x00000200, 0x00008},
10613 { 0x00010000, 0x0a000},
10614 { 0x00020000, 0x13c00},
10615 { 0xffffffff, 0x00000}
10616 }, mem_tbl_57765
[] = {
10617 { 0x00000200, 0x00008},
10618 { 0x00004000, 0x00800},
10619 { 0x00006000, 0x09800},
10620 { 0x00010000, 0x0a000},
10621 { 0xffffffff, 0x00000}
10623 struct mem_entry
*mem_tbl
;
10627 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
10628 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
)
10629 mem_tbl
= mem_tbl_5717
;
10630 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
10631 mem_tbl
= mem_tbl_57765
;
10632 else if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
10633 mem_tbl
= mem_tbl_5755
;
10634 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
10635 mem_tbl
= mem_tbl_5906
;
10636 else if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
10637 mem_tbl
= mem_tbl_5705
;
10639 mem_tbl
= mem_tbl_570x
;
10641 for (i
= 0; mem_tbl
[i
].offset
!= 0xffffffff; i
++) {
10642 err
= tg3_do_mem_test(tp
, mem_tbl
[i
].offset
, mem_tbl
[i
].len
);
10650 #define TG3_MAC_LOOPBACK 0
10651 #define TG3_PHY_LOOPBACK 1
10653 static int tg3_run_loopback(struct tg3
*tp
, int loopback_mode
)
10655 u32 mac_mode
, rx_start_idx
, rx_idx
, tx_idx
, opaque_key
;
10656 u32 desc_idx
, coal_now
;
10657 struct sk_buff
*skb
, *rx_skb
;
10660 int num_pkts
, tx_len
, rx_len
, i
, err
;
10661 struct tg3_rx_buffer_desc
*desc
;
10662 struct tg3_napi
*tnapi
, *rnapi
;
10663 struct tg3_rx_prodring_set
*tpr
= &tp
->napi
[0].prodring
;
10665 tnapi
= &tp
->napi
[0];
10666 rnapi
= &tp
->napi
[0];
10667 if (tp
->irq_cnt
> 1) {
10668 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_RSS
)
10669 rnapi
= &tp
->napi
[1];
10670 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)
10671 tnapi
= &tp
->napi
[1];
10673 coal_now
= tnapi
->coal_now
| rnapi
->coal_now
;
10675 if (loopback_mode
== TG3_MAC_LOOPBACK
) {
10676 /* HW errata - mac loopback fails in some cases on 5780.
10677 * Normal traffic and PHY loopback are not affected by
10680 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5780
)
10683 mac_mode
= (tp
->mac_mode
& ~MAC_MODE_PORT_MODE_MASK
) |
10684 MAC_MODE_PORT_INT_LPBACK
;
10685 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
10686 mac_mode
|= MAC_MODE_LINK_POLARITY
;
10687 if (tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
)
10688 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
10690 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
10691 tw32(MAC_MODE
, mac_mode
);
10692 } else if (loopback_mode
== TG3_PHY_LOOPBACK
) {
10695 if (tp
->phy_flags
& TG3_PHYFLG_IS_FET
) {
10696 tg3_phy_fet_toggle_apd(tp
, false);
10697 val
= BMCR_LOOPBACK
| BMCR_FULLDPLX
| BMCR_SPEED100
;
10699 val
= BMCR_LOOPBACK
| BMCR_FULLDPLX
| BMCR_SPEED1000
;
10701 tg3_phy_toggle_automdix(tp
, 0);
10703 tg3_writephy(tp
, MII_BMCR
, val
);
10706 mac_mode
= tp
->mac_mode
& ~MAC_MODE_PORT_MODE_MASK
;
10707 if (tp
->phy_flags
& TG3_PHYFLG_IS_FET
) {
10708 tg3_writephy(tp
, MII_TG3_FET_PTEST
,
10709 MII_TG3_FET_PTEST_FRC_TX_LINK
|
10710 MII_TG3_FET_PTEST_FRC_TX_LOCK
);
10711 /* The write needs to be flushed for the AC131 */
10712 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
10713 tg3_readphy(tp
, MII_TG3_FET_PTEST
, &val
);
10714 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
10716 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
10718 /* reset to prevent losing 1st rx packet intermittently */
10719 if (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
) {
10720 tw32_f(MAC_RX_MODE
, RX_MODE_RESET
);
10722 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
10724 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) {
10725 u32 masked_phy_id
= tp
->phy_id
& TG3_PHY_ID_MASK
;
10726 if (masked_phy_id
== TG3_PHY_ID_BCM5401
)
10727 mac_mode
&= ~MAC_MODE_LINK_POLARITY
;
10728 else if (masked_phy_id
== TG3_PHY_ID_BCM5411
)
10729 mac_mode
|= MAC_MODE_LINK_POLARITY
;
10730 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
10731 MII_TG3_EXT_CTRL_LNK3_LED_MODE
);
10733 tw32(MAC_MODE
, mac_mode
);
10741 skb
= netdev_alloc_skb(tp
->dev
, tx_len
);
10745 tx_data
= skb_put(skb
, tx_len
);
10746 memcpy(tx_data
, tp
->dev
->dev_addr
, 6);
10747 memset(tx_data
+ 6, 0x0, 8);
10749 tw32(MAC_RX_MTU_SIZE
, tx_len
+ 4);
10751 for (i
= 14; i
< tx_len
; i
++)
10752 tx_data
[i
] = (u8
) (i
& 0xff);
10754 map
= pci_map_single(tp
->pdev
, skb
->data
, tx_len
, PCI_DMA_TODEVICE
);
10755 if (pci_dma_mapping_error(tp
->pdev
, map
)) {
10756 dev_kfree_skb(skb
);
10760 tw32_f(HOSTCC_MODE
, tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
|
10765 rx_start_idx
= rnapi
->hw_status
->idx
[0].rx_producer
;
10769 tg3_set_txd(tnapi
, tnapi
->tx_prod
, map
, tx_len
, 0, 1);
10774 tw32_tx_mbox(tnapi
->prodmbox
, tnapi
->tx_prod
);
10775 tr32_mailbox(tnapi
->prodmbox
);
10779 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
10780 for (i
= 0; i
< 35; i
++) {
10781 tw32_f(HOSTCC_MODE
, tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
|
10786 tx_idx
= tnapi
->hw_status
->idx
[0].tx_consumer
;
10787 rx_idx
= rnapi
->hw_status
->idx
[0].rx_producer
;
10788 if ((tx_idx
== tnapi
->tx_prod
) &&
10789 (rx_idx
== (rx_start_idx
+ num_pkts
)))
10793 pci_unmap_single(tp
->pdev
, map
, tx_len
, PCI_DMA_TODEVICE
);
10794 dev_kfree_skb(skb
);
10796 if (tx_idx
!= tnapi
->tx_prod
)
10799 if (rx_idx
!= rx_start_idx
+ num_pkts
)
10802 desc
= &rnapi
->rx_rcb
[rx_start_idx
];
10803 desc_idx
= desc
->opaque
& RXD_OPAQUE_INDEX_MASK
;
10804 opaque_key
= desc
->opaque
& RXD_OPAQUE_RING_MASK
;
10805 if (opaque_key
!= RXD_OPAQUE_RING_STD
)
10808 if ((desc
->err_vlan
& RXD_ERR_MASK
) != 0 &&
10809 (desc
->err_vlan
!= RXD_ERR_ODD_NIBBLE_RCVD_MII
))
10812 rx_len
= ((desc
->idx_len
& RXD_LEN_MASK
) >> RXD_LEN_SHIFT
) - 4;
10813 if (rx_len
!= tx_len
)
10816 rx_skb
= tpr
->rx_std_buffers
[desc_idx
].skb
;
10818 map
= dma_unmap_addr(&tpr
->rx_std_buffers
[desc_idx
], mapping
);
10819 pci_dma_sync_single_for_cpu(tp
->pdev
, map
, rx_len
, PCI_DMA_FROMDEVICE
);
10821 for (i
= 14; i
< tx_len
; i
++) {
10822 if (*(rx_skb
->data
+ i
) != (u8
) (i
& 0xff))
10827 /* tg3_free_rings will unmap and free the rx_skb */
10832 #define TG3_MAC_LOOPBACK_FAILED 1
10833 #define TG3_PHY_LOOPBACK_FAILED 2
10834 #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
10835 TG3_PHY_LOOPBACK_FAILED)
10837 static int tg3_test_loopback(struct tg3
*tp
)
10842 if (!netif_running(tp
->dev
))
10843 return TG3_LOOPBACK_FAILED
;
10845 err
= tg3_reset_hw(tp
, 1);
10847 return TG3_LOOPBACK_FAILED
;
10849 /* Turn off gphy autopowerdown. */
10850 if (tp
->phy_flags
& TG3_PHYFLG_ENABLE_APD
)
10851 tg3_phy_toggle_apd(tp
, false);
10853 if (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) {
10857 tw32(TG3_CPMU_MUTEX_REQ
, CPMU_MUTEX_REQ_DRIVER
);
10859 /* Wait for up to 40 microseconds to acquire lock. */
10860 for (i
= 0; i
< 4; i
++) {
10861 status
= tr32(TG3_CPMU_MUTEX_GNT
);
10862 if (status
== CPMU_MUTEX_GNT_DRIVER
)
10867 if (status
!= CPMU_MUTEX_GNT_DRIVER
)
10868 return TG3_LOOPBACK_FAILED
;
10870 /* Turn off link-based power management. */
10871 cpmuctrl
= tr32(TG3_CPMU_CTRL
);
10872 tw32(TG3_CPMU_CTRL
,
10873 cpmuctrl
& ~(CPMU_CTRL_LINK_SPEED_MODE
|
10874 CPMU_CTRL_LINK_AWARE_MODE
));
10877 if (tg3_run_loopback(tp
, TG3_MAC_LOOPBACK
))
10878 err
|= TG3_MAC_LOOPBACK_FAILED
;
10880 if (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) {
10881 tw32(TG3_CPMU_CTRL
, cpmuctrl
);
10883 /* Release the mutex */
10884 tw32(TG3_CPMU_MUTEX_GNT
, CPMU_MUTEX_GNT_DRIVER
);
10887 if (!(tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) &&
10888 !(tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
)) {
10889 if (tg3_run_loopback(tp
, TG3_PHY_LOOPBACK
))
10890 err
|= TG3_PHY_LOOPBACK_FAILED
;
10893 /* Re-enable gphy autopowerdown. */
10894 if (tp
->phy_flags
& TG3_PHYFLG_ENABLE_APD
)
10895 tg3_phy_toggle_apd(tp
, true);
10900 static void tg3_self_test(struct net_device
*dev
, struct ethtool_test
*etest
,
10903 struct tg3
*tp
= netdev_priv(dev
);
10905 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)
10906 tg3_set_power_state(tp
, PCI_D0
);
10908 memset(data
, 0, sizeof(u64
) * TG3_NUM_TEST
);
10910 if (tg3_test_nvram(tp
) != 0) {
10911 etest
->flags
|= ETH_TEST_FL_FAILED
;
10914 if (tg3_test_link(tp
) != 0) {
10915 etest
->flags
|= ETH_TEST_FL_FAILED
;
10918 if (etest
->flags
& ETH_TEST_FL_OFFLINE
) {
10919 int err
, err2
= 0, irq_sync
= 0;
10921 if (netif_running(dev
)) {
10923 tg3_netif_stop(tp
);
10927 tg3_full_lock(tp
, irq_sync
);
10929 tg3_halt(tp
, RESET_KIND_SUSPEND
, 1);
10930 err
= tg3_nvram_lock(tp
);
10931 tg3_halt_cpu(tp
, RX_CPU_BASE
);
10932 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
10933 tg3_halt_cpu(tp
, TX_CPU_BASE
);
10935 tg3_nvram_unlock(tp
);
10937 if (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
)
10940 if (tg3_test_registers(tp
) != 0) {
10941 etest
->flags
|= ETH_TEST_FL_FAILED
;
10944 if (tg3_test_memory(tp
) != 0) {
10945 etest
->flags
|= ETH_TEST_FL_FAILED
;
10948 if ((data
[4] = tg3_test_loopback(tp
)) != 0)
10949 etest
->flags
|= ETH_TEST_FL_FAILED
;
10951 tg3_full_unlock(tp
);
10953 if (tg3_test_interrupt(tp
) != 0) {
10954 etest
->flags
|= ETH_TEST_FL_FAILED
;
10958 tg3_full_lock(tp
, 0);
10960 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
10961 if (netif_running(dev
)) {
10962 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
10963 err2
= tg3_restart_hw(tp
, 1);
10965 tg3_netif_start(tp
);
10968 tg3_full_unlock(tp
);
10970 if (irq_sync
&& !err2
)
10973 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)
10974 tg3_set_power_state(tp
, PCI_D3hot
);
10978 static int tg3_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
10980 struct mii_ioctl_data
*data
= if_mii(ifr
);
10981 struct tg3
*tp
= netdev_priv(dev
);
10984 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
10985 struct phy_device
*phydev
;
10986 if (!(tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
))
10988 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
10989 return phy_mii_ioctl(phydev
, ifr
, cmd
);
10994 data
->phy_id
= tp
->phy_addr
;
10997 case SIOCGMIIREG
: {
11000 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
)
11001 break; /* We have no PHY */
11003 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)
11006 spin_lock_bh(&tp
->lock
);
11007 err
= tg3_readphy(tp
, data
->reg_num
& 0x1f, &mii_regval
);
11008 spin_unlock_bh(&tp
->lock
);
11010 data
->val_out
= mii_regval
;
11016 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
)
11017 break; /* We have no PHY */
11019 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)
11022 spin_lock_bh(&tp
->lock
);
11023 err
= tg3_writephy(tp
, data
->reg_num
& 0x1f, data
->val_in
);
11024 spin_unlock_bh(&tp
->lock
);
11032 return -EOPNOTSUPP
;
11035 #if TG3_VLAN_TAG_USED
11036 static void tg3_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*grp
)
11038 struct tg3
*tp
= netdev_priv(dev
);
11040 if (!netif_running(dev
)) {
11045 tg3_netif_stop(tp
);
11047 tg3_full_lock(tp
, 0);
11051 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
11052 __tg3_set_rx_mode(dev
);
11054 tg3_netif_start(tp
);
11056 tg3_full_unlock(tp
);
11060 static int tg3_get_coalesce(struct net_device
*dev
, struct ethtool_coalesce
*ec
)
11062 struct tg3
*tp
= netdev_priv(dev
);
11064 memcpy(ec
, &tp
->coal
, sizeof(*ec
));
11068 static int tg3_set_coalesce(struct net_device
*dev
, struct ethtool_coalesce
*ec
)
11070 struct tg3
*tp
= netdev_priv(dev
);
11071 u32 max_rxcoal_tick_int
= 0, max_txcoal_tick_int
= 0;
11072 u32 max_stat_coal_ticks
= 0, min_stat_coal_ticks
= 0;
11074 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
11075 max_rxcoal_tick_int
= MAX_RXCOAL_TICK_INT
;
11076 max_txcoal_tick_int
= MAX_TXCOAL_TICK_INT
;
11077 max_stat_coal_ticks
= MAX_STAT_COAL_TICKS
;
11078 min_stat_coal_ticks
= MIN_STAT_COAL_TICKS
;
11081 if ((ec
->rx_coalesce_usecs
> MAX_RXCOL_TICKS
) ||
11082 (ec
->tx_coalesce_usecs
> MAX_TXCOL_TICKS
) ||
11083 (ec
->rx_max_coalesced_frames
> MAX_RXMAX_FRAMES
) ||
11084 (ec
->tx_max_coalesced_frames
> MAX_TXMAX_FRAMES
) ||
11085 (ec
->rx_coalesce_usecs_irq
> max_rxcoal_tick_int
) ||
11086 (ec
->tx_coalesce_usecs_irq
> max_txcoal_tick_int
) ||
11087 (ec
->rx_max_coalesced_frames_irq
> MAX_RXCOAL_MAXF_INT
) ||
11088 (ec
->tx_max_coalesced_frames_irq
> MAX_TXCOAL_MAXF_INT
) ||
11089 (ec
->stats_block_coalesce_usecs
> max_stat_coal_ticks
) ||
11090 (ec
->stats_block_coalesce_usecs
< min_stat_coal_ticks
))
11093 /* No rx interrupts will be generated if both are zero */
11094 if ((ec
->rx_coalesce_usecs
== 0) &&
11095 (ec
->rx_max_coalesced_frames
== 0))
11098 /* No tx interrupts will be generated if both are zero */
11099 if ((ec
->tx_coalesce_usecs
== 0) &&
11100 (ec
->tx_max_coalesced_frames
== 0))
11103 /* Only copy relevant parameters, ignore all others. */
11104 tp
->coal
.rx_coalesce_usecs
= ec
->rx_coalesce_usecs
;
11105 tp
->coal
.tx_coalesce_usecs
= ec
->tx_coalesce_usecs
;
11106 tp
->coal
.rx_max_coalesced_frames
= ec
->rx_max_coalesced_frames
;
11107 tp
->coal
.tx_max_coalesced_frames
= ec
->tx_max_coalesced_frames
;
11108 tp
->coal
.rx_coalesce_usecs_irq
= ec
->rx_coalesce_usecs_irq
;
11109 tp
->coal
.tx_coalesce_usecs_irq
= ec
->tx_coalesce_usecs_irq
;
11110 tp
->coal
.rx_max_coalesced_frames_irq
= ec
->rx_max_coalesced_frames_irq
;
11111 tp
->coal
.tx_max_coalesced_frames_irq
= ec
->tx_max_coalesced_frames_irq
;
11112 tp
->coal
.stats_block_coalesce_usecs
= ec
->stats_block_coalesce_usecs
;
11114 if (netif_running(dev
)) {
11115 tg3_full_lock(tp
, 0);
11116 __tg3_set_coalesce(tp
, &tp
->coal
);
11117 tg3_full_unlock(tp
);
11122 static const struct ethtool_ops tg3_ethtool_ops
= {
11123 .get_settings
= tg3_get_settings
,
11124 .set_settings
= tg3_set_settings
,
11125 .get_drvinfo
= tg3_get_drvinfo
,
11126 .get_regs_len
= tg3_get_regs_len
,
11127 .get_regs
= tg3_get_regs
,
11128 .get_wol
= tg3_get_wol
,
11129 .set_wol
= tg3_set_wol
,
11130 .get_msglevel
= tg3_get_msglevel
,
11131 .set_msglevel
= tg3_set_msglevel
,
11132 .nway_reset
= tg3_nway_reset
,
11133 .get_link
= ethtool_op_get_link
,
11134 .get_eeprom_len
= tg3_get_eeprom_len
,
11135 .get_eeprom
= tg3_get_eeprom
,
11136 .set_eeprom
= tg3_set_eeprom
,
11137 .get_ringparam
= tg3_get_ringparam
,
11138 .set_ringparam
= tg3_set_ringparam
,
11139 .get_pauseparam
= tg3_get_pauseparam
,
11140 .set_pauseparam
= tg3_set_pauseparam
,
11141 .get_rx_csum
= tg3_get_rx_csum
,
11142 .set_rx_csum
= tg3_set_rx_csum
,
11143 .set_tx_csum
= tg3_set_tx_csum
,
11144 .set_sg
= ethtool_op_set_sg
,
11145 .set_tso
= tg3_set_tso
,
11146 .self_test
= tg3_self_test
,
11147 .get_strings
= tg3_get_strings
,
11148 .phys_id
= tg3_phys_id
,
11149 .get_ethtool_stats
= tg3_get_ethtool_stats
,
11150 .get_coalesce
= tg3_get_coalesce
,
11151 .set_coalesce
= tg3_set_coalesce
,
11152 .get_sset_count
= tg3_get_sset_count
,
11155 static void __devinit
tg3_get_eeprom_size(struct tg3
*tp
)
11157 u32 cursize
, val
, magic
;
11159 tp
->nvram_size
= EEPROM_CHIP_SIZE
;
11161 if (tg3_nvram_read(tp
, 0, &magic
) != 0)
11164 if ((magic
!= TG3_EEPROM_MAGIC
) &&
11165 ((magic
& TG3_EEPROM_MAGIC_FW_MSK
) != TG3_EEPROM_MAGIC_FW
) &&
11166 ((magic
& TG3_EEPROM_MAGIC_HW_MSK
) != TG3_EEPROM_MAGIC_HW
))
11170 * Size the chip by reading offsets at increasing powers of two.
11171 * When we encounter our validation signature, we know the addressing
11172 * has wrapped around, and thus have our chip size.
11176 while (cursize
< tp
->nvram_size
) {
11177 if (tg3_nvram_read(tp
, cursize
, &val
) != 0)
11186 tp
->nvram_size
= cursize
;
11189 static void __devinit
tg3_get_nvram_size(struct tg3
*tp
)
11193 if ((tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) ||
11194 tg3_nvram_read(tp
, 0, &val
) != 0)
11197 /* Selfboot format */
11198 if (val
!= TG3_EEPROM_MAGIC
) {
11199 tg3_get_eeprom_size(tp
);
11203 if (tg3_nvram_read(tp
, 0xf0, &val
) == 0) {
11205 /* This is confusing. We want to operate on the
11206 * 16-bit value at offset 0xf2. The tg3_nvram_read()
11207 * call will read from NVRAM and byteswap the data
11208 * according to the byteswapping settings for all
11209 * other register accesses. This ensures the data we
11210 * want will always reside in the lower 16-bits.
11211 * However, the data in NVRAM is in LE format, which
11212 * means the data from the NVRAM read will always be
11213 * opposite the endianness of the CPU. The 16-bit
11214 * byteswap then brings the data to CPU endianness.
11216 tp
->nvram_size
= swab16((u16
)(val
& 0x0000ffff)) * 1024;
11220 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
11223 static void __devinit
tg3_get_nvram_info(struct tg3
*tp
)
11227 nvcfg1
= tr32(NVRAM_CFG1
);
11228 if (nvcfg1
& NVRAM_CFG1_FLASHIF_ENAB
) {
11229 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11231 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
11232 tw32(NVRAM_CFG1
, nvcfg1
);
11235 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
) ||
11236 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
11237 switch (nvcfg1
& NVRAM_CFG1_VENDOR_MASK
) {
11238 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED
:
11239 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11240 tp
->nvram_pagesize
= ATMEL_AT45DB0X1B_PAGE_SIZE
;
11241 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11243 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED
:
11244 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11245 tp
->nvram_pagesize
= ATMEL_AT25F512_PAGE_SIZE
;
11247 case FLASH_VENDOR_ATMEL_EEPROM
:
11248 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11249 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
11250 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11252 case FLASH_VENDOR_ST
:
11253 tp
->nvram_jedecnum
= JEDEC_ST
;
11254 tp
->nvram_pagesize
= ST_M45PEX0_PAGE_SIZE
;
11255 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11257 case FLASH_VENDOR_SAIFUN
:
11258 tp
->nvram_jedecnum
= JEDEC_SAIFUN
;
11259 tp
->nvram_pagesize
= SAIFUN_SA25F0XX_PAGE_SIZE
;
11261 case FLASH_VENDOR_SST_SMALL
:
11262 case FLASH_VENDOR_SST_LARGE
:
11263 tp
->nvram_jedecnum
= JEDEC_SST
;
11264 tp
->nvram_pagesize
= SST_25VF0X0_PAGE_SIZE
;
11268 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11269 tp
->nvram_pagesize
= ATMEL_AT45DB0X1B_PAGE_SIZE
;
11270 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11274 static void __devinit
tg3_nvram_get_pagesize(struct tg3
*tp
, u32 nvmcfg1
)
11276 switch (nvmcfg1
& NVRAM_CFG1_5752PAGE_SIZE_MASK
) {
11277 case FLASH_5752PAGE_SIZE_256
:
11278 tp
->nvram_pagesize
= 256;
11280 case FLASH_5752PAGE_SIZE_512
:
11281 tp
->nvram_pagesize
= 512;
11283 case FLASH_5752PAGE_SIZE_1K
:
11284 tp
->nvram_pagesize
= 1024;
11286 case FLASH_5752PAGE_SIZE_2K
:
11287 tp
->nvram_pagesize
= 2048;
11289 case FLASH_5752PAGE_SIZE_4K
:
11290 tp
->nvram_pagesize
= 4096;
11292 case FLASH_5752PAGE_SIZE_264
:
11293 tp
->nvram_pagesize
= 264;
11295 case FLASH_5752PAGE_SIZE_528
:
11296 tp
->nvram_pagesize
= 528;
11301 static void __devinit
tg3_get_5752_nvram_info(struct tg3
*tp
)
11305 nvcfg1
= tr32(NVRAM_CFG1
);
11307 /* NVRAM protection for TPM */
11308 if (nvcfg1
& (1 << 27))
11309 tp
->tg3_flags3
|= TG3_FLG3_PROTECTED_NVRAM
;
11311 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11312 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ
:
11313 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ
:
11314 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11315 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11317 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
11318 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11319 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11320 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11322 case FLASH_5752VENDOR_ST_M45PE10
:
11323 case FLASH_5752VENDOR_ST_M45PE20
:
11324 case FLASH_5752VENDOR_ST_M45PE40
:
11325 tp
->nvram_jedecnum
= JEDEC_ST
;
11326 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11327 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11331 if (tp
->tg3_flags2
& TG3_FLG2_FLASH
) {
11332 tg3_nvram_get_pagesize(tp
, nvcfg1
);
11334 /* For eeprom, set pagesize to maximum eeprom size */
11335 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
11337 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
11338 tw32(NVRAM_CFG1
, nvcfg1
);
11342 static void __devinit
tg3_get_5755_nvram_info(struct tg3
*tp
)
11344 u32 nvcfg1
, protect
= 0;
11346 nvcfg1
= tr32(NVRAM_CFG1
);
11348 /* NVRAM protection for TPM */
11349 if (nvcfg1
& (1 << 27)) {
11350 tp
->tg3_flags3
|= TG3_FLG3_PROTECTED_NVRAM
;
11354 nvcfg1
&= NVRAM_CFG1_5752VENDOR_MASK
;
11356 case FLASH_5755VENDOR_ATMEL_FLASH_1
:
11357 case FLASH_5755VENDOR_ATMEL_FLASH_2
:
11358 case FLASH_5755VENDOR_ATMEL_FLASH_3
:
11359 case FLASH_5755VENDOR_ATMEL_FLASH_5
:
11360 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11361 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11362 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11363 tp
->nvram_pagesize
= 264;
11364 if (nvcfg1
== FLASH_5755VENDOR_ATMEL_FLASH_1
||
11365 nvcfg1
== FLASH_5755VENDOR_ATMEL_FLASH_5
)
11366 tp
->nvram_size
= (protect
? 0x3e200 :
11367 TG3_NVRAM_SIZE_512KB
);
11368 else if (nvcfg1
== FLASH_5755VENDOR_ATMEL_FLASH_2
)
11369 tp
->nvram_size
= (protect
? 0x1f200 :
11370 TG3_NVRAM_SIZE_256KB
);
11372 tp
->nvram_size
= (protect
? 0x1f200 :
11373 TG3_NVRAM_SIZE_128KB
);
11375 case FLASH_5752VENDOR_ST_M45PE10
:
11376 case FLASH_5752VENDOR_ST_M45PE20
:
11377 case FLASH_5752VENDOR_ST_M45PE40
:
11378 tp
->nvram_jedecnum
= JEDEC_ST
;
11379 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11380 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11381 tp
->nvram_pagesize
= 256;
11382 if (nvcfg1
== FLASH_5752VENDOR_ST_M45PE10
)
11383 tp
->nvram_size
= (protect
?
11384 TG3_NVRAM_SIZE_64KB
:
11385 TG3_NVRAM_SIZE_128KB
);
11386 else if (nvcfg1
== FLASH_5752VENDOR_ST_M45PE20
)
11387 tp
->nvram_size
= (protect
?
11388 TG3_NVRAM_SIZE_64KB
:
11389 TG3_NVRAM_SIZE_256KB
);
11391 tp
->nvram_size
= (protect
?
11392 TG3_NVRAM_SIZE_128KB
:
11393 TG3_NVRAM_SIZE_512KB
);
11398 static void __devinit
tg3_get_5787_nvram_info(struct tg3
*tp
)
11402 nvcfg1
= tr32(NVRAM_CFG1
);
11404 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11405 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ
:
11406 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ
:
11407 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ
:
11408 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ
:
11409 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11410 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11411 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
11413 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
11414 tw32(NVRAM_CFG1
, nvcfg1
);
11416 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
11417 case FLASH_5755VENDOR_ATMEL_FLASH_1
:
11418 case FLASH_5755VENDOR_ATMEL_FLASH_2
:
11419 case FLASH_5755VENDOR_ATMEL_FLASH_3
:
11420 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11421 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11422 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11423 tp
->nvram_pagesize
= 264;
11425 case FLASH_5752VENDOR_ST_M45PE10
:
11426 case FLASH_5752VENDOR_ST_M45PE20
:
11427 case FLASH_5752VENDOR_ST_M45PE40
:
11428 tp
->nvram_jedecnum
= JEDEC_ST
;
11429 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11430 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11431 tp
->nvram_pagesize
= 256;
11436 static void __devinit
tg3_get_5761_nvram_info(struct tg3
*tp
)
11438 u32 nvcfg1
, protect
= 0;
11440 nvcfg1
= tr32(NVRAM_CFG1
);
11442 /* NVRAM protection for TPM */
11443 if (nvcfg1
& (1 << 27)) {
11444 tp
->tg3_flags3
|= TG3_FLG3_PROTECTED_NVRAM
;
11448 nvcfg1
&= NVRAM_CFG1_5752VENDOR_MASK
;
11450 case FLASH_5761VENDOR_ATMEL_ADB021D
:
11451 case FLASH_5761VENDOR_ATMEL_ADB041D
:
11452 case FLASH_5761VENDOR_ATMEL_ADB081D
:
11453 case FLASH_5761VENDOR_ATMEL_ADB161D
:
11454 case FLASH_5761VENDOR_ATMEL_MDB021D
:
11455 case FLASH_5761VENDOR_ATMEL_MDB041D
:
11456 case FLASH_5761VENDOR_ATMEL_MDB081D
:
11457 case FLASH_5761VENDOR_ATMEL_MDB161D
:
11458 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11459 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11460 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11461 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
11462 tp
->nvram_pagesize
= 256;
11464 case FLASH_5761VENDOR_ST_A_M45PE20
:
11465 case FLASH_5761VENDOR_ST_A_M45PE40
:
11466 case FLASH_5761VENDOR_ST_A_M45PE80
:
11467 case FLASH_5761VENDOR_ST_A_M45PE16
:
11468 case FLASH_5761VENDOR_ST_M_M45PE20
:
11469 case FLASH_5761VENDOR_ST_M_M45PE40
:
11470 case FLASH_5761VENDOR_ST_M_M45PE80
:
11471 case FLASH_5761VENDOR_ST_M_M45PE16
:
11472 tp
->nvram_jedecnum
= JEDEC_ST
;
11473 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11474 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11475 tp
->nvram_pagesize
= 256;
11480 tp
->nvram_size
= tr32(NVRAM_ADDR_LOCKOUT
);
11483 case FLASH_5761VENDOR_ATMEL_ADB161D
:
11484 case FLASH_5761VENDOR_ATMEL_MDB161D
:
11485 case FLASH_5761VENDOR_ST_A_M45PE16
:
11486 case FLASH_5761VENDOR_ST_M_M45PE16
:
11487 tp
->nvram_size
= TG3_NVRAM_SIZE_2MB
;
11489 case FLASH_5761VENDOR_ATMEL_ADB081D
:
11490 case FLASH_5761VENDOR_ATMEL_MDB081D
:
11491 case FLASH_5761VENDOR_ST_A_M45PE80
:
11492 case FLASH_5761VENDOR_ST_M_M45PE80
:
11493 tp
->nvram_size
= TG3_NVRAM_SIZE_1MB
;
11495 case FLASH_5761VENDOR_ATMEL_ADB041D
:
11496 case FLASH_5761VENDOR_ATMEL_MDB041D
:
11497 case FLASH_5761VENDOR_ST_A_M45PE40
:
11498 case FLASH_5761VENDOR_ST_M_M45PE40
:
11499 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
11501 case FLASH_5761VENDOR_ATMEL_ADB021D
:
11502 case FLASH_5761VENDOR_ATMEL_MDB021D
:
11503 case FLASH_5761VENDOR_ST_A_M45PE20
:
11504 case FLASH_5761VENDOR_ST_M_M45PE20
:
11505 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
11511 static void __devinit
tg3_get_5906_nvram_info(struct tg3
*tp
)
11513 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11514 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11515 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
11518 static void __devinit
tg3_get_57780_nvram_info(struct tg3
*tp
)
11522 nvcfg1
= tr32(NVRAM_CFG1
);
11524 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11525 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ
:
11526 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ
:
11527 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11528 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11529 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
11531 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
11532 tw32(NVRAM_CFG1
, nvcfg1
);
11534 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
11535 case FLASH_57780VENDOR_ATMEL_AT45DB011D
:
11536 case FLASH_57780VENDOR_ATMEL_AT45DB011B
:
11537 case FLASH_57780VENDOR_ATMEL_AT45DB021D
:
11538 case FLASH_57780VENDOR_ATMEL_AT45DB021B
:
11539 case FLASH_57780VENDOR_ATMEL_AT45DB041D
:
11540 case FLASH_57780VENDOR_ATMEL_AT45DB041B
:
11541 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11542 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11543 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11545 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11546 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
11547 case FLASH_57780VENDOR_ATMEL_AT45DB011D
:
11548 case FLASH_57780VENDOR_ATMEL_AT45DB011B
:
11549 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
11551 case FLASH_57780VENDOR_ATMEL_AT45DB021D
:
11552 case FLASH_57780VENDOR_ATMEL_AT45DB021B
:
11553 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
11555 case FLASH_57780VENDOR_ATMEL_AT45DB041D
:
11556 case FLASH_57780VENDOR_ATMEL_AT45DB041B
:
11557 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
11561 case FLASH_5752VENDOR_ST_M45PE10
:
11562 case FLASH_5752VENDOR_ST_M45PE20
:
11563 case FLASH_5752VENDOR_ST_M45PE40
:
11564 tp
->nvram_jedecnum
= JEDEC_ST
;
11565 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11566 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11568 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11569 case FLASH_5752VENDOR_ST_M45PE10
:
11570 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
11572 case FLASH_5752VENDOR_ST_M45PE20
:
11573 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
11575 case FLASH_5752VENDOR_ST_M45PE40
:
11576 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
11581 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM
;
11585 tg3_nvram_get_pagesize(tp
, nvcfg1
);
11586 if (tp
->nvram_pagesize
!= 264 && tp
->nvram_pagesize
!= 528)
11587 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
11591 static void __devinit
tg3_get_5717_nvram_info(struct tg3
*tp
)
11595 nvcfg1
= tr32(NVRAM_CFG1
);
11597 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11598 case FLASH_5717VENDOR_ATMEL_EEPROM
:
11599 case FLASH_5717VENDOR_MICRO_EEPROM
:
11600 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11601 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11602 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
11604 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
11605 tw32(NVRAM_CFG1
, nvcfg1
);
11607 case FLASH_5717VENDOR_ATMEL_MDB011D
:
11608 case FLASH_5717VENDOR_ATMEL_ADB011B
:
11609 case FLASH_5717VENDOR_ATMEL_ADB011D
:
11610 case FLASH_5717VENDOR_ATMEL_MDB021D
:
11611 case FLASH_5717VENDOR_ATMEL_ADB021B
:
11612 case FLASH_5717VENDOR_ATMEL_ADB021D
:
11613 case FLASH_5717VENDOR_ATMEL_45USPT
:
11614 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11615 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11616 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11618 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11619 case FLASH_5717VENDOR_ATMEL_MDB021D
:
11620 case FLASH_5717VENDOR_ATMEL_ADB021B
:
11621 case FLASH_5717VENDOR_ATMEL_ADB021D
:
11622 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
11625 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
11629 case FLASH_5717VENDOR_ST_M_M25PE10
:
11630 case FLASH_5717VENDOR_ST_A_M25PE10
:
11631 case FLASH_5717VENDOR_ST_M_M45PE10
:
11632 case FLASH_5717VENDOR_ST_A_M45PE10
:
11633 case FLASH_5717VENDOR_ST_M_M25PE20
:
11634 case FLASH_5717VENDOR_ST_A_M25PE20
:
11635 case FLASH_5717VENDOR_ST_M_M45PE20
:
11636 case FLASH_5717VENDOR_ST_A_M45PE20
:
11637 case FLASH_5717VENDOR_ST_25USPT
:
11638 case FLASH_5717VENDOR_ST_45USPT
:
11639 tp
->nvram_jedecnum
= JEDEC_ST
;
11640 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11641 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11643 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11644 case FLASH_5717VENDOR_ST_M_M25PE20
:
11645 case FLASH_5717VENDOR_ST_A_M25PE20
:
11646 case FLASH_5717VENDOR_ST_M_M45PE20
:
11647 case FLASH_5717VENDOR_ST_A_M45PE20
:
11648 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
11651 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
11656 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM
;
11660 tg3_nvram_get_pagesize(tp
, nvcfg1
);
11661 if (tp
->nvram_pagesize
!= 264 && tp
->nvram_pagesize
!= 528)
11662 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
11665 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11666 static void __devinit
tg3_nvram_init(struct tg3
*tp
)
11668 tw32_f(GRC_EEPROM_ADDR
,
11669 (EEPROM_ADDR_FSM_RESET
|
11670 (EEPROM_DEFAULT_CLOCK_PERIOD
<<
11671 EEPROM_ADDR_CLKPERD_SHIFT
)));
11675 /* Enable seeprom accesses. */
11676 tw32_f(GRC_LOCAL_CTRL
,
11677 tr32(GRC_LOCAL_CTRL
) | GRC_LCLCTRL_AUTO_SEEPROM
);
11680 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
11681 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
) {
11682 tp
->tg3_flags
|= TG3_FLAG_NVRAM
;
11684 if (tg3_nvram_lock(tp
)) {
11685 netdev_warn(tp
->dev
,
11686 "Cannot get nvram lock, %s failed\n",
11690 tg3_enable_nvram_access(tp
);
11692 tp
->nvram_size
= 0;
11694 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
)
11695 tg3_get_5752_nvram_info(tp
);
11696 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
)
11697 tg3_get_5755_nvram_info(tp
);
11698 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5787
||
11699 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
11700 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
11701 tg3_get_5787_nvram_info(tp
);
11702 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
)
11703 tg3_get_5761_nvram_info(tp
);
11704 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
11705 tg3_get_5906_nvram_info(tp
);
11706 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
||
11707 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
11708 tg3_get_57780_nvram_info(tp
);
11709 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
11710 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
)
11711 tg3_get_5717_nvram_info(tp
);
11713 tg3_get_nvram_info(tp
);
11715 if (tp
->nvram_size
== 0)
11716 tg3_get_nvram_size(tp
);
11718 tg3_disable_nvram_access(tp
);
11719 tg3_nvram_unlock(tp
);
11722 tp
->tg3_flags
&= ~(TG3_FLAG_NVRAM
| TG3_FLAG_NVRAM_BUFFERED
);
11724 tg3_get_eeprom_size(tp
);
11728 static int tg3_nvram_write_block_using_eeprom(struct tg3
*tp
,
11729 u32 offset
, u32 len
, u8
*buf
)
11734 for (i
= 0; i
< len
; i
+= 4) {
11740 memcpy(&data
, buf
+ i
, 4);
11743 * The SEEPROM interface expects the data to always be opposite
11744 * the native endian format. We accomplish this by reversing
11745 * all the operations that would have been performed on the
11746 * data from a call to tg3_nvram_read_be32().
11748 tw32(GRC_EEPROM_DATA
, swab32(be32_to_cpu(data
)));
11750 val
= tr32(GRC_EEPROM_ADDR
);
11751 tw32(GRC_EEPROM_ADDR
, val
| EEPROM_ADDR_COMPLETE
);
11753 val
&= ~(EEPROM_ADDR_ADDR_MASK
| EEPROM_ADDR_DEVID_MASK
|
11755 tw32(GRC_EEPROM_ADDR
, val
|
11756 (0 << EEPROM_ADDR_DEVID_SHIFT
) |
11757 (addr
& EEPROM_ADDR_ADDR_MASK
) |
11758 EEPROM_ADDR_START
|
11759 EEPROM_ADDR_WRITE
);
11761 for (j
= 0; j
< 1000; j
++) {
11762 val
= tr32(GRC_EEPROM_ADDR
);
11764 if (val
& EEPROM_ADDR_COMPLETE
)
11768 if (!(val
& EEPROM_ADDR_COMPLETE
)) {
11777 /* offset and length are dword aligned */
11778 static int tg3_nvram_write_block_unbuffered(struct tg3
*tp
, u32 offset
, u32 len
,
11782 u32 pagesize
= tp
->nvram_pagesize
;
11783 u32 pagemask
= pagesize
- 1;
11787 tmp
= kmalloc(pagesize
, GFP_KERNEL
);
11793 u32 phy_addr
, page_off
, size
;
11795 phy_addr
= offset
& ~pagemask
;
11797 for (j
= 0; j
< pagesize
; j
+= 4) {
11798 ret
= tg3_nvram_read_be32(tp
, phy_addr
+ j
,
11799 (__be32
*) (tmp
+ j
));
11806 page_off
= offset
& pagemask
;
11813 memcpy(tmp
+ page_off
, buf
, size
);
11815 offset
= offset
+ (pagesize
- page_off
);
11817 tg3_enable_nvram_access(tp
);
11820 * Before we can erase the flash page, we need
11821 * to issue a special "write enable" command.
11823 nvram_cmd
= NVRAM_CMD_WREN
| NVRAM_CMD_GO
| NVRAM_CMD_DONE
;
11825 if (tg3_nvram_exec_cmd(tp
, nvram_cmd
))
11828 /* Erase the target page */
11829 tw32(NVRAM_ADDR
, phy_addr
);
11831 nvram_cmd
= NVRAM_CMD_GO
| NVRAM_CMD_DONE
| NVRAM_CMD_WR
|
11832 NVRAM_CMD_FIRST
| NVRAM_CMD_LAST
| NVRAM_CMD_ERASE
;
11834 if (tg3_nvram_exec_cmd(tp
, nvram_cmd
))
11837 /* Issue another write enable to start the write. */
11838 nvram_cmd
= NVRAM_CMD_WREN
| NVRAM_CMD_GO
| NVRAM_CMD_DONE
;
11840 if (tg3_nvram_exec_cmd(tp
, nvram_cmd
))
11843 for (j
= 0; j
< pagesize
; j
+= 4) {
11846 data
= *((__be32
*) (tmp
+ j
));
11848 tw32(NVRAM_WRDATA
, be32_to_cpu(data
));
11850 tw32(NVRAM_ADDR
, phy_addr
+ j
);
11852 nvram_cmd
= NVRAM_CMD_GO
| NVRAM_CMD_DONE
|
11856 nvram_cmd
|= NVRAM_CMD_FIRST
;
11857 else if (j
== (pagesize
- 4))
11858 nvram_cmd
|= NVRAM_CMD_LAST
;
11860 if ((ret
= tg3_nvram_exec_cmd(tp
, nvram_cmd
)))
11867 nvram_cmd
= NVRAM_CMD_WRDI
| NVRAM_CMD_GO
| NVRAM_CMD_DONE
;
11868 tg3_nvram_exec_cmd(tp
, nvram_cmd
);
11875 /* offset and length are dword aligned */
11876 static int tg3_nvram_write_block_buffered(struct tg3
*tp
, u32 offset
, u32 len
,
11881 for (i
= 0; i
< len
; i
+= 4, offset
+= 4) {
11882 u32 page_off
, phy_addr
, nvram_cmd
;
11885 memcpy(&data
, buf
+ i
, 4);
11886 tw32(NVRAM_WRDATA
, be32_to_cpu(data
));
11888 page_off
= offset
% tp
->nvram_pagesize
;
11890 phy_addr
= tg3_nvram_phys_addr(tp
, offset
);
11892 tw32(NVRAM_ADDR
, phy_addr
);
11894 nvram_cmd
= NVRAM_CMD_GO
| NVRAM_CMD_DONE
| NVRAM_CMD_WR
;
11896 if (page_off
== 0 || i
== 0)
11897 nvram_cmd
|= NVRAM_CMD_FIRST
;
11898 if (page_off
== (tp
->nvram_pagesize
- 4))
11899 nvram_cmd
|= NVRAM_CMD_LAST
;
11901 if (i
== (len
- 4))
11902 nvram_cmd
|= NVRAM_CMD_LAST
;
11904 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5752
&&
11905 !(tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) &&
11906 (tp
->nvram_jedecnum
== JEDEC_ST
) &&
11907 (nvram_cmd
& NVRAM_CMD_FIRST
)) {
11909 if ((ret
= tg3_nvram_exec_cmd(tp
,
11910 NVRAM_CMD_WREN
| NVRAM_CMD_GO
|
11915 if (!(tp
->tg3_flags2
& TG3_FLG2_FLASH
)) {
11916 /* We always do complete word writes to eeprom. */
11917 nvram_cmd
|= (NVRAM_CMD_FIRST
| NVRAM_CMD_LAST
);
11920 if ((ret
= tg3_nvram_exec_cmd(tp
, nvram_cmd
)))
11926 /* offset and length are dword aligned */
11927 static int tg3_nvram_write_block(struct tg3
*tp
, u32 offset
, u32 len
, u8
*buf
)
11931 if (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
) {
11932 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
&
11933 ~GRC_LCLCTRL_GPIO_OUTPUT1
);
11937 if (!(tp
->tg3_flags
& TG3_FLAG_NVRAM
)) {
11938 ret
= tg3_nvram_write_block_using_eeprom(tp
, offset
, len
, buf
);
11942 ret
= tg3_nvram_lock(tp
);
11946 tg3_enable_nvram_access(tp
);
11947 if ((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
11948 !(tp
->tg3_flags3
& TG3_FLG3_PROTECTED_NVRAM
))
11949 tw32(NVRAM_WRITE1
, 0x406);
11951 grc_mode
= tr32(GRC_MODE
);
11952 tw32(GRC_MODE
, grc_mode
| GRC_MODE_NVRAM_WR_ENABLE
);
11954 if ((tp
->tg3_flags
& TG3_FLAG_NVRAM_BUFFERED
) ||
11955 !(tp
->tg3_flags2
& TG3_FLG2_FLASH
)) {
11957 ret
= tg3_nvram_write_block_buffered(tp
, offset
, len
,
11960 ret
= tg3_nvram_write_block_unbuffered(tp
, offset
, len
,
11964 grc_mode
= tr32(GRC_MODE
);
11965 tw32(GRC_MODE
, grc_mode
& ~GRC_MODE_NVRAM_WR_ENABLE
);
11967 tg3_disable_nvram_access(tp
);
11968 tg3_nvram_unlock(tp
);
11971 if (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
) {
11972 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
);
11979 struct subsys_tbl_ent
{
11980 u16 subsys_vendor
, subsys_devid
;
11984 static struct subsys_tbl_ent subsys_id_to_phy_id
[] __devinitdata
= {
11985 /* Broadcom boards. */
11986 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11987 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6
, TG3_PHY_ID_BCM5401
},
11988 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11989 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5
, TG3_PHY_ID_BCM5701
},
11990 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11991 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6
, TG3_PHY_ID_BCM8002
},
11992 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11993 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9
, 0 },
11994 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11995 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1
, TG3_PHY_ID_BCM5701
},
11996 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11997 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8
, TG3_PHY_ID_BCM5701
},
11998 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11999 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7
, 0 },
12000 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
12001 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10
, TG3_PHY_ID_BCM5701
},
12002 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
12003 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12
, TG3_PHY_ID_BCM5701
},
12004 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
12005 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1
, TG3_PHY_ID_BCM5703
},
12006 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
12007 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2
, TG3_PHY_ID_BCM5703
},
12010 { TG3PCI_SUBVENDOR_ID_3COM
,
12011 TG3PCI_SUBDEVICE_ID_3COM_3C996T
, TG3_PHY_ID_BCM5401
},
12012 { TG3PCI_SUBVENDOR_ID_3COM
,
12013 TG3PCI_SUBDEVICE_ID_3COM_3C996BT
, TG3_PHY_ID_BCM5701
},
12014 { TG3PCI_SUBVENDOR_ID_3COM
,
12015 TG3PCI_SUBDEVICE_ID_3COM_3C996SX
, 0 },
12016 { TG3PCI_SUBVENDOR_ID_3COM
,
12017 TG3PCI_SUBDEVICE_ID_3COM_3C1000T
, TG3_PHY_ID_BCM5701
},
12018 { TG3PCI_SUBVENDOR_ID_3COM
,
12019 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01
, TG3_PHY_ID_BCM5701
},
12022 { TG3PCI_SUBVENDOR_ID_DELL
,
12023 TG3PCI_SUBDEVICE_ID_DELL_VIPER
, TG3_PHY_ID_BCM5401
},
12024 { TG3PCI_SUBVENDOR_ID_DELL
,
12025 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR
, TG3_PHY_ID_BCM5401
},
12026 { TG3PCI_SUBVENDOR_ID_DELL
,
12027 TG3PCI_SUBDEVICE_ID_DELL_MERLOT
, TG3_PHY_ID_BCM5411
},
12028 { TG3PCI_SUBVENDOR_ID_DELL
,
12029 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT
, TG3_PHY_ID_BCM5411
},
12031 /* Compaq boards. */
12032 { TG3PCI_SUBVENDOR_ID_COMPAQ
,
12033 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE
, TG3_PHY_ID_BCM5701
},
12034 { TG3PCI_SUBVENDOR_ID_COMPAQ
,
12035 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2
, TG3_PHY_ID_BCM5701
},
12036 { TG3PCI_SUBVENDOR_ID_COMPAQ
,
12037 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING
, 0 },
12038 { TG3PCI_SUBVENDOR_ID_COMPAQ
,
12039 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780
, TG3_PHY_ID_BCM5701
},
12040 { TG3PCI_SUBVENDOR_ID_COMPAQ
,
12041 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2
, TG3_PHY_ID_BCM5701
},
12044 { TG3PCI_SUBVENDOR_ID_IBM
,
12045 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2
, 0 }
12048 static struct subsys_tbl_ent
* __devinit
tg3_lookup_by_subsys(struct tg3
*tp
)
12052 for (i
= 0; i
< ARRAY_SIZE(subsys_id_to_phy_id
); i
++) {
12053 if ((subsys_id_to_phy_id
[i
].subsys_vendor
==
12054 tp
->pdev
->subsystem_vendor
) &&
12055 (subsys_id_to_phy_id
[i
].subsys_devid
==
12056 tp
->pdev
->subsystem_device
))
12057 return &subsys_id_to_phy_id
[i
];
12062 static void __devinit
tg3_get_eeprom_hw_cfg(struct tg3
*tp
)
12067 /* On some early chips the SRAM cannot be accessed in D3hot state,
12068 * so need make sure we're in D0.
12070 pci_read_config_word(tp
->pdev
, tp
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
12071 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
12072 pci_write_config_word(tp
->pdev
, tp
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
12075 /* Make sure register accesses (indirect or otherwise)
12076 * will function correctly.
12078 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
12079 tp
->misc_host_ctrl
);
12081 /* The memory arbiter has to be enabled in order for SRAM accesses
12082 * to succeed. Normally on powerup the tg3 chip firmware will make
12083 * sure it is enabled, but other entities such as system netboot
12084 * code might disable it.
12086 val
= tr32(MEMARB_MODE
);
12087 tw32(MEMARB_MODE
, val
| MEMARB_MODE_ENABLE
);
12089 tp
->phy_id
= TG3_PHY_ID_INVALID
;
12090 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
12092 /* Assume an onboard device and WOL capable by default. */
12093 tp
->tg3_flags
|= TG3_FLAG_EEPROM_WRITE_PROT
| TG3_FLAG_WOL_CAP
;
12095 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
12096 if (!(tr32(PCIE_TRANSACTION_CFG
) & PCIE_TRANS_CFG_LOM
)) {
12097 tp
->tg3_flags
&= ~TG3_FLAG_EEPROM_WRITE_PROT
;
12098 tp
->tg3_flags2
|= TG3_FLG2_IS_NIC
;
12100 val
= tr32(VCPU_CFGSHDW
);
12101 if (val
& VCPU_CFGSHDW_ASPM_DBNC
)
12102 tp
->tg3_flags
|= TG3_FLAG_ASPM_WORKAROUND
;
12103 if ((val
& VCPU_CFGSHDW_WOL_ENABLE
) &&
12104 (val
& VCPU_CFGSHDW_WOL_MAGPKT
))
12105 tp
->tg3_flags
|= TG3_FLAG_WOL_ENABLE
;
12109 tg3_read_mem(tp
, NIC_SRAM_DATA_SIG
, &val
);
12110 if (val
== NIC_SRAM_DATA_SIG_MAGIC
) {
12111 u32 nic_cfg
, led_cfg
;
12112 u32 nic_phy_id
, ver
, cfg2
= 0, cfg4
= 0, eeprom_phy_id
;
12113 int eeprom_phy_serdes
= 0;
12115 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG
, &nic_cfg
);
12116 tp
->nic_sram_data_cfg
= nic_cfg
;
12118 tg3_read_mem(tp
, NIC_SRAM_DATA_VER
, &ver
);
12119 ver
>>= NIC_SRAM_DATA_VER_SHIFT
;
12120 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
) &&
12121 (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
) &&
12122 (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5703
) &&
12123 (ver
> 0) && (ver
< 0x100))
12124 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG_2
, &cfg2
);
12126 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
12127 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG_4
, &cfg4
);
12129 if ((nic_cfg
& NIC_SRAM_DATA_CFG_PHY_TYPE_MASK
) ==
12130 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER
)
12131 eeprom_phy_serdes
= 1;
12133 tg3_read_mem(tp
, NIC_SRAM_DATA_PHY_ID
, &nic_phy_id
);
12134 if (nic_phy_id
!= 0) {
12135 u32 id1
= nic_phy_id
& NIC_SRAM_DATA_PHY_ID1_MASK
;
12136 u32 id2
= nic_phy_id
& NIC_SRAM_DATA_PHY_ID2_MASK
;
12138 eeprom_phy_id
= (id1
>> 16) << 10;
12139 eeprom_phy_id
|= (id2
& 0xfc00) << 16;
12140 eeprom_phy_id
|= (id2
& 0x03ff) << 0;
12144 tp
->phy_id
= eeprom_phy_id
;
12145 if (eeprom_phy_serdes
) {
12146 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
12147 tp
->phy_flags
|= TG3_PHYFLG_PHY_SERDES
;
12149 tp
->phy_flags
|= TG3_PHYFLG_MII_SERDES
;
12152 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
12153 led_cfg
= cfg2
& (NIC_SRAM_DATA_CFG_LED_MODE_MASK
|
12154 SHASTA_EXT_LED_MODE_MASK
);
12156 led_cfg
= nic_cfg
& NIC_SRAM_DATA_CFG_LED_MODE_MASK
;
12160 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1
:
12161 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
12164 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2
:
12165 tp
->led_ctrl
= LED_CTRL_MODE_PHY_2
;
12168 case NIC_SRAM_DATA_CFG_LED_MODE_MAC
:
12169 tp
->led_ctrl
= LED_CTRL_MODE_MAC
;
12171 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12172 * read on some older 5700/5701 bootcode.
12174 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
12176 GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
12178 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
12182 case SHASTA_EXT_LED_SHARED
:
12183 tp
->led_ctrl
= LED_CTRL_MODE_SHARED
;
12184 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
&&
12185 tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A1
)
12186 tp
->led_ctrl
|= (LED_CTRL_MODE_PHY_1
|
12187 LED_CTRL_MODE_PHY_2
);
12190 case SHASTA_EXT_LED_MAC
:
12191 tp
->led_ctrl
= LED_CTRL_MODE_SHASTA_MAC
;
12194 case SHASTA_EXT_LED_COMBO
:
12195 tp
->led_ctrl
= LED_CTRL_MODE_COMBO
;
12196 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
)
12197 tp
->led_ctrl
|= (LED_CTRL_MODE_PHY_1
|
12198 LED_CTRL_MODE_PHY_2
);
12203 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
12204 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) &&
12205 tp
->pdev
->subsystem_vendor
== PCI_VENDOR_ID_DELL
)
12206 tp
->led_ctrl
= LED_CTRL_MODE_PHY_2
;
12208 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
)
12209 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
12211 if (nic_cfg
& NIC_SRAM_DATA_CFG_EEPROM_WP
) {
12212 tp
->tg3_flags
|= TG3_FLAG_EEPROM_WRITE_PROT
;
12213 if ((tp
->pdev
->subsystem_vendor
==
12214 PCI_VENDOR_ID_ARIMA
) &&
12215 (tp
->pdev
->subsystem_device
== 0x205a ||
12216 tp
->pdev
->subsystem_device
== 0x2063))
12217 tp
->tg3_flags
&= ~TG3_FLAG_EEPROM_WRITE_PROT
;
12219 tp
->tg3_flags
&= ~TG3_FLAG_EEPROM_WRITE_PROT
;
12220 tp
->tg3_flags2
|= TG3_FLG2_IS_NIC
;
12223 if (nic_cfg
& NIC_SRAM_DATA_CFG_ASF_ENABLE
) {
12224 tp
->tg3_flags
|= TG3_FLAG_ENABLE_ASF
;
12225 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
12226 tp
->tg3_flags2
|= TG3_FLG2_ASF_NEW_HANDSHAKE
;
12229 if ((nic_cfg
& NIC_SRAM_DATA_CFG_APE_ENABLE
) &&
12230 (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
))
12231 tp
->tg3_flags3
|= TG3_FLG3_ENABLE_APE
;
12233 if (tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
&&
12234 !(nic_cfg
& NIC_SRAM_DATA_CFG_FIBER_WOL
))
12235 tp
->tg3_flags
&= ~TG3_FLAG_WOL_CAP
;
12237 if ((tp
->tg3_flags
& TG3_FLAG_WOL_CAP
) &&
12238 (nic_cfg
& NIC_SRAM_DATA_CFG_WOL_ENABLE
))
12239 tp
->tg3_flags
|= TG3_FLAG_WOL_ENABLE
;
12241 if (cfg2
& (1 << 17))
12242 tp
->phy_flags
|= TG3_PHYFLG_CAPACITIVE_COUPLING
;
12244 /* serdes signal pre-emphasis in register 0x590 set by */
12245 /* bootcode if bit 18 is set */
12246 if (cfg2
& (1 << 18))
12247 tp
->phy_flags
|= TG3_PHYFLG_SERDES_PREEMPHASIS
;
12249 if (((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
12250 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
)) &&
12251 (cfg2
& NIC_SRAM_DATA_CFG_2_APD_EN
))
12252 tp
->phy_flags
|= TG3_PHYFLG_ENABLE_APD
;
12254 if ((tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) &&
12255 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5785
&&
12256 !(tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
)) {
12259 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG_3
, &cfg3
);
12260 if (cfg3
& NIC_SRAM_ASPM_DEBOUNCE
)
12261 tp
->tg3_flags
|= TG3_FLAG_ASPM_WORKAROUND
;
12264 if (cfg4
& NIC_SRAM_RGMII_INBAND_DISABLE
)
12265 tp
->tg3_flags3
|= TG3_FLG3_RGMII_INBAND_DISABLE
;
12266 if (cfg4
& NIC_SRAM_RGMII_EXT_IBND_RX_EN
)
12267 tp
->tg3_flags3
|= TG3_FLG3_RGMII_EXT_IBND_RX_EN
;
12268 if (cfg4
& NIC_SRAM_RGMII_EXT_IBND_TX_EN
)
12269 tp
->tg3_flags3
|= TG3_FLG3_RGMII_EXT_IBND_TX_EN
;
12272 device_init_wakeup(&tp
->pdev
->dev
, tp
->tg3_flags
& TG3_FLAG_WOL_CAP
);
12273 device_set_wakeup_enable(&tp
->pdev
->dev
,
12274 tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
);
12277 static int __devinit
tg3_issue_otp_command(struct tg3
*tp
, u32 cmd
)
12282 tw32(OTP_CTRL
, cmd
| OTP_CTRL_OTP_CMD_START
);
12283 tw32(OTP_CTRL
, cmd
);
12285 /* Wait for up to 1 ms for command to execute. */
12286 for (i
= 0; i
< 100; i
++) {
12287 val
= tr32(OTP_STATUS
);
12288 if (val
& OTP_STATUS_CMD_DONE
)
12293 return (val
& OTP_STATUS_CMD_DONE
) ? 0 : -EBUSY
;
12296 /* Read the gphy configuration from the OTP region of the chip. The gphy
12297 * configuration is a 32-bit value that straddles the alignment boundary.
12298 * We do two 32-bit reads and then shift and merge the results.
12300 static u32 __devinit
tg3_read_otp_phycfg(struct tg3
*tp
)
12302 u32 bhalf_otp
, thalf_otp
;
12304 tw32(OTP_MODE
, OTP_MODE_OTP_THRU_GRC
);
12306 if (tg3_issue_otp_command(tp
, OTP_CTRL_OTP_CMD_INIT
))
12309 tw32(OTP_ADDRESS
, OTP_ADDRESS_MAGIC1
);
12311 if (tg3_issue_otp_command(tp
, OTP_CTRL_OTP_CMD_READ
))
12314 thalf_otp
= tr32(OTP_READ_DATA
);
12316 tw32(OTP_ADDRESS
, OTP_ADDRESS_MAGIC2
);
12318 if (tg3_issue_otp_command(tp
, OTP_CTRL_OTP_CMD_READ
))
12321 bhalf_otp
= tr32(OTP_READ_DATA
);
12323 return ((thalf_otp
& 0x0000ffff) << 16) | (bhalf_otp
>> 16);
12326 static int __devinit
tg3_phy_probe(struct tg3
*tp
)
12328 u32 hw_phy_id_1
, hw_phy_id_2
;
12329 u32 hw_phy_id
, hw_phy_id_masked
;
12332 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
)
12333 return tg3_phy_init(tp
);
12335 /* Reading the PHY ID register can conflict with ASF
12336 * firmware access to the PHY hardware.
12339 if ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) ||
12340 (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)) {
12341 hw_phy_id
= hw_phy_id_masked
= TG3_PHY_ID_INVALID
;
12343 /* Now read the physical PHY_ID from the chip and verify
12344 * that it is sane. If it doesn't look good, we fall back
12345 * to either the hard-coded table based PHY_ID and failing
12346 * that the value found in the eeprom area.
12348 err
|= tg3_readphy(tp
, MII_PHYSID1
, &hw_phy_id_1
);
12349 err
|= tg3_readphy(tp
, MII_PHYSID2
, &hw_phy_id_2
);
12351 hw_phy_id
= (hw_phy_id_1
& 0xffff) << 10;
12352 hw_phy_id
|= (hw_phy_id_2
& 0xfc00) << 16;
12353 hw_phy_id
|= (hw_phy_id_2
& 0x03ff) << 0;
12355 hw_phy_id_masked
= hw_phy_id
& TG3_PHY_ID_MASK
;
12358 if (!err
&& TG3_KNOWN_PHY_ID(hw_phy_id_masked
)) {
12359 tp
->phy_id
= hw_phy_id
;
12360 if (hw_phy_id_masked
== TG3_PHY_ID_BCM8002
)
12361 tp
->phy_flags
|= TG3_PHYFLG_PHY_SERDES
;
12363 tp
->phy_flags
&= ~TG3_PHYFLG_PHY_SERDES
;
12365 if (tp
->phy_id
!= TG3_PHY_ID_INVALID
) {
12366 /* Do nothing, phy ID already set up in
12367 * tg3_get_eeprom_hw_cfg().
12370 struct subsys_tbl_ent
*p
;
12372 /* No eeprom signature? Try the hardcoded
12373 * subsys device table.
12375 p
= tg3_lookup_by_subsys(tp
);
12379 tp
->phy_id
= p
->phy_id
;
12381 tp
->phy_id
== TG3_PHY_ID_BCM8002
)
12382 tp
->phy_flags
|= TG3_PHYFLG_PHY_SERDES
;
12386 if (!(tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
) &&
12387 !(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) &&
12388 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)) {
12389 u32 bmsr
, adv_reg
, tg3_ctrl
, mask
;
12391 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
12392 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
12393 (bmsr
& BMSR_LSTATUS
))
12394 goto skip_phy_reset
;
12396 err
= tg3_phy_reset(tp
);
12400 adv_reg
= (ADVERTISE_10HALF
| ADVERTISE_10FULL
|
12401 ADVERTISE_100HALF
| ADVERTISE_100FULL
|
12402 ADVERTISE_CSMA
| ADVERTISE_PAUSE_CAP
);
12404 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
)) {
12405 tg3_ctrl
= (MII_TG3_CTRL_ADV_1000_HALF
|
12406 MII_TG3_CTRL_ADV_1000_FULL
);
12407 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
12408 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
)
12409 tg3_ctrl
|= (MII_TG3_CTRL_AS_MASTER
|
12410 MII_TG3_CTRL_ENABLE_AS_MASTER
);
12413 mask
= (ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
12414 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
|
12415 ADVERTISED_1000baseT_Half
| ADVERTISED_1000baseT_Full
);
12416 if (!tg3_copper_is_advertising_all(tp
, mask
)) {
12417 tg3_writephy(tp
, MII_ADVERTISE
, adv_reg
);
12419 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
))
12420 tg3_writephy(tp
, MII_TG3_CTRL
, tg3_ctrl
);
12422 tg3_writephy(tp
, MII_BMCR
,
12423 BMCR_ANENABLE
| BMCR_ANRESTART
);
12425 tg3_phy_set_wirespeed(tp
);
12427 tg3_writephy(tp
, MII_ADVERTISE
, adv_reg
);
12428 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
))
12429 tg3_writephy(tp
, MII_TG3_CTRL
, tg3_ctrl
);
12433 if ((tp
->phy_id
& TG3_PHY_ID_MASK
) == TG3_PHY_ID_BCM5401
) {
12434 err
= tg3_init_5401phy_dsp(tp
);
12438 err
= tg3_init_5401phy_dsp(tp
);
12441 if (tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
)
12442 tp
->link_config
.advertising
=
12443 (ADVERTISED_1000baseT_Half
|
12444 ADVERTISED_1000baseT_Full
|
12445 ADVERTISED_Autoneg
|
12447 if (tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
)
12448 tp
->link_config
.advertising
&=
12449 ~(ADVERTISED_1000baseT_Half
|
12450 ADVERTISED_1000baseT_Full
);
12455 static void __devinit
tg3_read_vpd(struct tg3
*tp
)
12458 unsigned int block_end
, rosize
, len
;
12462 if ((tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) ||
12463 tg3_nvram_read(tp
, 0x0, &magic
))
12466 vpd_data
= kmalloc(TG3_NVM_VPD_LEN
, GFP_KERNEL
);
12470 if (magic
== TG3_EEPROM_MAGIC
) {
12471 for (i
= 0; i
< TG3_NVM_VPD_LEN
; i
+= 4) {
12474 /* The data is in little-endian format in NVRAM.
12475 * Use the big-endian read routines to preserve
12476 * the byte order as it exists in NVRAM.
12478 if (tg3_nvram_read_be32(tp
, TG3_NVM_VPD_OFF
+ i
, &tmp
))
12479 goto out_not_found
;
12481 memcpy(&vpd_data
[i
], &tmp
, sizeof(tmp
));
12485 unsigned int pos
= 0;
12487 for (; pos
< TG3_NVM_VPD_LEN
&& i
< 3; i
++, pos
+= cnt
) {
12488 cnt
= pci_read_vpd(tp
->pdev
, pos
,
12489 TG3_NVM_VPD_LEN
- pos
,
12491 if (cnt
== -ETIMEDOUT
|| -EINTR
)
12494 goto out_not_found
;
12496 if (pos
!= TG3_NVM_VPD_LEN
)
12497 goto out_not_found
;
12500 i
= pci_vpd_find_tag(vpd_data
, 0, TG3_NVM_VPD_LEN
,
12501 PCI_VPD_LRDT_RO_DATA
);
12503 goto out_not_found
;
12505 rosize
= pci_vpd_lrdt_size(&vpd_data
[i
]);
12506 block_end
= i
+ PCI_VPD_LRDT_TAG_SIZE
+ rosize
;
12507 i
+= PCI_VPD_LRDT_TAG_SIZE
;
12509 if (block_end
> TG3_NVM_VPD_LEN
)
12510 goto out_not_found
;
12512 j
= pci_vpd_find_info_keyword(vpd_data
, i
, rosize
,
12513 PCI_VPD_RO_KEYWORD_MFR_ID
);
12515 len
= pci_vpd_info_field_size(&vpd_data
[j
]);
12517 j
+= PCI_VPD_INFO_FLD_HDR_SIZE
;
12518 if (j
+ len
> block_end
|| len
!= 4 ||
12519 memcmp(&vpd_data
[j
], "1028", 4))
12522 j
= pci_vpd_find_info_keyword(vpd_data
, i
, rosize
,
12523 PCI_VPD_RO_KEYWORD_VENDOR0
);
12527 len
= pci_vpd_info_field_size(&vpd_data
[j
]);
12529 j
+= PCI_VPD_INFO_FLD_HDR_SIZE
;
12530 if (j
+ len
> block_end
)
12533 memcpy(tp
->fw_ver
, &vpd_data
[j
], len
);
12534 strncat(tp
->fw_ver
, " bc ", TG3_NVM_VPD_LEN
- len
- 1);
12538 i
= pci_vpd_find_info_keyword(vpd_data
, i
, rosize
,
12539 PCI_VPD_RO_KEYWORD_PARTNO
);
12541 goto out_not_found
;
12543 len
= pci_vpd_info_field_size(&vpd_data
[i
]);
12545 i
+= PCI_VPD_INFO_FLD_HDR_SIZE
;
12546 if (len
> TG3_BPN_SIZE
||
12547 (len
+ i
) > TG3_NVM_VPD_LEN
)
12548 goto out_not_found
;
12550 memcpy(tp
->board_part_number
, &vpd_data
[i
], len
);
12554 if (tp
->board_part_number
[0])
12558 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
) {
12559 if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5717
)
12560 strcpy(tp
->board_part_number
, "BCM5717");
12561 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5718
)
12562 strcpy(tp
->board_part_number
, "BCM5718");
12565 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
) {
12566 if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57780
)
12567 strcpy(tp
->board_part_number
, "BCM57780");
12568 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57760
)
12569 strcpy(tp
->board_part_number
, "BCM57760");
12570 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57790
)
12571 strcpy(tp
->board_part_number
, "BCM57790");
12572 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57788
)
12573 strcpy(tp
->board_part_number
, "BCM57788");
12576 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
) {
12577 if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57761
)
12578 strcpy(tp
->board_part_number
, "BCM57761");
12579 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57765
)
12580 strcpy(tp
->board_part_number
, "BCM57765");
12581 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57781
)
12582 strcpy(tp
->board_part_number
, "BCM57781");
12583 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57785
)
12584 strcpy(tp
->board_part_number
, "BCM57785");
12585 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57791
)
12586 strcpy(tp
->board_part_number
, "BCM57791");
12587 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57795
)
12588 strcpy(tp
->board_part_number
, "BCM57795");
12591 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
12592 strcpy(tp
->board_part_number
, "BCM95906");
12595 strcpy(tp
->board_part_number
, "none");
12599 static int __devinit
tg3_fw_img_is_valid(struct tg3
*tp
, u32 offset
)
12603 if (tg3_nvram_read(tp
, offset
, &val
) ||
12604 (val
& 0xfc000000) != 0x0c000000 ||
12605 tg3_nvram_read(tp
, offset
+ 4, &val
) ||
12612 static void __devinit
tg3_read_bc_ver(struct tg3
*tp
)
12614 u32 val
, offset
, start
, ver_offset
;
12616 bool newver
= false;
12618 if (tg3_nvram_read(tp
, 0xc, &offset
) ||
12619 tg3_nvram_read(tp
, 0x4, &start
))
12622 offset
= tg3_nvram_logical_addr(tp
, offset
);
12624 if (tg3_nvram_read(tp
, offset
, &val
))
12627 if ((val
& 0xfc000000) == 0x0c000000) {
12628 if (tg3_nvram_read(tp
, offset
+ 4, &val
))
12635 dst_off
= strlen(tp
->fw_ver
);
12638 if (TG3_VER_SIZE
- dst_off
< 16 ||
12639 tg3_nvram_read(tp
, offset
+ 8, &ver_offset
))
12642 offset
= offset
+ ver_offset
- start
;
12643 for (i
= 0; i
< 16; i
+= 4) {
12645 if (tg3_nvram_read_be32(tp
, offset
+ i
, &v
))
12648 memcpy(tp
->fw_ver
+ dst_off
+ i
, &v
, sizeof(v
));
12653 if (tg3_nvram_read(tp
, TG3_NVM_PTREV_BCVER
, &ver_offset
))
12656 major
= (ver_offset
& TG3_NVM_BCVER_MAJMSK
) >>
12657 TG3_NVM_BCVER_MAJSFT
;
12658 minor
= ver_offset
& TG3_NVM_BCVER_MINMSK
;
12659 snprintf(&tp
->fw_ver
[dst_off
], TG3_VER_SIZE
- dst_off
,
12660 "v%d.%02d", major
, minor
);
12664 static void __devinit
tg3_read_hwsb_ver(struct tg3
*tp
)
12666 u32 val
, major
, minor
;
12668 /* Use native endian representation */
12669 if (tg3_nvram_read(tp
, TG3_NVM_HWSB_CFG1
, &val
))
12672 major
= (val
& TG3_NVM_HWSB_CFG1_MAJMSK
) >>
12673 TG3_NVM_HWSB_CFG1_MAJSFT
;
12674 minor
= (val
& TG3_NVM_HWSB_CFG1_MINMSK
) >>
12675 TG3_NVM_HWSB_CFG1_MINSFT
;
12677 snprintf(&tp
->fw_ver
[0], 32, "sb v%d.%02d", major
, minor
);
12680 static void __devinit
tg3_read_sb_ver(struct tg3
*tp
, u32 val
)
12682 u32 offset
, major
, minor
, build
;
12684 strncat(tp
->fw_ver
, "sb", TG3_VER_SIZE
- strlen(tp
->fw_ver
) - 1);
12686 if ((val
& TG3_EEPROM_SB_FORMAT_MASK
) != TG3_EEPROM_SB_FORMAT_1
)
12689 switch (val
& TG3_EEPROM_SB_REVISION_MASK
) {
12690 case TG3_EEPROM_SB_REVISION_0
:
12691 offset
= TG3_EEPROM_SB_F1R0_EDH_OFF
;
12693 case TG3_EEPROM_SB_REVISION_2
:
12694 offset
= TG3_EEPROM_SB_F1R2_EDH_OFF
;
12696 case TG3_EEPROM_SB_REVISION_3
:
12697 offset
= TG3_EEPROM_SB_F1R3_EDH_OFF
;
12699 case TG3_EEPROM_SB_REVISION_4
:
12700 offset
= TG3_EEPROM_SB_F1R4_EDH_OFF
;
12702 case TG3_EEPROM_SB_REVISION_5
:
12703 offset
= TG3_EEPROM_SB_F1R5_EDH_OFF
;
12709 if (tg3_nvram_read(tp
, offset
, &val
))
12712 build
= (val
& TG3_EEPROM_SB_EDH_BLD_MASK
) >>
12713 TG3_EEPROM_SB_EDH_BLD_SHFT
;
12714 major
= (val
& TG3_EEPROM_SB_EDH_MAJ_MASK
) >>
12715 TG3_EEPROM_SB_EDH_MAJ_SHFT
;
12716 minor
= val
& TG3_EEPROM_SB_EDH_MIN_MASK
;
12718 if (minor
> 99 || build
> 26)
12721 offset
= strlen(tp
->fw_ver
);
12722 snprintf(&tp
->fw_ver
[offset
], TG3_VER_SIZE
- offset
,
12723 " v%d.%02d", major
, minor
);
12726 offset
= strlen(tp
->fw_ver
);
12727 if (offset
< TG3_VER_SIZE
- 1)
12728 tp
->fw_ver
[offset
] = 'a' + build
- 1;
12732 static void __devinit
tg3_read_mgmtfw_ver(struct tg3
*tp
)
12734 u32 val
, offset
, start
;
12737 for (offset
= TG3_NVM_DIR_START
;
12738 offset
< TG3_NVM_DIR_END
;
12739 offset
+= TG3_NVM_DIRENT_SIZE
) {
12740 if (tg3_nvram_read(tp
, offset
, &val
))
12743 if ((val
>> TG3_NVM_DIRTYPE_SHIFT
) == TG3_NVM_DIRTYPE_ASFINI
)
12747 if (offset
== TG3_NVM_DIR_END
)
12750 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
12751 start
= 0x08000000;
12752 else if (tg3_nvram_read(tp
, offset
- 4, &start
))
12755 if (tg3_nvram_read(tp
, offset
+ 4, &offset
) ||
12756 !tg3_fw_img_is_valid(tp
, offset
) ||
12757 tg3_nvram_read(tp
, offset
+ 8, &val
))
12760 offset
+= val
- start
;
12762 vlen
= strlen(tp
->fw_ver
);
12764 tp
->fw_ver
[vlen
++] = ',';
12765 tp
->fw_ver
[vlen
++] = ' ';
12767 for (i
= 0; i
< 4; i
++) {
12769 if (tg3_nvram_read_be32(tp
, offset
, &v
))
12772 offset
+= sizeof(v
);
12774 if (vlen
> TG3_VER_SIZE
- sizeof(v
)) {
12775 memcpy(&tp
->fw_ver
[vlen
], &v
, TG3_VER_SIZE
- vlen
);
12779 memcpy(&tp
->fw_ver
[vlen
], &v
, sizeof(v
));
12784 static void __devinit
tg3_read_dash_ver(struct tg3
*tp
)
12790 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) ||
12791 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
12794 apedata
= tg3_ape_read32(tp
, TG3_APE_SEG_SIG
);
12795 if (apedata
!= APE_SEG_SIG_MAGIC
)
12798 apedata
= tg3_ape_read32(tp
, TG3_APE_FW_STATUS
);
12799 if (!(apedata
& APE_FW_STATUS_READY
))
12802 apedata
= tg3_ape_read32(tp
, TG3_APE_FW_VERSION
);
12804 if (tg3_ape_read32(tp
, TG3_APE_FW_FEATURES
) & TG3_APE_FW_FEATURE_NCSI
) {
12805 tp
->tg3_flags3
|= TG3_FLG3_APE_HAS_NCSI
;
12811 vlen
= strlen(tp
->fw_ver
);
12813 snprintf(&tp
->fw_ver
[vlen
], TG3_VER_SIZE
- vlen
, " %s v%d.%d.%d.%d",
12815 (apedata
& APE_FW_VERSION_MAJMSK
) >> APE_FW_VERSION_MAJSFT
,
12816 (apedata
& APE_FW_VERSION_MINMSK
) >> APE_FW_VERSION_MINSFT
,
12817 (apedata
& APE_FW_VERSION_REVMSK
) >> APE_FW_VERSION_REVSFT
,
12818 (apedata
& APE_FW_VERSION_BLDMSK
));
12821 static void __devinit
tg3_read_fw_ver(struct tg3
*tp
)
12824 bool vpd_vers
= false;
12826 if (tp
->fw_ver
[0] != 0)
12829 if (tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) {
12830 strcat(tp
->fw_ver
, "sb");
12834 if (tg3_nvram_read(tp
, 0, &val
))
12837 if (val
== TG3_EEPROM_MAGIC
)
12838 tg3_read_bc_ver(tp
);
12839 else if ((val
& TG3_EEPROM_MAGIC_FW_MSK
) == TG3_EEPROM_MAGIC_FW
)
12840 tg3_read_sb_ver(tp
, val
);
12841 else if ((val
& TG3_EEPROM_MAGIC_HW_MSK
) == TG3_EEPROM_MAGIC_HW
)
12842 tg3_read_hwsb_ver(tp
);
12846 if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) ||
12847 (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) || vpd_vers
)
12850 tg3_read_mgmtfw_ver(tp
);
12853 tp
->fw_ver
[TG3_VER_SIZE
- 1] = 0;
12856 static struct pci_dev
* __devinit
tg3_find_peer(struct tg3
*);
12858 static void inline vlan_features_add(struct net_device
*dev
, unsigned long flags
)
12860 #if TG3_VLAN_TAG_USED
12861 dev
->vlan_features
|= flags
;
12865 static inline u32
tg3_rx_ret_ring_size(struct tg3
*tp
)
12867 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
12868 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
)
12870 else if ((tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) &&
12871 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
12877 static int __devinit
tg3_get_invariants(struct tg3
*tp
)
12879 static struct pci_device_id write_reorder_chipsets
[] = {
12880 { PCI_DEVICE(PCI_VENDOR_ID_AMD
,
12881 PCI_DEVICE_ID_AMD_FE_GATE_700C
) },
12882 { PCI_DEVICE(PCI_VENDOR_ID_AMD
,
12883 PCI_DEVICE_ID_AMD_8131_BRIDGE
) },
12884 { PCI_DEVICE(PCI_VENDOR_ID_VIA
,
12885 PCI_DEVICE_ID_VIA_8385_0
) },
12889 u32 pci_state_reg
, grc_misc_cfg
;
12894 /* Force memory write invalidate off. If we leave it on,
12895 * then on 5700_BX chips we have to enable a workaround.
12896 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12897 * to match the cacheline size. The Broadcom driver have this
12898 * workaround but turns MWI off all the times so never uses
12899 * it. This seems to suggest that the workaround is insufficient.
12901 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
12902 pci_cmd
&= ~PCI_COMMAND_INVALIDATE
;
12903 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
12905 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12906 * has the register indirect write enable bit set before
12907 * we try to access any of the MMIO registers. It is also
12908 * critical that the PCI-X hw workaround situation is decided
12909 * before that as well.
12911 pci_read_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
12914 tp
->pci_chip_rev_id
= (misc_ctrl_reg
>>
12915 MISC_HOST_CTRL_CHIPREV_SHIFT
);
12916 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_USE_PROD_ID_REG
) {
12917 u32 prod_id_asic_rev
;
12919 if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5717
||
12920 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5718
||
12921 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5719
)
12922 pci_read_config_dword(tp
->pdev
,
12923 TG3PCI_GEN2_PRODID_ASICREV
,
12924 &prod_id_asic_rev
);
12925 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57781
||
12926 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57785
||
12927 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57761
||
12928 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57765
||
12929 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57791
||
12930 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57795
)
12931 pci_read_config_dword(tp
->pdev
,
12932 TG3PCI_GEN15_PRODID_ASICREV
,
12933 &prod_id_asic_rev
);
12935 pci_read_config_dword(tp
->pdev
, TG3PCI_PRODID_ASICREV
,
12936 &prod_id_asic_rev
);
12938 tp
->pci_chip_rev_id
= prod_id_asic_rev
;
12941 /* Wrong chip ID in 5752 A0. This code can be removed later
12942 * as A0 is not in production.
12944 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5752_A0_HW
)
12945 tp
->pci_chip_rev_id
= CHIPREV_ID_5752_A0
;
12947 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12948 * we need to disable memory and use config. cycles
12949 * only to access all registers. The 5702/03 chips
12950 * can mistakenly decode the special cycles from the
12951 * ICH chipsets as memory write cycles, causing corruption
12952 * of register and memory space. Only certain ICH bridges
12953 * will drive special cycles with non-zero data during the
12954 * address phase which can fall within the 5703's address
12955 * range. This is not an ICH bug as the PCI spec allows
12956 * non-zero address during special cycles. However, only
12957 * these ICH bridges are known to drive non-zero addresses
12958 * during special cycles.
12960 * Since special cycles do not cross PCI bridges, we only
12961 * enable this workaround if the 5703 is on the secondary
12962 * bus of these ICH bridges.
12964 if ((tp
->pci_chip_rev_id
== CHIPREV_ID_5703_A1
) ||
12965 (tp
->pci_chip_rev_id
== CHIPREV_ID_5703_A2
)) {
12966 static struct tg3_dev_id
{
12970 } ich_chipsets
[] = {
12971 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AA_8
,
12973 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AB_8
,
12975 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_11
,
12977 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_6
,
12981 struct tg3_dev_id
*pci_id
= &ich_chipsets
[0];
12982 struct pci_dev
*bridge
= NULL
;
12984 while (pci_id
->vendor
!= 0) {
12985 bridge
= pci_get_device(pci_id
->vendor
, pci_id
->device
,
12991 if (pci_id
->rev
!= PCI_ANY_ID
) {
12992 if (bridge
->revision
> pci_id
->rev
)
12995 if (bridge
->subordinate
&&
12996 (bridge
->subordinate
->number
==
12997 tp
->pdev
->bus
->number
)) {
12999 tp
->tg3_flags2
|= TG3_FLG2_ICH_WORKAROUND
;
13000 pci_dev_put(bridge
);
13006 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)) {
13007 static struct tg3_dev_id
{
13010 } bridge_chipsets
[] = {
13011 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_0
},
13012 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_1
},
13015 struct tg3_dev_id
*pci_id
= &bridge_chipsets
[0];
13016 struct pci_dev
*bridge
= NULL
;
13018 while (pci_id
->vendor
!= 0) {
13019 bridge
= pci_get_device(pci_id
->vendor
,
13026 if (bridge
->subordinate
&&
13027 (bridge
->subordinate
->number
<=
13028 tp
->pdev
->bus
->number
) &&
13029 (bridge
->subordinate
->subordinate
>=
13030 tp
->pdev
->bus
->number
)) {
13031 tp
->tg3_flags3
|= TG3_FLG3_5701_DMA_BUG
;
13032 pci_dev_put(bridge
);
13038 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
13039 * DMA addresses > 40-bit. This bridge may have other additional
13040 * 57xx devices behind it in some 4-port NIC designs for example.
13041 * Any tg3 device found behind the bridge will also need the 40-bit
13044 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5780
||
13045 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
) {
13046 tp
->tg3_flags2
|= TG3_FLG2_5780_CLASS
;
13047 tp
->tg3_flags
|= TG3_FLAG_40BIT_DMA_BUG
;
13048 tp
->msi_cap
= pci_find_capability(tp
->pdev
, PCI_CAP_ID_MSI
);
13050 struct pci_dev
*bridge
= NULL
;
13053 bridge
= pci_get_device(PCI_VENDOR_ID_SERVERWORKS
,
13054 PCI_DEVICE_ID_SERVERWORKS_EPB
,
13056 if (bridge
&& bridge
->subordinate
&&
13057 (bridge
->subordinate
->number
<=
13058 tp
->pdev
->bus
->number
) &&
13059 (bridge
->subordinate
->subordinate
>=
13060 tp
->pdev
->bus
->number
)) {
13061 tp
->tg3_flags
|= TG3_FLAG_40BIT_DMA_BUG
;
13062 pci_dev_put(bridge
);
13068 /* Initialize misc host control in PCI block. */
13069 tp
->misc_host_ctrl
|= (misc_ctrl_reg
&
13070 MISC_HOST_CTRL_CHIPREV
);
13071 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
13072 tp
->misc_host_ctrl
);
13074 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
13075 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
||
13076 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
)
13077 tp
->pdev_peer
= tg3_find_peer(tp
);
13079 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
13080 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
||
13081 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
13082 tp
->tg3_flags3
|= TG3_FLG3_5717_PLUS
;
13084 /* Intentionally exclude ASIC_REV_5906 */
13085 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
||
13086 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5787
||
13087 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
13088 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
13089 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
13090 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
||
13091 (tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
))
13092 tp
->tg3_flags3
|= TG3_FLG3_5755_PLUS
;
13094 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
||
13095 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
||
13096 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
||
13097 (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) ||
13098 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
13099 tp
->tg3_flags2
|= TG3_FLG2_5750_PLUS
;
13101 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) ||
13102 (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
))
13103 tp
->tg3_flags2
|= TG3_FLG2_5705_PLUS
;
13105 /* 5700 B0 chips do not support checksumming correctly due
13106 * to hardware bugs.
13108 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5700_B0
)
13109 tp
->tg3_flags
|= TG3_FLAG_BROKEN_CHECKSUMS
;
13111 unsigned long features
= NETIF_F_IP_CSUM
| NETIF_F_SG
| NETIF_F_GRO
;
13113 tp
->tg3_flags
|= TG3_FLAG_RX_CHECKSUMS
;
13114 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
13115 features
|= NETIF_F_IPV6_CSUM
;
13116 tp
->dev
->features
|= features
;
13117 vlan_features_add(tp
->dev
, features
);
13120 /* Determine TSO capabilities */
13121 if (tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
)
13122 tp
->tg3_flags2
|= TG3_FLG2_HW_TSO_3
;
13123 else if ((tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) ||
13124 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
13125 tp
->tg3_flags2
|= TG3_FLG2_HW_TSO_2
;
13126 else if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) {
13127 tp
->tg3_flags2
|= TG3_FLG2_HW_TSO_1
| TG3_FLG2_TSO_BUG
;
13128 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
&&
13129 tp
->pci_chip_rev_id
>= CHIPREV_ID_5750_C2
)
13130 tp
->tg3_flags2
&= ~TG3_FLG2_TSO_BUG
;
13131 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
13132 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
&&
13133 tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A0
) {
13134 tp
->tg3_flags2
|= TG3_FLG2_TSO_BUG
;
13135 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
)
13136 tp
->fw_needed
= FIRMWARE_TG3TSO5
;
13138 tp
->fw_needed
= FIRMWARE_TG3TSO
;
13143 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) {
13144 tp
->tg3_flags
|= TG3_FLAG_SUPPORT_MSI
;
13145 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_AX
||
13146 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_BX
||
13147 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
&&
13148 tp
->pci_chip_rev_id
<= CHIPREV_ID_5714_A2
&&
13149 tp
->pdev_peer
== tp
->pdev
))
13150 tp
->tg3_flags
&= ~TG3_FLAG_SUPPORT_MSI
;
13152 if ((tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) ||
13153 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
13154 tp
->tg3_flags2
|= TG3_FLG2_1SHOT_MSI
;
13157 if (tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
) {
13158 tp
->tg3_flags
|= TG3_FLAG_SUPPORT_MSIX
;
13159 tp
->irq_max
= TG3_IRQ_MAX_VECS
;
13163 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
13164 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
||
13165 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
13166 tp
->tg3_flags3
|= TG3_FLG3_SHORT_DMA_BUG
;
13167 else if (!(tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)) {
13168 tp
->tg3_flags3
|= TG3_FLG3_4G_DMA_BNDRY_BUG
;
13169 tp
->tg3_flags3
|= TG3_FLG3_40BIT_DMA_LIMIT_BUG
;
13172 if (tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
)
13173 tp
->tg3_flags3
|= TG3_FLG3_USE_JUMBO_BDFLAG
;
13175 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) ||
13176 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) ||
13177 (tp
->tg3_flags3
& TG3_FLG3_USE_JUMBO_BDFLAG
))
13178 tp
->tg3_flags
|= TG3_FLAG_JUMBO_CAPABLE
;
13180 pci_read_config_dword(tp
->pdev
, TG3PCI_PCISTATE
,
13183 tp
->pcie_cap
= pci_find_capability(tp
->pdev
, PCI_CAP_ID_EXP
);
13184 if (tp
->pcie_cap
!= 0) {
13187 tp
->tg3_flags2
|= TG3_FLG2_PCI_EXPRESS
;
13189 pcie_set_readrq(tp
->pdev
, 4096);
13191 pci_read_config_word(tp
->pdev
,
13192 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
13194 if (lnkctl
& PCI_EXP_LNKCTL_CLKREQ_EN
) {
13195 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
13196 tp
->tg3_flags2
&= ~TG3_FLG2_HW_TSO_2
;
13197 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
13198 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
13199 tp
->pci_chip_rev_id
== CHIPREV_ID_57780_A0
||
13200 tp
->pci_chip_rev_id
== CHIPREV_ID_57780_A1
)
13201 tp
->tg3_flags3
|= TG3_FLG3_CLKREQ_BUG
;
13202 } else if (tp
->pci_chip_rev_id
== CHIPREV_ID_5717_A0
) {
13203 tp
->tg3_flags3
|= TG3_FLG3_L1PLLPD_EN
;
13205 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
) {
13206 tp
->tg3_flags2
|= TG3_FLG2_PCI_EXPRESS
;
13207 } else if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) ||
13208 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
13209 tp
->pcix_cap
= pci_find_capability(tp
->pdev
, PCI_CAP_ID_PCIX
);
13210 if (!tp
->pcix_cap
) {
13211 dev_err(&tp
->pdev
->dev
,
13212 "Cannot find PCI-X capability, aborting\n");
13216 if (!(pci_state_reg
& PCISTATE_CONV_PCI_MODE
))
13217 tp
->tg3_flags
|= TG3_FLAG_PCIX_MODE
;
13220 /* If we have an AMD 762 or VIA K8T800 chipset, write
13221 * reordering to the mailbox registers done by the host
13222 * controller can cause major troubles. We read back from
13223 * every mailbox register write to force the writes to be
13224 * posted to the chip in order.
13226 if (pci_dev_present(write_reorder_chipsets
) &&
13227 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
))
13228 tp
->tg3_flags
|= TG3_FLAG_MBOX_WRITE_REORDER
;
13230 pci_read_config_byte(tp
->pdev
, PCI_CACHE_LINE_SIZE
,
13231 &tp
->pci_cacheline_sz
);
13232 pci_read_config_byte(tp
->pdev
, PCI_LATENCY_TIMER
,
13233 &tp
->pci_lat_timer
);
13234 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
&&
13235 tp
->pci_lat_timer
< 64) {
13236 tp
->pci_lat_timer
= 64;
13237 pci_write_config_byte(tp
->pdev
, PCI_LATENCY_TIMER
,
13238 tp
->pci_lat_timer
);
13241 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5700_BX
) {
13242 /* 5700 BX chips need to have their TX producer index
13243 * mailboxes written twice to workaround a bug.
13245 tp
->tg3_flags
|= TG3_FLAG_TXD_MBOX_HWBUG
;
13247 /* If we are in PCI-X mode, enable register write workaround.
13249 * The workaround is to use indirect register accesses
13250 * for all chip writes not to mailbox registers.
13252 if (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) {
13255 tp
->tg3_flags
|= TG3_FLAG_PCIX_TARGET_HWBUG
;
13257 /* The chip can have it's power management PCI config
13258 * space registers clobbered due to this bug.
13259 * So explicitly force the chip into D0 here.
13261 pci_read_config_dword(tp
->pdev
,
13262 tp
->pm_cap
+ PCI_PM_CTRL
,
13264 pm_reg
&= ~PCI_PM_CTRL_STATE_MASK
;
13265 pm_reg
|= PCI_PM_CTRL_PME_ENABLE
| 0 /* D0 */;
13266 pci_write_config_dword(tp
->pdev
,
13267 tp
->pm_cap
+ PCI_PM_CTRL
,
13270 /* Also, force SERR#/PERR# in PCI command. */
13271 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
13272 pci_cmd
|= PCI_COMMAND_PARITY
| PCI_COMMAND_SERR
;
13273 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
13277 if ((pci_state_reg
& PCISTATE_BUS_SPEED_HIGH
) != 0)
13278 tp
->tg3_flags
|= TG3_FLAG_PCI_HIGH_SPEED
;
13279 if ((pci_state_reg
& PCISTATE_BUS_32BIT
) != 0)
13280 tp
->tg3_flags
|= TG3_FLAG_PCI_32BIT
;
13282 /* Chip-specific fixup from Broadcom driver */
13283 if ((tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
) &&
13284 (!(pci_state_reg
& PCISTATE_RETRY_SAME_DMA
))) {
13285 pci_state_reg
|= PCISTATE_RETRY_SAME_DMA
;
13286 pci_write_config_dword(tp
->pdev
, TG3PCI_PCISTATE
, pci_state_reg
);
13289 /* Default fast path register access methods */
13290 tp
->read32
= tg3_read32
;
13291 tp
->write32
= tg3_write32
;
13292 tp
->read32_mbox
= tg3_read32
;
13293 tp
->write32_mbox
= tg3_write32
;
13294 tp
->write32_tx_mbox
= tg3_write32
;
13295 tp
->write32_rx_mbox
= tg3_write32
;
13297 /* Various workaround register access methods */
13298 if (tp
->tg3_flags
& TG3_FLAG_PCIX_TARGET_HWBUG
)
13299 tp
->write32
= tg3_write_indirect_reg32
;
13300 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
||
13301 ((tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) &&
13302 tp
->pci_chip_rev_id
== CHIPREV_ID_5750_A0
)) {
13304 * Back to back register writes can cause problems on these
13305 * chips, the workaround is to read back all reg writes
13306 * except those to mailbox regs.
13308 * See tg3_write_indirect_reg32().
13310 tp
->write32
= tg3_write_flush_reg32
;
13313 if ((tp
->tg3_flags
& TG3_FLAG_TXD_MBOX_HWBUG
) ||
13314 (tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
)) {
13315 tp
->write32_tx_mbox
= tg3_write32_tx_mbox
;
13316 if (tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
)
13317 tp
->write32_rx_mbox
= tg3_write_flush_reg32
;
13320 if (tp
->tg3_flags2
& TG3_FLG2_ICH_WORKAROUND
) {
13321 tp
->read32
= tg3_read_indirect_reg32
;
13322 tp
->write32
= tg3_write_indirect_reg32
;
13323 tp
->read32_mbox
= tg3_read_indirect_mbox
;
13324 tp
->write32_mbox
= tg3_write_indirect_mbox
;
13325 tp
->write32_tx_mbox
= tg3_write_indirect_mbox
;
13326 tp
->write32_rx_mbox
= tg3_write_indirect_mbox
;
13331 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
13332 pci_cmd
&= ~PCI_COMMAND_MEMORY
;
13333 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
13335 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
13336 tp
->read32_mbox
= tg3_read32_mbox_5906
;
13337 tp
->write32_mbox
= tg3_write32_mbox_5906
;
13338 tp
->write32_tx_mbox
= tg3_write32_mbox_5906
;
13339 tp
->write32_rx_mbox
= tg3_write32_mbox_5906
;
13342 if (tp
->write32
== tg3_write_indirect_reg32
||
13343 ((tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) &&
13344 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
13345 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)))
13346 tp
->tg3_flags
|= TG3_FLAG_SRAM_USE_CONFIG
;
13348 /* Get eeprom hw config before calling tg3_set_power_state().
13349 * In particular, the TG3_FLG2_IS_NIC flag must be
13350 * determined before calling tg3_set_power_state() so that
13351 * we know whether or not to switch out of Vaux power.
13352 * When the flag is set, it means that GPIO1 is used for eeprom
13353 * write protect and also implies that it is a LOM where GPIOs
13354 * are not used to switch power.
13356 tg3_get_eeprom_hw_cfg(tp
);
13358 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
13359 /* Allow reads and writes to the
13360 * APE register and memory space.
13362 pci_state_reg
|= PCISTATE_ALLOW_APE_CTLSPC_WR
|
13363 PCISTATE_ALLOW_APE_SHMEM_WR
|
13364 PCISTATE_ALLOW_APE_PSPACE_WR
;
13365 pci_write_config_dword(tp
->pdev
, TG3PCI_PCISTATE
,
13369 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
13370 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
13371 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
13372 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
||
13373 (tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
))
13374 tp
->tg3_flags
|= TG3_FLAG_CPMU_PRESENT
;
13376 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13377 * GPIO1 driven high will bring 5700's external PHY out of reset.
13378 * It is also used as eeprom write protect on LOMs.
13380 tp
->grc_local_ctrl
= GRC_LCLCTRL_INT_ON_ATTN
| GRC_LCLCTRL_AUTO_SEEPROM
;
13381 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) ||
13382 (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
))
13383 tp
->grc_local_ctrl
|= (GRC_LCLCTRL_GPIO_OE1
|
13384 GRC_LCLCTRL_GPIO_OUTPUT1
);
13385 /* Unused GPIO3 must be driven as output on 5752 because there
13386 * are no pull-up resistors on unused GPIO pins.
13388 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
)
13389 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE3
;
13391 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
||
13392 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
||
13393 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
13394 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_UART_SEL
;
13396 if (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5761
||
13397 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5761S
) {
13398 /* Turn off the debug UART. */
13399 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_UART_SEL
;
13400 if (tp
->tg3_flags2
& TG3_FLG2_IS_NIC
)
13401 /* Keep VMain power. */
13402 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE0
|
13403 GRC_LCLCTRL_GPIO_OUTPUT0
;
13406 /* Force the chip into D0. */
13407 err
= tg3_set_power_state(tp
, PCI_D0
);
13409 dev_err(&tp
->pdev
->dev
, "Transition to D0 failed\n");
13413 /* Derive initial jumbo mode from MTU assigned in
13414 * ether_setup() via the alloc_etherdev() call
13416 if (tp
->dev
->mtu
> ETH_DATA_LEN
&&
13417 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
13418 tp
->tg3_flags
|= TG3_FLAG_JUMBO_RING_ENABLE
;
13420 /* Determine WakeOnLan speed to use. */
13421 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
13422 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
13423 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
||
13424 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B2
) {
13425 tp
->tg3_flags
&= ~(TG3_FLAG_WOL_SPEED_100MB
);
13427 tp
->tg3_flags
|= TG3_FLAG_WOL_SPEED_100MB
;
13430 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
13431 tp
->phy_flags
|= TG3_PHYFLG_IS_FET
;
13433 /* A few boards don't want Ethernet@WireSpeed phy feature */
13434 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) ||
13435 ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) &&
13436 (tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A0
) &&
13437 (tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A1
)) ||
13438 (tp
->phy_flags
& TG3_PHYFLG_IS_FET
) ||
13439 (tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
))
13440 tp
->phy_flags
|= TG3_PHYFLG_NO_ETH_WIRE_SPEED
;
13442 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5703_AX
||
13443 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5704_AX
)
13444 tp
->phy_flags
|= TG3_PHYFLG_ADC_BUG
;
13445 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
)
13446 tp
->phy_flags
|= TG3_PHYFLG_5704_A0_BUG
;
13448 if ((tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
13449 !(tp
->phy_flags
& TG3_PHYFLG_IS_FET
) &&
13450 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5785
&&
13451 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_57780
&&
13452 !(tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
)) {
13453 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
||
13454 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5787
||
13455 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
13456 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
) {
13457 if (tp
->pdev
->device
!= PCI_DEVICE_ID_TIGON3_5756
&&
13458 tp
->pdev
->device
!= PCI_DEVICE_ID_TIGON3_5722
)
13459 tp
->phy_flags
|= TG3_PHYFLG_JITTER_BUG
;
13460 if (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5755M
)
13461 tp
->phy_flags
|= TG3_PHYFLG_ADJUST_TRIM
;
13463 tp
->phy_flags
|= TG3_PHYFLG_BER_BUG
;
13466 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
13467 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
) {
13468 tp
->phy_otp
= tg3_read_otp_phycfg(tp
);
13469 if (tp
->phy_otp
== 0)
13470 tp
->phy_otp
= TG3_OTP_DEFAULT
;
13473 if (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
)
13474 tp
->mi_mode
= MAC_MI_MODE_500KHZ_CONST
;
13476 tp
->mi_mode
= MAC_MI_MODE_BASE
;
13478 tp
->coalesce_mode
= 0;
13479 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5700_AX
&&
13480 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5700_BX
)
13481 tp
->coalesce_mode
|= HOSTCC_MODE_32BYTE
;
13483 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
13484 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
13485 tp
->tg3_flags3
|= TG3_FLG3_USE_PHYLIB
;
13487 err
= tg3_mdio_init(tp
);
13491 /* Initialize data/descriptor byte/word swapping. */
13492 val
= tr32(GRC_MODE
);
13493 val
&= GRC_MODE_HOST_STACKUP
;
13494 tw32(GRC_MODE
, val
| tp
->grc_mode
);
13496 tg3_switch_clocks(tp
);
13498 /* Clear this out for sanity. */
13499 tw32(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
13501 pci_read_config_dword(tp
->pdev
, TG3PCI_PCISTATE
,
13503 if ((pci_state_reg
& PCISTATE_CONV_PCI_MODE
) == 0 &&
13504 (tp
->tg3_flags
& TG3_FLAG_PCIX_TARGET_HWBUG
) == 0) {
13505 u32 chiprevid
= GET_CHIP_REV_ID(tp
->misc_host_ctrl
);
13507 if (chiprevid
== CHIPREV_ID_5701_A0
||
13508 chiprevid
== CHIPREV_ID_5701_B0
||
13509 chiprevid
== CHIPREV_ID_5701_B2
||
13510 chiprevid
== CHIPREV_ID_5701_B5
) {
13511 void __iomem
*sram_base
;
13513 /* Write some dummy words into the SRAM status block
13514 * area, see if it reads back correctly. If the return
13515 * value is bad, force enable the PCIX workaround.
13517 sram_base
= tp
->regs
+ NIC_SRAM_WIN_BASE
+ NIC_SRAM_STATS_BLK
;
13519 writel(0x00000000, sram_base
);
13520 writel(0x00000000, sram_base
+ 4);
13521 writel(0xffffffff, sram_base
+ 4);
13522 if (readl(sram_base
) != 0x00000000)
13523 tp
->tg3_flags
|= TG3_FLAG_PCIX_TARGET_HWBUG
;
13528 tg3_nvram_init(tp
);
13530 grc_misc_cfg
= tr32(GRC_MISC_CFG
);
13531 grc_misc_cfg
&= GRC_MISC_CFG_BOARD_ID_MASK
;
13533 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
13534 (grc_misc_cfg
== GRC_MISC_CFG_BOARD_ID_5788
||
13535 grc_misc_cfg
== GRC_MISC_CFG_BOARD_ID_5788M
))
13536 tp
->tg3_flags2
|= TG3_FLG2_IS_5788
;
13538 if (!(tp
->tg3_flags2
& TG3_FLG2_IS_5788
) &&
13539 (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
))
13540 tp
->tg3_flags
|= TG3_FLAG_TAGGED_STATUS
;
13541 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) {
13542 tp
->coalesce_mode
|= (HOSTCC_MODE_CLRTICK_RXBD
|
13543 HOSTCC_MODE_CLRTICK_TXBD
);
13545 tp
->misc_host_ctrl
|= MISC_HOST_CTRL_TAGGED_STATUS
;
13546 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
13547 tp
->misc_host_ctrl
);
13550 /* Preserve the APE MAC_MODE bits */
13551 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
13552 tp
->mac_mode
= tr32(MAC_MODE
) |
13553 MAC_MODE_APE_TX_EN
| MAC_MODE_APE_RX_EN
;
13555 tp
->mac_mode
= TG3_DEF_MAC_MODE
;
13557 /* these are limited to 10/100 only */
13558 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
&&
13559 (grc_misc_cfg
== 0x8000 || grc_misc_cfg
== 0x4000)) ||
13560 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
13561 tp
->pdev
->vendor
== PCI_VENDOR_ID_BROADCOM
&&
13562 (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5901
||
13563 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5901_2
||
13564 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5705F
)) ||
13565 (tp
->pdev
->vendor
== PCI_VENDOR_ID_BROADCOM
&&
13566 (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5751F
||
13567 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5753F
||
13568 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5787F
)) ||
13569 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57790
||
13570 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57791
||
13571 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57795
||
13572 (tp
->phy_flags
& TG3_PHYFLG_IS_FET
))
13573 tp
->phy_flags
|= TG3_PHYFLG_10_100_ONLY
;
13575 err
= tg3_phy_probe(tp
);
13577 dev_err(&tp
->pdev
->dev
, "phy probe failed, err %d\n", err
);
13578 /* ... but do not return immediately ... */
13583 tg3_read_fw_ver(tp
);
13585 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) {
13586 tp
->phy_flags
&= ~TG3_PHYFLG_USE_MI_INTERRUPT
;
13588 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
)
13589 tp
->phy_flags
|= TG3_PHYFLG_USE_MI_INTERRUPT
;
13591 tp
->phy_flags
&= ~TG3_PHYFLG_USE_MI_INTERRUPT
;
13594 /* 5700 {AX,BX} chips have a broken status block link
13595 * change bit implementation, so we must use the
13596 * status register in those cases.
13598 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
)
13599 tp
->tg3_flags
|= TG3_FLAG_USE_LINKCHG_REG
;
13601 tp
->tg3_flags
&= ~TG3_FLAG_USE_LINKCHG_REG
;
13603 /* The led_ctrl is set during tg3_phy_probe, here we might
13604 * have to force the link status polling mechanism based
13605 * upon subsystem IDs.
13607 if (tp
->pdev
->subsystem_vendor
== PCI_VENDOR_ID_DELL
&&
13608 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
&&
13609 !(tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
)) {
13610 tp
->phy_flags
|= TG3_PHYFLG_USE_MI_INTERRUPT
;
13611 tp
->tg3_flags
|= TG3_FLAG_USE_LINKCHG_REG
;
13614 /* For all SERDES we poll the MAC status register. */
13615 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
)
13616 tp
->tg3_flags
|= TG3_FLAG_POLL_SERDES
;
13618 tp
->tg3_flags
&= ~TG3_FLAG_POLL_SERDES
;
13620 tp
->rx_offset
= NET_IP_ALIGN
+ TG3_RX_HEADROOM
;
13621 tp
->rx_copy_thresh
= TG3_RX_COPY_THRESHOLD
;
13622 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
&&
13623 (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) != 0) {
13624 tp
->rx_offset
-= NET_IP_ALIGN
;
13625 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
13626 tp
->rx_copy_thresh
= ~(u16
)0;
13630 tp
->rx_std_ring_mask
= TG3_RX_STD_RING_SIZE(tp
) - 1;
13631 tp
->rx_jmb_ring_mask
= TG3_RX_JMB_RING_SIZE(tp
) - 1;
13632 tp
->rx_ret_ring_mask
= tg3_rx_ret_ring_size(tp
) - 1;
13634 tp
->rx_std_max_post
= tp
->rx_std_ring_mask
+ 1;
13636 /* Increment the rx prod index on the rx std ring by at most
13637 * 8 for these chips to workaround hw errata.
13639 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
||
13640 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
||
13641 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
)
13642 tp
->rx_std_max_post
= 8;
13644 if (tp
->tg3_flags
& TG3_FLAG_ASPM_WORKAROUND
)
13645 tp
->pwrmgmt_thresh
= tr32(PCIE_PWR_MGMT_THRESH
) &
13646 PCIE_PWR_MGMT_L1_THRESH_MSK
;
13651 #ifdef CONFIG_SPARC
13652 static int __devinit
tg3_get_macaddr_sparc(struct tg3
*tp
)
13654 struct net_device
*dev
= tp
->dev
;
13655 struct pci_dev
*pdev
= tp
->pdev
;
13656 struct device_node
*dp
= pci_device_to_OF_node(pdev
);
13657 const unsigned char *addr
;
13660 addr
= of_get_property(dp
, "local-mac-address", &len
);
13661 if (addr
&& len
== 6) {
13662 memcpy(dev
->dev_addr
, addr
, 6);
13663 memcpy(dev
->perm_addr
, dev
->dev_addr
, 6);
13669 static int __devinit
tg3_get_default_macaddr_sparc(struct tg3
*tp
)
13671 struct net_device
*dev
= tp
->dev
;
13673 memcpy(dev
->dev_addr
, idprom
->id_ethaddr
, 6);
13674 memcpy(dev
->perm_addr
, idprom
->id_ethaddr
, 6);
13679 static int __devinit
tg3_get_device_address(struct tg3
*tp
)
13681 struct net_device
*dev
= tp
->dev
;
13682 u32 hi
, lo
, mac_offset
;
13685 #ifdef CONFIG_SPARC
13686 if (!tg3_get_macaddr_sparc(tp
))
13691 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) ||
13692 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
13693 if (tr32(TG3PCI_DUAL_MAC_CTRL
) & DUAL_MAC_CTRL_ID
)
13695 if (tg3_nvram_lock(tp
))
13696 tw32_f(NVRAM_CMD
, NVRAM_CMD_RESET
);
13698 tg3_nvram_unlock(tp
);
13699 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
13700 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5719
) {
13701 if (PCI_FUNC(tp
->pdev
->devfn
) & 1)
13703 if (PCI_FUNC(tp
->pdev
->devfn
) > 1)
13704 mac_offset
+= 0x18c;
13705 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
13708 /* First try to get it from MAC address mailbox. */
13709 tg3_read_mem(tp
, NIC_SRAM_MAC_ADDR_HIGH_MBOX
, &hi
);
13710 if ((hi
>> 16) == 0x484b) {
13711 dev
->dev_addr
[0] = (hi
>> 8) & 0xff;
13712 dev
->dev_addr
[1] = (hi
>> 0) & 0xff;
13714 tg3_read_mem(tp
, NIC_SRAM_MAC_ADDR_LOW_MBOX
, &lo
);
13715 dev
->dev_addr
[2] = (lo
>> 24) & 0xff;
13716 dev
->dev_addr
[3] = (lo
>> 16) & 0xff;
13717 dev
->dev_addr
[4] = (lo
>> 8) & 0xff;
13718 dev
->dev_addr
[5] = (lo
>> 0) & 0xff;
13720 /* Some old bootcode may report a 0 MAC address in SRAM */
13721 addr_ok
= is_valid_ether_addr(&dev
->dev_addr
[0]);
13724 /* Next, try NVRAM. */
13725 if (!(tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) &&
13726 !tg3_nvram_read_be32(tp
, mac_offset
+ 0, &hi
) &&
13727 !tg3_nvram_read_be32(tp
, mac_offset
+ 4, &lo
)) {
13728 memcpy(&dev
->dev_addr
[0], ((char *)&hi
) + 2, 2);
13729 memcpy(&dev
->dev_addr
[2], (char *)&lo
, sizeof(lo
));
13731 /* Finally just fetch it out of the MAC control regs. */
13733 hi
= tr32(MAC_ADDR_0_HIGH
);
13734 lo
= tr32(MAC_ADDR_0_LOW
);
13736 dev
->dev_addr
[5] = lo
& 0xff;
13737 dev
->dev_addr
[4] = (lo
>> 8) & 0xff;
13738 dev
->dev_addr
[3] = (lo
>> 16) & 0xff;
13739 dev
->dev_addr
[2] = (lo
>> 24) & 0xff;
13740 dev
->dev_addr
[1] = hi
& 0xff;
13741 dev
->dev_addr
[0] = (hi
>> 8) & 0xff;
13745 if (!is_valid_ether_addr(&dev
->dev_addr
[0])) {
13746 #ifdef CONFIG_SPARC
13747 if (!tg3_get_default_macaddr_sparc(tp
))
13752 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
13756 #define BOUNDARY_SINGLE_CACHELINE 1
13757 #define BOUNDARY_MULTI_CACHELINE 2
13759 static u32 __devinit
tg3_calc_dma_bndry(struct tg3
*tp
, u32 val
)
13761 int cacheline_size
;
13765 pci_read_config_byte(tp
->pdev
, PCI_CACHE_LINE_SIZE
, &byte
);
13767 cacheline_size
= 1024;
13769 cacheline_size
= (int) byte
* 4;
13771 /* On 5703 and later chips, the boundary bits have no
13774 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
13775 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
&&
13776 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
))
13779 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13780 goal
= BOUNDARY_MULTI_CACHELINE
;
13782 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13783 goal
= BOUNDARY_SINGLE_CACHELINE
;
13789 if (tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
) {
13790 val
= goal
? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT
;
13797 /* PCI controllers on most RISC systems tend to disconnect
13798 * when a device tries to burst across a cache-line boundary.
13799 * Therefore, letting tg3 do so just wastes PCI bandwidth.
13801 * Unfortunately, for PCI-E there are only limited
13802 * write-side controls for this, and thus for reads
13803 * we will still get the disconnects. We'll also waste
13804 * these PCI cycles for both read and write for chips
13805 * other than 5700 and 5701 which do not implement the
13808 if ((tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) &&
13809 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)) {
13810 switch (cacheline_size
) {
13815 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
13816 val
|= (DMA_RWCTRL_READ_BNDRY_128_PCIX
|
13817 DMA_RWCTRL_WRITE_BNDRY_128_PCIX
);
13819 val
|= (DMA_RWCTRL_READ_BNDRY_384_PCIX
|
13820 DMA_RWCTRL_WRITE_BNDRY_384_PCIX
);
13825 val
|= (DMA_RWCTRL_READ_BNDRY_256_PCIX
|
13826 DMA_RWCTRL_WRITE_BNDRY_256_PCIX
);
13830 val
|= (DMA_RWCTRL_READ_BNDRY_384_PCIX
|
13831 DMA_RWCTRL_WRITE_BNDRY_384_PCIX
);
13834 } else if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
13835 switch (cacheline_size
) {
13839 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
13840 val
&= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE
;
13841 val
|= DMA_RWCTRL_WRITE_BNDRY_64_PCIE
;
13847 val
&= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE
;
13848 val
|= DMA_RWCTRL_WRITE_BNDRY_128_PCIE
;
13852 switch (cacheline_size
) {
13854 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
13855 val
|= (DMA_RWCTRL_READ_BNDRY_16
|
13856 DMA_RWCTRL_WRITE_BNDRY_16
);
13861 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
13862 val
|= (DMA_RWCTRL_READ_BNDRY_32
|
13863 DMA_RWCTRL_WRITE_BNDRY_32
);
13868 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
13869 val
|= (DMA_RWCTRL_READ_BNDRY_64
|
13870 DMA_RWCTRL_WRITE_BNDRY_64
);
13875 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
13876 val
|= (DMA_RWCTRL_READ_BNDRY_128
|
13877 DMA_RWCTRL_WRITE_BNDRY_128
);
13882 val
|= (DMA_RWCTRL_READ_BNDRY_256
|
13883 DMA_RWCTRL_WRITE_BNDRY_256
);
13886 val
|= (DMA_RWCTRL_READ_BNDRY_512
|
13887 DMA_RWCTRL_WRITE_BNDRY_512
);
13891 val
|= (DMA_RWCTRL_READ_BNDRY_1024
|
13892 DMA_RWCTRL_WRITE_BNDRY_1024
);
13901 static int __devinit
tg3_do_test_dma(struct tg3
*tp
, u32
*buf
, dma_addr_t buf_dma
, int size
, int to_device
)
13903 struct tg3_internal_buffer_desc test_desc
;
13904 u32 sram_dma_descs
;
13907 sram_dma_descs
= NIC_SRAM_DMA_DESC_POOL_BASE
;
13909 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ
, 0);
13910 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ
, 0);
13911 tw32(RDMAC_STATUS
, 0);
13912 tw32(WDMAC_STATUS
, 0);
13914 tw32(BUFMGR_MODE
, 0);
13915 tw32(FTQ_RESET
, 0);
13917 test_desc
.addr_hi
= ((u64
) buf_dma
) >> 32;
13918 test_desc
.addr_lo
= buf_dma
& 0xffffffff;
13919 test_desc
.nic_mbuf
= 0x00002100;
13920 test_desc
.len
= size
;
13923 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13924 * the *second* time the tg3 driver was getting loaded after an
13927 * Broadcom tells me:
13928 * ...the DMA engine is connected to the GRC block and a DMA
13929 * reset may affect the GRC block in some unpredictable way...
13930 * The behavior of resets to individual blocks has not been tested.
13932 * Broadcom noted the GRC reset will also reset all sub-components.
13935 test_desc
.cqid_sqid
= (13 << 8) | 2;
13937 tw32_f(RDMAC_MODE
, RDMAC_MODE_ENABLE
);
13940 test_desc
.cqid_sqid
= (16 << 8) | 7;
13942 tw32_f(WDMAC_MODE
, WDMAC_MODE_ENABLE
);
13945 test_desc
.flags
= 0x00000005;
13947 for (i
= 0; i
< (sizeof(test_desc
) / sizeof(u32
)); i
++) {
13950 val
= *(((u32
*)&test_desc
) + i
);
13951 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
,
13952 sram_dma_descs
+ (i
* sizeof(u32
)));
13953 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_DATA
, val
);
13955 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, 0);
13958 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ
, sram_dma_descs
);
13960 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ
, sram_dma_descs
);
13963 for (i
= 0; i
< 40; i
++) {
13967 val
= tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ
);
13969 val
= tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ
);
13970 if ((val
& 0xffff) == sram_dma_descs
) {
13981 #define TEST_BUFFER_SIZE 0x2000
13983 static int __devinit
tg3_test_dma(struct tg3
*tp
)
13985 dma_addr_t buf_dma
;
13986 u32
*buf
, saved_dma_rwctrl
;
13989 buf
= pci_alloc_consistent(tp
->pdev
, TEST_BUFFER_SIZE
, &buf_dma
);
13995 tp
->dma_rwctrl
= ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT
) |
13996 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT
));
13998 tp
->dma_rwctrl
= tg3_calc_dma_bndry(tp
, tp
->dma_rwctrl
);
14000 if (tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
)
14003 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
14004 /* DMA read watermark not used on PCIE */
14005 tp
->dma_rwctrl
|= 0x00180000;
14006 } else if (!(tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
)) {
14007 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
||
14008 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
)
14009 tp
->dma_rwctrl
|= 0x003f0000;
14011 tp
->dma_rwctrl
|= 0x003f000f;
14013 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
14014 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
14015 u32 ccval
= (tr32(TG3PCI_CLOCK_CTRL
) & 0x1f);
14016 u32 read_water
= 0x7;
14018 /* If the 5704 is behind the EPB bridge, we can
14019 * do the less restrictive ONE_DMA workaround for
14020 * better performance.
14022 if ((tp
->tg3_flags
& TG3_FLAG_40BIT_DMA_BUG
) &&
14023 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
)
14024 tp
->dma_rwctrl
|= 0x8000;
14025 else if (ccval
== 0x6 || ccval
== 0x7)
14026 tp
->dma_rwctrl
|= DMA_RWCTRL_ONE_DMA
;
14028 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
)
14030 /* Set bit 23 to enable PCIX hw bug fix */
14032 (read_water
<< DMA_RWCTRL_READ_WATER_SHIFT
) |
14033 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT
) |
14035 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5780
) {
14036 /* 5780 always in PCIX mode */
14037 tp
->dma_rwctrl
|= 0x00144000;
14038 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
) {
14039 /* 5714 always in PCIX mode */
14040 tp
->dma_rwctrl
|= 0x00148000;
14042 tp
->dma_rwctrl
|= 0x001b000f;
14046 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
14047 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
)
14048 tp
->dma_rwctrl
&= 0xfffffff0;
14050 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
14051 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
14052 /* Remove this if it causes problems for some boards. */
14053 tp
->dma_rwctrl
|= DMA_RWCTRL_USE_MEM_READ_MULT
;
14055 /* On 5700/5701 chips, we need to set this bit.
14056 * Otherwise the chip will issue cacheline transactions
14057 * to streamable DMA memory with not all the byte
14058 * enables turned on. This is an error on several
14059 * RISC PCI controllers, in particular sparc64.
14061 * On 5703/5704 chips, this bit has been reassigned
14062 * a different meaning. In particular, it is used
14063 * on those chips to enable a PCI-X workaround.
14065 tp
->dma_rwctrl
|= DMA_RWCTRL_ASSERT_ALL_BE
;
14068 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
14071 /* Unneeded, already done by tg3_get_invariants. */
14072 tg3_switch_clocks(tp
);
14075 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
14076 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
)
14079 /* It is best to perform DMA test with maximum write burst size
14080 * to expose the 5700/5701 write DMA bug.
14082 saved_dma_rwctrl
= tp
->dma_rwctrl
;
14083 tp
->dma_rwctrl
&= ~DMA_RWCTRL_WRITE_BNDRY_MASK
;
14084 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
14089 for (i
= 0; i
< TEST_BUFFER_SIZE
/ sizeof(u32
); i
++)
14092 /* Send the buffer to the chip. */
14093 ret
= tg3_do_test_dma(tp
, buf
, buf_dma
, TEST_BUFFER_SIZE
, 1);
14095 dev_err(&tp
->pdev
->dev
,
14096 "%s: Buffer write failed. err = %d\n",
14102 /* validate data reached card RAM correctly. */
14103 for (i
= 0; i
< TEST_BUFFER_SIZE
/ sizeof(u32
); i
++) {
14105 tg3_read_mem(tp
, 0x2100 + (i
*4), &val
);
14106 if (le32_to_cpu(val
) != p
[i
]) {
14107 dev_err(&tp
->pdev
->dev
,
14108 "%s: Buffer corrupted on device! "
14109 "(%d != %d)\n", __func__
, val
, i
);
14110 /* ret = -ENODEV here? */
14115 /* Now read it back. */
14116 ret
= tg3_do_test_dma(tp
, buf
, buf_dma
, TEST_BUFFER_SIZE
, 0);
14118 dev_err(&tp
->pdev
->dev
, "%s: Buffer read failed. "
14119 "err = %d\n", __func__
, ret
);
14124 for (i
= 0; i
< TEST_BUFFER_SIZE
/ sizeof(u32
); i
++) {
14128 if ((tp
->dma_rwctrl
& DMA_RWCTRL_WRITE_BNDRY_MASK
) !=
14129 DMA_RWCTRL_WRITE_BNDRY_16
) {
14130 tp
->dma_rwctrl
&= ~DMA_RWCTRL_WRITE_BNDRY_MASK
;
14131 tp
->dma_rwctrl
|= DMA_RWCTRL_WRITE_BNDRY_16
;
14132 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
14135 dev_err(&tp
->pdev
->dev
,
14136 "%s: Buffer corrupted on read back! "
14137 "(%d != %d)\n", __func__
, p
[i
], i
);
14143 if (i
== (TEST_BUFFER_SIZE
/ sizeof(u32
))) {
14149 if ((tp
->dma_rwctrl
& DMA_RWCTRL_WRITE_BNDRY_MASK
) !=
14150 DMA_RWCTRL_WRITE_BNDRY_16
) {
14151 static struct pci_device_id dma_wait_state_chipsets
[] = {
14152 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
,
14153 PCI_DEVICE_ID_APPLE_UNI_N_PCI15
) },
14157 /* DMA test passed without adjusting DMA boundary,
14158 * now look for chipsets that are known to expose the
14159 * DMA bug without failing the test.
14161 if (pci_dev_present(dma_wait_state_chipsets
)) {
14162 tp
->dma_rwctrl
&= ~DMA_RWCTRL_WRITE_BNDRY_MASK
;
14163 tp
->dma_rwctrl
|= DMA_RWCTRL_WRITE_BNDRY_16
;
14165 /* Safe to use the calculated DMA boundary. */
14166 tp
->dma_rwctrl
= saved_dma_rwctrl
;
14169 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
14173 pci_free_consistent(tp
->pdev
, TEST_BUFFER_SIZE
, buf
, buf_dma
);
14178 static void __devinit
tg3_init_link_config(struct tg3
*tp
)
14180 tp
->link_config
.advertising
=
14181 (ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
14182 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
|
14183 ADVERTISED_1000baseT_Half
| ADVERTISED_1000baseT_Full
|
14184 ADVERTISED_Autoneg
| ADVERTISED_MII
);
14185 tp
->link_config
.speed
= SPEED_INVALID
;
14186 tp
->link_config
.duplex
= DUPLEX_INVALID
;
14187 tp
->link_config
.autoneg
= AUTONEG_ENABLE
;
14188 tp
->link_config
.active_speed
= SPEED_INVALID
;
14189 tp
->link_config
.active_duplex
= DUPLEX_INVALID
;
14190 tp
->link_config
.orig_speed
= SPEED_INVALID
;
14191 tp
->link_config
.orig_duplex
= DUPLEX_INVALID
;
14192 tp
->link_config
.orig_autoneg
= AUTONEG_INVALID
;
14195 static void __devinit
tg3_init_bufmgr_config(struct tg3
*tp
)
14197 if (tp
->tg3_flags3
& TG3_FLG3_5717_PLUS
) {
14198 tp
->bufmgr_config
.mbuf_read_dma_low_water
=
14199 DEFAULT_MB_RDMA_LOW_WATER_5705
;
14200 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
14201 DEFAULT_MB_MACRX_LOW_WATER_57765
;
14202 tp
->bufmgr_config
.mbuf_high_water
=
14203 DEFAULT_MB_HIGH_WATER_57765
;
14205 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
=
14206 DEFAULT_MB_RDMA_LOW_WATER_5705
;
14207 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
=
14208 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765
;
14209 tp
->bufmgr_config
.mbuf_high_water_jumbo
=
14210 DEFAULT_MB_HIGH_WATER_JUMBO_57765
;
14211 } else if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
14212 tp
->bufmgr_config
.mbuf_read_dma_low_water
=
14213 DEFAULT_MB_RDMA_LOW_WATER_5705
;
14214 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
14215 DEFAULT_MB_MACRX_LOW_WATER_5705
;
14216 tp
->bufmgr_config
.mbuf_high_water
=
14217 DEFAULT_MB_HIGH_WATER_5705
;
14218 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
14219 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
14220 DEFAULT_MB_MACRX_LOW_WATER_5906
;
14221 tp
->bufmgr_config
.mbuf_high_water
=
14222 DEFAULT_MB_HIGH_WATER_5906
;
14225 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
=
14226 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780
;
14227 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
=
14228 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780
;
14229 tp
->bufmgr_config
.mbuf_high_water_jumbo
=
14230 DEFAULT_MB_HIGH_WATER_JUMBO_5780
;
14232 tp
->bufmgr_config
.mbuf_read_dma_low_water
=
14233 DEFAULT_MB_RDMA_LOW_WATER
;
14234 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
14235 DEFAULT_MB_MACRX_LOW_WATER
;
14236 tp
->bufmgr_config
.mbuf_high_water
=
14237 DEFAULT_MB_HIGH_WATER
;
14239 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
=
14240 DEFAULT_MB_RDMA_LOW_WATER_JUMBO
;
14241 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
=
14242 DEFAULT_MB_MACRX_LOW_WATER_JUMBO
;
14243 tp
->bufmgr_config
.mbuf_high_water_jumbo
=
14244 DEFAULT_MB_HIGH_WATER_JUMBO
;
14247 tp
->bufmgr_config
.dma_low_water
= DEFAULT_DMA_LOW_WATER
;
14248 tp
->bufmgr_config
.dma_high_water
= DEFAULT_DMA_HIGH_WATER
;
14251 static char * __devinit
tg3_phy_string(struct tg3
*tp
)
14253 switch (tp
->phy_id
& TG3_PHY_ID_MASK
) {
14254 case TG3_PHY_ID_BCM5400
: return "5400";
14255 case TG3_PHY_ID_BCM5401
: return "5401";
14256 case TG3_PHY_ID_BCM5411
: return "5411";
14257 case TG3_PHY_ID_BCM5701
: return "5701";
14258 case TG3_PHY_ID_BCM5703
: return "5703";
14259 case TG3_PHY_ID_BCM5704
: return "5704";
14260 case TG3_PHY_ID_BCM5705
: return "5705";
14261 case TG3_PHY_ID_BCM5750
: return "5750";
14262 case TG3_PHY_ID_BCM5752
: return "5752";
14263 case TG3_PHY_ID_BCM5714
: return "5714";
14264 case TG3_PHY_ID_BCM5780
: return "5780";
14265 case TG3_PHY_ID_BCM5755
: return "5755";
14266 case TG3_PHY_ID_BCM5787
: return "5787";
14267 case TG3_PHY_ID_BCM5784
: return "5784";
14268 case TG3_PHY_ID_BCM5756
: return "5722/5756";
14269 case TG3_PHY_ID_BCM5906
: return "5906";
14270 case TG3_PHY_ID_BCM5761
: return "5761";
14271 case TG3_PHY_ID_BCM5718C
: return "5718C";
14272 case TG3_PHY_ID_BCM5718S
: return "5718S";
14273 case TG3_PHY_ID_BCM57765
: return "57765";
14274 case TG3_PHY_ID_BCM5719C
: return "5719C";
14275 case TG3_PHY_ID_BCM8002
: return "8002/serdes";
14276 case 0: return "serdes";
14277 default: return "unknown";
14281 static char * __devinit
tg3_bus_string(struct tg3
*tp
, char *str
)
14283 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
14284 strcpy(str
, "PCI Express");
14286 } else if (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) {
14287 u32 clock_ctrl
= tr32(TG3PCI_CLOCK_CTRL
) & 0x1f;
14289 strcpy(str
, "PCIX:");
14291 if ((clock_ctrl
== 7) ||
14292 ((tr32(GRC_MISC_CFG
) & GRC_MISC_CFG_BOARD_ID_MASK
) ==
14293 GRC_MISC_CFG_BOARD_ID_5704CIOBE
))
14294 strcat(str
, "133MHz");
14295 else if (clock_ctrl
== 0)
14296 strcat(str
, "33MHz");
14297 else if (clock_ctrl
== 2)
14298 strcat(str
, "50MHz");
14299 else if (clock_ctrl
== 4)
14300 strcat(str
, "66MHz");
14301 else if (clock_ctrl
== 6)
14302 strcat(str
, "100MHz");
14304 strcpy(str
, "PCI:");
14305 if (tp
->tg3_flags
& TG3_FLAG_PCI_HIGH_SPEED
)
14306 strcat(str
, "66MHz");
14308 strcat(str
, "33MHz");
14310 if (tp
->tg3_flags
& TG3_FLAG_PCI_32BIT
)
14311 strcat(str
, ":32-bit");
14313 strcat(str
, ":64-bit");
14317 static struct pci_dev
* __devinit
tg3_find_peer(struct tg3
*tp
)
14319 struct pci_dev
*peer
;
14320 unsigned int func
, devnr
= tp
->pdev
->devfn
& ~7;
14322 for (func
= 0; func
< 8; func
++) {
14323 peer
= pci_get_slot(tp
->pdev
->bus
, devnr
| func
);
14324 if (peer
&& peer
!= tp
->pdev
)
14328 /* 5704 can be configured in single-port mode, set peer to
14329 * tp->pdev in that case.
14337 * We don't need to keep the refcount elevated; there's no way
14338 * to remove one half of this device without removing the other
14345 static void __devinit
tg3_init_coal(struct tg3
*tp
)
14347 struct ethtool_coalesce
*ec
= &tp
->coal
;
14349 memset(ec
, 0, sizeof(*ec
));
14350 ec
->cmd
= ETHTOOL_GCOALESCE
;
14351 ec
->rx_coalesce_usecs
= LOW_RXCOL_TICKS
;
14352 ec
->tx_coalesce_usecs
= LOW_TXCOL_TICKS
;
14353 ec
->rx_max_coalesced_frames
= LOW_RXMAX_FRAMES
;
14354 ec
->tx_max_coalesced_frames
= LOW_TXMAX_FRAMES
;
14355 ec
->rx_coalesce_usecs_irq
= DEFAULT_RXCOAL_TICK_INT
;
14356 ec
->tx_coalesce_usecs_irq
= DEFAULT_TXCOAL_TICK_INT
;
14357 ec
->rx_max_coalesced_frames_irq
= DEFAULT_RXCOAL_MAXF_INT
;
14358 ec
->tx_max_coalesced_frames_irq
= DEFAULT_TXCOAL_MAXF_INT
;
14359 ec
->stats_block_coalesce_usecs
= DEFAULT_STAT_COAL_TICKS
;
14361 if (tp
->coalesce_mode
& (HOSTCC_MODE_CLRTICK_RXBD
|
14362 HOSTCC_MODE_CLRTICK_TXBD
)) {
14363 ec
->rx_coalesce_usecs
= LOW_RXCOL_TICKS_CLRTCKS
;
14364 ec
->rx_coalesce_usecs_irq
= DEFAULT_RXCOAL_TICK_INT_CLRTCKS
;
14365 ec
->tx_coalesce_usecs
= LOW_TXCOL_TICKS_CLRTCKS
;
14366 ec
->tx_coalesce_usecs_irq
= DEFAULT_TXCOAL_TICK_INT_CLRTCKS
;
14369 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
14370 ec
->rx_coalesce_usecs_irq
= 0;
14371 ec
->tx_coalesce_usecs_irq
= 0;
14372 ec
->stats_block_coalesce_usecs
= 0;
14376 static const struct net_device_ops tg3_netdev_ops
= {
14377 .ndo_open
= tg3_open
,
14378 .ndo_stop
= tg3_close
,
14379 .ndo_start_xmit
= tg3_start_xmit
,
14380 .ndo_get_stats64
= tg3_get_stats64
,
14381 .ndo_validate_addr
= eth_validate_addr
,
14382 .ndo_set_multicast_list
= tg3_set_rx_mode
,
14383 .ndo_set_mac_address
= tg3_set_mac_addr
,
14384 .ndo_do_ioctl
= tg3_ioctl
,
14385 .ndo_tx_timeout
= tg3_tx_timeout
,
14386 .ndo_change_mtu
= tg3_change_mtu
,
14387 #if TG3_VLAN_TAG_USED
14388 .ndo_vlan_rx_register
= tg3_vlan_rx_register
,
14390 #ifdef CONFIG_NET_POLL_CONTROLLER
14391 .ndo_poll_controller
= tg3_poll_controller
,
14395 static const struct net_device_ops tg3_netdev_ops_dma_bug
= {
14396 .ndo_open
= tg3_open
,
14397 .ndo_stop
= tg3_close
,
14398 .ndo_start_xmit
= tg3_start_xmit_dma_bug
,
14399 .ndo_get_stats64
= tg3_get_stats64
,
14400 .ndo_validate_addr
= eth_validate_addr
,
14401 .ndo_set_multicast_list
= tg3_set_rx_mode
,
14402 .ndo_set_mac_address
= tg3_set_mac_addr
,
14403 .ndo_do_ioctl
= tg3_ioctl
,
14404 .ndo_tx_timeout
= tg3_tx_timeout
,
14405 .ndo_change_mtu
= tg3_change_mtu
,
14406 #if TG3_VLAN_TAG_USED
14407 .ndo_vlan_rx_register
= tg3_vlan_rx_register
,
14409 #ifdef CONFIG_NET_POLL_CONTROLLER
14410 .ndo_poll_controller
= tg3_poll_controller
,
14414 static int __devinit
tg3_init_one(struct pci_dev
*pdev
,
14415 const struct pci_device_id
*ent
)
14417 struct net_device
*dev
;
14419 int i
, err
, pm_cap
;
14420 u32 sndmbx
, rcvmbx
, intmbx
;
14422 u64 dma_mask
, persist_dma_mask
;
14424 printk_once(KERN_INFO
"%s\n", version
);
14426 err
= pci_enable_device(pdev
);
14428 dev_err(&pdev
->dev
, "Cannot enable PCI device, aborting\n");
14432 err
= pci_request_regions(pdev
, DRV_MODULE_NAME
);
14434 dev_err(&pdev
->dev
, "Cannot obtain PCI resources, aborting\n");
14435 goto err_out_disable_pdev
;
14438 pci_set_master(pdev
);
14440 /* Find power-management capability. */
14441 pm_cap
= pci_find_capability(pdev
, PCI_CAP_ID_PM
);
14443 dev_err(&pdev
->dev
,
14444 "Cannot find Power Management capability, aborting\n");
14446 goto err_out_free_res
;
14449 dev
= alloc_etherdev_mq(sizeof(*tp
), TG3_IRQ_MAX_VECS
);
14451 dev_err(&pdev
->dev
, "Etherdev alloc failed, aborting\n");
14453 goto err_out_free_res
;
14456 SET_NETDEV_DEV(dev
, &pdev
->dev
);
14458 #if TG3_VLAN_TAG_USED
14459 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
14462 tp
= netdev_priv(dev
);
14465 tp
->pm_cap
= pm_cap
;
14466 tp
->rx_mode
= TG3_DEF_RX_MODE
;
14467 tp
->tx_mode
= TG3_DEF_TX_MODE
;
14470 tp
->msg_enable
= tg3_debug
;
14472 tp
->msg_enable
= TG3_DEF_MSG_ENABLE
;
14474 /* The word/byte swap controls here control register access byte
14475 * swapping. DMA data byte swapping is controlled in the GRC_MODE
14478 tp
->misc_host_ctrl
=
14479 MISC_HOST_CTRL_MASK_PCI_INT
|
14480 MISC_HOST_CTRL_WORD_SWAP
|
14481 MISC_HOST_CTRL_INDIR_ACCESS
|
14482 MISC_HOST_CTRL_PCISTATE_RW
;
14484 /* The NONFRM (non-frame) byte/word swap controls take effect
14485 * on descriptor entries, anything which isn't packet data.
14487 * The StrongARM chips on the board (one for tx, one for rx)
14488 * are running in big-endian mode.
14490 tp
->grc_mode
= (GRC_MODE_WSWAP_DATA
| GRC_MODE_BSWAP_DATA
|
14491 GRC_MODE_WSWAP_NONFRM_DATA
);
14492 #ifdef __BIG_ENDIAN
14493 tp
->grc_mode
|= GRC_MODE_BSWAP_NONFRM_DATA
;
14495 spin_lock_init(&tp
->lock
);
14496 spin_lock_init(&tp
->indirect_lock
);
14497 INIT_WORK(&tp
->reset_task
, tg3_reset_task
);
14499 tp
->regs
= pci_ioremap_bar(pdev
, BAR_0
);
14501 dev_err(&pdev
->dev
, "Cannot map device registers, aborting\n");
14503 goto err_out_free_dev
;
14506 tg3_init_link_config(tp
);
14508 tp
->rx_pending
= TG3_DEF_RX_RING_PENDING
;
14509 tp
->rx_jumbo_pending
= TG3_DEF_RX_JUMBO_RING_PENDING
;
14511 dev
->ethtool_ops
= &tg3_ethtool_ops
;
14512 dev
->watchdog_timeo
= TG3_TX_TIMEOUT
;
14513 dev
->irq
= pdev
->irq
;
14515 err
= tg3_get_invariants(tp
);
14517 dev_err(&pdev
->dev
,
14518 "Problem fetching invariants of chip, aborting\n");
14519 goto err_out_iounmap
;
14522 if ((tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) &&
14523 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5717
&&
14524 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5719
)
14525 dev
->netdev_ops
= &tg3_netdev_ops
;
14527 dev
->netdev_ops
= &tg3_netdev_ops_dma_bug
;
14530 /* The EPB bridge inside 5714, 5715, and 5780 and any
14531 * device behind the EPB cannot support DMA addresses > 40-bit.
14532 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14533 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14534 * do DMA address check in tg3_start_xmit().
14536 if (tp
->tg3_flags2
& TG3_FLG2_IS_5788
)
14537 persist_dma_mask
= dma_mask
= DMA_BIT_MASK(32);
14538 else if (tp
->tg3_flags
& TG3_FLAG_40BIT_DMA_BUG
) {
14539 persist_dma_mask
= dma_mask
= DMA_BIT_MASK(40);
14540 #ifdef CONFIG_HIGHMEM
14541 dma_mask
= DMA_BIT_MASK(64);
14544 persist_dma_mask
= dma_mask
= DMA_BIT_MASK(64);
14546 /* Configure DMA attributes. */
14547 if (dma_mask
> DMA_BIT_MASK(32)) {
14548 err
= pci_set_dma_mask(pdev
, dma_mask
);
14550 dev
->features
|= NETIF_F_HIGHDMA
;
14551 err
= pci_set_consistent_dma_mask(pdev
,
14554 dev_err(&pdev
->dev
, "Unable to obtain 64 bit "
14555 "DMA for consistent allocations\n");
14556 goto err_out_iounmap
;
14560 if (err
|| dma_mask
== DMA_BIT_MASK(32)) {
14561 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
14563 dev_err(&pdev
->dev
,
14564 "No usable DMA configuration, aborting\n");
14565 goto err_out_iounmap
;
14569 tg3_init_bufmgr_config(tp
);
14571 /* Selectively allow TSO based on operating conditions */
14572 if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO
) ||
14573 (tp
->fw_needed
&& !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)))
14574 tp
->tg3_flags2
|= TG3_FLG2_TSO_CAPABLE
;
14576 tp
->tg3_flags2
&= ~(TG3_FLG2_TSO_CAPABLE
| TG3_FLG2_TSO_BUG
);
14577 tp
->fw_needed
= NULL
;
14580 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
)
14581 tp
->fw_needed
= FIRMWARE_TG3
;
14583 /* TSO is on by default on chips that support hardware TSO.
14584 * Firmware TSO on older chips gives lower performance, so it
14585 * is off by default, but can be enabled using ethtool.
14587 if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO
) &&
14588 (dev
->features
& NETIF_F_IP_CSUM
)) {
14589 dev
->features
|= NETIF_F_TSO
;
14590 vlan_features_add(dev
, NETIF_F_TSO
);
14592 if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO_2
) ||
14593 (tp
->tg3_flags2
& TG3_FLG2_HW_TSO_3
)) {
14594 if (dev
->features
& NETIF_F_IPV6_CSUM
) {
14595 dev
->features
|= NETIF_F_TSO6
;
14596 vlan_features_add(dev
, NETIF_F_TSO6
);
14598 if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO_3
) ||
14599 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
14600 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
14601 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
) ||
14602 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
14603 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
) {
14604 dev
->features
|= NETIF_F_TSO_ECN
;
14605 vlan_features_add(dev
, NETIF_F_TSO_ECN
);
14609 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A1
&&
14610 !(tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) &&
14611 !(tr32(TG3PCI_PCISTATE
) & PCISTATE_BUS_SPEED_HIGH
)) {
14612 tp
->tg3_flags2
|= TG3_FLG2_MAX_RXPEND_64
;
14613 tp
->rx_pending
= 63;
14616 err
= tg3_get_device_address(tp
);
14618 dev_err(&pdev
->dev
,
14619 "Could not obtain valid ethernet address, aborting\n");
14620 goto err_out_iounmap
;
14623 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
14624 tp
->aperegs
= pci_ioremap_bar(pdev
, BAR_2
);
14625 if (!tp
->aperegs
) {
14626 dev_err(&pdev
->dev
,
14627 "Cannot map APE registers, aborting\n");
14629 goto err_out_iounmap
;
14632 tg3_ape_lock_init(tp
);
14634 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)
14635 tg3_read_dash_ver(tp
);
14639 * Reset chip in case UNDI or EFI driver did not shutdown
14640 * DMA self test will enable WDMAC and we'll see (spurious)
14641 * pending DMA on the PCI bus at that point.
14643 if ((tr32(HOSTCC_MODE
) & HOSTCC_MODE_ENABLE
) ||
14644 (tr32(WDMAC_MODE
) & WDMAC_MODE_ENABLE
)) {
14645 tw32(MEMARB_MODE
, MEMARB_MODE_ENABLE
);
14646 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
14649 err
= tg3_test_dma(tp
);
14651 dev_err(&pdev
->dev
, "DMA engine test failed, aborting\n");
14652 goto err_out_apeunmap
;
14655 /* flow control autonegotiation is default behavior */
14656 tp
->tg3_flags
|= TG3_FLAG_PAUSE_AUTONEG
;
14657 tp
->link_config
.flowctrl
= FLOW_CTRL_TX
| FLOW_CTRL_RX
;
14659 intmbx
= MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
;
14660 rcvmbx
= MAILBOX_RCVRET_CON_IDX_0
+ TG3_64BIT_REG_LOW
;
14661 sndmbx
= MAILBOX_SNDHOST_PROD_IDX_0
+ TG3_64BIT_REG_LOW
;
14662 for (i
= 0; i
< tp
->irq_max
; i
++) {
14663 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
14666 tnapi
->tx_pending
= TG3_DEF_TX_RING_PENDING
;
14668 tnapi
->int_mbox
= intmbx
;
14674 tnapi
->consmbox
= rcvmbx
;
14675 tnapi
->prodmbox
= sndmbx
;
14678 tnapi
->coal_now
= HOSTCC_MODE_COAL_VEC1_NOW
<< (i
- 1);
14680 tnapi
->coal_now
= HOSTCC_MODE_NOW
;
14682 if (!(tp
->tg3_flags
& TG3_FLAG_SUPPORT_MSIX
))
14686 * If we support MSIX, we'll be using RSS. If we're using
14687 * RSS, the first vector only handles link interrupts and the
14688 * remaining vectors handle rx and tx interrupts. Reuse the
14689 * mailbox values for the next iteration. The values we setup
14690 * above are still useful for the single vectored mode.
14705 pci_set_drvdata(pdev
, dev
);
14707 err
= register_netdev(dev
);
14709 dev_err(&pdev
->dev
, "Cannot register net device, aborting\n");
14710 goto err_out_apeunmap
;
14713 netdev_info(dev
, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14714 tp
->board_part_number
,
14715 tp
->pci_chip_rev_id
,
14716 tg3_bus_string(tp
, str
),
14719 if (tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
) {
14720 struct phy_device
*phydev
;
14721 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
14723 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14724 phydev
->drv
->name
, dev_name(&phydev
->dev
));
14728 if (tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
)
14729 ethtype
= "10/100Base-TX";
14730 else if (tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
)
14731 ethtype
= "1000Base-SX";
14733 ethtype
= "10/100/1000Base-T";
14735 netdev_info(dev
, "attached PHY is %s (%s Ethernet) "
14736 "(WireSpeed[%d])\n", tg3_phy_string(tp
), ethtype
,
14737 (tp
->phy_flags
& TG3_PHYFLG_NO_ETH_WIRE_SPEED
) == 0);
14740 netdev_info(dev
, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14741 (tp
->tg3_flags
& TG3_FLAG_RX_CHECKSUMS
) != 0,
14742 (tp
->tg3_flags
& TG3_FLAG_USE_LINKCHG_REG
) != 0,
14743 (tp
->phy_flags
& TG3_PHYFLG_USE_MI_INTERRUPT
) != 0,
14744 (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) != 0,
14745 (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) != 0);
14746 netdev_info(dev
, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14748 pdev
->dma_mask
== DMA_BIT_MASK(32) ? 32 :
14749 ((u64
)pdev
->dma_mask
) == DMA_BIT_MASK(40) ? 40 : 64);
14755 iounmap(tp
->aperegs
);
14756 tp
->aperegs
= NULL
;
14769 pci_release_regions(pdev
);
14771 err_out_disable_pdev
:
14772 pci_disable_device(pdev
);
14773 pci_set_drvdata(pdev
, NULL
);
14777 static void __devexit
tg3_remove_one(struct pci_dev
*pdev
)
14779 struct net_device
*dev
= pci_get_drvdata(pdev
);
14782 struct tg3
*tp
= netdev_priv(dev
);
14785 release_firmware(tp
->fw
);
14787 flush_scheduled_work();
14789 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
14794 unregister_netdev(dev
);
14796 iounmap(tp
->aperegs
);
14797 tp
->aperegs
= NULL
;
14804 pci_release_regions(pdev
);
14805 pci_disable_device(pdev
);
14806 pci_set_drvdata(pdev
, NULL
);
14810 static int tg3_suspend(struct pci_dev
*pdev
, pm_message_t state
)
14812 struct net_device
*dev
= pci_get_drvdata(pdev
);
14813 struct tg3
*tp
= netdev_priv(dev
);
14814 pci_power_t target_state
;
14817 /* PCI register 4 needs to be saved whether netif_running() or not.
14818 * MSI address and data need to be saved if using MSI and
14821 pci_save_state(pdev
);
14823 if (!netif_running(dev
))
14826 flush_scheduled_work();
14828 tg3_netif_stop(tp
);
14830 del_timer_sync(&tp
->timer
);
14832 tg3_full_lock(tp
, 1);
14833 tg3_disable_ints(tp
);
14834 tg3_full_unlock(tp
);
14836 netif_device_detach(dev
);
14838 tg3_full_lock(tp
, 0);
14839 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
14840 tp
->tg3_flags
&= ~TG3_FLAG_INIT_COMPLETE
;
14841 tg3_full_unlock(tp
);
14843 target_state
= pdev
->pm_cap
? pci_target_state(pdev
) : PCI_D3hot
;
14845 err
= tg3_set_power_state(tp
, target_state
);
14849 tg3_full_lock(tp
, 0);
14851 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
14852 err2
= tg3_restart_hw(tp
, 1);
14856 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
14857 add_timer(&tp
->timer
);
14859 netif_device_attach(dev
);
14860 tg3_netif_start(tp
);
14863 tg3_full_unlock(tp
);
14872 static int tg3_resume(struct pci_dev
*pdev
)
14874 struct net_device
*dev
= pci_get_drvdata(pdev
);
14875 struct tg3
*tp
= netdev_priv(dev
);
14878 pci_restore_state(tp
->pdev
);
14880 if (!netif_running(dev
))
14883 err
= tg3_set_power_state(tp
, PCI_D0
);
14887 netif_device_attach(dev
);
14889 tg3_full_lock(tp
, 0);
14891 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
14892 err
= tg3_restart_hw(tp
, 1);
14896 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
14897 add_timer(&tp
->timer
);
14899 tg3_netif_start(tp
);
14902 tg3_full_unlock(tp
);
14910 static struct pci_driver tg3_driver
= {
14911 .name
= DRV_MODULE_NAME
,
14912 .id_table
= tg3_pci_tbl
,
14913 .probe
= tg3_init_one
,
14914 .remove
= __devexit_p(tg3_remove_one
),
14915 .suspend
= tg3_suspend
,
14916 .resume
= tg3_resume
14919 static int __init
tg3_init(void)
14921 return pci_register_driver(&tg3_driver
);
14924 static void __exit
tg3_cleanup(void)
14926 pci_unregister_driver(&tg3_driver
);
14929 module_init(tg3_init
);
14930 module_exit(tg3_cleanup
);