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Merge git://git.infradead.org/mtd-2.6
[deliverable/linux.git] / drivers / net / tulip / dmfe.c
1 /*
2 A Davicom DM9102/DM9102A/DM9102A+DM9801/DM9102A+DM9802 NIC fast
3 ethernet driver for Linux.
4 Copyright (C) 1997 Sten Wang
5
6 This program is free software; you can redistribute it and/or
7 modify it under the terms of the GNU General Public License
8 as published by the Free Software Foundation; either version 2
9 of the License, or (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 DAVICOM Web-Site: www.davicom.com.tw
17
18 Author: Sten Wang, 886-3-5798797-8517, E-mail: sten_wang@davicom.com.tw
19 Maintainer: Tobias Ringstrom <tori@unhappy.mine.nu>
20
21 (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
22
23 Marcelo Tosatti <marcelo@conectiva.com.br> :
24 Made it compile in 2.3 (device to net_device)
25
26 Alan Cox <alan@lxorguk.ukuu.org.uk> :
27 Cleaned up for kernel merge.
28 Removed the back compatibility support
29 Reformatted, fixing spelling etc as I went
30 Removed IRQ 0-15 assumption
31
32 Jeff Garzik <jgarzik@pobox.com> :
33 Updated to use new PCI driver API.
34 Resource usage cleanups.
35 Report driver version to user.
36
37 Tobias Ringstrom <tori@unhappy.mine.nu> :
38 Cleaned up and added SMP safety. Thanks go to Jeff Garzik,
39 Andrew Morton and Frank Davis for the SMP safety fixes.
40
41 Vojtech Pavlik <vojtech@suse.cz> :
42 Cleaned up pointer arithmetics.
43 Fixed a lot of 64bit issues.
44 Cleaned up printk()s a bit.
45 Fixed some obvious big endian problems.
46
47 Tobias Ringstrom <tori@unhappy.mine.nu> :
48 Use time_after for jiffies calculation. Added ethtool
49 support. Updated PCI resource allocation. Do not
50 forget to unmap PCI mapped skbs.
51
52 Alan Cox <alan@lxorguk.ukuu.org.uk>
53 Added new PCI identifiers provided by Clear Zhang at ALi
54 for their 1563 ethernet device.
55
56 TODO
57
58 Check on 64 bit boxes.
59 Check and fix on big endian boxes.
60
61 Test and make sure PCI latency is now correct for all cases.
62 */
63
64 #define DRV_NAME "dmfe"
65 #define DRV_VERSION "1.36.4"
66 #define DRV_RELDATE "2002-01-17"
67
68 #include <linux/module.h>
69 #include <linux/kernel.h>
70 #include <linux/string.h>
71 #include <linux/timer.h>
72 #include <linux/ptrace.h>
73 #include <linux/errno.h>
74 #include <linux/ioport.h>
75 #include <linux/slab.h>
76 #include <linux/interrupt.h>
77 #include <linux/pci.h>
78 #include <linux/dma-mapping.h>
79 #include <linux/init.h>
80 #include <linux/netdevice.h>
81 #include <linux/etherdevice.h>
82 #include <linux/ethtool.h>
83 #include <linux/skbuff.h>
84 #include <linux/delay.h>
85 #include <linux/spinlock.h>
86 #include <linux/crc32.h>
87 #include <linux/bitops.h>
88
89 #include <asm/processor.h>
90 #include <asm/io.h>
91 #include <asm/dma.h>
92 #include <asm/uaccess.h>
93 #include <asm/irq.h>
94
95
96 /* Board/System/Debug information/definition ---------------- */
97 #define PCI_DM9132_ID 0x91321282 /* Davicom DM9132 ID */
98 #define PCI_DM9102_ID 0x91021282 /* Davicom DM9102 ID */
99 #define PCI_DM9100_ID 0x91001282 /* Davicom DM9100 ID */
100 #define PCI_DM9009_ID 0x90091282 /* Davicom DM9009 ID */
101
102 #define DM9102_IO_SIZE 0x80
103 #define DM9102A_IO_SIZE 0x100
104 #define TX_MAX_SEND_CNT 0x1 /* Maximum tx packet per time */
105 #define TX_DESC_CNT 0x10 /* Allocated Tx descriptors */
106 #define RX_DESC_CNT 0x20 /* Allocated Rx descriptors */
107 #define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
108 #define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
109 #define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
110 #define TX_BUF_ALLOC 0x600
111 #define RX_ALLOC_SIZE 0x620
112 #define DM910X_RESET 1
113 #define CR0_DEFAULT 0x00E00000 /* TX & RX burst mode */
114 #define CR6_DEFAULT 0x00080000 /* HD */
115 #define CR7_DEFAULT 0x180c1
116 #define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
117 #define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
118 #define MAX_PACKET_SIZE 1514
119 #define DMFE_MAX_MULTICAST 14
120 #define RX_COPY_SIZE 100
121 #define MAX_CHECK_PACKET 0x8000
122 #define DM9801_NOISE_FLOOR 8
123 #define DM9802_NOISE_FLOOR 5
124
125 #define DMFE_WOL_LINKCHANGE 0x20000000
126 #define DMFE_WOL_SAMPLEPACKET 0x10000000
127 #define DMFE_WOL_MAGICPACKET 0x08000000
128
129
130 #define DMFE_10MHF 0
131 #define DMFE_100MHF 1
132 #define DMFE_10MFD 4
133 #define DMFE_100MFD 5
134 #define DMFE_AUTO 8
135 #define DMFE_1M_HPNA 0x10
136
137 #define DMFE_TXTH_72 0x400000 /* TX TH 72 byte */
138 #define DMFE_TXTH_96 0x404000 /* TX TH 96 byte */
139 #define DMFE_TXTH_128 0x0000 /* TX TH 128 byte */
140 #define DMFE_TXTH_256 0x4000 /* TX TH 256 byte */
141 #define DMFE_TXTH_512 0x8000 /* TX TH 512 byte */
142 #define DMFE_TXTH_1K 0xC000 /* TX TH 1K byte */
143
144 #define DMFE_TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */
145 #define DMFE_TX_TIMEOUT ((3*HZ)/2) /* tx packet time-out time 1.5 s" */
146 #define DMFE_TX_KICK (HZ/2) /* tx packet Kick-out time 0.5 s" */
147
148 #define DMFE_DBUG(dbug_now, msg, value) \
149 do { \
150 if (dmfe_debug || (dbug_now)) \
151 printk(KERN_ERR DRV_NAME ": %s %lx\n",\
152 (msg), (long) (value)); \
153 } while (0)
154
155 #define SHOW_MEDIA_TYPE(mode) \
156 printk (KERN_INFO DRV_NAME ": Change Speed to %sMhz %s duplex\n" , \
157 (mode & 1) ? "100":"10", (mode & 4) ? "full":"half");
158
159
160 /* CR9 definition: SROM/MII */
161 #define CR9_SROM_READ 0x4800
162 #define CR9_SRCS 0x1
163 #define CR9_SRCLK 0x2
164 #define CR9_CRDOUT 0x8
165 #define SROM_DATA_0 0x0
166 #define SROM_DATA_1 0x4
167 #define PHY_DATA_1 0x20000
168 #define PHY_DATA_0 0x00000
169 #define MDCLKH 0x10000
170
171 #define PHY_POWER_DOWN 0x800
172
173 #define SROM_V41_CODE 0x14
174
175 #define SROM_CLK_WRITE(data, ioaddr) \
176 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
177 udelay(5); \
178 outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr); \
179 udelay(5); \
180 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
181 udelay(5);
182
183 #define __CHK_IO_SIZE(pci_id, dev_rev) \
184 (( ((pci_id)==PCI_DM9132_ID) || ((dev_rev) >= 0x30) ) ? \
185 DM9102A_IO_SIZE: DM9102_IO_SIZE)
186
187 #define CHK_IO_SIZE(pci_dev) \
188 (__CHK_IO_SIZE(((pci_dev)->device << 16) | (pci_dev)->vendor, \
189 (pci_dev)->revision))
190
191 /* Sten Check */
192 #define DEVICE net_device
193
194 /* Structure/enum declaration ------------------------------- */
195 struct tx_desc {
196 __le32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
197 char *tx_buf_ptr; /* Data for us */
198 struct tx_desc *next_tx_desc;
199 } __attribute__(( aligned(32) ));
200
201 struct rx_desc {
202 __le32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
203 struct sk_buff *rx_skb_ptr; /* Data for us */
204 struct rx_desc *next_rx_desc;
205 } __attribute__(( aligned(32) ));
206
207 struct dmfe_board_info {
208 u32 chip_id; /* Chip vendor/Device ID */
209 u8 chip_revision; /* Chip revision */
210 struct DEVICE *next_dev; /* next device */
211 struct pci_dev *pdev; /* PCI device */
212 spinlock_t lock;
213
214 long ioaddr; /* I/O base address */
215 u32 cr0_data;
216 u32 cr5_data;
217 u32 cr6_data;
218 u32 cr7_data;
219 u32 cr15_data;
220
221 /* pointer for memory physical address */
222 dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */
223 dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */
224 dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */
225 dma_addr_t first_tx_desc_dma;
226 dma_addr_t first_rx_desc_dma;
227
228 /* descriptor pointer */
229 unsigned char *buf_pool_ptr; /* Tx buffer pool memory */
230 unsigned char *buf_pool_start; /* Tx buffer pool align dword */
231 unsigned char *desc_pool_ptr; /* descriptor pool memory */
232 struct tx_desc *first_tx_desc;
233 struct tx_desc *tx_insert_ptr;
234 struct tx_desc *tx_remove_ptr;
235 struct rx_desc *first_rx_desc;
236 struct rx_desc *rx_insert_ptr;
237 struct rx_desc *rx_ready_ptr; /* packet come pointer */
238 unsigned long tx_packet_cnt; /* transmitted packet count */
239 unsigned long tx_queue_cnt; /* wait to send packet count */
240 unsigned long rx_avail_cnt; /* available rx descriptor count */
241 unsigned long interval_rx_cnt; /* rx packet count a callback time */
242
243 u16 HPNA_command; /* For HPNA register 16 */
244 u16 HPNA_timer; /* For HPNA remote device check */
245 u16 dbug_cnt;
246 u16 NIC_capability; /* NIC media capability */
247 u16 PHY_reg4; /* Saved Phyxcer register 4 value */
248
249 u8 HPNA_present; /* 0:none, 1:DM9801, 2:DM9802 */
250 u8 chip_type; /* Keep DM9102A chip type */
251 u8 media_mode; /* user specify media mode */
252 u8 op_mode; /* real work media mode */
253 u8 phy_addr;
254 u8 wait_reset; /* Hardware failed, need to reset */
255 u8 dm910x_chk_mode; /* Operating mode check */
256 u8 first_in_callback; /* Flag to record state */
257 u8 wol_mode; /* user WOL settings */
258 struct timer_list timer;
259
260 /* System defined statistic counter */
261 struct net_device_stats stats;
262
263 /* Driver defined statistic counter */
264 unsigned long tx_fifo_underrun;
265 unsigned long tx_loss_carrier;
266 unsigned long tx_no_carrier;
267 unsigned long tx_late_collision;
268 unsigned long tx_excessive_collision;
269 unsigned long tx_jabber_timeout;
270 unsigned long reset_count;
271 unsigned long reset_cr8;
272 unsigned long reset_fatal;
273 unsigned long reset_TXtimeout;
274
275 /* NIC SROM data */
276 unsigned char srom[128];
277 };
278
279 enum dmfe_offsets {
280 DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
281 DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
282 DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
283 DCR15 = 0x78
284 };
285
286 enum dmfe_CR6_bits {
287 CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
288 CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
289 CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
290 };
291
292 /* Global variable declaration ----------------------------- */
293 static int __devinitdata printed_version;
294 static char version[] __devinitdata =
295 KERN_INFO DRV_NAME ": Davicom DM9xxx net driver, version "
296 DRV_VERSION " (" DRV_RELDATE ")\n";
297
298 static int dmfe_debug;
299 static unsigned char dmfe_media_mode = DMFE_AUTO;
300 static u32 dmfe_cr6_user_set;
301
302 /* For module input parameter */
303 static int debug;
304 static u32 cr6set;
305 static unsigned char mode = 8;
306 static u8 chkmode = 1;
307 static u8 HPNA_mode; /* Default: Low Power/High Speed */
308 static u8 HPNA_rx_cmd; /* Default: Disable Rx remote command */
309 static u8 HPNA_tx_cmd; /* Default: Don't issue remote command */
310 static u8 HPNA_NoiseFloor; /* Default: HPNA NoiseFloor */
311 static u8 SF_mode; /* Special Function: 1:VLAN, 2:RX Flow Control
312 4: TX pause packet */
313
314
315 /* function declaration ------------------------------------- */
316 static int dmfe_open(struct DEVICE *);
317 static int dmfe_start_xmit(struct sk_buff *, struct DEVICE *);
318 static int dmfe_stop(struct DEVICE *);
319 static struct net_device_stats * dmfe_get_stats(struct DEVICE *);
320 static void dmfe_set_filter_mode(struct DEVICE *);
321 static const struct ethtool_ops netdev_ethtool_ops;
322 static u16 read_srom_word(long ,int);
323 static irqreturn_t dmfe_interrupt(int , void *);
324 #ifdef CONFIG_NET_POLL_CONTROLLER
325 static void poll_dmfe (struct net_device *dev);
326 #endif
327 static void dmfe_descriptor_init(struct dmfe_board_info *, unsigned long);
328 static void allocate_rx_buffer(struct dmfe_board_info *);
329 static void update_cr6(u32, unsigned long);
330 static void send_filter_frame(struct DEVICE * ,int);
331 static void dm9132_id_table(struct DEVICE * ,int);
332 static u16 phy_read(unsigned long, u8, u8, u32);
333 static void phy_write(unsigned long, u8, u8, u16, u32);
334 static void phy_write_1bit(unsigned long, u32);
335 static u16 phy_read_1bit(unsigned long);
336 static u8 dmfe_sense_speed(struct dmfe_board_info *);
337 static void dmfe_process_mode(struct dmfe_board_info *);
338 static void dmfe_timer(unsigned long);
339 static inline u32 cal_CRC(unsigned char *, unsigned int, u8);
340 static void dmfe_rx_packet(struct DEVICE *, struct dmfe_board_info *);
341 static void dmfe_free_tx_pkt(struct DEVICE *, struct dmfe_board_info *);
342 static void dmfe_reuse_skb(struct dmfe_board_info *, struct sk_buff *);
343 static void dmfe_dynamic_reset(struct DEVICE *);
344 static void dmfe_free_rxbuffer(struct dmfe_board_info *);
345 static void dmfe_init_dm910x(struct DEVICE *);
346 static void dmfe_parse_srom(struct dmfe_board_info *);
347 static void dmfe_program_DM9801(struct dmfe_board_info *, int);
348 static void dmfe_program_DM9802(struct dmfe_board_info *);
349 static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * );
350 static void dmfe_set_phyxcer(struct dmfe_board_info *);
351
352 /* DM910X network board routine ---------------------------- */
353
354 /*
355 * Search DM910X board ,allocate space and register it
356 */
357
358 static int __devinit dmfe_init_one (struct pci_dev *pdev,
359 const struct pci_device_id *ent)
360 {
361 struct dmfe_board_info *db; /* board information structure */
362 struct net_device *dev;
363 u32 pci_pmr;
364 int i, err;
365 DECLARE_MAC_BUF(mac);
366
367 DMFE_DBUG(0, "dmfe_init_one()", 0);
368
369 if (!printed_version++)
370 printk(version);
371
372 /* Init network device */
373 dev = alloc_etherdev(sizeof(*db));
374 if (dev == NULL)
375 return -ENOMEM;
376 SET_NETDEV_DEV(dev, &pdev->dev);
377
378 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
379 printk(KERN_WARNING DRV_NAME
380 ": 32-bit PCI DMA not available.\n");
381 err = -ENODEV;
382 goto err_out_free;
383 }
384
385 /* Enable Master/IO access, Disable memory access */
386 err = pci_enable_device(pdev);
387 if (err)
388 goto err_out_free;
389
390 if (!pci_resource_start(pdev, 0)) {
391 printk(KERN_ERR DRV_NAME ": I/O base is zero\n");
392 err = -ENODEV;
393 goto err_out_disable;
394 }
395
396 if (pci_resource_len(pdev, 0) < (CHK_IO_SIZE(pdev)) ) {
397 printk(KERN_ERR DRV_NAME ": Allocated I/O size too small\n");
398 err = -ENODEV;
399 goto err_out_disable;
400 }
401
402 #if 0 /* pci_{enable_device,set_master} sets minimum latency for us now */
403
404 /* Set Latency Timer 80h */
405 /* FIXME: setting values > 32 breaks some SiS 559x stuff.
406 Need a PCI quirk.. */
407
408 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
409 #endif
410
411 if (pci_request_regions(pdev, DRV_NAME)) {
412 printk(KERN_ERR DRV_NAME ": Failed to request PCI regions\n");
413 err = -ENODEV;
414 goto err_out_disable;
415 }
416
417 /* Init system & device */
418 db = netdev_priv(dev);
419
420 /* Allocate Tx/Rx descriptor memory */
421 db->desc_pool_ptr = pci_alloc_consistent(pdev, sizeof(struct tx_desc) *
422 DESC_ALL_CNT + 0x20, &db->desc_pool_dma_ptr);
423 if (!db->desc_pool_ptr)
424 goto err_out_res;
425
426 db->buf_pool_ptr = pci_alloc_consistent(pdev, TX_BUF_ALLOC *
427 TX_DESC_CNT + 4, &db->buf_pool_dma_ptr);
428 if (!db->buf_pool_ptr)
429 goto err_out_free_desc;
430
431 db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
432 db->first_tx_desc_dma = db->desc_pool_dma_ptr;
433 db->buf_pool_start = db->buf_pool_ptr;
434 db->buf_pool_dma_start = db->buf_pool_dma_ptr;
435
436 db->chip_id = ent->driver_data;
437 db->ioaddr = pci_resource_start(pdev, 0);
438 db->chip_revision = pdev->revision;
439 db->wol_mode = 0;
440
441 db->pdev = pdev;
442
443 dev->base_addr = db->ioaddr;
444 dev->irq = pdev->irq;
445 pci_set_drvdata(pdev, dev);
446 dev->open = &dmfe_open;
447 dev->hard_start_xmit = &dmfe_start_xmit;
448 dev->stop = &dmfe_stop;
449 dev->get_stats = &dmfe_get_stats;
450 dev->set_multicast_list = &dmfe_set_filter_mode;
451 #ifdef CONFIG_NET_POLL_CONTROLLER
452 dev->poll_controller = &poll_dmfe;
453 #endif
454 dev->ethtool_ops = &netdev_ethtool_ops;
455 netif_carrier_off(dev);
456 spin_lock_init(&db->lock);
457
458 pci_read_config_dword(pdev, 0x50, &pci_pmr);
459 pci_pmr &= 0x70000;
460 if ( (pci_pmr == 0x10000) && (db->chip_revision == 0x31) )
461 db->chip_type = 1; /* DM9102A E3 */
462 else
463 db->chip_type = 0;
464
465 /* read 64 word srom data */
466 for (i = 0; i < 64; i++)
467 ((__le16 *) db->srom)[i] =
468 cpu_to_le16(read_srom_word(db->ioaddr, i));
469
470 /* Set Node address */
471 for (i = 0; i < 6; i++)
472 dev->dev_addr[i] = db->srom[20 + i];
473
474 err = register_netdev (dev);
475 if (err)
476 goto err_out_free_buf;
477
478 printk(KERN_INFO "%s: Davicom DM%04lx at pci%s, "
479 "%s, irq %d.\n",
480 dev->name,
481 ent->driver_data >> 16,
482 pci_name(pdev),
483 print_mac(mac, dev->dev_addr),
484 dev->irq);
485
486 pci_set_master(pdev);
487
488 return 0;
489
490 err_out_free_buf:
491 pci_free_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
492 db->buf_pool_ptr, db->buf_pool_dma_ptr);
493 err_out_free_desc:
494 pci_free_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20,
495 db->desc_pool_ptr, db->desc_pool_dma_ptr);
496 err_out_res:
497 pci_release_regions(pdev);
498 err_out_disable:
499 pci_disable_device(pdev);
500 err_out_free:
501 pci_set_drvdata(pdev, NULL);
502 free_netdev(dev);
503
504 return err;
505 }
506
507
508 static void __devexit dmfe_remove_one (struct pci_dev *pdev)
509 {
510 struct net_device *dev = pci_get_drvdata(pdev);
511 struct dmfe_board_info *db = netdev_priv(dev);
512
513 DMFE_DBUG(0, "dmfe_remove_one()", 0);
514
515 if (dev) {
516
517 unregister_netdev(dev);
518
519 pci_free_consistent(db->pdev, sizeof(struct tx_desc) *
520 DESC_ALL_CNT + 0x20, db->desc_pool_ptr,
521 db->desc_pool_dma_ptr);
522 pci_free_consistent(db->pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
523 db->buf_pool_ptr, db->buf_pool_dma_ptr);
524 pci_release_regions(pdev);
525 free_netdev(dev); /* free board information */
526
527 pci_set_drvdata(pdev, NULL);
528 }
529
530 DMFE_DBUG(0, "dmfe_remove_one() exit", 0);
531 }
532
533
534 /*
535 * Open the interface.
536 * The interface is opened whenever "ifconfig" actives it.
537 */
538
539 static int dmfe_open(struct DEVICE *dev)
540 {
541 int ret;
542 struct dmfe_board_info *db = netdev_priv(dev);
543
544 DMFE_DBUG(0, "dmfe_open", 0);
545
546 ret = request_irq(dev->irq, &dmfe_interrupt,
547 IRQF_SHARED, dev->name, dev);
548 if (ret)
549 return ret;
550
551 /* system variable init */
552 db->cr6_data = CR6_DEFAULT | dmfe_cr6_user_set;
553 db->tx_packet_cnt = 0;
554 db->tx_queue_cnt = 0;
555 db->rx_avail_cnt = 0;
556 db->wait_reset = 0;
557
558 db->first_in_callback = 0;
559 db->NIC_capability = 0xf; /* All capability*/
560 db->PHY_reg4 = 0x1e0;
561
562 /* CR6 operation mode decision */
563 if ( !chkmode || (db->chip_id == PCI_DM9132_ID) ||
564 (db->chip_revision >= 0x30) ) {
565 db->cr6_data |= DMFE_TXTH_256;
566 db->cr0_data = CR0_DEFAULT;
567 db->dm910x_chk_mode=4; /* Enter the normal mode */
568 } else {
569 db->cr6_data |= CR6_SFT; /* Store & Forward mode */
570 db->cr0_data = 0;
571 db->dm910x_chk_mode = 1; /* Enter the check mode */
572 }
573
574 /* Initilize DM910X board */
575 dmfe_init_dm910x(dev);
576
577 /* Active System Interface */
578 netif_wake_queue(dev);
579
580 /* set and active a timer process */
581 init_timer(&db->timer);
582 db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
583 db->timer.data = (unsigned long)dev;
584 db->timer.function = &dmfe_timer;
585 add_timer(&db->timer);
586
587 return 0;
588 }
589
590
591 /* Initilize DM910X board
592 * Reset DM910X board
593 * Initilize TX/Rx descriptor chain structure
594 * Send the set-up frame
595 * Enable Tx/Rx machine
596 */
597
598 static void dmfe_init_dm910x(struct DEVICE *dev)
599 {
600 struct dmfe_board_info *db = netdev_priv(dev);
601 unsigned long ioaddr = db->ioaddr;
602
603 DMFE_DBUG(0, "dmfe_init_dm910x()", 0);
604
605 /* Reset DM910x MAC controller */
606 outl(DM910X_RESET, ioaddr + DCR0); /* RESET MAC */
607 udelay(100);
608 outl(db->cr0_data, ioaddr + DCR0);
609 udelay(5);
610
611 /* Phy addr : DM910(A)2/DM9132/9801, phy address = 1 */
612 db->phy_addr = 1;
613
614 /* Parser SROM and media mode */
615 dmfe_parse_srom(db);
616 db->media_mode = dmfe_media_mode;
617
618 /* RESET Phyxcer Chip by GPR port bit 7 */
619 outl(0x180, ioaddr + DCR12); /* Let bit 7 output port */
620 if (db->chip_id == PCI_DM9009_ID) {
621 outl(0x80, ioaddr + DCR12); /* Issue RESET signal */
622 mdelay(300); /* Delay 300 ms */
623 }
624 outl(0x0, ioaddr + DCR12); /* Clear RESET signal */
625
626 /* Process Phyxcer Media Mode */
627 if ( !(db->media_mode & 0x10) ) /* Force 1M mode */
628 dmfe_set_phyxcer(db);
629
630 /* Media Mode Process */
631 if ( !(db->media_mode & DMFE_AUTO) )
632 db->op_mode = db->media_mode; /* Force Mode */
633
634 /* Initiliaze Transmit/Receive decriptor and CR3/4 */
635 dmfe_descriptor_init(db, ioaddr);
636
637 /* Init CR6 to program DM910x operation */
638 update_cr6(db->cr6_data, ioaddr);
639
640 /* Send setup frame */
641 if (db->chip_id == PCI_DM9132_ID)
642 dm9132_id_table(dev, dev->mc_count); /* DM9132 */
643 else
644 send_filter_frame(dev, dev->mc_count); /* DM9102/DM9102A */
645
646 /* Init CR7, interrupt active bit */
647 db->cr7_data = CR7_DEFAULT;
648 outl(db->cr7_data, ioaddr + DCR7);
649
650 /* Init CR15, Tx jabber and Rx watchdog timer */
651 outl(db->cr15_data, ioaddr + DCR15);
652
653 /* Enable DM910X Tx/Rx function */
654 db->cr6_data |= CR6_RXSC | CR6_TXSC | 0x40000;
655 update_cr6(db->cr6_data, ioaddr);
656 }
657
658
659 /*
660 * Hardware start transmission.
661 * Send a packet to media from the upper layer.
662 */
663
664 static int dmfe_start_xmit(struct sk_buff *skb, struct DEVICE *dev)
665 {
666 struct dmfe_board_info *db = netdev_priv(dev);
667 struct tx_desc *txptr;
668 unsigned long flags;
669
670 DMFE_DBUG(0, "dmfe_start_xmit", 0);
671
672 /* Resource flag check */
673 netif_stop_queue(dev);
674
675 /* Too large packet check */
676 if (skb->len > MAX_PACKET_SIZE) {
677 printk(KERN_ERR DRV_NAME ": big packet = %d\n", (u16)skb->len);
678 dev_kfree_skb(skb);
679 return 0;
680 }
681
682 spin_lock_irqsave(&db->lock, flags);
683
684 /* No Tx resource check, it never happen nromally */
685 if (db->tx_queue_cnt >= TX_FREE_DESC_CNT) {
686 spin_unlock_irqrestore(&db->lock, flags);
687 printk(KERN_ERR DRV_NAME ": No Tx resource %ld\n",
688 db->tx_queue_cnt);
689 return 1;
690 }
691
692 /* Disable NIC interrupt */
693 outl(0, dev->base_addr + DCR7);
694
695 /* transmit this packet */
696 txptr = db->tx_insert_ptr;
697 skb_copy_from_linear_data(skb, txptr->tx_buf_ptr, skb->len);
698 txptr->tdes1 = cpu_to_le32(0xe1000000 | skb->len);
699
700 /* Point to next transmit free descriptor */
701 db->tx_insert_ptr = txptr->next_tx_desc;
702
703 /* Transmit Packet Process */
704 if ( (!db->tx_queue_cnt) && (db->tx_packet_cnt < TX_MAX_SEND_CNT) ) {
705 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
706 db->tx_packet_cnt++; /* Ready to send */
707 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
708 dev->trans_start = jiffies; /* saved time stamp */
709 } else {
710 db->tx_queue_cnt++; /* queue TX packet */
711 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
712 }
713
714 /* Tx resource check */
715 if ( db->tx_queue_cnt < TX_FREE_DESC_CNT )
716 netif_wake_queue(dev);
717
718 /* Restore CR7 to enable interrupt */
719 spin_unlock_irqrestore(&db->lock, flags);
720 outl(db->cr7_data, dev->base_addr + DCR7);
721
722 /* free this SKB */
723 dev_kfree_skb(skb);
724
725 return 0;
726 }
727
728
729 /*
730 * Stop the interface.
731 * The interface is stopped when it is brought.
732 */
733
734 static int dmfe_stop(struct DEVICE *dev)
735 {
736 struct dmfe_board_info *db = netdev_priv(dev);
737 unsigned long ioaddr = dev->base_addr;
738
739 DMFE_DBUG(0, "dmfe_stop", 0);
740
741 /* disable system */
742 netif_stop_queue(dev);
743
744 /* deleted timer */
745 del_timer_sync(&db->timer);
746
747 /* Reset & stop DM910X board */
748 outl(DM910X_RESET, ioaddr + DCR0);
749 udelay(5);
750 phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
751
752 /* free interrupt */
753 free_irq(dev->irq, dev);
754
755 /* free allocated rx buffer */
756 dmfe_free_rxbuffer(db);
757
758 #if 0
759 /* show statistic counter */
760 printk(DRV_NAME ": FU:%lx EC:%lx LC:%lx NC:%lx"
761 " LOC:%lx TXJT:%lx RESET:%lx RCR8:%lx FAL:%lx TT:%lx\n",
762 db->tx_fifo_underrun, db->tx_excessive_collision,
763 db->tx_late_collision, db->tx_no_carrier, db->tx_loss_carrier,
764 db->tx_jabber_timeout, db->reset_count, db->reset_cr8,
765 db->reset_fatal, db->reset_TXtimeout);
766 #endif
767
768 return 0;
769 }
770
771
772 /*
773 * DM9102 insterrupt handler
774 * receive the packet to upper layer, free the transmitted packet
775 */
776
777 static irqreturn_t dmfe_interrupt(int irq, void *dev_id)
778 {
779 struct DEVICE *dev = dev_id;
780 struct dmfe_board_info *db = netdev_priv(dev);
781 unsigned long ioaddr = dev->base_addr;
782 unsigned long flags;
783
784 DMFE_DBUG(0, "dmfe_interrupt()", 0);
785
786 spin_lock_irqsave(&db->lock, flags);
787
788 /* Got DM910X status */
789 db->cr5_data = inl(ioaddr + DCR5);
790 outl(db->cr5_data, ioaddr + DCR5);
791 if ( !(db->cr5_data & 0xc1) ) {
792 spin_unlock_irqrestore(&db->lock, flags);
793 return IRQ_HANDLED;
794 }
795
796 /* Disable all interrupt in CR7 to solve the interrupt edge problem */
797 outl(0, ioaddr + DCR7);
798
799 /* Check system status */
800 if (db->cr5_data & 0x2000) {
801 /* system bus error happen */
802 DMFE_DBUG(1, "System bus error happen. CR5=", db->cr5_data);
803 db->reset_fatal++;
804 db->wait_reset = 1; /* Need to RESET */
805 spin_unlock_irqrestore(&db->lock, flags);
806 return IRQ_HANDLED;
807 }
808
809 /* Received the coming packet */
810 if ( (db->cr5_data & 0x40) && db->rx_avail_cnt )
811 dmfe_rx_packet(dev, db);
812
813 /* reallocate rx descriptor buffer */
814 if (db->rx_avail_cnt<RX_DESC_CNT)
815 allocate_rx_buffer(db);
816
817 /* Free the transmitted descriptor */
818 if ( db->cr5_data & 0x01)
819 dmfe_free_tx_pkt(dev, db);
820
821 /* Mode Check */
822 if (db->dm910x_chk_mode & 0x2) {
823 db->dm910x_chk_mode = 0x4;
824 db->cr6_data |= 0x100;
825 update_cr6(db->cr6_data, db->ioaddr);
826 }
827
828 /* Restore CR7 to enable interrupt mask */
829 outl(db->cr7_data, ioaddr + DCR7);
830
831 spin_unlock_irqrestore(&db->lock, flags);
832 return IRQ_HANDLED;
833 }
834
835
836 #ifdef CONFIG_NET_POLL_CONTROLLER
837 /*
838 * Polling 'interrupt' - used by things like netconsole to send skbs
839 * without having to re-enable interrupts. It's not called while
840 * the interrupt routine is executing.
841 */
842
843 static void poll_dmfe (struct net_device *dev)
844 {
845 /* disable_irq here is not very nice, but with the lockless
846 interrupt handler we have no other choice. */
847 disable_irq(dev->irq);
848 dmfe_interrupt (dev->irq, dev);
849 enable_irq(dev->irq);
850 }
851 #endif
852
853 /*
854 * Free TX resource after TX complete
855 */
856
857 static void dmfe_free_tx_pkt(struct DEVICE *dev, struct dmfe_board_info * db)
858 {
859 struct tx_desc *txptr;
860 unsigned long ioaddr = dev->base_addr;
861 u32 tdes0;
862
863 txptr = db->tx_remove_ptr;
864 while(db->tx_packet_cnt) {
865 tdes0 = le32_to_cpu(txptr->tdes0);
866 /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */
867 if (tdes0 & 0x80000000)
868 break;
869
870 /* A packet sent completed */
871 db->tx_packet_cnt--;
872 db->stats.tx_packets++;
873
874 /* Transmit statistic counter */
875 if ( tdes0 != 0x7fffffff ) {
876 /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */
877 db->stats.collisions += (tdes0 >> 3) & 0xf;
878 db->stats.tx_bytes += le32_to_cpu(txptr->tdes1) & 0x7ff;
879 if (tdes0 & TDES0_ERR_MASK) {
880 db->stats.tx_errors++;
881
882 if (tdes0 & 0x0002) { /* UnderRun */
883 db->tx_fifo_underrun++;
884 if ( !(db->cr6_data & CR6_SFT) ) {
885 db->cr6_data = db->cr6_data | CR6_SFT;
886 update_cr6(db->cr6_data, db->ioaddr);
887 }
888 }
889 if (tdes0 & 0x0100)
890 db->tx_excessive_collision++;
891 if (tdes0 & 0x0200)
892 db->tx_late_collision++;
893 if (tdes0 & 0x0400)
894 db->tx_no_carrier++;
895 if (tdes0 & 0x0800)
896 db->tx_loss_carrier++;
897 if (tdes0 & 0x4000)
898 db->tx_jabber_timeout++;
899 }
900 }
901
902 txptr = txptr->next_tx_desc;
903 }/* End of while */
904
905 /* Update TX remove pointer to next */
906 db->tx_remove_ptr = txptr;
907
908 /* Send the Tx packet in queue */
909 if ( (db->tx_packet_cnt < TX_MAX_SEND_CNT) && db->tx_queue_cnt ) {
910 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
911 db->tx_packet_cnt++; /* Ready to send */
912 db->tx_queue_cnt--;
913 outl(0x1, ioaddr + DCR1); /* Issue Tx polling */
914 dev->trans_start = jiffies; /* saved time stamp */
915 }
916
917 /* Resource available check */
918 if ( db->tx_queue_cnt < TX_WAKE_DESC_CNT )
919 netif_wake_queue(dev); /* Active upper layer, send again */
920 }
921
922
923 /*
924 * Calculate the CRC valude of the Rx packet
925 * flag = 1 : return the reverse CRC (for the received packet CRC)
926 * 0 : return the normal CRC (for Hash Table index)
927 */
928
929 static inline u32 cal_CRC(unsigned char * Data, unsigned int Len, u8 flag)
930 {
931 u32 crc = crc32(~0, Data, Len);
932 if (flag) crc = ~crc;
933 return crc;
934 }
935
936
937 /*
938 * Receive the come packet and pass to upper layer
939 */
940
941 static void dmfe_rx_packet(struct DEVICE *dev, struct dmfe_board_info * db)
942 {
943 struct rx_desc *rxptr;
944 struct sk_buff *skb, *newskb;
945 int rxlen;
946 u32 rdes0;
947
948 rxptr = db->rx_ready_ptr;
949
950 while(db->rx_avail_cnt) {
951 rdes0 = le32_to_cpu(rxptr->rdes0);
952 if (rdes0 & 0x80000000) /* packet owner check */
953 break;
954
955 db->rx_avail_cnt--;
956 db->interval_rx_cnt++;
957
958 pci_unmap_single(db->pdev, le32_to_cpu(rxptr->rdes2),
959 RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
960
961 if ( (rdes0 & 0x300) != 0x300) {
962 /* A packet without First/Last flag */
963 /* reuse this SKB */
964 DMFE_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
965 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
966 } else {
967 /* A packet with First/Last flag */
968 rxlen = ( (rdes0 >> 16) & 0x3fff) - 4;
969
970 /* error summary bit check */
971 if (rdes0 & 0x8000) {
972 /* This is a error packet */
973 //printk(DRV_NAME ": rdes0: %lx\n", rdes0);
974 db->stats.rx_errors++;
975 if (rdes0 & 1)
976 db->stats.rx_fifo_errors++;
977 if (rdes0 & 2)
978 db->stats.rx_crc_errors++;
979 if (rdes0 & 0x80)
980 db->stats.rx_length_errors++;
981 }
982
983 if ( !(rdes0 & 0x8000) ||
984 ((db->cr6_data & CR6_PM) && (rxlen>6)) ) {
985 skb = rxptr->rx_skb_ptr;
986
987 /* Received Packet CRC check need or not */
988 if ( (db->dm910x_chk_mode & 1) &&
989 (cal_CRC(skb->data, rxlen, 1) !=
990 (*(u32 *) (skb->data+rxlen) ))) { /* FIXME (?) */
991 /* Found a error received packet */
992 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
993 db->dm910x_chk_mode = 3;
994 } else {
995 /* Good packet, send to upper layer */
996 /* Shorst packet used new SKB */
997 if ((rxlen < RX_COPY_SIZE) &&
998 ((newskb = dev_alloc_skb(rxlen + 2))
999 != NULL)) {
1000
1001 skb = newskb;
1002 /* size less than COPY_SIZE, allocate a rxlen SKB */
1003 skb_reserve(skb, 2); /* 16byte align */
1004 skb_copy_from_linear_data(rxptr->rx_skb_ptr,
1005 skb_put(skb, rxlen),
1006 rxlen);
1007 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
1008 } else
1009 skb_put(skb, rxlen);
1010
1011 skb->protocol = eth_type_trans(skb, dev);
1012 netif_rx(skb);
1013 dev->last_rx = jiffies;
1014 db->stats.rx_packets++;
1015 db->stats.rx_bytes += rxlen;
1016 }
1017 } else {
1018 /* Reuse SKB buffer when the packet is error */
1019 DMFE_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
1020 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
1021 }
1022 }
1023
1024 rxptr = rxptr->next_rx_desc;
1025 }
1026
1027 db->rx_ready_ptr = rxptr;
1028 }
1029
1030
1031 /*
1032 * Get statistics from driver.
1033 */
1034
1035 static struct net_device_stats * dmfe_get_stats(struct DEVICE *dev)
1036 {
1037 struct dmfe_board_info *db = netdev_priv(dev);
1038
1039 DMFE_DBUG(0, "dmfe_get_stats", 0);
1040 return &db->stats;
1041 }
1042
1043
1044 /*
1045 * Set DM910X multicast address
1046 */
1047
1048 static void dmfe_set_filter_mode(struct DEVICE * dev)
1049 {
1050 struct dmfe_board_info *db = netdev_priv(dev);
1051 unsigned long flags;
1052
1053 DMFE_DBUG(0, "dmfe_set_filter_mode()", 0);
1054 spin_lock_irqsave(&db->lock, flags);
1055
1056 if (dev->flags & IFF_PROMISC) {
1057 DMFE_DBUG(0, "Enable PROM Mode", 0);
1058 db->cr6_data |= CR6_PM | CR6_PBF;
1059 update_cr6(db->cr6_data, db->ioaddr);
1060 spin_unlock_irqrestore(&db->lock, flags);
1061 return;
1062 }
1063
1064 if (dev->flags & IFF_ALLMULTI || dev->mc_count > DMFE_MAX_MULTICAST) {
1065 DMFE_DBUG(0, "Pass all multicast address", dev->mc_count);
1066 db->cr6_data &= ~(CR6_PM | CR6_PBF);
1067 db->cr6_data |= CR6_PAM;
1068 spin_unlock_irqrestore(&db->lock, flags);
1069 return;
1070 }
1071
1072 DMFE_DBUG(0, "Set multicast address", dev->mc_count);
1073 if (db->chip_id == PCI_DM9132_ID)
1074 dm9132_id_table(dev, dev->mc_count); /* DM9132 */
1075 else
1076 send_filter_frame(dev, dev->mc_count); /* DM9102/DM9102A */
1077 spin_unlock_irqrestore(&db->lock, flags);
1078 }
1079
1080 /*
1081 * Ethtool interace
1082 */
1083
1084 static void dmfe_ethtool_get_drvinfo(struct net_device *dev,
1085 struct ethtool_drvinfo *info)
1086 {
1087 struct dmfe_board_info *np = netdev_priv(dev);
1088
1089 strcpy(info->driver, DRV_NAME);
1090 strcpy(info->version, DRV_VERSION);
1091 if (np->pdev)
1092 strcpy(info->bus_info, pci_name(np->pdev));
1093 else
1094 sprintf(info->bus_info, "EISA 0x%lx %d",
1095 dev->base_addr, dev->irq);
1096 }
1097
1098 static int dmfe_ethtool_set_wol(struct net_device *dev,
1099 struct ethtool_wolinfo *wolinfo)
1100 {
1101 struct dmfe_board_info *db = netdev_priv(dev);
1102
1103 if (wolinfo->wolopts & (WAKE_UCAST | WAKE_MCAST | WAKE_BCAST |
1104 WAKE_ARP | WAKE_MAGICSECURE))
1105 return -EOPNOTSUPP;
1106
1107 db->wol_mode = wolinfo->wolopts;
1108 return 0;
1109 }
1110
1111 static void dmfe_ethtool_get_wol(struct net_device *dev,
1112 struct ethtool_wolinfo *wolinfo)
1113 {
1114 struct dmfe_board_info *db = netdev_priv(dev);
1115
1116 wolinfo->supported = WAKE_PHY | WAKE_MAGIC;
1117 wolinfo->wolopts = db->wol_mode;
1118 return;
1119 }
1120
1121
1122 static const struct ethtool_ops netdev_ethtool_ops = {
1123 .get_drvinfo = dmfe_ethtool_get_drvinfo,
1124 .get_link = ethtool_op_get_link,
1125 .set_wol = dmfe_ethtool_set_wol,
1126 .get_wol = dmfe_ethtool_get_wol,
1127 };
1128
1129 /*
1130 * A periodic timer routine
1131 * Dynamic media sense, allocate Rx buffer...
1132 */
1133
1134 static void dmfe_timer(unsigned long data)
1135 {
1136 u32 tmp_cr8;
1137 unsigned char tmp_cr12;
1138 struct DEVICE *dev = (struct DEVICE *) data;
1139 struct dmfe_board_info *db = netdev_priv(dev);
1140 unsigned long flags;
1141
1142 int link_ok, link_ok_phy;
1143
1144 DMFE_DBUG(0, "dmfe_timer()", 0);
1145 spin_lock_irqsave(&db->lock, flags);
1146
1147 /* Media mode process when Link OK before enter this route */
1148 if (db->first_in_callback == 0) {
1149 db->first_in_callback = 1;
1150 if (db->chip_type && (db->chip_id==PCI_DM9102_ID)) {
1151 db->cr6_data &= ~0x40000;
1152 update_cr6(db->cr6_data, db->ioaddr);
1153 phy_write(db->ioaddr,
1154 db->phy_addr, 0, 0x1000, db->chip_id);
1155 db->cr6_data |= 0x40000;
1156 update_cr6(db->cr6_data, db->ioaddr);
1157 db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
1158 add_timer(&db->timer);
1159 spin_unlock_irqrestore(&db->lock, flags);
1160 return;
1161 }
1162 }
1163
1164
1165 /* Operating Mode Check */
1166 if ( (db->dm910x_chk_mode & 0x1) &&
1167 (db->stats.rx_packets > MAX_CHECK_PACKET) )
1168 db->dm910x_chk_mode = 0x4;
1169
1170 /* Dynamic reset DM910X : system error or transmit time-out */
1171 tmp_cr8 = inl(db->ioaddr + DCR8);
1172 if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) {
1173 db->reset_cr8++;
1174 db->wait_reset = 1;
1175 }
1176 db->interval_rx_cnt = 0;
1177
1178 /* TX polling kick monitor */
1179 if ( db->tx_packet_cnt &&
1180 time_after(jiffies, dev->trans_start + DMFE_TX_KICK) ) {
1181 outl(0x1, dev->base_addr + DCR1); /* Tx polling again */
1182
1183 /* TX Timeout */
1184 if ( time_after(jiffies, dev->trans_start + DMFE_TX_TIMEOUT) ) {
1185 db->reset_TXtimeout++;
1186 db->wait_reset = 1;
1187 printk(KERN_WARNING "%s: Tx timeout - resetting\n",
1188 dev->name);
1189 }
1190 }
1191
1192 if (db->wait_reset) {
1193 DMFE_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt);
1194 db->reset_count++;
1195 dmfe_dynamic_reset(dev);
1196 db->first_in_callback = 0;
1197 db->timer.expires = DMFE_TIMER_WUT;
1198 add_timer(&db->timer);
1199 spin_unlock_irqrestore(&db->lock, flags);
1200 return;
1201 }
1202
1203 /* Link status check, Dynamic media type change */
1204 if (db->chip_id == PCI_DM9132_ID)
1205 tmp_cr12 = inb(db->ioaddr + DCR9 + 3); /* DM9132 */
1206 else
1207 tmp_cr12 = inb(db->ioaddr + DCR12); /* DM9102/DM9102A */
1208
1209 if ( ((db->chip_id == PCI_DM9102_ID) &&
1210 (db->chip_revision == 0x30)) ||
1211 ((db->chip_id == PCI_DM9132_ID) &&
1212 (db->chip_revision == 0x10)) ) {
1213 /* DM9102A Chip */
1214 if (tmp_cr12 & 2)
1215 link_ok = 0;
1216 else
1217 link_ok = 1;
1218 }
1219 else
1220 /*0x43 is used instead of 0x3 because bit 6 should represent
1221 link status of external PHY */
1222 link_ok = (tmp_cr12 & 0x43) ? 1 : 0;
1223
1224
1225 /* If chip reports that link is failed it could be because external
1226 PHY link status pin is not conected correctly to chip
1227 To be sure ask PHY too.
1228 */
1229
1230 /* need a dummy read because of PHY's register latch*/
1231 phy_read (db->ioaddr, db->phy_addr, 1, db->chip_id);
1232 link_ok_phy = (phy_read (db->ioaddr,
1233 db->phy_addr, 1, db->chip_id) & 0x4) ? 1 : 0;
1234
1235 if (link_ok_phy != link_ok) {
1236 DMFE_DBUG (0, "PHY and chip report different link status", 0);
1237 link_ok = link_ok | link_ok_phy;
1238 }
1239
1240 if ( !link_ok && netif_carrier_ok(dev)) {
1241 /* Link Failed */
1242 DMFE_DBUG(0, "Link Failed", tmp_cr12);
1243 netif_carrier_off(dev);
1244
1245 /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */
1246 /* AUTO or force 1M Homerun/Longrun don't need */
1247 if ( !(db->media_mode & 0x38) )
1248 phy_write(db->ioaddr, db->phy_addr,
1249 0, 0x1000, db->chip_id);
1250
1251 /* AUTO mode, if INT phyxcer link failed, select EXT device */
1252 if (db->media_mode & DMFE_AUTO) {
1253 /* 10/100M link failed, used 1M Home-Net */
1254 db->cr6_data|=0x00040000; /* bit18=1, MII */
1255 db->cr6_data&=~0x00000200; /* bit9=0, HD mode */
1256 update_cr6(db->cr6_data, db->ioaddr);
1257 }
1258 } else if (!netif_carrier_ok(dev)) {
1259
1260 DMFE_DBUG(0, "Link link OK", tmp_cr12);
1261
1262 /* Auto Sense Speed */
1263 if ( !(db->media_mode & DMFE_AUTO) || !dmfe_sense_speed(db)) {
1264 netif_carrier_on(dev);
1265 SHOW_MEDIA_TYPE(db->op_mode);
1266 }
1267
1268 dmfe_process_mode(db);
1269 }
1270
1271 /* HPNA remote command check */
1272 if (db->HPNA_command & 0xf00) {
1273 db->HPNA_timer--;
1274 if (!db->HPNA_timer)
1275 dmfe_HPNA_remote_cmd_chk(db);
1276 }
1277
1278 /* Timer active again */
1279 db->timer.expires = DMFE_TIMER_WUT;
1280 add_timer(&db->timer);
1281 spin_unlock_irqrestore(&db->lock, flags);
1282 }
1283
1284
1285 /*
1286 * Dynamic reset the DM910X board
1287 * Stop DM910X board
1288 * Free Tx/Rx allocated memory
1289 * Reset DM910X board
1290 * Re-initilize DM910X board
1291 */
1292
1293 static void dmfe_dynamic_reset(struct DEVICE *dev)
1294 {
1295 struct dmfe_board_info *db = netdev_priv(dev);
1296
1297 DMFE_DBUG(0, "dmfe_dynamic_reset()", 0);
1298
1299 /* Sopt MAC controller */
1300 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
1301 update_cr6(db->cr6_data, dev->base_addr);
1302 outl(0, dev->base_addr + DCR7); /* Disable Interrupt */
1303 outl(inl(dev->base_addr + DCR5), dev->base_addr + DCR5);
1304
1305 /* Disable upper layer interface */
1306 netif_stop_queue(dev);
1307
1308 /* Free Rx Allocate buffer */
1309 dmfe_free_rxbuffer(db);
1310
1311 /* system variable init */
1312 db->tx_packet_cnt = 0;
1313 db->tx_queue_cnt = 0;
1314 db->rx_avail_cnt = 0;
1315 netif_carrier_off(dev);
1316 db->wait_reset = 0;
1317
1318 /* Re-initilize DM910X board */
1319 dmfe_init_dm910x(dev);
1320
1321 /* Restart upper layer interface */
1322 netif_wake_queue(dev);
1323 }
1324
1325
1326 /*
1327 * free all allocated rx buffer
1328 */
1329
1330 static void dmfe_free_rxbuffer(struct dmfe_board_info * db)
1331 {
1332 DMFE_DBUG(0, "dmfe_free_rxbuffer()", 0);
1333
1334 /* free allocated rx buffer */
1335 while (db->rx_avail_cnt) {
1336 dev_kfree_skb(db->rx_ready_ptr->rx_skb_ptr);
1337 db->rx_ready_ptr = db->rx_ready_ptr->next_rx_desc;
1338 db->rx_avail_cnt--;
1339 }
1340 }
1341
1342
1343 /*
1344 * Reuse the SK buffer
1345 */
1346
1347 static void dmfe_reuse_skb(struct dmfe_board_info *db, struct sk_buff * skb)
1348 {
1349 struct rx_desc *rxptr = db->rx_insert_ptr;
1350
1351 if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) {
1352 rxptr->rx_skb_ptr = skb;
1353 rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev,
1354 skb->data, RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) );
1355 wmb();
1356 rxptr->rdes0 = cpu_to_le32(0x80000000);
1357 db->rx_avail_cnt++;
1358 db->rx_insert_ptr = rxptr->next_rx_desc;
1359 } else
1360 DMFE_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt);
1361 }
1362
1363
1364 /*
1365 * Initialize transmit/Receive descriptor
1366 * Using Chain structure, and allocate Tx/Rx buffer
1367 */
1368
1369 static void dmfe_descriptor_init(struct dmfe_board_info *db, unsigned long ioaddr)
1370 {
1371 struct tx_desc *tmp_tx;
1372 struct rx_desc *tmp_rx;
1373 unsigned char *tmp_buf;
1374 dma_addr_t tmp_tx_dma, tmp_rx_dma;
1375 dma_addr_t tmp_buf_dma;
1376 int i;
1377
1378 DMFE_DBUG(0, "dmfe_descriptor_init()", 0);
1379
1380 /* tx descriptor start pointer */
1381 db->tx_insert_ptr = db->first_tx_desc;
1382 db->tx_remove_ptr = db->first_tx_desc;
1383 outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */
1384
1385 /* rx descriptor start pointer */
1386 db->first_rx_desc = (void *)db->first_tx_desc +
1387 sizeof(struct tx_desc) * TX_DESC_CNT;
1388
1389 db->first_rx_desc_dma = db->first_tx_desc_dma +
1390 sizeof(struct tx_desc) * TX_DESC_CNT;
1391 db->rx_insert_ptr = db->first_rx_desc;
1392 db->rx_ready_ptr = db->first_rx_desc;
1393 outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */
1394
1395 /* Init Transmit chain */
1396 tmp_buf = db->buf_pool_start;
1397 tmp_buf_dma = db->buf_pool_dma_start;
1398 tmp_tx_dma = db->first_tx_desc_dma;
1399 for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) {
1400 tmp_tx->tx_buf_ptr = tmp_buf;
1401 tmp_tx->tdes0 = cpu_to_le32(0);
1402 tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
1403 tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
1404 tmp_tx_dma += sizeof(struct tx_desc);
1405 tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
1406 tmp_tx->next_tx_desc = tmp_tx + 1;
1407 tmp_buf = tmp_buf + TX_BUF_ALLOC;
1408 tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
1409 }
1410 (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
1411 tmp_tx->next_tx_desc = db->first_tx_desc;
1412
1413 /* Init Receive descriptor chain */
1414 tmp_rx_dma=db->first_rx_desc_dma;
1415 for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) {
1416 tmp_rx->rdes0 = cpu_to_le32(0);
1417 tmp_rx->rdes1 = cpu_to_le32(0x01000600);
1418 tmp_rx_dma += sizeof(struct rx_desc);
1419 tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
1420 tmp_rx->next_rx_desc = tmp_rx + 1;
1421 }
1422 (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
1423 tmp_rx->next_rx_desc = db->first_rx_desc;
1424
1425 /* pre-allocate Rx buffer */
1426 allocate_rx_buffer(db);
1427 }
1428
1429
1430 /*
1431 * Update CR6 value
1432 * Firstly stop DM910X , then written value and start
1433 */
1434
1435 static void update_cr6(u32 cr6_data, unsigned long ioaddr)
1436 {
1437 u32 cr6_tmp;
1438
1439 cr6_tmp = cr6_data & ~0x2002; /* stop Tx/Rx */
1440 outl(cr6_tmp, ioaddr + DCR6);
1441 udelay(5);
1442 outl(cr6_data, ioaddr + DCR6);
1443 udelay(5);
1444 }
1445
1446
1447 /*
1448 * Send a setup frame for DM9132
1449 * This setup frame initilize DM910X address filter mode
1450 */
1451
1452 static void dm9132_id_table(struct DEVICE *dev, int mc_cnt)
1453 {
1454 struct dev_mc_list *mcptr;
1455 u16 * addrptr;
1456 unsigned long ioaddr = dev->base_addr+0xc0; /* ID Table */
1457 u32 hash_val;
1458 u16 i, hash_table[4];
1459
1460 DMFE_DBUG(0, "dm9132_id_table()", 0);
1461
1462 /* Node address */
1463 addrptr = (u16 *) dev->dev_addr;
1464 outw(addrptr[0], ioaddr);
1465 ioaddr += 4;
1466 outw(addrptr[1], ioaddr);
1467 ioaddr += 4;
1468 outw(addrptr[2], ioaddr);
1469 ioaddr += 4;
1470
1471 /* Clear Hash Table */
1472 for (i = 0; i < 4; i++)
1473 hash_table[i] = 0x0;
1474
1475 /* broadcast address */
1476 hash_table[3] = 0x8000;
1477
1478 /* the multicast address in Hash Table : 64 bits */
1479 for (mcptr = dev->mc_list, i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
1480 hash_val = cal_CRC( (char *) mcptr->dmi_addr, 6, 0) & 0x3f;
1481 hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16);
1482 }
1483
1484 /* Write the hash table to MAC MD table */
1485 for (i = 0; i < 4; i++, ioaddr += 4)
1486 outw(hash_table[i], ioaddr);
1487 }
1488
1489
1490 /*
1491 * Send a setup frame for DM9102/DM9102A
1492 * This setup frame initilize DM910X address filter mode
1493 */
1494
1495 static void send_filter_frame(struct DEVICE *dev, int mc_cnt)
1496 {
1497 struct dmfe_board_info *db = netdev_priv(dev);
1498 struct dev_mc_list *mcptr;
1499 struct tx_desc *txptr;
1500 u16 * addrptr;
1501 u32 * suptr;
1502 int i;
1503
1504 DMFE_DBUG(0, "send_filter_frame()", 0);
1505
1506 txptr = db->tx_insert_ptr;
1507 suptr = (u32 *) txptr->tx_buf_ptr;
1508
1509 /* Node address */
1510 addrptr = (u16 *) dev->dev_addr;
1511 *suptr++ = addrptr[0];
1512 *suptr++ = addrptr[1];
1513 *suptr++ = addrptr[2];
1514
1515 /* broadcast address */
1516 *suptr++ = 0xffff;
1517 *suptr++ = 0xffff;
1518 *suptr++ = 0xffff;
1519
1520 /* fit the multicast address */
1521 for (mcptr = dev->mc_list, i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
1522 addrptr = (u16 *) mcptr->dmi_addr;
1523 *suptr++ = addrptr[0];
1524 *suptr++ = addrptr[1];
1525 *suptr++ = addrptr[2];
1526 }
1527
1528 for (; i<14; i++) {
1529 *suptr++ = 0xffff;
1530 *suptr++ = 0xffff;
1531 *suptr++ = 0xffff;
1532 }
1533
1534 /* prepare the setup frame */
1535 db->tx_insert_ptr = txptr->next_tx_desc;
1536 txptr->tdes1 = cpu_to_le32(0x890000c0);
1537
1538 /* Resource Check and Send the setup packet */
1539 if (!db->tx_packet_cnt) {
1540 /* Resource Empty */
1541 db->tx_packet_cnt++;
1542 txptr->tdes0 = cpu_to_le32(0x80000000);
1543 update_cr6(db->cr6_data | 0x2000, dev->base_addr);
1544 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
1545 update_cr6(db->cr6_data, dev->base_addr);
1546 dev->trans_start = jiffies;
1547 } else
1548 db->tx_queue_cnt++; /* Put in TX queue */
1549 }
1550
1551
1552 /*
1553 * Allocate rx buffer,
1554 * As possible as allocate maxiumn Rx buffer
1555 */
1556
1557 static void allocate_rx_buffer(struct dmfe_board_info *db)
1558 {
1559 struct rx_desc *rxptr;
1560 struct sk_buff *skb;
1561
1562 rxptr = db->rx_insert_ptr;
1563
1564 while(db->rx_avail_cnt < RX_DESC_CNT) {
1565 if ( ( skb = dev_alloc_skb(RX_ALLOC_SIZE) ) == NULL )
1566 break;
1567 rxptr->rx_skb_ptr = skb; /* FIXME (?) */
1568 rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev, skb->data,
1569 RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) );
1570 wmb();
1571 rxptr->rdes0 = cpu_to_le32(0x80000000);
1572 rxptr = rxptr->next_rx_desc;
1573 db->rx_avail_cnt++;
1574 }
1575
1576 db->rx_insert_ptr = rxptr;
1577 }
1578
1579
1580 /*
1581 * Read one word data from the serial ROM
1582 */
1583
1584 static u16 read_srom_word(long ioaddr, int offset)
1585 {
1586 int i;
1587 u16 srom_data = 0;
1588 long cr9_ioaddr = ioaddr + DCR9;
1589
1590 outl(CR9_SROM_READ, cr9_ioaddr);
1591 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1592
1593 /* Send the Read Command 110b */
1594 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1595 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1596 SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
1597
1598 /* Send the offset */
1599 for (i = 5; i >= 0; i--) {
1600 srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
1601 SROM_CLK_WRITE(srom_data, cr9_ioaddr);
1602 }
1603
1604 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1605
1606 for (i = 16; i > 0; i--) {
1607 outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
1608 udelay(5);
1609 srom_data = (srom_data << 1) |
1610 ((inl(cr9_ioaddr) & CR9_CRDOUT) ? 1 : 0);
1611 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1612 udelay(5);
1613 }
1614
1615 outl(CR9_SROM_READ, cr9_ioaddr);
1616 return srom_data;
1617 }
1618
1619
1620 /*
1621 * Auto sense the media mode
1622 */
1623
1624 static u8 dmfe_sense_speed(struct dmfe_board_info * db)
1625 {
1626 u8 ErrFlag = 0;
1627 u16 phy_mode;
1628
1629 /* CR6 bit18=0, select 10/100M */
1630 update_cr6( (db->cr6_data & ~0x40000), db->ioaddr);
1631
1632 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1633 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1634
1635 if ( (phy_mode & 0x24) == 0x24 ) {
1636 if (db->chip_id == PCI_DM9132_ID) /* DM9132 */
1637 phy_mode = phy_read(db->ioaddr,
1638 db->phy_addr, 7, db->chip_id) & 0xf000;
1639 else /* DM9102/DM9102A */
1640 phy_mode = phy_read(db->ioaddr,
1641 db->phy_addr, 17, db->chip_id) & 0xf000;
1642 /* printk(DRV_NAME ": Phy_mode %x ",phy_mode); */
1643 switch (phy_mode) {
1644 case 0x1000: db->op_mode = DMFE_10MHF; break;
1645 case 0x2000: db->op_mode = DMFE_10MFD; break;
1646 case 0x4000: db->op_mode = DMFE_100MHF; break;
1647 case 0x8000: db->op_mode = DMFE_100MFD; break;
1648 default: db->op_mode = DMFE_10MHF;
1649 ErrFlag = 1;
1650 break;
1651 }
1652 } else {
1653 db->op_mode = DMFE_10MHF;
1654 DMFE_DBUG(0, "Link Failed :", phy_mode);
1655 ErrFlag = 1;
1656 }
1657
1658 return ErrFlag;
1659 }
1660
1661
1662 /*
1663 * Set 10/100 phyxcer capability
1664 * AUTO mode : phyxcer register4 is NIC capability
1665 * Force mode: phyxcer register4 is the force media
1666 */
1667
1668 static void dmfe_set_phyxcer(struct dmfe_board_info *db)
1669 {
1670 u16 phy_reg;
1671
1672 /* Select 10/100M phyxcer */
1673 db->cr6_data &= ~0x40000;
1674 update_cr6(db->cr6_data, db->ioaddr);
1675
1676 /* DM9009 Chip: Phyxcer reg18 bit12=0 */
1677 if (db->chip_id == PCI_DM9009_ID) {
1678 phy_reg = phy_read(db->ioaddr,
1679 db->phy_addr, 18, db->chip_id) & ~0x1000;
1680
1681 phy_write(db->ioaddr,
1682 db->phy_addr, 18, phy_reg, db->chip_id);
1683 }
1684
1685 /* Phyxcer capability setting */
1686 phy_reg = phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0;
1687
1688 if (db->media_mode & DMFE_AUTO) {
1689 /* AUTO Mode */
1690 phy_reg |= db->PHY_reg4;
1691 } else {
1692 /* Force Mode */
1693 switch(db->media_mode) {
1694 case DMFE_10MHF: phy_reg |= 0x20; break;
1695 case DMFE_10MFD: phy_reg |= 0x40; break;
1696 case DMFE_100MHF: phy_reg |= 0x80; break;
1697 case DMFE_100MFD: phy_reg |= 0x100; break;
1698 }
1699 if (db->chip_id == PCI_DM9009_ID) phy_reg &= 0x61;
1700 }
1701
1702 /* Write new capability to Phyxcer Reg4 */
1703 if ( !(phy_reg & 0x01e0)) {
1704 phy_reg|=db->PHY_reg4;
1705 db->media_mode|=DMFE_AUTO;
1706 }
1707 phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
1708
1709 /* Restart Auto-Negotiation */
1710 if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
1711 phy_write(db->ioaddr, db->phy_addr, 0, 0x1800, db->chip_id);
1712 if ( !db->chip_type )
1713 phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
1714 }
1715
1716
1717 /*
1718 * Process op-mode
1719 * AUTO mode : PHY controller in Auto-negotiation Mode
1720 * Force mode: PHY controller in force mode with HUB
1721 * N-way force capability with SWITCH
1722 */
1723
1724 static void dmfe_process_mode(struct dmfe_board_info *db)
1725 {
1726 u16 phy_reg;
1727
1728 /* Full Duplex Mode Check */
1729 if (db->op_mode & 0x4)
1730 db->cr6_data |= CR6_FDM; /* Set Full Duplex Bit */
1731 else
1732 db->cr6_data &= ~CR6_FDM; /* Clear Full Duplex Bit */
1733
1734 /* Transciver Selection */
1735 if (db->op_mode & 0x10) /* 1M HomePNA */
1736 db->cr6_data |= 0x40000;/* External MII select */
1737 else
1738 db->cr6_data &= ~0x40000;/* Internal 10/100 transciver */
1739
1740 update_cr6(db->cr6_data, db->ioaddr);
1741
1742 /* 10/100M phyxcer force mode need */
1743 if ( !(db->media_mode & 0x18)) {
1744 /* Forece Mode */
1745 phy_reg = phy_read(db->ioaddr, db->phy_addr, 6, db->chip_id);
1746 if ( !(phy_reg & 0x1) ) {
1747 /* parter without N-Way capability */
1748 phy_reg = 0x0;
1749 switch(db->op_mode) {
1750 case DMFE_10MHF: phy_reg = 0x0; break;
1751 case DMFE_10MFD: phy_reg = 0x100; break;
1752 case DMFE_100MHF: phy_reg = 0x2000; break;
1753 case DMFE_100MFD: phy_reg = 0x2100; break;
1754 }
1755 phy_write(db->ioaddr,
1756 db->phy_addr, 0, phy_reg, db->chip_id);
1757 if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
1758 mdelay(20);
1759 phy_write(db->ioaddr,
1760 db->phy_addr, 0, phy_reg, db->chip_id);
1761 }
1762 }
1763 }
1764
1765
1766 /*
1767 * Write a word to Phy register
1768 */
1769
1770 static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset,
1771 u16 phy_data, u32 chip_id)
1772 {
1773 u16 i;
1774 unsigned long ioaddr;
1775
1776 if (chip_id == PCI_DM9132_ID) {
1777 ioaddr = iobase + 0x80 + offset * 4;
1778 outw(phy_data, ioaddr);
1779 } else {
1780 /* DM9102/DM9102A Chip */
1781 ioaddr = iobase + DCR9;
1782
1783 /* Send 33 synchronization clock to Phy controller */
1784 for (i = 0; i < 35; i++)
1785 phy_write_1bit(ioaddr, PHY_DATA_1);
1786
1787 /* Send start command(01) to Phy */
1788 phy_write_1bit(ioaddr, PHY_DATA_0);
1789 phy_write_1bit(ioaddr, PHY_DATA_1);
1790
1791 /* Send write command(01) to Phy */
1792 phy_write_1bit(ioaddr, PHY_DATA_0);
1793 phy_write_1bit(ioaddr, PHY_DATA_1);
1794
1795 /* Send Phy address */
1796 for (i = 0x10; i > 0; i = i >> 1)
1797 phy_write_1bit(ioaddr,
1798 phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1799
1800 /* Send register address */
1801 for (i = 0x10; i > 0; i = i >> 1)
1802 phy_write_1bit(ioaddr,
1803 offset & i ? PHY_DATA_1 : PHY_DATA_0);
1804
1805 /* written trasnition */
1806 phy_write_1bit(ioaddr, PHY_DATA_1);
1807 phy_write_1bit(ioaddr, PHY_DATA_0);
1808
1809 /* Write a word data to PHY controller */
1810 for ( i = 0x8000; i > 0; i >>= 1)
1811 phy_write_1bit(ioaddr,
1812 phy_data & i ? PHY_DATA_1 : PHY_DATA_0);
1813 }
1814 }
1815
1816
1817 /*
1818 * Read a word data from phy register
1819 */
1820
1821 static u16 phy_read(unsigned long iobase, u8 phy_addr, u8 offset, u32 chip_id)
1822 {
1823 int i;
1824 u16 phy_data;
1825 unsigned long ioaddr;
1826
1827 if (chip_id == PCI_DM9132_ID) {
1828 /* DM9132 Chip */
1829 ioaddr = iobase + 0x80 + offset * 4;
1830 phy_data = inw(ioaddr);
1831 } else {
1832 /* DM9102/DM9102A Chip */
1833 ioaddr = iobase + DCR9;
1834
1835 /* Send 33 synchronization clock to Phy controller */
1836 for (i = 0; i < 35; i++)
1837 phy_write_1bit(ioaddr, PHY_DATA_1);
1838
1839 /* Send start command(01) to Phy */
1840 phy_write_1bit(ioaddr, PHY_DATA_0);
1841 phy_write_1bit(ioaddr, PHY_DATA_1);
1842
1843 /* Send read command(10) to Phy */
1844 phy_write_1bit(ioaddr, PHY_DATA_1);
1845 phy_write_1bit(ioaddr, PHY_DATA_0);
1846
1847 /* Send Phy address */
1848 for (i = 0x10; i > 0; i = i >> 1)
1849 phy_write_1bit(ioaddr,
1850 phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1851
1852 /* Send register address */
1853 for (i = 0x10; i > 0; i = i >> 1)
1854 phy_write_1bit(ioaddr,
1855 offset & i ? PHY_DATA_1 : PHY_DATA_0);
1856
1857 /* Skip transition state */
1858 phy_read_1bit(ioaddr);
1859
1860 /* read 16bit data */
1861 for (phy_data = 0, i = 0; i < 16; i++) {
1862 phy_data <<= 1;
1863 phy_data |= phy_read_1bit(ioaddr);
1864 }
1865 }
1866
1867 return phy_data;
1868 }
1869
1870
1871 /*
1872 * Write one bit data to Phy Controller
1873 */
1874
1875 static void phy_write_1bit(unsigned long ioaddr, u32 phy_data)
1876 {
1877 outl(phy_data, ioaddr); /* MII Clock Low */
1878 udelay(1);
1879 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */
1880 udelay(1);
1881 outl(phy_data, ioaddr); /* MII Clock Low */
1882 udelay(1);
1883 }
1884
1885
1886 /*
1887 * Read one bit phy data from PHY controller
1888 */
1889
1890 static u16 phy_read_1bit(unsigned long ioaddr)
1891 {
1892 u16 phy_data;
1893
1894 outl(0x50000, ioaddr);
1895 udelay(1);
1896 phy_data = ( inl(ioaddr) >> 19 ) & 0x1;
1897 outl(0x40000, ioaddr);
1898 udelay(1);
1899
1900 return phy_data;
1901 }
1902
1903
1904 /*
1905 * Parser SROM and media mode
1906 */
1907
1908 static void dmfe_parse_srom(struct dmfe_board_info * db)
1909 {
1910 char * srom = db->srom;
1911 int dmfe_mode, tmp_reg;
1912
1913 DMFE_DBUG(0, "dmfe_parse_srom() ", 0);
1914
1915 /* Init CR15 */
1916 db->cr15_data = CR15_DEFAULT;
1917
1918 /* Check SROM Version */
1919 if ( ( (int) srom[18] & 0xff) == SROM_V41_CODE) {
1920 /* SROM V4.01 */
1921 /* Get NIC support media mode */
1922 db->NIC_capability = le16_to_cpup((__le16 *) (srom + 34));
1923 db->PHY_reg4 = 0;
1924 for (tmp_reg = 1; tmp_reg < 0x10; tmp_reg <<= 1) {
1925 switch( db->NIC_capability & tmp_reg ) {
1926 case 0x1: db->PHY_reg4 |= 0x0020; break;
1927 case 0x2: db->PHY_reg4 |= 0x0040; break;
1928 case 0x4: db->PHY_reg4 |= 0x0080; break;
1929 case 0x8: db->PHY_reg4 |= 0x0100; break;
1930 }
1931 }
1932
1933 /* Media Mode Force or not check */
1934 dmfe_mode = (le32_to_cpup((__le32 *) (srom + 34)) &
1935 le32_to_cpup((__le32 *) (srom + 36)));
1936 switch(dmfe_mode) {
1937 case 0x4: dmfe_media_mode = DMFE_100MHF; break; /* 100MHF */
1938 case 0x2: dmfe_media_mode = DMFE_10MFD; break; /* 10MFD */
1939 case 0x8: dmfe_media_mode = DMFE_100MFD; break; /* 100MFD */
1940 case 0x100:
1941 case 0x200: dmfe_media_mode = DMFE_1M_HPNA; break;/* HomePNA */
1942 }
1943
1944 /* Special Function setting */
1945 /* VLAN function */
1946 if ( (SF_mode & 0x1) || (srom[43] & 0x80) )
1947 db->cr15_data |= 0x40;
1948
1949 /* Flow Control */
1950 if ( (SF_mode & 0x2) || (srom[40] & 0x1) )
1951 db->cr15_data |= 0x400;
1952
1953 /* TX pause packet */
1954 if ( (SF_mode & 0x4) || (srom[40] & 0xe) )
1955 db->cr15_data |= 0x9800;
1956 }
1957
1958 /* Parse HPNA parameter */
1959 db->HPNA_command = 1;
1960
1961 /* Accept remote command or not */
1962 if (HPNA_rx_cmd == 0)
1963 db->HPNA_command |= 0x8000;
1964
1965 /* Issue remote command & operation mode */
1966 if (HPNA_tx_cmd == 1)
1967 switch(HPNA_mode) { /* Issue Remote Command */
1968 case 0: db->HPNA_command |= 0x0904; break;
1969 case 1: db->HPNA_command |= 0x0a00; break;
1970 case 2: db->HPNA_command |= 0x0506; break;
1971 case 3: db->HPNA_command |= 0x0602; break;
1972 }
1973 else
1974 switch(HPNA_mode) { /* Don't Issue */
1975 case 0: db->HPNA_command |= 0x0004; break;
1976 case 1: db->HPNA_command |= 0x0000; break;
1977 case 2: db->HPNA_command |= 0x0006; break;
1978 case 3: db->HPNA_command |= 0x0002; break;
1979 }
1980
1981 /* Check DM9801 or DM9802 present or not */
1982 db->HPNA_present = 0;
1983 update_cr6(db->cr6_data|0x40000, db->ioaddr);
1984 tmp_reg = phy_read(db->ioaddr, db->phy_addr, 3, db->chip_id);
1985 if ( ( tmp_reg & 0xfff0 ) == 0xb900 ) {
1986 /* DM9801 or DM9802 present */
1987 db->HPNA_timer = 8;
1988 if ( phy_read(db->ioaddr, db->phy_addr, 31, db->chip_id) == 0x4404) {
1989 /* DM9801 HomeRun */
1990 db->HPNA_present = 1;
1991 dmfe_program_DM9801(db, tmp_reg);
1992 } else {
1993 /* DM9802 LongRun */
1994 db->HPNA_present = 2;
1995 dmfe_program_DM9802(db);
1996 }
1997 }
1998
1999 }
2000
2001
2002 /*
2003 * Init HomeRun DM9801
2004 */
2005
2006 static void dmfe_program_DM9801(struct dmfe_board_info * db, int HPNA_rev)
2007 {
2008 uint reg17, reg25;
2009
2010 if ( !HPNA_NoiseFloor ) HPNA_NoiseFloor = DM9801_NOISE_FLOOR;
2011 switch(HPNA_rev) {
2012 case 0xb900: /* DM9801 E3 */
2013 db->HPNA_command |= 0x1000;
2014 reg25 = phy_read(db->ioaddr, db->phy_addr, 24, db->chip_id);
2015 reg25 = ( (reg25 + HPNA_NoiseFloor) & 0xff) | 0xf000;
2016 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
2017 break;
2018 case 0xb901: /* DM9801 E4 */
2019 reg25 = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
2020 reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor;
2021 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
2022 reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor + 3;
2023 break;
2024 case 0xb902: /* DM9801 E5 */
2025 case 0xb903: /* DM9801 E6 */
2026 default:
2027 db->HPNA_command |= 0x1000;
2028 reg25 = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
2029 reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor - 5;
2030 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
2031 reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor;
2032 break;
2033 }
2034 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
2035 phy_write(db->ioaddr, db->phy_addr, 17, reg17, db->chip_id);
2036 phy_write(db->ioaddr, db->phy_addr, 25, reg25, db->chip_id);
2037 }
2038
2039
2040 /*
2041 * Init HomeRun DM9802
2042 */
2043
2044 static void dmfe_program_DM9802(struct dmfe_board_info * db)
2045 {
2046 uint phy_reg;
2047
2048 if ( !HPNA_NoiseFloor ) HPNA_NoiseFloor = DM9802_NOISE_FLOOR;
2049 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
2050 phy_reg = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
2051 phy_reg = ( phy_reg & 0xff00) + HPNA_NoiseFloor;
2052 phy_write(db->ioaddr, db->phy_addr, 25, phy_reg, db->chip_id);
2053 }
2054
2055
2056 /*
2057 * Check remote HPNA power and speed status. If not correct,
2058 * issue command again.
2059 */
2060
2061 static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * db)
2062 {
2063 uint phy_reg;
2064
2065 /* Got remote device status */
2066 phy_reg = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id) & 0x60;
2067 switch(phy_reg) {
2068 case 0x00: phy_reg = 0x0a00;break; /* LP/LS */
2069 case 0x20: phy_reg = 0x0900;break; /* LP/HS */
2070 case 0x40: phy_reg = 0x0600;break; /* HP/LS */
2071 case 0x60: phy_reg = 0x0500;break; /* HP/HS */
2072 }
2073
2074 /* Check remote device status match our setting ot not */
2075 if ( phy_reg != (db->HPNA_command & 0x0f00) ) {
2076 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command,
2077 db->chip_id);
2078 db->HPNA_timer=8;
2079 } else
2080 db->HPNA_timer=600; /* Match, every 10 minutes, check */
2081 }
2082
2083
2084
2085 static struct pci_device_id dmfe_pci_tbl[] = {
2086 { 0x1282, 0x9132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9132_ID },
2087 { 0x1282, 0x9102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9102_ID },
2088 { 0x1282, 0x9100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9100_ID },
2089 { 0x1282, 0x9009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9009_ID },
2090 { 0, }
2091 };
2092 MODULE_DEVICE_TABLE(pci, dmfe_pci_tbl);
2093
2094
2095 #ifdef CONFIG_PM
2096 static int dmfe_suspend(struct pci_dev *pci_dev, pm_message_t state)
2097 {
2098 struct net_device *dev = pci_get_drvdata(pci_dev);
2099 struct dmfe_board_info *db = netdev_priv(dev);
2100 u32 tmp;
2101
2102 /* Disable upper layer interface */
2103 netif_device_detach(dev);
2104
2105 /* Disable Tx/Rx */
2106 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC);
2107 update_cr6(db->cr6_data, dev->base_addr);
2108
2109 /* Disable Interrupt */
2110 outl(0, dev->base_addr + DCR7);
2111 outl(inl (dev->base_addr + DCR5), dev->base_addr + DCR5);
2112
2113 /* Fre RX buffers */
2114 dmfe_free_rxbuffer(db);
2115
2116 /* Enable WOL */
2117 pci_read_config_dword(pci_dev, 0x40, &tmp);
2118 tmp &= ~(DMFE_WOL_LINKCHANGE|DMFE_WOL_MAGICPACKET);
2119
2120 if (db->wol_mode & WAKE_PHY)
2121 tmp |= DMFE_WOL_LINKCHANGE;
2122 if (db->wol_mode & WAKE_MAGIC)
2123 tmp |= DMFE_WOL_MAGICPACKET;
2124
2125 pci_write_config_dword(pci_dev, 0x40, tmp);
2126
2127 pci_enable_wake(pci_dev, PCI_D3hot, 1);
2128 pci_enable_wake(pci_dev, PCI_D3cold, 1);
2129
2130 /* Power down device*/
2131 pci_save_state(pci_dev);
2132 pci_set_power_state(pci_dev, pci_choose_state (pci_dev, state));
2133
2134 return 0;
2135 }
2136
2137 static int dmfe_resume(struct pci_dev *pci_dev)
2138 {
2139 struct net_device *dev = pci_get_drvdata(pci_dev);
2140 u32 tmp;
2141
2142 pci_set_power_state(pci_dev, PCI_D0);
2143 pci_restore_state(pci_dev);
2144
2145 /* Re-initilize DM910X board */
2146 dmfe_init_dm910x(dev);
2147
2148 /* Disable WOL */
2149 pci_read_config_dword(pci_dev, 0x40, &tmp);
2150
2151 tmp &= ~(DMFE_WOL_LINKCHANGE | DMFE_WOL_MAGICPACKET);
2152 pci_write_config_dword(pci_dev, 0x40, tmp);
2153
2154 pci_enable_wake(pci_dev, PCI_D3hot, 0);
2155 pci_enable_wake(pci_dev, PCI_D3cold, 0);
2156
2157 /* Restart upper layer interface */
2158 netif_device_attach(dev);
2159
2160 return 0;
2161 }
2162 #else
2163 #define dmfe_suspend NULL
2164 #define dmfe_resume NULL
2165 #endif
2166
2167 static struct pci_driver dmfe_driver = {
2168 .name = "dmfe",
2169 .id_table = dmfe_pci_tbl,
2170 .probe = dmfe_init_one,
2171 .remove = __devexit_p(dmfe_remove_one),
2172 .suspend = dmfe_suspend,
2173 .resume = dmfe_resume
2174 };
2175
2176 MODULE_AUTHOR("Sten Wang, sten_wang@davicom.com.tw");
2177 MODULE_DESCRIPTION("Davicom DM910X fast ethernet driver");
2178 MODULE_LICENSE("GPL");
2179 MODULE_VERSION(DRV_VERSION);
2180
2181 module_param(debug, int, 0);
2182 module_param(mode, byte, 0);
2183 module_param(cr6set, int, 0);
2184 module_param(chkmode, byte, 0);
2185 module_param(HPNA_mode, byte, 0);
2186 module_param(HPNA_rx_cmd, byte, 0);
2187 module_param(HPNA_tx_cmd, byte, 0);
2188 module_param(HPNA_NoiseFloor, byte, 0);
2189 module_param(SF_mode, byte, 0);
2190 MODULE_PARM_DESC(debug, "Davicom DM9xxx enable debugging (0-1)");
2191 MODULE_PARM_DESC(mode, "Davicom DM9xxx: "
2192 "Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA");
2193
2194 MODULE_PARM_DESC(SF_mode, "Davicom DM9xxx special function "
2195 "(bit 0: VLAN, bit 1 Flow Control, bit 2: TX pause packet)");
2196
2197 /* Description:
2198 * when user used insmod to add module, system invoked init_module()
2199 * to initilize and register.
2200 */
2201
2202 static int __init dmfe_init_module(void)
2203 {
2204 int rc;
2205
2206 printk(version);
2207 printed_version = 1;
2208
2209 DMFE_DBUG(0, "init_module() ", debug);
2210
2211 if (debug)
2212 dmfe_debug = debug; /* set debug flag */
2213 if (cr6set)
2214 dmfe_cr6_user_set = cr6set;
2215
2216 switch(mode) {
2217 case DMFE_10MHF:
2218 case DMFE_100MHF:
2219 case DMFE_10MFD:
2220 case DMFE_100MFD:
2221 case DMFE_1M_HPNA:
2222 dmfe_media_mode = mode;
2223 break;
2224 default:dmfe_media_mode = DMFE_AUTO;
2225 break;
2226 }
2227
2228 if (HPNA_mode > 4)
2229 HPNA_mode = 0; /* Default: LP/HS */
2230 if (HPNA_rx_cmd > 1)
2231 HPNA_rx_cmd = 0; /* Default: Ignored remote cmd */
2232 if (HPNA_tx_cmd > 1)
2233 HPNA_tx_cmd = 0; /* Default: Don't issue remote cmd */
2234 if (HPNA_NoiseFloor > 15)
2235 HPNA_NoiseFloor = 0;
2236
2237 rc = pci_register_driver(&dmfe_driver);
2238 if (rc < 0)
2239 return rc;
2240
2241 return 0;
2242 }
2243
2244
2245 /*
2246 * Description:
2247 * when user used rmmod to delete module, system invoked clean_module()
2248 * to un-register all registered services.
2249 */
2250
2251 static void __exit dmfe_cleanup_module(void)
2252 {
2253 DMFE_DBUG(0, "dmfe_clean_module() ", debug);
2254 pci_unregister_driver(&dmfe_driver);
2255 }
2256
2257 module_init(dmfe_init_module);
2258 module_exit(dmfe_cleanup_module);
Linux kernel - Deliverables
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