drivers/net/tulip/tulip.h

   1 /*
   2         drivers/net/tulip/tulip.h
   3
   4         Copyright 2000,2001  The Linux Kernel Team
   5         Written/copyright 1994-2001 by Donald Becker.
   6
   7         This software may be used and distributed according to the terms
   8         of the GNU General Public License, incorporated herein by reference.
   9
  10         Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html}
  11         for more information on this driver, or visit the project
  12         Web page at http://sourceforge.net/projects/tulip/
  13
  14 */
  15
  16 #ifndef __NET_TULIP_H__
  17 #define __NET_TULIP_H__
  18
  19 #include <linux/kernel.h>
  20 #include <linux/types.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/netdevice.h>
  23 #include <linux/timer.h>
  24 #include <linux/delay.h>
  25 #include <linux/pci.h>
  26 #include <asm/io.h>
  27 #include <asm/irq.h>
  28
  29
  30
  31 /* undefine, or define to various debugging levels (>4 == obscene levels) */
  32 #define TULIP_DEBUG 1
  33
  34 #ifdef CONFIG_TULIP_MMIO
  35 #define TULIP_BAR       1       /* CBMA */
  36 #else
  37 #define TULIP_BAR       0       /* CBIO */
  38 #endif
  39
  40
  41
  42 struct tulip_chip_table {
  43         char *chip_name;
  44         int io_size;
  45         int valid_intrs;        /* CSR7 interrupt enable settings */
  46         int flags;
  47         void (*media_timer) (unsigned long);
  48         work_func_t media_task;
  49 };
  50
  51
  52 enum tbl_flag {
  53         HAS_MII                 = 0x0001,
  54         HAS_MEDIA_TABLE         = 0x0002,
  55         CSR12_IN_SROM           = 0x0004,
  56         ALWAYS_CHECK_MII        = 0x0008,
  57         HAS_ACPI                = 0x0010,
  58         MC_HASH_ONLY            = 0x0020, /* Hash-only multicast filter. */
  59         HAS_PNICNWAY            = 0x0080,
  60         HAS_NWAY                = 0x0040, /* Uses internal NWay xcvr. */
  61         HAS_INTR_MITIGATION     = 0x0100,
  62         IS_ASIX                 = 0x0200,
  63         HAS_8023X               = 0x0400,
  64         COMET_MAC_ADDR          = 0x0800,
  65         HAS_PCI_MWI             = 0x1000,
  66         HAS_PHY_IRQ             = 0x2000,
  67         HAS_SWAPPED_SEEPROM     = 0x4000,
  68         NEEDS_FAKE_MEDIA_TABLE  = 0x8000,
  69 };
  70
  71
  72 /* chip types.  careful!  order is VERY IMPORTANT here, as these
  73  * are used throughout the driver as indices into arrays */
  74 /* Note 21142 == 21143. */
  75 enum chips {
  76         DC21040 = 0,
  77         DC21041 = 1,
  78         DC21140 = 2,
  79         DC21142 = 3, DC21143 = 3,
  80         LC82C168,
  81         MX98713,
  82         MX98715,
  83         MX98725,
  84         AX88140,
  85         PNIC2,
  86         COMET,
  87         COMPEX9881,
  88         I21145,
  89         DM910X,
  90         CONEXANT,
  91 };
  92
  93
  94 enum MediaIs {
  95         MediaIsFD = 1,
  96         MediaAlwaysFD = 2,
  97         MediaIsMII = 4,
  98         MediaIsFx = 8,
  99         MediaIs100 = 16
 100 };
 101
 102
 103 /* Offsets to the Command and Status Registers, "CSRs".  All accesses
 104    must be longword instructions and quadword aligned. */
 105 enum tulip_offsets {
 106         CSR0 = 0,
 107         CSR1 = 0x08,
 108         CSR2 = 0x10,
 109         CSR3 = 0x18,
 110         CSR4 = 0x20,
 111         CSR5 = 0x28,
 112         CSR6 = 0x30,
 113         CSR7 = 0x38,
 114         CSR8 = 0x40,
 115         CSR9 = 0x48,
 116         CSR10 = 0x50,
 117         CSR11 = 0x58,
 118         CSR12 = 0x60,
 119         CSR13 = 0x68,
 120         CSR14 = 0x70,
 121         CSR15 = 0x78,
 122 };
 123
 124 /* register offset and bits for CFDD PCI config reg */
 125 enum pci_cfg_driver_reg {
 126         CFDD = 0x40,
 127         CFDD_Sleep = (1 << 31),
 128         CFDD_Snooze = (1 << 30),
 129 };
 130
 131 #define RxPollInt (RxIntr|RxNoBuf|RxDied|RxJabber)
 132
 133 /* The bits in the CSR5 status registers, mostly interrupt sources. */
 134 enum status_bits {
 135         TimerInt = 0x800,
 136         SystemError = 0x2000,
 137         TPLnkFail = 0x1000,
 138         TPLnkPass = 0x10,
 139         NormalIntr = 0x10000,
 140         AbnormalIntr = 0x8000,
 141         RxJabber = 0x200,
 142         RxDied = 0x100,
 143         RxNoBuf = 0x80,
 144         RxIntr = 0x40,
 145         TxFIFOUnderflow = 0x20,
 146         RxErrIntr = 0x10,
 147         TxJabber = 0x08,
 148         TxNoBuf = 0x04,
 149         TxDied = 0x02,
 150         TxIntr = 0x01,
 151 };
 152
 153 /* bit mask for CSR5 TX/RX process state */
 154 #define CSR5_TS 0x00700000
 155 #define CSR5_RS 0x000e0000
 156
 157 enum tulip_mode_bits {
 158         TxThreshold             = (1 << 22),
 159         FullDuplex              = (1 << 9),
 160         TxOn                    = 0x2000,
 161         AcceptBroadcast         = 0x0100,
 162         AcceptAllMulticast      = 0x0080,
 163         AcceptAllPhys           = 0x0040,
 164         AcceptRunt              = 0x0008,
 165         RxOn                    = 0x0002,
 166         RxTx                    = (TxOn | RxOn),
 167 };
 168
 169
 170 enum tulip_busconfig_bits {
 171         MWI                     = (1 << 24),
 172         MRL                     = (1 << 23),
 173         MRM                     = (1 << 21),
 174         CALShift                = 14,
 175         BurstLenShift           = 8,
 176 };
 177
 178
 179 /* The Tulip Rx and Tx buffer descriptors. */
 180 struct tulip_rx_desc {
 181         __le32 status;
 182         __le32 length;
 183         __le32 buffer1;
 184         __le32 buffer2;
 185 };
 186
 187
 188 struct tulip_tx_desc {
 189         __le32 status;
 190         __le32 length;
 191         __le32 buffer1;
 192         __le32 buffer2;         /* We use only buffer 1.  */
 193 };
 194
 195
 196 enum desc_status_bits {
 197         DescOwned    = 0x80000000,
 198         DescWholePkt = 0x60000000,
 199         DescEndPkt   = 0x40000000,
 200         DescStartPkt = 0x20000000,
 201         DescEndRing  = 0x02000000,
 202         DescUseLink  = 0x01000000,
 203         RxDescFatalErr = 0x008000,
 204         RxWholePkt   = 0x00000300,
 205 };
 206
 207
 208 enum t21143_csr6_bits {
 209         csr6_sc = (1<<31),
 210         csr6_ra = (1<<30),
 211         csr6_ign_dest_msb = (1<<26),
 212         csr6_mbo = (1<<25),
 213         csr6_scr = (1<<24),  /* scramble mode flag: can't be set */
 214         csr6_pcs = (1<<23),  /* Enables PCS functions (symbol mode requires csr6_ps be set) default is set */
 215         csr6_ttm = (1<<22),  /* Transmit Threshold Mode, set for 10baseT, 0 for 100BaseTX */
 216         csr6_sf = (1<<21),   /* Store and forward. If set ignores TR bits */
 217         csr6_hbd = (1<<19),  /* Heart beat disable. Disables SQE function in 10baseT */
 218         csr6_ps = (1<<18),   /* Port Select. 0 (defualt) = 10baseT, 1 = 100baseTX: can't be set */
 219         csr6_ca = (1<<17),   /* Collision Offset Enable. If set uses special algorithm in low collision situations */
 220         csr6_trh = (1<<15),  /* Transmit Threshold high bit */
 221         csr6_trl = (1<<14),  /* Transmit Threshold low bit */
 222
 223         /***************************************************************
 224          * This table shows transmit threshold values based on media   *
 225          * and these two registers (from PNIC1 & 2 docs) Note: this is *
 226          * all meaningless if sf is set.                               *
 227          ***************************************************************/
 228
 229         /***********************************
 230          * (trh,trl) * 100BaseTX * 10BaseT *
 231          ***********************************
 232          *   (0,0)   *     128   *    72   *
 233          *   (0,1)   *     256   *    96   *
 234          *   (1,0)   *     512   *   128   *
 235          *   (1,1)   *    1024   *   160   *
 236          ***********************************/
 237
 238         csr6_fc = (1<<12),   /* Forces a collision in next transmission (for testing in loopback mode) */
 239         csr6_om_int_loop = (1<<10), /* internal (FIFO) loopback flag */
 240         csr6_om_ext_loop = (1<<11), /* external (PMD) loopback flag */
 241         /* set both and you get (PHY) loopback */
 242         csr6_fd = (1<<9),    /* Full duplex mode, disables hearbeat, no loopback */
 243         csr6_pm = (1<<7),    /* Pass All Multicast */
 244         csr6_pr = (1<<6),    /* Promiscuous mode */
 245         csr6_sb = (1<<5),    /* Start(1)/Stop(0) backoff counter */
 246         csr6_if = (1<<4),    /* Inverse Filtering, rejects only addresses in address table: can't be set */
 247         csr6_pb = (1<<3),    /* Pass Bad Frames, (1) causes even bad frames to be passed on */
 248         csr6_ho = (1<<2),    /* Hash-only filtering mode: can't be set */
 249         csr6_hp = (1<<0),    /* Hash/Perfect Receive Filtering Mode: can't be set */
 250
 251         csr6_mask_capture = (csr6_sc | csr6_ca),
 252         csr6_mask_defstate = (csr6_mask_capture | csr6_mbo),
 253         csr6_mask_hdcap = (csr6_mask_defstate | csr6_hbd | csr6_ps),
 254         csr6_mask_hdcaptt = (csr6_mask_hdcap  | csr6_trh | csr6_trl),
 255         csr6_mask_fullcap = (csr6_mask_hdcaptt | csr6_fd),
 256         csr6_mask_fullpromisc = (csr6_pr | csr6_pm),
 257         csr6_mask_filters = (csr6_hp | csr6_ho | csr6_if),
 258         csr6_mask_100bt = (csr6_scr | csr6_pcs | csr6_hbd),
 259 };
 260
 261
 262 /* Keep the ring sizes a power of two for efficiency.
 263    Making the Tx ring too large decreases the effectiveness of channel
 264    bonding and packet priority.
 265    There are no ill effects from too-large receive rings. */
 266
 267 #define TX_RING_SIZE    32
 268 #define RX_RING_SIZE    128
 269 #define MEDIA_MASK     31
 270
 271 /* The receiver on the DC21143 rev 65 can fail to close the last
 272  * receive descriptor in certain circumstances (see errata) when
 273  * using MWI. This can only occur if the receive buffer ends on
 274  * a cache line boundary, so the "+ 4" below ensures it doesn't.
 275  */
 276 #define PKT_BUF_SZ      (1536 + 4)      /* Size of each temporary Rx buffer. */
 277
 278 #define TULIP_MIN_CACHE_LINE    8       /* in units of 32-bit words */
 279
 280 #if defined(__sparc__) || defined(__hppa__)
 281 /* The UltraSparc PCI controllers will disconnect at every 64-byte
 282  * crossing anyways so it makes no sense to tell Tulip to burst
 283  * any more than that.
 284  */
 285 #define TULIP_MAX_CACHE_LINE    16      /* in units of 32-bit words */
 286 #else
 287 #define TULIP_MAX_CACHE_LINE    32      /* in units of 32-bit words */
 288 #endif
 289
 290
 291 /* Ring-wrap flag in length field, use for last ring entry.
 292         0x01000000 means chain on buffer2 address,
 293         0x02000000 means use the ring start address in CSR2/3.
 294    Note: Some work-alike chips do not function correctly in chained mode.
 295    The ASIX chip works only in chained mode.
 296    Thus we indicates ring mode, but always write the 'next' field for
 297    chained mode as well.
 298 */
 299 #define DESC_RING_WRAP 0x02000000
 300
 301
 302 #define EEPROM_SIZE 512         /* 2 << EEPROM_ADDRLEN */
 303
 304
 305 #define RUN_AT(x) (jiffies + (x))
 306
 307 #if defined(__i386__)                   /* AKA get_unaligned() */
 308 #define get_u16(ptr) (*(u16 *)(ptr))
 309 #else
 310 #define get_u16(ptr) (((u8*)(ptr))[0] + (((u8*)(ptr))[1]<<8))
 311 #endif
 312
 313 struct medialeaf {
 314         u8 type;
 315         u8 media;
 316         unsigned char *leafdata;
 317 };
 318
 319
 320 struct mediatable {
 321         u16 defaultmedia;
 322         u8 leafcount;
 323         u8 csr12dir;            /* General purpose pin directions. */
 324         unsigned has_mii:1;
 325         unsigned has_nonmii:1;
 326         unsigned has_reset:6;
 327         u32 csr15dir;
 328         u32 csr15val;           /* 21143 NWay setting. */
 329         struct medialeaf mleaf[0];
 330 };
 331
 332
 333 struct mediainfo {
 334         struct mediainfo *next;
 335         int info_type;
 336         int index;
 337         unsigned char *info;
 338 };
 339
 340 struct ring_info {
 341         struct sk_buff  *skb;
 342         dma_addr_t      mapping;
 343 };
 344
 345
 346 struct tulip_private {
 347         const char *product_name;
 348         struct net_device *next_module;
 349         struct tulip_rx_desc *rx_ring;
 350         struct tulip_tx_desc *tx_ring;
 351         dma_addr_t rx_ring_dma;
 352         dma_addr_t tx_ring_dma;
 353         /* The saved address of a sent-in-place packet/buffer, for skfree(). */
 354         struct ring_info tx_buffers[TX_RING_SIZE];
 355         /* The addresses of receive-in-place skbuffs. */
 356         struct ring_info rx_buffers[RX_RING_SIZE];
 357         u16 setup_frame[96];    /* Pseudo-Tx frame to init address table. */
 358         int chip_id;
 359         int revision;
 360         int flags;
 361         struct napi_struct napi;
 362         struct net_device_stats stats;
 363         struct timer_list timer;        /* Media selection timer. */
 364         struct timer_list oom_timer;    /* Out of memory timer. */
 365         u32 mc_filter[2];
 366         spinlock_t lock;
 367         spinlock_t mii_lock;
 368         unsigned int cur_rx, cur_tx;    /* The next free ring entry */
 369         unsigned int dirty_rx, dirty_tx;        /* The ring entries to be free()ed. */
 370
 371 #ifdef  CONFIG_TULIP_NAPI_HW_MITIGATION
 372         int mit_on;
 373 #endif
 374         unsigned int full_duplex:1;     /* Full-duplex operation requested. */
 375         unsigned int full_duplex_lock:1;
 376         unsigned int fake_addr:1;       /* Multiport board faked address. */
 377         unsigned int default_port:4;    /* Last dev->if_port value. */
 378         unsigned int media2:4;  /* Secondary monitored media port. */
 379         unsigned int medialock:1;       /* Don't sense media type. */
 380         unsigned int mediasense:1;      /* Media sensing in progress. */
 381         unsigned int nway:1, nwayset:1;         /* 21143 internal NWay. */
 382         unsigned int timeout_recovery:1;
 383         unsigned int csr0;      /* CSR0 setting. */
 384         unsigned int csr6;      /* Current CSR6 control settings. */
 385         unsigned char eeprom[EEPROM_SIZE];      /* Serial EEPROM contents. */
 386         void (*link_change) (struct net_device * dev, int csr5);
 387         u16 sym_advertise, mii_advertise; /* NWay capabilities advertised.  */
 388         u16 lpar;               /* 21143 Link partner ability. */
 389         u16 advertising[4];
 390         signed char phys[4], mii_cnt;   /* MII device addresses. */
 391         struct mediatable *mtable;
 392         int cur_index;          /* Current media index. */
 393         int saved_if_port;
 394         struct pci_dev *pdev;
 395         int ttimer;
 396         int susp_rx;
 397         unsigned long nir;
 398         void __iomem *base_addr;
 399         int csr12_shadow;
 400         int pad0;               /* Used for 8-byte alignment */
 401         struct work_struct media_work;
 402         struct net_device *dev;
 403 };
 404
 405
 406 struct eeprom_fixup {
 407         char *name;
 408         unsigned char addr0;
 409         unsigned char addr1;
 410         unsigned char addr2;
 411         u16 newtable[32];       /* Max length below. */
 412 };
 413
 414
 415 /* 21142.c */
 416 extern u16 t21142_csr14[];
 417 void t21142_media_task(struct work_struct *work);
 418 void t21142_start_nway(struct net_device *dev);
 419 void t21142_lnk_change(struct net_device *dev, int csr5);
 420
 421
 422 /* PNIC2.c */
 423 void pnic2_lnk_change(struct net_device *dev, int csr5);
 424 void pnic2_timer(unsigned long data);
 425 void pnic2_start_nway(struct net_device *dev);
 426 void pnic2_lnk_change(struct net_device *dev, int csr5);
 427
 428 /* eeprom.c */
 429 void tulip_parse_eeprom(struct net_device *dev);
 430 int tulip_read_eeprom(struct net_device *dev, int location, int addr_len);
 431
 432 /* interrupt.c */
 433 extern unsigned int tulip_max_interrupt_work;
 434 extern int tulip_rx_copybreak;
 435 irqreturn_t tulip_interrupt(int irq, void *dev_instance);
 436 int tulip_refill_rx(struct net_device *dev);
 437 #ifdef CONFIG_TULIP_NAPI
 438 int tulip_poll(struct napi_struct *napi, int budget);
 439 #endif
 440
 441
 442 /* media.c */
 443 int tulip_mdio_read(struct net_device *dev, int phy_id, int location);
 444 void tulip_mdio_write(struct net_device *dev, int phy_id, int location, int value);
 445 void tulip_select_media(struct net_device *dev, int startup);
 446 int tulip_check_duplex(struct net_device *dev);
 447 void tulip_find_mii (struct net_device *dev, int board_idx);
 448
 449 /* pnic.c */
 450 void pnic_do_nway(struct net_device *dev);
 451 void pnic_lnk_change(struct net_device *dev, int csr5);
 452 void pnic_timer(unsigned long data);
 453
 454 /* timer.c */
 455 void tulip_media_task(struct work_struct *work);
 456 void mxic_timer(unsigned long data);
 457 void comet_timer(unsigned long data);
 458
 459 /* tulip_core.c */
 460 extern int tulip_debug;
 461 extern const char * const medianame[];
 462 extern const char tulip_media_cap[];
 463 extern struct tulip_chip_table tulip_tbl[];
 464 void oom_timer(unsigned long data);
 465 extern u8 t21040_csr13[];
 466
 467 static inline void tulip_start_rxtx(struct tulip_private *tp)
 468 {
 469         void __iomem *ioaddr = tp->base_addr;
 470         iowrite32(tp->csr6 | RxTx, ioaddr + CSR6);
 471         barrier();
 472         (void) ioread32(ioaddr + CSR6); /* mmio sync */
 473 }
 474
 475 static inline void tulip_stop_rxtx(struct tulip_private *tp)
 476 {
 477         void __iomem *ioaddr = tp->base_addr;
 478         u32 csr6 = ioread32(ioaddr + CSR6);
 479
 480         if (csr6 & RxTx) {
 481                 unsigned i=1300/10;
 482                 iowrite32(csr6 & ~RxTx, ioaddr + CSR6);
 483                 barrier();
 484                 /* wait until in-flight frame completes.
 485                  * Max time @ 10BT: 1500*8b/10Mbps == 1200us (+ 100us margin)
 486                  * Typically expect this loop to end in < 50 us on 100BT.
 487                  */
 488                 while (--i && (ioread32(ioaddr + CSR5) & (CSR5_TS|CSR5_RS)))
 489                         udelay(10);
 490
 491                 if (!i)
 492                         printk(KERN_DEBUG "%s: tulip_stop_rxtx() failed"
 493                                         " (CSR5 0x%x CSR6 0x%x)\n",
 494                                         pci_name(tp->pdev),
 495                                         ioread32(ioaddr + CSR5),
 496                                         ioread32(ioaddr + CSR6));
 497         }
 498 }
 499
 500 static inline void tulip_restart_rxtx(struct tulip_private *tp)
 501 {
 502         tulip_stop_rxtx(tp);
 503         udelay(5);
 504         tulip_start_rxtx(tp);
 505 }
 506
 507 static inline void tulip_tx_timeout_complete(struct tulip_private *tp, void __iomem *ioaddr)
 508 {
 509         /* Stop and restart the chip's Tx processes. */
 510         tulip_restart_rxtx(tp);
 511         /* Trigger an immediate transmit demand. */
 512         iowrite32(0, ioaddr + CSR1);
 513
 514         tp->stats.tx_errors++;
 515 }
 516
 517 #endif /* __NET_TULIP_H__ */