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tulip: Use DEFINE_PCI_DEVICE_TABLE and static const
[deliverable/linux.git] / drivers / net / tulip / tulip_core.c
1 /* tulip_core.c: A DEC 21x4x-family ethernet driver for Linux.
2
3 Copyright 2000,2001 The Linux Kernel Team
4 Written/copyright 1994-2001 by Donald Becker.
5
6 This software may be used and distributed according to the terms
7 of the GNU General Public License, incorporated herein by reference.
8
9 Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html}
10 for more information on this driver.
11
12 Please submit bugs to http://bugzilla.kernel.org/ .
13 */
14
15
16 #define DRV_NAME "tulip"
17 #ifdef CONFIG_TULIP_NAPI
18 #define DRV_VERSION "1.1.15-NAPI" /* Keep at least for test */
19 #else
20 #define DRV_VERSION "1.1.15"
21 #endif
22 #define DRV_RELDATE "Feb 27, 2007"
23
24
25 #include <linux/module.h>
26 #include <linux/pci.h>
27 #include <linux/slab.h>
28 #include "tulip.h"
29 #include <linux/init.h>
30 #include <linux/etherdevice.h>
31 #include <linux/delay.h>
32 #include <linux/mii.h>
33 #include <linux/crc32.h>
34 #include <asm/unaligned.h>
35 #include <asm/uaccess.h>
36
37 #ifdef CONFIG_SPARC
38 #include <asm/prom.h>
39 #endif
40
41 static char version[] __devinitdata =
42 "Linux Tulip driver version " DRV_VERSION " (" DRV_RELDATE ")\n";
43
44 /* A few user-configurable values. */
45
46 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
47 static unsigned int max_interrupt_work = 25;
48
49 #define MAX_UNITS 8
50 /* Used to pass the full-duplex flag, etc. */
51 static int full_duplex[MAX_UNITS];
52 static int options[MAX_UNITS];
53 static int mtu[MAX_UNITS]; /* Jumbo MTU for interfaces. */
54
55 /* The possible media types that can be set in options[] are: */
56 const char * const medianame[32] = {
57 "10baseT", "10base2", "AUI", "100baseTx",
58 "10baseT-FDX", "100baseTx-FDX", "100baseT4", "100baseFx",
59 "100baseFx-FDX", "MII 10baseT", "MII 10baseT-FDX", "MII",
60 "10baseT(forced)", "MII 100baseTx", "MII 100baseTx-FDX", "MII 100baseT4",
61 "MII 100baseFx-HDX", "MII 100baseFx-FDX", "Home-PNA 1Mbps", "Invalid-19",
62 "","","","", "","","","", "","","","Transceiver reset",
63 };
64
65 /* Set the copy breakpoint for the copy-only-tiny-buffer Rx structure. */
66 #if defined(__alpha__) || defined(__arm__) || defined(__hppa__) || \
67 defined(CONFIG_SPARC) || defined(__ia64__) || \
68 defined(__sh__) || defined(__mips__)
69 static int rx_copybreak = 1518;
70 #else
71 static int rx_copybreak = 100;
72 #endif
73
74 /*
75 Set the bus performance register.
76 Typical: Set 16 longword cache alignment, no burst limit.
77 Cache alignment bits 15:14 Burst length 13:8
78 0000 No alignment 0x00000000 unlimited 0800 8 longwords
79 4000 8 longwords 0100 1 longword 1000 16 longwords
80 8000 16 longwords 0200 2 longwords 2000 32 longwords
81 C000 32 longwords 0400 4 longwords
82 Warning: many older 486 systems are broken and require setting 0x00A04800
83 8 longword cache alignment, 8 longword burst.
84 ToDo: Non-Intel setting could be better.
85 */
86
87 #if defined(__alpha__) || defined(__ia64__)
88 static int csr0 = 0x01A00000 | 0xE000;
89 #elif defined(__i386__) || defined(__powerpc__) || defined(__x86_64__)
90 static int csr0 = 0x01A00000 | 0x8000;
91 #elif defined(CONFIG_SPARC) || defined(__hppa__)
92 /* The UltraSparc PCI controllers will disconnect at every 64-byte
93 * crossing anyways so it makes no sense to tell Tulip to burst
94 * any more than that.
95 */
96 static int csr0 = 0x01A00000 | 0x9000;
97 #elif defined(__arm__) || defined(__sh__)
98 static int csr0 = 0x01A00000 | 0x4800;
99 #elif defined(__mips__)
100 static int csr0 = 0x00200000 | 0x4000;
101 #else
102 #warning Processor architecture undefined!
103 static int csr0 = 0x00A00000 | 0x4800;
104 #endif
105
106 /* Operational parameters that usually are not changed. */
107 /* Time in jiffies before concluding the transmitter is hung. */
108 #define TX_TIMEOUT (4*HZ)
109
110
111 MODULE_AUTHOR("The Linux Kernel Team");
112 MODULE_DESCRIPTION("Digital 21*4* Tulip ethernet driver");
113 MODULE_LICENSE("GPL");
114 MODULE_VERSION(DRV_VERSION);
115 module_param(tulip_debug, int, 0);
116 module_param(max_interrupt_work, int, 0);
117 module_param(rx_copybreak, int, 0);
118 module_param(csr0, int, 0);
119 module_param_array(options, int, NULL, 0);
120 module_param_array(full_duplex, int, NULL, 0);
121
122 #define PFX DRV_NAME ": "
123
124 #ifdef TULIP_DEBUG
125 int tulip_debug = TULIP_DEBUG;
126 #else
127 int tulip_debug = 1;
128 #endif
129
130 static void tulip_timer(unsigned long data)
131 {
132 struct net_device *dev = (struct net_device *)data;
133 struct tulip_private *tp = netdev_priv(dev);
134
135 if (netif_running(dev))
136 schedule_work(&tp->media_work);
137 }
138
139 /*
140 * This table use during operation for capabilities and media timer.
141 *
142 * It is indexed via the values in 'enum chips'
143 */
144
145 struct tulip_chip_table tulip_tbl[] = {
146 { }, /* placeholder for array, slot unused currently */
147 { }, /* placeholder for array, slot unused currently */
148
149 /* DC21140 */
150 { "Digital DS21140 Tulip", 128, 0x0001ebef,
151 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | HAS_PCI_MWI, tulip_timer,
152 tulip_media_task },
153
154 /* DC21142, DC21143 */
155 { "Digital DS21142/43 Tulip", 128, 0x0801fbff,
156 HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII | HAS_ACPI | HAS_NWAY
157 | HAS_INTR_MITIGATION | HAS_PCI_MWI, tulip_timer, t21142_media_task },
158
159 /* LC82C168 */
160 { "Lite-On 82c168 PNIC", 256, 0x0001fbef,
161 HAS_MII | HAS_PNICNWAY, pnic_timer, },
162
163 /* MX98713 */
164 { "Macronix 98713 PMAC", 128, 0x0001ebef,
165 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM, mxic_timer, },
166
167 /* MX98715 */
168 { "Macronix 98715 PMAC", 256, 0x0001ebef,
169 HAS_MEDIA_TABLE, mxic_timer, },
170
171 /* MX98725 */
172 { "Macronix 98725 PMAC", 256, 0x0001ebef,
173 HAS_MEDIA_TABLE, mxic_timer, },
174
175 /* AX88140 */
176 { "ASIX AX88140", 128, 0x0001fbff,
177 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | MC_HASH_ONLY
178 | IS_ASIX, tulip_timer, tulip_media_task },
179
180 /* PNIC2 */
181 { "Lite-On PNIC-II", 256, 0x0801fbff,
182 HAS_MII | HAS_NWAY | HAS_8023X | HAS_PCI_MWI, pnic2_timer, },
183
184 /* COMET */
185 { "ADMtek Comet", 256, 0x0001abef,
186 HAS_MII | MC_HASH_ONLY | COMET_MAC_ADDR, comet_timer, },
187
188 /* COMPEX9881 */
189 { "Compex 9881 PMAC", 128, 0x0001ebef,
190 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM, mxic_timer, },
191
192 /* I21145 */
193 { "Intel DS21145 Tulip", 128, 0x0801fbff,
194 HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII | HAS_ACPI
195 | HAS_NWAY | HAS_PCI_MWI, tulip_timer, tulip_media_task },
196
197 /* DM910X */
198 #ifdef CONFIG_TULIP_DM910X
199 { "Davicom DM9102/DM9102A", 128, 0x0001ebef,
200 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | HAS_ACPI,
201 tulip_timer, tulip_media_task },
202 #else
203 { NULL },
204 #endif
205
206 /* RS7112 */
207 { "Conexant LANfinity", 256, 0x0001ebef,
208 HAS_MII | HAS_ACPI, tulip_timer, tulip_media_task },
209
210 };
211
212
213 static DEFINE_PCI_DEVICE_TABLE(tulip_pci_tbl) = {
214 { 0x1011, 0x0009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DC21140 },
215 { 0x1011, 0x0019, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DC21143 },
216 { 0x11AD, 0x0002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, LC82C168 },
217 { 0x10d9, 0x0512, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98713 },
218 { 0x10d9, 0x0531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98715 },
219 /* { 0x10d9, 0x0531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98725 },*/
220 { 0x125B, 0x1400, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AX88140 },
221 { 0x11AD, 0xc115, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PNIC2 },
222 { 0x1317, 0x0981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
223 { 0x1317, 0x0985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
224 { 0x1317, 0x1985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
225 { 0x1317, 0x9511, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
226 { 0x13D1, 0xAB02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
227 { 0x13D1, 0xAB03, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
228 { 0x13D1, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
229 { 0x104A, 0x0981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
230 { 0x104A, 0x2774, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
231 { 0x1259, 0xa120, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
232 { 0x11F6, 0x9881, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMPEX9881 },
233 { 0x8086, 0x0039, PCI_ANY_ID, PCI_ANY_ID, 0, 0, I21145 },
234 #ifdef CONFIG_TULIP_DM910X
235 { 0x1282, 0x9100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DM910X },
236 { 0x1282, 0x9102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DM910X },
237 #endif
238 { 0x1113, 0x1216, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
239 { 0x1113, 0x1217, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98715 },
240 { 0x1113, 0x9511, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
241 { 0x1186, 0x1541, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
242 { 0x1186, 0x1561, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
243 { 0x1186, 0x1591, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
244 { 0x14f1, 0x1803, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CONEXANT },
245 { 0x1626, 0x8410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
246 { 0x1737, 0xAB09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
247 { 0x1737, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
248 { 0x17B3, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
249 { 0x10b7, 0x9300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, /* 3Com 3CSOHO100B-TX */
250 { 0x14ea, 0xab08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, /* Planex FNW-3602-TX */
251 { 0x1414, 0x0001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, /* Microsoft MN-120 */
252 { 0x1414, 0x0002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
253 { } /* terminate list */
254 };
255 MODULE_DEVICE_TABLE(pci, tulip_pci_tbl);
256
257
258 /* A full-duplex map for media types. */
259 const char tulip_media_cap[32] =
260 {0,0,0,16, 3,19,16,24, 27,4,7,5, 0,20,23,20, 28,31,0,0, };
261
262 static void tulip_tx_timeout(struct net_device *dev);
263 static void tulip_init_ring(struct net_device *dev);
264 static void tulip_free_ring(struct net_device *dev);
265 static netdev_tx_t tulip_start_xmit(struct sk_buff *skb,
266 struct net_device *dev);
267 static int tulip_open(struct net_device *dev);
268 static int tulip_close(struct net_device *dev);
269 static void tulip_up(struct net_device *dev);
270 static void tulip_down(struct net_device *dev);
271 static struct net_device_stats *tulip_get_stats(struct net_device *dev);
272 static int private_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
273 static void set_rx_mode(struct net_device *dev);
274 static void tulip_set_wolopts(struct pci_dev *pdev, u32 wolopts);
275 #ifdef CONFIG_NET_POLL_CONTROLLER
276 static void poll_tulip(struct net_device *dev);
277 #endif
278
279 static void tulip_set_power_state (struct tulip_private *tp,
280 int sleep, int snooze)
281 {
282 if (tp->flags & HAS_ACPI) {
283 u32 tmp, newtmp;
284 pci_read_config_dword (tp->pdev, CFDD, &tmp);
285 newtmp = tmp & ~(CFDD_Sleep | CFDD_Snooze);
286 if (sleep)
287 newtmp |= CFDD_Sleep;
288 else if (snooze)
289 newtmp |= CFDD_Snooze;
290 if (tmp != newtmp)
291 pci_write_config_dword (tp->pdev, CFDD, newtmp);
292 }
293
294 }
295
296
297 static void tulip_up(struct net_device *dev)
298 {
299 struct tulip_private *tp = netdev_priv(dev);
300 void __iomem *ioaddr = tp->base_addr;
301 int next_tick = 3*HZ;
302 u32 reg;
303 int i;
304
305 #ifdef CONFIG_TULIP_NAPI
306 napi_enable(&tp->napi);
307 #endif
308
309 /* Wake the chip from sleep/snooze mode. */
310 tulip_set_power_state (tp, 0, 0);
311
312 /* Disable all WOL events */
313 pci_enable_wake(tp->pdev, PCI_D3hot, 0);
314 pci_enable_wake(tp->pdev, PCI_D3cold, 0);
315 tulip_set_wolopts(tp->pdev, 0);
316
317 /* On some chip revs we must set the MII/SYM port before the reset!? */
318 if (tp->mii_cnt || (tp->mtable && tp->mtable->has_mii))
319 iowrite32(0x00040000, ioaddr + CSR6);
320
321 /* Reset the chip, holding bit 0 set at least 50 PCI cycles. */
322 iowrite32(0x00000001, ioaddr + CSR0);
323 pci_read_config_dword(tp->pdev, PCI_COMMAND, &reg); /* flush write */
324 udelay(100);
325
326 /* Deassert reset.
327 Wait the specified 50 PCI cycles after a reset by initializing
328 Tx and Rx queues and the address filter list. */
329 iowrite32(tp->csr0, ioaddr + CSR0);
330 pci_read_config_dword(tp->pdev, PCI_COMMAND, &reg); /* flush write */
331 udelay(100);
332
333 if (tulip_debug > 1)
334 printk(KERN_DEBUG "%s: tulip_up(), irq==%d\n",
335 dev->name, dev->irq);
336
337 iowrite32(tp->rx_ring_dma, ioaddr + CSR3);
338 iowrite32(tp->tx_ring_dma, ioaddr + CSR4);
339 tp->cur_rx = tp->cur_tx = 0;
340 tp->dirty_rx = tp->dirty_tx = 0;
341
342 if (tp->flags & MC_HASH_ONLY) {
343 u32 addr_low = get_unaligned_le32(dev->dev_addr);
344 u32 addr_high = get_unaligned_le16(dev->dev_addr + 4);
345 if (tp->chip_id == AX88140) {
346 iowrite32(0, ioaddr + CSR13);
347 iowrite32(addr_low, ioaddr + CSR14);
348 iowrite32(1, ioaddr + CSR13);
349 iowrite32(addr_high, ioaddr + CSR14);
350 } else if (tp->flags & COMET_MAC_ADDR) {
351 iowrite32(addr_low, ioaddr + 0xA4);
352 iowrite32(addr_high, ioaddr + 0xA8);
353 iowrite32(0, ioaddr + CSR27);
354 iowrite32(0, ioaddr + CSR28);
355 }
356 } else {
357 /* This is set_rx_mode(), but without starting the transmitter. */
358 u16 *eaddrs = (u16 *)dev->dev_addr;
359 u16 *setup_frm = &tp->setup_frame[15*6];
360 dma_addr_t mapping;
361
362 /* 21140 bug: you must add the broadcast address. */
363 memset(tp->setup_frame, 0xff, sizeof(tp->setup_frame));
364 /* Fill the final entry of the table with our physical address. */
365 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
366 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
367 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
368
369 mapping = pci_map_single(tp->pdev, tp->setup_frame,
370 sizeof(tp->setup_frame),
371 PCI_DMA_TODEVICE);
372 tp->tx_buffers[tp->cur_tx].skb = NULL;
373 tp->tx_buffers[tp->cur_tx].mapping = mapping;
374
375 /* Put the setup frame on the Tx list. */
376 tp->tx_ring[tp->cur_tx].length = cpu_to_le32(0x08000000 | 192);
377 tp->tx_ring[tp->cur_tx].buffer1 = cpu_to_le32(mapping);
378 tp->tx_ring[tp->cur_tx].status = cpu_to_le32(DescOwned);
379
380 tp->cur_tx++;
381 }
382
383 tp->saved_if_port = dev->if_port;
384 if (dev->if_port == 0)
385 dev->if_port = tp->default_port;
386
387 /* Allow selecting a default media. */
388 i = 0;
389 if (tp->mtable == NULL)
390 goto media_picked;
391 if (dev->if_port) {
392 int looking_for = tulip_media_cap[dev->if_port] & MediaIsMII ? 11 :
393 (dev->if_port == 12 ? 0 : dev->if_port);
394 for (i = 0; i < tp->mtable->leafcount; i++)
395 if (tp->mtable->mleaf[i].media == looking_for) {
396 dev_info(&dev->dev,
397 "Using user-specified media %s\n",
398 medianame[dev->if_port]);
399 goto media_picked;
400 }
401 }
402 if ((tp->mtable->defaultmedia & 0x0800) == 0) {
403 int looking_for = tp->mtable->defaultmedia & MEDIA_MASK;
404 for (i = 0; i < tp->mtable->leafcount; i++)
405 if (tp->mtable->mleaf[i].media == looking_for) {
406 dev_info(&dev->dev,
407 "Using EEPROM-set media %s\n",
408 medianame[looking_for]);
409 goto media_picked;
410 }
411 }
412 /* Start sensing first non-full-duplex media. */
413 for (i = tp->mtable->leafcount - 1;
414 (tulip_media_cap[tp->mtable->mleaf[i].media] & MediaAlwaysFD) && i > 0; i--)
415 ;
416 media_picked:
417
418 tp->csr6 = 0;
419 tp->cur_index = i;
420 tp->nwayset = 0;
421
422 if (dev->if_port) {
423 if (tp->chip_id == DC21143 &&
424 (tulip_media_cap[dev->if_port] & MediaIsMII)) {
425 /* We must reset the media CSRs when we force-select MII mode. */
426 iowrite32(0x0000, ioaddr + CSR13);
427 iowrite32(0x0000, ioaddr + CSR14);
428 iowrite32(0x0008, ioaddr + CSR15);
429 }
430 tulip_select_media(dev, 1);
431 } else if (tp->chip_id == DC21142) {
432 if (tp->mii_cnt) {
433 tulip_select_media(dev, 1);
434 if (tulip_debug > 1)
435 dev_info(&dev->dev,
436 "Using MII transceiver %d, status %04x\n",
437 tp->phys[0],
438 tulip_mdio_read(dev, tp->phys[0], 1));
439 iowrite32(csr6_mask_defstate, ioaddr + CSR6);
440 tp->csr6 = csr6_mask_hdcap;
441 dev->if_port = 11;
442 iowrite32(0x0000, ioaddr + CSR13);
443 iowrite32(0x0000, ioaddr + CSR14);
444 } else
445 t21142_start_nway(dev);
446 } else if (tp->chip_id == PNIC2) {
447 /* for initial startup advertise 10/100 Full and Half */
448 tp->sym_advertise = 0x01E0;
449 /* enable autonegotiate end interrupt */
450 iowrite32(ioread32(ioaddr+CSR5)| 0x00008010, ioaddr + CSR5);
451 iowrite32(ioread32(ioaddr+CSR7)| 0x00008010, ioaddr + CSR7);
452 pnic2_start_nway(dev);
453 } else if (tp->chip_id == LC82C168 && ! tp->medialock) {
454 if (tp->mii_cnt) {
455 dev->if_port = 11;
456 tp->csr6 = 0x814C0000 | (tp->full_duplex ? 0x0200 : 0);
457 iowrite32(0x0001, ioaddr + CSR15);
458 } else if (ioread32(ioaddr + CSR5) & TPLnkPass)
459 pnic_do_nway(dev);
460 else {
461 /* Start with 10mbps to do autonegotiation. */
462 iowrite32(0x32, ioaddr + CSR12);
463 tp->csr6 = 0x00420000;
464 iowrite32(0x0001B078, ioaddr + 0xB8);
465 iowrite32(0x0201B078, ioaddr + 0xB8);
466 next_tick = 1*HZ;
467 }
468 } else if ((tp->chip_id == MX98713 || tp->chip_id == COMPEX9881) &&
469 ! tp->medialock) {
470 dev->if_port = 0;
471 tp->csr6 = 0x01880000 | (tp->full_duplex ? 0x0200 : 0);
472 iowrite32(0x0f370000 | ioread16(ioaddr + 0x80), ioaddr + 0x80);
473 } else if (tp->chip_id == MX98715 || tp->chip_id == MX98725) {
474 /* Provided by BOLO, Macronix - 12/10/1998. */
475 dev->if_port = 0;
476 tp->csr6 = 0x01a80200;
477 iowrite32(0x0f370000 | ioread16(ioaddr + 0x80), ioaddr + 0x80);
478 iowrite32(0x11000 | ioread16(ioaddr + 0xa0), ioaddr + 0xa0);
479 } else if (tp->chip_id == COMET || tp->chip_id == CONEXANT) {
480 /* Enable automatic Tx underrun recovery. */
481 iowrite32(ioread32(ioaddr + 0x88) | 1, ioaddr + 0x88);
482 dev->if_port = tp->mii_cnt ? 11 : 0;
483 tp->csr6 = 0x00040000;
484 } else if (tp->chip_id == AX88140) {
485 tp->csr6 = tp->mii_cnt ? 0x00040100 : 0x00000100;
486 } else
487 tulip_select_media(dev, 1);
488
489 /* Start the chip's Tx to process setup frame. */
490 tulip_stop_rxtx(tp);
491 barrier();
492 udelay(5);
493 iowrite32(tp->csr6 | TxOn, ioaddr + CSR6);
494
495 /* Enable interrupts by setting the interrupt mask. */
496 iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR5);
497 iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR7);
498 tulip_start_rxtx(tp);
499 iowrite32(0, ioaddr + CSR2); /* Rx poll demand */
500
501 if (tulip_debug > 2) {
502 printk(KERN_DEBUG "%s: Done tulip_up(), CSR0 %08x, CSR5 %08x CSR6 %08x\n",
503 dev->name, ioread32(ioaddr + CSR0),
504 ioread32(ioaddr + CSR5),
505 ioread32(ioaddr + CSR6));
506 }
507
508 /* Set the timer to switch to check for link beat and perhaps switch
509 to an alternate media type. */
510 tp->timer.expires = RUN_AT(next_tick);
511 add_timer(&tp->timer);
512 #ifdef CONFIG_TULIP_NAPI
513 init_timer(&tp->oom_timer);
514 tp->oom_timer.data = (unsigned long)dev;
515 tp->oom_timer.function = oom_timer;
516 #endif
517 }
518
519 static int
520 tulip_open(struct net_device *dev)
521 {
522 int retval;
523
524 tulip_init_ring (dev);
525
526 retval = request_irq(dev->irq, tulip_interrupt, IRQF_SHARED, dev->name, dev);
527 if (retval)
528 goto free_ring;
529
530 tulip_up (dev);
531
532 netif_start_queue (dev);
533
534 return 0;
535
536 free_ring:
537 tulip_free_ring (dev);
538 return retval;
539 }
540
541
542 static void tulip_tx_timeout(struct net_device *dev)
543 {
544 struct tulip_private *tp = netdev_priv(dev);
545 void __iomem *ioaddr = tp->base_addr;
546 unsigned long flags;
547
548 spin_lock_irqsave (&tp->lock, flags);
549
550 if (tulip_media_cap[dev->if_port] & MediaIsMII) {
551 /* Do nothing -- the media monitor should handle this. */
552 if (tulip_debug > 1)
553 dev_warn(&dev->dev,
554 "Transmit timeout using MII device\n");
555 } else if (tp->chip_id == DC21140 || tp->chip_id == DC21142 ||
556 tp->chip_id == MX98713 || tp->chip_id == COMPEX9881 ||
557 tp->chip_id == DM910X) {
558 dev_warn(&dev->dev,
559 "21140 transmit timed out, status %08x, SIA %08x %08x %08x %08x, resetting...\n",
560 ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12),
561 ioread32(ioaddr + CSR13), ioread32(ioaddr + CSR14),
562 ioread32(ioaddr + CSR15));
563 tp->timeout_recovery = 1;
564 schedule_work(&tp->media_work);
565 goto out_unlock;
566 } else if (tp->chip_id == PNIC2) {
567 dev_warn(&dev->dev,
568 "PNIC2 transmit timed out, status %08x, CSR6/7 %08x / %08x CSR12 %08x, resetting...\n",
569 (int)ioread32(ioaddr + CSR5),
570 (int)ioread32(ioaddr + CSR6),
571 (int)ioread32(ioaddr + CSR7),
572 (int)ioread32(ioaddr + CSR12));
573 } else {
574 dev_warn(&dev->dev,
575 "Transmit timed out, status %08x, CSR12 %08x, resetting...\n",
576 ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12));
577 dev->if_port = 0;
578 }
579
580 #if defined(way_too_many_messages)
581 if (tulip_debug > 3) {
582 int i;
583 for (i = 0; i < RX_RING_SIZE; i++) {
584 u8 *buf = (u8 *)(tp->rx_ring[i].buffer1);
585 int j;
586 printk(KERN_DEBUG
587 "%2d: %08x %08x %08x %08x %02x %02x %02x\n",
588 i,
589 (unsigned int)tp->rx_ring[i].status,
590 (unsigned int)tp->rx_ring[i].length,
591 (unsigned int)tp->rx_ring[i].buffer1,
592 (unsigned int)tp->rx_ring[i].buffer2,
593 buf[0], buf[1], buf[2]);
594 for (j = 0; buf[j] != 0xee && j < 1600; j++)
595 if (j < 100)
596 pr_cont(" %02x", buf[j]);
597 pr_cont(" j=%d\n", j);
598 }
599 printk(KERN_DEBUG " Rx ring %p: ", tp->rx_ring);
600 for (i = 0; i < RX_RING_SIZE; i++)
601 pr_cont(" %08x", (unsigned int)tp->rx_ring[i].status);
602 printk(KERN_DEBUG " Tx ring %p: ", tp->tx_ring);
603 for (i = 0; i < TX_RING_SIZE; i++)
604 pr_cont(" %08x", (unsigned int)tp->tx_ring[i].status);
605 pr_cont("\n");
606 }
607 #endif
608
609 tulip_tx_timeout_complete(tp, ioaddr);
610
611 out_unlock:
612 spin_unlock_irqrestore (&tp->lock, flags);
613 dev->trans_start = jiffies; /* prevent tx timeout */
614 netif_wake_queue (dev);
615 }
616
617
618 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
619 static void tulip_init_ring(struct net_device *dev)
620 {
621 struct tulip_private *tp = netdev_priv(dev);
622 int i;
623
624 tp->susp_rx = 0;
625 tp->ttimer = 0;
626 tp->nir = 0;
627
628 for (i = 0; i < RX_RING_SIZE; i++) {
629 tp->rx_ring[i].status = 0x00000000;
630 tp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ);
631 tp->rx_ring[i].buffer2 = cpu_to_le32(tp->rx_ring_dma + sizeof(struct tulip_rx_desc) * (i + 1));
632 tp->rx_buffers[i].skb = NULL;
633 tp->rx_buffers[i].mapping = 0;
634 }
635 /* Mark the last entry as wrapping the ring. */
636 tp->rx_ring[i-1].length = cpu_to_le32(PKT_BUF_SZ | DESC_RING_WRAP);
637 tp->rx_ring[i-1].buffer2 = cpu_to_le32(tp->rx_ring_dma);
638
639 for (i = 0; i < RX_RING_SIZE; i++) {
640 dma_addr_t mapping;
641
642 /* Note the receive buffer must be longword aligned.
643 dev_alloc_skb() provides 16 byte alignment. But do *not*
644 use skb_reserve() to align the IP header! */
645 struct sk_buff *skb = dev_alloc_skb(PKT_BUF_SZ);
646 tp->rx_buffers[i].skb = skb;
647 if (skb == NULL)
648 break;
649 mapping = pci_map_single(tp->pdev, skb->data,
650 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
651 tp->rx_buffers[i].mapping = mapping;
652 skb->dev = dev; /* Mark as being used by this device. */
653 tp->rx_ring[i].status = cpu_to_le32(DescOwned); /* Owned by Tulip chip */
654 tp->rx_ring[i].buffer1 = cpu_to_le32(mapping);
655 }
656 tp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
657
658 /* The Tx buffer descriptor is filled in as needed, but we
659 do need to clear the ownership bit. */
660 for (i = 0; i < TX_RING_SIZE; i++) {
661 tp->tx_buffers[i].skb = NULL;
662 tp->tx_buffers[i].mapping = 0;
663 tp->tx_ring[i].status = 0x00000000;
664 tp->tx_ring[i].buffer2 = cpu_to_le32(tp->tx_ring_dma + sizeof(struct tulip_tx_desc) * (i + 1));
665 }
666 tp->tx_ring[i-1].buffer2 = cpu_to_le32(tp->tx_ring_dma);
667 }
668
669 static netdev_tx_t
670 tulip_start_xmit(struct sk_buff *skb, struct net_device *dev)
671 {
672 struct tulip_private *tp = netdev_priv(dev);
673 int entry;
674 u32 flag;
675 dma_addr_t mapping;
676 unsigned long flags;
677
678 spin_lock_irqsave(&tp->lock, flags);
679
680 /* Calculate the next Tx descriptor entry. */
681 entry = tp->cur_tx % TX_RING_SIZE;
682
683 tp->tx_buffers[entry].skb = skb;
684 mapping = pci_map_single(tp->pdev, skb->data,
685 skb->len, PCI_DMA_TODEVICE);
686 tp->tx_buffers[entry].mapping = mapping;
687 tp->tx_ring[entry].buffer1 = cpu_to_le32(mapping);
688
689 if (tp->cur_tx - tp->dirty_tx < TX_RING_SIZE/2) {/* Typical path */
690 flag = 0x60000000; /* No interrupt */
691 } else if (tp->cur_tx - tp->dirty_tx == TX_RING_SIZE/2) {
692 flag = 0xe0000000; /* Tx-done intr. */
693 } else if (tp->cur_tx - tp->dirty_tx < TX_RING_SIZE - 2) {
694 flag = 0x60000000; /* No Tx-done intr. */
695 } else { /* Leave room for set_rx_mode() to fill entries. */
696 flag = 0xe0000000; /* Tx-done intr. */
697 netif_stop_queue(dev);
698 }
699 if (entry == TX_RING_SIZE-1)
700 flag = 0xe0000000 | DESC_RING_WRAP;
701
702 tp->tx_ring[entry].length = cpu_to_le32(skb->len | flag);
703 /* if we were using Transmit Automatic Polling, we would need a
704 * wmb() here. */
705 tp->tx_ring[entry].status = cpu_to_le32(DescOwned);
706 wmb();
707
708 tp->cur_tx++;
709
710 /* Trigger an immediate transmit demand. */
711 iowrite32(0, tp->base_addr + CSR1);
712
713 spin_unlock_irqrestore(&tp->lock, flags);
714
715 return NETDEV_TX_OK;
716 }
717
718 static void tulip_clean_tx_ring(struct tulip_private *tp)
719 {
720 unsigned int dirty_tx;
721
722 for (dirty_tx = tp->dirty_tx ; tp->cur_tx - dirty_tx > 0;
723 dirty_tx++) {
724 int entry = dirty_tx % TX_RING_SIZE;
725 int status = le32_to_cpu(tp->tx_ring[entry].status);
726
727 if (status < 0) {
728 tp->dev->stats.tx_errors++; /* It wasn't Txed */
729 tp->tx_ring[entry].status = 0;
730 }
731
732 /* Check for Tx filter setup frames. */
733 if (tp->tx_buffers[entry].skb == NULL) {
734 /* test because dummy frames not mapped */
735 if (tp->tx_buffers[entry].mapping)
736 pci_unmap_single(tp->pdev,
737 tp->tx_buffers[entry].mapping,
738 sizeof(tp->setup_frame),
739 PCI_DMA_TODEVICE);
740 continue;
741 }
742
743 pci_unmap_single(tp->pdev, tp->tx_buffers[entry].mapping,
744 tp->tx_buffers[entry].skb->len,
745 PCI_DMA_TODEVICE);
746
747 /* Free the original skb. */
748 dev_kfree_skb_irq(tp->tx_buffers[entry].skb);
749 tp->tx_buffers[entry].skb = NULL;
750 tp->tx_buffers[entry].mapping = 0;
751 }
752 }
753
754 static void tulip_down (struct net_device *dev)
755 {
756 struct tulip_private *tp = netdev_priv(dev);
757 void __iomem *ioaddr = tp->base_addr;
758 unsigned long flags;
759
760 cancel_work_sync(&tp->media_work);
761
762 #ifdef CONFIG_TULIP_NAPI
763 napi_disable(&tp->napi);
764 #endif
765
766 del_timer_sync (&tp->timer);
767 #ifdef CONFIG_TULIP_NAPI
768 del_timer_sync (&tp->oom_timer);
769 #endif
770 spin_lock_irqsave (&tp->lock, flags);
771
772 /* Disable interrupts by clearing the interrupt mask. */
773 iowrite32 (0x00000000, ioaddr + CSR7);
774
775 /* Stop the Tx and Rx processes. */
776 tulip_stop_rxtx(tp);
777
778 /* prepare receive buffers */
779 tulip_refill_rx(dev);
780
781 /* release any unconsumed transmit buffers */
782 tulip_clean_tx_ring(tp);
783
784 if (ioread32(ioaddr + CSR6) != 0xffffffff)
785 dev->stats.rx_missed_errors += ioread32(ioaddr + CSR8) & 0xffff;
786
787 spin_unlock_irqrestore (&tp->lock, flags);
788
789 init_timer(&tp->timer);
790 tp->timer.data = (unsigned long)dev;
791 tp->timer.function = tulip_tbl[tp->chip_id].media_timer;
792
793 dev->if_port = tp->saved_if_port;
794
795 /* Leave the driver in snooze, not sleep, mode. */
796 tulip_set_power_state (tp, 0, 1);
797 }
798
799 static void tulip_free_ring (struct net_device *dev)
800 {
801 struct tulip_private *tp = netdev_priv(dev);
802 int i;
803
804 /* Free all the skbuffs in the Rx queue. */
805 for (i = 0; i < RX_RING_SIZE; i++) {
806 struct sk_buff *skb = tp->rx_buffers[i].skb;
807 dma_addr_t mapping = tp->rx_buffers[i].mapping;
808
809 tp->rx_buffers[i].skb = NULL;
810 tp->rx_buffers[i].mapping = 0;
811
812 tp->rx_ring[i].status = 0; /* Not owned by Tulip chip. */
813 tp->rx_ring[i].length = 0;
814 /* An invalid address. */
815 tp->rx_ring[i].buffer1 = cpu_to_le32(0xBADF00D0);
816 if (skb) {
817 pci_unmap_single(tp->pdev, mapping, PKT_BUF_SZ,
818 PCI_DMA_FROMDEVICE);
819 dev_kfree_skb (skb);
820 }
821 }
822
823 for (i = 0; i < TX_RING_SIZE; i++) {
824 struct sk_buff *skb = tp->tx_buffers[i].skb;
825
826 if (skb != NULL) {
827 pci_unmap_single(tp->pdev, tp->tx_buffers[i].mapping,
828 skb->len, PCI_DMA_TODEVICE);
829 dev_kfree_skb (skb);
830 }
831 tp->tx_buffers[i].skb = NULL;
832 tp->tx_buffers[i].mapping = 0;
833 }
834 }
835
836 static int tulip_close (struct net_device *dev)
837 {
838 struct tulip_private *tp = netdev_priv(dev);
839 void __iomem *ioaddr = tp->base_addr;
840
841 netif_stop_queue (dev);
842
843 tulip_down (dev);
844
845 if (tulip_debug > 1)
846 dev_printk(KERN_DEBUG, &dev->dev,
847 "Shutting down ethercard, status was %02x\n",
848 ioread32 (ioaddr + CSR5));
849
850 free_irq (dev->irq, dev);
851
852 tulip_free_ring (dev);
853
854 return 0;
855 }
856
857 static struct net_device_stats *tulip_get_stats(struct net_device *dev)
858 {
859 struct tulip_private *tp = netdev_priv(dev);
860 void __iomem *ioaddr = tp->base_addr;
861
862 if (netif_running(dev)) {
863 unsigned long flags;
864
865 spin_lock_irqsave (&tp->lock, flags);
866
867 dev->stats.rx_missed_errors += ioread32(ioaddr + CSR8) & 0xffff;
868
869 spin_unlock_irqrestore(&tp->lock, flags);
870 }
871
872 return &dev->stats;
873 }
874
875
876 static void tulip_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
877 {
878 struct tulip_private *np = netdev_priv(dev);
879 strcpy(info->driver, DRV_NAME);
880 strcpy(info->version, DRV_VERSION);
881 strcpy(info->bus_info, pci_name(np->pdev));
882 }
883
884
885 static int tulip_ethtool_set_wol(struct net_device *dev,
886 struct ethtool_wolinfo *wolinfo)
887 {
888 struct tulip_private *tp = netdev_priv(dev);
889
890 if (wolinfo->wolopts & (~tp->wolinfo.supported))
891 return -EOPNOTSUPP;
892
893 tp->wolinfo.wolopts = wolinfo->wolopts;
894 device_set_wakeup_enable(&tp->pdev->dev, tp->wolinfo.wolopts);
895 return 0;
896 }
897
898 static void tulip_ethtool_get_wol(struct net_device *dev,
899 struct ethtool_wolinfo *wolinfo)
900 {
901 struct tulip_private *tp = netdev_priv(dev);
902
903 wolinfo->supported = tp->wolinfo.supported;
904 wolinfo->wolopts = tp->wolinfo.wolopts;
905 return;
906 }
907
908
909 static const struct ethtool_ops ops = {
910 .get_drvinfo = tulip_get_drvinfo,
911 .set_wol = tulip_ethtool_set_wol,
912 .get_wol = tulip_ethtool_get_wol,
913 };
914
915 /* Provide ioctl() calls to examine the MII xcvr state. */
916 static int private_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
917 {
918 struct tulip_private *tp = netdev_priv(dev);
919 void __iomem *ioaddr = tp->base_addr;
920 struct mii_ioctl_data *data = if_mii(rq);
921 const unsigned int phy_idx = 0;
922 int phy = tp->phys[phy_idx] & 0x1f;
923 unsigned int regnum = data->reg_num;
924
925 switch (cmd) {
926 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
927 if (tp->mii_cnt)
928 data->phy_id = phy;
929 else if (tp->flags & HAS_NWAY)
930 data->phy_id = 32;
931 else if (tp->chip_id == COMET)
932 data->phy_id = 1;
933 else
934 return -ENODEV;
935
936 case SIOCGMIIREG: /* Read MII PHY register. */
937 if (data->phy_id == 32 && (tp->flags & HAS_NWAY)) {
938 int csr12 = ioread32 (ioaddr + CSR12);
939 int csr14 = ioread32 (ioaddr + CSR14);
940 switch (regnum) {
941 case 0:
942 if (((csr14<<5) & 0x1000) ||
943 (dev->if_port == 5 && tp->nwayset))
944 data->val_out = 0x1000;
945 else
946 data->val_out = (tulip_media_cap[dev->if_port]&MediaIs100 ? 0x2000 : 0)
947 | (tulip_media_cap[dev->if_port]&MediaIsFD ? 0x0100 : 0);
948 break;
949 case 1:
950 data->val_out =
951 0x1848 +
952 ((csr12&0x7000) == 0x5000 ? 0x20 : 0) +
953 ((csr12&0x06) == 6 ? 0 : 4);
954 data->val_out |= 0x6048;
955 break;
956 case 4:
957 /* Advertised value, bogus 10baseTx-FD value from CSR6. */
958 data->val_out =
959 ((ioread32(ioaddr + CSR6) >> 3) & 0x0040) +
960 ((csr14 >> 1) & 0x20) + 1;
961 data->val_out |= ((csr14 >> 9) & 0x03C0);
962 break;
963 case 5: data->val_out = tp->lpar; break;
964 default: data->val_out = 0; break;
965 }
966 } else {
967 data->val_out = tulip_mdio_read (dev, data->phy_id & 0x1f, regnum);
968 }
969 return 0;
970
971 case SIOCSMIIREG: /* Write MII PHY register. */
972 if (regnum & ~0x1f)
973 return -EINVAL;
974 if (data->phy_id == phy) {
975 u16 value = data->val_in;
976 switch (regnum) {
977 case 0: /* Check for autonegotiation on or reset. */
978 tp->full_duplex_lock = (value & 0x9000) ? 0 : 1;
979 if (tp->full_duplex_lock)
980 tp->full_duplex = (value & 0x0100) ? 1 : 0;
981 break;
982 case 4:
983 tp->advertising[phy_idx] =
984 tp->mii_advertise = data->val_in;
985 break;
986 }
987 }
988 if (data->phy_id == 32 && (tp->flags & HAS_NWAY)) {
989 u16 value = data->val_in;
990 if (regnum == 0) {
991 if ((value & 0x1200) == 0x1200) {
992 if (tp->chip_id == PNIC2) {
993 pnic2_start_nway (dev);
994 } else {
995 t21142_start_nway (dev);
996 }
997 }
998 } else if (regnum == 4)
999 tp->sym_advertise = value;
1000 } else {
1001 tulip_mdio_write (dev, data->phy_id & 0x1f, regnum, data->val_in);
1002 }
1003 return 0;
1004 default:
1005 return -EOPNOTSUPP;
1006 }
1007
1008 return -EOPNOTSUPP;
1009 }
1010
1011
1012 /* Set or clear the multicast filter for this adaptor.
1013 Note that we only use exclusion around actually queueing the
1014 new frame, not around filling tp->setup_frame. This is non-deterministic
1015 when re-entered but still correct. */
1016
1017 #undef set_bit_le
1018 #define set_bit_le(i,p) do { ((char *)(p))[(i)/8] |= (1<<((i)%8)); } while(0)
1019
1020 static void build_setup_frame_hash(u16 *setup_frm, struct net_device *dev)
1021 {
1022 struct tulip_private *tp = netdev_priv(dev);
1023 u16 hash_table[32];
1024 struct netdev_hw_addr *ha;
1025 int i;
1026 u16 *eaddrs;
1027
1028 memset(hash_table, 0, sizeof(hash_table));
1029 set_bit_le(255, hash_table); /* Broadcast entry */
1030 /* This should work on big-endian machines as well. */
1031 netdev_for_each_mc_addr(ha, dev) {
1032 int index = ether_crc_le(ETH_ALEN, ha->addr) & 0x1ff;
1033
1034 set_bit_le(index, hash_table);
1035 }
1036 for (i = 0; i < 32; i++) {
1037 *setup_frm++ = hash_table[i];
1038 *setup_frm++ = hash_table[i];
1039 }
1040 setup_frm = &tp->setup_frame[13*6];
1041
1042 /* Fill the final entry with our physical address. */
1043 eaddrs = (u16 *)dev->dev_addr;
1044 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
1045 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
1046 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
1047 }
1048
1049 static void build_setup_frame_perfect(u16 *setup_frm, struct net_device *dev)
1050 {
1051 struct tulip_private *tp = netdev_priv(dev);
1052 struct netdev_hw_addr *ha;
1053 u16 *eaddrs;
1054
1055 /* We have <= 14 addresses so we can use the wonderful
1056 16 address perfect filtering of the Tulip. */
1057 netdev_for_each_mc_addr(ha, dev) {
1058 eaddrs = (u16 *) ha->addr;
1059 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
1060 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
1061 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
1062 }
1063 /* Fill the unused entries with the broadcast address. */
1064 memset(setup_frm, 0xff, (15 - netdev_mc_count(dev)) * 12);
1065 setup_frm = &tp->setup_frame[15*6];
1066
1067 /* Fill the final entry with our physical address. */
1068 eaddrs = (u16 *)dev->dev_addr;
1069 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
1070 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
1071 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
1072 }
1073
1074
1075 static void set_rx_mode(struct net_device *dev)
1076 {
1077 struct tulip_private *tp = netdev_priv(dev);
1078 void __iomem *ioaddr = tp->base_addr;
1079 int csr6;
1080
1081 csr6 = ioread32(ioaddr + CSR6) & ~0x00D5;
1082
1083 tp->csr6 &= ~0x00D5;
1084 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1085 tp->csr6 |= AcceptAllMulticast | AcceptAllPhys;
1086 csr6 |= AcceptAllMulticast | AcceptAllPhys;
1087 } else if ((netdev_mc_count(dev) > 1000) ||
1088 (dev->flags & IFF_ALLMULTI)) {
1089 /* Too many to filter well -- accept all multicasts. */
1090 tp->csr6 |= AcceptAllMulticast;
1091 csr6 |= AcceptAllMulticast;
1092 } else if (tp->flags & MC_HASH_ONLY) {
1093 /* Some work-alikes have only a 64-entry hash filter table. */
1094 /* Should verify correctness on big-endian/__powerpc__ */
1095 struct netdev_hw_addr *ha;
1096 if (netdev_mc_count(dev) > 64) {
1097 /* Arbitrary non-effective limit. */
1098 tp->csr6 |= AcceptAllMulticast;
1099 csr6 |= AcceptAllMulticast;
1100 } else {
1101 u32 mc_filter[2] = {0, 0}; /* Multicast hash filter */
1102 int filterbit;
1103 netdev_for_each_mc_addr(ha, dev) {
1104 if (tp->flags & COMET_MAC_ADDR)
1105 filterbit = ether_crc_le(ETH_ALEN,
1106 ha->addr);
1107 else
1108 filterbit = ether_crc(ETH_ALEN,
1109 ha->addr) >> 26;
1110 filterbit &= 0x3f;
1111 mc_filter[filterbit >> 5] |= 1 << (filterbit & 31);
1112 if (tulip_debug > 2)
1113 dev_info(&dev->dev,
1114 "Added filter for %pM %08x bit %d\n",
1115 ha->addr,
1116 ether_crc(ETH_ALEN, ha->addr),
1117 filterbit);
1118 }
1119 if (mc_filter[0] == tp->mc_filter[0] &&
1120 mc_filter[1] == tp->mc_filter[1])
1121 ; /* No change. */
1122 else if (tp->flags & IS_ASIX) {
1123 iowrite32(2, ioaddr + CSR13);
1124 iowrite32(mc_filter[0], ioaddr + CSR14);
1125 iowrite32(3, ioaddr + CSR13);
1126 iowrite32(mc_filter[1], ioaddr + CSR14);
1127 } else if (tp->flags & COMET_MAC_ADDR) {
1128 iowrite32(mc_filter[0], ioaddr + CSR27);
1129 iowrite32(mc_filter[1], ioaddr + CSR28);
1130 }
1131 tp->mc_filter[0] = mc_filter[0];
1132 tp->mc_filter[1] = mc_filter[1];
1133 }
1134 } else {
1135 unsigned long flags;
1136 u32 tx_flags = 0x08000000 | 192;
1137
1138 /* Note that only the low-address shortword of setup_frame is valid!
1139 The values are doubled for big-endian architectures. */
1140 if (netdev_mc_count(dev) > 14) {
1141 /* Must use a multicast hash table. */
1142 build_setup_frame_hash(tp->setup_frame, dev);
1143 tx_flags = 0x08400000 | 192;
1144 } else {
1145 build_setup_frame_perfect(tp->setup_frame, dev);
1146 }
1147
1148 spin_lock_irqsave(&tp->lock, flags);
1149
1150 if (tp->cur_tx - tp->dirty_tx > TX_RING_SIZE - 2) {
1151 /* Same setup recently queued, we need not add it. */
1152 } else {
1153 unsigned int entry;
1154 int dummy = -1;
1155
1156 /* Now add this frame to the Tx list. */
1157
1158 entry = tp->cur_tx++ % TX_RING_SIZE;
1159
1160 if (entry != 0) {
1161 /* Avoid a chip errata by prefixing a dummy entry. */
1162 tp->tx_buffers[entry].skb = NULL;
1163 tp->tx_buffers[entry].mapping = 0;
1164 tp->tx_ring[entry].length =
1165 (entry == TX_RING_SIZE-1) ? cpu_to_le32(DESC_RING_WRAP) : 0;
1166 tp->tx_ring[entry].buffer1 = 0;
1167 /* Must set DescOwned later to avoid race with chip */
1168 dummy = entry;
1169 entry = tp->cur_tx++ % TX_RING_SIZE;
1170
1171 }
1172
1173 tp->tx_buffers[entry].skb = NULL;
1174 tp->tx_buffers[entry].mapping =
1175 pci_map_single(tp->pdev, tp->setup_frame,
1176 sizeof(tp->setup_frame),
1177 PCI_DMA_TODEVICE);
1178 /* Put the setup frame on the Tx list. */
1179 if (entry == TX_RING_SIZE-1)
1180 tx_flags |= DESC_RING_WRAP; /* Wrap ring. */
1181 tp->tx_ring[entry].length = cpu_to_le32(tx_flags);
1182 tp->tx_ring[entry].buffer1 =
1183 cpu_to_le32(tp->tx_buffers[entry].mapping);
1184 tp->tx_ring[entry].status = cpu_to_le32(DescOwned);
1185 if (dummy >= 0)
1186 tp->tx_ring[dummy].status = cpu_to_le32(DescOwned);
1187 if (tp->cur_tx - tp->dirty_tx >= TX_RING_SIZE - 2)
1188 netif_stop_queue(dev);
1189
1190 /* Trigger an immediate transmit demand. */
1191 iowrite32(0, ioaddr + CSR1);
1192 }
1193
1194 spin_unlock_irqrestore(&tp->lock, flags);
1195 }
1196
1197 iowrite32(csr6, ioaddr + CSR6);
1198 }
1199
1200 #ifdef CONFIG_TULIP_MWI
1201 static void __devinit tulip_mwi_config (struct pci_dev *pdev,
1202 struct net_device *dev)
1203 {
1204 struct tulip_private *tp = netdev_priv(dev);
1205 u8 cache;
1206 u16 pci_command;
1207 u32 csr0;
1208
1209 if (tulip_debug > 3)
1210 printk(KERN_DEBUG "%s: tulip_mwi_config()\n", pci_name(pdev));
1211
1212 tp->csr0 = csr0 = 0;
1213
1214 /* if we have any cache line size at all, we can do MRM and MWI */
1215 csr0 |= MRM | MWI;
1216
1217 /* Enable MWI in the standard PCI command bit.
1218 * Check for the case where MWI is desired but not available
1219 */
1220 pci_try_set_mwi(pdev);
1221
1222 /* read result from hardware (in case bit refused to enable) */
1223 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
1224 if ((csr0 & MWI) && (!(pci_command & PCI_COMMAND_INVALIDATE)))
1225 csr0 &= ~MWI;
1226
1227 /* if cache line size hardwired to zero, no MWI */
1228 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache);
1229 if ((csr0 & MWI) && (cache == 0)) {
1230 csr0 &= ~MWI;
1231 pci_clear_mwi(pdev);
1232 }
1233
1234 /* assign per-cacheline-size cache alignment and
1235 * burst length values
1236 */
1237 switch (cache) {
1238 case 8:
1239 csr0 |= MRL | (1 << CALShift) | (16 << BurstLenShift);
1240 break;
1241 case 16:
1242 csr0 |= MRL | (2 << CALShift) | (16 << BurstLenShift);
1243 break;
1244 case 32:
1245 csr0 |= MRL | (3 << CALShift) | (32 << BurstLenShift);
1246 break;
1247 default:
1248 cache = 0;
1249 break;
1250 }
1251
1252 /* if we have a good cache line size, we by now have a good
1253 * csr0, so save it and exit
1254 */
1255 if (cache)
1256 goto out;
1257
1258 /* we don't have a good csr0 or cache line size, disable MWI */
1259 if (csr0 & MWI) {
1260 pci_clear_mwi(pdev);
1261 csr0 &= ~MWI;
1262 }
1263
1264 /* sane defaults for burst length and cache alignment
1265 * originally from de4x5 driver
1266 */
1267 csr0 |= (8 << BurstLenShift) | (1 << CALShift);
1268
1269 out:
1270 tp->csr0 = csr0;
1271 if (tulip_debug > 2)
1272 printk(KERN_DEBUG "%s: MWI config cacheline=%d, csr0=%08x\n",
1273 pci_name(pdev), cache, csr0);
1274 }
1275 #endif
1276
1277 /*
1278 * Chips that have the MRM/reserved bit quirk and the burst quirk. That
1279 * is the DM910X and the on chip ULi devices
1280 */
1281
1282 static int tulip_uli_dm_quirk(struct pci_dev *pdev)
1283 {
1284 if (pdev->vendor == 0x1282 && pdev->device == 0x9102)
1285 return 1;
1286 return 0;
1287 }
1288
1289 static const struct net_device_ops tulip_netdev_ops = {
1290 .ndo_open = tulip_open,
1291 .ndo_start_xmit = tulip_start_xmit,
1292 .ndo_tx_timeout = tulip_tx_timeout,
1293 .ndo_stop = tulip_close,
1294 .ndo_get_stats = tulip_get_stats,
1295 .ndo_do_ioctl = private_ioctl,
1296 .ndo_set_multicast_list = set_rx_mode,
1297 .ndo_change_mtu = eth_change_mtu,
1298 .ndo_set_mac_address = eth_mac_addr,
1299 .ndo_validate_addr = eth_validate_addr,
1300 #ifdef CONFIG_NET_POLL_CONTROLLER
1301 .ndo_poll_controller = poll_tulip,
1302 #endif
1303 };
1304
1305 DEFINE_PCI_DEVICE_TABLE(early_486_chipsets) = {
1306 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82424) },
1307 { PCI_DEVICE(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496) },
1308 { },
1309 };
1310
1311 static int __devinit tulip_init_one (struct pci_dev *pdev,
1312 const struct pci_device_id *ent)
1313 {
1314 struct tulip_private *tp;
1315 /* See note below on the multiport cards. */
1316 static unsigned char last_phys_addr[6] = {0x00, 'L', 'i', 'n', 'u', 'x'};
1317 static int last_irq;
1318 static int multiport_cnt; /* For four-port boards w/one EEPROM */
1319 int i, irq;
1320 unsigned short sum;
1321 unsigned char *ee_data;
1322 struct net_device *dev;
1323 void __iomem *ioaddr;
1324 static int board_idx = -1;
1325 int chip_idx = ent->driver_data;
1326 const char *chip_name = tulip_tbl[chip_idx].chip_name;
1327 unsigned int eeprom_missing = 0;
1328 unsigned int force_csr0 = 0;
1329
1330 #ifndef MODULE
1331 if (tulip_debug > 0)
1332 printk_once(KERN_INFO "%s", version);
1333 #endif
1334
1335 board_idx++;
1336
1337 /*
1338 * Lan media wire a tulip chip to a wan interface. Needs a very
1339 * different driver (lmc driver)
1340 */
1341
1342 if (pdev->subsystem_vendor == PCI_VENDOR_ID_LMC) {
1343 pr_err(PFX "skipping LMC card\n");
1344 return -ENODEV;
1345 } else if (pdev->subsystem_vendor == PCI_VENDOR_ID_SBE &&
1346 (pdev->subsystem_device == PCI_SUBDEVICE_ID_SBE_T3E3 ||
1347 pdev->subsystem_device == PCI_SUBDEVICE_ID_SBE_2T3E3_P0 ||
1348 pdev->subsystem_device == PCI_SUBDEVICE_ID_SBE_2T3E3_P1)) {
1349 pr_err(PFX "skipping SBE T3E3 port\n");
1350 return -ENODEV;
1351 }
1352
1353 /*
1354 * DM910x chips should be handled by the dmfe driver, except
1355 * on-board chips on SPARC systems. Also, early DM9100s need
1356 * software CRC which only the dmfe driver supports.
1357 */
1358
1359 #ifdef CONFIG_TULIP_DM910X
1360 if (chip_idx == DM910X) {
1361 struct device_node *dp;
1362
1363 if (pdev->vendor == 0x1282 && pdev->device == 0x9100 &&
1364 pdev->revision < 0x30) {
1365 pr_info(PFX "skipping early DM9100 with Crc bug (use dmfe)\n");
1366 return -ENODEV;
1367 }
1368
1369 dp = pci_device_to_OF_node(pdev);
1370 if (!(dp && of_get_property(dp, "local-mac-address", NULL))) {
1371 pr_info(PFX "skipping DM910x expansion card (use dmfe)\n");
1372 return -ENODEV;
1373 }
1374 }
1375 #endif
1376
1377 /*
1378 * Looks for early PCI chipsets where people report hangs
1379 * without the workarounds being on.
1380 */
1381
1382 /* 1. Intel Saturn. Switch to 8 long words burst, 8 long word cache
1383 aligned. Aries might need this too. The Saturn errata are not
1384 pretty reading but thankfully it's an old 486 chipset.
1385
1386 2. The dreaded SiS496 486 chipset. Same workaround as Intel
1387 Saturn.
1388 */
1389
1390 if (pci_dev_present(early_486_chipsets)) {
1391 csr0 = MRL | MRM | (8 << BurstLenShift) | (1 << CALShift);
1392 force_csr0 = 1;
1393 }
1394
1395 /* bugfix: the ASIX must have a burst limit or horrible things happen. */
1396 if (chip_idx == AX88140) {
1397 if ((csr0 & 0x3f00) == 0)
1398 csr0 |= 0x2000;
1399 }
1400
1401 /* PNIC doesn't have MWI/MRL/MRM... */
1402 if (chip_idx == LC82C168)
1403 csr0 &= ~0xfff10000; /* zero reserved bits 31:20, 16 */
1404
1405 /* DM9102A has troubles with MRM & clear reserved bits 24:22, 20, 16, 7:1 */
1406 if (tulip_uli_dm_quirk(pdev)) {
1407 csr0 &= ~0x01f100ff;
1408 #if defined(CONFIG_SPARC)
1409 csr0 = (csr0 & ~0xff00) | 0xe000;
1410 #endif
1411 }
1412 /*
1413 * And back to business
1414 */
1415
1416 i = pci_enable_device(pdev);
1417 if (i) {
1418 pr_err(PFX "Cannot enable tulip board #%d, aborting\n",
1419 board_idx);
1420 return i;
1421 }
1422
1423 /* The chip will fail to enter a low-power state later unless
1424 * first explicitly commanded into D0 */
1425 if (pci_set_power_state(pdev, PCI_D0)) {
1426 printk (KERN_NOTICE PFX
1427 "Failed to set power state to D0\n");
1428 }
1429
1430 irq = pdev->irq;
1431
1432 /* alloc_etherdev ensures aligned and zeroed private structures */
1433 dev = alloc_etherdev (sizeof (*tp));
1434 if (!dev) {
1435 pr_err(PFX "ether device alloc failed, aborting\n");
1436 return -ENOMEM;
1437 }
1438
1439 SET_NETDEV_DEV(dev, &pdev->dev);
1440 if (pci_resource_len (pdev, 0) < tulip_tbl[chip_idx].io_size) {
1441 pr_err(PFX "%s: I/O region (0x%llx@0x%llx) too small, aborting\n",
1442 pci_name(pdev),
1443 (unsigned long long)pci_resource_len (pdev, 0),
1444 (unsigned long long)pci_resource_start (pdev, 0));
1445 goto err_out_free_netdev;
1446 }
1447
1448 /* grab all resources from both PIO and MMIO regions, as we
1449 * don't want anyone else messing around with our hardware */
1450 if (pci_request_regions (pdev, DRV_NAME))
1451 goto err_out_free_netdev;
1452
1453 ioaddr = pci_iomap(pdev, TULIP_BAR, tulip_tbl[chip_idx].io_size);
1454
1455 if (!ioaddr)
1456 goto err_out_free_res;
1457
1458 /*
1459 * initialize private data structure 'tp'
1460 * it is zeroed and aligned in alloc_etherdev
1461 */
1462 tp = netdev_priv(dev);
1463 tp->dev = dev;
1464
1465 tp->rx_ring = pci_alloc_consistent(pdev,
1466 sizeof(struct tulip_rx_desc) * RX_RING_SIZE +
1467 sizeof(struct tulip_tx_desc) * TX_RING_SIZE,
1468 &tp->rx_ring_dma);
1469 if (!tp->rx_ring)
1470 goto err_out_mtable;
1471 tp->tx_ring = (struct tulip_tx_desc *)(tp->rx_ring + RX_RING_SIZE);
1472 tp->tx_ring_dma = tp->rx_ring_dma + sizeof(struct tulip_rx_desc) * RX_RING_SIZE;
1473
1474 tp->chip_id = chip_idx;
1475 tp->flags = tulip_tbl[chip_idx].flags;
1476
1477 tp->wolinfo.supported = 0;
1478 tp->wolinfo.wolopts = 0;
1479 /* COMET: Enable power management only for AN983B */
1480 if (chip_idx == COMET ) {
1481 u32 sig;
1482 pci_read_config_dword (pdev, 0x80, &sig);
1483 if (sig == 0x09811317) {
1484 tp->flags |= COMET_PM;
1485 tp->wolinfo.supported = WAKE_PHY | WAKE_MAGIC;
1486 printk(KERN_INFO "tulip_init_one: Enabled WOL support for AN983B\n");
1487 }
1488 }
1489 tp->pdev = pdev;
1490 tp->base_addr = ioaddr;
1491 tp->revision = pdev->revision;
1492 tp->csr0 = csr0;
1493 spin_lock_init(&tp->lock);
1494 spin_lock_init(&tp->mii_lock);
1495 init_timer(&tp->timer);
1496 tp->timer.data = (unsigned long)dev;
1497 tp->timer.function = tulip_tbl[tp->chip_id].media_timer;
1498
1499 INIT_WORK(&tp->media_work, tulip_tbl[tp->chip_id].media_task);
1500
1501 dev->base_addr = (unsigned long)ioaddr;
1502
1503 #ifdef CONFIG_TULIP_MWI
1504 if (!force_csr0 && (tp->flags & HAS_PCI_MWI))
1505 tulip_mwi_config (pdev, dev);
1506 #endif
1507
1508 /* Stop the chip's Tx and Rx processes. */
1509 tulip_stop_rxtx(tp);
1510
1511 pci_set_master(pdev);
1512
1513 #ifdef CONFIG_GSC
1514 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP) {
1515 switch (pdev->subsystem_device) {
1516 default:
1517 break;
1518 case 0x1061:
1519 case 0x1062:
1520 case 0x1063:
1521 case 0x1098:
1522 case 0x1099:
1523 case 0x10EE:
1524 tp->flags |= HAS_SWAPPED_SEEPROM | NEEDS_FAKE_MEDIA_TABLE;
1525 chip_name = "GSC DS21140 Tulip";
1526 }
1527 }
1528 #endif
1529
1530 /* Clear the missed-packet counter. */
1531 ioread32(ioaddr + CSR8);
1532
1533 /* The station address ROM is read byte serially. The register must
1534 be polled, waiting for the value to be read bit serially from the
1535 EEPROM.
1536 */
1537 ee_data = tp->eeprom;
1538 memset(ee_data, 0, sizeof(tp->eeprom));
1539 sum = 0;
1540 if (chip_idx == LC82C168) {
1541 for (i = 0; i < 3; i++) {
1542 int value, boguscnt = 100000;
1543 iowrite32(0x600 | i, ioaddr + 0x98);
1544 do {
1545 value = ioread32(ioaddr + CSR9);
1546 } while (value < 0 && --boguscnt > 0);
1547 put_unaligned_le16(value, ((__le16 *)dev->dev_addr) + i);
1548 sum += value & 0xffff;
1549 }
1550 } else if (chip_idx == COMET) {
1551 /* No need to read the EEPROM. */
1552 put_unaligned_le32(ioread32(ioaddr + 0xA4), dev->dev_addr);
1553 put_unaligned_le16(ioread32(ioaddr + 0xA8), dev->dev_addr + 4);
1554 for (i = 0; i < 6; i ++)
1555 sum += dev->dev_addr[i];
1556 } else {
1557 /* A serial EEPROM interface, we read now and sort it out later. */
1558 int sa_offset = 0;
1559 int ee_addr_size = tulip_read_eeprom(dev, 0xff, 8) & 0x40000 ? 8 : 6;
1560 int ee_max_addr = ((1 << ee_addr_size) - 1) * sizeof(u16);
1561
1562 if (ee_max_addr > sizeof(tp->eeprom))
1563 ee_max_addr = sizeof(tp->eeprom);
1564
1565 for (i = 0; i < ee_max_addr ; i += sizeof(u16)) {
1566 u16 data = tulip_read_eeprom(dev, i/2, ee_addr_size);
1567 ee_data[i] = data & 0xff;
1568 ee_data[i + 1] = data >> 8;
1569 }
1570
1571 /* DEC now has a specification (see Notes) but early board makers
1572 just put the address in the first EEPROM locations. */
1573 /* This does memcmp(ee_data, ee_data+16, 8) */
1574 for (i = 0; i < 8; i ++)
1575 if (ee_data[i] != ee_data[16+i])
1576 sa_offset = 20;
1577 if (chip_idx == CONEXANT) {
1578 /* Check that the tuple type and length is correct. */
1579 if (ee_data[0x198] == 0x04 && ee_data[0x199] == 6)
1580 sa_offset = 0x19A;
1581 } else if (ee_data[0] == 0xff && ee_data[1] == 0xff &&
1582 ee_data[2] == 0) {
1583 sa_offset = 2; /* Grrr, damn Matrox boards. */
1584 multiport_cnt = 4;
1585 }
1586 #ifdef CONFIG_MIPS_COBALT
1587 if ((pdev->bus->number == 0) &&
1588 ((PCI_SLOT(pdev->devfn) == 7) ||
1589 (PCI_SLOT(pdev->devfn) == 12))) {
1590 /* Cobalt MAC address in first EEPROM locations. */
1591 sa_offset = 0;
1592 /* Ensure our media table fixup get's applied */
1593 memcpy(ee_data + 16, ee_data, 8);
1594 }
1595 #endif
1596 #ifdef CONFIG_GSC
1597 /* Check to see if we have a broken srom */
1598 if (ee_data[0] == 0x61 && ee_data[1] == 0x10) {
1599 /* pci_vendor_id and subsystem_id are swapped */
1600 ee_data[0] = ee_data[2];
1601 ee_data[1] = ee_data[3];
1602 ee_data[2] = 0x61;
1603 ee_data[3] = 0x10;
1604
1605 /* HSC-PCI boards need to be byte-swaped and shifted
1606 * up 1 word. This shift needs to happen at the end
1607 * of the MAC first because of the 2 byte overlap.
1608 */
1609 for (i = 4; i >= 0; i -= 2) {
1610 ee_data[17 + i + 3] = ee_data[17 + i];
1611 ee_data[16 + i + 5] = ee_data[16 + i];
1612 }
1613 }
1614 #endif
1615
1616 for (i = 0; i < 6; i ++) {
1617 dev->dev_addr[i] = ee_data[i + sa_offset];
1618 sum += ee_data[i + sa_offset];
1619 }
1620 }
1621 /* Lite-On boards have the address byte-swapped. */
1622 if ((dev->dev_addr[0] == 0xA0 ||
1623 dev->dev_addr[0] == 0xC0 ||
1624 dev->dev_addr[0] == 0x02) &&
1625 dev->dev_addr[1] == 0x00)
1626 for (i = 0; i < 6; i+=2) {
1627 char tmp = dev->dev_addr[i];
1628 dev->dev_addr[i] = dev->dev_addr[i+1];
1629 dev->dev_addr[i+1] = tmp;
1630 }
1631 /* On the Zynx 315 Etherarray and other multiport boards only the
1632 first Tulip has an EEPROM.
1633 On Sparc systems the mac address is held in the OBP property
1634 "local-mac-address".
1635 The addresses of the subsequent ports are derived from the first.
1636 Many PCI BIOSes also incorrectly report the IRQ line, so we correct
1637 that here as well. */
1638 if (sum == 0 || sum == 6*0xff) {
1639 #if defined(CONFIG_SPARC)
1640 struct device_node *dp = pci_device_to_OF_node(pdev);
1641 const unsigned char *addr;
1642 int len;
1643 #endif
1644 eeprom_missing = 1;
1645 for (i = 0; i < 5; i++)
1646 dev->dev_addr[i] = last_phys_addr[i];
1647 dev->dev_addr[i] = last_phys_addr[i] + 1;
1648 #if defined(CONFIG_SPARC)
1649 addr = of_get_property(dp, "local-mac-address", &len);
1650 if (addr && len == 6)
1651 memcpy(dev->dev_addr, addr, 6);
1652 #endif
1653 #if defined(__i386__) || defined(__x86_64__) /* Patch up x86 BIOS bug. */
1654 if (last_irq)
1655 irq = last_irq;
1656 #endif
1657 }
1658
1659 for (i = 0; i < 6; i++)
1660 last_phys_addr[i] = dev->dev_addr[i];
1661 last_irq = irq;
1662 dev->irq = irq;
1663
1664 /* The lower four bits are the media type. */
1665 if (board_idx >= 0 && board_idx < MAX_UNITS) {
1666 if (options[board_idx] & MEDIA_MASK)
1667 tp->default_port = options[board_idx] & MEDIA_MASK;
1668 if ((options[board_idx] & FullDuplex) || full_duplex[board_idx] > 0)
1669 tp->full_duplex = 1;
1670 if (mtu[board_idx] > 0)
1671 dev->mtu = mtu[board_idx];
1672 }
1673 if (dev->mem_start & MEDIA_MASK)
1674 tp->default_port = dev->mem_start & MEDIA_MASK;
1675 if (tp->default_port) {
1676 pr_info(DRV_NAME "%d: Transceiver selection forced to %s\n",
1677 board_idx, medianame[tp->default_port & MEDIA_MASK]);
1678 tp->medialock = 1;
1679 if (tulip_media_cap[tp->default_port] & MediaAlwaysFD)
1680 tp->full_duplex = 1;
1681 }
1682 if (tp->full_duplex)
1683 tp->full_duplex_lock = 1;
1684
1685 if (tulip_media_cap[tp->default_port] & MediaIsMII) {
1686 static const u16 media2advert[] = {
1687 0x20, 0x40, 0x03e0, 0x60, 0x80, 0x100, 0x200
1688 };
1689 tp->mii_advertise = media2advert[tp->default_port - 9];
1690 tp->mii_advertise |= (tp->flags & HAS_8023X); /* Matching bits! */
1691 }
1692
1693 if (tp->flags & HAS_MEDIA_TABLE) {
1694 sprintf(dev->name, DRV_NAME "%d", board_idx); /* hack */
1695 tulip_parse_eeprom(dev);
1696 strcpy(dev->name, "eth%d"); /* un-hack */
1697 }
1698
1699 if ((tp->flags & ALWAYS_CHECK_MII) ||
1700 (tp->mtable && tp->mtable->has_mii) ||
1701 ( ! tp->mtable && (tp->flags & HAS_MII))) {
1702 if (tp->mtable && tp->mtable->has_mii) {
1703 for (i = 0; i < tp->mtable->leafcount; i++)
1704 if (tp->mtable->mleaf[i].media == 11) {
1705 tp->cur_index = i;
1706 tp->saved_if_port = dev->if_port;
1707 tulip_select_media(dev, 2);
1708 dev->if_port = tp->saved_if_port;
1709 break;
1710 }
1711 }
1712
1713 /* Find the connected MII xcvrs.
1714 Doing this in open() would allow detecting external xcvrs
1715 later, but takes much time. */
1716 tulip_find_mii (dev, board_idx);
1717 }
1718
1719 /* The Tulip-specific entries in the device structure. */
1720 dev->netdev_ops = &tulip_netdev_ops;
1721 dev->watchdog_timeo = TX_TIMEOUT;
1722 #ifdef CONFIG_TULIP_NAPI
1723 netif_napi_add(dev, &tp->napi, tulip_poll, 16);
1724 #endif
1725 SET_ETHTOOL_OPS(dev, &ops);
1726
1727 if (register_netdev(dev))
1728 goto err_out_free_ring;
1729
1730 pci_set_drvdata(pdev, dev);
1731
1732 dev_info(&dev->dev,
1733 #ifdef CONFIG_TULIP_MMIO
1734 "%s rev %d at MMIO %#llx,%s %pM, IRQ %d\n",
1735 #else
1736 "%s rev %d at Port %#llx,%s %pM, IRQ %d\n",
1737 #endif
1738 chip_name, pdev->revision,
1739 (unsigned long long)pci_resource_start(pdev, TULIP_BAR),
1740 eeprom_missing ? " EEPROM not present," : "",
1741 dev->dev_addr, irq);
1742
1743 if (tp->chip_id == PNIC2)
1744 tp->link_change = pnic2_lnk_change;
1745 else if (tp->flags & HAS_NWAY)
1746 tp->link_change = t21142_lnk_change;
1747 else if (tp->flags & HAS_PNICNWAY)
1748 tp->link_change = pnic_lnk_change;
1749
1750 /* Reset the xcvr interface and turn on heartbeat. */
1751 switch (chip_idx) {
1752 case DC21140:
1753 case DM910X:
1754 default:
1755 if (tp->mtable)
1756 iowrite32(tp->mtable->csr12dir | 0x100, ioaddr + CSR12);
1757 break;
1758 case DC21142:
1759 if (tp->mii_cnt || tulip_media_cap[dev->if_port] & MediaIsMII) {
1760 iowrite32(csr6_mask_defstate, ioaddr + CSR6);
1761 iowrite32(0x0000, ioaddr + CSR13);
1762 iowrite32(0x0000, ioaddr + CSR14);
1763 iowrite32(csr6_mask_hdcap, ioaddr + CSR6);
1764 } else
1765 t21142_start_nway(dev);
1766 break;
1767 case PNIC2:
1768 /* just do a reset for sanity sake */
1769 iowrite32(0x0000, ioaddr + CSR13);
1770 iowrite32(0x0000, ioaddr + CSR14);
1771 break;
1772 case LC82C168:
1773 if ( ! tp->mii_cnt) {
1774 tp->nway = 1;
1775 tp->nwayset = 0;
1776 iowrite32(csr6_ttm | csr6_ca, ioaddr + CSR6);
1777 iowrite32(0x30, ioaddr + CSR12);
1778 iowrite32(0x0001F078, ioaddr + CSR6);
1779 iowrite32(0x0201F078, ioaddr + CSR6); /* Turn on autonegotiation. */
1780 }
1781 break;
1782 case MX98713:
1783 case COMPEX9881:
1784 iowrite32(0x00000000, ioaddr + CSR6);
1785 iowrite32(0x000711C0, ioaddr + CSR14); /* Turn on NWay. */
1786 iowrite32(0x00000001, ioaddr + CSR13);
1787 break;
1788 case MX98715:
1789 case MX98725:
1790 iowrite32(0x01a80000, ioaddr + CSR6);
1791 iowrite32(0xFFFFFFFF, ioaddr + CSR14);
1792 iowrite32(0x00001000, ioaddr + CSR12);
1793 break;
1794 case COMET:
1795 /* No initialization necessary. */
1796 break;
1797 }
1798
1799 /* put the chip in snooze mode until opened */
1800 tulip_set_power_state (tp, 0, 1);
1801
1802 return 0;
1803
1804 err_out_free_ring:
1805 pci_free_consistent (pdev,
1806 sizeof (struct tulip_rx_desc) * RX_RING_SIZE +
1807 sizeof (struct tulip_tx_desc) * TX_RING_SIZE,
1808 tp->rx_ring, tp->rx_ring_dma);
1809
1810 err_out_mtable:
1811 kfree (tp->mtable);
1812 pci_iounmap(pdev, ioaddr);
1813
1814 err_out_free_res:
1815 pci_release_regions (pdev);
1816
1817 err_out_free_netdev:
1818 free_netdev (dev);
1819 return -ENODEV;
1820 }
1821
1822
1823 /* set the registers according to the given wolopts */
1824 static void tulip_set_wolopts (struct pci_dev *pdev, u32 wolopts)
1825 {
1826 struct net_device *dev = pci_get_drvdata(pdev);
1827 struct tulip_private *tp = netdev_priv(dev);
1828 void __iomem *ioaddr = tp->base_addr;
1829
1830 if (tp->flags & COMET_PM) {
1831
1832 unsigned int tmp;
1833
1834 tmp = ioread32(ioaddr + CSR18);
1835 tmp &= ~(comet_csr18_pmes_sticky | comet_csr18_apm_mode | comet_csr18_d3a);
1836 tmp |= comet_csr18_pm_mode;
1837 iowrite32(tmp, ioaddr + CSR18);
1838
1839 /* Set the Wake-up Control/Status Register to the given WOL options*/
1840 tmp = ioread32(ioaddr + CSR13);
1841 tmp &= ~(comet_csr13_linkoffe | comet_csr13_linkone | comet_csr13_wfre | comet_csr13_lsce | comet_csr13_mpre);
1842 if (wolopts & WAKE_MAGIC)
1843 tmp |= comet_csr13_mpre;
1844 if (wolopts & WAKE_PHY)
1845 tmp |= comet_csr13_linkoffe | comet_csr13_linkone | comet_csr13_lsce;
1846 /* Clear the event flags */
1847 tmp |= comet_csr13_wfr | comet_csr13_mpr | comet_csr13_lsc;
1848 iowrite32(tmp, ioaddr + CSR13);
1849 }
1850 }
1851
1852 #ifdef CONFIG_PM
1853
1854
1855 static int tulip_suspend (struct pci_dev *pdev, pm_message_t state)
1856 {
1857 pci_power_t pstate;
1858 struct net_device *dev = pci_get_drvdata(pdev);
1859 struct tulip_private *tp = netdev_priv(dev);
1860
1861 if (!dev)
1862 return -EINVAL;
1863
1864 if (!netif_running(dev))
1865 goto save_state;
1866
1867 tulip_down(dev);
1868
1869 netif_device_detach(dev);
1870 free_irq(dev->irq, dev);
1871
1872 save_state:
1873 pci_save_state(pdev);
1874 pci_disable_device(pdev);
1875 pstate = pci_choose_state(pdev, state);
1876 if (state.event == PM_EVENT_SUSPEND && pstate != PCI_D0) {
1877 int rc;
1878
1879 tulip_set_wolopts(pdev, tp->wolinfo.wolopts);
1880 rc = pci_enable_wake(pdev, pstate, tp->wolinfo.wolopts);
1881 if (rc)
1882 printk("tulip: pci_enable_wake failed (%d)\n", rc);
1883 }
1884 pci_set_power_state(pdev, pstate);
1885
1886 return 0;
1887 }
1888
1889
1890 static int tulip_resume(struct pci_dev *pdev)
1891 {
1892 struct net_device *dev = pci_get_drvdata(pdev);
1893 struct tulip_private *tp = netdev_priv(dev);
1894 void __iomem *ioaddr = tp->base_addr;
1895 int retval;
1896 unsigned int tmp;
1897
1898 if (!dev)
1899 return -EINVAL;
1900
1901 pci_set_power_state(pdev, PCI_D0);
1902 pci_restore_state(pdev);
1903
1904 if (!netif_running(dev))
1905 return 0;
1906
1907 if ((retval = pci_enable_device(pdev))) {
1908 pr_err(PFX "pci_enable_device failed in resume\n");
1909 return retval;
1910 }
1911
1912 if ((retval = request_irq(dev->irq, tulip_interrupt, IRQF_SHARED, dev->name, dev))) {
1913 pr_err(PFX "request_irq failed in resume\n");
1914 return retval;
1915 }
1916
1917 if (tp->flags & COMET_PM) {
1918 pci_enable_wake(pdev, PCI_D3hot, 0);
1919 pci_enable_wake(pdev, PCI_D3cold, 0);
1920
1921 /* Clear the PMES flag */
1922 tmp = ioread32(ioaddr + CSR20);
1923 tmp |= comet_csr20_pmes;
1924 iowrite32(tmp, ioaddr + CSR20);
1925
1926 /* Disable all wake-up events */
1927 tulip_set_wolopts(pdev, 0);
1928 }
1929 netif_device_attach(dev);
1930
1931 if (netif_running(dev))
1932 tulip_up(dev);
1933
1934 return 0;
1935 }
1936
1937 #endif /* CONFIG_PM */
1938
1939
1940 static void __devexit tulip_remove_one (struct pci_dev *pdev)
1941 {
1942 struct net_device *dev = pci_get_drvdata (pdev);
1943 struct tulip_private *tp;
1944
1945 if (!dev)
1946 return;
1947
1948 tp = netdev_priv(dev);
1949 unregister_netdev(dev);
1950 pci_free_consistent (pdev,
1951 sizeof (struct tulip_rx_desc) * RX_RING_SIZE +
1952 sizeof (struct tulip_tx_desc) * TX_RING_SIZE,
1953 tp->rx_ring, tp->rx_ring_dma);
1954 kfree (tp->mtable);
1955 pci_iounmap(pdev, tp->base_addr);
1956 free_netdev (dev);
1957 pci_release_regions (pdev);
1958 pci_set_drvdata (pdev, NULL);
1959
1960 /* pci_power_off (pdev, -1); */
1961 }
1962
1963 #ifdef CONFIG_NET_POLL_CONTROLLER
1964 /*
1965 * Polling 'interrupt' - used by things like netconsole to send skbs
1966 * without having to re-enable interrupts. It's not called while
1967 * the interrupt routine is executing.
1968 */
1969
1970 static void poll_tulip (struct net_device *dev)
1971 {
1972 /* disable_irq here is not very nice, but with the lockless
1973 interrupt handler we have no other choice. */
1974 disable_irq(dev->irq);
1975 tulip_interrupt (dev->irq, dev);
1976 enable_irq(dev->irq);
1977 }
1978 #endif
1979
1980 static struct pci_driver tulip_driver = {
1981 .name = DRV_NAME,
1982 .id_table = tulip_pci_tbl,
1983 .probe = tulip_init_one,
1984 .remove = __devexit_p(tulip_remove_one),
1985 #ifdef CONFIG_PM
1986 .suspend = tulip_suspend,
1987 .resume = tulip_resume,
1988 #endif /* CONFIG_PM */
1989 };
1990
1991
1992 static int __init tulip_init (void)
1993 {
1994 #ifdef MODULE
1995 pr_info("%s", version);
1996 #endif
1997
1998 /* copy module parms into globals */
1999 tulip_rx_copybreak = rx_copybreak;
2000 tulip_max_interrupt_work = max_interrupt_work;
2001
2002 /* probe for and init boards */
2003 return pci_register_driver(&tulip_driver);
2004 }
2005
2006
2007 static void __exit tulip_cleanup (void)
2008 {
2009 pci_unregister_driver (&tulip_driver);
2010 }
2011
2012
2013 module_init(tulip_init);
2014 module_exit(tulip_cleanup);
Linux kernel - Deliverables
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