projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
ucc_geth: Implement Transmit on Demand support
[deliverable/linux.git] / drivers / net / ucc_geth.c
1 /*
2 * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
3 *
4 * Author: Shlomi Gridish <gridish@freescale.com>
5 * Li Yang <leoli@freescale.com>
6 *
7 * Description:
8 * QE UCC Gigabit Ethernet Driver
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/errno.h>
18 #include <linux/slab.h>
19 #include <linux/stddef.h>
20 #include <linux/interrupt.h>
21 #include <linux/netdevice.h>
22 #include <linux/etherdevice.h>
23 #include <linux/skbuff.h>
24 #include <linux/spinlock.h>
25 #include <linux/mm.h>
26 #include <linux/ethtool.h>
27 #include <linux/delay.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/fsl_devices.h>
30 #include <linux/ethtool.h>
31 #include <linux/mii.h>
32 #include <linux/phy.h>
33 #include <linux/workqueue.h>
34
35 #include <asm/of_platform.h>
36 #include <asm/uaccess.h>
37 #include <asm/irq.h>
38 #include <asm/io.h>
39 #include <asm/immap_qe.h>
40 #include <asm/qe.h>
41 #include <asm/ucc.h>
42 #include <asm/ucc_fast.h>
43
44 #include "ucc_geth.h"
45 #include "ucc_geth_mii.h"
46
47 #undef DEBUG
48
49 #define DRV_DESC "QE UCC Gigabit Ethernet Controller version:Sept 11, 2006"
50 #define DRV_NAME "ucc_geth"
51
52 #define ugeth_printk(level, format, arg...) \
53 printk(level format "\n", ## arg)
54
55 #define ugeth_dbg(format, arg...) \
56 ugeth_printk(KERN_DEBUG , format , ## arg)
57 #define ugeth_err(format, arg...) \
58 ugeth_printk(KERN_ERR , format , ## arg)
59 #define ugeth_info(format, arg...) \
60 ugeth_printk(KERN_INFO , format , ## arg)
61 #define ugeth_warn(format, arg...) \
62 ugeth_printk(KERN_WARNING , format , ## arg)
63
64 #ifdef UGETH_VERBOSE_DEBUG
65 #define ugeth_vdbg ugeth_dbg
66 #else
67 #define ugeth_vdbg(fmt, args...) do { } while (0)
68 #endif /* UGETH_VERBOSE_DEBUG */
69
70 static DEFINE_SPINLOCK(ugeth_lock);
71
72 static struct ucc_geth_info ugeth_primary_info = {
73 .uf_info = {
74 .bd_mem_part = MEM_PART_SYSTEM,
75 .rtsm = UCC_FAST_SEND_IDLES_BETWEEN_FRAMES,
76 .max_rx_buf_length = 1536,
77 /* adjusted at startup if max-speed 1000 */
78 .urfs = UCC_GETH_URFS_INIT,
79 .urfet = UCC_GETH_URFET_INIT,
80 .urfset = UCC_GETH_URFSET_INIT,
81 .utfs = UCC_GETH_UTFS_INIT,
82 .utfet = UCC_GETH_UTFET_INIT,
83 .utftt = UCC_GETH_UTFTT_INIT,
84 .ufpt = 256,
85 .mode = UCC_FAST_PROTOCOL_MODE_ETHERNET,
86 .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL,
87 .tenc = UCC_FAST_TX_ENCODING_NRZ,
88 .renc = UCC_FAST_RX_ENCODING_NRZ,
89 .tcrc = UCC_FAST_16_BIT_CRC,
90 .synl = UCC_FAST_SYNC_LEN_NOT_USED,
91 },
92 .numQueuesTx = 1,
93 .numQueuesRx = 1,
94 .extendedFilteringChainPointer = ((uint32_t) NULL),
95 .typeorlen = 3072 /*1536 */ ,
96 .nonBackToBackIfgPart1 = 0x40,
97 .nonBackToBackIfgPart2 = 0x60,
98 .miminumInterFrameGapEnforcement = 0x50,
99 .backToBackInterFrameGap = 0x60,
100 .mblinterval = 128,
101 .nortsrbytetime = 5,
102 .fracsiz = 1,
103 .strictpriorityq = 0xff,
104 .altBebTruncation = 0xa,
105 .excessDefer = 1,
106 .maxRetransmission = 0xf,
107 .collisionWindow = 0x37,
108 .receiveFlowControl = 1,
109 .maxGroupAddrInHash = 4,
110 .maxIndAddrInHash = 4,
111 .prel = 7,
112 .maxFrameLength = 1518,
113 .minFrameLength = 64,
114 .maxD1Length = 1520,
115 .maxD2Length = 1520,
116 .vlantype = 0x8100,
117 .ecamptr = ((uint32_t) NULL),
118 .eventRegMask = UCCE_OTHER,
119 .pausePeriod = 0xf000,
120 .interruptcoalescingmaxvalue = {1, 1, 1, 1, 1, 1, 1, 1},
121 .bdRingLenTx = {
122 TX_BD_RING_LEN,
123 TX_BD_RING_LEN,
124 TX_BD_RING_LEN,
125 TX_BD_RING_LEN,
126 TX_BD_RING_LEN,
127 TX_BD_RING_LEN,
128 TX_BD_RING_LEN,
129 TX_BD_RING_LEN},
130
131 .bdRingLenRx = {
132 RX_BD_RING_LEN,
133 RX_BD_RING_LEN,
134 RX_BD_RING_LEN,
135 RX_BD_RING_LEN,
136 RX_BD_RING_LEN,
137 RX_BD_RING_LEN,
138 RX_BD_RING_LEN,
139 RX_BD_RING_LEN},
140
141 .numStationAddresses = UCC_GETH_NUM_OF_STATION_ADDRESSES_1,
142 .largestexternallookupkeysize =
143 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE,
144 .statisticsMode = UCC_GETH_STATISTICS_GATHERING_MODE_NONE,
145 .vlanOperationTagged = UCC_GETH_VLAN_OPERATION_TAGGED_NOP,
146 .vlanOperationNonTagged = UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP,
147 .rxQoSMode = UCC_GETH_QOS_MODE_DEFAULT,
148 .aufc = UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE,
149 .padAndCrc = MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC,
150 .numThreadsTx = UCC_GETH_NUM_OF_THREADS_4,
151 .numThreadsRx = UCC_GETH_NUM_OF_THREADS_4,
152 .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
153 .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
154 };
155
156 static struct ucc_geth_info ugeth_info[8];
157
158 #ifdef DEBUG
159 static void mem_disp(u8 *addr, int size)
160 {
161 u8 *i;
162 int size16Aling = (size >> 4) << 4;
163 int size4Aling = (size >> 2) << 2;
164 int notAlign = 0;
165 if (size % 16)
166 notAlign = 1;
167
168 for (i = addr; (u32) i < (u32) addr + size16Aling; i += 16)
169 printk("0x%08x: %08x %08x %08x %08x\r\n",
170 (u32) i,
171 *((u32 *) (i)),
172 *((u32 *) (i + 4)),
173 *((u32 *) (i + 8)), *((u32 *) (i + 12)));
174 if (notAlign == 1)
175 printk("0x%08x: ", (u32) i);
176 for (; (u32) i < (u32) addr + size4Aling; i += 4)
177 printk("%08x ", *((u32 *) (i)));
178 for (; (u32) i < (u32) addr + size; i++)
179 printk("%02x", *((u8 *) (i)));
180 if (notAlign == 1)
181 printk("\r\n");
182 }
183 #endif /* DEBUG */
184
185 #ifdef CONFIG_UGETH_FILTERING
186 static void enqueue(struct list_head *node, struct list_head *lh)
187 {
188 unsigned long flags;
189
190 spin_lock_irqsave(&ugeth_lock, flags);
191 list_add_tail(node, lh);
192 spin_unlock_irqrestore(&ugeth_lock, flags);
193 }
194 #endif /* CONFIG_UGETH_FILTERING */
195
196 static struct list_head *dequeue(struct list_head *lh)
197 {
198 unsigned long flags;
199
200 spin_lock_irqsave(&ugeth_lock, flags);
201 if (!list_empty(lh)) {
202 struct list_head *node = lh->next;
203 list_del(node);
204 spin_unlock_irqrestore(&ugeth_lock, flags);
205 return node;
206 } else {
207 spin_unlock_irqrestore(&ugeth_lock, flags);
208 return NULL;
209 }
210 }
211
212 static struct sk_buff *get_new_skb(struct ucc_geth_private *ugeth, u8 *bd)
213 {
214 struct sk_buff *skb = NULL;
215
216 skb = dev_alloc_skb(ugeth->ug_info->uf_info.max_rx_buf_length +
217 UCC_GETH_RX_DATA_BUF_ALIGNMENT);
218
219 if (skb == NULL)
220 return NULL;
221
222 /* We need the data buffer to be aligned properly. We will reserve
223 * as many bytes as needed to align the data properly
224 */
225 skb_reserve(skb,
226 UCC_GETH_RX_DATA_BUF_ALIGNMENT -
227 (((unsigned)skb->data) & (UCC_GETH_RX_DATA_BUF_ALIGNMENT -
228 1)));
229
230 skb->dev = ugeth->dev;
231
232 out_be32(&((struct qe_bd *)bd)->buf,
233 dma_map_single(NULL,
234 skb->data,
235 ugeth->ug_info->uf_info.max_rx_buf_length +
236 UCC_GETH_RX_DATA_BUF_ALIGNMENT,
237 DMA_FROM_DEVICE));
238
239 out_be32((u32 *)bd, (R_E | R_I | (in_be32((u32 *)bd) & R_W)));
240
241 return skb;
242 }
243
244 static int rx_bd_buffer_set(struct ucc_geth_private *ugeth, u8 rxQ)
245 {
246 u8 *bd;
247 u32 bd_status;
248 struct sk_buff *skb;
249 int i;
250
251 bd = ugeth->p_rx_bd_ring[rxQ];
252 i = 0;
253
254 do {
255 bd_status = in_be32((u32*)bd);
256 skb = get_new_skb(ugeth, bd);
257
258 if (!skb) /* If can not allocate data buffer,
259 abort. Cleanup will be elsewhere */
260 return -ENOMEM;
261
262 ugeth->rx_skbuff[rxQ][i] = skb;
263
264 /* advance the BD pointer */
265 bd += sizeof(struct qe_bd);
266 i++;
267 } while (!(bd_status & R_W));
268
269 return 0;
270 }
271
272 static int fill_init_enet_entries(struct ucc_geth_private *ugeth,
273 volatile u32 *p_start,
274 u8 num_entries,
275 u32 thread_size,
276 u32 thread_alignment,
277 enum qe_risc_allocation risc,
278 int skip_page_for_first_entry)
279 {
280 u32 init_enet_offset;
281 u8 i;
282 int snum;
283
284 for (i = 0; i < num_entries; i++) {
285 if ((snum = qe_get_snum()) < 0) {
286 ugeth_err("fill_init_enet_entries: Can not get SNUM.");
287 return snum;
288 }
289 if ((i == 0) && skip_page_for_first_entry)
290 /* First entry of Rx does not have page */
291 init_enet_offset = 0;
292 else {
293 init_enet_offset =
294 qe_muram_alloc(thread_size, thread_alignment);
295 if (IS_MURAM_ERR(init_enet_offset)) {
296 ugeth_err
297 ("fill_init_enet_entries: Can not allocate DPRAM memory.");
298 qe_put_snum((u8) snum);
299 return -ENOMEM;
300 }
301 }
302 *(p_start++) =
303 ((u8) snum << ENET_INIT_PARAM_SNUM_SHIFT) | init_enet_offset
304 | risc;
305 }
306
307 return 0;
308 }
309
310 static int return_init_enet_entries(struct ucc_geth_private *ugeth,
311 volatile u32 *p_start,
312 u8 num_entries,
313 enum qe_risc_allocation risc,
314 int skip_page_for_first_entry)
315 {
316 u32 init_enet_offset;
317 u8 i;
318 int snum;
319
320 for (i = 0; i < num_entries; i++) {
321 /* Check that this entry was actually valid --
322 needed in case failed in allocations */
323 if ((*p_start & ENET_INIT_PARAM_RISC_MASK) == risc) {
324 snum =
325 (u32) (*p_start & ENET_INIT_PARAM_SNUM_MASK) >>
326 ENET_INIT_PARAM_SNUM_SHIFT;
327 qe_put_snum((u8) snum);
328 if (!((i == 0) && skip_page_for_first_entry)) {
329 /* First entry of Rx does not have page */
330 init_enet_offset =
331 (in_be32(p_start) &
332 ENET_INIT_PARAM_PTR_MASK);
333 qe_muram_free(init_enet_offset);
334 }
335 *(p_start++) = 0; /* Just for cosmetics */
336 }
337 }
338
339 return 0;
340 }
341
342 #ifdef DEBUG
343 static int dump_init_enet_entries(struct ucc_geth_private *ugeth,
344 volatile u32 *p_start,
345 u8 num_entries,
346 u32 thread_size,
347 enum qe_risc_allocation risc,
348 int skip_page_for_first_entry)
349 {
350 u32 init_enet_offset;
351 u8 i;
352 int snum;
353
354 for (i = 0; i < num_entries; i++) {
355 /* Check that this entry was actually valid --
356 needed in case failed in allocations */
357 if ((*p_start & ENET_INIT_PARAM_RISC_MASK) == risc) {
358 snum =
359 (u32) (*p_start & ENET_INIT_PARAM_SNUM_MASK) >>
360 ENET_INIT_PARAM_SNUM_SHIFT;
361 qe_put_snum((u8) snum);
362 if (!((i == 0) && skip_page_for_first_entry)) {
363 /* First entry of Rx does not have page */
364 init_enet_offset =
365 (in_be32(p_start) &
366 ENET_INIT_PARAM_PTR_MASK);
367 ugeth_info("Init enet entry %d:", i);
368 ugeth_info("Base address: 0x%08x",
369 (u32)
370 qe_muram_addr(init_enet_offset));
371 mem_disp(qe_muram_addr(init_enet_offset),
372 thread_size);
373 }
374 p_start++;
375 }
376 }
377
378 return 0;
379 }
380 #endif
381
382 #ifdef CONFIG_UGETH_FILTERING
383 static struct enet_addr_container *get_enet_addr_container(void)
384 {
385 struct enet_addr_container *enet_addr_cont;
386
387 /* allocate memory */
388 enet_addr_cont = kmalloc(sizeof(struct enet_addr_container), GFP_KERNEL);
389 if (!enet_addr_cont) {
390 ugeth_err("%s: No memory for enet_addr_container object.",
391 __FUNCTION__);
392 return NULL;
393 }
394
395 return enet_addr_cont;
396 }
397 #endif /* CONFIG_UGETH_FILTERING */
398
399 static void put_enet_addr_container(struct enet_addr_container *enet_addr_cont)
400 {
401 kfree(enet_addr_cont);
402 }
403
404 static void set_mac_addr(__be16 __iomem *reg, u8 *mac)
405 {
406 out_be16(&reg[0], ((u16)mac[5] << 8) | mac[4]);
407 out_be16(&reg[1], ((u16)mac[3] << 8) | mac[2]);
408 out_be16(&reg[2], ((u16)mac[1] << 8) | mac[0]);
409 }
410
411 #ifdef CONFIG_UGETH_FILTERING
412 static int hw_add_addr_in_paddr(struct ucc_geth_private *ugeth,
413 u8 *p_enet_addr, u8 paddr_num)
414 {
415 struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
416
417 if (!(paddr_num < NUM_OF_PADDRS)) {
418 ugeth_warn("%s: Illegal paddr_num.", __FUNCTION__);
419 return -EINVAL;
420 }
421
422 p_82xx_addr_filt =
423 (struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram->
424 addressfiltering;
425
426 /* Ethernet frames are defined in Little Endian mode, */
427 /* therefore to insert the address we reverse the bytes. */
428 set_mac_addr(&p_82xx_addr_filt->paddr[paddr_num].h, p_enet_addr);
429 return 0;
430 }
431 #endif /* CONFIG_UGETH_FILTERING */
432
433 static int hw_clear_addr_in_paddr(struct ucc_geth_private *ugeth, u8 paddr_num)
434 {
435 struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
436
437 if (!(paddr_num < NUM_OF_PADDRS)) {
438 ugeth_warn("%s: Illagel paddr_num.", __FUNCTION__);
439 return -EINVAL;
440 }
441
442 p_82xx_addr_filt =
443 (struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram->
444 addressfiltering;
445
446 /* Writing address ff.ff.ff.ff.ff.ff disables address
447 recognition for this register */
448 out_be16(&p_82xx_addr_filt->paddr[paddr_num].h, 0xffff);
449 out_be16(&p_82xx_addr_filt->paddr[paddr_num].m, 0xffff);
450 out_be16(&p_82xx_addr_filt->paddr[paddr_num].l, 0xffff);
451
452 return 0;
453 }
454
455 static void hw_add_addr_in_hash(struct ucc_geth_private *ugeth,
456 u8 *p_enet_addr)
457 {
458 struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
459 u32 cecr_subblock;
460
461 p_82xx_addr_filt =
462 (struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram->
463 addressfiltering;
464
465 cecr_subblock =
466 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
467
468 /* Ethernet frames are defined in Little Endian mode,
469 therefor to insert */
470 /* the address to the hash (Big Endian mode), we reverse the bytes.*/
471
472 set_mac_addr(&p_82xx_addr_filt->taddr.h, p_enet_addr);
473
474 qe_issue_cmd(QE_SET_GROUP_ADDRESS, cecr_subblock,
475 QE_CR_PROTOCOL_ETHERNET, 0);
476 }
477
478 #ifdef CONFIG_UGETH_MAGIC_PACKET
479 static void magic_packet_detection_enable(struct ucc_geth_private *ugeth)
480 {
481 struct ucc_fast_private *uccf;
482 struct ucc_geth *ug_regs;
483 u32 maccfg2, uccm;
484
485 uccf = ugeth->uccf;
486 ug_regs = ugeth->ug_regs;
487
488 /* Enable interrupts for magic packet detection */
489 uccm = in_be32(uccf->p_uccm);
490 uccm |= UCCE_MPD;
491 out_be32(uccf->p_uccm, uccm);
492
493 /* Enable magic packet detection */
494 maccfg2 = in_be32(&ug_regs->maccfg2);
495 maccfg2 |= MACCFG2_MPE;
496 out_be32(&ug_regs->maccfg2, maccfg2);
497 }
498
499 static void magic_packet_detection_disable(struct ucc_geth_private *ugeth)
500 {
501 struct ucc_fast_private *uccf;
502 struct ucc_geth *ug_regs;
503 u32 maccfg2, uccm;
504
505 uccf = ugeth->uccf;
506 ug_regs = ugeth->ug_regs;
507
508 /* Disable interrupts for magic packet detection */
509 uccm = in_be32(uccf->p_uccm);
510 uccm &= ~UCCE_MPD;
511 out_be32(uccf->p_uccm, uccm);
512
513 /* Disable magic packet detection */
514 maccfg2 = in_be32(&ug_regs->maccfg2);
515 maccfg2 &= ~MACCFG2_MPE;
516 out_be32(&ug_regs->maccfg2, maccfg2);
517 }
518 #endif /* MAGIC_PACKET */
519
520 static inline int compare_addr(u8 **addr1, u8 **addr2)
521 {
522 return memcmp(addr1, addr2, ENET_NUM_OCTETS_PER_ADDRESS);
523 }
524
525 #ifdef DEBUG
526 static void get_statistics(struct ucc_geth_private *ugeth,
527 struct ucc_geth_tx_firmware_statistics *
528 tx_firmware_statistics,
529 struct ucc_geth_rx_firmware_statistics *
530 rx_firmware_statistics,
531 struct ucc_geth_hardware_statistics *hardware_statistics)
532 {
533 struct ucc_fast *uf_regs;
534 struct ucc_geth *ug_regs;
535 struct ucc_geth_tx_firmware_statistics_pram *p_tx_fw_statistics_pram;
536 struct ucc_geth_rx_firmware_statistics_pram *p_rx_fw_statistics_pram;
537
538 ug_regs = ugeth->ug_regs;
539 uf_regs = (struct ucc_fast *) ug_regs;
540 p_tx_fw_statistics_pram = ugeth->p_tx_fw_statistics_pram;
541 p_rx_fw_statistics_pram = ugeth->p_rx_fw_statistics_pram;
542
543 /* Tx firmware only if user handed pointer and driver actually
544 gathers Tx firmware statistics */
545 if (tx_firmware_statistics && p_tx_fw_statistics_pram) {
546 tx_firmware_statistics->sicoltx =
547 in_be32(&p_tx_fw_statistics_pram->sicoltx);
548 tx_firmware_statistics->mulcoltx =
549 in_be32(&p_tx_fw_statistics_pram->mulcoltx);
550 tx_firmware_statistics->latecoltxfr =
551 in_be32(&p_tx_fw_statistics_pram->latecoltxfr);
552 tx_firmware_statistics->frabortduecol =
553 in_be32(&p_tx_fw_statistics_pram->frabortduecol);
554 tx_firmware_statistics->frlostinmactxer =
555 in_be32(&p_tx_fw_statistics_pram->frlostinmactxer);
556 tx_firmware_statistics->carriersenseertx =
557 in_be32(&p_tx_fw_statistics_pram->carriersenseertx);
558 tx_firmware_statistics->frtxok =
559 in_be32(&p_tx_fw_statistics_pram->frtxok);
560 tx_firmware_statistics->txfrexcessivedefer =
561 in_be32(&p_tx_fw_statistics_pram->txfrexcessivedefer);
562 tx_firmware_statistics->txpkts256 =
563 in_be32(&p_tx_fw_statistics_pram->txpkts256);
564 tx_firmware_statistics->txpkts512 =
565 in_be32(&p_tx_fw_statistics_pram->txpkts512);
566 tx_firmware_statistics->txpkts1024 =
567 in_be32(&p_tx_fw_statistics_pram->txpkts1024);
568 tx_firmware_statistics->txpktsjumbo =
569 in_be32(&p_tx_fw_statistics_pram->txpktsjumbo);
570 }
571
572 /* Rx firmware only if user handed pointer and driver actually
573 * gathers Rx firmware statistics */
574 if (rx_firmware_statistics && p_rx_fw_statistics_pram) {
575 int i;
576 rx_firmware_statistics->frrxfcser =
577 in_be32(&p_rx_fw_statistics_pram->frrxfcser);
578 rx_firmware_statistics->fraligner =
579 in_be32(&p_rx_fw_statistics_pram->fraligner);
580 rx_firmware_statistics->inrangelenrxer =
581 in_be32(&p_rx_fw_statistics_pram->inrangelenrxer);
582 rx_firmware_statistics->outrangelenrxer =
583 in_be32(&p_rx_fw_statistics_pram->outrangelenrxer);
584 rx_firmware_statistics->frtoolong =
585 in_be32(&p_rx_fw_statistics_pram->frtoolong);
586 rx_firmware_statistics->runt =
587 in_be32(&p_rx_fw_statistics_pram->runt);
588 rx_firmware_statistics->verylongevent =
589 in_be32(&p_rx_fw_statistics_pram->verylongevent);
590 rx_firmware_statistics->symbolerror =
591 in_be32(&p_rx_fw_statistics_pram->symbolerror);
592 rx_firmware_statistics->dropbsy =
593 in_be32(&p_rx_fw_statistics_pram->dropbsy);
594 for (i = 0; i < 0x8; i++)
595 rx_firmware_statistics->res0[i] =
596 p_rx_fw_statistics_pram->res0[i];
597 rx_firmware_statistics->mismatchdrop =
598 in_be32(&p_rx_fw_statistics_pram->mismatchdrop);
599 rx_firmware_statistics->underpkts =
600 in_be32(&p_rx_fw_statistics_pram->underpkts);
601 rx_firmware_statistics->pkts256 =
602 in_be32(&p_rx_fw_statistics_pram->pkts256);
603 rx_firmware_statistics->pkts512 =
604 in_be32(&p_rx_fw_statistics_pram->pkts512);
605 rx_firmware_statistics->pkts1024 =
606 in_be32(&p_rx_fw_statistics_pram->pkts1024);
607 rx_firmware_statistics->pktsjumbo =
608 in_be32(&p_rx_fw_statistics_pram->pktsjumbo);
609 rx_firmware_statistics->frlossinmacer =
610 in_be32(&p_rx_fw_statistics_pram->frlossinmacer);
611 rx_firmware_statistics->pausefr =
612 in_be32(&p_rx_fw_statistics_pram->pausefr);
613 for (i = 0; i < 0x4; i++)
614 rx_firmware_statistics->res1[i] =
615 p_rx_fw_statistics_pram->res1[i];
616 rx_firmware_statistics->removevlan =
617 in_be32(&p_rx_fw_statistics_pram->removevlan);
618 rx_firmware_statistics->replacevlan =
619 in_be32(&p_rx_fw_statistics_pram->replacevlan);
620 rx_firmware_statistics->insertvlan =
621 in_be32(&p_rx_fw_statistics_pram->insertvlan);
622 }
623
624 /* Hardware only if user handed pointer and driver actually
625 gathers hardware statistics */
626 if (hardware_statistics && (in_be32(&uf_regs->upsmr) & UPSMR_HSE)) {
627 hardware_statistics->tx64 = in_be32(&ug_regs->tx64);
628 hardware_statistics->tx127 = in_be32(&ug_regs->tx127);
629 hardware_statistics->tx255 = in_be32(&ug_regs->tx255);
630 hardware_statistics->rx64 = in_be32(&ug_regs->rx64);
631 hardware_statistics->rx127 = in_be32(&ug_regs->rx127);
632 hardware_statistics->rx255 = in_be32(&ug_regs->rx255);
633 hardware_statistics->txok = in_be32(&ug_regs->txok);
634 hardware_statistics->txcf = in_be16(&ug_regs->txcf);
635 hardware_statistics->tmca = in_be32(&ug_regs->tmca);
636 hardware_statistics->tbca = in_be32(&ug_regs->tbca);
637 hardware_statistics->rxfok = in_be32(&ug_regs->rxfok);
638 hardware_statistics->rxbok = in_be32(&ug_regs->rxbok);
639 hardware_statistics->rbyt = in_be32(&ug_regs->rbyt);
640 hardware_statistics->rmca = in_be32(&ug_regs->rmca);
641 hardware_statistics->rbca = in_be32(&ug_regs->rbca);
642 }
643 }
644
645 static void dump_bds(struct ucc_geth_private *ugeth)
646 {
647 int i;
648 int length;
649
650 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
651 if (ugeth->p_tx_bd_ring[i]) {
652 length =
653 (ugeth->ug_info->bdRingLenTx[i] *
654 sizeof(struct qe_bd));
655 ugeth_info("TX BDs[%d]", i);
656 mem_disp(ugeth->p_tx_bd_ring[i], length);
657 }
658 }
659 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
660 if (ugeth->p_rx_bd_ring[i]) {
661 length =
662 (ugeth->ug_info->bdRingLenRx[i] *
663 sizeof(struct qe_bd));
664 ugeth_info("RX BDs[%d]", i);
665 mem_disp(ugeth->p_rx_bd_ring[i], length);
666 }
667 }
668 }
669
670 static void dump_regs(struct ucc_geth_private *ugeth)
671 {
672 int i;
673
674 ugeth_info("UCC%d Geth registers:", ugeth->ug_info->uf_info.ucc_num);
675 ugeth_info("Base address: 0x%08x", (u32) ugeth->ug_regs);
676
677 ugeth_info("maccfg1 : addr - 0x%08x, val - 0x%08x",
678 (u32) & ugeth->ug_regs->maccfg1,
679 in_be32(&ugeth->ug_regs->maccfg1));
680 ugeth_info("maccfg2 : addr - 0x%08x, val - 0x%08x",
681 (u32) & ugeth->ug_regs->maccfg2,
682 in_be32(&ugeth->ug_regs->maccfg2));
683 ugeth_info("ipgifg : addr - 0x%08x, val - 0x%08x",
684 (u32) & ugeth->ug_regs->ipgifg,
685 in_be32(&ugeth->ug_regs->ipgifg));
686 ugeth_info("hafdup : addr - 0x%08x, val - 0x%08x",
687 (u32) & ugeth->ug_regs->hafdup,
688 in_be32(&ugeth->ug_regs->hafdup));
689 ugeth_info("ifctl : addr - 0x%08x, val - 0x%08x",
690 (u32) & ugeth->ug_regs->ifctl,
691 in_be32(&ugeth->ug_regs->ifctl));
692 ugeth_info("ifstat : addr - 0x%08x, val - 0x%08x",
693 (u32) & ugeth->ug_regs->ifstat,
694 in_be32(&ugeth->ug_regs->ifstat));
695 ugeth_info("macstnaddr1: addr - 0x%08x, val - 0x%08x",
696 (u32) & ugeth->ug_regs->macstnaddr1,
697 in_be32(&ugeth->ug_regs->macstnaddr1));
698 ugeth_info("macstnaddr2: addr - 0x%08x, val - 0x%08x",
699 (u32) & ugeth->ug_regs->macstnaddr2,
700 in_be32(&ugeth->ug_regs->macstnaddr2));
701 ugeth_info("uempr : addr - 0x%08x, val - 0x%08x",
702 (u32) & ugeth->ug_regs->uempr,
703 in_be32(&ugeth->ug_regs->uempr));
704 ugeth_info("utbipar : addr - 0x%08x, val - 0x%08x",
705 (u32) & ugeth->ug_regs->utbipar,
706 in_be32(&ugeth->ug_regs->utbipar));
707 ugeth_info("uescr : addr - 0x%08x, val - 0x%04x",
708 (u32) & ugeth->ug_regs->uescr,
709 in_be16(&ugeth->ug_regs->uescr));
710 ugeth_info("tx64 : addr - 0x%08x, val - 0x%08x",
711 (u32) & ugeth->ug_regs->tx64,
712 in_be32(&ugeth->ug_regs->tx64));
713 ugeth_info("tx127 : addr - 0x%08x, val - 0x%08x",
714 (u32) & ugeth->ug_regs->tx127,
715 in_be32(&ugeth->ug_regs->tx127));
716 ugeth_info("tx255 : addr - 0x%08x, val - 0x%08x",
717 (u32) & ugeth->ug_regs->tx255,
718 in_be32(&ugeth->ug_regs->tx255));
719 ugeth_info("rx64 : addr - 0x%08x, val - 0x%08x",
720 (u32) & ugeth->ug_regs->rx64,
721 in_be32(&ugeth->ug_regs->rx64));
722 ugeth_info("rx127 : addr - 0x%08x, val - 0x%08x",
723 (u32) & ugeth->ug_regs->rx127,
724 in_be32(&ugeth->ug_regs->rx127));
725 ugeth_info("rx255 : addr - 0x%08x, val - 0x%08x",
726 (u32) & ugeth->ug_regs->rx255,
727 in_be32(&ugeth->ug_regs->rx255));
728 ugeth_info("txok : addr - 0x%08x, val - 0x%08x",
729 (u32) & ugeth->ug_regs->txok,
730 in_be32(&ugeth->ug_regs->txok));
731 ugeth_info("txcf : addr - 0x%08x, val - 0x%04x",
732 (u32) & ugeth->ug_regs->txcf,
733 in_be16(&ugeth->ug_regs->txcf));
734 ugeth_info("tmca : addr - 0x%08x, val - 0x%08x",
735 (u32) & ugeth->ug_regs->tmca,
736 in_be32(&ugeth->ug_regs->tmca));
737 ugeth_info("tbca : addr - 0x%08x, val - 0x%08x",
738 (u32) & ugeth->ug_regs->tbca,
739 in_be32(&ugeth->ug_regs->tbca));
740 ugeth_info("rxfok : addr - 0x%08x, val - 0x%08x",
741 (u32) & ugeth->ug_regs->rxfok,
742 in_be32(&ugeth->ug_regs->rxfok));
743 ugeth_info("rxbok : addr - 0x%08x, val - 0x%08x",
744 (u32) & ugeth->ug_regs->rxbok,
745 in_be32(&ugeth->ug_regs->rxbok));
746 ugeth_info("rbyt : addr - 0x%08x, val - 0x%08x",
747 (u32) & ugeth->ug_regs->rbyt,
748 in_be32(&ugeth->ug_regs->rbyt));
749 ugeth_info("rmca : addr - 0x%08x, val - 0x%08x",
750 (u32) & ugeth->ug_regs->rmca,
751 in_be32(&ugeth->ug_regs->rmca));
752 ugeth_info("rbca : addr - 0x%08x, val - 0x%08x",
753 (u32) & ugeth->ug_regs->rbca,
754 in_be32(&ugeth->ug_regs->rbca));
755 ugeth_info("scar : addr - 0x%08x, val - 0x%08x",
756 (u32) & ugeth->ug_regs->scar,
757 in_be32(&ugeth->ug_regs->scar));
758 ugeth_info("scam : addr - 0x%08x, val - 0x%08x",
759 (u32) & ugeth->ug_regs->scam,
760 in_be32(&ugeth->ug_regs->scam));
761
762 if (ugeth->p_thread_data_tx) {
763 int numThreadsTxNumerical;
764 switch (ugeth->ug_info->numThreadsTx) {
765 case UCC_GETH_NUM_OF_THREADS_1:
766 numThreadsTxNumerical = 1;
767 break;
768 case UCC_GETH_NUM_OF_THREADS_2:
769 numThreadsTxNumerical = 2;
770 break;
771 case UCC_GETH_NUM_OF_THREADS_4:
772 numThreadsTxNumerical = 4;
773 break;
774 case UCC_GETH_NUM_OF_THREADS_6:
775 numThreadsTxNumerical = 6;
776 break;
777 case UCC_GETH_NUM_OF_THREADS_8:
778 numThreadsTxNumerical = 8;
779 break;
780 default:
781 numThreadsTxNumerical = 0;
782 break;
783 }
784
785 ugeth_info("Thread data TXs:");
786 ugeth_info("Base address: 0x%08x",
787 (u32) ugeth->p_thread_data_tx);
788 for (i = 0; i < numThreadsTxNumerical; i++) {
789 ugeth_info("Thread data TX[%d]:", i);
790 ugeth_info("Base address: 0x%08x",
791 (u32) & ugeth->p_thread_data_tx[i]);
792 mem_disp((u8 *) & ugeth->p_thread_data_tx[i],
793 sizeof(struct ucc_geth_thread_data_tx));
794 }
795 }
796 if (ugeth->p_thread_data_rx) {
797 int numThreadsRxNumerical;
798 switch (ugeth->ug_info->numThreadsRx) {
799 case UCC_GETH_NUM_OF_THREADS_1:
800 numThreadsRxNumerical = 1;
801 break;
802 case UCC_GETH_NUM_OF_THREADS_2:
803 numThreadsRxNumerical = 2;
804 break;
805 case UCC_GETH_NUM_OF_THREADS_4:
806 numThreadsRxNumerical = 4;
807 break;
808 case UCC_GETH_NUM_OF_THREADS_6:
809 numThreadsRxNumerical = 6;
810 break;
811 case UCC_GETH_NUM_OF_THREADS_8:
812 numThreadsRxNumerical = 8;
813 break;
814 default:
815 numThreadsRxNumerical = 0;
816 break;
817 }
818
819 ugeth_info("Thread data RX:");
820 ugeth_info("Base address: 0x%08x",
821 (u32) ugeth->p_thread_data_rx);
822 for (i = 0; i < numThreadsRxNumerical; i++) {
823 ugeth_info("Thread data RX[%d]:", i);
824 ugeth_info("Base address: 0x%08x",
825 (u32) & ugeth->p_thread_data_rx[i]);
826 mem_disp((u8 *) & ugeth->p_thread_data_rx[i],
827 sizeof(struct ucc_geth_thread_data_rx));
828 }
829 }
830 if (ugeth->p_exf_glbl_param) {
831 ugeth_info("EXF global param:");
832 ugeth_info("Base address: 0x%08x",
833 (u32) ugeth->p_exf_glbl_param);
834 mem_disp((u8 *) ugeth->p_exf_glbl_param,
835 sizeof(*ugeth->p_exf_glbl_param));
836 }
837 if (ugeth->p_tx_glbl_pram) {
838 ugeth_info("TX global param:");
839 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_tx_glbl_pram);
840 ugeth_info("temoder : addr - 0x%08x, val - 0x%04x",
841 (u32) & ugeth->p_tx_glbl_pram->temoder,
842 in_be16(&ugeth->p_tx_glbl_pram->temoder));
843 ugeth_info("sqptr : addr - 0x%08x, val - 0x%08x",
844 (u32) & ugeth->p_tx_glbl_pram->sqptr,
845 in_be32(&ugeth->p_tx_glbl_pram->sqptr));
846 ugeth_info("schedulerbasepointer: addr - 0x%08x, val - 0x%08x",
847 (u32) & ugeth->p_tx_glbl_pram->schedulerbasepointer,
848 in_be32(&ugeth->p_tx_glbl_pram->
849 schedulerbasepointer));
850 ugeth_info("txrmonbaseptr: addr - 0x%08x, val - 0x%08x",
851 (u32) & ugeth->p_tx_glbl_pram->txrmonbaseptr,
852 in_be32(&ugeth->p_tx_glbl_pram->txrmonbaseptr));
853 ugeth_info("tstate : addr - 0x%08x, val - 0x%08x",
854 (u32) & ugeth->p_tx_glbl_pram->tstate,
855 in_be32(&ugeth->p_tx_glbl_pram->tstate));
856 ugeth_info("iphoffset[0] : addr - 0x%08x, val - 0x%02x",
857 (u32) & ugeth->p_tx_glbl_pram->iphoffset[0],
858 ugeth->p_tx_glbl_pram->iphoffset[0]);
859 ugeth_info("iphoffset[1] : addr - 0x%08x, val - 0x%02x",
860 (u32) & ugeth->p_tx_glbl_pram->iphoffset[1],
861 ugeth->p_tx_glbl_pram->iphoffset[1]);
862 ugeth_info("iphoffset[2] : addr - 0x%08x, val - 0x%02x",
863 (u32) & ugeth->p_tx_glbl_pram->iphoffset[2],
864 ugeth->p_tx_glbl_pram->iphoffset[2]);
865 ugeth_info("iphoffset[3] : addr - 0x%08x, val - 0x%02x",
866 (u32) & ugeth->p_tx_glbl_pram->iphoffset[3],
867 ugeth->p_tx_glbl_pram->iphoffset[3]);
868 ugeth_info("iphoffset[4] : addr - 0x%08x, val - 0x%02x",
869 (u32) & ugeth->p_tx_glbl_pram->iphoffset[4],
870 ugeth->p_tx_glbl_pram->iphoffset[4]);
871 ugeth_info("iphoffset[5] : addr - 0x%08x, val - 0x%02x",
872 (u32) & ugeth->p_tx_glbl_pram->iphoffset[5],
873 ugeth->p_tx_glbl_pram->iphoffset[5]);
874 ugeth_info("iphoffset[6] : addr - 0x%08x, val - 0x%02x",
875 (u32) & ugeth->p_tx_glbl_pram->iphoffset[6],
876 ugeth->p_tx_glbl_pram->iphoffset[6]);
877 ugeth_info("iphoffset[7] : addr - 0x%08x, val - 0x%02x",
878 (u32) & ugeth->p_tx_glbl_pram->iphoffset[7],
879 ugeth->p_tx_glbl_pram->iphoffset[7]);
880 ugeth_info("vtagtable[0] : addr - 0x%08x, val - 0x%08x",
881 (u32) & ugeth->p_tx_glbl_pram->vtagtable[0],
882 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[0]));
883 ugeth_info("vtagtable[1] : addr - 0x%08x, val - 0x%08x",
884 (u32) & ugeth->p_tx_glbl_pram->vtagtable[1],
885 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[1]));
886 ugeth_info("vtagtable[2] : addr - 0x%08x, val - 0x%08x",
887 (u32) & ugeth->p_tx_glbl_pram->vtagtable[2],
888 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[2]));
889 ugeth_info("vtagtable[3] : addr - 0x%08x, val - 0x%08x",
890 (u32) & ugeth->p_tx_glbl_pram->vtagtable[3],
891 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[3]));
892 ugeth_info("vtagtable[4] : addr - 0x%08x, val - 0x%08x",
893 (u32) & ugeth->p_tx_glbl_pram->vtagtable[4],
894 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[4]));
895 ugeth_info("vtagtable[5] : addr - 0x%08x, val - 0x%08x",
896 (u32) & ugeth->p_tx_glbl_pram->vtagtable[5],
897 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[5]));
898 ugeth_info("vtagtable[6] : addr - 0x%08x, val - 0x%08x",
899 (u32) & ugeth->p_tx_glbl_pram->vtagtable[6],
900 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[6]));
901 ugeth_info("vtagtable[7] : addr - 0x%08x, val - 0x%08x",
902 (u32) & ugeth->p_tx_glbl_pram->vtagtable[7],
903 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[7]));
904 ugeth_info("tqptr : addr - 0x%08x, val - 0x%08x",
905 (u32) & ugeth->p_tx_glbl_pram->tqptr,
906 in_be32(&ugeth->p_tx_glbl_pram->tqptr));
907 }
908 if (ugeth->p_rx_glbl_pram) {
909 ugeth_info("RX global param:");
910 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_glbl_pram);
911 ugeth_info("remoder : addr - 0x%08x, val - 0x%08x",
912 (u32) & ugeth->p_rx_glbl_pram->remoder,
913 in_be32(&ugeth->p_rx_glbl_pram->remoder));
914 ugeth_info("rqptr : addr - 0x%08x, val - 0x%08x",
915 (u32) & ugeth->p_rx_glbl_pram->rqptr,
916 in_be32(&ugeth->p_rx_glbl_pram->rqptr));
917 ugeth_info("typeorlen : addr - 0x%08x, val - 0x%04x",
918 (u32) & ugeth->p_rx_glbl_pram->typeorlen,
919 in_be16(&ugeth->p_rx_glbl_pram->typeorlen));
920 ugeth_info("rxgstpack : addr - 0x%08x, val - 0x%02x",
921 (u32) & ugeth->p_rx_glbl_pram->rxgstpack,
922 ugeth->p_rx_glbl_pram->rxgstpack);
923 ugeth_info("rxrmonbaseptr : addr - 0x%08x, val - 0x%08x",
924 (u32) & ugeth->p_rx_glbl_pram->rxrmonbaseptr,
925 in_be32(&ugeth->p_rx_glbl_pram->rxrmonbaseptr));
926 ugeth_info("intcoalescingptr: addr - 0x%08x, val - 0x%08x",
927 (u32) & ugeth->p_rx_glbl_pram->intcoalescingptr,
928 in_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr));
929 ugeth_info("rstate : addr - 0x%08x, val - 0x%02x",
930 (u32) & ugeth->p_rx_glbl_pram->rstate,
931 ugeth->p_rx_glbl_pram->rstate);
932 ugeth_info("mrblr : addr - 0x%08x, val - 0x%04x",
933 (u32) & ugeth->p_rx_glbl_pram->mrblr,
934 in_be16(&ugeth->p_rx_glbl_pram->mrblr));
935 ugeth_info("rbdqptr : addr - 0x%08x, val - 0x%08x",
936 (u32) & ugeth->p_rx_glbl_pram->rbdqptr,
937 in_be32(&ugeth->p_rx_glbl_pram->rbdqptr));
938 ugeth_info("mflr : addr - 0x%08x, val - 0x%04x",
939 (u32) & ugeth->p_rx_glbl_pram->mflr,
940 in_be16(&ugeth->p_rx_glbl_pram->mflr));
941 ugeth_info("minflr : addr - 0x%08x, val - 0x%04x",
942 (u32) & ugeth->p_rx_glbl_pram->minflr,
943 in_be16(&ugeth->p_rx_glbl_pram->minflr));
944 ugeth_info("maxd1 : addr - 0x%08x, val - 0x%04x",
945 (u32) & ugeth->p_rx_glbl_pram->maxd1,
946 in_be16(&ugeth->p_rx_glbl_pram->maxd1));
947 ugeth_info("maxd2 : addr - 0x%08x, val - 0x%04x",
948 (u32) & ugeth->p_rx_glbl_pram->maxd2,
949 in_be16(&ugeth->p_rx_glbl_pram->maxd2));
950 ugeth_info("ecamptr : addr - 0x%08x, val - 0x%08x",
951 (u32) & ugeth->p_rx_glbl_pram->ecamptr,
952 in_be32(&ugeth->p_rx_glbl_pram->ecamptr));
953 ugeth_info("l2qt : addr - 0x%08x, val - 0x%08x",
954 (u32) & ugeth->p_rx_glbl_pram->l2qt,
955 in_be32(&ugeth->p_rx_glbl_pram->l2qt));
956 ugeth_info("l3qt[0] : addr - 0x%08x, val - 0x%08x",
957 (u32) & ugeth->p_rx_glbl_pram->l3qt[0],
958 in_be32(&ugeth->p_rx_glbl_pram->l3qt[0]));
959 ugeth_info("l3qt[1] : addr - 0x%08x, val - 0x%08x",
960 (u32) & ugeth->p_rx_glbl_pram->l3qt[1],
961 in_be32(&ugeth->p_rx_glbl_pram->l3qt[1]));
962 ugeth_info("l3qt[2] : addr - 0x%08x, val - 0x%08x",
963 (u32) & ugeth->p_rx_glbl_pram->l3qt[2],
964 in_be32(&ugeth->p_rx_glbl_pram->l3qt[2]));
965 ugeth_info("l3qt[3] : addr - 0x%08x, val - 0x%08x",
966 (u32) & ugeth->p_rx_glbl_pram->l3qt[3],
967 in_be32(&ugeth->p_rx_glbl_pram->l3qt[3]));
968 ugeth_info("l3qt[4] : addr - 0x%08x, val - 0x%08x",
969 (u32) & ugeth->p_rx_glbl_pram->l3qt[4],
970 in_be32(&ugeth->p_rx_glbl_pram->l3qt[4]));
971 ugeth_info("l3qt[5] : addr - 0x%08x, val - 0x%08x",
972 (u32) & ugeth->p_rx_glbl_pram->l3qt[5],
973 in_be32(&ugeth->p_rx_glbl_pram->l3qt[5]));
974 ugeth_info("l3qt[6] : addr - 0x%08x, val - 0x%08x",
975 (u32) & ugeth->p_rx_glbl_pram->l3qt[6],
976 in_be32(&ugeth->p_rx_glbl_pram->l3qt[6]));
977 ugeth_info("l3qt[7] : addr - 0x%08x, val - 0x%08x",
978 (u32) & ugeth->p_rx_glbl_pram->l3qt[7],
979 in_be32(&ugeth->p_rx_glbl_pram->l3qt[7]));
980 ugeth_info("vlantype : addr - 0x%08x, val - 0x%04x",
981 (u32) & ugeth->p_rx_glbl_pram->vlantype,
982 in_be16(&ugeth->p_rx_glbl_pram->vlantype));
983 ugeth_info("vlantci : addr - 0x%08x, val - 0x%04x",
984 (u32) & ugeth->p_rx_glbl_pram->vlantci,
985 in_be16(&ugeth->p_rx_glbl_pram->vlantci));
986 for (i = 0; i < 64; i++)
987 ugeth_info
988 ("addressfiltering[%d]: addr - 0x%08x, val - 0x%02x",
989 i,
990 (u32) & ugeth->p_rx_glbl_pram->addressfiltering[i],
991 ugeth->p_rx_glbl_pram->addressfiltering[i]);
992 ugeth_info("exfGlobalParam : addr - 0x%08x, val - 0x%08x",
993 (u32) & ugeth->p_rx_glbl_pram->exfGlobalParam,
994 in_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam));
995 }
996 if (ugeth->p_send_q_mem_reg) {
997 ugeth_info("Send Q memory registers:");
998 ugeth_info("Base address: 0x%08x",
999 (u32) ugeth->p_send_q_mem_reg);
1000 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
1001 ugeth_info("SQQD[%d]:", i);
1002 ugeth_info("Base address: 0x%08x",
1003 (u32) & ugeth->p_send_q_mem_reg->sqqd[i]);
1004 mem_disp((u8 *) & ugeth->p_send_q_mem_reg->sqqd[i],
1005 sizeof(struct ucc_geth_send_queue_qd));
1006 }
1007 }
1008 if (ugeth->p_scheduler) {
1009 ugeth_info("Scheduler:");
1010 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_scheduler);
1011 mem_disp((u8 *) ugeth->p_scheduler,
1012 sizeof(*ugeth->p_scheduler));
1013 }
1014 if (ugeth->p_tx_fw_statistics_pram) {
1015 ugeth_info("TX FW statistics pram:");
1016 ugeth_info("Base address: 0x%08x",
1017 (u32) ugeth->p_tx_fw_statistics_pram);
1018 mem_disp((u8 *) ugeth->p_tx_fw_statistics_pram,
1019 sizeof(*ugeth->p_tx_fw_statistics_pram));
1020 }
1021 if (ugeth->p_rx_fw_statistics_pram) {
1022 ugeth_info("RX FW statistics pram:");
1023 ugeth_info("Base address: 0x%08x",
1024 (u32) ugeth->p_rx_fw_statistics_pram);
1025 mem_disp((u8 *) ugeth->p_rx_fw_statistics_pram,
1026 sizeof(*ugeth->p_rx_fw_statistics_pram));
1027 }
1028 if (ugeth->p_rx_irq_coalescing_tbl) {
1029 ugeth_info("RX IRQ coalescing tables:");
1030 ugeth_info("Base address: 0x%08x",
1031 (u32) ugeth->p_rx_irq_coalescing_tbl);
1032 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
1033 ugeth_info("RX IRQ coalescing table entry[%d]:", i);
1034 ugeth_info("Base address: 0x%08x",
1035 (u32) & ugeth->p_rx_irq_coalescing_tbl->
1036 coalescingentry[i]);
1037 ugeth_info
1038 ("interruptcoalescingmaxvalue: addr - 0x%08x, val - 0x%08x",
1039 (u32) & ugeth->p_rx_irq_coalescing_tbl->
1040 coalescingentry[i].interruptcoalescingmaxvalue,
1041 in_be32(&ugeth->p_rx_irq_coalescing_tbl->
1042 coalescingentry[i].
1043 interruptcoalescingmaxvalue));
1044 ugeth_info
1045 ("interruptcoalescingcounter : addr - 0x%08x, val - 0x%08x",
1046 (u32) & ugeth->p_rx_irq_coalescing_tbl->
1047 coalescingentry[i].interruptcoalescingcounter,
1048 in_be32(&ugeth->p_rx_irq_coalescing_tbl->
1049 coalescingentry[i].
1050 interruptcoalescingcounter));
1051 }
1052 }
1053 if (ugeth->p_rx_bd_qs_tbl) {
1054 ugeth_info("RX BD QS tables:");
1055 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_bd_qs_tbl);
1056 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
1057 ugeth_info("RX BD QS table[%d]:", i);
1058 ugeth_info("Base address: 0x%08x",
1059 (u32) & ugeth->p_rx_bd_qs_tbl[i]);
1060 ugeth_info
1061 ("bdbaseptr : addr - 0x%08x, val - 0x%08x",
1062 (u32) & ugeth->p_rx_bd_qs_tbl[i].bdbaseptr,
1063 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr));
1064 ugeth_info
1065 ("bdptr : addr - 0x%08x, val - 0x%08x",
1066 (u32) & ugeth->p_rx_bd_qs_tbl[i].bdptr,
1067 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdptr));
1068 ugeth_info
1069 ("externalbdbaseptr: addr - 0x%08x, val - 0x%08x",
1070 (u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
1071 in_be32(&ugeth->p_rx_bd_qs_tbl[i].
1072 externalbdbaseptr));
1073 ugeth_info
1074 ("externalbdptr : addr - 0x%08x, val - 0x%08x",
1075 (u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdptr,
1076 in_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdptr));
1077 ugeth_info("ucode RX Prefetched BDs:");
1078 ugeth_info("Base address: 0x%08x",
1079 (u32)
1080 qe_muram_addr(in_be32
1081 (&ugeth->p_rx_bd_qs_tbl[i].
1082 bdbaseptr)));
1083 mem_disp((u8 *)
1084 qe_muram_addr(in_be32
1085 (&ugeth->p_rx_bd_qs_tbl[i].
1086 bdbaseptr)),
1087 sizeof(struct ucc_geth_rx_prefetched_bds));
1088 }
1089 }
1090 if (ugeth->p_init_enet_param_shadow) {
1091 int size;
1092 ugeth_info("Init enet param shadow:");
1093 ugeth_info("Base address: 0x%08x",
1094 (u32) ugeth->p_init_enet_param_shadow);
1095 mem_disp((u8 *) ugeth->p_init_enet_param_shadow,
1096 sizeof(*ugeth->p_init_enet_param_shadow));
1097
1098 size = sizeof(struct ucc_geth_thread_rx_pram);
1099 if (ugeth->ug_info->rxExtendedFiltering) {
1100 size +=
1101 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
1102 if (ugeth->ug_info->largestexternallookupkeysize ==
1103 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
1104 size +=
1105 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
1106 if (ugeth->ug_info->largestexternallookupkeysize ==
1107 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
1108 size +=
1109 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
1110 }
1111
1112 dump_init_enet_entries(ugeth,
1113 &(ugeth->p_init_enet_param_shadow->
1114 txthread[0]),
1115 ENET_INIT_PARAM_MAX_ENTRIES_TX,
1116 sizeof(struct ucc_geth_thread_tx_pram),
1117 ugeth->ug_info->riscTx, 0);
1118 dump_init_enet_entries(ugeth,
1119 &(ugeth->p_init_enet_param_shadow->
1120 rxthread[0]),
1121 ENET_INIT_PARAM_MAX_ENTRIES_RX, size,
1122 ugeth->ug_info->riscRx, 1);
1123 }
1124 }
1125 #endif /* DEBUG */
1126
1127 static void init_default_reg_vals(volatile u32 *upsmr_register,
1128 volatile u32 *maccfg1_register,
1129 volatile u32 *maccfg2_register)
1130 {
1131 out_be32(upsmr_register, UCC_GETH_UPSMR_INIT);
1132 out_be32(maccfg1_register, UCC_GETH_MACCFG1_INIT);
1133 out_be32(maccfg2_register, UCC_GETH_MACCFG2_INIT);
1134 }
1135
1136 static int init_half_duplex_params(int alt_beb,
1137 int back_pressure_no_backoff,
1138 int no_backoff,
1139 int excess_defer,
1140 u8 alt_beb_truncation,
1141 u8 max_retransmissions,
1142 u8 collision_window,
1143 volatile u32 *hafdup_register)
1144 {
1145 u32 value = 0;
1146
1147 if ((alt_beb_truncation > HALFDUP_ALT_BEB_TRUNCATION_MAX) ||
1148 (max_retransmissions > HALFDUP_MAX_RETRANSMISSION_MAX) ||
1149 (collision_window > HALFDUP_COLLISION_WINDOW_MAX))
1150 return -EINVAL;
1151
1152 value = (u32) (alt_beb_truncation << HALFDUP_ALT_BEB_TRUNCATION_SHIFT);
1153
1154 if (alt_beb)
1155 value |= HALFDUP_ALT_BEB;
1156 if (back_pressure_no_backoff)
1157 value |= HALFDUP_BACK_PRESSURE_NO_BACKOFF;
1158 if (no_backoff)
1159 value |= HALFDUP_NO_BACKOFF;
1160 if (excess_defer)
1161 value |= HALFDUP_EXCESSIVE_DEFER;
1162
1163 value |= (max_retransmissions << HALFDUP_MAX_RETRANSMISSION_SHIFT);
1164
1165 value |= collision_window;
1166
1167 out_be32(hafdup_register, value);
1168 return 0;
1169 }
1170
1171 static int init_inter_frame_gap_params(u8 non_btb_cs_ipg,
1172 u8 non_btb_ipg,
1173 u8 min_ifg,
1174 u8 btb_ipg,
1175 volatile u32 *ipgifg_register)
1176 {
1177 u32 value = 0;
1178
1179 /* Non-Back-to-back IPG part 1 should be <= Non-Back-to-back
1180 IPG part 2 */
1181 if (non_btb_cs_ipg > non_btb_ipg)
1182 return -EINVAL;
1183
1184 if ((non_btb_cs_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX) ||
1185 (non_btb_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX) ||
1186 /*(min_ifg > IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX) || */
1187 (btb_ipg > IPGIFG_BACK_TO_BACK_IFG_MAX))
1188 return -EINVAL;
1189
1190 value |=
1191 ((non_btb_cs_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT) &
1192 IPGIFG_NBTB_CS_IPG_MASK);
1193 value |=
1194 ((non_btb_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT) &
1195 IPGIFG_NBTB_IPG_MASK);
1196 value |=
1197 ((min_ifg << IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT) &
1198 IPGIFG_MIN_IFG_MASK);
1199 value |= (btb_ipg & IPGIFG_BTB_IPG_MASK);
1200
1201 out_be32(ipgifg_register, value);
1202 return 0;
1203 }
1204
1205 static int init_flow_control_params(u32 automatic_flow_control_mode,
1206 int rx_flow_control_enable,
1207 int tx_flow_control_enable,
1208 u16 pause_period,
1209 u16 extension_field,
1210 volatile u32 *upsmr_register,
1211 volatile u32 *uempr_register,
1212 volatile u32 *maccfg1_register)
1213 {
1214 u32 value = 0;
1215
1216 /* Set UEMPR register */
1217 value = (u32) pause_period << UEMPR_PAUSE_TIME_VALUE_SHIFT;
1218 value |= (u32) extension_field << UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT;
1219 out_be32(uempr_register, value);
1220
1221 /* Set UPSMR register */
1222 value = in_be32(upsmr_register);
1223 value |= automatic_flow_control_mode;
1224 out_be32(upsmr_register, value);
1225
1226 value = in_be32(maccfg1_register);
1227 if (rx_flow_control_enable)
1228 value |= MACCFG1_FLOW_RX;
1229 if (tx_flow_control_enable)
1230 value |= MACCFG1_FLOW_TX;
1231 out_be32(maccfg1_register, value);
1232
1233 return 0;
1234 }
1235
1236 static int init_hw_statistics_gathering_mode(int enable_hardware_statistics,
1237 int auto_zero_hardware_statistics,
1238 volatile u32 *upsmr_register,
1239 volatile u16 *uescr_register)
1240 {
1241 u32 upsmr_value = 0;
1242 u16 uescr_value = 0;
1243 /* Enable hardware statistics gathering if requested */
1244 if (enable_hardware_statistics) {
1245 upsmr_value = in_be32(upsmr_register);
1246 upsmr_value |= UPSMR_HSE;
1247 out_be32(upsmr_register, upsmr_value);
1248 }
1249
1250 /* Clear hardware statistics counters */
1251 uescr_value = in_be16(uescr_register);
1252 uescr_value |= UESCR_CLRCNT;
1253 /* Automatically zero hardware statistics counters on read,
1254 if requested */
1255 if (auto_zero_hardware_statistics)
1256 uescr_value |= UESCR_AUTOZ;
1257 out_be16(uescr_register, uescr_value);
1258
1259 return 0;
1260 }
1261
1262 static int init_firmware_statistics_gathering_mode(int
1263 enable_tx_firmware_statistics,
1264 int enable_rx_firmware_statistics,
1265 volatile u32 *tx_rmon_base_ptr,
1266 u32 tx_firmware_statistics_structure_address,
1267 volatile u32 *rx_rmon_base_ptr,
1268 u32 rx_firmware_statistics_structure_address,
1269 volatile u16 *temoder_register,
1270 volatile u32 *remoder_register)
1271 {
1272 /* Note: this function does not check if */
1273 /* the parameters it receives are NULL */
1274 u16 temoder_value;
1275 u32 remoder_value;
1276
1277 if (enable_tx_firmware_statistics) {
1278 out_be32(tx_rmon_base_ptr,
1279 tx_firmware_statistics_structure_address);
1280 temoder_value = in_be16(temoder_register);
1281 temoder_value |= TEMODER_TX_RMON_STATISTICS_ENABLE;
1282 out_be16(temoder_register, temoder_value);
1283 }
1284
1285 if (enable_rx_firmware_statistics) {
1286 out_be32(rx_rmon_base_ptr,
1287 rx_firmware_statistics_structure_address);
1288 remoder_value = in_be32(remoder_register);
1289 remoder_value |= REMODER_RX_RMON_STATISTICS_ENABLE;
1290 out_be32(remoder_register, remoder_value);
1291 }
1292
1293 return 0;
1294 }
1295
1296 static int init_mac_station_addr_regs(u8 address_byte_0,
1297 u8 address_byte_1,
1298 u8 address_byte_2,
1299 u8 address_byte_3,
1300 u8 address_byte_4,
1301 u8 address_byte_5,
1302 volatile u32 *macstnaddr1_register,
1303 volatile u32 *macstnaddr2_register)
1304 {
1305 u32 value = 0;
1306
1307 /* Example: for a station address of 0x12345678ABCD, */
1308 /* 0x12 is byte 0, 0x34 is byte 1 and so on and 0xCD is byte 5 */
1309
1310 /* MACSTNADDR1 Register: */
1311
1312 /* 0 7 8 15 */
1313 /* station address byte 5 station address byte 4 */
1314 /* 16 23 24 31 */
1315 /* station address byte 3 station address byte 2 */
1316 value |= (u32) ((address_byte_2 << 0) & 0x000000FF);
1317 value |= (u32) ((address_byte_3 << 8) & 0x0000FF00);
1318 value |= (u32) ((address_byte_4 << 16) & 0x00FF0000);
1319 value |= (u32) ((address_byte_5 << 24) & 0xFF000000);
1320
1321 out_be32(macstnaddr1_register, value);
1322
1323 /* MACSTNADDR2 Register: */
1324
1325 /* 0 7 8 15 */
1326 /* station address byte 1 station address byte 0 */
1327 /* 16 23 24 31 */
1328 /* reserved reserved */
1329 value = 0;
1330 value |= (u32) ((address_byte_0 << 16) & 0x00FF0000);
1331 value |= (u32) ((address_byte_1 << 24) & 0xFF000000);
1332
1333 out_be32(macstnaddr2_register, value);
1334
1335 return 0;
1336 }
1337
1338 static int init_check_frame_length_mode(int length_check,
1339 volatile u32 *maccfg2_register)
1340 {
1341 u32 value = 0;
1342
1343 value = in_be32(maccfg2_register);
1344
1345 if (length_check)
1346 value |= MACCFG2_LC;
1347 else
1348 value &= ~MACCFG2_LC;
1349
1350 out_be32(maccfg2_register, value);
1351 return 0;
1352 }
1353
1354 static int init_preamble_length(u8 preamble_length,
1355 volatile u32 *maccfg2_register)
1356 {
1357 u32 value = 0;
1358
1359 if ((preamble_length < 3) || (preamble_length > 7))
1360 return -EINVAL;
1361
1362 value = in_be32(maccfg2_register);
1363 value &= ~MACCFG2_PREL_MASK;
1364 value |= (preamble_length << MACCFG2_PREL_SHIFT);
1365 out_be32(maccfg2_register, value);
1366 return 0;
1367 }
1368
1369 static int init_rx_parameters(int reject_broadcast,
1370 int receive_short_frames,
1371 int promiscuous, volatile u32 *upsmr_register)
1372 {
1373 u32 value = 0;
1374
1375 value = in_be32(upsmr_register);
1376
1377 if (reject_broadcast)
1378 value |= UPSMR_BRO;
1379 else
1380 value &= ~UPSMR_BRO;
1381
1382 if (receive_short_frames)
1383 value |= UPSMR_RSH;
1384 else
1385 value &= ~UPSMR_RSH;
1386
1387 if (promiscuous)
1388 value |= UPSMR_PRO;
1389 else
1390 value &= ~UPSMR_PRO;
1391
1392 out_be32(upsmr_register, value);
1393
1394 return 0;
1395 }
1396
1397 static int init_max_rx_buff_len(u16 max_rx_buf_len,
1398 volatile u16 *mrblr_register)
1399 {
1400 /* max_rx_buf_len value must be a multiple of 128 */
1401 if ((max_rx_buf_len == 0)
1402 || (max_rx_buf_len % UCC_GETH_MRBLR_ALIGNMENT))
1403 return -EINVAL;
1404
1405 out_be16(mrblr_register, max_rx_buf_len);
1406 return 0;
1407 }
1408
1409 static int init_min_frame_len(u16 min_frame_length,
1410 volatile u16 *minflr_register,
1411 volatile u16 *mrblr_register)
1412 {
1413 u16 mrblr_value = 0;
1414
1415 mrblr_value = in_be16(mrblr_register);
1416 if (min_frame_length >= (mrblr_value - 4))
1417 return -EINVAL;
1418
1419 out_be16(minflr_register, min_frame_length);
1420 return 0;
1421 }
1422
1423 static int adjust_enet_interface(struct ucc_geth_private *ugeth)
1424 {
1425 struct ucc_geth_info *ug_info;
1426 struct ucc_geth *ug_regs;
1427 struct ucc_fast *uf_regs;
1428 int ret_val;
1429 u32 upsmr, maccfg2, tbiBaseAddress;
1430 u16 value;
1431
1432 ugeth_vdbg("%s: IN", __FUNCTION__);
1433
1434 ug_info = ugeth->ug_info;
1435 ug_regs = ugeth->ug_regs;
1436 uf_regs = ugeth->uccf->uf_regs;
1437
1438 /* Set MACCFG2 */
1439 maccfg2 = in_be32(&ug_regs->maccfg2);
1440 maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
1441 if ((ugeth->max_speed == SPEED_10) ||
1442 (ugeth->max_speed == SPEED_100))
1443 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
1444 else if (ugeth->max_speed == SPEED_1000)
1445 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
1446 maccfg2 |= ug_info->padAndCrc;
1447 out_be32(&ug_regs->maccfg2, maccfg2);
1448
1449 /* Set UPSMR */
1450 upsmr = in_be32(&uf_regs->upsmr);
1451 upsmr &= ~(UPSMR_RPM | UPSMR_R10M | UPSMR_TBIM | UPSMR_RMM);
1452 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1453 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1454 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1455 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1456 upsmr |= UPSMR_RPM;
1457 switch (ugeth->max_speed) {
1458 case SPEED_10:
1459 upsmr |= UPSMR_R10M;
1460 /* FALLTHROUGH */
1461 case SPEED_100:
1462 if (ugeth->phy_interface != PHY_INTERFACE_MODE_RTBI)
1463 upsmr |= UPSMR_RMM;
1464 }
1465 }
1466 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1467 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1468 upsmr |= UPSMR_TBIM;
1469 }
1470 out_be32(&uf_regs->upsmr, upsmr);
1471
1472 /* Disable autonegotiation in tbi mode, because by default it
1473 comes up in autonegotiation mode. */
1474 /* Note that this depends on proper setting in utbipar register. */
1475 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1476 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1477 tbiBaseAddress = in_be32(&ug_regs->utbipar);
1478 tbiBaseAddress &= UTBIPAR_PHY_ADDRESS_MASK;
1479 tbiBaseAddress >>= UTBIPAR_PHY_ADDRESS_SHIFT;
1480 value = ugeth->phydev->bus->read(ugeth->phydev->bus,
1481 (u8) tbiBaseAddress, ENET_TBI_MII_CR);
1482 value &= ~0x1000; /* Turn off autonegotiation */
1483 ugeth->phydev->bus->write(ugeth->phydev->bus,
1484 (u8) tbiBaseAddress, ENET_TBI_MII_CR, value);
1485 }
1486
1487 init_check_frame_length_mode(ug_info->lengthCheckRx, &ug_regs->maccfg2);
1488
1489 ret_val = init_preamble_length(ug_info->prel, &ug_regs->maccfg2);
1490 if (ret_val != 0) {
1491 ugeth_err
1492 ("%s: Preamble length must be between 3 and 7 inclusive.",
1493 __FUNCTION__);
1494 return ret_val;
1495 }
1496
1497 return 0;
1498 }
1499
1500 /* Called every time the controller might need to be made
1501 * aware of new link state. The PHY code conveys this
1502 * information through variables in the ugeth structure, and this
1503 * function converts those variables into the appropriate
1504 * register values, and can bring down the device if needed.
1505 */
1506
1507 static void adjust_link(struct net_device *dev)
1508 {
1509 struct ucc_geth_private *ugeth = netdev_priv(dev);
1510 struct ucc_geth *ug_regs;
1511 struct ucc_fast *uf_regs;
1512 struct phy_device *phydev = ugeth->phydev;
1513 unsigned long flags;
1514 int new_state = 0;
1515
1516 ug_regs = ugeth->ug_regs;
1517 uf_regs = ugeth->uccf->uf_regs;
1518
1519 spin_lock_irqsave(&ugeth->lock, flags);
1520
1521 if (phydev->link) {
1522 u32 tempval = in_be32(&ug_regs->maccfg2);
1523 u32 upsmr = in_be32(&uf_regs->upsmr);
1524 /* Now we make sure that we can be in full duplex mode.
1525 * If not, we operate in half-duplex mode. */
1526 if (phydev->duplex != ugeth->oldduplex) {
1527 new_state = 1;
1528 if (!(phydev->duplex))
1529 tempval &= ~(MACCFG2_FDX);
1530 else
1531 tempval |= MACCFG2_FDX;
1532 ugeth->oldduplex = phydev->duplex;
1533 }
1534
1535 if (phydev->speed != ugeth->oldspeed) {
1536 new_state = 1;
1537 switch (phydev->speed) {
1538 case SPEED_1000:
1539 tempval = ((tempval &
1540 ~(MACCFG2_INTERFACE_MODE_MASK)) |
1541 MACCFG2_INTERFACE_MODE_BYTE);
1542 break;
1543 case SPEED_100:
1544 case SPEED_10:
1545 tempval = ((tempval &
1546 ~(MACCFG2_INTERFACE_MODE_MASK)) |
1547 MACCFG2_INTERFACE_MODE_NIBBLE);
1548 /* if reduced mode, re-set UPSMR.R10M */
1549 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1550 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1551 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1552 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1553 if (phydev->speed == SPEED_10)
1554 upsmr |= UPSMR_R10M;
1555 else
1556 upsmr &= ~(UPSMR_R10M);
1557 }
1558 break;
1559 default:
1560 if (netif_msg_link(ugeth))
1561 ugeth_warn(
1562 "%s: Ack! Speed (%d) is not 10/100/1000!",
1563 dev->name, phydev->speed);
1564 break;
1565 }
1566 ugeth->oldspeed = phydev->speed;
1567 }
1568
1569 out_be32(&ug_regs->maccfg2, tempval);
1570 out_be32(&uf_regs->upsmr, upsmr);
1571
1572 if (!ugeth->oldlink) {
1573 new_state = 1;
1574 ugeth->oldlink = 1;
1575 netif_schedule(dev);
1576 }
1577 } else if (ugeth->oldlink) {
1578 new_state = 1;
1579 ugeth->oldlink = 0;
1580 ugeth->oldspeed = 0;
1581 ugeth->oldduplex = -1;
1582 }
1583
1584 if (new_state && netif_msg_link(ugeth))
1585 phy_print_status(phydev);
1586
1587 spin_unlock_irqrestore(&ugeth->lock, flags);
1588 }
1589
1590 /* Configure the PHY for dev.
1591 * returns 0 if success. -1 if failure
1592 */
1593 static int init_phy(struct net_device *dev)
1594 {
1595 struct ucc_geth_private *priv = netdev_priv(dev);
1596 struct phy_device *phydev;
1597 char phy_id[BUS_ID_SIZE];
1598
1599 priv->oldlink = 0;
1600 priv->oldspeed = 0;
1601 priv->oldduplex = -1;
1602
1603 snprintf(phy_id, BUS_ID_SIZE, PHY_ID_FMT, priv->ug_info->mdio_bus,
1604 priv->ug_info->phy_address);
1605
1606 phydev = phy_connect(dev, phy_id, &adjust_link, 0, priv->phy_interface);
1607
1608 if (IS_ERR(phydev)) {
1609 printk("%s: Could not attach to PHY\n", dev->name);
1610 return PTR_ERR(phydev);
1611 }
1612
1613 phydev->supported &= (ADVERTISED_10baseT_Half |
1614 ADVERTISED_10baseT_Full |
1615 ADVERTISED_100baseT_Half |
1616 ADVERTISED_100baseT_Full);
1617
1618 if (priv->max_speed == SPEED_1000)
1619 phydev->supported |= ADVERTISED_1000baseT_Full;
1620
1621 phydev->advertising = phydev->supported;
1622
1623 priv->phydev = phydev;
1624
1625 return 0;
1626 }
1627
1628
1629
1630 static int ugeth_graceful_stop_tx(struct ucc_geth_private *ugeth)
1631 {
1632 struct ucc_fast_private *uccf;
1633 u32 cecr_subblock;
1634 u32 temp;
1635
1636 uccf = ugeth->uccf;
1637
1638 /* Mask GRACEFUL STOP TX interrupt bit and clear it */
1639 temp = in_be32(uccf->p_uccm);
1640 temp &= ~UCCE_GRA;
1641 out_be32(uccf->p_uccm, temp);
1642 out_be32(uccf->p_ucce, UCCE_GRA); /* clear by writing 1 */
1643
1644 /* Issue host command */
1645 cecr_subblock =
1646 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1647 qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
1648 QE_CR_PROTOCOL_ETHERNET, 0);
1649
1650 /* Wait for command to complete */
1651 do {
1652 temp = in_be32(uccf->p_ucce);
1653 } while (!(temp & UCCE_GRA));
1654
1655 uccf->stopped_tx = 1;
1656
1657 return 0;
1658 }
1659
1660 static int ugeth_graceful_stop_rx(struct ucc_geth_private * ugeth)
1661 {
1662 struct ucc_fast_private *uccf;
1663 u32 cecr_subblock;
1664 u8 temp;
1665
1666 uccf = ugeth->uccf;
1667
1668 /* Clear acknowledge bit */
1669 temp = ugeth->p_rx_glbl_pram->rxgstpack;
1670 temp &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
1671 ugeth->p_rx_glbl_pram->rxgstpack = temp;
1672
1673 /* Keep issuing command and checking acknowledge bit until
1674 it is asserted, according to spec */
1675 do {
1676 /* Issue host command */
1677 cecr_subblock =
1678 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.
1679 ucc_num);
1680 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
1681 QE_CR_PROTOCOL_ETHERNET, 0);
1682
1683 temp = ugeth->p_rx_glbl_pram->rxgstpack;
1684 } while (!(temp & GRACEFUL_STOP_ACKNOWLEDGE_RX));
1685
1686 uccf->stopped_rx = 1;
1687
1688 return 0;
1689 }
1690
1691 static int ugeth_restart_tx(struct ucc_geth_private *ugeth)
1692 {
1693 struct ucc_fast_private *uccf;
1694 u32 cecr_subblock;
1695
1696 uccf = ugeth->uccf;
1697
1698 cecr_subblock =
1699 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1700 qe_issue_cmd(QE_RESTART_TX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET, 0);
1701 uccf->stopped_tx = 0;
1702
1703 return 0;
1704 }
1705
1706 static int ugeth_restart_rx(struct ucc_geth_private *ugeth)
1707 {
1708 struct ucc_fast_private *uccf;
1709 u32 cecr_subblock;
1710
1711 uccf = ugeth->uccf;
1712
1713 cecr_subblock =
1714 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1715 qe_issue_cmd(QE_RESTART_RX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
1716 0);
1717 uccf->stopped_rx = 0;
1718
1719 return 0;
1720 }
1721
1722 static int ugeth_enable(struct ucc_geth_private *ugeth, enum comm_dir mode)
1723 {
1724 struct ucc_fast_private *uccf;
1725 int enabled_tx, enabled_rx;
1726
1727 uccf = ugeth->uccf;
1728
1729 /* check if the UCC number is in range. */
1730 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
1731 ugeth_err("%s: ucc_num out of range.", __FUNCTION__);
1732 return -EINVAL;
1733 }
1734
1735 enabled_tx = uccf->enabled_tx;
1736 enabled_rx = uccf->enabled_rx;
1737
1738 /* Get Tx and Rx going again, in case this channel was actively
1739 disabled. */
1740 if ((mode & COMM_DIR_TX) && (!enabled_tx) && uccf->stopped_tx)
1741 ugeth_restart_tx(ugeth);
1742 if ((mode & COMM_DIR_RX) && (!enabled_rx) && uccf->stopped_rx)
1743 ugeth_restart_rx(ugeth);
1744
1745 ucc_fast_enable(uccf, mode); /* OK to do even if not disabled */
1746
1747 return 0;
1748
1749 }
1750
1751 static int ugeth_disable(struct ucc_geth_private * ugeth, enum comm_dir mode)
1752 {
1753 struct ucc_fast_private *uccf;
1754
1755 uccf = ugeth->uccf;
1756
1757 /* check if the UCC number is in range. */
1758 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
1759 ugeth_err("%s: ucc_num out of range.", __FUNCTION__);
1760 return -EINVAL;
1761 }
1762
1763 /* Stop any transmissions */
1764 if ((mode & COMM_DIR_TX) && uccf->enabled_tx && !uccf->stopped_tx)
1765 ugeth_graceful_stop_tx(ugeth);
1766
1767 /* Stop any receptions */
1768 if ((mode & COMM_DIR_RX) && uccf->enabled_rx && !uccf->stopped_rx)
1769 ugeth_graceful_stop_rx(ugeth);
1770
1771 ucc_fast_disable(ugeth->uccf, mode); /* OK to do even if not enabled */
1772
1773 return 0;
1774 }
1775
1776 static void ugeth_dump_regs(struct ucc_geth_private *ugeth)
1777 {
1778 #ifdef DEBUG
1779 ucc_fast_dump_regs(ugeth->uccf);
1780 dump_regs(ugeth);
1781 dump_bds(ugeth);
1782 #endif
1783 }
1784
1785 #ifdef CONFIG_UGETH_FILTERING
1786 static int ugeth_ext_filtering_serialize_tad(struct ucc_geth_tad_params *
1787 p_UccGethTadParams,
1788 struct qe_fltr_tad *qe_fltr_tad)
1789 {
1790 u16 temp;
1791
1792 /* Zero serialized TAD */
1793 memset(qe_fltr_tad, 0, QE_FLTR_TAD_SIZE);
1794
1795 qe_fltr_tad->serialized[0] |= UCC_GETH_TAD_V; /* Must have this */
1796 if (p_UccGethTadParams->rx_non_dynamic_extended_features_mode ||
1797 (p_UccGethTadParams->vtag_op != UCC_GETH_VLAN_OPERATION_TAGGED_NOP)
1798 || (p_UccGethTadParams->vnontag_op !=
1799 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP)
1800 )
1801 qe_fltr_tad->serialized[0] |= UCC_GETH_TAD_EF;
1802 if (p_UccGethTadParams->reject_frame)
1803 qe_fltr_tad->serialized[0] |= UCC_GETH_TAD_REJ;
1804 temp =
1805 (u16) (((u16) p_UccGethTadParams->
1806 vtag_op) << UCC_GETH_TAD_VTAG_OP_SHIFT);
1807 qe_fltr_tad->serialized[0] |= (u8) (temp >> 8); /* upper bits */
1808
1809 qe_fltr_tad->serialized[1] |= (u8) (temp & 0x00ff); /* lower bits */
1810 if (p_UccGethTadParams->vnontag_op ==
1811 UCC_GETH_VLAN_OPERATION_NON_TAGGED_Q_TAG_INSERT)
1812 qe_fltr_tad->serialized[1] |= UCC_GETH_TAD_V_NON_VTAG_OP;
1813 qe_fltr_tad->serialized[1] |=
1814 p_UccGethTadParams->rqos << UCC_GETH_TAD_RQOS_SHIFT;
1815
1816 qe_fltr_tad->serialized[2] |=
1817 p_UccGethTadParams->vpri << UCC_GETH_TAD_V_PRIORITY_SHIFT;
1818 /* upper bits */
1819 qe_fltr_tad->serialized[2] |= (u8) (p_UccGethTadParams->vid >> 8);
1820 /* lower bits */
1821 qe_fltr_tad->serialized[3] |= (u8) (p_UccGethTadParams->vid & 0x00ff);
1822
1823 return 0;
1824 }
1825
1826 static struct enet_addr_container_t
1827 *ugeth_82xx_filtering_get_match_addr_in_hash(struct ucc_geth_private *ugeth,
1828 struct enet_addr *p_enet_addr)
1829 {
1830 struct enet_addr_container *enet_addr_cont;
1831 struct list_head *p_lh;
1832 u16 i, num;
1833 int32_t j;
1834 u8 *p_counter;
1835
1836 if ((*p_enet_addr)[0] & ENET_GROUP_ADDR) {
1837 p_lh = &ugeth->group_hash_q;
1838 p_counter = &(ugeth->numGroupAddrInHash);
1839 } else {
1840 p_lh = &ugeth->ind_hash_q;
1841 p_counter = &(ugeth->numIndAddrInHash);
1842 }
1843
1844 if (!p_lh)
1845 return NULL;
1846
1847 num = *p_counter;
1848
1849 for (i = 0; i < num; i++) {
1850 enet_addr_cont =
1851 (struct enet_addr_container *)
1852 ENET_ADDR_CONT_ENTRY(dequeue(p_lh));
1853 for (j = ENET_NUM_OCTETS_PER_ADDRESS - 1; j >= 0; j--) {
1854 if ((*p_enet_addr)[j] != (enet_addr_cont->address)[j])
1855 break;
1856 if (j == 0)
1857 return enet_addr_cont; /* Found */
1858 }
1859 enqueue(p_lh, &enet_addr_cont->node); /* Put it back */
1860 }
1861 return NULL;
1862 }
1863
1864 static int ugeth_82xx_filtering_add_addr_in_hash(struct ucc_geth_private *ugeth,
1865 struct enet_addr *p_enet_addr)
1866 {
1867 enum ucc_geth_enet_address_recognition_location location;
1868 struct enet_addr_container *enet_addr_cont;
1869 struct list_head *p_lh;
1870 u8 i;
1871 u32 limit;
1872 u8 *p_counter;
1873
1874 if ((*p_enet_addr)[0] & ENET_GROUP_ADDR) {
1875 p_lh = &ugeth->group_hash_q;
1876 limit = ugeth->ug_info->maxGroupAddrInHash;
1877 location =
1878 UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_GROUP_HASH;
1879 p_counter = &(ugeth->numGroupAddrInHash);
1880 } else {
1881 p_lh = &ugeth->ind_hash_q;
1882 limit = ugeth->ug_info->maxIndAddrInHash;
1883 location =
1884 UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_INDIVIDUAL_HASH;
1885 p_counter = &(ugeth->numIndAddrInHash);
1886 }
1887
1888 if ((enet_addr_cont =
1889 ugeth_82xx_filtering_get_match_addr_in_hash(ugeth, p_enet_addr))) {
1890 list_add(p_lh, &enet_addr_cont->node); /* Put it back */
1891 return 0;
1892 }
1893 if ((!p_lh) || (!(*p_counter < limit)))
1894 return -EBUSY;
1895 if (!(enet_addr_cont = get_enet_addr_container()))
1896 return -ENOMEM;
1897 for (i = 0; i < ENET_NUM_OCTETS_PER_ADDRESS; i++)
1898 (enet_addr_cont->address)[i] = (*p_enet_addr)[i];
1899 enet_addr_cont->location = location;
1900 enqueue(p_lh, &enet_addr_cont->node); /* Put it back */
1901 ++(*p_counter);
1902
1903 hw_add_addr_in_hash(ugeth, enet_addr_cont->address);
1904 return 0;
1905 }
1906
1907 static int ugeth_82xx_filtering_clear_addr_in_hash(struct ucc_geth_private *ugeth,
1908 struct enet_addr *p_enet_addr)
1909 {
1910 struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
1911 struct enet_addr_container *enet_addr_cont;
1912 struct ucc_fast_private *uccf;
1913 enum comm_dir comm_dir;
1914 u16 i, num;
1915 struct list_head *p_lh;
1916 u32 *addr_h, *addr_l;
1917 u8 *p_counter;
1918
1919 uccf = ugeth->uccf;
1920
1921 p_82xx_addr_filt =
1922 (struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram->
1923 addressfiltering;
1924
1925 if (!
1926 (enet_addr_cont =
1927 ugeth_82xx_filtering_get_match_addr_in_hash(ugeth, p_enet_addr)))
1928 return -ENOENT;
1929
1930 /* It's been found and removed from the CQ. */
1931 /* Now destroy its container */
1932 put_enet_addr_container(enet_addr_cont);
1933
1934 if ((*p_enet_addr)[0] & ENET_GROUP_ADDR) {
1935 addr_h = &(p_82xx_addr_filt->gaddr_h);
1936 addr_l = &(p_82xx_addr_filt->gaddr_l);
1937 p_lh = &ugeth->group_hash_q;
1938 p_counter = &(ugeth->numGroupAddrInHash);
1939 } else {
1940 addr_h = &(p_82xx_addr_filt->iaddr_h);
1941 addr_l = &(p_82xx_addr_filt->iaddr_l);
1942 p_lh = &ugeth->ind_hash_q;
1943 p_counter = &(ugeth->numIndAddrInHash);
1944 }
1945
1946 comm_dir = 0;
1947 if (uccf->enabled_tx)
1948 comm_dir |= COMM_DIR_TX;
1949 if (uccf->enabled_rx)
1950 comm_dir |= COMM_DIR_RX;
1951 if (comm_dir)
1952 ugeth_disable(ugeth, comm_dir);
1953
1954 /* Clear the hash table. */
1955 out_be32(addr_h, 0x00000000);
1956 out_be32(addr_l, 0x00000000);
1957
1958 /* Add all remaining CQ elements back into hash */
1959 num = --(*p_counter);
1960 for (i = 0; i < num; i++) {
1961 enet_addr_cont =
1962 (struct enet_addr_container *)
1963 ENET_ADDR_CONT_ENTRY(dequeue(p_lh));
1964 hw_add_addr_in_hash(ugeth, enet_addr_cont->address);
1965 enqueue(p_lh, &enet_addr_cont->node); /* Put it back */
1966 }
1967
1968 if (comm_dir)
1969 ugeth_enable(ugeth, comm_dir);
1970
1971 return 0;
1972 }
1973 #endif /* CONFIG_UGETH_FILTERING */
1974
1975 static int ugeth_82xx_filtering_clear_all_addr_in_hash(struct ucc_geth_private *
1976 ugeth,
1977 enum enet_addr_type
1978 enet_addr_type)
1979 {
1980 struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
1981 struct ucc_fast_private *uccf;
1982 enum comm_dir comm_dir;
1983 struct list_head *p_lh;
1984 u16 i, num;
1985 u32 *addr_h, *addr_l;
1986 u8 *p_counter;
1987
1988 uccf = ugeth->uccf;
1989
1990 p_82xx_addr_filt =
1991 (struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram->
1992 addressfiltering;
1993
1994 if (enet_addr_type == ENET_ADDR_TYPE_GROUP) {
1995 addr_h = &(p_82xx_addr_filt->gaddr_h);
1996 addr_l = &(p_82xx_addr_filt->gaddr_l);
1997 p_lh = &ugeth->group_hash_q;
1998 p_counter = &(ugeth->numGroupAddrInHash);
1999 } else if (enet_addr_type == ENET_ADDR_TYPE_INDIVIDUAL) {
2000 addr_h = &(p_82xx_addr_filt->iaddr_h);
2001 addr_l = &(p_82xx_addr_filt->iaddr_l);
2002 p_lh = &ugeth->ind_hash_q;
2003 p_counter = &(ugeth->numIndAddrInHash);
2004 } else
2005 return -EINVAL;
2006
2007 comm_dir = 0;
2008 if (uccf->enabled_tx)
2009 comm_dir |= COMM_DIR_TX;
2010 if (uccf->enabled_rx)
2011 comm_dir |= COMM_DIR_RX;
2012 if (comm_dir)
2013 ugeth_disable(ugeth, comm_dir);
2014
2015 /* Clear the hash table. */
2016 out_be32(addr_h, 0x00000000);
2017 out_be32(addr_l, 0x00000000);
2018
2019 if (!p_lh)
2020 return 0;
2021
2022 num = *p_counter;
2023
2024 /* Delete all remaining CQ elements */
2025 for (i = 0; i < num; i++)
2026 put_enet_addr_container(ENET_ADDR_CONT_ENTRY(dequeue(p_lh)));
2027
2028 *p_counter = 0;
2029
2030 if (comm_dir)
2031 ugeth_enable(ugeth, comm_dir);
2032
2033 return 0;
2034 }
2035
2036 #ifdef CONFIG_UGETH_FILTERING
2037 static int ugeth_82xx_filtering_add_addr_in_paddr(struct ucc_geth_private *ugeth,
2038 struct enet_addr *p_enet_addr,
2039 u8 paddr_num)
2040 {
2041 int i;
2042
2043 if ((*p_enet_addr)[0] & ENET_GROUP_ADDR)
2044 ugeth_warn
2045 ("%s: multicast address added to paddr will have no "
2046 "effect - is this what you wanted?",
2047 __FUNCTION__);
2048
2049 ugeth->indAddrRegUsed[paddr_num] = 1; /* mark this paddr as used */
2050 /* store address in our database */
2051 for (i = 0; i < ENET_NUM_OCTETS_PER_ADDRESS; i++)
2052 ugeth->paddr[paddr_num][i] = (*p_enet_addr)[i];
2053 /* put in hardware */
2054 return hw_add_addr_in_paddr(ugeth, p_enet_addr, paddr_num);
2055 }
2056 #endif /* CONFIG_UGETH_FILTERING */
2057
2058 static int ugeth_82xx_filtering_clear_addr_in_paddr(struct ucc_geth_private *ugeth,
2059 u8 paddr_num)
2060 {
2061 ugeth->indAddrRegUsed[paddr_num] = 0; /* mark this paddr as not used */
2062 return hw_clear_addr_in_paddr(ugeth, paddr_num);/* clear in hardware */
2063 }
2064
2065 static void ucc_geth_memclean(struct ucc_geth_private *ugeth)
2066 {
2067 u16 i, j;
2068 u8 *bd;
2069
2070 if (!ugeth)
2071 return;
2072
2073 if (ugeth->uccf)
2074 ucc_fast_free(ugeth->uccf);
2075
2076 if (ugeth->p_thread_data_tx) {
2077 qe_muram_free(ugeth->thread_dat_tx_offset);
2078 ugeth->p_thread_data_tx = NULL;
2079 }
2080 if (ugeth->p_thread_data_rx) {
2081 qe_muram_free(ugeth->thread_dat_rx_offset);
2082 ugeth->p_thread_data_rx = NULL;
2083 }
2084 if (ugeth->p_exf_glbl_param) {
2085 qe_muram_free(ugeth->exf_glbl_param_offset);
2086 ugeth->p_exf_glbl_param = NULL;
2087 }
2088 if (ugeth->p_rx_glbl_pram) {
2089 qe_muram_free(ugeth->rx_glbl_pram_offset);
2090 ugeth->p_rx_glbl_pram = NULL;
2091 }
2092 if (ugeth->p_tx_glbl_pram) {
2093 qe_muram_free(ugeth->tx_glbl_pram_offset);
2094 ugeth->p_tx_glbl_pram = NULL;
2095 }
2096 if (ugeth->p_send_q_mem_reg) {
2097 qe_muram_free(ugeth->send_q_mem_reg_offset);
2098 ugeth->p_send_q_mem_reg = NULL;
2099 }
2100 if (ugeth->p_scheduler) {
2101 qe_muram_free(ugeth->scheduler_offset);
2102 ugeth->p_scheduler = NULL;
2103 }
2104 if (ugeth->p_tx_fw_statistics_pram) {
2105 qe_muram_free(ugeth->tx_fw_statistics_pram_offset);
2106 ugeth->p_tx_fw_statistics_pram = NULL;
2107 }
2108 if (ugeth->p_rx_fw_statistics_pram) {
2109 qe_muram_free(ugeth->rx_fw_statistics_pram_offset);
2110 ugeth->p_rx_fw_statistics_pram = NULL;
2111 }
2112 if (ugeth->p_rx_irq_coalescing_tbl) {
2113 qe_muram_free(ugeth->rx_irq_coalescing_tbl_offset);
2114 ugeth->p_rx_irq_coalescing_tbl = NULL;
2115 }
2116 if (ugeth->p_rx_bd_qs_tbl) {
2117 qe_muram_free(ugeth->rx_bd_qs_tbl_offset);
2118 ugeth->p_rx_bd_qs_tbl = NULL;
2119 }
2120 if (ugeth->p_init_enet_param_shadow) {
2121 return_init_enet_entries(ugeth,
2122 &(ugeth->p_init_enet_param_shadow->
2123 rxthread[0]),
2124 ENET_INIT_PARAM_MAX_ENTRIES_RX,
2125 ugeth->ug_info->riscRx, 1);
2126 return_init_enet_entries(ugeth,
2127 &(ugeth->p_init_enet_param_shadow->
2128 txthread[0]),
2129 ENET_INIT_PARAM_MAX_ENTRIES_TX,
2130 ugeth->ug_info->riscTx, 0);
2131 kfree(ugeth->p_init_enet_param_shadow);
2132 ugeth->p_init_enet_param_shadow = NULL;
2133 }
2134 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
2135 bd = ugeth->p_tx_bd_ring[i];
2136 for (j = 0; j < ugeth->ug_info->bdRingLenTx[i]; j++) {
2137 if (ugeth->tx_skbuff[i][j]) {
2138 dma_unmap_single(NULL,
2139 ((qe_bd_t *)bd)->buf,
2140 (in_be32((u32 *)bd) &
2141 BD_LENGTH_MASK),
2142 DMA_TO_DEVICE);
2143 dev_kfree_skb_any(ugeth->tx_skbuff[i][j]);
2144 ugeth->tx_skbuff[i][j] = NULL;
2145 }
2146 }
2147
2148 kfree(ugeth->tx_skbuff[i]);
2149
2150 if (ugeth->p_tx_bd_ring[i]) {
2151 if (ugeth->ug_info->uf_info.bd_mem_part ==
2152 MEM_PART_SYSTEM)
2153 kfree((void *)ugeth->tx_bd_ring_offset[i]);
2154 else if (ugeth->ug_info->uf_info.bd_mem_part ==
2155 MEM_PART_MURAM)
2156 qe_muram_free(ugeth->tx_bd_ring_offset[i]);
2157 ugeth->p_tx_bd_ring[i] = NULL;
2158 }
2159 }
2160 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
2161 if (ugeth->p_rx_bd_ring[i]) {
2162 /* Return existing data buffers in ring */
2163 bd = ugeth->p_rx_bd_ring[i];
2164 for (j = 0; j < ugeth->ug_info->bdRingLenRx[i]; j++) {
2165 if (ugeth->rx_skbuff[i][j]) {
2166 dma_unmap_single(NULL,
2167 ((struct qe_bd *)bd)->buf,
2168 ugeth->ug_info->
2169 uf_info.max_rx_buf_length +
2170 UCC_GETH_RX_DATA_BUF_ALIGNMENT,
2171 DMA_FROM_DEVICE);
2172 dev_kfree_skb_any(
2173 ugeth->rx_skbuff[i][j]);
2174 ugeth->rx_skbuff[i][j] = NULL;
2175 }
2176 bd += sizeof(struct qe_bd);
2177 }
2178
2179 kfree(ugeth->rx_skbuff[i]);
2180
2181 if (ugeth->ug_info->uf_info.bd_mem_part ==
2182 MEM_PART_SYSTEM)
2183 kfree((void *)ugeth->rx_bd_ring_offset[i]);
2184 else if (ugeth->ug_info->uf_info.bd_mem_part ==
2185 MEM_PART_MURAM)
2186 qe_muram_free(ugeth->rx_bd_ring_offset[i]);
2187 ugeth->p_rx_bd_ring[i] = NULL;
2188 }
2189 }
2190 while (!list_empty(&ugeth->group_hash_q))
2191 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
2192 (dequeue(&ugeth->group_hash_q)));
2193 while (!list_empty(&ugeth->ind_hash_q))
2194 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
2195 (dequeue(&ugeth->ind_hash_q)));
2196
2197 }
2198
2199 static void ucc_geth_set_multi(struct net_device *dev)
2200 {
2201 struct ucc_geth_private *ugeth;
2202 struct dev_mc_list *dmi;
2203 struct ucc_fast *uf_regs;
2204 struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
2205 u8 tempaddr[6];
2206 u8 *mcptr, *tdptr;
2207 int i, j;
2208
2209 ugeth = netdev_priv(dev);
2210
2211 uf_regs = ugeth->uccf->uf_regs;
2212
2213 if (dev->flags & IFF_PROMISC) {
2214
2215 uf_regs->upsmr |= UPSMR_PRO;
2216
2217 } else {
2218
2219 uf_regs->upsmr &= ~UPSMR_PRO;
2220
2221 p_82xx_addr_filt =
2222 (struct ucc_geth_82xx_address_filtering_pram *) ugeth->
2223 p_rx_glbl_pram->addressfiltering;
2224
2225 if (dev->flags & IFF_ALLMULTI) {
2226 /* Catch all multicast addresses, so set the
2227 * filter to all 1's.
2228 */
2229 out_be32(&p_82xx_addr_filt->gaddr_h, 0xffffffff);
2230 out_be32(&p_82xx_addr_filt->gaddr_l, 0xffffffff);
2231 } else {
2232 /* Clear filter and add the addresses in the list.
2233 */
2234 out_be32(&p_82xx_addr_filt->gaddr_h, 0x0);
2235 out_be32(&p_82xx_addr_filt->gaddr_l, 0x0);
2236
2237 dmi = dev->mc_list;
2238
2239 for (i = 0; i < dev->mc_count; i++, dmi = dmi->next) {
2240
2241 /* Only support group multicast for now.
2242 */
2243 if (!(dmi->dmi_addr[0] & 1))
2244 continue;
2245
2246 /* The address in dmi_addr is LSB first,
2247 * and taddr is MSB first. We have to
2248 * copy bytes MSB first from dmi_addr.
2249 */
2250 mcptr = (u8 *) dmi->dmi_addr + 5;
2251 tdptr = (u8 *) tempaddr;
2252 for (j = 0; j < 6; j++)
2253 *tdptr++ = *mcptr--;
2254
2255 /* Ask CPM to run CRC and set bit in
2256 * filter mask.
2257 */
2258 hw_add_addr_in_hash(ugeth, tempaddr);
2259 }
2260 }
2261 }
2262 }
2263
2264 static void ucc_geth_stop(struct ucc_geth_private *ugeth)
2265 {
2266 struct ucc_geth *ug_regs = ugeth->ug_regs;
2267 struct phy_device *phydev = ugeth->phydev;
2268 u32 tempval;
2269
2270 ugeth_vdbg("%s: IN", __FUNCTION__);
2271
2272 /* Disable the controller */
2273 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
2274
2275 /* Tell the kernel the link is down */
2276 phy_stop(phydev);
2277
2278 /* Mask all interrupts */
2279 out_be32(ugeth->uccf->p_ucce, 0x00000000);
2280
2281 /* Clear all interrupts */
2282 out_be32(ugeth->uccf->p_ucce, 0xffffffff);
2283
2284 /* Disable Rx and Tx */
2285 tempval = in_be32(&ug_regs->maccfg1);
2286 tempval &= ~(MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
2287 out_be32(&ug_regs->maccfg1, tempval);
2288
2289 free_irq(ugeth->ug_info->uf_info.irq, ugeth->dev);
2290
2291 ucc_geth_memclean(ugeth);
2292 }
2293
2294 static int ucc_struct_init(struct ucc_geth_private *ugeth)
2295 {
2296 struct ucc_geth_info *ug_info;
2297 struct ucc_fast_info *uf_info;
2298 int i;
2299
2300 ug_info = ugeth->ug_info;
2301 uf_info = &ug_info->uf_info;
2302
2303 if (!((uf_info->bd_mem_part == MEM_PART_SYSTEM) ||
2304 (uf_info->bd_mem_part == MEM_PART_MURAM))) {
2305 ugeth_err("%s: Bad memory partition value.", __FUNCTION__);
2306 return -EINVAL;
2307 }
2308
2309 /* Rx BD lengths */
2310 for (i = 0; i < ug_info->numQueuesRx; i++) {
2311 if ((ug_info->bdRingLenRx[i] < UCC_GETH_RX_BD_RING_SIZE_MIN) ||
2312 (ug_info->bdRingLenRx[i] %
2313 UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT)) {
2314 ugeth_err
2315 ("%s: Rx BD ring length must be multiple of 4,"
2316 " no smaller than 8.", __FUNCTION__);
2317 return -EINVAL;
2318 }
2319 }
2320
2321 /* Tx BD lengths */
2322 for (i = 0; i < ug_info->numQueuesTx; i++) {
2323 if (ug_info->bdRingLenTx[i] < UCC_GETH_TX_BD_RING_SIZE_MIN) {
2324 ugeth_err
2325 ("%s: Tx BD ring length must be no smaller than 2.",
2326 __FUNCTION__);
2327 return -EINVAL;
2328 }
2329 }
2330
2331 /* mrblr */
2332 if ((uf_info->max_rx_buf_length == 0) ||
2333 (uf_info->max_rx_buf_length % UCC_GETH_MRBLR_ALIGNMENT)) {
2334 ugeth_err
2335 ("%s: max_rx_buf_length must be non-zero multiple of 128.",
2336 __FUNCTION__);
2337 return -EINVAL;
2338 }
2339
2340 /* num Tx queues */
2341 if (ug_info->numQueuesTx > NUM_TX_QUEUES) {
2342 ugeth_err("%s: number of tx queues too large.", __FUNCTION__);
2343 return -EINVAL;
2344 }
2345
2346 /* num Rx queues */
2347 if (ug_info->numQueuesRx > NUM_RX_QUEUES) {
2348 ugeth_err("%s: number of rx queues too large.", __FUNCTION__);
2349 return -EINVAL;
2350 }
2351
2352 /* l2qt */
2353 for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++) {
2354 if (ug_info->l2qt[i] >= ug_info->numQueuesRx) {
2355 ugeth_err
2356 ("%s: VLAN priority table entry must not be"
2357 " larger than number of Rx queues.",
2358 __FUNCTION__);
2359 return -EINVAL;
2360 }
2361 }
2362
2363 /* l3qt */
2364 for (i = 0; i < UCC_GETH_IP_PRIORITY_MAX; i++) {
2365 if (ug_info->l3qt[i] >= ug_info->numQueuesRx) {
2366 ugeth_err
2367 ("%s: IP priority table entry must not be"
2368 " larger than number of Rx queues.",
2369 __FUNCTION__);
2370 return -EINVAL;
2371 }
2372 }
2373
2374 if (ug_info->cam && !ug_info->ecamptr) {
2375 ugeth_err("%s: If cam mode is chosen, must supply cam ptr.",
2376 __FUNCTION__);
2377 return -EINVAL;
2378 }
2379
2380 if ((ug_info->numStationAddresses !=
2381 UCC_GETH_NUM_OF_STATION_ADDRESSES_1)
2382 && ug_info->rxExtendedFiltering) {
2383 ugeth_err("%s: Number of station addresses greater than 1 "
2384 "not allowed in extended parsing mode.",
2385 __FUNCTION__);
2386 return -EINVAL;
2387 }
2388
2389 /* Generate uccm_mask for receive */
2390 uf_info->uccm_mask = ug_info->eventRegMask & UCCE_OTHER;/* Errors */
2391 for (i = 0; i < ug_info->numQueuesRx; i++)
2392 uf_info->uccm_mask |= (UCCE_RXBF_SINGLE_MASK << i);
2393
2394 for (i = 0; i < ug_info->numQueuesTx; i++)
2395 uf_info->uccm_mask |= (UCCE_TXBF_SINGLE_MASK << i);
2396 /* Initialize the general fast UCC block. */
2397 if (ucc_fast_init(uf_info, &ugeth->uccf)) {
2398 ugeth_err("%s: Failed to init uccf.", __FUNCTION__);
2399 ucc_geth_memclean(ugeth);
2400 return -ENOMEM;
2401 }
2402
2403 ugeth->ug_regs = (struct ucc_geth *) ioremap(uf_info->regs, sizeof(struct ucc_geth));
2404
2405 return 0;
2406 }
2407
2408 static int ucc_geth_startup(struct ucc_geth_private *ugeth)
2409 {
2410 struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
2411 struct ucc_geth_init_pram *p_init_enet_pram;
2412 struct ucc_fast_private *uccf;
2413 struct ucc_geth_info *ug_info;
2414 struct ucc_fast_info *uf_info;
2415 struct ucc_fast *uf_regs;
2416 struct ucc_geth *ug_regs;
2417 int ret_val = -EINVAL;
2418 u32 remoder = UCC_GETH_REMODER_INIT;
2419 u32 init_enet_pram_offset, cecr_subblock, command, maccfg1;
2420 u32 ifstat, i, j, size, l2qt, l3qt, length;
2421 u16 temoder = UCC_GETH_TEMODER_INIT;
2422 u16 test;
2423 u8 function_code = 0;
2424 u8 *bd, *endOfRing;
2425 u8 numThreadsRxNumerical, numThreadsTxNumerical;
2426
2427 ugeth_vdbg("%s: IN", __FUNCTION__);
2428 uccf = ugeth->uccf;
2429 ug_info = ugeth->ug_info;
2430 uf_info = &ug_info->uf_info;
2431 uf_regs = uccf->uf_regs;
2432 ug_regs = ugeth->ug_regs;
2433
2434 switch (ug_info->numThreadsRx) {
2435 case UCC_GETH_NUM_OF_THREADS_1:
2436 numThreadsRxNumerical = 1;
2437 break;
2438 case UCC_GETH_NUM_OF_THREADS_2:
2439 numThreadsRxNumerical = 2;
2440 break;
2441 case UCC_GETH_NUM_OF_THREADS_4:
2442 numThreadsRxNumerical = 4;
2443 break;
2444 case UCC_GETH_NUM_OF_THREADS_6:
2445 numThreadsRxNumerical = 6;
2446 break;
2447 case UCC_GETH_NUM_OF_THREADS_8:
2448 numThreadsRxNumerical = 8;
2449 break;
2450 default:
2451 ugeth_err("%s: Bad number of Rx threads value.", __FUNCTION__);
2452 ucc_geth_memclean(ugeth);
2453 return -EINVAL;
2454 break;
2455 }
2456
2457 switch (ug_info->numThreadsTx) {
2458 case UCC_GETH_NUM_OF_THREADS_1:
2459 numThreadsTxNumerical = 1;
2460 break;
2461 case UCC_GETH_NUM_OF_THREADS_2:
2462 numThreadsTxNumerical = 2;
2463 break;
2464 case UCC_GETH_NUM_OF_THREADS_4:
2465 numThreadsTxNumerical = 4;
2466 break;
2467 case UCC_GETH_NUM_OF_THREADS_6:
2468 numThreadsTxNumerical = 6;
2469 break;
2470 case UCC_GETH_NUM_OF_THREADS_8:
2471 numThreadsTxNumerical = 8;
2472 break;
2473 default:
2474 ugeth_err("%s: Bad number of Tx threads value.", __FUNCTION__);
2475 ucc_geth_memclean(ugeth);
2476 return -EINVAL;
2477 break;
2478 }
2479
2480 /* Calculate rx_extended_features */
2481 ugeth->rx_non_dynamic_extended_features = ug_info->ipCheckSumCheck ||
2482 ug_info->ipAddressAlignment ||
2483 (ug_info->numStationAddresses !=
2484 UCC_GETH_NUM_OF_STATION_ADDRESSES_1);
2485
2486 ugeth->rx_extended_features = ugeth->rx_non_dynamic_extended_features ||
2487 (ug_info->vlanOperationTagged != UCC_GETH_VLAN_OPERATION_TAGGED_NOP)
2488 || (ug_info->vlanOperationNonTagged !=
2489 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP);
2490
2491 init_default_reg_vals(&uf_regs->upsmr,
2492 &ug_regs->maccfg1, &ug_regs->maccfg2);
2493
2494 /* Set UPSMR */
2495 /* For more details see the hardware spec. */
2496 init_rx_parameters(ug_info->bro,
2497 ug_info->rsh, ug_info->pro, &uf_regs->upsmr);
2498
2499 /* We're going to ignore other registers for now, */
2500 /* except as needed to get up and running */
2501
2502 /* Set MACCFG1 */
2503 /* For more details see the hardware spec. */
2504 init_flow_control_params(ug_info->aufc,
2505 ug_info->receiveFlowControl,
2506 1,
2507 ug_info->pausePeriod,
2508 ug_info->extensionField,
2509 &uf_regs->upsmr,
2510 &ug_regs->uempr, &ug_regs->maccfg1);
2511
2512 maccfg1 = in_be32(&ug_regs->maccfg1);
2513 maccfg1 |= MACCFG1_ENABLE_RX;
2514 maccfg1 |= MACCFG1_ENABLE_TX;
2515 out_be32(&ug_regs->maccfg1, maccfg1);
2516
2517 /* Set IPGIFG */
2518 /* For more details see the hardware spec. */
2519 ret_val = init_inter_frame_gap_params(ug_info->nonBackToBackIfgPart1,
2520 ug_info->nonBackToBackIfgPart2,
2521 ug_info->
2522 miminumInterFrameGapEnforcement,
2523 ug_info->backToBackInterFrameGap,
2524 &ug_regs->ipgifg);
2525 if (ret_val != 0) {
2526 ugeth_err("%s: IPGIFG initialization parameter too large.",
2527 __FUNCTION__);
2528 ucc_geth_memclean(ugeth);
2529 return ret_val;
2530 }
2531
2532 /* Set HAFDUP */
2533 /* For more details see the hardware spec. */
2534 ret_val = init_half_duplex_params(ug_info->altBeb,
2535 ug_info->backPressureNoBackoff,
2536 ug_info->noBackoff,
2537 ug_info->excessDefer,
2538 ug_info->altBebTruncation,
2539 ug_info->maxRetransmission,
2540 ug_info->collisionWindow,
2541 &ug_regs->hafdup);
2542 if (ret_val != 0) {
2543 ugeth_err("%s: Half Duplex initialization parameter too large.",
2544 __FUNCTION__);
2545 ucc_geth_memclean(ugeth);
2546 return ret_val;
2547 }
2548
2549 /* Set IFSTAT */
2550 /* For more details see the hardware spec. */
2551 /* Read only - resets upon read */
2552 ifstat = in_be32(&ug_regs->ifstat);
2553
2554 /* Clear UEMPR */
2555 /* For more details see the hardware spec. */
2556 out_be32(&ug_regs->uempr, 0);
2557
2558 /* Set UESCR */
2559 /* For more details see the hardware spec. */
2560 init_hw_statistics_gathering_mode((ug_info->statisticsMode &
2561 UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE),
2562 0, &uf_regs->upsmr, &ug_regs->uescr);
2563
2564 /* Allocate Tx bds */
2565 for (j = 0; j < ug_info->numQueuesTx; j++) {
2566 /* Allocate in multiple of
2567 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT,
2568 according to spec */
2569 length = ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd))
2570 / UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2571 * UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
2572 if ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)) %
2573 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2574 length += UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
2575 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2576 u32 align = 4;
2577 if (UCC_GETH_TX_BD_RING_ALIGNMENT > 4)
2578 align = UCC_GETH_TX_BD_RING_ALIGNMENT;
2579 ugeth->tx_bd_ring_offset[j] =
2580 kmalloc((u32) (length + align), GFP_KERNEL);
2581
2582 if (ugeth->tx_bd_ring_offset[j] != 0)
2583 ugeth->p_tx_bd_ring[j] =
2584 (void*)((ugeth->tx_bd_ring_offset[j] +
2585 align) & ~(align - 1));
2586 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2587 ugeth->tx_bd_ring_offset[j] =
2588 qe_muram_alloc(length,
2589 UCC_GETH_TX_BD_RING_ALIGNMENT);
2590 if (!IS_MURAM_ERR(ugeth->tx_bd_ring_offset[j]))
2591 ugeth->p_tx_bd_ring[j] =
2592 (u8 *) qe_muram_addr(ugeth->
2593 tx_bd_ring_offset[j]);
2594 }
2595 if (!ugeth->p_tx_bd_ring[j]) {
2596 ugeth_err
2597 ("%s: Can not allocate memory for Tx bd rings.",
2598 __FUNCTION__);
2599 ucc_geth_memclean(ugeth);
2600 return -ENOMEM;
2601 }
2602 /* Zero unused end of bd ring, according to spec */
2603 memset(ugeth->p_tx_bd_ring[j] +
2604 ug_info->bdRingLenTx[j] * sizeof(struct qe_bd), 0,
2605 length - ug_info->bdRingLenTx[j] * sizeof(struct qe_bd));
2606 }
2607
2608 /* Allocate Rx bds */
2609 for (j = 0; j < ug_info->numQueuesRx; j++) {
2610 length = ug_info->bdRingLenRx[j] * sizeof(struct qe_bd);
2611 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2612 u32 align = 4;
2613 if (UCC_GETH_RX_BD_RING_ALIGNMENT > 4)
2614 align = UCC_GETH_RX_BD_RING_ALIGNMENT;
2615 ugeth->rx_bd_ring_offset[j] =
2616 kmalloc((u32) (length + align), GFP_KERNEL);
2617 if (ugeth->rx_bd_ring_offset[j] != 0)
2618 ugeth->p_rx_bd_ring[j] =
2619 (void*)((ugeth->rx_bd_ring_offset[j] +
2620 align) & ~(align - 1));
2621 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2622 ugeth->rx_bd_ring_offset[j] =
2623 qe_muram_alloc(length,
2624 UCC_GETH_RX_BD_RING_ALIGNMENT);
2625 if (!IS_MURAM_ERR(ugeth->rx_bd_ring_offset[j]))
2626 ugeth->p_rx_bd_ring[j] =
2627 (u8 *) qe_muram_addr(ugeth->
2628 rx_bd_ring_offset[j]);
2629 }
2630 if (!ugeth->p_rx_bd_ring[j]) {
2631 ugeth_err
2632 ("%s: Can not allocate memory for Rx bd rings.",
2633 __FUNCTION__);
2634 ucc_geth_memclean(ugeth);
2635 return -ENOMEM;
2636 }
2637 }
2638
2639 /* Init Tx bds */
2640 for (j = 0; j < ug_info->numQueuesTx; j++) {
2641 /* Setup the skbuff rings */
2642 ugeth->tx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) *
2643 ugeth->ug_info->bdRingLenTx[j],
2644 GFP_KERNEL);
2645
2646 if (ugeth->tx_skbuff[j] == NULL) {
2647 ugeth_err("%s: Could not allocate tx_skbuff",
2648 __FUNCTION__);
2649 ucc_geth_memclean(ugeth);
2650 return -ENOMEM;
2651 }
2652
2653 for (i = 0; i < ugeth->ug_info->bdRingLenTx[j]; i++)
2654 ugeth->tx_skbuff[j][i] = NULL;
2655
2656 ugeth->skb_curtx[j] = ugeth->skb_dirtytx[j] = 0;
2657 bd = ugeth->confBd[j] = ugeth->txBd[j] = ugeth->p_tx_bd_ring[j];
2658 for (i = 0; i < ug_info->bdRingLenTx[j]; i++) {
2659 /* clear bd buffer */
2660 out_be32(&((struct qe_bd *)bd)->buf, 0);
2661 /* set bd status and length */
2662 out_be32((u32 *)bd, 0);
2663 bd += sizeof(struct qe_bd);
2664 }
2665 bd -= sizeof(struct qe_bd);
2666 /* set bd status and length */
2667 out_be32((u32 *)bd, T_W); /* for last BD set Wrap bit */
2668 }
2669
2670 /* Init Rx bds */
2671 for (j = 0; j < ug_info->numQueuesRx; j++) {
2672 /* Setup the skbuff rings */
2673 ugeth->rx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) *
2674 ugeth->ug_info->bdRingLenRx[j],
2675 GFP_KERNEL);
2676
2677 if (ugeth->rx_skbuff[j] == NULL) {
2678 ugeth_err("%s: Could not allocate rx_skbuff",
2679 __FUNCTION__);
2680 ucc_geth_memclean(ugeth);
2681 return -ENOMEM;
2682 }
2683
2684 for (i = 0; i < ugeth->ug_info->bdRingLenRx[j]; i++)
2685 ugeth->rx_skbuff[j][i] = NULL;
2686
2687 ugeth->skb_currx[j] = 0;
2688 bd = ugeth->rxBd[j] = ugeth->p_rx_bd_ring[j];
2689 for (i = 0; i < ug_info->bdRingLenRx[j]; i++) {
2690 /* set bd status and length */
2691 out_be32((u32 *)bd, R_I);
2692 /* clear bd buffer */
2693 out_be32(&((struct qe_bd *)bd)->buf, 0);
2694 bd += sizeof(struct qe_bd);
2695 }
2696 bd -= sizeof(struct qe_bd);
2697 /* set bd status and length */
2698 out_be32((u32 *)bd, R_W); /* for last BD set Wrap bit */
2699 }
2700
2701 /*
2702 * Global PRAM
2703 */
2704 /* Tx global PRAM */
2705 /* Allocate global tx parameter RAM page */
2706 ugeth->tx_glbl_pram_offset =
2707 qe_muram_alloc(sizeof(struct ucc_geth_tx_global_pram),
2708 UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT);
2709 if (IS_MURAM_ERR(ugeth->tx_glbl_pram_offset)) {
2710 ugeth_err
2711 ("%s: Can not allocate DPRAM memory for p_tx_glbl_pram.",
2712 __FUNCTION__);
2713 ucc_geth_memclean(ugeth);
2714 return -ENOMEM;
2715 }
2716 ugeth->p_tx_glbl_pram =
2717 (struct ucc_geth_tx_global_pram *) qe_muram_addr(ugeth->
2718 tx_glbl_pram_offset);
2719 /* Zero out p_tx_glbl_pram */
2720 memset(ugeth->p_tx_glbl_pram, 0, sizeof(struct ucc_geth_tx_global_pram));
2721
2722 /* Fill global PRAM */
2723
2724 /* TQPTR */
2725 /* Size varies with number of Tx threads */
2726 ugeth->thread_dat_tx_offset =
2727 qe_muram_alloc(numThreadsTxNumerical *
2728 sizeof(struct ucc_geth_thread_data_tx) +
2729 32 * (numThreadsTxNumerical == 1),
2730 UCC_GETH_THREAD_DATA_ALIGNMENT);
2731 if (IS_MURAM_ERR(ugeth->thread_dat_tx_offset)) {
2732 ugeth_err
2733 ("%s: Can not allocate DPRAM memory for p_thread_data_tx.",
2734 __FUNCTION__);
2735 ucc_geth_memclean(ugeth);
2736 return -ENOMEM;
2737 }
2738
2739 ugeth->p_thread_data_tx =
2740 (struct ucc_geth_thread_data_tx *) qe_muram_addr(ugeth->
2741 thread_dat_tx_offset);
2742 out_be32(&ugeth->p_tx_glbl_pram->tqptr, ugeth->thread_dat_tx_offset);
2743
2744 /* vtagtable */
2745 for (i = 0; i < UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX; i++)
2746 out_be32(&ugeth->p_tx_glbl_pram->vtagtable[i],
2747 ug_info->vtagtable[i]);
2748
2749 /* iphoffset */
2750 for (i = 0; i < TX_IP_OFFSET_ENTRY_MAX; i++)
2751 ugeth->p_tx_glbl_pram->iphoffset[i] = ug_info->iphoffset[i];
2752
2753 /* SQPTR */
2754 /* Size varies with number of Tx queues */
2755 ugeth->send_q_mem_reg_offset =
2756 qe_muram_alloc(ug_info->numQueuesTx *
2757 sizeof(struct ucc_geth_send_queue_qd),
2758 UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
2759 if (IS_MURAM_ERR(ugeth->send_q_mem_reg_offset)) {
2760 ugeth_err
2761 ("%s: Can not allocate DPRAM memory for p_send_q_mem_reg.",
2762 __FUNCTION__);
2763 ucc_geth_memclean(ugeth);
2764 return -ENOMEM;
2765 }
2766
2767 ugeth->p_send_q_mem_reg =
2768 (struct ucc_geth_send_queue_mem_region *) qe_muram_addr(ugeth->
2769 send_q_mem_reg_offset);
2770 out_be32(&ugeth->p_tx_glbl_pram->sqptr, ugeth->send_q_mem_reg_offset);
2771
2772 /* Setup the table */
2773 /* Assume BD rings are already established */
2774 for (i = 0; i < ug_info->numQueuesTx; i++) {
2775 endOfRing =
2776 ugeth->p_tx_bd_ring[i] + (ug_info->bdRingLenTx[i] -
2777 1) * sizeof(struct qe_bd);
2778 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
2779 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2780 (u32) virt_to_phys(ugeth->p_tx_bd_ring[i]));
2781 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2782 last_bd_completed_address,
2783 (u32) virt_to_phys(endOfRing));
2784 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
2785 MEM_PART_MURAM) {
2786 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2787 (u32) immrbar_virt_to_phys(ugeth->
2788 p_tx_bd_ring[i]));
2789 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2790 last_bd_completed_address,
2791 (u32) immrbar_virt_to_phys(endOfRing));
2792 }
2793 }
2794
2795 /* schedulerbasepointer */
2796
2797 if (ug_info->numQueuesTx > 1) {
2798 /* scheduler exists only if more than 1 tx queue */
2799 ugeth->scheduler_offset =
2800 qe_muram_alloc(sizeof(struct ucc_geth_scheduler),
2801 UCC_GETH_SCHEDULER_ALIGNMENT);
2802 if (IS_MURAM_ERR(ugeth->scheduler_offset)) {
2803 ugeth_err
2804 ("%s: Can not allocate DPRAM memory for p_scheduler.",
2805 __FUNCTION__);
2806 ucc_geth_memclean(ugeth);
2807 return -ENOMEM;
2808 }
2809
2810 ugeth->p_scheduler =
2811 (struct ucc_geth_scheduler *) qe_muram_addr(ugeth->
2812 scheduler_offset);
2813 out_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer,
2814 ugeth->scheduler_offset);
2815 /* Zero out p_scheduler */
2816 memset(ugeth->p_scheduler, 0, sizeof(struct ucc_geth_scheduler));
2817
2818 /* Set values in scheduler */
2819 out_be32(&ugeth->p_scheduler->mblinterval,
2820 ug_info->mblinterval);
2821 out_be16(&ugeth->p_scheduler->nortsrbytetime,
2822 ug_info->nortsrbytetime);
2823 ugeth->p_scheduler->fracsiz = ug_info->fracsiz;
2824 ugeth->p_scheduler->strictpriorityq = ug_info->strictpriorityq;
2825 ugeth->p_scheduler->txasap = ug_info->txasap;
2826 ugeth->p_scheduler->extrabw = ug_info->extrabw;
2827 for (i = 0; i < NUM_TX_QUEUES; i++)
2828 ugeth->p_scheduler->weightfactor[i] =
2829 ug_info->weightfactor[i];
2830
2831 /* Set pointers to cpucount registers in scheduler */
2832 ugeth->p_cpucount[0] = &(ugeth->p_scheduler->cpucount0);
2833 ugeth->p_cpucount[1] = &(ugeth->p_scheduler->cpucount1);
2834 ugeth->p_cpucount[2] = &(ugeth->p_scheduler->cpucount2);
2835 ugeth->p_cpucount[3] = &(ugeth->p_scheduler->cpucount3);
2836 ugeth->p_cpucount[4] = &(ugeth->p_scheduler->cpucount4);
2837 ugeth->p_cpucount[5] = &(ugeth->p_scheduler->cpucount5);
2838 ugeth->p_cpucount[6] = &(ugeth->p_scheduler->cpucount6);
2839 ugeth->p_cpucount[7] = &(ugeth->p_scheduler->cpucount7);
2840 }
2841
2842 /* schedulerbasepointer */
2843 /* TxRMON_PTR (statistics) */
2844 if (ug_info->
2845 statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX) {
2846 ugeth->tx_fw_statistics_pram_offset =
2847 qe_muram_alloc(sizeof
2848 (struct ucc_geth_tx_firmware_statistics_pram),
2849 UCC_GETH_TX_STATISTICS_ALIGNMENT);
2850 if (IS_MURAM_ERR(ugeth->tx_fw_statistics_pram_offset)) {
2851 ugeth_err
2852 ("%s: Can not allocate DPRAM memory for"
2853 " p_tx_fw_statistics_pram.", __FUNCTION__);
2854 ucc_geth_memclean(ugeth);
2855 return -ENOMEM;
2856 }
2857 ugeth->p_tx_fw_statistics_pram =
2858 (struct ucc_geth_tx_firmware_statistics_pram *)
2859 qe_muram_addr(ugeth->tx_fw_statistics_pram_offset);
2860 /* Zero out p_tx_fw_statistics_pram */
2861 memset(ugeth->p_tx_fw_statistics_pram,
2862 0, sizeof(struct ucc_geth_tx_firmware_statistics_pram));
2863 }
2864
2865 /* temoder */
2866 /* Already has speed set */
2867
2868 if (ug_info->numQueuesTx > 1)
2869 temoder |= TEMODER_SCHEDULER_ENABLE;
2870 if (ug_info->ipCheckSumGenerate)
2871 temoder |= TEMODER_IP_CHECKSUM_GENERATE;
2872 temoder |= ((ug_info->numQueuesTx - 1) << TEMODER_NUM_OF_QUEUES_SHIFT);
2873 out_be16(&ugeth->p_tx_glbl_pram->temoder, temoder);
2874
2875 test = in_be16(&ugeth->p_tx_glbl_pram->temoder);
2876
2877 /* Function code register value to be used later */
2878 function_code = QE_BMR_BYTE_ORDER_BO_MOT | UCC_FAST_FUNCTION_CODE_GBL;
2879 /* Required for QE */
2880
2881 /* function code register */
2882 out_be32(&ugeth->p_tx_glbl_pram->tstate, ((u32) function_code) << 24);
2883
2884 /* Rx global PRAM */
2885 /* Allocate global rx parameter RAM page */
2886 ugeth->rx_glbl_pram_offset =
2887 qe_muram_alloc(sizeof(struct ucc_geth_rx_global_pram),
2888 UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT);
2889 if (IS_MURAM_ERR(ugeth->rx_glbl_pram_offset)) {
2890 ugeth_err
2891 ("%s: Can not allocate DPRAM memory for p_rx_glbl_pram.",
2892 __FUNCTION__);
2893 ucc_geth_memclean(ugeth);
2894 return -ENOMEM;
2895 }
2896 ugeth->p_rx_glbl_pram =
2897 (struct ucc_geth_rx_global_pram *) qe_muram_addr(ugeth->
2898 rx_glbl_pram_offset);
2899 /* Zero out p_rx_glbl_pram */
2900 memset(ugeth->p_rx_glbl_pram, 0, sizeof(struct ucc_geth_rx_global_pram));
2901
2902 /* Fill global PRAM */
2903
2904 /* RQPTR */
2905 /* Size varies with number of Rx threads */
2906 ugeth->thread_dat_rx_offset =
2907 qe_muram_alloc(numThreadsRxNumerical *
2908 sizeof(struct ucc_geth_thread_data_rx),
2909 UCC_GETH_THREAD_DATA_ALIGNMENT);
2910 if (IS_MURAM_ERR(ugeth->thread_dat_rx_offset)) {
2911 ugeth_err
2912 ("%s: Can not allocate DPRAM memory for p_thread_data_rx.",
2913 __FUNCTION__);
2914 ucc_geth_memclean(ugeth);
2915 return -ENOMEM;
2916 }
2917
2918 ugeth->p_thread_data_rx =
2919 (struct ucc_geth_thread_data_rx *) qe_muram_addr(ugeth->
2920 thread_dat_rx_offset);
2921 out_be32(&ugeth->p_rx_glbl_pram->rqptr, ugeth->thread_dat_rx_offset);
2922
2923 /* typeorlen */
2924 out_be16(&ugeth->p_rx_glbl_pram->typeorlen, ug_info->typeorlen);
2925
2926 /* rxrmonbaseptr (statistics) */
2927 if (ug_info->
2928 statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX) {
2929 ugeth->rx_fw_statistics_pram_offset =
2930 qe_muram_alloc(sizeof
2931 (struct ucc_geth_rx_firmware_statistics_pram),
2932 UCC_GETH_RX_STATISTICS_ALIGNMENT);
2933 if (IS_MURAM_ERR(ugeth->rx_fw_statistics_pram_offset)) {
2934 ugeth_err
2935 ("%s: Can not allocate DPRAM memory for"
2936 " p_rx_fw_statistics_pram.", __FUNCTION__);
2937 ucc_geth_memclean(ugeth);
2938 return -ENOMEM;
2939 }
2940 ugeth->p_rx_fw_statistics_pram =
2941 (struct ucc_geth_rx_firmware_statistics_pram *)
2942 qe_muram_addr(ugeth->rx_fw_statistics_pram_offset);
2943 /* Zero out p_rx_fw_statistics_pram */
2944 memset(ugeth->p_rx_fw_statistics_pram, 0,
2945 sizeof(struct ucc_geth_rx_firmware_statistics_pram));
2946 }
2947
2948 /* intCoalescingPtr */
2949
2950 /* Size varies with number of Rx queues */
2951 ugeth->rx_irq_coalescing_tbl_offset =
2952 qe_muram_alloc(ug_info->numQueuesRx *
2953 sizeof(struct ucc_geth_rx_interrupt_coalescing_entry)
2954 + 4, UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT);
2955 if (IS_MURAM_ERR(ugeth->rx_irq_coalescing_tbl_offset)) {
2956 ugeth_err
2957 ("%s: Can not allocate DPRAM memory for"
2958 " p_rx_irq_coalescing_tbl.", __FUNCTION__);
2959 ucc_geth_memclean(ugeth);
2960 return -ENOMEM;
2961 }
2962
2963 ugeth->p_rx_irq_coalescing_tbl =
2964 (struct ucc_geth_rx_interrupt_coalescing_table *)
2965 qe_muram_addr(ugeth->rx_irq_coalescing_tbl_offset);
2966 out_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr,
2967 ugeth->rx_irq_coalescing_tbl_offset);
2968
2969 /* Fill interrupt coalescing table */
2970 for (i = 0; i < ug_info->numQueuesRx; i++) {
2971 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
2972 interruptcoalescingmaxvalue,
2973 ug_info->interruptcoalescingmaxvalue[i]);
2974 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
2975 interruptcoalescingcounter,
2976 ug_info->interruptcoalescingmaxvalue[i]);
2977 }
2978
2979 /* MRBLR */
2980 init_max_rx_buff_len(uf_info->max_rx_buf_length,
2981 &ugeth->p_rx_glbl_pram->mrblr);
2982 /* MFLR */
2983 out_be16(&ugeth->p_rx_glbl_pram->mflr, ug_info->maxFrameLength);
2984 /* MINFLR */
2985 init_min_frame_len(ug_info->minFrameLength,
2986 &ugeth->p_rx_glbl_pram->minflr,
2987 &ugeth->p_rx_glbl_pram->mrblr);
2988 /* MAXD1 */
2989 out_be16(&ugeth->p_rx_glbl_pram->maxd1, ug_info->maxD1Length);
2990 /* MAXD2 */
2991 out_be16(&ugeth->p_rx_glbl_pram->maxd2, ug_info->maxD2Length);
2992
2993 /* l2qt */
2994 l2qt = 0;
2995 for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++)
2996 l2qt |= (ug_info->l2qt[i] << (28 - 4 * i));
2997 out_be32(&ugeth->p_rx_glbl_pram->l2qt, l2qt);
2998
2999 /* l3qt */
3000 for (j = 0; j < UCC_GETH_IP_PRIORITY_MAX; j += 8) {
3001 l3qt = 0;
3002 for (i = 0; i < 8; i++)
3003 l3qt |= (ug_info->l3qt[j + i] << (28 - 4 * i));
3004 out_be32(&ugeth->p_rx_glbl_pram->l3qt[j/8], l3qt);
3005 }
3006
3007 /* vlantype */
3008 out_be16(&ugeth->p_rx_glbl_pram->vlantype, ug_info->vlantype);
3009
3010 /* vlantci */
3011 out_be16(&ugeth->p_rx_glbl_pram->vlantci, ug_info->vlantci);
3012
3013 /* ecamptr */
3014 out_be32(&ugeth->p_rx_glbl_pram->ecamptr, ug_info->ecamptr);
3015
3016 /* RBDQPTR */
3017 /* Size varies with number of Rx queues */
3018 ugeth->rx_bd_qs_tbl_offset =
3019 qe_muram_alloc(ug_info->numQueuesRx *
3020 (sizeof(struct ucc_geth_rx_bd_queues_entry) +
3021 sizeof(struct ucc_geth_rx_prefetched_bds)),
3022 UCC_GETH_RX_BD_QUEUES_ALIGNMENT);
3023 if (IS_MURAM_ERR(ugeth->rx_bd_qs_tbl_offset)) {
3024 ugeth_err
3025 ("%s: Can not allocate DPRAM memory for p_rx_bd_qs_tbl.",
3026 __FUNCTION__);
3027 ucc_geth_memclean(ugeth);
3028 return -ENOMEM;
3029 }
3030
3031 ugeth->p_rx_bd_qs_tbl =
3032 (struct ucc_geth_rx_bd_queues_entry *) qe_muram_addr(ugeth->
3033 rx_bd_qs_tbl_offset);
3034 out_be32(&ugeth->p_rx_glbl_pram->rbdqptr, ugeth->rx_bd_qs_tbl_offset);
3035 /* Zero out p_rx_bd_qs_tbl */
3036 memset(ugeth->p_rx_bd_qs_tbl,
3037 0,
3038 ug_info->numQueuesRx * (sizeof(struct ucc_geth_rx_bd_queues_entry) +
3039 sizeof(struct ucc_geth_rx_prefetched_bds)));
3040
3041 /* Setup the table */
3042 /* Assume BD rings are already established */
3043 for (i = 0; i < ug_info->numQueuesRx; i++) {
3044 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
3045 out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
3046 (u32) virt_to_phys(ugeth->p_rx_bd_ring[i]));
3047 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
3048 MEM_PART_MURAM) {
3049 out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
3050 (u32) immrbar_virt_to_phys(ugeth->
3051 p_rx_bd_ring[i]));
3052 }
3053 /* rest of fields handled by QE */
3054 }
3055
3056 /* remoder */
3057 /* Already has speed set */
3058
3059 if (ugeth->rx_extended_features)
3060 remoder |= REMODER_RX_EXTENDED_FEATURES;
3061 if (ug_info->rxExtendedFiltering)
3062 remoder |= REMODER_RX_EXTENDED_FILTERING;
3063 if (ug_info->dynamicMaxFrameLength)
3064 remoder |= REMODER_DYNAMIC_MAX_FRAME_LENGTH;
3065 if (ug_info->dynamicMinFrameLength)
3066 remoder |= REMODER_DYNAMIC_MIN_FRAME_LENGTH;
3067 remoder |=
3068 ug_info->vlanOperationTagged << REMODER_VLAN_OPERATION_TAGGED_SHIFT;
3069 remoder |=
3070 ug_info->
3071 vlanOperationNonTagged << REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT;
3072 remoder |= ug_info->rxQoSMode << REMODER_RX_QOS_MODE_SHIFT;
3073 remoder |= ((ug_info->numQueuesRx - 1) << REMODER_NUM_OF_QUEUES_SHIFT);
3074 if (ug_info->ipCheckSumCheck)
3075 remoder |= REMODER_IP_CHECKSUM_CHECK;
3076 if (ug_info->ipAddressAlignment)
3077 remoder |= REMODER_IP_ADDRESS_ALIGNMENT;
3078 out_be32(&ugeth->p_rx_glbl_pram->remoder, remoder);
3079
3080 /* Note that this function must be called */
3081 /* ONLY AFTER p_tx_fw_statistics_pram */
3082 /* andp_UccGethRxFirmwareStatisticsPram are allocated ! */
3083 init_firmware_statistics_gathering_mode((ug_info->
3084 statisticsMode &
3085 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX),
3086 (ug_info->statisticsMode &
3087 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX),
3088 &ugeth->p_tx_glbl_pram->txrmonbaseptr,
3089 ugeth->tx_fw_statistics_pram_offset,
3090 &ugeth->p_rx_glbl_pram->rxrmonbaseptr,
3091 ugeth->rx_fw_statistics_pram_offset,
3092 &ugeth->p_tx_glbl_pram->temoder,
3093 &ugeth->p_rx_glbl_pram->remoder);
3094
3095 /* function code register */
3096 ugeth->p_rx_glbl_pram->rstate = function_code;
3097
3098 /* initialize extended filtering */
3099 if (ug_info->rxExtendedFiltering) {
3100 if (!ug_info->extendedFilteringChainPointer) {
3101 ugeth_err("%s: Null Extended Filtering Chain Pointer.",
3102 __FUNCTION__);
3103 ucc_geth_memclean(ugeth);
3104 return -EINVAL;
3105 }
3106
3107 /* Allocate memory for extended filtering Mode Global
3108 Parameters */
3109 ugeth->exf_glbl_param_offset =
3110 qe_muram_alloc(sizeof(struct ucc_geth_exf_global_pram),
3111 UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT);
3112 if (IS_MURAM_ERR(ugeth->exf_glbl_param_offset)) {
3113 ugeth_err
3114 ("%s: Can not allocate DPRAM memory for"
3115 " p_exf_glbl_param.", __FUNCTION__);
3116 ucc_geth_memclean(ugeth);
3117 return -ENOMEM;
3118 }
3119
3120 ugeth->p_exf_glbl_param =
3121 (struct ucc_geth_exf_global_pram *) qe_muram_addr(ugeth->
3122 exf_glbl_param_offset);
3123 out_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam,
3124 ugeth->exf_glbl_param_offset);
3125 out_be32(&ugeth->p_exf_glbl_param->l2pcdptr,
3126 (u32) ug_info->extendedFilteringChainPointer);
3127
3128 } else { /* initialize 82xx style address filtering */
3129
3130 /* Init individual address recognition registers to disabled */
3131
3132 for (j = 0; j < NUM_OF_PADDRS; j++)
3133 ugeth_82xx_filtering_clear_addr_in_paddr(ugeth, (u8) j);
3134
3135 /* Create CQs for hash tables */
3136 if (ug_info->maxGroupAddrInHash > 0) {
3137 INIT_LIST_HEAD(&ugeth->group_hash_q);
3138 }
3139 if (ug_info->maxIndAddrInHash > 0) {
3140 INIT_LIST_HEAD(&ugeth->ind_hash_q);
3141 }
3142 p_82xx_addr_filt =
3143 (struct ucc_geth_82xx_address_filtering_pram *) ugeth->
3144 p_rx_glbl_pram->addressfiltering;
3145
3146 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
3147 ENET_ADDR_TYPE_GROUP);
3148 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
3149 ENET_ADDR_TYPE_INDIVIDUAL);
3150 }
3151
3152 /*
3153 * Initialize UCC at QE level
3154 */
3155
3156 command = QE_INIT_TX_RX;
3157
3158 /* Allocate shadow InitEnet command parameter structure.
3159 * This is needed because after the InitEnet command is executed,
3160 * the structure in DPRAM is released, because DPRAM is a premium
3161 * resource.
3162 * This shadow structure keeps a copy of what was done so that the
3163 * allocated resources can be released when the channel is freed.
3164 */
3165 if (!(ugeth->p_init_enet_param_shadow =
3166 kmalloc(sizeof(struct ucc_geth_init_pram), GFP_KERNEL))) {
3167 ugeth_err
3168 ("%s: Can not allocate memory for"
3169 " p_UccInitEnetParamShadows.", __FUNCTION__);
3170 ucc_geth_memclean(ugeth);
3171 return -ENOMEM;
3172 }
3173 /* Zero out *p_init_enet_param_shadow */
3174 memset((char *)ugeth->p_init_enet_param_shadow,
3175 0, sizeof(struct ucc_geth_init_pram));
3176
3177 /* Fill shadow InitEnet command parameter structure */
3178
3179 ugeth->p_init_enet_param_shadow->resinit1 =
3180 ENET_INIT_PARAM_MAGIC_RES_INIT1;
3181 ugeth->p_init_enet_param_shadow->resinit2 =
3182 ENET_INIT_PARAM_MAGIC_RES_INIT2;
3183 ugeth->p_init_enet_param_shadow->resinit3 =
3184 ENET_INIT_PARAM_MAGIC_RES_INIT3;
3185 ugeth->p_init_enet_param_shadow->resinit4 =
3186 ENET_INIT_PARAM_MAGIC_RES_INIT4;
3187 ugeth->p_init_enet_param_shadow->resinit5 =
3188 ENET_INIT_PARAM_MAGIC_RES_INIT5;
3189 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
3190 ((u32) ug_info->numThreadsRx) << ENET_INIT_PARAM_RGF_SHIFT;
3191 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
3192 ((u32) ug_info->numThreadsTx) << ENET_INIT_PARAM_TGF_SHIFT;
3193
3194 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
3195 ugeth->rx_glbl_pram_offset | ug_info->riscRx;
3196 if ((ug_info->largestexternallookupkeysize !=
3197 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE)
3198 && (ug_info->largestexternallookupkeysize !=
3199 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
3200 && (ug_info->largestexternallookupkeysize !=
3201 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES)) {
3202 ugeth_err("%s: Invalid largest External Lookup Key Size.",
3203 __FUNCTION__);
3204 ucc_geth_memclean(ugeth);
3205 return -EINVAL;
3206 }
3207 ugeth->p_init_enet_param_shadow->largestexternallookupkeysize =
3208 ug_info->largestexternallookupkeysize;
3209 size = sizeof(struct ucc_geth_thread_rx_pram);
3210 if (ug_info->rxExtendedFiltering) {
3211 size += THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
3212 if (ug_info->largestexternallookupkeysize ==
3213 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
3214 size +=
3215 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
3216 if (ug_info->largestexternallookupkeysize ==
3217 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
3218 size +=
3219 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
3220 }
3221
3222 if ((ret_val = fill_init_enet_entries(ugeth, &(ugeth->
3223 p_init_enet_param_shadow->rxthread[0]),
3224 (u8) (numThreadsRxNumerical + 1)
3225 /* Rx needs one extra for terminator */
3226 , size, UCC_GETH_THREAD_RX_PRAM_ALIGNMENT,
3227 ug_info->riscRx, 1)) != 0) {
3228 ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
3229 __FUNCTION__);
3230 ucc_geth_memclean(ugeth);
3231 return ret_val;
3232 }
3233
3234 ugeth->p_init_enet_param_shadow->txglobal =
3235 ugeth->tx_glbl_pram_offset | ug_info->riscTx;
3236 if ((ret_val =
3237 fill_init_enet_entries(ugeth,
3238 &(ugeth->p_init_enet_param_shadow->
3239 txthread[0]), numThreadsTxNumerical,
3240 sizeof(struct ucc_geth_thread_tx_pram),
3241 UCC_GETH_THREAD_TX_PRAM_ALIGNMENT,
3242 ug_info->riscTx, 0)) != 0) {
3243 ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
3244 __FUNCTION__);
3245 ucc_geth_memclean(ugeth);
3246 return ret_val;
3247 }
3248
3249 /* Load Rx bds with buffers */
3250 for (i = 0; i < ug_info->numQueuesRx; i++) {
3251 if ((ret_val = rx_bd_buffer_set(ugeth, (u8) i)) != 0) {
3252 ugeth_err("%s: Can not fill Rx bds with buffers.",
3253 __FUNCTION__);
3254 ucc_geth_memclean(ugeth);
3255 return ret_val;
3256 }
3257 }
3258
3259 /* Allocate InitEnet command parameter structure */
3260 init_enet_pram_offset = qe_muram_alloc(sizeof(struct ucc_geth_init_pram), 4);
3261 if (IS_MURAM_ERR(init_enet_pram_offset)) {
3262 ugeth_err
3263 ("%s: Can not allocate DPRAM memory for p_init_enet_pram.",
3264 __FUNCTION__);
3265 ucc_geth_memclean(ugeth);
3266 return -ENOMEM;
3267 }
3268 p_init_enet_pram =
3269 (struct ucc_geth_init_pram *) qe_muram_addr(init_enet_pram_offset);
3270
3271 /* Copy shadow InitEnet command parameter structure into PRAM */
3272 p_init_enet_pram->resinit1 = ugeth->p_init_enet_param_shadow->resinit1;
3273 p_init_enet_pram->resinit2 = ugeth->p_init_enet_param_shadow->resinit2;
3274 p_init_enet_pram->resinit3 = ugeth->p_init_enet_param_shadow->resinit3;
3275 p_init_enet_pram->resinit4 = ugeth->p_init_enet_param_shadow->resinit4;
3276 out_be16(&p_init_enet_pram->resinit5,
3277 ugeth->p_init_enet_param_shadow->resinit5);
3278 p_init_enet_pram->largestexternallookupkeysize =
3279 ugeth->p_init_enet_param_shadow->largestexternallookupkeysize;
3280 out_be32(&p_init_enet_pram->rgftgfrxglobal,
3281 ugeth->p_init_enet_param_shadow->rgftgfrxglobal);
3282 for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_RX; i++)
3283 out_be32(&p_init_enet_pram->rxthread[i],
3284 ugeth->p_init_enet_param_shadow->rxthread[i]);
3285 out_be32(&p_init_enet_pram->txglobal,
3286 ugeth->p_init_enet_param_shadow->txglobal);
3287 for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_TX; i++)
3288 out_be32(&p_init_enet_pram->txthread[i],
3289 ugeth->p_init_enet_param_shadow->txthread[i]);
3290
3291 /* Issue QE command */
3292 cecr_subblock =
3293 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
3294 qe_issue_cmd(command, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
3295 init_enet_pram_offset);
3296
3297 /* Free InitEnet command parameter */
3298 qe_muram_free(init_enet_pram_offset);
3299
3300 return 0;
3301 }
3302
3303 /* returns a net_device_stats structure pointer */
3304 static struct net_device_stats *ucc_geth_get_stats(struct net_device *dev)
3305 {
3306 struct ucc_geth_private *ugeth = netdev_priv(dev);
3307
3308 return &(ugeth->stats);
3309 }
3310
3311 /* ucc_geth_timeout gets called when a packet has not been
3312 * transmitted after a set amount of time.
3313 * For now, assume that clearing out all the structures, and
3314 * starting over will fix the problem. */
3315 static void ucc_geth_timeout(struct net_device *dev)
3316 {
3317 struct ucc_geth_private *ugeth = netdev_priv(dev);
3318
3319 ugeth_vdbg("%s: IN", __FUNCTION__);
3320
3321 ugeth->stats.tx_errors++;
3322
3323 ugeth_dump_regs(ugeth);
3324
3325 if (dev->flags & IFF_UP) {
3326 ucc_geth_stop(ugeth);
3327 ucc_geth_startup(ugeth);
3328 }
3329
3330 netif_schedule(dev);
3331 }
3332
3333 /* This is called by the kernel when a frame is ready for transmission. */
3334 /* It is pointed to by the dev->hard_start_xmit function pointer */
3335 static int ucc_geth_start_xmit(struct sk_buff *skb, struct net_device *dev)
3336 {
3337 struct ucc_geth_private *ugeth = netdev_priv(dev);
3338 #ifdef CONFIG_UGETH_TX_ON_DEMAND
3339 struct ucc_fast_private *uccf;
3340 #endif
3341 u8 *bd; /* BD pointer */
3342 u32 bd_status;
3343 u8 txQ = 0;
3344
3345 ugeth_vdbg("%s: IN", __FUNCTION__);
3346
3347 spin_lock_irq(&ugeth->lock);
3348
3349 ugeth->stats.tx_bytes += skb->len;
3350
3351 /* Start from the next BD that should be filled */
3352 bd = ugeth->txBd[txQ];
3353 bd_status = in_be32((u32 *)bd);
3354 /* Save the skb pointer so we can free it later */
3355 ugeth->tx_skbuff[txQ][ugeth->skb_curtx[txQ]] = skb;
3356
3357 /* Update the current skb pointer (wrapping if this was the last) */
3358 ugeth->skb_curtx[txQ] =
3359 (ugeth->skb_curtx[txQ] +
3360 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3361
3362 /* set up the buffer descriptor */
3363 out_be32(&((struct qe_bd *)bd)->buf,
3364 dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE));
3365
3366 /* printk(KERN_DEBUG"skb->data is 0x%x\n",skb->data); */
3367
3368 bd_status = (bd_status & T_W) | T_R | T_I | T_L | skb->len;
3369
3370 /* set bd status and length */
3371 out_be32((u32 *)bd, bd_status);
3372
3373 dev->trans_start = jiffies;
3374
3375 /* Move to next BD in the ring */
3376 if (!(bd_status & T_W))
3377 bd += sizeof(struct qe_bd);
3378 else
3379 bd = ugeth->p_tx_bd_ring[txQ];
3380
3381 /* If the next BD still needs to be cleaned up, then the bds
3382 are full. We need to tell the kernel to stop sending us stuff. */
3383 if (bd == ugeth->confBd[txQ]) {
3384 if (!netif_queue_stopped(dev))
3385 netif_stop_queue(dev);
3386 }
3387
3388 ugeth->txBd[txQ] = bd;
3389
3390 if (ugeth->p_scheduler) {
3391 ugeth->cpucount[txQ]++;
3392 /* Indicate to QE that there are more Tx bds ready for
3393 transmission */
3394 /* This is done by writing a running counter of the bd
3395 count to the scheduler PRAM. */
3396 out_be16(ugeth->p_cpucount[txQ], ugeth->cpucount[txQ]);
3397 }
3398
3399 #ifdef CONFIG_UGETH_TX_ON_DEMAND
3400 uccf = ugeth->uccf;
3401 out_be16(uccf->p_utodr, UCC_FAST_TOD);
3402 #endif
3403 spin_unlock_irq(&ugeth->lock);
3404
3405 return 0;
3406 }
3407
3408 static int ucc_geth_rx(struct ucc_geth_private *ugeth, u8 rxQ, int rx_work_limit)
3409 {
3410 struct sk_buff *skb;
3411 u8 *bd;
3412 u16 length, howmany = 0;
3413 u32 bd_status;
3414 u8 *bdBuffer;
3415
3416 ugeth_vdbg("%s: IN", __FUNCTION__);
3417
3418 /* collect received buffers */
3419 bd = ugeth->rxBd[rxQ];
3420
3421 bd_status = in_be32((u32 *)bd);
3422
3423 /* while there are received buffers and BD is full (~R_E) */
3424 while (!((bd_status & (R_E)) || (--rx_work_limit < 0))) {
3425 bdBuffer = (u8 *) in_be32(&((struct qe_bd *)bd)->buf);
3426 length = (u16) ((bd_status & BD_LENGTH_MASK) - 4);
3427 skb = ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]];
3428
3429 /* determine whether buffer is first, last, first and last
3430 (single buffer frame) or middle (not first and not last) */
3431 if (!skb ||
3432 (!(bd_status & (R_F | R_L))) ||
3433 (bd_status & R_ERRORS_FATAL)) {
3434 ugeth_vdbg("%s, %d: ERROR!!! skb - 0x%08x",
3435 __FUNCTION__, __LINE__, (u32) skb);
3436 if (skb)
3437 dev_kfree_skb_any(skb);
3438
3439 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = NULL;
3440 ugeth->stats.rx_dropped++;
3441 } else {
3442 ugeth->stats.rx_packets++;
3443 howmany++;
3444
3445 /* Prep the skb for the packet */
3446 skb_put(skb, length);
3447
3448 /* Tell the skb what kind of packet this is */
3449 skb->protocol = eth_type_trans(skb, ugeth->dev);
3450
3451 ugeth->stats.rx_bytes += length;
3452 /* Send the packet up the stack */
3453 #ifdef CONFIG_UGETH_NAPI
3454 netif_receive_skb(skb);
3455 #else
3456 netif_rx(skb);
3457 #endif /* CONFIG_UGETH_NAPI */
3458 }
3459
3460 ugeth->dev->last_rx = jiffies;
3461
3462 skb = get_new_skb(ugeth, bd);
3463 if (!skb) {
3464 ugeth_warn("%s: No Rx Data Buffer", __FUNCTION__);
3465 ugeth->stats.rx_dropped++;
3466 break;
3467 }
3468
3469 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = skb;
3470
3471 /* update to point at the next skb */
3472 ugeth->skb_currx[rxQ] =
3473 (ugeth->skb_currx[rxQ] +
3474 1) & RX_RING_MOD_MASK(ugeth->ug_info->bdRingLenRx[rxQ]);
3475
3476 if (bd_status & R_W)
3477 bd = ugeth->p_rx_bd_ring[rxQ];
3478 else
3479 bd += sizeof(struct qe_bd);
3480
3481 bd_status = in_be32((u32 *)bd);
3482 }
3483
3484 ugeth->rxBd[rxQ] = bd;
3485 return howmany;
3486 }
3487
3488 static int ucc_geth_tx(struct net_device *dev, u8 txQ)
3489 {
3490 /* Start from the next BD that should be filled */
3491 struct ucc_geth_private *ugeth = netdev_priv(dev);
3492 u8 *bd; /* BD pointer */
3493 u32 bd_status;
3494
3495 bd = ugeth->confBd[txQ];
3496 bd_status = in_be32((u32 *)bd);
3497
3498 /* Normal processing. */
3499 while ((bd_status & T_R) == 0) {
3500 /* BD contains already transmitted buffer. */
3501 /* Handle the transmitted buffer and release */
3502 /* the BD to be used with the current frame */
3503
3504 if ((bd == ugeth->txBd[txQ]) && (netif_queue_stopped(dev) == 0))
3505 break;
3506
3507 ugeth->stats.tx_packets++;
3508
3509 /* Free the sk buffer associated with this TxBD */
3510 dev_kfree_skb_irq(ugeth->
3511 tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]]);
3512 ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]] = NULL;
3513 ugeth->skb_dirtytx[txQ] =
3514 (ugeth->skb_dirtytx[txQ] +
3515 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3516
3517 /* We freed a buffer, so now we can restart transmission */
3518 if (netif_queue_stopped(dev))
3519 netif_wake_queue(dev);
3520
3521 /* Advance the confirmation BD pointer */
3522 if (!(bd_status & T_W))
3523 bd += sizeof(struct qe_bd);
3524 else
3525 bd = ugeth->p_tx_bd_ring[txQ];
3526 bd_status = in_be32((u32 *)bd);
3527 }
3528 ugeth->confBd[txQ] = bd;
3529 return 0;
3530 }
3531
3532 #ifdef CONFIG_UGETH_NAPI
3533 static int ucc_geth_poll(struct net_device *dev, int *budget)
3534 {
3535 struct ucc_geth_private *ugeth = netdev_priv(dev);
3536 struct ucc_geth_info *ug_info;
3537 struct ucc_fast_private *uccf;
3538 int howmany;
3539 u8 i;
3540 int rx_work_limit;
3541 register u32 uccm;
3542
3543 ug_info = ugeth->ug_info;
3544
3545 rx_work_limit = *budget;
3546 if (rx_work_limit > dev->quota)
3547 rx_work_limit = dev->quota;
3548
3549 howmany = 0;
3550
3551 for (i = 0; i < ug_info->numQueuesRx; i++) {
3552 howmany += ucc_geth_rx(ugeth, i, rx_work_limit);
3553 }
3554
3555 dev->quota -= howmany;
3556 rx_work_limit -= howmany;
3557 *budget -= howmany;
3558
3559 if (rx_work_limit > 0) {
3560 netif_rx_complete(dev);
3561 uccf = ugeth->uccf;
3562 uccm = in_be32(uccf->p_uccm);
3563 uccm |= UCCE_RX_EVENTS;
3564 out_be32(uccf->p_uccm, uccm);
3565 }
3566
3567 return (rx_work_limit > 0) ? 0 : 1;
3568 }
3569 #endif /* CONFIG_UGETH_NAPI */
3570
3571 static irqreturn_t ucc_geth_irq_handler(int irq, void *info)
3572 {
3573 struct net_device *dev = (struct net_device *)info;
3574 struct ucc_geth_private *ugeth = netdev_priv(dev);
3575 struct ucc_fast_private *uccf;
3576 struct ucc_geth_info *ug_info;
3577 register u32 ucce;
3578 register u32 uccm;
3579 #ifndef CONFIG_UGETH_NAPI
3580 register u32 rx_mask;
3581 #endif
3582 register u32 tx_mask;
3583 u8 i;
3584
3585 ugeth_vdbg("%s: IN", __FUNCTION__);
3586
3587 if (!ugeth)
3588 return IRQ_NONE;
3589
3590 uccf = ugeth->uccf;
3591 ug_info = ugeth->ug_info;
3592
3593 /* read and clear events */
3594 ucce = (u32) in_be32(uccf->p_ucce);
3595 uccm = (u32) in_be32(uccf->p_uccm);
3596 ucce &= uccm;
3597 out_be32(uccf->p_ucce, ucce);
3598
3599 /* check for receive events that require processing */
3600 if (ucce & UCCE_RX_EVENTS) {
3601 #ifdef CONFIG_UGETH_NAPI
3602 if (netif_rx_schedule_prep(dev)) {
3603 uccm &= ~UCCE_RX_EVENTS;
3604 out_be32(uccf->p_uccm, uccm);
3605 __netif_rx_schedule(dev);
3606 }
3607 #else
3608 rx_mask = UCCE_RXBF_SINGLE_MASK;
3609 for (i = 0; i < ug_info->numQueuesRx; i++) {
3610 if (ucce & rx_mask)
3611 ucc_geth_rx(ugeth, i, (int)ugeth->ug_info->bdRingLenRx[i]);
3612 ucce &= ~rx_mask;
3613 rx_mask <<= 1;
3614 }
3615 #endif /* CONFIG_UGETH_NAPI */
3616 }
3617
3618 /* Tx event processing */
3619 if (ucce & UCCE_TX_EVENTS) {
3620 spin_lock(&ugeth->lock);
3621 tx_mask = UCCE_TXBF_SINGLE_MASK;
3622 for (i = 0; i < ug_info->numQueuesTx; i++) {
3623 if (ucce & tx_mask)
3624 ucc_geth_tx(dev, i);
3625 ucce &= ~tx_mask;
3626 tx_mask <<= 1;
3627 }
3628 spin_unlock(&ugeth->lock);
3629 }
3630
3631 /* Errors and other events */
3632 if (ucce & UCCE_OTHER) {
3633 if (ucce & UCCE_BSY) {
3634 ugeth->stats.rx_errors++;
3635 }
3636 if (ucce & UCCE_TXE) {
3637 ugeth->stats.tx_errors++;
3638 }
3639 }
3640
3641 return IRQ_HANDLED;
3642 }
3643
3644 /* Called when something needs to use the ethernet device */
3645 /* Returns 0 for success. */
3646 static int ucc_geth_open(struct net_device *dev)
3647 {
3648 struct ucc_geth_private *ugeth = netdev_priv(dev);
3649 int err;
3650
3651 ugeth_vdbg("%s: IN", __FUNCTION__);
3652
3653 /* Test station address */
3654 if (dev->dev_addr[0] & ENET_GROUP_ADDR) {
3655 ugeth_err("%s: Multicast address used for station address"
3656 " - is this what you wanted?", __FUNCTION__);
3657 return -EINVAL;
3658 }
3659
3660 err = ucc_struct_init(ugeth);
3661 if (err) {
3662 ugeth_err("%s: Cannot configure internal struct, aborting.", dev->name);
3663 return err;
3664 }
3665
3666 err = ucc_geth_startup(ugeth);
3667 if (err) {
3668 ugeth_err("%s: Cannot configure net device, aborting.",
3669 dev->name);
3670 return err;
3671 }
3672
3673 err = adjust_enet_interface(ugeth);
3674 if (err) {
3675 ugeth_err("%s: Cannot configure net device, aborting.",
3676 dev->name);
3677 return err;
3678 }
3679
3680 /* Set MACSTNADDR1, MACSTNADDR2 */
3681 /* For more details see the hardware spec. */
3682 init_mac_station_addr_regs(dev->dev_addr[0],
3683 dev->dev_addr[1],
3684 dev->dev_addr[2],
3685 dev->dev_addr[3],
3686 dev->dev_addr[4],
3687 dev->dev_addr[5],
3688 &ugeth->ug_regs->macstnaddr1,
3689 &ugeth->ug_regs->macstnaddr2);
3690
3691 err = init_phy(dev);
3692 if (err) {
3693 ugeth_err("%s: Cannot initialize PHY, aborting.", dev->name);
3694 return err;
3695 }
3696
3697 phy_start(ugeth->phydev);
3698
3699 err =
3700 request_irq(ugeth->ug_info->uf_info.irq, ucc_geth_irq_handler, 0,
3701 "UCC Geth", dev);
3702 if (err) {
3703 ugeth_err("%s: Cannot get IRQ for net device, aborting.",
3704 dev->name);
3705 ucc_geth_stop(ugeth);
3706 return err;
3707 }
3708
3709 err = ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
3710 if (err) {
3711 ugeth_err("%s: Cannot enable net device, aborting.", dev->name);
3712 ucc_geth_stop(ugeth);
3713 return err;
3714 }
3715
3716 netif_start_queue(dev);
3717
3718 return err;
3719 }
3720
3721 /* Stops the kernel queue, and halts the controller */
3722 static int ucc_geth_close(struct net_device *dev)
3723 {
3724 struct ucc_geth_private *ugeth = netdev_priv(dev);
3725
3726 ugeth_vdbg("%s: IN", __FUNCTION__);
3727
3728 ucc_geth_stop(ugeth);
3729
3730 phy_disconnect(ugeth->phydev);
3731 ugeth->phydev = NULL;
3732
3733 netif_stop_queue(dev);
3734
3735 return 0;
3736 }
3737
3738 const struct ethtool_ops ucc_geth_ethtool_ops = { };
3739
3740 static phy_interface_t to_phy_interface(const char *interface_type)
3741 {
3742 if (strcasecmp(interface_type, "mii") == 0)
3743 return PHY_INTERFACE_MODE_MII;
3744 if (strcasecmp(interface_type, "gmii") == 0)
3745 return PHY_INTERFACE_MODE_GMII;
3746 if (strcasecmp(interface_type, "tbi") == 0)
3747 return PHY_INTERFACE_MODE_TBI;
3748 if (strcasecmp(interface_type, "rmii") == 0)
3749 return PHY_INTERFACE_MODE_RMII;
3750 if (strcasecmp(interface_type, "rgmii") == 0)
3751 return PHY_INTERFACE_MODE_RGMII;
3752 if (strcasecmp(interface_type, "rgmii-id") == 0)
3753 return PHY_INTERFACE_MODE_RGMII_ID;
3754 if (strcasecmp(interface_type, "rtbi") == 0)
3755 return PHY_INTERFACE_MODE_RTBI;
3756
3757 return PHY_INTERFACE_MODE_MII;
3758 }
3759
3760 static int ucc_geth_probe(struct of_device* ofdev, const struct of_device_id *match)
3761 {
3762 struct device *device = &ofdev->dev;
3763 struct device_node *np = ofdev->node;
3764 struct device_node *mdio;
3765 struct net_device *dev = NULL;
3766 struct ucc_geth_private *ugeth = NULL;
3767 struct ucc_geth_info *ug_info;
3768 struct resource res;
3769 struct device_node *phy;
3770 int err, ucc_num, max_speed = 0;
3771 const phandle *ph;
3772 const unsigned int *prop;
3773 const void *mac_addr;
3774 phy_interface_t phy_interface;
3775 static const int enet_to_speed[] = {
3776 SPEED_10, SPEED_10, SPEED_10,
3777 SPEED_100, SPEED_100, SPEED_100,
3778 SPEED_1000, SPEED_1000, SPEED_1000, SPEED_1000,
3779 };
3780 static const phy_interface_t enet_to_phy_interface[] = {
3781 PHY_INTERFACE_MODE_MII, PHY_INTERFACE_MODE_RMII,
3782 PHY_INTERFACE_MODE_RGMII, PHY_INTERFACE_MODE_MII,
3783 PHY_INTERFACE_MODE_RMII, PHY_INTERFACE_MODE_RGMII,
3784 PHY_INTERFACE_MODE_GMII, PHY_INTERFACE_MODE_RGMII,
3785 PHY_INTERFACE_MODE_TBI, PHY_INTERFACE_MODE_RTBI,
3786 };
3787
3788 ugeth_vdbg("%s: IN", __FUNCTION__);
3789
3790 prop = get_property(np, "device-id", NULL);
3791 ucc_num = *prop - 1;
3792 if ((ucc_num < 0) || (ucc_num > 7))
3793 return -ENODEV;
3794
3795 ug_info = &ugeth_info[ucc_num];
3796 ug_info->uf_info.ucc_num = ucc_num;
3797
3798 prop = get_property(np, "rx-clock", NULL);
3799 ug_info->uf_info.rx_clock = *prop;
3800 prop = get_property(np, "tx-clock", NULL);
3801 ug_info->uf_info.tx_clock = *prop;
3802 err = of_address_to_resource(np, 0, &res);
3803 if (err)
3804 return -EINVAL;
3805
3806 ug_info->uf_info.regs = res.start;
3807 ug_info->uf_info.irq = irq_of_parse_and_map(np, 0);
3808
3809 ph = get_property(np, "phy-handle", NULL);
3810 phy = of_find_node_by_phandle(*ph);
3811
3812 if (phy == NULL)
3813 return -ENODEV;
3814
3815 /* set the PHY address */
3816 prop = get_property(phy, "reg", NULL);
3817 if (prop == NULL)
3818 return -1;
3819 ug_info->phy_address = *prop;
3820
3821 /* get the phy interface type, or default to MII */
3822 prop = get_property(np, "interface-type", NULL);
3823 if (!prop) {
3824 /* handle interface property present in old trees */
3825 prop = get_property(phy, "interface", NULL);
3826 if (prop != NULL)
3827 phy_interface = enet_to_phy_interface[*prop];
3828 else
3829 phy_interface = PHY_INTERFACE_MODE_MII;
3830 } else {
3831 phy_interface = to_phy_interface((const char *)prop);
3832 }
3833
3834 /* get speed, or derive from interface */
3835 prop = get_property(np, "max-speed", NULL);
3836 if (!prop) {
3837 /* handle interface property present in old trees */
3838 prop = get_property(phy, "interface", NULL);
3839 if (prop != NULL)
3840 max_speed = enet_to_speed[*prop];
3841 } else {
3842 max_speed = *prop;
3843 }
3844 if (!max_speed) {
3845 switch (phy_interface) {
3846 case PHY_INTERFACE_MODE_GMII:
3847 case PHY_INTERFACE_MODE_RGMII:
3848 case PHY_INTERFACE_MODE_RGMII_ID:
3849 case PHY_INTERFACE_MODE_TBI:
3850 case PHY_INTERFACE_MODE_RTBI:
3851 max_speed = SPEED_1000;
3852 break;
3853 default:
3854 max_speed = SPEED_100;
3855 break;
3856 }
3857 }
3858
3859 if (max_speed == SPEED_1000) {
3860 ug_info->uf_info.urfs = UCC_GETH_URFS_GIGA_INIT;
3861 ug_info->uf_info.urfet = UCC_GETH_URFET_GIGA_INIT;
3862 ug_info->uf_info.urfset = UCC_GETH_URFSET_GIGA_INIT;
3863 ug_info->uf_info.utfs = UCC_GETH_UTFS_GIGA_INIT;
3864 ug_info->uf_info.utfet = UCC_GETH_UTFET_GIGA_INIT;
3865 ug_info->uf_info.utftt = UCC_GETH_UTFTT_GIGA_INIT;
3866 }
3867
3868 /* Set the bus id */
3869 mdio = of_get_parent(phy);
3870
3871 if (mdio == NULL)
3872 return -1;
3873
3874 err = of_address_to_resource(mdio, 0, &res);
3875 of_node_put(mdio);
3876
3877 if (err)
3878 return -1;
3879
3880 ug_info->mdio_bus = res.start;
3881
3882 printk(KERN_INFO "ucc_geth: UCC%1d at 0x%8x (irq = %d) \n",
3883 ug_info->uf_info.ucc_num + 1, ug_info->uf_info.regs,
3884 ug_info->uf_info.irq);
3885
3886 if (ug_info == NULL) {
3887 ugeth_err("%s: [%d] Missing additional data!", __FUNCTION__,
3888 ucc_num);
3889 return -ENODEV;
3890 }
3891
3892 /* Create an ethernet device instance */
3893 dev = alloc_etherdev(sizeof(*ugeth));
3894
3895 if (dev == NULL)
3896 return -ENOMEM;
3897
3898 ugeth = netdev_priv(dev);
3899 spin_lock_init(&ugeth->lock);
3900
3901 dev_set_drvdata(device, dev);
3902
3903 /* Set the dev->base_addr to the gfar reg region */
3904 dev->base_addr = (unsigned long)(ug_info->uf_info.regs);
3905
3906 SET_MODULE_OWNER(dev);
3907 SET_NETDEV_DEV(dev, device);
3908
3909 /* Fill in the dev structure */
3910 dev->open = ucc_geth_open;
3911 dev->hard_start_xmit = ucc_geth_start_xmit;
3912 dev->tx_timeout = ucc_geth_timeout;
3913 dev->watchdog_timeo = TX_TIMEOUT;
3914 #ifdef CONFIG_UGETH_NAPI
3915 dev->poll = ucc_geth_poll;
3916 dev->weight = UCC_GETH_DEV_WEIGHT;
3917 #endif /* CONFIG_UGETH_NAPI */
3918 dev->stop = ucc_geth_close;
3919 dev->get_stats = ucc_geth_get_stats;
3920 // dev->change_mtu = ucc_geth_change_mtu;
3921 dev->mtu = 1500;
3922 dev->set_multicast_list = ucc_geth_set_multi;
3923 dev->ethtool_ops = &ucc_geth_ethtool_ops;
3924
3925 ugeth->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
3926 ugeth->phy_interface = phy_interface;
3927 ugeth->max_speed = max_speed;
3928
3929 err = register_netdev(dev);
3930 if (err) {
3931 ugeth_err("%s: Cannot register net device, aborting.",
3932 dev->name);
3933 free_netdev(dev);
3934 return err;
3935 }
3936
3937 mac_addr = of_get_mac_address(np);
3938 if (mac_addr)
3939 memcpy(dev->dev_addr, mac_addr, 6);
3940
3941 ugeth->ug_info = ug_info;
3942 ugeth->dev = dev;
3943
3944 return 0;
3945 }
3946
3947 static int ucc_geth_remove(struct of_device* ofdev)
3948 {
3949 struct device *device = &ofdev->dev;
3950 struct net_device *dev = dev_get_drvdata(device);
3951 struct ucc_geth_private *ugeth = netdev_priv(dev);
3952
3953 dev_set_drvdata(device, NULL);
3954 ucc_geth_memclean(ugeth);
3955 free_netdev(dev);
3956
3957 return 0;
3958 }
3959
3960 static struct of_device_id ucc_geth_match[] = {
3961 {
3962 .type = "network",
3963 .compatible = "ucc_geth",
3964 },
3965 {},
3966 };
3967
3968 MODULE_DEVICE_TABLE(of, ucc_geth_match);
3969
3970 static struct of_platform_driver ucc_geth_driver = {
3971 .name = DRV_NAME,
3972 .match_table = ucc_geth_match,
3973 .probe = ucc_geth_probe,
3974 .remove = ucc_geth_remove,
3975 };
3976
3977 static int __init ucc_geth_init(void)
3978 {
3979 int i, ret;
3980
3981 ret = uec_mdio_init();
3982
3983 if (ret)
3984 return ret;
3985
3986 printk(KERN_INFO "ucc_geth: " DRV_DESC "\n");
3987 for (i = 0; i < 8; i++)
3988 memcpy(&(ugeth_info[i]), &ugeth_primary_info,
3989 sizeof(ugeth_primary_info));
3990
3991 ret = of_register_platform_driver(&ucc_geth_driver);
3992
3993 if (ret)
3994 uec_mdio_exit();
3995
3996 return ret;
3997 }
3998
3999 static void __exit ucc_geth_exit(void)
4000 {
4001 of_unregister_platform_driver(&ucc_geth_driver);
4002 uec_mdio_exit();
4003 }
4004
4005 module_init(ucc_geth_init);
4006 module_exit(ucc_geth_exit);
4007
4008 MODULE_AUTHOR("Freescale Semiconductor, Inc");
4009 MODULE_DESCRIPTION(DRV_DESC);
4010 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
This page took 0.169753 seconds and 5 git commands to generate.