2 * Copyright (C) 2006-2007 Freescale Semicondutor, Inc. All rights reserved.
4 * Author: Shlomi Gridish <gridish@freescale.com>
5 * Li Yang <leoli@freescale.com>
8 * QE UCC Gigabit Ethernet Driver
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/errno.h>
18 #include <linux/slab.h>
19 #include <linux/stddef.h>
20 #include <linux/interrupt.h>
21 #include <linux/netdevice.h>
22 #include <linux/etherdevice.h>
23 #include <linux/skbuff.h>
24 #include <linux/spinlock.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/mii.h>
28 #include <linux/phy.h>
29 #include <linux/workqueue.h>
30 #include <linux/of_platform.h>
32 #include <asm/uaccess.h>
35 #include <asm/immap_qe.h>
38 #include <asm/ucc_fast.h>
41 #include "fsl_pq_mdio.h"
45 #define ugeth_printk(level, format, arg...) \
46 printk(level format "\n", ## arg)
48 #define ugeth_dbg(format, arg...) \
49 ugeth_printk(KERN_DEBUG , format , ## arg)
50 #define ugeth_err(format, arg...) \
51 ugeth_printk(KERN_ERR , format , ## arg)
52 #define ugeth_info(format, arg...) \
53 ugeth_printk(KERN_INFO , format , ## arg)
54 #define ugeth_warn(format, arg...) \
55 ugeth_printk(KERN_WARNING , format , ## arg)
57 #ifdef UGETH_VERBOSE_DEBUG
58 #define ugeth_vdbg ugeth_dbg
60 #define ugeth_vdbg(fmt, args...) do { } while (0)
61 #endif /* UGETH_VERBOSE_DEBUG */
62 #define UGETH_MSG_DEFAULT (NETIF_MSG_IFUP << 1 ) - 1
65 static DEFINE_SPINLOCK(ugeth_lock
);
71 module_param_named(debug
, debug
.msg_enable
, int, 0);
72 MODULE_PARM_DESC(debug
, "Debug verbosity level (0=none, ..., 0xffff=all)");
74 static struct ucc_geth_info ugeth_primary_info
= {
76 .bd_mem_part
= MEM_PART_SYSTEM
,
77 .rtsm
= UCC_FAST_SEND_IDLES_BETWEEN_FRAMES
,
78 .max_rx_buf_length
= 1536,
79 /* adjusted at startup if max-speed 1000 */
80 .urfs
= UCC_GETH_URFS_INIT
,
81 .urfet
= UCC_GETH_URFET_INIT
,
82 .urfset
= UCC_GETH_URFSET_INIT
,
83 .utfs
= UCC_GETH_UTFS_INIT
,
84 .utfet
= UCC_GETH_UTFET_INIT
,
85 .utftt
= UCC_GETH_UTFTT_INIT
,
87 .mode
= UCC_FAST_PROTOCOL_MODE_ETHERNET
,
88 .ttx_trx
= UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL
,
89 .tenc
= UCC_FAST_TX_ENCODING_NRZ
,
90 .renc
= UCC_FAST_RX_ENCODING_NRZ
,
91 .tcrc
= UCC_FAST_16_BIT_CRC
,
92 .synl
= UCC_FAST_SYNC_LEN_NOT_USED
,
96 .extendedFilteringChainPointer
= ((uint32_t) NULL
),
97 .typeorlen
= 3072 /*1536 */ ,
98 .nonBackToBackIfgPart1
= 0x40,
99 .nonBackToBackIfgPart2
= 0x60,
100 .miminumInterFrameGapEnforcement
= 0x50,
101 .backToBackInterFrameGap
= 0x60,
105 .strictpriorityq
= 0xff,
106 .altBebTruncation
= 0xa,
108 .maxRetransmission
= 0xf,
109 .collisionWindow
= 0x37,
110 .receiveFlowControl
= 1,
111 .transmitFlowControl
= 1,
112 .maxGroupAddrInHash
= 4,
113 .maxIndAddrInHash
= 4,
115 .maxFrameLength
= 1518,
116 .minFrameLength
= 64,
120 .ecamptr
= ((uint32_t) NULL
),
121 .eventRegMask
= UCCE_OTHER
,
122 .pausePeriod
= 0xf000,
123 .interruptcoalescingmaxvalue
= {1, 1, 1, 1, 1, 1, 1, 1},
144 .numStationAddresses
= UCC_GETH_NUM_OF_STATION_ADDRESSES_1
,
145 .largestexternallookupkeysize
=
146 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE
,
147 .statisticsMode
= UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE
|
148 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX
|
149 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX
,
150 .vlanOperationTagged
= UCC_GETH_VLAN_OPERATION_TAGGED_NOP
,
151 .vlanOperationNonTagged
= UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP
,
152 .rxQoSMode
= UCC_GETH_QOS_MODE_DEFAULT
,
153 .aufc
= UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE
,
154 .padAndCrc
= MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC
,
155 .numThreadsTx
= UCC_GETH_NUM_OF_THREADS_1
,
156 .numThreadsRx
= UCC_GETH_NUM_OF_THREADS_1
,
157 .riscTx
= QE_RISC_ALLOCATION_RISC1_AND_RISC2
,
158 .riscRx
= QE_RISC_ALLOCATION_RISC1_AND_RISC2
,
161 static struct ucc_geth_info ugeth_info
[8];
164 static void mem_disp(u8
*addr
, int size
)
167 int size16Aling
= (size
>> 4) << 4;
168 int size4Aling
= (size
>> 2) << 2;
173 for (i
= addr
; (u32
) i
< (u32
) addr
+ size16Aling
; i
+= 16)
174 printk("0x%08x: %08x %08x %08x %08x\r\n",
178 *((u32
*) (i
+ 8)), *((u32
*) (i
+ 12)));
180 printk("0x%08x: ", (u32
) i
);
181 for (; (u32
) i
< (u32
) addr
+ size4Aling
; i
+= 4)
182 printk("%08x ", *((u32
*) (i
)));
183 for (; (u32
) i
< (u32
) addr
+ size
; i
++)
184 printk("%02x", *((u8
*) (i
)));
190 static struct list_head
*dequeue(struct list_head
*lh
)
194 spin_lock_irqsave(&ugeth_lock
, flags
);
195 if (!list_empty(lh
)) {
196 struct list_head
*node
= lh
->next
;
198 spin_unlock_irqrestore(&ugeth_lock
, flags
);
201 spin_unlock_irqrestore(&ugeth_lock
, flags
);
206 static struct sk_buff
*get_new_skb(struct ucc_geth_private
*ugeth
,
209 struct sk_buff
*skb
= NULL
;
211 skb
= dev_alloc_skb(ugeth
->ug_info
->uf_info
.max_rx_buf_length
+
212 UCC_GETH_RX_DATA_BUF_ALIGNMENT
);
217 /* We need the data buffer to be aligned properly. We will reserve
218 * as many bytes as needed to align the data properly
221 UCC_GETH_RX_DATA_BUF_ALIGNMENT
-
222 (((unsigned)skb
->data
) & (UCC_GETH_RX_DATA_BUF_ALIGNMENT
-
225 skb
->dev
= ugeth
->ndev
;
227 out_be32(&((struct qe_bd __iomem
*)bd
)->buf
,
228 dma_map_single(ugeth
->dev
,
230 ugeth
->ug_info
->uf_info
.max_rx_buf_length
+
231 UCC_GETH_RX_DATA_BUF_ALIGNMENT
,
234 out_be32((u32 __iomem
*)bd
,
235 (R_E
| R_I
| (in_be32((u32 __iomem
*)bd
) & R_W
)));
240 static int rx_bd_buffer_set(struct ucc_geth_private
*ugeth
, u8 rxQ
)
247 bd
= ugeth
->p_rx_bd_ring
[rxQ
];
251 bd_status
= in_be32((u32 __iomem
*)bd
);
252 skb
= get_new_skb(ugeth
, bd
);
254 if (!skb
) /* If can not allocate data buffer,
255 abort. Cleanup will be elsewhere */
258 ugeth
->rx_skbuff
[rxQ
][i
] = skb
;
260 /* advance the BD pointer */
261 bd
+= sizeof(struct qe_bd
);
263 } while (!(bd_status
& R_W
));
268 static int fill_init_enet_entries(struct ucc_geth_private
*ugeth
,
272 u32 thread_alignment
,
274 int skip_page_for_first_entry
)
276 u32 init_enet_offset
;
280 for (i
= 0; i
< num_entries
; i
++) {
281 if ((snum
= qe_get_snum()) < 0) {
282 if (netif_msg_ifup(ugeth
))
283 ugeth_err("fill_init_enet_entries: Can not get SNUM.");
286 if ((i
== 0) && skip_page_for_first_entry
)
287 /* First entry of Rx does not have page */
288 init_enet_offset
= 0;
291 qe_muram_alloc(thread_size
, thread_alignment
);
292 if (IS_ERR_VALUE(init_enet_offset
)) {
293 if (netif_msg_ifup(ugeth
))
294 ugeth_err("fill_init_enet_entries: Can not allocate DPRAM memory.");
295 qe_put_snum((u8
) snum
);
300 ((u8
) snum
<< ENET_INIT_PARAM_SNUM_SHIFT
) | init_enet_offset
307 static int return_init_enet_entries(struct ucc_geth_private
*ugeth
,
311 int skip_page_for_first_entry
)
313 u32 init_enet_offset
;
317 for (i
= 0; i
< num_entries
; i
++) {
320 /* Check that this entry was actually valid --
321 needed in case failed in allocations */
322 if ((val
& ENET_INIT_PARAM_RISC_MASK
) == risc
) {
324 (u32
) (val
& ENET_INIT_PARAM_SNUM_MASK
) >>
325 ENET_INIT_PARAM_SNUM_SHIFT
;
326 qe_put_snum((u8
) snum
);
327 if (!((i
== 0) && skip_page_for_first_entry
)) {
328 /* First entry of Rx does not have page */
330 (val
& ENET_INIT_PARAM_PTR_MASK
);
331 qe_muram_free(init_enet_offset
);
341 static int dump_init_enet_entries(struct ucc_geth_private
*ugeth
,
342 u32 __iomem
*p_start
,
346 int skip_page_for_first_entry
)
348 u32 init_enet_offset
;
352 for (i
= 0; i
< num_entries
; i
++) {
353 u32 val
= in_be32(p_start
);
355 /* Check that this entry was actually valid --
356 needed in case failed in allocations */
357 if ((val
& ENET_INIT_PARAM_RISC_MASK
) == risc
) {
359 (u32
) (val
& ENET_INIT_PARAM_SNUM_MASK
) >>
360 ENET_INIT_PARAM_SNUM_SHIFT
;
361 qe_put_snum((u8
) snum
);
362 if (!((i
== 0) && skip_page_for_first_entry
)) {
363 /* First entry of Rx does not have page */
366 ENET_INIT_PARAM_PTR_MASK
);
367 ugeth_info("Init enet entry %d:", i
);
368 ugeth_info("Base address: 0x%08x",
370 qe_muram_addr(init_enet_offset
));
371 mem_disp(qe_muram_addr(init_enet_offset
),
382 static void put_enet_addr_container(struct enet_addr_container
*enet_addr_cont
)
384 kfree(enet_addr_cont
);
387 static void set_mac_addr(__be16 __iomem
*reg
, u8
*mac
)
389 out_be16(®
[0], ((u16
)mac
[5] << 8) | mac
[4]);
390 out_be16(®
[1], ((u16
)mac
[3] << 8) | mac
[2]);
391 out_be16(®
[2], ((u16
)mac
[1] << 8) | mac
[0]);
394 static int hw_clear_addr_in_paddr(struct ucc_geth_private
*ugeth
, u8 paddr_num
)
396 struct ucc_geth_82xx_address_filtering_pram __iomem
*p_82xx_addr_filt
;
398 if (!(paddr_num
< NUM_OF_PADDRS
)) {
399 ugeth_warn("%s: Illagel paddr_num.", __func__
);
404 (struct ucc_geth_82xx_address_filtering_pram __iomem
*) ugeth
->p_rx_glbl_pram
->
407 /* Writing address ff.ff.ff.ff.ff.ff disables address
408 recognition for this register */
409 out_be16(&p_82xx_addr_filt
->paddr
[paddr_num
].h
, 0xffff);
410 out_be16(&p_82xx_addr_filt
->paddr
[paddr_num
].m
, 0xffff);
411 out_be16(&p_82xx_addr_filt
->paddr
[paddr_num
].l
, 0xffff);
416 static void hw_add_addr_in_hash(struct ucc_geth_private
*ugeth
,
419 struct ucc_geth_82xx_address_filtering_pram __iomem
*p_82xx_addr_filt
;
423 (struct ucc_geth_82xx_address_filtering_pram __iomem
*) ugeth
->p_rx_glbl_pram
->
427 ucc_fast_get_qe_cr_subblock(ugeth
->ug_info
->uf_info
.ucc_num
);
429 /* Ethernet frames are defined in Little Endian mode,
430 therefor to insert */
431 /* the address to the hash (Big Endian mode), we reverse the bytes.*/
433 set_mac_addr(&p_82xx_addr_filt
->taddr
.h
, p_enet_addr
);
435 qe_issue_cmd(QE_SET_GROUP_ADDRESS
, cecr_subblock
,
436 QE_CR_PROTOCOL_ETHERNET
, 0);
439 #ifdef CONFIG_UGETH_MAGIC_PACKET
440 static void magic_packet_detection_enable(struct ucc_geth_private
*ugeth
)
442 struct ucc_fast_private
*uccf
;
443 struct ucc_geth __iomem
*ug_regs
;
446 ug_regs
= ugeth
->ug_regs
;
448 /* Enable interrupts for magic packet detection */
449 setbits32(uccf
->p_uccm
, UCC_GETH_UCCE_MPD
);
451 /* Enable magic packet detection */
452 setbits32(&ug_regs
->maccfg2
, MACCFG2_MPE
);
455 static void magic_packet_detection_disable(struct ucc_geth_private
*ugeth
)
457 struct ucc_fast_private
*uccf
;
458 struct ucc_geth __iomem
*ug_regs
;
461 ug_regs
= ugeth
->ug_regs
;
463 /* Disable interrupts for magic packet detection */
464 clrbits32(uccf
->p_uccm
, UCC_GETH_UCCE_MPD
);
466 /* Disable magic packet detection */
467 clrbits32(&ug_regs
->maccfg2
, MACCFG2_MPE
);
469 #endif /* MAGIC_PACKET */
471 static inline int compare_addr(u8
**addr1
, u8
**addr2
)
473 return memcmp(addr1
, addr2
, ENET_NUM_OCTETS_PER_ADDRESS
);
477 static void get_statistics(struct ucc_geth_private
*ugeth
,
478 struct ucc_geth_tx_firmware_statistics
*
479 tx_firmware_statistics
,
480 struct ucc_geth_rx_firmware_statistics
*
481 rx_firmware_statistics
,
482 struct ucc_geth_hardware_statistics
*hardware_statistics
)
484 struct ucc_fast __iomem
*uf_regs
;
485 struct ucc_geth __iomem
*ug_regs
;
486 struct ucc_geth_tx_firmware_statistics_pram
*p_tx_fw_statistics_pram
;
487 struct ucc_geth_rx_firmware_statistics_pram
*p_rx_fw_statistics_pram
;
489 ug_regs
= ugeth
->ug_regs
;
490 uf_regs
= (struct ucc_fast __iomem
*) ug_regs
;
491 p_tx_fw_statistics_pram
= ugeth
->p_tx_fw_statistics_pram
;
492 p_rx_fw_statistics_pram
= ugeth
->p_rx_fw_statistics_pram
;
494 /* Tx firmware only if user handed pointer and driver actually
495 gathers Tx firmware statistics */
496 if (tx_firmware_statistics
&& p_tx_fw_statistics_pram
) {
497 tx_firmware_statistics
->sicoltx
=
498 in_be32(&p_tx_fw_statistics_pram
->sicoltx
);
499 tx_firmware_statistics
->mulcoltx
=
500 in_be32(&p_tx_fw_statistics_pram
->mulcoltx
);
501 tx_firmware_statistics
->latecoltxfr
=
502 in_be32(&p_tx_fw_statistics_pram
->latecoltxfr
);
503 tx_firmware_statistics
->frabortduecol
=
504 in_be32(&p_tx_fw_statistics_pram
->frabortduecol
);
505 tx_firmware_statistics
->frlostinmactxer
=
506 in_be32(&p_tx_fw_statistics_pram
->frlostinmactxer
);
507 tx_firmware_statistics
->carriersenseertx
=
508 in_be32(&p_tx_fw_statistics_pram
->carriersenseertx
);
509 tx_firmware_statistics
->frtxok
=
510 in_be32(&p_tx_fw_statistics_pram
->frtxok
);
511 tx_firmware_statistics
->txfrexcessivedefer
=
512 in_be32(&p_tx_fw_statistics_pram
->txfrexcessivedefer
);
513 tx_firmware_statistics
->txpkts256
=
514 in_be32(&p_tx_fw_statistics_pram
->txpkts256
);
515 tx_firmware_statistics
->txpkts512
=
516 in_be32(&p_tx_fw_statistics_pram
->txpkts512
);
517 tx_firmware_statistics
->txpkts1024
=
518 in_be32(&p_tx_fw_statistics_pram
->txpkts1024
);
519 tx_firmware_statistics
->txpktsjumbo
=
520 in_be32(&p_tx_fw_statistics_pram
->txpktsjumbo
);
523 /* Rx firmware only if user handed pointer and driver actually
524 * gathers Rx firmware statistics */
525 if (rx_firmware_statistics
&& p_rx_fw_statistics_pram
) {
527 rx_firmware_statistics
->frrxfcser
=
528 in_be32(&p_rx_fw_statistics_pram
->frrxfcser
);
529 rx_firmware_statistics
->fraligner
=
530 in_be32(&p_rx_fw_statistics_pram
->fraligner
);
531 rx_firmware_statistics
->inrangelenrxer
=
532 in_be32(&p_rx_fw_statistics_pram
->inrangelenrxer
);
533 rx_firmware_statistics
->outrangelenrxer
=
534 in_be32(&p_rx_fw_statistics_pram
->outrangelenrxer
);
535 rx_firmware_statistics
->frtoolong
=
536 in_be32(&p_rx_fw_statistics_pram
->frtoolong
);
537 rx_firmware_statistics
->runt
=
538 in_be32(&p_rx_fw_statistics_pram
->runt
);
539 rx_firmware_statistics
->verylongevent
=
540 in_be32(&p_rx_fw_statistics_pram
->verylongevent
);
541 rx_firmware_statistics
->symbolerror
=
542 in_be32(&p_rx_fw_statistics_pram
->symbolerror
);
543 rx_firmware_statistics
->dropbsy
=
544 in_be32(&p_rx_fw_statistics_pram
->dropbsy
);
545 for (i
= 0; i
< 0x8; i
++)
546 rx_firmware_statistics
->res0
[i
] =
547 p_rx_fw_statistics_pram
->res0
[i
];
548 rx_firmware_statistics
->mismatchdrop
=
549 in_be32(&p_rx_fw_statistics_pram
->mismatchdrop
);
550 rx_firmware_statistics
->underpkts
=
551 in_be32(&p_rx_fw_statistics_pram
->underpkts
);
552 rx_firmware_statistics
->pkts256
=
553 in_be32(&p_rx_fw_statistics_pram
->pkts256
);
554 rx_firmware_statistics
->pkts512
=
555 in_be32(&p_rx_fw_statistics_pram
->pkts512
);
556 rx_firmware_statistics
->pkts1024
=
557 in_be32(&p_rx_fw_statistics_pram
->pkts1024
);
558 rx_firmware_statistics
->pktsjumbo
=
559 in_be32(&p_rx_fw_statistics_pram
->pktsjumbo
);
560 rx_firmware_statistics
->frlossinmacer
=
561 in_be32(&p_rx_fw_statistics_pram
->frlossinmacer
);
562 rx_firmware_statistics
->pausefr
=
563 in_be32(&p_rx_fw_statistics_pram
->pausefr
);
564 for (i
= 0; i
< 0x4; i
++)
565 rx_firmware_statistics
->res1
[i
] =
566 p_rx_fw_statistics_pram
->res1
[i
];
567 rx_firmware_statistics
->removevlan
=
568 in_be32(&p_rx_fw_statistics_pram
->removevlan
);
569 rx_firmware_statistics
->replacevlan
=
570 in_be32(&p_rx_fw_statistics_pram
->replacevlan
);
571 rx_firmware_statistics
->insertvlan
=
572 in_be32(&p_rx_fw_statistics_pram
->insertvlan
);
575 /* Hardware only if user handed pointer and driver actually
576 gathers hardware statistics */
577 if (hardware_statistics
&&
578 (in_be32(&uf_regs
->upsmr
) & UCC_GETH_UPSMR_HSE
)) {
579 hardware_statistics
->tx64
= in_be32(&ug_regs
->tx64
);
580 hardware_statistics
->tx127
= in_be32(&ug_regs
->tx127
);
581 hardware_statistics
->tx255
= in_be32(&ug_regs
->tx255
);
582 hardware_statistics
->rx64
= in_be32(&ug_regs
->rx64
);
583 hardware_statistics
->rx127
= in_be32(&ug_regs
->rx127
);
584 hardware_statistics
->rx255
= in_be32(&ug_regs
->rx255
);
585 hardware_statistics
->txok
= in_be32(&ug_regs
->txok
);
586 hardware_statistics
->txcf
= in_be16(&ug_regs
->txcf
);
587 hardware_statistics
->tmca
= in_be32(&ug_regs
->tmca
);
588 hardware_statistics
->tbca
= in_be32(&ug_regs
->tbca
);
589 hardware_statistics
->rxfok
= in_be32(&ug_regs
->rxfok
);
590 hardware_statistics
->rxbok
= in_be32(&ug_regs
->rxbok
);
591 hardware_statistics
->rbyt
= in_be32(&ug_regs
->rbyt
);
592 hardware_statistics
->rmca
= in_be32(&ug_regs
->rmca
);
593 hardware_statistics
->rbca
= in_be32(&ug_regs
->rbca
);
597 static void dump_bds(struct ucc_geth_private
*ugeth
)
602 for (i
= 0; i
< ugeth
->ug_info
->numQueuesTx
; i
++) {
603 if (ugeth
->p_tx_bd_ring
[i
]) {
605 (ugeth
->ug_info
->bdRingLenTx
[i
] *
606 sizeof(struct qe_bd
));
607 ugeth_info("TX BDs[%d]", i
);
608 mem_disp(ugeth
->p_tx_bd_ring
[i
], length
);
611 for (i
= 0; i
< ugeth
->ug_info
->numQueuesRx
; i
++) {
612 if (ugeth
->p_rx_bd_ring
[i
]) {
614 (ugeth
->ug_info
->bdRingLenRx
[i
] *
615 sizeof(struct qe_bd
));
616 ugeth_info("RX BDs[%d]", i
);
617 mem_disp(ugeth
->p_rx_bd_ring
[i
], length
);
622 static void dump_regs(struct ucc_geth_private
*ugeth
)
626 ugeth_info("UCC%d Geth registers:", ugeth
->ug_info
->uf_info
.ucc_num
);
627 ugeth_info("Base address: 0x%08x", (u32
) ugeth
->ug_regs
);
629 ugeth_info("maccfg1 : addr - 0x%08x, val - 0x%08x",
630 (u32
) & ugeth
->ug_regs
->maccfg1
,
631 in_be32(&ugeth
->ug_regs
->maccfg1
));
632 ugeth_info("maccfg2 : addr - 0x%08x, val - 0x%08x",
633 (u32
) & ugeth
->ug_regs
->maccfg2
,
634 in_be32(&ugeth
->ug_regs
->maccfg2
));
635 ugeth_info("ipgifg : addr - 0x%08x, val - 0x%08x",
636 (u32
) & ugeth
->ug_regs
->ipgifg
,
637 in_be32(&ugeth
->ug_regs
->ipgifg
));
638 ugeth_info("hafdup : addr - 0x%08x, val - 0x%08x",
639 (u32
) & ugeth
->ug_regs
->hafdup
,
640 in_be32(&ugeth
->ug_regs
->hafdup
));
641 ugeth_info("ifctl : addr - 0x%08x, val - 0x%08x",
642 (u32
) & ugeth
->ug_regs
->ifctl
,
643 in_be32(&ugeth
->ug_regs
->ifctl
));
644 ugeth_info("ifstat : addr - 0x%08x, val - 0x%08x",
645 (u32
) & ugeth
->ug_regs
->ifstat
,
646 in_be32(&ugeth
->ug_regs
->ifstat
));
647 ugeth_info("macstnaddr1: addr - 0x%08x, val - 0x%08x",
648 (u32
) & ugeth
->ug_regs
->macstnaddr1
,
649 in_be32(&ugeth
->ug_regs
->macstnaddr1
));
650 ugeth_info("macstnaddr2: addr - 0x%08x, val - 0x%08x",
651 (u32
) & ugeth
->ug_regs
->macstnaddr2
,
652 in_be32(&ugeth
->ug_regs
->macstnaddr2
));
653 ugeth_info("uempr : addr - 0x%08x, val - 0x%08x",
654 (u32
) & ugeth
->ug_regs
->uempr
,
655 in_be32(&ugeth
->ug_regs
->uempr
));
656 ugeth_info("utbipar : addr - 0x%08x, val - 0x%08x",
657 (u32
) & ugeth
->ug_regs
->utbipar
,
658 in_be32(&ugeth
->ug_regs
->utbipar
));
659 ugeth_info("uescr : addr - 0x%08x, val - 0x%04x",
660 (u32
) & ugeth
->ug_regs
->uescr
,
661 in_be16(&ugeth
->ug_regs
->uescr
));
662 ugeth_info("tx64 : addr - 0x%08x, val - 0x%08x",
663 (u32
) & ugeth
->ug_regs
->tx64
,
664 in_be32(&ugeth
->ug_regs
->tx64
));
665 ugeth_info("tx127 : addr - 0x%08x, val - 0x%08x",
666 (u32
) & ugeth
->ug_regs
->tx127
,
667 in_be32(&ugeth
->ug_regs
->tx127
));
668 ugeth_info("tx255 : addr - 0x%08x, val - 0x%08x",
669 (u32
) & ugeth
->ug_regs
->tx255
,
670 in_be32(&ugeth
->ug_regs
->tx255
));
671 ugeth_info("rx64 : addr - 0x%08x, val - 0x%08x",
672 (u32
) & ugeth
->ug_regs
->rx64
,
673 in_be32(&ugeth
->ug_regs
->rx64
));
674 ugeth_info("rx127 : addr - 0x%08x, val - 0x%08x",
675 (u32
) & ugeth
->ug_regs
->rx127
,
676 in_be32(&ugeth
->ug_regs
->rx127
));
677 ugeth_info("rx255 : addr - 0x%08x, val - 0x%08x",
678 (u32
) & ugeth
->ug_regs
->rx255
,
679 in_be32(&ugeth
->ug_regs
->rx255
));
680 ugeth_info("txok : addr - 0x%08x, val - 0x%08x",
681 (u32
) & ugeth
->ug_regs
->txok
,
682 in_be32(&ugeth
->ug_regs
->txok
));
683 ugeth_info("txcf : addr - 0x%08x, val - 0x%04x",
684 (u32
) & ugeth
->ug_regs
->txcf
,
685 in_be16(&ugeth
->ug_regs
->txcf
));
686 ugeth_info("tmca : addr - 0x%08x, val - 0x%08x",
687 (u32
) & ugeth
->ug_regs
->tmca
,
688 in_be32(&ugeth
->ug_regs
->tmca
));
689 ugeth_info("tbca : addr - 0x%08x, val - 0x%08x",
690 (u32
) & ugeth
->ug_regs
->tbca
,
691 in_be32(&ugeth
->ug_regs
->tbca
));
692 ugeth_info("rxfok : addr - 0x%08x, val - 0x%08x",
693 (u32
) & ugeth
->ug_regs
->rxfok
,
694 in_be32(&ugeth
->ug_regs
->rxfok
));
695 ugeth_info("rxbok : addr - 0x%08x, val - 0x%08x",
696 (u32
) & ugeth
->ug_regs
->rxbok
,
697 in_be32(&ugeth
->ug_regs
->rxbok
));
698 ugeth_info("rbyt : addr - 0x%08x, val - 0x%08x",
699 (u32
) & ugeth
->ug_regs
->rbyt
,
700 in_be32(&ugeth
->ug_regs
->rbyt
));
701 ugeth_info("rmca : addr - 0x%08x, val - 0x%08x",
702 (u32
) & ugeth
->ug_regs
->rmca
,
703 in_be32(&ugeth
->ug_regs
->rmca
));
704 ugeth_info("rbca : addr - 0x%08x, val - 0x%08x",
705 (u32
) & ugeth
->ug_regs
->rbca
,
706 in_be32(&ugeth
->ug_regs
->rbca
));
707 ugeth_info("scar : addr - 0x%08x, val - 0x%08x",
708 (u32
) & ugeth
->ug_regs
->scar
,
709 in_be32(&ugeth
->ug_regs
->scar
));
710 ugeth_info("scam : addr - 0x%08x, val - 0x%08x",
711 (u32
) & ugeth
->ug_regs
->scam
,
712 in_be32(&ugeth
->ug_regs
->scam
));
714 if (ugeth
->p_thread_data_tx
) {
715 int numThreadsTxNumerical
;
716 switch (ugeth
->ug_info
->numThreadsTx
) {
717 case UCC_GETH_NUM_OF_THREADS_1
:
718 numThreadsTxNumerical
= 1;
720 case UCC_GETH_NUM_OF_THREADS_2
:
721 numThreadsTxNumerical
= 2;
723 case UCC_GETH_NUM_OF_THREADS_4
:
724 numThreadsTxNumerical
= 4;
726 case UCC_GETH_NUM_OF_THREADS_6
:
727 numThreadsTxNumerical
= 6;
729 case UCC_GETH_NUM_OF_THREADS_8
:
730 numThreadsTxNumerical
= 8;
733 numThreadsTxNumerical
= 0;
737 ugeth_info("Thread data TXs:");
738 ugeth_info("Base address: 0x%08x",
739 (u32
) ugeth
->p_thread_data_tx
);
740 for (i
= 0; i
< numThreadsTxNumerical
; i
++) {
741 ugeth_info("Thread data TX[%d]:", i
);
742 ugeth_info("Base address: 0x%08x",
743 (u32
) & ugeth
->p_thread_data_tx
[i
]);
744 mem_disp((u8
*) & ugeth
->p_thread_data_tx
[i
],
745 sizeof(struct ucc_geth_thread_data_tx
));
748 if (ugeth
->p_thread_data_rx
) {
749 int numThreadsRxNumerical
;
750 switch (ugeth
->ug_info
->numThreadsRx
) {
751 case UCC_GETH_NUM_OF_THREADS_1
:
752 numThreadsRxNumerical
= 1;
754 case UCC_GETH_NUM_OF_THREADS_2
:
755 numThreadsRxNumerical
= 2;
757 case UCC_GETH_NUM_OF_THREADS_4
:
758 numThreadsRxNumerical
= 4;
760 case UCC_GETH_NUM_OF_THREADS_6
:
761 numThreadsRxNumerical
= 6;
763 case UCC_GETH_NUM_OF_THREADS_8
:
764 numThreadsRxNumerical
= 8;
767 numThreadsRxNumerical
= 0;
771 ugeth_info("Thread data RX:");
772 ugeth_info("Base address: 0x%08x",
773 (u32
) ugeth
->p_thread_data_rx
);
774 for (i
= 0; i
< numThreadsRxNumerical
; i
++) {
775 ugeth_info("Thread data RX[%d]:", i
);
776 ugeth_info("Base address: 0x%08x",
777 (u32
) & ugeth
->p_thread_data_rx
[i
]);
778 mem_disp((u8
*) & ugeth
->p_thread_data_rx
[i
],
779 sizeof(struct ucc_geth_thread_data_rx
));
782 if (ugeth
->p_exf_glbl_param
) {
783 ugeth_info("EXF global param:");
784 ugeth_info("Base address: 0x%08x",
785 (u32
) ugeth
->p_exf_glbl_param
);
786 mem_disp((u8
*) ugeth
->p_exf_glbl_param
,
787 sizeof(*ugeth
->p_exf_glbl_param
));
789 if (ugeth
->p_tx_glbl_pram
) {
790 ugeth_info("TX global param:");
791 ugeth_info("Base address: 0x%08x", (u32
) ugeth
->p_tx_glbl_pram
);
792 ugeth_info("temoder : addr - 0x%08x, val - 0x%04x",
793 (u32
) & ugeth
->p_tx_glbl_pram
->temoder
,
794 in_be16(&ugeth
->p_tx_glbl_pram
->temoder
));
795 ugeth_info("sqptr : addr - 0x%08x, val - 0x%08x",
796 (u32
) & ugeth
->p_tx_glbl_pram
->sqptr
,
797 in_be32(&ugeth
->p_tx_glbl_pram
->sqptr
));
798 ugeth_info("schedulerbasepointer: addr - 0x%08x, val - 0x%08x",
799 (u32
) & ugeth
->p_tx_glbl_pram
->schedulerbasepointer
,
800 in_be32(&ugeth
->p_tx_glbl_pram
->
801 schedulerbasepointer
));
802 ugeth_info("txrmonbaseptr: addr - 0x%08x, val - 0x%08x",
803 (u32
) & ugeth
->p_tx_glbl_pram
->txrmonbaseptr
,
804 in_be32(&ugeth
->p_tx_glbl_pram
->txrmonbaseptr
));
805 ugeth_info("tstate : addr - 0x%08x, val - 0x%08x",
806 (u32
) & ugeth
->p_tx_glbl_pram
->tstate
,
807 in_be32(&ugeth
->p_tx_glbl_pram
->tstate
));
808 ugeth_info("iphoffset[0] : addr - 0x%08x, val - 0x%02x",
809 (u32
) & ugeth
->p_tx_glbl_pram
->iphoffset
[0],
810 ugeth
->p_tx_glbl_pram
->iphoffset
[0]);
811 ugeth_info("iphoffset[1] : addr - 0x%08x, val - 0x%02x",
812 (u32
) & ugeth
->p_tx_glbl_pram
->iphoffset
[1],
813 ugeth
->p_tx_glbl_pram
->iphoffset
[1]);
814 ugeth_info("iphoffset[2] : addr - 0x%08x, val - 0x%02x",
815 (u32
) & ugeth
->p_tx_glbl_pram
->iphoffset
[2],
816 ugeth
->p_tx_glbl_pram
->iphoffset
[2]);
817 ugeth_info("iphoffset[3] : addr - 0x%08x, val - 0x%02x",
818 (u32
) & ugeth
->p_tx_glbl_pram
->iphoffset
[3],
819 ugeth
->p_tx_glbl_pram
->iphoffset
[3]);
820 ugeth_info("iphoffset[4] : addr - 0x%08x, val - 0x%02x",
821 (u32
) & ugeth
->p_tx_glbl_pram
->iphoffset
[4],
822 ugeth
->p_tx_glbl_pram
->iphoffset
[4]);
823 ugeth_info("iphoffset[5] : addr - 0x%08x, val - 0x%02x",
824 (u32
) & ugeth
->p_tx_glbl_pram
->iphoffset
[5],
825 ugeth
->p_tx_glbl_pram
->iphoffset
[5]);
826 ugeth_info("iphoffset[6] : addr - 0x%08x, val - 0x%02x",
827 (u32
) & ugeth
->p_tx_glbl_pram
->iphoffset
[6],
828 ugeth
->p_tx_glbl_pram
->iphoffset
[6]);
829 ugeth_info("iphoffset[7] : addr - 0x%08x, val - 0x%02x",
830 (u32
) & ugeth
->p_tx_glbl_pram
->iphoffset
[7],
831 ugeth
->p_tx_glbl_pram
->iphoffset
[7]);
832 ugeth_info("vtagtable[0] : addr - 0x%08x, val - 0x%08x",
833 (u32
) & ugeth
->p_tx_glbl_pram
->vtagtable
[0],
834 in_be32(&ugeth
->p_tx_glbl_pram
->vtagtable
[0]));
835 ugeth_info("vtagtable[1] : addr - 0x%08x, val - 0x%08x",
836 (u32
) & ugeth
->p_tx_glbl_pram
->vtagtable
[1],
837 in_be32(&ugeth
->p_tx_glbl_pram
->vtagtable
[1]));
838 ugeth_info("vtagtable[2] : addr - 0x%08x, val - 0x%08x",
839 (u32
) & ugeth
->p_tx_glbl_pram
->vtagtable
[2],
840 in_be32(&ugeth
->p_tx_glbl_pram
->vtagtable
[2]));
841 ugeth_info("vtagtable[3] : addr - 0x%08x, val - 0x%08x",
842 (u32
) & ugeth
->p_tx_glbl_pram
->vtagtable
[3],
843 in_be32(&ugeth
->p_tx_glbl_pram
->vtagtable
[3]));
844 ugeth_info("vtagtable[4] : addr - 0x%08x, val - 0x%08x",
845 (u32
) & ugeth
->p_tx_glbl_pram
->vtagtable
[4],
846 in_be32(&ugeth
->p_tx_glbl_pram
->vtagtable
[4]));
847 ugeth_info("vtagtable[5] : addr - 0x%08x, val - 0x%08x",
848 (u32
) & ugeth
->p_tx_glbl_pram
->vtagtable
[5],
849 in_be32(&ugeth
->p_tx_glbl_pram
->vtagtable
[5]));
850 ugeth_info("vtagtable[6] : addr - 0x%08x, val - 0x%08x",
851 (u32
) & ugeth
->p_tx_glbl_pram
->vtagtable
[6],
852 in_be32(&ugeth
->p_tx_glbl_pram
->vtagtable
[6]));
853 ugeth_info("vtagtable[7] : addr - 0x%08x, val - 0x%08x",
854 (u32
) & ugeth
->p_tx_glbl_pram
->vtagtable
[7],
855 in_be32(&ugeth
->p_tx_glbl_pram
->vtagtable
[7]));
856 ugeth_info("tqptr : addr - 0x%08x, val - 0x%08x",
857 (u32
) & ugeth
->p_tx_glbl_pram
->tqptr
,
858 in_be32(&ugeth
->p_tx_glbl_pram
->tqptr
));
860 if (ugeth
->p_rx_glbl_pram
) {
861 ugeth_info("RX global param:");
862 ugeth_info("Base address: 0x%08x", (u32
) ugeth
->p_rx_glbl_pram
);
863 ugeth_info("remoder : addr - 0x%08x, val - 0x%08x",
864 (u32
) & ugeth
->p_rx_glbl_pram
->remoder
,
865 in_be32(&ugeth
->p_rx_glbl_pram
->remoder
));
866 ugeth_info("rqptr : addr - 0x%08x, val - 0x%08x",
867 (u32
) & ugeth
->p_rx_glbl_pram
->rqptr
,
868 in_be32(&ugeth
->p_rx_glbl_pram
->rqptr
));
869 ugeth_info("typeorlen : addr - 0x%08x, val - 0x%04x",
870 (u32
) & ugeth
->p_rx_glbl_pram
->typeorlen
,
871 in_be16(&ugeth
->p_rx_glbl_pram
->typeorlen
));
872 ugeth_info("rxgstpack : addr - 0x%08x, val - 0x%02x",
873 (u32
) & ugeth
->p_rx_glbl_pram
->rxgstpack
,
874 ugeth
->p_rx_glbl_pram
->rxgstpack
);
875 ugeth_info("rxrmonbaseptr : addr - 0x%08x, val - 0x%08x",
876 (u32
) & ugeth
->p_rx_glbl_pram
->rxrmonbaseptr
,
877 in_be32(&ugeth
->p_rx_glbl_pram
->rxrmonbaseptr
));
878 ugeth_info("intcoalescingptr: addr - 0x%08x, val - 0x%08x",
879 (u32
) & ugeth
->p_rx_glbl_pram
->intcoalescingptr
,
880 in_be32(&ugeth
->p_rx_glbl_pram
->intcoalescingptr
));
881 ugeth_info("rstate : addr - 0x%08x, val - 0x%02x",
882 (u32
) & ugeth
->p_rx_glbl_pram
->rstate
,
883 ugeth
->p_rx_glbl_pram
->rstate
);
884 ugeth_info("mrblr : addr - 0x%08x, val - 0x%04x",
885 (u32
) & ugeth
->p_rx_glbl_pram
->mrblr
,
886 in_be16(&ugeth
->p_rx_glbl_pram
->mrblr
));
887 ugeth_info("rbdqptr : addr - 0x%08x, val - 0x%08x",
888 (u32
) & ugeth
->p_rx_glbl_pram
->rbdqptr
,
889 in_be32(&ugeth
->p_rx_glbl_pram
->rbdqptr
));
890 ugeth_info("mflr : addr - 0x%08x, val - 0x%04x",
891 (u32
) & ugeth
->p_rx_glbl_pram
->mflr
,
892 in_be16(&ugeth
->p_rx_glbl_pram
->mflr
));
893 ugeth_info("minflr : addr - 0x%08x, val - 0x%04x",
894 (u32
) & ugeth
->p_rx_glbl_pram
->minflr
,
895 in_be16(&ugeth
->p_rx_glbl_pram
->minflr
));
896 ugeth_info("maxd1 : addr - 0x%08x, val - 0x%04x",
897 (u32
) & ugeth
->p_rx_glbl_pram
->maxd1
,
898 in_be16(&ugeth
->p_rx_glbl_pram
->maxd1
));
899 ugeth_info("maxd2 : addr - 0x%08x, val - 0x%04x",
900 (u32
) & ugeth
->p_rx_glbl_pram
->maxd2
,
901 in_be16(&ugeth
->p_rx_glbl_pram
->maxd2
));
902 ugeth_info("ecamptr : addr - 0x%08x, val - 0x%08x",
903 (u32
) & ugeth
->p_rx_glbl_pram
->ecamptr
,
904 in_be32(&ugeth
->p_rx_glbl_pram
->ecamptr
));
905 ugeth_info("l2qt : addr - 0x%08x, val - 0x%08x",
906 (u32
) & ugeth
->p_rx_glbl_pram
->l2qt
,
907 in_be32(&ugeth
->p_rx_glbl_pram
->l2qt
));
908 ugeth_info("l3qt[0] : addr - 0x%08x, val - 0x%08x",
909 (u32
) & ugeth
->p_rx_glbl_pram
->l3qt
[0],
910 in_be32(&ugeth
->p_rx_glbl_pram
->l3qt
[0]));
911 ugeth_info("l3qt[1] : addr - 0x%08x, val - 0x%08x",
912 (u32
) & ugeth
->p_rx_glbl_pram
->l3qt
[1],
913 in_be32(&ugeth
->p_rx_glbl_pram
->l3qt
[1]));
914 ugeth_info("l3qt[2] : addr - 0x%08x, val - 0x%08x",
915 (u32
) & ugeth
->p_rx_glbl_pram
->l3qt
[2],
916 in_be32(&ugeth
->p_rx_glbl_pram
->l3qt
[2]));
917 ugeth_info("l3qt[3] : addr - 0x%08x, val - 0x%08x",
918 (u32
) & ugeth
->p_rx_glbl_pram
->l3qt
[3],
919 in_be32(&ugeth
->p_rx_glbl_pram
->l3qt
[3]));
920 ugeth_info("l3qt[4] : addr - 0x%08x, val - 0x%08x",
921 (u32
) & ugeth
->p_rx_glbl_pram
->l3qt
[4],
922 in_be32(&ugeth
->p_rx_glbl_pram
->l3qt
[4]));
923 ugeth_info("l3qt[5] : addr - 0x%08x, val - 0x%08x",
924 (u32
) & ugeth
->p_rx_glbl_pram
->l3qt
[5],
925 in_be32(&ugeth
->p_rx_glbl_pram
->l3qt
[5]));
926 ugeth_info("l3qt[6] : addr - 0x%08x, val - 0x%08x",
927 (u32
) & ugeth
->p_rx_glbl_pram
->l3qt
[6],
928 in_be32(&ugeth
->p_rx_glbl_pram
->l3qt
[6]));
929 ugeth_info("l3qt[7] : addr - 0x%08x, val - 0x%08x",
930 (u32
) & ugeth
->p_rx_glbl_pram
->l3qt
[7],
931 in_be32(&ugeth
->p_rx_glbl_pram
->l3qt
[7]));
932 ugeth_info("vlantype : addr - 0x%08x, val - 0x%04x",
933 (u32
) & ugeth
->p_rx_glbl_pram
->vlantype
,
934 in_be16(&ugeth
->p_rx_glbl_pram
->vlantype
));
935 ugeth_info("vlantci : addr - 0x%08x, val - 0x%04x",
936 (u32
) & ugeth
->p_rx_glbl_pram
->vlantci
,
937 in_be16(&ugeth
->p_rx_glbl_pram
->vlantci
));
938 for (i
= 0; i
< 64; i
++)
940 ("addressfiltering[%d]: addr - 0x%08x, val - 0x%02x",
942 (u32
) & ugeth
->p_rx_glbl_pram
->addressfiltering
[i
],
943 ugeth
->p_rx_glbl_pram
->addressfiltering
[i
]);
944 ugeth_info("exfGlobalParam : addr - 0x%08x, val - 0x%08x",
945 (u32
) & ugeth
->p_rx_glbl_pram
->exfGlobalParam
,
946 in_be32(&ugeth
->p_rx_glbl_pram
->exfGlobalParam
));
948 if (ugeth
->p_send_q_mem_reg
) {
949 ugeth_info("Send Q memory registers:");
950 ugeth_info("Base address: 0x%08x",
951 (u32
) ugeth
->p_send_q_mem_reg
);
952 for (i
= 0; i
< ugeth
->ug_info
->numQueuesTx
; i
++) {
953 ugeth_info("SQQD[%d]:", i
);
954 ugeth_info("Base address: 0x%08x",
955 (u32
) & ugeth
->p_send_q_mem_reg
->sqqd
[i
]);
956 mem_disp((u8
*) & ugeth
->p_send_q_mem_reg
->sqqd
[i
],
957 sizeof(struct ucc_geth_send_queue_qd
));
960 if (ugeth
->p_scheduler
) {
961 ugeth_info("Scheduler:");
962 ugeth_info("Base address: 0x%08x", (u32
) ugeth
->p_scheduler
);
963 mem_disp((u8
*) ugeth
->p_scheduler
,
964 sizeof(*ugeth
->p_scheduler
));
966 if (ugeth
->p_tx_fw_statistics_pram
) {
967 ugeth_info("TX FW statistics pram:");
968 ugeth_info("Base address: 0x%08x",
969 (u32
) ugeth
->p_tx_fw_statistics_pram
);
970 mem_disp((u8
*) ugeth
->p_tx_fw_statistics_pram
,
971 sizeof(*ugeth
->p_tx_fw_statistics_pram
));
973 if (ugeth
->p_rx_fw_statistics_pram
) {
974 ugeth_info("RX FW statistics pram:");
975 ugeth_info("Base address: 0x%08x",
976 (u32
) ugeth
->p_rx_fw_statistics_pram
);
977 mem_disp((u8
*) ugeth
->p_rx_fw_statistics_pram
,
978 sizeof(*ugeth
->p_rx_fw_statistics_pram
));
980 if (ugeth
->p_rx_irq_coalescing_tbl
) {
981 ugeth_info("RX IRQ coalescing tables:");
982 ugeth_info("Base address: 0x%08x",
983 (u32
) ugeth
->p_rx_irq_coalescing_tbl
);
984 for (i
= 0; i
< ugeth
->ug_info
->numQueuesRx
; i
++) {
985 ugeth_info("RX IRQ coalescing table entry[%d]:", i
);
986 ugeth_info("Base address: 0x%08x",
987 (u32
) & ugeth
->p_rx_irq_coalescing_tbl
->
990 ("interruptcoalescingmaxvalue: addr - 0x%08x, val - 0x%08x",
991 (u32
) & ugeth
->p_rx_irq_coalescing_tbl
->
992 coalescingentry
[i
].interruptcoalescingmaxvalue
,
993 in_be32(&ugeth
->p_rx_irq_coalescing_tbl
->
995 interruptcoalescingmaxvalue
));
997 ("interruptcoalescingcounter : addr - 0x%08x, val - 0x%08x",
998 (u32
) & ugeth
->p_rx_irq_coalescing_tbl
->
999 coalescingentry
[i
].interruptcoalescingcounter
,
1000 in_be32(&ugeth
->p_rx_irq_coalescing_tbl
->
1002 interruptcoalescingcounter
));
1005 if (ugeth
->p_rx_bd_qs_tbl
) {
1006 ugeth_info("RX BD QS tables:");
1007 ugeth_info("Base address: 0x%08x", (u32
) ugeth
->p_rx_bd_qs_tbl
);
1008 for (i
= 0; i
< ugeth
->ug_info
->numQueuesRx
; i
++) {
1009 ugeth_info("RX BD QS table[%d]:", i
);
1010 ugeth_info("Base address: 0x%08x",
1011 (u32
) & ugeth
->p_rx_bd_qs_tbl
[i
]);
1013 ("bdbaseptr : addr - 0x%08x, val - 0x%08x",
1014 (u32
) & ugeth
->p_rx_bd_qs_tbl
[i
].bdbaseptr
,
1015 in_be32(&ugeth
->p_rx_bd_qs_tbl
[i
].bdbaseptr
));
1017 ("bdptr : addr - 0x%08x, val - 0x%08x",
1018 (u32
) & ugeth
->p_rx_bd_qs_tbl
[i
].bdptr
,
1019 in_be32(&ugeth
->p_rx_bd_qs_tbl
[i
].bdptr
));
1021 ("externalbdbaseptr: addr - 0x%08x, val - 0x%08x",
1022 (u32
) & ugeth
->p_rx_bd_qs_tbl
[i
].externalbdbaseptr
,
1023 in_be32(&ugeth
->p_rx_bd_qs_tbl
[i
].
1024 externalbdbaseptr
));
1026 ("externalbdptr : addr - 0x%08x, val - 0x%08x",
1027 (u32
) & ugeth
->p_rx_bd_qs_tbl
[i
].externalbdptr
,
1028 in_be32(&ugeth
->p_rx_bd_qs_tbl
[i
].externalbdptr
));
1029 ugeth_info("ucode RX Prefetched BDs:");
1030 ugeth_info("Base address: 0x%08x",
1032 qe_muram_addr(in_be32
1033 (&ugeth
->p_rx_bd_qs_tbl
[i
].
1036 qe_muram_addr(in_be32
1037 (&ugeth
->p_rx_bd_qs_tbl
[i
].
1039 sizeof(struct ucc_geth_rx_prefetched_bds
));
1042 if (ugeth
->p_init_enet_param_shadow
) {
1044 ugeth_info("Init enet param shadow:");
1045 ugeth_info("Base address: 0x%08x",
1046 (u32
) ugeth
->p_init_enet_param_shadow
);
1047 mem_disp((u8
*) ugeth
->p_init_enet_param_shadow
,
1048 sizeof(*ugeth
->p_init_enet_param_shadow
));
1050 size
= sizeof(struct ucc_geth_thread_rx_pram
);
1051 if (ugeth
->ug_info
->rxExtendedFiltering
) {
1053 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING
;
1054 if (ugeth
->ug_info
->largestexternallookupkeysize
==
1055 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES
)
1057 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8
;
1058 if (ugeth
->ug_info
->largestexternallookupkeysize
==
1059 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES
)
1061 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16
;
1064 dump_init_enet_entries(ugeth
,
1065 &(ugeth
->p_init_enet_param_shadow
->
1067 ENET_INIT_PARAM_MAX_ENTRIES_TX
,
1068 sizeof(struct ucc_geth_thread_tx_pram
),
1069 ugeth
->ug_info
->riscTx
, 0);
1070 dump_init_enet_entries(ugeth
,
1071 &(ugeth
->p_init_enet_param_shadow
->
1073 ENET_INIT_PARAM_MAX_ENTRIES_RX
, size
,
1074 ugeth
->ug_info
->riscRx
, 1);
1079 static void init_default_reg_vals(u32 __iomem
*upsmr_register
,
1080 u32 __iomem
*maccfg1_register
,
1081 u32 __iomem
*maccfg2_register
)
1083 out_be32(upsmr_register
, UCC_GETH_UPSMR_INIT
);
1084 out_be32(maccfg1_register
, UCC_GETH_MACCFG1_INIT
);
1085 out_be32(maccfg2_register
, UCC_GETH_MACCFG2_INIT
);
1088 static int init_half_duplex_params(int alt_beb
,
1089 int back_pressure_no_backoff
,
1092 u8 alt_beb_truncation
,
1093 u8 max_retransmissions
,
1094 u8 collision_window
,
1095 u32 __iomem
*hafdup_register
)
1099 if ((alt_beb_truncation
> HALFDUP_ALT_BEB_TRUNCATION_MAX
) ||
1100 (max_retransmissions
> HALFDUP_MAX_RETRANSMISSION_MAX
) ||
1101 (collision_window
> HALFDUP_COLLISION_WINDOW_MAX
))
1104 value
= (u32
) (alt_beb_truncation
<< HALFDUP_ALT_BEB_TRUNCATION_SHIFT
);
1107 value
|= HALFDUP_ALT_BEB
;
1108 if (back_pressure_no_backoff
)
1109 value
|= HALFDUP_BACK_PRESSURE_NO_BACKOFF
;
1111 value
|= HALFDUP_NO_BACKOFF
;
1113 value
|= HALFDUP_EXCESSIVE_DEFER
;
1115 value
|= (max_retransmissions
<< HALFDUP_MAX_RETRANSMISSION_SHIFT
);
1117 value
|= collision_window
;
1119 out_be32(hafdup_register
, value
);
1123 static int init_inter_frame_gap_params(u8 non_btb_cs_ipg
,
1127 u32 __iomem
*ipgifg_register
)
1131 /* Non-Back-to-back IPG part 1 should be <= Non-Back-to-back
1133 if (non_btb_cs_ipg
> non_btb_ipg
)
1136 if ((non_btb_cs_ipg
> IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX
) ||
1137 (non_btb_ipg
> IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX
) ||
1138 /*(min_ifg > IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX) || */
1139 (btb_ipg
> IPGIFG_BACK_TO_BACK_IFG_MAX
))
1143 ((non_btb_cs_ipg
<< IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT
) &
1144 IPGIFG_NBTB_CS_IPG_MASK
);
1146 ((non_btb_ipg
<< IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT
) &
1147 IPGIFG_NBTB_IPG_MASK
);
1149 ((min_ifg
<< IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT
) &
1150 IPGIFG_MIN_IFG_MASK
);
1151 value
|= (btb_ipg
& IPGIFG_BTB_IPG_MASK
);
1153 out_be32(ipgifg_register
, value
);
1157 int init_flow_control_params(u32 automatic_flow_control_mode
,
1158 int rx_flow_control_enable
,
1159 int tx_flow_control_enable
,
1161 u16 extension_field
,
1162 u32 __iomem
*upsmr_register
,
1163 u32 __iomem
*uempr_register
,
1164 u32 __iomem
*maccfg1_register
)
1168 /* Set UEMPR register */
1169 value
= (u32
) pause_period
<< UEMPR_PAUSE_TIME_VALUE_SHIFT
;
1170 value
|= (u32
) extension_field
<< UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT
;
1171 out_be32(uempr_register
, value
);
1173 /* Set UPSMR register */
1174 setbits32(upsmr_register
, automatic_flow_control_mode
);
1176 value
= in_be32(maccfg1_register
);
1177 if (rx_flow_control_enable
)
1178 value
|= MACCFG1_FLOW_RX
;
1179 if (tx_flow_control_enable
)
1180 value
|= MACCFG1_FLOW_TX
;
1181 out_be32(maccfg1_register
, value
);
1186 static int init_hw_statistics_gathering_mode(int enable_hardware_statistics
,
1187 int auto_zero_hardware_statistics
,
1188 u32 __iomem
*upsmr_register
,
1189 u16 __iomem
*uescr_register
)
1191 u16 uescr_value
= 0;
1193 /* Enable hardware statistics gathering if requested */
1194 if (enable_hardware_statistics
)
1195 setbits32(upsmr_register
, UCC_GETH_UPSMR_HSE
);
1197 /* Clear hardware statistics counters */
1198 uescr_value
= in_be16(uescr_register
);
1199 uescr_value
|= UESCR_CLRCNT
;
1200 /* Automatically zero hardware statistics counters on read,
1202 if (auto_zero_hardware_statistics
)
1203 uescr_value
|= UESCR_AUTOZ
;
1204 out_be16(uescr_register
, uescr_value
);
1209 static int init_firmware_statistics_gathering_mode(int
1210 enable_tx_firmware_statistics
,
1211 int enable_rx_firmware_statistics
,
1212 u32 __iomem
*tx_rmon_base_ptr
,
1213 u32 tx_firmware_statistics_structure_address
,
1214 u32 __iomem
*rx_rmon_base_ptr
,
1215 u32 rx_firmware_statistics_structure_address
,
1216 u16 __iomem
*temoder_register
,
1217 u32 __iomem
*remoder_register
)
1219 /* Note: this function does not check if */
1220 /* the parameters it receives are NULL */
1222 if (enable_tx_firmware_statistics
) {
1223 out_be32(tx_rmon_base_ptr
,
1224 tx_firmware_statistics_structure_address
);
1225 setbits16(temoder_register
, TEMODER_TX_RMON_STATISTICS_ENABLE
);
1228 if (enable_rx_firmware_statistics
) {
1229 out_be32(rx_rmon_base_ptr
,
1230 rx_firmware_statistics_structure_address
);
1231 setbits32(remoder_register
, REMODER_RX_RMON_STATISTICS_ENABLE
);
1237 static int init_mac_station_addr_regs(u8 address_byte_0
,
1243 u32 __iomem
*macstnaddr1_register
,
1244 u32 __iomem
*macstnaddr2_register
)
1248 /* Example: for a station address of 0x12345678ABCD, */
1249 /* 0x12 is byte 0, 0x34 is byte 1 and so on and 0xCD is byte 5 */
1251 /* MACSTNADDR1 Register: */
1254 /* station address byte 5 station address byte 4 */
1256 /* station address byte 3 station address byte 2 */
1257 value
|= (u32
) ((address_byte_2
<< 0) & 0x000000FF);
1258 value
|= (u32
) ((address_byte_3
<< 8) & 0x0000FF00);
1259 value
|= (u32
) ((address_byte_4
<< 16) & 0x00FF0000);
1260 value
|= (u32
) ((address_byte_5
<< 24) & 0xFF000000);
1262 out_be32(macstnaddr1_register
, value
);
1264 /* MACSTNADDR2 Register: */
1267 /* station address byte 1 station address byte 0 */
1269 /* reserved reserved */
1271 value
|= (u32
) ((address_byte_0
<< 16) & 0x00FF0000);
1272 value
|= (u32
) ((address_byte_1
<< 24) & 0xFF000000);
1274 out_be32(macstnaddr2_register
, value
);
1279 static int init_check_frame_length_mode(int length_check
,
1280 u32 __iomem
*maccfg2_register
)
1284 value
= in_be32(maccfg2_register
);
1287 value
|= MACCFG2_LC
;
1289 value
&= ~MACCFG2_LC
;
1291 out_be32(maccfg2_register
, value
);
1295 static int init_preamble_length(u8 preamble_length
,
1296 u32 __iomem
*maccfg2_register
)
1298 if ((preamble_length
< 3) || (preamble_length
> 7))
1301 clrsetbits_be32(maccfg2_register
, MACCFG2_PREL_MASK
,
1302 preamble_length
<< MACCFG2_PREL_SHIFT
);
1307 static int init_rx_parameters(int reject_broadcast
,
1308 int receive_short_frames
,
1309 int promiscuous
, u32 __iomem
*upsmr_register
)
1313 value
= in_be32(upsmr_register
);
1315 if (reject_broadcast
)
1316 value
|= UCC_GETH_UPSMR_BRO
;
1318 value
&= ~UCC_GETH_UPSMR_BRO
;
1320 if (receive_short_frames
)
1321 value
|= UCC_GETH_UPSMR_RSH
;
1323 value
&= ~UCC_GETH_UPSMR_RSH
;
1326 value
|= UCC_GETH_UPSMR_PRO
;
1328 value
&= ~UCC_GETH_UPSMR_PRO
;
1330 out_be32(upsmr_register
, value
);
1335 static int init_max_rx_buff_len(u16 max_rx_buf_len
,
1336 u16 __iomem
*mrblr_register
)
1338 /* max_rx_buf_len value must be a multiple of 128 */
1339 if ((max_rx_buf_len
== 0)
1340 || (max_rx_buf_len
% UCC_GETH_MRBLR_ALIGNMENT
))
1343 out_be16(mrblr_register
, max_rx_buf_len
);
1347 static int init_min_frame_len(u16 min_frame_length
,
1348 u16 __iomem
*minflr_register
,
1349 u16 __iomem
*mrblr_register
)
1351 u16 mrblr_value
= 0;
1353 mrblr_value
= in_be16(mrblr_register
);
1354 if (min_frame_length
>= (mrblr_value
- 4))
1357 out_be16(minflr_register
, min_frame_length
);
1361 static int adjust_enet_interface(struct ucc_geth_private
*ugeth
)
1363 struct ucc_geth_info
*ug_info
;
1364 struct ucc_geth __iomem
*ug_regs
;
1365 struct ucc_fast __iomem
*uf_regs
;
1367 u32 upsmr
, maccfg2
, tbiBaseAddress
;
1370 ugeth_vdbg("%s: IN", __func__
);
1372 ug_info
= ugeth
->ug_info
;
1373 ug_regs
= ugeth
->ug_regs
;
1374 uf_regs
= ugeth
->uccf
->uf_regs
;
1377 maccfg2
= in_be32(&ug_regs
->maccfg2
);
1378 maccfg2
&= ~MACCFG2_INTERFACE_MODE_MASK
;
1379 if ((ugeth
->max_speed
== SPEED_10
) ||
1380 (ugeth
->max_speed
== SPEED_100
))
1381 maccfg2
|= MACCFG2_INTERFACE_MODE_NIBBLE
;
1382 else if (ugeth
->max_speed
== SPEED_1000
)
1383 maccfg2
|= MACCFG2_INTERFACE_MODE_BYTE
;
1384 maccfg2
|= ug_info
->padAndCrc
;
1385 out_be32(&ug_regs
->maccfg2
, maccfg2
);
1388 upsmr
= in_be32(&uf_regs
->upsmr
);
1389 upsmr
&= ~(UCC_GETH_UPSMR_RPM
| UCC_GETH_UPSMR_R10M
|
1390 UCC_GETH_UPSMR_TBIM
| UCC_GETH_UPSMR_RMM
);
1391 if ((ugeth
->phy_interface
== PHY_INTERFACE_MODE_RMII
) ||
1392 (ugeth
->phy_interface
== PHY_INTERFACE_MODE_RGMII
) ||
1393 (ugeth
->phy_interface
== PHY_INTERFACE_MODE_RGMII_ID
) ||
1394 (ugeth
->phy_interface
== PHY_INTERFACE_MODE_RGMII_RXID
) ||
1395 (ugeth
->phy_interface
== PHY_INTERFACE_MODE_RGMII_TXID
) ||
1396 (ugeth
->phy_interface
== PHY_INTERFACE_MODE_RTBI
)) {
1397 if (ugeth
->phy_interface
!= PHY_INTERFACE_MODE_RMII
)
1398 upsmr
|= UCC_GETH_UPSMR_RPM
;
1399 switch (ugeth
->max_speed
) {
1401 upsmr
|= UCC_GETH_UPSMR_R10M
;
1404 if (ugeth
->phy_interface
!= PHY_INTERFACE_MODE_RTBI
)
1405 upsmr
|= UCC_GETH_UPSMR_RMM
;
1408 if ((ugeth
->phy_interface
== PHY_INTERFACE_MODE_TBI
) ||
1409 (ugeth
->phy_interface
== PHY_INTERFACE_MODE_RTBI
)) {
1410 upsmr
|= UCC_GETH_UPSMR_TBIM
;
1412 out_be32(&uf_regs
->upsmr
, upsmr
);
1414 /* Disable autonegotiation in tbi mode, because by default it
1415 comes up in autonegotiation mode. */
1416 /* Note that this depends on proper setting in utbipar register. */
1417 if ((ugeth
->phy_interface
== PHY_INTERFACE_MODE_TBI
) ||
1418 (ugeth
->phy_interface
== PHY_INTERFACE_MODE_RTBI
)) {
1419 tbiBaseAddress
= in_be32(&ug_regs
->utbipar
);
1420 tbiBaseAddress
&= UTBIPAR_PHY_ADDRESS_MASK
;
1421 tbiBaseAddress
>>= UTBIPAR_PHY_ADDRESS_SHIFT
;
1422 value
= ugeth
->phydev
->bus
->read(ugeth
->phydev
->bus
,
1423 (u8
) tbiBaseAddress
, ENET_TBI_MII_CR
);
1424 value
&= ~0x1000; /* Turn off autonegotiation */
1425 ugeth
->phydev
->bus
->write(ugeth
->phydev
->bus
,
1426 (u8
) tbiBaseAddress
, ENET_TBI_MII_CR
, value
);
1429 init_check_frame_length_mode(ug_info
->lengthCheckRx
, &ug_regs
->maccfg2
);
1431 ret_val
= init_preamble_length(ug_info
->prel
, &ug_regs
->maccfg2
);
1433 if (netif_msg_probe(ugeth
))
1434 ugeth_err("%s: Preamble length must be between 3 and 7 inclusive.",
1442 /* Called every time the controller might need to be made
1443 * aware of new link state. The PHY code conveys this
1444 * information through variables in the ugeth structure, and this
1445 * function converts those variables into the appropriate
1446 * register values, and can bring down the device if needed.
1449 static void adjust_link(struct net_device
*dev
)
1451 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
1452 struct ucc_geth __iomem
*ug_regs
;
1453 struct ucc_fast __iomem
*uf_regs
;
1454 struct phy_device
*phydev
= ugeth
->phydev
;
1455 unsigned long flags
;
1458 ug_regs
= ugeth
->ug_regs
;
1459 uf_regs
= ugeth
->uccf
->uf_regs
;
1461 spin_lock_irqsave(&ugeth
->lock
, flags
);
1464 u32 tempval
= in_be32(&ug_regs
->maccfg2
);
1465 u32 upsmr
= in_be32(&uf_regs
->upsmr
);
1466 /* Now we make sure that we can be in full duplex mode.
1467 * If not, we operate in half-duplex mode. */
1468 if (phydev
->duplex
!= ugeth
->oldduplex
) {
1470 if (!(phydev
->duplex
))
1471 tempval
&= ~(MACCFG2_FDX
);
1473 tempval
|= MACCFG2_FDX
;
1474 ugeth
->oldduplex
= phydev
->duplex
;
1477 if (phydev
->speed
!= ugeth
->oldspeed
) {
1479 switch (phydev
->speed
) {
1481 tempval
= ((tempval
&
1482 ~(MACCFG2_INTERFACE_MODE_MASK
)) |
1483 MACCFG2_INTERFACE_MODE_BYTE
);
1487 tempval
= ((tempval
&
1488 ~(MACCFG2_INTERFACE_MODE_MASK
)) |
1489 MACCFG2_INTERFACE_MODE_NIBBLE
);
1490 /* if reduced mode, re-set UPSMR.R10M */
1491 if ((ugeth
->phy_interface
== PHY_INTERFACE_MODE_RMII
) ||
1492 (ugeth
->phy_interface
== PHY_INTERFACE_MODE_RGMII
) ||
1493 (ugeth
->phy_interface
== PHY_INTERFACE_MODE_RGMII_ID
) ||
1494 (ugeth
->phy_interface
== PHY_INTERFACE_MODE_RGMII_RXID
) ||
1495 (ugeth
->phy_interface
== PHY_INTERFACE_MODE_RGMII_TXID
) ||
1496 (ugeth
->phy_interface
== PHY_INTERFACE_MODE_RTBI
)) {
1497 if (phydev
->speed
== SPEED_10
)
1498 upsmr
|= UCC_GETH_UPSMR_R10M
;
1500 upsmr
&= ~UCC_GETH_UPSMR_R10M
;
1504 if (netif_msg_link(ugeth
))
1506 "%s: Ack! Speed (%d) is not 10/100/1000!",
1507 dev
->name
, phydev
->speed
);
1510 ugeth
->oldspeed
= phydev
->speed
;
1513 out_be32(&ug_regs
->maccfg2
, tempval
);
1514 out_be32(&uf_regs
->upsmr
, upsmr
);
1516 if (!ugeth
->oldlink
) {
1520 } else if (ugeth
->oldlink
) {
1523 ugeth
->oldspeed
= 0;
1524 ugeth
->oldduplex
= -1;
1527 if (new_state
&& netif_msg_link(ugeth
))
1528 phy_print_status(phydev
);
1530 spin_unlock_irqrestore(&ugeth
->lock
, flags
);
1533 /* Configure the PHY for dev.
1534 * returns 0 if success. -1 if failure
1536 static int init_phy(struct net_device
*dev
)
1538 struct ucc_geth_private
*priv
= netdev_priv(dev
);
1539 struct ucc_geth_info
*ug_info
= priv
->ug_info
;
1540 struct phy_device
*phydev
;
1544 priv
->oldduplex
= -1;
1546 phydev
= phy_connect(dev
, ug_info
->phy_bus_id
, &adjust_link
, 0,
1547 priv
->phy_interface
);
1549 if (IS_ERR(phydev
)) {
1550 printk("%s: Could not attach to PHY\n", dev
->name
);
1551 return PTR_ERR(phydev
);
1554 phydev
->supported
&= (ADVERTISED_10baseT_Half
|
1555 ADVERTISED_10baseT_Full
|
1556 ADVERTISED_100baseT_Half
|
1557 ADVERTISED_100baseT_Full
);
1559 if (priv
->max_speed
== SPEED_1000
)
1560 phydev
->supported
|= ADVERTISED_1000baseT_Full
;
1562 phydev
->advertising
= phydev
->supported
;
1564 priv
->phydev
= phydev
;
1571 static int ugeth_graceful_stop_tx(struct ucc_geth_private
*ugeth
)
1573 struct ucc_fast_private
*uccf
;
1580 /* Mask GRACEFUL STOP TX interrupt bit and clear it */
1581 clrbits32(uccf
->p_uccm
, UCC_GETH_UCCE_GRA
);
1582 out_be32(uccf
->p_ucce
, UCC_GETH_UCCE_GRA
); /* clear by writing 1 */
1584 /* Issue host command */
1586 ucc_fast_get_qe_cr_subblock(ugeth
->ug_info
->uf_info
.ucc_num
);
1587 qe_issue_cmd(QE_GRACEFUL_STOP_TX
, cecr_subblock
,
1588 QE_CR_PROTOCOL_ETHERNET
, 0);
1590 /* Wait for command to complete */
1593 temp
= in_be32(uccf
->p_ucce
);
1594 } while (!(temp
& UCC_GETH_UCCE_GRA
) && --i
);
1596 uccf
->stopped_tx
= 1;
1601 static int ugeth_graceful_stop_rx(struct ucc_geth_private
* ugeth
)
1603 struct ucc_fast_private
*uccf
;
1610 /* Clear acknowledge bit */
1611 temp
= in_8(&ugeth
->p_rx_glbl_pram
->rxgstpack
);
1612 temp
&= ~GRACEFUL_STOP_ACKNOWLEDGE_RX
;
1613 out_8(&ugeth
->p_rx_glbl_pram
->rxgstpack
, temp
);
1615 /* Keep issuing command and checking acknowledge bit until
1616 it is asserted, according to spec */
1618 /* Issue host command */
1620 ucc_fast_get_qe_cr_subblock(ugeth
->ug_info
->uf_info
.
1622 qe_issue_cmd(QE_GRACEFUL_STOP_RX
, cecr_subblock
,
1623 QE_CR_PROTOCOL_ETHERNET
, 0);
1625 temp
= in_8(&ugeth
->p_rx_glbl_pram
->rxgstpack
);
1626 } while (!(temp
& GRACEFUL_STOP_ACKNOWLEDGE_RX
) && --i
);
1628 uccf
->stopped_rx
= 1;
1633 static int ugeth_restart_tx(struct ucc_geth_private
*ugeth
)
1635 struct ucc_fast_private
*uccf
;
1641 ucc_fast_get_qe_cr_subblock(ugeth
->ug_info
->uf_info
.ucc_num
);
1642 qe_issue_cmd(QE_RESTART_TX
, cecr_subblock
, QE_CR_PROTOCOL_ETHERNET
, 0);
1643 uccf
->stopped_tx
= 0;
1648 static int ugeth_restart_rx(struct ucc_geth_private
*ugeth
)
1650 struct ucc_fast_private
*uccf
;
1656 ucc_fast_get_qe_cr_subblock(ugeth
->ug_info
->uf_info
.ucc_num
);
1657 qe_issue_cmd(QE_RESTART_RX
, cecr_subblock
, QE_CR_PROTOCOL_ETHERNET
,
1659 uccf
->stopped_rx
= 0;
1664 static int ugeth_enable(struct ucc_geth_private
*ugeth
, enum comm_dir mode
)
1666 struct ucc_fast_private
*uccf
;
1667 int enabled_tx
, enabled_rx
;
1671 /* check if the UCC number is in range. */
1672 if (ugeth
->ug_info
->uf_info
.ucc_num
>= UCC_MAX_NUM
) {
1673 if (netif_msg_probe(ugeth
))
1674 ugeth_err("%s: ucc_num out of range.", __func__
);
1678 enabled_tx
= uccf
->enabled_tx
;
1679 enabled_rx
= uccf
->enabled_rx
;
1681 /* Get Tx and Rx going again, in case this channel was actively
1683 if ((mode
& COMM_DIR_TX
) && (!enabled_tx
) && uccf
->stopped_tx
)
1684 ugeth_restart_tx(ugeth
);
1685 if ((mode
& COMM_DIR_RX
) && (!enabled_rx
) && uccf
->stopped_rx
)
1686 ugeth_restart_rx(ugeth
);
1688 ucc_fast_enable(uccf
, mode
); /* OK to do even if not disabled */
1694 static int ugeth_disable(struct ucc_geth_private
* ugeth
, enum comm_dir mode
)
1696 struct ucc_fast_private
*uccf
;
1700 /* check if the UCC number is in range. */
1701 if (ugeth
->ug_info
->uf_info
.ucc_num
>= UCC_MAX_NUM
) {
1702 if (netif_msg_probe(ugeth
))
1703 ugeth_err("%s: ucc_num out of range.", __func__
);
1707 /* Stop any transmissions */
1708 if ((mode
& COMM_DIR_TX
) && uccf
->enabled_tx
&& !uccf
->stopped_tx
)
1709 ugeth_graceful_stop_tx(ugeth
);
1711 /* Stop any receptions */
1712 if ((mode
& COMM_DIR_RX
) && uccf
->enabled_rx
&& !uccf
->stopped_rx
)
1713 ugeth_graceful_stop_rx(ugeth
);
1715 ucc_fast_disable(ugeth
->uccf
, mode
); /* OK to do even if not enabled */
1720 static void ugeth_dump_regs(struct ucc_geth_private
*ugeth
)
1723 ucc_fast_dump_regs(ugeth
->uccf
);
1729 static int ugeth_82xx_filtering_clear_all_addr_in_hash(struct ucc_geth_private
*
1734 struct ucc_geth_82xx_address_filtering_pram __iomem
*p_82xx_addr_filt
;
1735 struct ucc_fast_private
*uccf
;
1736 enum comm_dir comm_dir
;
1737 struct list_head
*p_lh
;
1739 u32 __iomem
*addr_h
;
1740 u32 __iomem
*addr_l
;
1746 (struct ucc_geth_82xx_address_filtering_pram __iomem
*)
1747 ugeth
->p_rx_glbl_pram
->addressfiltering
;
1749 if (enet_addr_type
== ENET_ADDR_TYPE_GROUP
) {
1750 addr_h
= &(p_82xx_addr_filt
->gaddr_h
);
1751 addr_l
= &(p_82xx_addr_filt
->gaddr_l
);
1752 p_lh
= &ugeth
->group_hash_q
;
1753 p_counter
= &(ugeth
->numGroupAddrInHash
);
1754 } else if (enet_addr_type
== ENET_ADDR_TYPE_INDIVIDUAL
) {
1755 addr_h
= &(p_82xx_addr_filt
->iaddr_h
);
1756 addr_l
= &(p_82xx_addr_filt
->iaddr_l
);
1757 p_lh
= &ugeth
->ind_hash_q
;
1758 p_counter
= &(ugeth
->numIndAddrInHash
);
1763 if (uccf
->enabled_tx
)
1764 comm_dir
|= COMM_DIR_TX
;
1765 if (uccf
->enabled_rx
)
1766 comm_dir
|= COMM_DIR_RX
;
1768 ugeth_disable(ugeth
, comm_dir
);
1770 /* Clear the hash table. */
1771 out_be32(addr_h
, 0x00000000);
1772 out_be32(addr_l
, 0x00000000);
1779 /* Delete all remaining CQ elements */
1780 for (i
= 0; i
< num
; i
++)
1781 put_enet_addr_container(ENET_ADDR_CONT_ENTRY(dequeue(p_lh
)));
1786 ugeth_enable(ugeth
, comm_dir
);
1791 static int ugeth_82xx_filtering_clear_addr_in_paddr(struct ucc_geth_private
*ugeth
,
1794 ugeth
->indAddrRegUsed
[paddr_num
] = 0; /* mark this paddr as not used */
1795 return hw_clear_addr_in_paddr(ugeth
, paddr_num
);/* clear in hardware */
1798 static void ucc_geth_memclean(struct ucc_geth_private
*ugeth
)
1807 ucc_fast_free(ugeth
->uccf
);
1811 if (ugeth
->p_thread_data_tx
) {
1812 qe_muram_free(ugeth
->thread_dat_tx_offset
);
1813 ugeth
->p_thread_data_tx
= NULL
;
1815 if (ugeth
->p_thread_data_rx
) {
1816 qe_muram_free(ugeth
->thread_dat_rx_offset
);
1817 ugeth
->p_thread_data_rx
= NULL
;
1819 if (ugeth
->p_exf_glbl_param
) {
1820 qe_muram_free(ugeth
->exf_glbl_param_offset
);
1821 ugeth
->p_exf_glbl_param
= NULL
;
1823 if (ugeth
->p_rx_glbl_pram
) {
1824 qe_muram_free(ugeth
->rx_glbl_pram_offset
);
1825 ugeth
->p_rx_glbl_pram
= NULL
;
1827 if (ugeth
->p_tx_glbl_pram
) {
1828 qe_muram_free(ugeth
->tx_glbl_pram_offset
);
1829 ugeth
->p_tx_glbl_pram
= NULL
;
1831 if (ugeth
->p_send_q_mem_reg
) {
1832 qe_muram_free(ugeth
->send_q_mem_reg_offset
);
1833 ugeth
->p_send_q_mem_reg
= NULL
;
1835 if (ugeth
->p_scheduler
) {
1836 qe_muram_free(ugeth
->scheduler_offset
);
1837 ugeth
->p_scheduler
= NULL
;
1839 if (ugeth
->p_tx_fw_statistics_pram
) {
1840 qe_muram_free(ugeth
->tx_fw_statistics_pram_offset
);
1841 ugeth
->p_tx_fw_statistics_pram
= NULL
;
1843 if (ugeth
->p_rx_fw_statistics_pram
) {
1844 qe_muram_free(ugeth
->rx_fw_statistics_pram_offset
);
1845 ugeth
->p_rx_fw_statistics_pram
= NULL
;
1847 if (ugeth
->p_rx_irq_coalescing_tbl
) {
1848 qe_muram_free(ugeth
->rx_irq_coalescing_tbl_offset
);
1849 ugeth
->p_rx_irq_coalescing_tbl
= NULL
;
1851 if (ugeth
->p_rx_bd_qs_tbl
) {
1852 qe_muram_free(ugeth
->rx_bd_qs_tbl_offset
);
1853 ugeth
->p_rx_bd_qs_tbl
= NULL
;
1855 if (ugeth
->p_init_enet_param_shadow
) {
1856 return_init_enet_entries(ugeth
,
1857 &(ugeth
->p_init_enet_param_shadow
->
1859 ENET_INIT_PARAM_MAX_ENTRIES_RX
,
1860 ugeth
->ug_info
->riscRx
, 1);
1861 return_init_enet_entries(ugeth
,
1862 &(ugeth
->p_init_enet_param_shadow
->
1864 ENET_INIT_PARAM_MAX_ENTRIES_TX
,
1865 ugeth
->ug_info
->riscTx
, 0);
1866 kfree(ugeth
->p_init_enet_param_shadow
);
1867 ugeth
->p_init_enet_param_shadow
= NULL
;
1869 for (i
= 0; i
< ugeth
->ug_info
->numQueuesTx
; i
++) {
1870 bd
= ugeth
->p_tx_bd_ring
[i
];
1873 for (j
= 0; j
< ugeth
->ug_info
->bdRingLenTx
[i
]; j
++) {
1874 if (ugeth
->tx_skbuff
[i
][j
]) {
1875 dma_unmap_single(ugeth
->dev
,
1876 in_be32(&((struct qe_bd __iomem
*)bd
)->buf
),
1877 (in_be32((u32 __iomem
*)bd
) &
1880 dev_kfree_skb_any(ugeth
->tx_skbuff
[i
][j
]);
1881 ugeth
->tx_skbuff
[i
][j
] = NULL
;
1885 kfree(ugeth
->tx_skbuff
[i
]);
1887 if (ugeth
->p_tx_bd_ring
[i
]) {
1888 if (ugeth
->ug_info
->uf_info
.bd_mem_part
==
1890 kfree((void *)ugeth
->tx_bd_ring_offset
[i
]);
1891 else if (ugeth
->ug_info
->uf_info
.bd_mem_part
==
1893 qe_muram_free(ugeth
->tx_bd_ring_offset
[i
]);
1894 ugeth
->p_tx_bd_ring
[i
] = NULL
;
1897 for (i
= 0; i
< ugeth
->ug_info
->numQueuesRx
; i
++) {
1898 if (ugeth
->p_rx_bd_ring
[i
]) {
1899 /* Return existing data buffers in ring */
1900 bd
= ugeth
->p_rx_bd_ring
[i
];
1901 for (j
= 0; j
< ugeth
->ug_info
->bdRingLenRx
[i
]; j
++) {
1902 if (ugeth
->rx_skbuff
[i
][j
]) {
1903 dma_unmap_single(ugeth
->dev
,
1904 in_be32(&((struct qe_bd __iomem
*)bd
)->buf
),
1906 uf_info
.max_rx_buf_length
+
1907 UCC_GETH_RX_DATA_BUF_ALIGNMENT
,
1910 ugeth
->rx_skbuff
[i
][j
]);
1911 ugeth
->rx_skbuff
[i
][j
] = NULL
;
1913 bd
+= sizeof(struct qe_bd
);
1916 kfree(ugeth
->rx_skbuff
[i
]);
1918 if (ugeth
->ug_info
->uf_info
.bd_mem_part
==
1920 kfree((void *)ugeth
->rx_bd_ring_offset
[i
]);
1921 else if (ugeth
->ug_info
->uf_info
.bd_mem_part
==
1923 qe_muram_free(ugeth
->rx_bd_ring_offset
[i
]);
1924 ugeth
->p_rx_bd_ring
[i
] = NULL
;
1927 while (!list_empty(&ugeth
->group_hash_q
))
1928 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
1929 (dequeue(&ugeth
->group_hash_q
)));
1930 while (!list_empty(&ugeth
->ind_hash_q
))
1931 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
1932 (dequeue(&ugeth
->ind_hash_q
)));
1933 if (ugeth
->ug_regs
) {
1934 iounmap(ugeth
->ug_regs
);
1935 ugeth
->ug_regs
= NULL
;
1939 static void ucc_geth_set_multi(struct net_device
*dev
)
1941 struct ucc_geth_private
*ugeth
;
1942 struct dev_mc_list
*dmi
;
1943 struct ucc_fast __iomem
*uf_regs
;
1944 struct ucc_geth_82xx_address_filtering_pram __iomem
*p_82xx_addr_filt
;
1947 ugeth
= netdev_priv(dev
);
1949 uf_regs
= ugeth
->uccf
->uf_regs
;
1951 if (dev
->flags
& IFF_PROMISC
) {
1952 setbits32(&uf_regs
->upsmr
, UCC_GETH_UPSMR_PRO
);
1954 clrbits32(&uf_regs
->upsmr
, UCC_GETH_UPSMR_PRO
);
1957 (struct ucc_geth_82xx_address_filtering_pram __iomem
*) ugeth
->
1958 p_rx_glbl_pram
->addressfiltering
;
1960 if (dev
->flags
& IFF_ALLMULTI
) {
1961 /* Catch all multicast addresses, so set the
1962 * filter to all 1's.
1964 out_be32(&p_82xx_addr_filt
->gaddr_h
, 0xffffffff);
1965 out_be32(&p_82xx_addr_filt
->gaddr_l
, 0xffffffff);
1967 /* Clear filter and add the addresses in the list.
1969 out_be32(&p_82xx_addr_filt
->gaddr_h
, 0x0);
1970 out_be32(&p_82xx_addr_filt
->gaddr_l
, 0x0);
1974 for (i
= 0; i
< dev
->mc_count
; i
++, dmi
= dmi
->next
) {
1976 /* Only support group multicast for now.
1978 if (!(dmi
->dmi_addr
[0] & 1))
1981 /* Ask CPM to run CRC and set bit in
1984 hw_add_addr_in_hash(ugeth
, dmi
->dmi_addr
);
1990 static void ucc_geth_stop(struct ucc_geth_private
*ugeth
)
1992 struct ucc_geth __iomem
*ug_regs
= ugeth
->ug_regs
;
1993 struct phy_device
*phydev
= ugeth
->phydev
;
1995 ugeth_vdbg("%s: IN", __func__
);
1997 /* Disable the controller */
1998 ugeth_disable(ugeth
, COMM_DIR_RX_AND_TX
);
2000 /* Tell the kernel the link is down */
2003 /* Mask all interrupts */
2004 out_be32(ugeth
->uccf
->p_uccm
, 0x00000000);
2006 /* Clear all interrupts */
2007 out_be32(ugeth
->uccf
->p_ucce
, 0xffffffff);
2009 /* Disable Rx and Tx */
2010 clrbits32(&ug_regs
->maccfg1
, MACCFG1_ENABLE_RX
| MACCFG1_ENABLE_TX
);
2012 phy_disconnect(ugeth
->phydev
);
2013 ugeth
->phydev
= NULL
;
2015 ucc_geth_memclean(ugeth
);
2018 static int ucc_struct_init(struct ucc_geth_private
*ugeth
)
2020 struct ucc_geth_info
*ug_info
;
2021 struct ucc_fast_info
*uf_info
;
2024 ug_info
= ugeth
->ug_info
;
2025 uf_info
= &ug_info
->uf_info
;
2027 if (!((uf_info
->bd_mem_part
== MEM_PART_SYSTEM
) ||
2028 (uf_info
->bd_mem_part
== MEM_PART_MURAM
))) {
2029 if (netif_msg_probe(ugeth
))
2030 ugeth_err("%s: Bad memory partition value.",
2036 for (i
= 0; i
< ug_info
->numQueuesRx
; i
++) {
2037 if ((ug_info
->bdRingLenRx
[i
] < UCC_GETH_RX_BD_RING_SIZE_MIN
) ||
2038 (ug_info
->bdRingLenRx
[i
] %
2039 UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT
)) {
2040 if (netif_msg_probe(ugeth
))
2042 ("%s: Rx BD ring length must be multiple of 4, no smaller than 8.",
2049 for (i
= 0; i
< ug_info
->numQueuesTx
; i
++) {
2050 if (ug_info
->bdRingLenTx
[i
] < UCC_GETH_TX_BD_RING_SIZE_MIN
) {
2051 if (netif_msg_probe(ugeth
))
2053 ("%s: Tx BD ring length must be no smaller than 2.",
2060 if ((uf_info
->max_rx_buf_length
== 0) ||
2061 (uf_info
->max_rx_buf_length
% UCC_GETH_MRBLR_ALIGNMENT
)) {
2062 if (netif_msg_probe(ugeth
))
2064 ("%s: max_rx_buf_length must be non-zero multiple of 128.",
2070 if (ug_info
->numQueuesTx
> NUM_TX_QUEUES
) {
2071 if (netif_msg_probe(ugeth
))
2072 ugeth_err("%s: number of tx queues too large.", __func__
);
2077 if (ug_info
->numQueuesRx
> NUM_RX_QUEUES
) {
2078 if (netif_msg_probe(ugeth
))
2079 ugeth_err("%s: number of rx queues too large.", __func__
);
2084 for (i
= 0; i
< UCC_GETH_VLAN_PRIORITY_MAX
; i
++) {
2085 if (ug_info
->l2qt
[i
] >= ug_info
->numQueuesRx
) {
2086 if (netif_msg_probe(ugeth
))
2088 ("%s: VLAN priority table entry must not be"
2089 " larger than number of Rx queues.",
2096 for (i
= 0; i
< UCC_GETH_IP_PRIORITY_MAX
; i
++) {
2097 if (ug_info
->l3qt
[i
] >= ug_info
->numQueuesRx
) {
2098 if (netif_msg_probe(ugeth
))
2100 ("%s: IP priority table entry must not be"
2101 " larger than number of Rx queues.",
2107 if (ug_info
->cam
&& !ug_info
->ecamptr
) {
2108 if (netif_msg_probe(ugeth
))
2109 ugeth_err("%s: If cam mode is chosen, must supply cam ptr.",
2114 if ((ug_info
->numStationAddresses
!=
2115 UCC_GETH_NUM_OF_STATION_ADDRESSES_1
)
2116 && ug_info
->rxExtendedFiltering
) {
2117 if (netif_msg_probe(ugeth
))
2118 ugeth_err("%s: Number of station addresses greater than 1 "
2119 "not allowed in extended parsing mode.",
2124 /* Generate uccm_mask for receive */
2125 uf_info
->uccm_mask
= ug_info
->eventRegMask
& UCCE_OTHER
;/* Errors */
2126 for (i
= 0; i
< ug_info
->numQueuesRx
; i
++)
2127 uf_info
->uccm_mask
|= (UCC_GETH_UCCE_RXF0
<< i
);
2129 for (i
= 0; i
< ug_info
->numQueuesTx
; i
++)
2130 uf_info
->uccm_mask
|= (UCC_GETH_UCCE_TXB0
<< i
);
2131 /* Initialize the general fast UCC block. */
2132 if (ucc_fast_init(uf_info
, &ugeth
->uccf
)) {
2133 if (netif_msg_probe(ugeth
))
2134 ugeth_err("%s: Failed to init uccf.", __func__
);
2138 /* read the number of risc engines, update the riscTx and riscRx
2139 * if there are 4 riscs in QE
2141 if (qe_get_num_of_risc() == 4) {
2142 ug_info
->riscTx
= QE_RISC_ALLOCATION_FOUR_RISCS
;
2143 ug_info
->riscRx
= QE_RISC_ALLOCATION_FOUR_RISCS
;
2146 ugeth
->ug_regs
= ioremap(uf_info
->regs
, sizeof(*ugeth
->ug_regs
));
2147 if (!ugeth
->ug_regs
) {
2148 if (netif_msg_probe(ugeth
))
2149 ugeth_err("%s: Failed to ioremap regs.", __func__
);
2156 static int ucc_geth_startup(struct ucc_geth_private
*ugeth
)
2158 struct ucc_geth_82xx_address_filtering_pram __iomem
*p_82xx_addr_filt
;
2159 struct ucc_geth_init_pram __iomem
*p_init_enet_pram
;
2160 struct ucc_fast_private
*uccf
;
2161 struct ucc_geth_info
*ug_info
;
2162 struct ucc_fast_info
*uf_info
;
2163 struct ucc_fast __iomem
*uf_regs
;
2164 struct ucc_geth __iomem
*ug_regs
;
2165 int ret_val
= -EINVAL
;
2166 u32 remoder
= UCC_GETH_REMODER_INIT
;
2167 u32 init_enet_pram_offset
, cecr_subblock
, command
;
2168 u32 ifstat
, i
, j
, size
, l2qt
, l3qt
, length
;
2169 u16 temoder
= UCC_GETH_TEMODER_INIT
;
2171 u8 function_code
= 0;
2173 u8 __iomem
*endOfRing
;
2174 u8 numThreadsRxNumerical
, numThreadsTxNumerical
;
2176 ugeth_vdbg("%s: IN", __func__
);
2178 ug_info
= ugeth
->ug_info
;
2179 uf_info
= &ug_info
->uf_info
;
2180 uf_regs
= uccf
->uf_regs
;
2181 ug_regs
= ugeth
->ug_regs
;
2183 switch (ug_info
->numThreadsRx
) {
2184 case UCC_GETH_NUM_OF_THREADS_1
:
2185 numThreadsRxNumerical
= 1;
2187 case UCC_GETH_NUM_OF_THREADS_2
:
2188 numThreadsRxNumerical
= 2;
2190 case UCC_GETH_NUM_OF_THREADS_4
:
2191 numThreadsRxNumerical
= 4;
2193 case UCC_GETH_NUM_OF_THREADS_6
:
2194 numThreadsRxNumerical
= 6;
2196 case UCC_GETH_NUM_OF_THREADS_8
:
2197 numThreadsRxNumerical
= 8;
2200 if (netif_msg_ifup(ugeth
))
2201 ugeth_err("%s: Bad number of Rx threads value.",
2207 switch (ug_info
->numThreadsTx
) {
2208 case UCC_GETH_NUM_OF_THREADS_1
:
2209 numThreadsTxNumerical
= 1;
2211 case UCC_GETH_NUM_OF_THREADS_2
:
2212 numThreadsTxNumerical
= 2;
2214 case UCC_GETH_NUM_OF_THREADS_4
:
2215 numThreadsTxNumerical
= 4;
2217 case UCC_GETH_NUM_OF_THREADS_6
:
2218 numThreadsTxNumerical
= 6;
2220 case UCC_GETH_NUM_OF_THREADS_8
:
2221 numThreadsTxNumerical
= 8;
2224 if (netif_msg_ifup(ugeth
))
2225 ugeth_err("%s: Bad number of Tx threads value.",
2231 /* Calculate rx_extended_features */
2232 ugeth
->rx_non_dynamic_extended_features
= ug_info
->ipCheckSumCheck
||
2233 ug_info
->ipAddressAlignment
||
2234 (ug_info
->numStationAddresses
!=
2235 UCC_GETH_NUM_OF_STATION_ADDRESSES_1
);
2237 ugeth
->rx_extended_features
= ugeth
->rx_non_dynamic_extended_features
||
2238 (ug_info
->vlanOperationTagged
!= UCC_GETH_VLAN_OPERATION_TAGGED_NOP
)
2239 || (ug_info
->vlanOperationNonTagged
!=
2240 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP
);
2242 init_default_reg_vals(&uf_regs
->upsmr
,
2243 &ug_regs
->maccfg1
, &ug_regs
->maccfg2
);
2246 /* For more details see the hardware spec. */
2247 init_rx_parameters(ug_info
->bro
,
2248 ug_info
->rsh
, ug_info
->pro
, &uf_regs
->upsmr
);
2250 /* We're going to ignore other registers for now, */
2251 /* except as needed to get up and running */
2254 /* For more details see the hardware spec. */
2255 init_flow_control_params(ug_info
->aufc
,
2256 ug_info
->receiveFlowControl
,
2257 ug_info
->transmitFlowControl
,
2258 ug_info
->pausePeriod
,
2259 ug_info
->extensionField
,
2261 &ug_regs
->uempr
, &ug_regs
->maccfg1
);
2263 setbits32(&ug_regs
->maccfg1
, MACCFG1_ENABLE_RX
| MACCFG1_ENABLE_TX
);
2266 /* For more details see the hardware spec. */
2267 ret_val
= init_inter_frame_gap_params(ug_info
->nonBackToBackIfgPart1
,
2268 ug_info
->nonBackToBackIfgPart2
,
2270 miminumInterFrameGapEnforcement
,
2271 ug_info
->backToBackInterFrameGap
,
2274 if (netif_msg_ifup(ugeth
))
2275 ugeth_err("%s: IPGIFG initialization parameter too large.",
2281 /* For more details see the hardware spec. */
2282 ret_val
= init_half_duplex_params(ug_info
->altBeb
,
2283 ug_info
->backPressureNoBackoff
,
2285 ug_info
->excessDefer
,
2286 ug_info
->altBebTruncation
,
2287 ug_info
->maxRetransmission
,
2288 ug_info
->collisionWindow
,
2291 if (netif_msg_ifup(ugeth
))
2292 ugeth_err("%s: Half Duplex initialization parameter too large.",
2298 /* For more details see the hardware spec. */
2299 /* Read only - resets upon read */
2300 ifstat
= in_be32(&ug_regs
->ifstat
);
2303 /* For more details see the hardware spec. */
2304 out_be32(&ug_regs
->uempr
, 0);
2307 /* For more details see the hardware spec. */
2308 init_hw_statistics_gathering_mode((ug_info
->statisticsMode
&
2309 UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE
),
2310 0, &uf_regs
->upsmr
, &ug_regs
->uescr
);
2312 /* Allocate Tx bds */
2313 for (j
= 0; j
< ug_info
->numQueuesTx
; j
++) {
2314 /* Allocate in multiple of
2315 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT,
2316 according to spec */
2317 length
= ((ug_info
->bdRingLenTx
[j
] * sizeof(struct qe_bd
))
2318 / UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT
)
2319 * UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT
;
2320 if ((ug_info
->bdRingLenTx
[j
] * sizeof(struct qe_bd
)) %
2321 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT
)
2322 length
+= UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT
;
2323 if (uf_info
->bd_mem_part
== MEM_PART_SYSTEM
) {
2325 if (UCC_GETH_TX_BD_RING_ALIGNMENT
> 4)
2326 align
= UCC_GETH_TX_BD_RING_ALIGNMENT
;
2327 ugeth
->tx_bd_ring_offset
[j
] =
2328 (u32
) kmalloc((u32
) (length
+ align
), GFP_KERNEL
);
2330 if (ugeth
->tx_bd_ring_offset
[j
] != 0)
2331 ugeth
->p_tx_bd_ring
[j
] =
2332 (u8 __iomem
*)((ugeth
->tx_bd_ring_offset
[j
] +
2333 align
) & ~(align
- 1));
2334 } else if (uf_info
->bd_mem_part
== MEM_PART_MURAM
) {
2335 ugeth
->tx_bd_ring_offset
[j
] =
2336 qe_muram_alloc(length
,
2337 UCC_GETH_TX_BD_RING_ALIGNMENT
);
2338 if (!IS_ERR_VALUE(ugeth
->tx_bd_ring_offset
[j
]))
2339 ugeth
->p_tx_bd_ring
[j
] =
2340 (u8 __iomem
*) qe_muram_addr(ugeth
->
2341 tx_bd_ring_offset
[j
]);
2343 if (!ugeth
->p_tx_bd_ring
[j
]) {
2344 if (netif_msg_ifup(ugeth
))
2346 ("%s: Can not allocate memory for Tx bd rings.",
2350 /* Zero unused end of bd ring, according to spec */
2351 memset_io((void __iomem
*)(ugeth
->p_tx_bd_ring
[j
] +
2352 ug_info
->bdRingLenTx
[j
] * sizeof(struct qe_bd
)), 0,
2353 length
- ug_info
->bdRingLenTx
[j
] * sizeof(struct qe_bd
));
2356 /* Allocate Rx bds */
2357 for (j
= 0; j
< ug_info
->numQueuesRx
; j
++) {
2358 length
= ug_info
->bdRingLenRx
[j
] * sizeof(struct qe_bd
);
2359 if (uf_info
->bd_mem_part
== MEM_PART_SYSTEM
) {
2361 if (UCC_GETH_RX_BD_RING_ALIGNMENT
> 4)
2362 align
= UCC_GETH_RX_BD_RING_ALIGNMENT
;
2363 ugeth
->rx_bd_ring_offset
[j
] =
2364 (u32
) kmalloc((u32
) (length
+ align
), GFP_KERNEL
);
2365 if (ugeth
->rx_bd_ring_offset
[j
] != 0)
2366 ugeth
->p_rx_bd_ring
[j
] =
2367 (u8 __iomem
*)((ugeth
->rx_bd_ring_offset
[j
] +
2368 align
) & ~(align
- 1));
2369 } else if (uf_info
->bd_mem_part
== MEM_PART_MURAM
) {
2370 ugeth
->rx_bd_ring_offset
[j
] =
2371 qe_muram_alloc(length
,
2372 UCC_GETH_RX_BD_RING_ALIGNMENT
);
2373 if (!IS_ERR_VALUE(ugeth
->rx_bd_ring_offset
[j
]))
2374 ugeth
->p_rx_bd_ring
[j
] =
2375 (u8 __iomem
*) qe_muram_addr(ugeth
->
2376 rx_bd_ring_offset
[j
]);
2378 if (!ugeth
->p_rx_bd_ring
[j
]) {
2379 if (netif_msg_ifup(ugeth
))
2381 ("%s: Can not allocate memory for Rx bd rings.",
2388 for (j
= 0; j
< ug_info
->numQueuesTx
; j
++) {
2389 /* Setup the skbuff rings */
2390 ugeth
->tx_skbuff
[j
] = kmalloc(sizeof(struct sk_buff
*) *
2391 ugeth
->ug_info
->bdRingLenTx
[j
],
2394 if (ugeth
->tx_skbuff
[j
] == NULL
) {
2395 if (netif_msg_ifup(ugeth
))
2396 ugeth_err("%s: Could not allocate tx_skbuff",
2401 for (i
= 0; i
< ugeth
->ug_info
->bdRingLenTx
[j
]; i
++)
2402 ugeth
->tx_skbuff
[j
][i
] = NULL
;
2404 ugeth
->skb_curtx
[j
] = ugeth
->skb_dirtytx
[j
] = 0;
2405 bd
= ugeth
->confBd
[j
] = ugeth
->txBd
[j
] = ugeth
->p_tx_bd_ring
[j
];
2406 for (i
= 0; i
< ug_info
->bdRingLenTx
[j
]; i
++) {
2407 /* clear bd buffer */
2408 out_be32(&((struct qe_bd __iomem
*)bd
)->buf
, 0);
2409 /* set bd status and length */
2410 out_be32((u32 __iomem
*)bd
, 0);
2411 bd
+= sizeof(struct qe_bd
);
2413 bd
-= sizeof(struct qe_bd
);
2414 /* set bd status and length */
2415 out_be32((u32 __iomem
*)bd
, T_W
); /* for last BD set Wrap bit */
2419 for (j
= 0; j
< ug_info
->numQueuesRx
; j
++) {
2420 /* Setup the skbuff rings */
2421 ugeth
->rx_skbuff
[j
] = kmalloc(sizeof(struct sk_buff
*) *
2422 ugeth
->ug_info
->bdRingLenRx
[j
],
2425 if (ugeth
->rx_skbuff
[j
] == NULL
) {
2426 if (netif_msg_ifup(ugeth
))
2427 ugeth_err("%s: Could not allocate rx_skbuff",
2432 for (i
= 0; i
< ugeth
->ug_info
->bdRingLenRx
[j
]; i
++)
2433 ugeth
->rx_skbuff
[j
][i
] = NULL
;
2435 ugeth
->skb_currx
[j
] = 0;
2436 bd
= ugeth
->rxBd
[j
] = ugeth
->p_rx_bd_ring
[j
];
2437 for (i
= 0; i
< ug_info
->bdRingLenRx
[j
]; i
++) {
2438 /* set bd status and length */
2439 out_be32((u32 __iomem
*)bd
, R_I
);
2440 /* clear bd buffer */
2441 out_be32(&((struct qe_bd __iomem
*)bd
)->buf
, 0);
2442 bd
+= sizeof(struct qe_bd
);
2444 bd
-= sizeof(struct qe_bd
);
2445 /* set bd status and length */
2446 out_be32((u32 __iomem
*)bd
, R_W
); /* for last BD set Wrap bit */
2452 /* Tx global PRAM */
2453 /* Allocate global tx parameter RAM page */
2454 ugeth
->tx_glbl_pram_offset
=
2455 qe_muram_alloc(sizeof(struct ucc_geth_tx_global_pram
),
2456 UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT
);
2457 if (IS_ERR_VALUE(ugeth
->tx_glbl_pram_offset
)) {
2458 if (netif_msg_ifup(ugeth
))
2460 ("%s: Can not allocate DPRAM memory for p_tx_glbl_pram.",
2464 ugeth
->p_tx_glbl_pram
=
2465 (struct ucc_geth_tx_global_pram __iomem
*) qe_muram_addr(ugeth
->
2466 tx_glbl_pram_offset
);
2467 /* Zero out p_tx_glbl_pram */
2468 memset_io((void __iomem
*)ugeth
->p_tx_glbl_pram
, 0, sizeof(struct ucc_geth_tx_global_pram
));
2470 /* Fill global PRAM */
2473 /* Size varies with number of Tx threads */
2474 ugeth
->thread_dat_tx_offset
=
2475 qe_muram_alloc(numThreadsTxNumerical
*
2476 sizeof(struct ucc_geth_thread_data_tx
) +
2477 32 * (numThreadsTxNumerical
== 1),
2478 UCC_GETH_THREAD_DATA_ALIGNMENT
);
2479 if (IS_ERR_VALUE(ugeth
->thread_dat_tx_offset
)) {
2480 if (netif_msg_ifup(ugeth
))
2482 ("%s: Can not allocate DPRAM memory for p_thread_data_tx.",
2487 ugeth
->p_thread_data_tx
=
2488 (struct ucc_geth_thread_data_tx __iomem
*) qe_muram_addr(ugeth
->
2489 thread_dat_tx_offset
);
2490 out_be32(&ugeth
->p_tx_glbl_pram
->tqptr
, ugeth
->thread_dat_tx_offset
);
2493 for (i
= 0; i
< UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX
; i
++)
2494 out_be32(&ugeth
->p_tx_glbl_pram
->vtagtable
[i
],
2495 ug_info
->vtagtable
[i
]);
2498 for (i
= 0; i
< TX_IP_OFFSET_ENTRY_MAX
; i
++)
2499 out_8(&ugeth
->p_tx_glbl_pram
->iphoffset
[i
],
2500 ug_info
->iphoffset
[i
]);
2503 /* Size varies with number of Tx queues */
2504 ugeth
->send_q_mem_reg_offset
=
2505 qe_muram_alloc(ug_info
->numQueuesTx
*
2506 sizeof(struct ucc_geth_send_queue_qd
),
2507 UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT
);
2508 if (IS_ERR_VALUE(ugeth
->send_q_mem_reg_offset
)) {
2509 if (netif_msg_ifup(ugeth
))
2511 ("%s: Can not allocate DPRAM memory for p_send_q_mem_reg.",
2516 ugeth
->p_send_q_mem_reg
=
2517 (struct ucc_geth_send_queue_mem_region __iomem
*) qe_muram_addr(ugeth
->
2518 send_q_mem_reg_offset
);
2519 out_be32(&ugeth
->p_tx_glbl_pram
->sqptr
, ugeth
->send_q_mem_reg_offset
);
2521 /* Setup the table */
2522 /* Assume BD rings are already established */
2523 for (i
= 0; i
< ug_info
->numQueuesTx
; i
++) {
2525 ugeth
->p_tx_bd_ring
[i
] + (ug_info
->bdRingLenTx
[i
] -
2526 1) * sizeof(struct qe_bd
);
2527 if (ugeth
->ug_info
->uf_info
.bd_mem_part
== MEM_PART_SYSTEM
) {
2528 out_be32(&ugeth
->p_send_q_mem_reg
->sqqd
[i
].bd_ring_base
,
2529 (u32
) virt_to_phys(ugeth
->p_tx_bd_ring
[i
]));
2530 out_be32(&ugeth
->p_send_q_mem_reg
->sqqd
[i
].
2531 last_bd_completed_address
,
2532 (u32
) virt_to_phys(endOfRing
));
2533 } else if (ugeth
->ug_info
->uf_info
.bd_mem_part
==
2535 out_be32(&ugeth
->p_send_q_mem_reg
->sqqd
[i
].bd_ring_base
,
2536 (u32
) immrbar_virt_to_phys(ugeth
->
2538 out_be32(&ugeth
->p_send_q_mem_reg
->sqqd
[i
].
2539 last_bd_completed_address
,
2540 (u32
) immrbar_virt_to_phys(endOfRing
));
2544 /* schedulerbasepointer */
2546 if (ug_info
->numQueuesTx
> 1) {
2547 /* scheduler exists only if more than 1 tx queue */
2548 ugeth
->scheduler_offset
=
2549 qe_muram_alloc(sizeof(struct ucc_geth_scheduler
),
2550 UCC_GETH_SCHEDULER_ALIGNMENT
);
2551 if (IS_ERR_VALUE(ugeth
->scheduler_offset
)) {
2552 if (netif_msg_ifup(ugeth
))
2554 ("%s: Can not allocate DPRAM memory for p_scheduler.",
2559 ugeth
->p_scheduler
=
2560 (struct ucc_geth_scheduler __iomem
*) qe_muram_addr(ugeth
->
2562 out_be32(&ugeth
->p_tx_glbl_pram
->schedulerbasepointer
,
2563 ugeth
->scheduler_offset
);
2564 /* Zero out p_scheduler */
2565 memset_io((void __iomem
*)ugeth
->p_scheduler
, 0, sizeof(struct ucc_geth_scheduler
));
2567 /* Set values in scheduler */
2568 out_be32(&ugeth
->p_scheduler
->mblinterval
,
2569 ug_info
->mblinterval
);
2570 out_be16(&ugeth
->p_scheduler
->nortsrbytetime
,
2571 ug_info
->nortsrbytetime
);
2572 out_8(&ugeth
->p_scheduler
->fracsiz
, ug_info
->fracsiz
);
2573 out_8(&ugeth
->p_scheduler
->strictpriorityq
,
2574 ug_info
->strictpriorityq
);
2575 out_8(&ugeth
->p_scheduler
->txasap
, ug_info
->txasap
);
2576 out_8(&ugeth
->p_scheduler
->extrabw
, ug_info
->extrabw
);
2577 for (i
= 0; i
< NUM_TX_QUEUES
; i
++)
2578 out_8(&ugeth
->p_scheduler
->weightfactor
[i
],
2579 ug_info
->weightfactor
[i
]);
2581 /* Set pointers to cpucount registers in scheduler */
2582 ugeth
->p_cpucount
[0] = &(ugeth
->p_scheduler
->cpucount0
);
2583 ugeth
->p_cpucount
[1] = &(ugeth
->p_scheduler
->cpucount1
);
2584 ugeth
->p_cpucount
[2] = &(ugeth
->p_scheduler
->cpucount2
);
2585 ugeth
->p_cpucount
[3] = &(ugeth
->p_scheduler
->cpucount3
);
2586 ugeth
->p_cpucount
[4] = &(ugeth
->p_scheduler
->cpucount4
);
2587 ugeth
->p_cpucount
[5] = &(ugeth
->p_scheduler
->cpucount5
);
2588 ugeth
->p_cpucount
[6] = &(ugeth
->p_scheduler
->cpucount6
);
2589 ugeth
->p_cpucount
[7] = &(ugeth
->p_scheduler
->cpucount7
);
2592 /* schedulerbasepointer */
2593 /* TxRMON_PTR (statistics) */
2595 statisticsMode
& UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX
) {
2596 ugeth
->tx_fw_statistics_pram_offset
=
2597 qe_muram_alloc(sizeof
2598 (struct ucc_geth_tx_firmware_statistics_pram
),
2599 UCC_GETH_TX_STATISTICS_ALIGNMENT
);
2600 if (IS_ERR_VALUE(ugeth
->tx_fw_statistics_pram_offset
)) {
2601 if (netif_msg_ifup(ugeth
))
2603 ("%s: Can not allocate DPRAM memory for"
2604 " p_tx_fw_statistics_pram.",
2608 ugeth
->p_tx_fw_statistics_pram
=
2609 (struct ucc_geth_tx_firmware_statistics_pram __iomem
*)
2610 qe_muram_addr(ugeth
->tx_fw_statistics_pram_offset
);
2611 /* Zero out p_tx_fw_statistics_pram */
2612 memset_io((void __iomem
*)ugeth
->p_tx_fw_statistics_pram
,
2613 0, sizeof(struct ucc_geth_tx_firmware_statistics_pram
));
2617 /* Already has speed set */
2619 if (ug_info
->numQueuesTx
> 1)
2620 temoder
|= TEMODER_SCHEDULER_ENABLE
;
2621 if (ug_info
->ipCheckSumGenerate
)
2622 temoder
|= TEMODER_IP_CHECKSUM_GENERATE
;
2623 temoder
|= ((ug_info
->numQueuesTx
- 1) << TEMODER_NUM_OF_QUEUES_SHIFT
);
2624 out_be16(&ugeth
->p_tx_glbl_pram
->temoder
, temoder
);
2626 test
= in_be16(&ugeth
->p_tx_glbl_pram
->temoder
);
2628 /* Function code register value to be used later */
2629 function_code
= UCC_BMR_BO_BE
| UCC_BMR_GBL
;
2630 /* Required for QE */
2632 /* function code register */
2633 out_be32(&ugeth
->p_tx_glbl_pram
->tstate
, ((u32
) function_code
) << 24);
2635 /* Rx global PRAM */
2636 /* Allocate global rx parameter RAM page */
2637 ugeth
->rx_glbl_pram_offset
=
2638 qe_muram_alloc(sizeof(struct ucc_geth_rx_global_pram
),
2639 UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT
);
2640 if (IS_ERR_VALUE(ugeth
->rx_glbl_pram_offset
)) {
2641 if (netif_msg_ifup(ugeth
))
2643 ("%s: Can not allocate DPRAM memory for p_rx_glbl_pram.",
2647 ugeth
->p_rx_glbl_pram
=
2648 (struct ucc_geth_rx_global_pram __iomem
*) qe_muram_addr(ugeth
->
2649 rx_glbl_pram_offset
);
2650 /* Zero out p_rx_glbl_pram */
2651 memset_io((void __iomem
*)ugeth
->p_rx_glbl_pram
, 0, sizeof(struct ucc_geth_rx_global_pram
));
2653 /* Fill global PRAM */
2656 /* Size varies with number of Rx threads */
2657 ugeth
->thread_dat_rx_offset
=
2658 qe_muram_alloc(numThreadsRxNumerical
*
2659 sizeof(struct ucc_geth_thread_data_rx
),
2660 UCC_GETH_THREAD_DATA_ALIGNMENT
);
2661 if (IS_ERR_VALUE(ugeth
->thread_dat_rx_offset
)) {
2662 if (netif_msg_ifup(ugeth
))
2664 ("%s: Can not allocate DPRAM memory for p_thread_data_rx.",
2669 ugeth
->p_thread_data_rx
=
2670 (struct ucc_geth_thread_data_rx __iomem
*) qe_muram_addr(ugeth
->
2671 thread_dat_rx_offset
);
2672 out_be32(&ugeth
->p_rx_glbl_pram
->rqptr
, ugeth
->thread_dat_rx_offset
);
2675 out_be16(&ugeth
->p_rx_glbl_pram
->typeorlen
, ug_info
->typeorlen
);
2677 /* rxrmonbaseptr (statistics) */
2679 statisticsMode
& UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX
) {
2680 ugeth
->rx_fw_statistics_pram_offset
=
2681 qe_muram_alloc(sizeof
2682 (struct ucc_geth_rx_firmware_statistics_pram
),
2683 UCC_GETH_RX_STATISTICS_ALIGNMENT
);
2684 if (IS_ERR_VALUE(ugeth
->rx_fw_statistics_pram_offset
)) {
2685 if (netif_msg_ifup(ugeth
))
2687 ("%s: Can not allocate DPRAM memory for"
2688 " p_rx_fw_statistics_pram.", __func__
);
2691 ugeth
->p_rx_fw_statistics_pram
=
2692 (struct ucc_geth_rx_firmware_statistics_pram __iomem
*)
2693 qe_muram_addr(ugeth
->rx_fw_statistics_pram_offset
);
2694 /* Zero out p_rx_fw_statistics_pram */
2695 memset_io((void __iomem
*)ugeth
->p_rx_fw_statistics_pram
, 0,
2696 sizeof(struct ucc_geth_rx_firmware_statistics_pram
));
2699 /* intCoalescingPtr */
2701 /* Size varies with number of Rx queues */
2702 ugeth
->rx_irq_coalescing_tbl_offset
=
2703 qe_muram_alloc(ug_info
->numQueuesRx
*
2704 sizeof(struct ucc_geth_rx_interrupt_coalescing_entry
)
2705 + 4, UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT
);
2706 if (IS_ERR_VALUE(ugeth
->rx_irq_coalescing_tbl_offset
)) {
2707 if (netif_msg_ifup(ugeth
))
2709 ("%s: Can not allocate DPRAM memory for"
2710 " p_rx_irq_coalescing_tbl.", __func__
);
2714 ugeth
->p_rx_irq_coalescing_tbl
=
2715 (struct ucc_geth_rx_interrupt_coalescing_table __iomem
*)
2716 qe_muram_addr(ugeth
->rx_irq_coalescing_tbl_offset
);
2717 out_be32(&ugeth
->p_rx_glbl_pram
->intcoalescingptr
,
2718 ugeth
->rx_irq_coalescing_tbl_offset
);
2720 /* Fill interrupt coalescing table */
2721 for (i
= 0; i
< ug_info
->numQueuesRx
; i
++) {
2722 out_be32(&ugeth
->p_rx_irq_coalescing_tbl
->coalescingentry
[i
].
2723 interruptcoalescingmaxvalue
,
2724 ug_info
->interruptcoalescingmaxvalue
[i
]);
2725 out_be32(&ugeth
->p_rx_irq_coalescing_tbl
->coalescingentry
[i
].
2726 interruptcoalescingcounter
,
2727 ug_info
->interruptcoalescingmaxvalue
[i
]);
2731 init_max_rx_buff_len(uf_info
->max_rx_buf_length
,
2732 &ugeth
->p_rx_glbl_pram
->mrblr
);
2734 out_be16(&ugeth
->p_rx_glbl_pram
->mflr
, ug_info
->maxFrameLength
);
2736 init_min_frame_len(ug_info
->minFrameLength
,
2737 &ugeth
->p_rx_glbl_pram
->minflr
,
2738 &ugeth
->p_rx_glbl_pram
->mrblr
);
2740 out_be16(&ugeth
->p_rx_glbl_pram
->maxd1
, ug_info
->maxD1Length
);
2742 out_be16(&ugeth
->p_rx_glbl_pram
->maxd2
, ug_info
->maxD2Length
);
2746 for (i
= 0; i
< UCC_GETH_VLAN_PRIORITY_MAX
; i
++)
2747 l2qt
|= (ug_info
->l2qt
[i
] << (28 - 4 * i
));
2748 out_be32(&ugeth
->p_rx_glbl_pram
->l2qt
, l2qt
);
2751 for (j
= 0; j
< UCC_GETH_IP_PRIORITY_MAX
; j
+= 8) {
2753 for (i
= 0; i
< 8; i
++)
2754 l3qt
|= (ug_info
->l3qt
[j
+ i
] << (28 - 4 * i
));
2755 out_be32(&ugeth
->p_rx_glbl_pram
->l3qt
[j
/8], l3qt
);
2759 out_be16(&ugeth
->p_rx_glbl_pram
->vlantype
, ug_info
->vlantype
);
2762 out_be16(&ugeth
->p_rx_glbl_pram
->vlantci
, ug_info
->vlantci
);
2765 out_be32(&ugeth
->p_rx_glbl_pram
->ecamptr
, ug_info
->ecamptr
);
2768 /* Size varies with number of Rx queues */
2769 ugeth
->rx_bd_qs_tbl_offset
=
2770 qe_muram_alloc(ug_info
->numQueuesRx
*
2771 (sizeof(struct ucc_geth_rx_bd_queues_entry
) +
2772 sizeof(struct ucc_geth_rx_prefetched_bds
)),
2773 UCC_GETH_RX_BD_QUEUES_ALIGNMENT
);
2774 if (IS_ERR_VALUE(ugeth
->rx_bd_qs_tbl_offset
)) {
2775 if (netif_msg_ifup(ugeth
))
2777 ("%s: Can not allocate DPRAM memory for p_rx_bd_qs_tbl.",
2782 ugeth
->p_rx_bd_qs_tbl
=
2783 (struct ucc_geth_rx_bd_queues_entry __iomem
*) qe_muram_addr(ugeth
->
2784 rx_bd_qs_tbl_offset
);
2785 out_be32(&ugeth
->p_rx_glbl_pram
->rbdqptr
, ugeth
->rx_bd_qs_tbl_offset
);
2786 /* Zero out p_rx_bd_qs_tbl */
2787 memset_io((void __iomem
*)ugeth
->p_rx_bd_qs_tbl
,
2789 ug_info
->numQueuesRx
* (sizeof(struct ucc_geth_rx_bd_queues_entry
) +
2790 sizeof(struct ucc_geth_rx_prefetched_bds
)));
2792 /* Setup the table */
2793 /* Assume BD rings are already established */
2794 for (i
= 0; i
< ug_info
->numQueuesRx
; i
++) {
2795 if (ugeth
->ug_info
->uf_info
.bd_mem_part
== MEM_PART_SYSTEM
) {
2796 out_be32(&ugeth
->p_rx_bd_qs_tbl
[i
].externalbdbaseptr
,
2797 (u32
) virt_to_phys(ugeth
->p_rx_bd_ring
[i
]));
2798 } else if (ugeth
->ug_info
->uf_info
.bd_mem_part
==
2800 out_be32(&ugeth
->p_rx_bd_qs_tbl
[i
].externalbdbaseptr
,
2801 (u32
) immrbar_virt_to_phys(ugeth
->
2804 /* rest of fields handled by QE */
2808 /* Already has speed set */
2810 if (ugeth
->rx_extended_features
)
2811 remoder
|= REMODER_RX_EXTENDED_FEATURES
;
2812 if (ug_info
->rxExtendedFiltering
)
2813 remoder
|= REMODER_RX_EXTENDED_FILTERING
;
2814 if (ug_info
->dynamicMaxFrameLength
)
2815 remoder
|= REMODER_DYNAMIC_MAX_FRAME_LENGTH
;
2816 if (ug_info
->dynamicMinFrameLength
)
2817 remoder
|= REMODER_DYNAMIC_MIN_FRAME_LENGTH
;
2819 ug_info
->vlanOperationTagged
<< REMODER_VLAN_OPERATION_TAGGED_SHIFT
;
2822 vlanOperationNonTagged
<< REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT
;
2823 remoder
|= ug_info
->rxQoSMode
<< REMODER_RX_QOS_MODE_SHIFT
;
2824 remoder
|= ((ug_info
->numQueuesRx
- 1) << REMODER_NUM_OF_QUEUES_SHIFT
);
2825 if (ug_info
->ipCheckSumCheck
)
2826 remoder
|= REMODER_IP_CHECKSUM_CHECK
;
2827 if (ug_info
->ipAddressAlignment
)
2828 remoder
|= REMODER_IP_ADDRESS_ALIGNMENT
;
2829 out_be32(&ugeth
->p_rx_glbl_pram
->remoder
, remoder
);
2831 /* Note that this function must be called */
2832 /* ONLY AFTER p_tx_fw_statistics_pram */
2833 /* andp_UccGethRxFirmwareStatisticsPram are allocated ! */
2834 init_firmware_statistics_gathering_mode((ug_info
->
2836 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX
),
2837 (ug_info
->statisticsMode
&
2838 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX
),
2839 &ugeth
->p_tx_glbl_pram
->txrmonbaseptr
,
2840 ugeth
->tx_fw_statistics_pram_offset
,
2841 &ugeth
->p_rx_glbl_pram
->rxrmonbaseptr
,
2842 ugeth
->rx_fw_statistics_pram_offset
,
2843 &ugeth
->p_tx_glbl_pram
->temoder
,
2844 &ugeth
->p_rx_glbl_pram
->remoder
);
2846 /* function code register */
2847 out_8(&ugeth
->p_rx_glbl_pram
->rstate
, function_code
);
2849 /* initialize extended filtering */
2850 if (ug_info
->rxExtendedFiltering
) {
2851 if (!ug_info
->extendedFilteringChainPointer
) {
2852 if (netif_msg_ifup(ugeth
))
2853 ugeth_err("%s: Null Extended Filtering Chain Pointer.",
2858 /* Allocate memory for extended filtering Mode Global
2860 ugeth
->exf_glbl_param_offset
=
2861 qe_muram_alloc(sizeof(struct ucc_geth_exf_global_pram
),
2862 UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT
);
2863 if (IS_ERR_VALUE(ugeth
->exf_glbl_param_offset
)) {
2864 if (netif_msg_ifup(ugeth
))
2866 ("%s: Can not allocate DPRAM memory for"
2867 " p_exf_glbl_param.", __func__
);
2871 ugeth
->p_exf_glbl_param
=
2872 (struct ucc_geth_exf_global_pram __iomem
*) qe_muram_addr(ugeth
->
2873 exf_glbl_param_offset
);
2874 out_be32(&ugeth
->p_rx_glbl_pram
->exfGlobalParam
,
2875 ugeth
->exf_glbl_param_offset
);
2876 out_be32(&ugeth
->p_exf_glbl_param
->l2pcdptr
,
2877 (u32
) ug_info
->extendedFilteringChainPointer
);
2879 } else { /* initialize 82xx style address filtering */
2881 /* Init individual address recognition registers to disabled */
2883 for (j
= 0; j
< NUM_OF_PADDRS
; j
++)
2884 ugeth_82xx_filtering_clear_addr_in_paddr(ugeth
, (u8
) j
);
2887 (struct ucc_geth_82xx_address_filtering_pram __iomem
*) ugeth
->
2888 p_rx_glbl_pram
->addressfiltering
;
2890 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth
,
2891 ENET_ADDR_TYPE_GROUP
);
2892 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth
,
2893 ENET_ADDR_TYPE_INDIVIDUAL
);
2897 * Initialize UCC at QE level
2900 command
= QE_INIT_TX_RX
;
2902 /* Allocate shadow InitEnet command parameter structure.
2903 * This is needed because after the InitEnet command is executed,
2904 * the structure in DPRAM is released, because DPRAM is a premium
2906 * This shadow structure keeps a copy of what was done so that the
2907 * allocated resources can be released when the channel is freed.
2909 if (!(ugeth
->p_init_enet_param_shadow
=
2910 kmalloc(sizeof(struct ucc_geth_init_pram
), GFP_KERNEL
))) {
2911 if (netif_msg_ifup(ugeth
))
2913 ("%s: Can not allocate memory for"
2914 " p_UccInitEnetParamShadows.", __func__
);
2917 /* Zero out *p_init_enet_param_shadow */
2918 memset((char *)ugeth
->p_init_enet_param_shadow
,
2919 0, sizeof(struct ucc_geth_init_pram
));
2921 /* Fill shadow InitEnet command parameter structure */
2923 ugeth
->p_init_enet_param_shadow
->resinit1
=
2924 ENET_INIT_PARAM_MAGIC_RES_INIT1
;
2925 ugeth
->p_init_enet_param_shadow
->resinit2
=
2926 ENET_INIT_PARAM_MAGIC_RES_INIT2
;
2927 ugeth
->p_init_enet_param_shadow
->resinit3
=
2928 ENET_INIT_PARAM_MAGIC_RES_INIT3
;
2929 ugeth
->p_init_enet_param_shadow
->resinit4
=
2930 ENET_INIT_PARAM_MAGIC_RES_INIT4
;
2931 ugeth
->p_init_enet_param_shadow
->resinit5
=
2932 ENET_INIT_PARAM_MAGIC_RES_INIT5
;
2933 ugeth
->p_init_enet_param_shadow
->rgftgfrxglobal
|=
2934 ((u32
) ug_info
->numThreadsRx
) << ENET_INIT_PARAM_RGF_SHIFT
;
2935 ugeth
->p_init_enet_param_shadow
->rgftgfrxglobal
|=
2936 ((u32
) ug_info
->numThreadsTx
) << ENET_INIT_PARAM_TGF_SHIFT
;
2938 ugeth
->p_init_enet_param_shadow
->rgftgfrxglobal
|=
2939 ugeth
->rx_glbl_pram_offset
| ug_info
->riscRx
;
2940 if ((ug_info
->largestexternallookupkeysize
!=
2941 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE
)
2942 && (ug_info
->largestexternallookupkeysize
!=
2943 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES
)
2944 && (ug_info
->largestexternallookupkeysize
!=
2945 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES
)) {
2946 if (netif_msg_ifup(ugeth
))
2947 ugeth_err("%s: Invalid largest External Lookup Key Size.",
2951 ugeth
->p_init_enet_param_shadow
->largestexternallookupkeysize
=
2952 ug_info
->largestexternallookupkeysize
;
2953 size
= sizeof(struct ucc_geth_thread_rx_pram
);
2954 if (ug_info
->rxExtendedFiltering
) {
2955 size
+= THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING
;
2956 if (ug_info
->largestexternallookupkeysize
==
2957 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES
)
2959 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8
;
2960 if (ug_info
->largestexternallookupkeysize
==
2961 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES
)
2963 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16
;
2966 if ((ret_val
= fill_init_enet_entries(ugeth
, &(ugeth
->
2967 p_init_enet_param_shadow
->rxthread
[0]),
2968 (u8
) (numThreadsRxNumerical
+ 1)
2969 /* Rx needs one extra for terminator */
2970 , size
, UCC_GETH_THREAD_RX_PRAM_ALIGNMENT
,
2971 ug_info
->riscRx
, 1)) != 0) {
2972 if (netif_msg_ifup(ugeth
))
2973 ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
2978 ugeth
->p_init_enet_param_shadow
->txglobal
=
2979 ugeth
->tx_glbl_pram_offset
| ug_info
->riscTx
;
2981 fill_init_enet_entries(ugeth
,
2982 &(ugeth
->p_init_enet_param_shadow
->
2983 txthread
[0]), numThreadsTxNumerical
,
2984 sizeof(struct ucc_geth_thread_tx_pram
),
2985 UCC_GETH_THREAD_TX_PRAM_ALIGNMENT
,
2986 ug_info
->riscTx
, 0)) != 0) {
2987 if (netif_msg_ifup(ugeth
))
2988 ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
2993 /* Load Rx bds with buffers */
2994 for (i
= 0; i
< ug_info
->numQueuesRx
; i
++) {
2995 if ((ret_val
= rx_bd_buffer_set(ugeth
, (u8
) i
)) != 0) {
2996 if (netif_msg_ifup(ugeth
))
2997 ugeth_err("%s: Can not fill Rx bds with buffers.",
3003 /* Allocate InitEnet command parameter structure */
3004 init_enet_pram_offset
= qe_muram_alloc(sizeof(struct ucc_geth_init_pram
), 4);
3005 if (IS_ERR_VALUE(init_enet_pram_offset
)) {
3006 if (netif_msg_ifup(ugeth
))
3008 ("%s: Can not allocate DPRAM memory for p_init_enet_pram.",
3013 (struct ucc_geth_init_pram __iomem
*) qe_muram_addr(init_enet_pram_offset
);
3015 /* Copy shadow InitEnet command parameter structure into PRAM */
3016 out_8(&p_init_enet_pram
->resinit1
,
3017 ugeth
->p_init_enet_param_shadow
->resinit1
);
3018 out_8(&p_init_enet_pram
->resinit2
,
3019 ugeth
->p_init_enet_param_shadow
->resinit2
);
3020 out_8(&p_init_enet_pram
->resinit3
,
3021 ugeth
->p_init_enet_param_shadow
->resinit3
);
3022 out_8(&p_init_enet_pram
->resinit4
,
3023 ugeth
->p_init_enet_param_shadow
->resinit4
);
3024 out_be16(&p_init_enet_pram
->resinit5
,
3025 ugeth
->p_init_enet_param_shadow
->resinit5
);
3026 out_8(&p_init_enet_pram
->largestexternallookupkeysize
,
3027 ugeth
->p_init_enet_param_shadow
->largestexternallookupkeysize
);
3028 out_be32(&p_init_enet_pram
->rgftgfrxglobal
,
3029 ugeth
->p_init_enet_param_shadow
->rgftgfrxglobal
);
3030 for (i
= 0; i
< ENET_INIT_PARAM_MAX_ENTRIES_RX
; i
++)
3031 out_be32(&p_init_enet_pram
->rxthread
[i
],
3032 ugeth
->p_init_enet_param_shadow
->rxthread
[i
]);
3033 out_be32(&p_init_enet_pram
->txglobal
,
3034 ugeth
->p_init_enet_param_shadow
->txglobal
);
3035 for (i
= 0; i
< ENET_INIT_PARAM_MAX_ENTRIES_TX
; i
++)
3036 out_be32(&p_init_enet_pram
->txthread
[i
],
3037 ugeth
->p_init_enet_param_shadow
->txthread
[i
]);
3039 /* Issue QE command */
3041 ucc_fast_get_qe_cr_subblock(ugeth
->ug_info
->uf_info
.ucc_num
);
3042 qe_issue_cmd(command
, cecr_subblock
, QE_CR_PROTOCOL_ETHERNET
,
3043 init_enet_pram_offset
);
3045 /* Free InitEnet command parameter */
3046 qe_muram_free(init_enet_pram_offset
);
3051 /* This is called by the kernel when a frame is ready for transmission. */
3052 /* It is pointed to by the dev->hard_start_xmit function pointer */
3053 static int ucc_geth_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
3055 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
3056 #ifdef CONFIG_UGETH_TX_ON_DEMAND
3057 struct ucc_fast_private
*uccf
;
3059 u8 __iomem
*bd
; /* BD pointer */
3063 ugeth_vdbg("%s: IN", __func__
);
3065 spin_lock_irq(&ugeth
->lock
);
3067 dev
->stats
.tx_bytes
+= skb
->len
;
3069 /* Start from the next BD that should be filled */
3070 bd
= ugeth
->txBd
[txQ
];
3071 bd_status
= in_be32((u32 __iomem
*)bd
);
3072 /* Save the skb pointer so we can free it later */
3073 ugeth
->tx_skbuff
[txQ
][ugeth
->skb_curtx
[txQ
]] = skb
;
3075 /* Update the current skb pointer (wrapping if this was the last) */
3076 ugeth
->skb_curtx
[txQ
] =
3077 (ugeth
->skb_curtx
[txQ
] +
3078 1) & TX_RING_MOD_MASK(ugeth
->ug_info
->bdRingLenTx
[txQ
]);
3080 /* set up the buffer descriptor */
3081 out_be32(&((struct qe_bd __iomem
*)bd
)->buf
,
3082 dma_map_single(ugeth
->dev
, skb
->data
,
3083 skb
->len
, DMA_TO_DEVICE
));
3085 /* printk(KERN_DEBUG"skb->data is 0x%x\n",skb->data); */
3087 bd_status
= (bd_status
& T_W
) | T_R
| T_I
| T_L
| skb
->len
;
3089 /* set bd status and length */
3090 out_be32((u32 __iomem
*)bd
, bd_status
);
3092 dev
->trans_start
= jiffies
;
3094 /* Move to next BD in the ring */
3095 if (!(bd_status
& T_W
))
3096 bd
+= sizeof(struct qe_bd
);
3098 bd
= ugeth
->p_tx_bd_ring
[txQ
];
3100 /* If the next BD still needs to be cleaned up, then the bds
3101 are full. We need to tell the kernel to stop sending us stuff. */
3102 if (bd
== ugeth
->confBd
[txQ
]) {
3103 if (!netif_queue_stopped(dev
))
3104 netif_stop_queue(dev
);
3107 ugeth
->txBd
[txQ
] = bd
;
3109 if (ugeth
->p_scheduler
) {
3110 ugeth
->cpucount
[txQ
]++;
3111 /* Indicate to QE that there are more Tx bds ready for
3113 /* This is done by writing a running counter of the bd
3114 count to the scheduler PRAM. */
3115 out_be16(ugeth
->p_cpucount
[txQ
], ugeth
->cpucount
[txQ
]);
3118 #ifdef CONFIG_UGETH_TX_ON_DEMAND
3120 out_be16(uccf
->p_utodr
, UCC_FAST_TOD
);
3122 spin_unlock_irq(&ugeth
->lock
);
3127 static int ucc_geth_rx(struct ucc_geth_private
*ugeth
, u8 rxQ
, int rx_work_limit
)
3129 struct sk_buff
*skb
;
3131 u16 length
, howmany
= 0;
3134 struct net_device
*dev
;
3136 ugeth_vdbg("%s: IN", __func__
);
3140 /* collect received buffers */
3141 bd
= ugeth
->rxBd
[rxQ
];
3143 bd_status
= in_be32((u32 __iomem
*)bd
);
3145 /* while there are received buffers and BD is full (~R_E) */
3146 while (!((bd_status
& (R_E
)) || (--rx_work_limit
< 0))) {
3147 bdBuffer
= (u8
*) in_be32(&((struct qe_bd __iomem
*)bd
)->buf
);
3148 length
= (u16
) ((bd_status
& BD_LENGTH_MASK
) - 4);
3149 skb
= ugeth
->rx_skbuff
[rxQ
][ugeth
->skb_currx
[rxQ
]];
3151 /* determine whether buffer is first, last, first and last
3152 (single buffer frame) or middle (not first and not last) */
3154 (!(bd_status
& (R_F
| R_L
))) ||
3155 (bd_status
& R_ERRORS_FATAL
)) {
3156 if (netif_msg_rx_err(ugeth
))
3157 ugeth_err("%s, %d: ERROR!!! skb - 0x%08x",
3158 __func__
, __LINE__
, (u32
) skb
);
3160 dev_kfree_skb_any(skb
);
3162 ugeth
->rx_skbuff
[rxQ
][ugeth
->skb_currx
[rxQ
]] = NULL
;
3163 dev
->stats
.rx_dropped
++;
3165 dev
->stats
.rx_packets
++;
3168 /* Prep the skb for the packet */
3169 skb_put(skb
, length
);
3171 /* Tell the skb what kind of packet this is */
3172 skb
->protocol
= eth_type_trans(skb
, ugeth
->ndev
);
3174 dev
->stats
.rx_bytes
+= length
;
3175 /* Send the packet up the stack */
3176 netif_receive_skb(skb
);
3179 skb
= get_new_skb(ugeth
, bd
);
3181 if (netif_msg_rx_err(ugeth
))
3182 ugeth_warn("%s: No Rx Data Buffer", __func__
);
3183 dev
->stats
.rx_dropped
++;
3187 ugeth
->rx_skbuff
[rxQ
][ugeth
->skb_currx
[rxQ
]] = skb
;
3189 /* update to point at the next skb */
3190 ugeth
->skb_currx
[rxQ
] =
3191 (ugeth
->skb_currx
[rxQ
] +
3192 1) & RX_RING_MOD_MASK(ugeth
->ug_info
->bdRingLenRx
[rxQ
]);
3194 if (bd_status
& R_W
)
3195 bd
= ugeth
->p_rx_bd_ring
[rxQ
];
3197 bd
+= sizeof(struct qe_bd
);
3199 bd_status
= in_be32((u32 __iomem
*)bd
);
3202 ugeth
->rxBd
[rxQ
] = bd
;
3206 static int ucc_geth_tx(struct net_device
*dev
, u8 txQ
)
3208 /* Start from the next BD that should be filled */
3209 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
3210 u8 __iomem
*bd
; /* BD pointer */
3213 bd
= ugeth
->confBd
[txQ
];
3214 bd_status
= in_be32((u32 __iomem
*)bd
);
3216 /* Normal processing. */
3217 while ((bd_status
& T_R
) == 0) {
3218 /* BD contains already transmitted buffer. */
3219 /* Handle the transmitted buffer and release */
3220 /* the BD to be used with the current frame */
3222 if ((bd
== ugeth
->txBd
[txQ
]) && (netif_queue_stopped(dev
) == 0))
3225 dev
->stats
.tx_packets
++;
3227 /* Free the sk buffer associated with this TxBD */
3228 dev_kfree_skb_irq(ugeth
->
3229 tx_skbuff
[txQ
][ugeth
->skb_dirtytx
[txQ
]]);
3230 ugeth
->tx_skbuff
[txQ
][ugeth
->skb_dirtytx
[txQ
]] = NULL
;
3231 ugeth
->skb_dirtytx
[txQ
] =
3232 (ugeth
->skb_dirtytx
[txQ
] +
3233 1) & TX_RING_MOD_MASK(ugeth
->ug_info
->bdRingLenTx
[txQ
]);
3235 /* We freed a buffer, so now we can restart transmission */
3236 if (netif_queue_stopped(dev
))
3237 netif_wake_queue(dev
);
3239 /* Advance the confirmation BD pointer */
3240 if (!(bd_status
& T_W
))
3241 bd
+= sizeof(struct qe_bd
);
3243 bd
= ugeth
->p_tx_bd_ring
[txQ
];
3244 bd_status
= in_be32((u32 __iomem
*)bd
);
3246 ugeth
->confBd
[txQ
] = bd
;
3250 static int ucc_geth_poll(struct napi_struct
*napi
, int budget
)
3252 struct ucc_geth_private
*ugeth
= container_of(napi
, struct ucc_geth_private
, napi
);
3253 struct ucc_geth_info
*ug_info
;
3256 ug_info
= ugeth
->ug_info
;
3259 for (i
= 0; i
< ug_info
->numQueuesRx
; i
++)
3260 howmany
+= ucc_geth_rx(ugeth
, i
, budget
- howmany
);
3262 if (howmany
< budget
) {
3263 napi_complete(napi
);
3264 setbits32(ugeth
->uccf
->p_uccm
, UCCE_RX_EVENTS
);
3270 static irqreturn_t
ucc_geth_irq_handler(int irq
, void *info
)
3272 struct net_device
*dev
= info
;
3273 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
3274 struct ucc_fast_private
*uccf
;
3275 struct ucc_geth_info
*ug_info
;
3278 register u32 tx_mask
;
3281 ugeth_vdbg("%s: IN", __func__
);
3284 ug_info
= ugeth
->ug_info
;
3286 /* read and clear events */
3287 ucce
= (u32
) in_be32(uccf
->p_ucce
);
3288 uccm
= (u32
) in_be32(uccf
->p_uccm
);
3290 out_be32(uccf
->p_ucce
, ucce
);
3292 /* check for receive events that require processing */
3293 if (ucce
& UCCE_RX_EVENTS
) {
3294 if (napi_schedule_prep(&ugeth
->napi
)) {
3295 uccm
&= ~UCCE_RX_EVENTS
;
3296 out_be32(uccf
->p_uccm
, uccm
);
3297 __napi_schedule(&ugeth
->napi
);
3301 /* Tx event processing */
3302 if (ucce
& UCCE_TX_EVENTS
) {
3303 spin_lock(&ugeth
->lock
);
3304 tx_mask
= UCC_GETH_UCCE_TXB0
;
3305 for (i
= 0; i
< ug_info
->numQueuesTx
; i
++) {
3307 ucc_geth_tx(dev
, i
);
3311 spin_unlock(&ugeth
->lock
);
3314 /* Errors and other events */
3315 if (ucce
& UCCE_OTHER
) {
3316 if (ucce
& UCC_GETH_UCCE_BSY
)
3317 dev
->stats
.rx_errors
++;
3318 if (ucce
& UCC_GETH_UCCE_TXE
)
3319 dev
->stats
.tx_errors
++;
3325 #ifdef CONFIG_NET_POLL_CONTROLLER
3327 * Polling 'interrupt' - used by things like netconsole to send skbs
3328 * without having to re-enable interrupts. It's not called while
3329 * the interrupt routine is executing.
3331 static void ucc_netpoll(struct net_device
*dev
)
3333 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
3334 int irq
= ugeth
->ug_info
->uf_info
.irq
;
3337 ucc_geth_irq_handler(irq
, dev
);
3340 #endif /* CONFIG_NET_POLL_CONTROLLER */
3342 /* Called when something needs to use the ethernet device */
3343 /* Returns 0 for success. */
3344 static int ucc_geth_open(struct net_device
*dev
)
3346 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
3349 ugeth_vdbg("%s: IN", __func__
);
3351 /* Test station address */
3352 if (dev
->dev_addr
[0] & ENET_GROUP_ADDR
) {
3353 if (netif_msg_ifup(ugeth
))
3354 ugeth_err("%s: Multicast address used for station address"
3355 " - is this what you wanted?", __func__
);
3359 err
= init_phy(dev
);
3361 if (netif_msg_ifup(ugeth
))
3362 ugeth_err("%s: Cannot initialize PHY, aborting.",
3367 err
= ucc_struct_init(ugeth
);
3369 if (netif_msg_ifup(ugeth
))
3370 ugeth_err("%s: Cannot configure internal struct, aborting.", dev
->name
);
3374 napi_enable(&ugeth
->napi
);
3376 err
= ucc_geth_startup(ugeth
);
3378 if (netif_msg_ifup(ugeth
))
3379 ugeth_err("%s: Cannot configure net device, aborting.",
3384 err
= adjust_enet_interface(ugeth
);
3386 if (netif_msg_ifup(ugeth
))
3387 ugeth_err("%s: Cannot configure net device, aborting.",
3392 /* Set MACSTNADDR1, MACSTNADDR2 */
3393 /* For more details see the hardware spec. */
3394 init_mac_station_addr_regs(dev
->dev_addr
[0],
3400 &ugeth
->ug_regs
->macstnaddr1
,
3401 &ugeth
->ug_regs
->macstnaddr2
);
3403 phy_start(ugeth
->phydev
);
3405 err
= ugeth_enable(ugeth
, COMM_DIR_RX_AND_TX
);
3407 if (netif_msg_ifup(ugeth
))
3408 ugeth_err("%s: Cannot enable net device, aborting.", dev
->name
);
3412 err
= request_irq(ugeth
->ug_info
->uf_info
.irq
, ucc_geth_irq_handler
,
3413 0, "UCC Geth", dev
);
3415 if (netif_msg_ifup(ugeth
))
3416 ugeth_err("%s: Cannot get IRQ for net device, aborting.",
3421 netif_start_queue(dev
);
3426 napi_disable(&ugeth
->napi
);
3428 ucc_geth_stop(ugeth
);
3432 /* Stops the kernel queue, and halts the controller */
3433 static int ucc_geth_close(struct net_device
*dev
)
3435 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
3437 ugeth_vdbg("%s: IN", __func__
);
3439 napi_disable(&ugeth
->napi
);
3441 ucc_geth_stop(ugeth
);
3443 free_irq(ugeth
->ug_info
->uf_info
.irq
, ugeth
->ndev
);
3445 netif_stop_queue(dev
);
3450 /* Reopen device. This will reset the MAC and PHY. */
3451 static void ucc_geth_timeout_work(struct work_struct
*work
)
3453 struct ucc_geth_private
*ugeth
;
3454 struct net_device
*dev
;
3456 ugeth
= container_of(work
, struct ucc_geth_private
, timeout_work
);
3459 ugeth_vdbg("%s: IN", __func__
);
3461 dev
->stats
.tx_errors
++;
3463 ugeth_dump_regs(ugeth
);
3465 if (dev
->flags
& IFF_UP
) {
3467 * Must reset MAC *and* PHY. This is done by reopening
3470 ucc_geth_close(dev
);
3474 netif_tx_schedule_all(dev
);
3478 * ucc_geth_timeout gets called when a packet has not been
3479 * transmitted after a set amount of time.
3481 static void ucc_geth_timeout(struct net_device
*dev
)
3483 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
3485 netif_carrier_off(dev
);
3486 schedule_work(&ugeth
->timeout_work
);
3489 static phy_interface_t
to_phy_interface(const char *phy_connection_type
)
3491 if (strcasecmp(phy_connection_type
, "mii") == 0)
3492 return PHY_INTERFACE_MODE_MII
;
3493 if (strcasecmp(phy_connection_type
, "gmii") == 0)
3494 return PHY_INTERFACE_MODE_GMII
;
3495 if (strcasecmp(phy_connection_type
, "tbi") == 0)
3496 return PHY_INTERFACE_MODE_TBI
;
3497 if (strcasecmp(phy_connection_type
, "rmii") == 0)
3498 return PHY_INTERFACE_MODE_RMII
;
3499 if (strcasecmp(phy_connection_type
, "rgmii") == 0)
3500 return PHY_INTERFACE_MODE_RGMII
;
3501 if (strcasecmp(phy_connection_type
, "rgmii-id") == 0)
3502 return PHY_INTERFACE_MODE_RGMII_ID
;
3503 if (strcasecmp(phy_connection_type
, "rgmii-txid") == 0)
3504 return PHY_INTERFACE_MODE_RGMII_TXID
;
3505 if (strcasecmp(phy_connection_type
, "rgmii-rxid") == 0)
3506 return PHY_INTERFACE_MODE_RGMII_RXID
;
3507 if (strcasecmp(phy_connection_type
, "rtbi") == 0)
3508 return PHY_INTERFACE_MODE_RTBI
;
3510 return PHY_INTERFACE_MODE_MII
;
3513 static const struct net_device_ops ucc_geth_netdev_ops
= {
3514 .ndo_open
= ucc_geth_open
,
3515 .ndo_stop
= ucc_geth_close
,
3516 .ndo_start_xmit
= ucc_geth_start_xmit
,
3517 .ndo_validate_addr
= eth_validate_addr
,
3518 .ndo_set_mac_address
= eth_mac_addr
,
3519 .ndo_change_mtu
= eth_change_mtu
,
3520 .ndo_set_multicast_list
= ucc_geth_set_multi
,
3521 .ndo_tx_timeout
= ucc_geth_timeout
,
3522 #ifdef CONFIG_NET_POLL_CONTROLLER
3523 .ndo_poll_controller
= ucc_netpoll
,
3527 static int ucc_geth_probe(struct of_device
* ofdev
, const struct of_device_id
*match
)
3529 struct device
*device
= &ofdev
->dev
;
3530 struct device_node
*np
= ofdev
->node
;
3531 struct device_node
*mdio
;
3532 struct net_device
*dev
= NULL
;
3533 struct ucc_geth_private
*ugeth
= NULL
;
3534 struct ucc_geth_info
*ug_info
;
3535 struct resource res
;
3536 struct device_node
*phy
;
3537 int err
, ucc_num
, max_speed
= 0;
3539 const u32
*fixed_link
;
3540 const unsigned int *prop
;
3542 const void *mac_addr
;
3543 phy_interface_t phy_interface
;
3544 static const int enet_to_speed
[] = {
3545 SPEED_10
, SPEED_10
, SPEED_10
,
3546 SPEED_100
, SPEED_100
, SPEED_100
,
3547 SPEED_1000
, SPEED_1000
, SPEED_1000
, SPEED_1000
,
3549 static const phy_interface_t enet_to_phy_interface
[] = {
3550 PHY_INTERFACE_MODE_MII
, PHY_INTERFACE_MODE_RMII
,
3551 PHY_INTERFACE_MODE_RGMII
, PHY_INTERFACE_MODE_MII
,
3552 PHY_INTERFACE_MODE_RMII
, PHY_INTERFACE_MODE_RGMII
,
3553 PHY_INTERFACE_MODE_GMII
, PHY_INTERFACE_MODE_RGMII
,
3554 PHY_INTERFACE_MODE_TBI
, PHY_INTERFACE_MODE_RTBI
,
3557 ugeth_vdbg("%s: IN", __func__
);
3559 prop
= of_get_property(np
, "cell-index", NULL
);
3561 prop
= of_get_property(np
, "device-id", NULL
);
3566 ucc_num
= *prop
- 1;
3567 if ((ucc_num
< 0) || (ucc_num
> 7))
3570 ug_info
= &ugeth_info
[ucc_num
];
3571 if (ug_info
== NULL
) {
3572 if (netif_msg_probe(&debug
))
3573 ugeth_err("%s: [%d] Missing additional data!",
3578 ug_info
->uf_info
.ucc_num
= ucc_num
;
3580 sprop
= of_get_property(np
, "rx-clock-name", NULL
);
3582 ug_info
->uf_info
.rx_clock
= qe_clock_source(sprop
);
3583 if ((ug_info
->uf_info
.rx_clock
< QE_CLK_NONE
) ||
3584 (ug_info
->uf_info
.rx_clock
> QE_CLK24
)) {
3586 "ucc_geth: invalid rx-clock-name property\n");
3590 prop
= of_get_property(np
, "rx-clock", NULL
);
3592 /* If both rx-clock-name and rx-clock are missing,
3593 we want to tell people to use rx-clock-name. */
3595 "ucc_geth: missing rx-clock-name property\n");
3598 if ((*prop
< QE_CLK_NONE
) || (*prop
> QE_CLK24
)) {
3600 "ucc_geth: invalid rx-clock propperty\n");
3603 ug_info
->uf_info
.rx_clock
= *prop
;
3606 sprop
= of_get_property(np
, "tx-clock-name", NULL
);
3608 ug_info
->uf_info
.tx_clock
= qe_clock_source(sprop
);
3609 if ((ug_info
->uf_info
.tx_clock
< QE_CLK_NONE
) ||
3610 (ug_info
->uf_info
.tx_clock
> QE_CLK24
)) {
3612 "ucc_geth: invalid tx-clock-name property\n");
3616 prop
= of_get_property(np
, "tx-clock", NULL
);
3619 "ucc_geth: mising tx-clock-name property\n");
3622 if ((*prop
< QE_CLK_NONE
) || (*prop
> QE_CLK24
)) {
3624 "ucc_geth: invalid tx-clock property\n");
3627 ug_info
->uf_info
.tx_clock
= *prop
;
3630 err
= of_address_to_resource(np
, 0, &res
);
3634 ug_info
->uf_info
.regs
= res
.start
;
3635 ug_info
->uf_info
.irq
= irq_of_parse_and_map(np
, 0);
3636 fixed_link
= of_get_property(np
, "fixed-link", NULL
);
3638 snprintf(ug_info
->phy_bus_id
, sizeof(ug_info
->phy_bus_id
),
3639 PHY_ID_FMT
, "0", fixed_link
[0]);
3642 char bus_name
[MII_BUS_ID_SIZE
];
3644 ph
= of_get_property(np
, "phy-handle", NULL
);
3645 phy
= of_find_node_by_phandle(*ph
);
3650 /* set the PHY address */
3651 prop
= of_get_property(phy
, "reg", NULL
);
3655 /* Set the bus id */
3656 mdio
= of_get_parent(phy
);
3661 err
= of_address_to_resource(mdio
, 0, &res
);
3667 fsl_pq_mdio_bus_name(bus_name
, mdio
);
3669 snprintf(ug_info
->phy_bus_id
, sizeof(ug_info
->phy_bus_id
),
3670 "%s:%02x", bus_name
, *prop
);
3673 /* get the phy interface type, or default to MII */
3674 prop
= of_get_property(np
, "phy-connection-type", NULL
);
3676 /* handle interface property present in old trees */
3677 prop
= of_get_property(phy
, "interface", NULL
);
3679 phy_interface
= enet_to_phy_interface
[*prop
];
3680 max_speed
= enet_to_speed
[*prop
];
3682 phy_interface
= PHY_INTERFACE_MODE_MII
;
3684 phy_interface
= to_phy_interface((const char *)prop
);
3687 /* get speed, or derive from PHY interface */
3689 switch (phy_interface
) {
3690 case PHY_INTERFACE_MODE_GMII
:
3691 case PHY_INTERFACE_MODE_RGMII
:
3692 case PHY_INTERFACE_MODE_RGMII_ID
:
3693 case PHY_INTERFACE_MODE_RGMII_RXID
:
3694 case PHY_INTERFACE_MODE_RGMII_TXID
:
3695 case PHY_INTERFACE_MODE_TBI
:
3696 case PHY_INTERFACE_MODE_RTBI
:
3697 max_speed
= SPEED_1000
;
3700 max_speed
= SPEED_100
;
3704 if (max_speed
== SPEED_1000
) {
3705 /* configure muram FIFOs for gigabit operation */
3706 ug_info
->uf_info
.urfs
= UCC_GETH_URFS_GIGA_INIT
;
3707 ug_info
->uf_info
.urfet
= UCC_GETH_URFET_GIGA_INIT
;
3708 ug_info
->uf_info
.urfset
= UCC_GETH_URFSET_GIGA_INIT
;
3709 ug_info
->uf_info
.utfs
= UCC_GETH_UTFS_GIGA_INIT
;
3710 ug_info
->uf_info
.utfet
= UCC_GETH_UTFET_GIGA_INIT
;
3711 ug_info
->uf_info
.utftt
= UCC_GETH_UTFTT_GIGA_INIT
;
3712 ug_info
->numThreadsTx
= UCC_GETH_NUM_OF_THREADS_4
;
3714 /* If QE's snum number is 46 which means we need to support
3715 * 4 UECs at 1000Base-T simultaneously, we need to allocate
3716 * more Threads to Rx.
3718 if (qe_get_num_of_snums() == 46)
3719 ug_info
->numThreadsRx
= UCC_GETH_NUM_OF_THREADS_6
;
3721 ug_info
->numThreadsRx
= UCC_GETH_NUM_OF_THREADS_4
;
3724 if (netif_msg_probe(&debug
))
3725 printk(KERN_INFO
"ucc_geth: UCC%1d at 0x%8x (irq = %d) \n",
3726 ug_info
->uf_info
.ucc_num
+ 1, ug_info
->uf_info
.regs
,
3727 ug_info
->uf_info
.irq
);
3729 /* Create an ethernet device instance */
3730 dev
= alloc_etherdev(sizeof(*ugeth
));
3735 ugeth
= netdev_priv(dev
);
3736 spin_lock_init(&ugeth
->lock
);
3738 /* Create CQs for hash tables */
3739 INIT_LIST_HEAD(&ugeth
->group_hash_q
);
3740 INIT_LIST_HEAD(&ugeth
->ind_hash_q
);
3742 dev_set_drvdata(device
, dev
);
3744 /* Set the dev->base_addr to the gfar reg region */
3745 dev
->base_addr
= (unsigned long)(ug_info
->uf_info
.regs
);
3747 SET_NETDEV_DEV(dev
, device
);
3749 /* Fill in the dev structure */
3750 uec_set_ethtool_ops(dev
);
3751 dev
->netdev_ops
= &ucc_geth_netdev_ops
;
3752 dev
->watchdog_timeo
= TX_TIMEOUT
;
3753 INIT_WORK(&ugeth
->timeout_work
, ucc_geth_timeout_work
);
3754 netif_napi_add(dev
, &ugeth
->napi
, ucc_geth_poll
, UCC_GETH_DEV_WEIGHT
);
3757 ugeth
->msg_enable
= netif_msg_init(debug
.msg_enable
, UGETH_MSG_DEFAULT
);
3758 ugeth
->phy_interface
= phy_interface
;
3759 ugeth
->max_speed
= max_speed
;
3761 err
= register_netdev(dev
);
3763 if (netif_msg_probe(ugeth
))
3764 ugeth_err("%s: Cannot register net device, aborting.",
3770 mac_addr
= of_get_mac_address(np
);
3772 memcpy(dev
->dev_addr
, mac_addr
, 6);
3774 ugeth
->ug_info
= ug_info
;
3775 ugeth
->dev
= device
;
3782 static int ucc_geth_remove(struct of_device
* ofdev
)
3784 struct device
*device
= &ofdev
->dev
;
3785 struct net_device
*dev
= dev_get_drvdata(device
);
3786 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
3788 unregister_netdev(dev
);
3790 ucc_geth_memclean(ugeth
);
3791 dev_set_drvdata(device
, NULL
);
3796 static struct of_device_id ucc_geth_match
[] = {
3799 .compatible
= "ucc_geth",
3804 MODULE_DEVICE_TABLE(of
, ucc_geth_match
);
3806 static struct of_platform_driver ucc_geth_driver
= {
3808 .match_table
= ucc_geth_match
,
3809 .probe
= ucc_geth_probe
,
3810 .remove
= ucc_geth_remove
,
3813 static int __init
ucc_geth_init(void)
3817 if (netif_msg_drv(&debug
))
3818 printk(KERN_INFO
"ucc_geth: " DRV_DESC
"\n");
3819 for (i
= 0; i
< 8; i
++)
3820 memcpy(&(ugeth_info
[i
]), &ugeth_primary_info
,
3821 sizeof(ugeth_primary_info
));
3823 ret
= of_register_platform_driver(&ucc_geth_driver
);
3828 static void __exit
ucc_geth_exit(void)
3830 of_unregister_platform_driver(&ucc_geth_driver
);
3833 module_init(ucc_geth_init
);
3834 module_exit(ucc_geth_exit
);
3836 MODULE_AUTHOR("Freescale Semiconductor, Inc");
3837 MODULE_DESCRIPTION(DRV_DESC
);
3838 MODULE_VERSION(DRV_VERSION
);
3839 MODULE_LICENSE("GPL");