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ucc_geth: Rearrange some code to avoid forward declarations
[deliverable/linux.git] / drivers / net / ucc_geth.c
1 /*
2 * Copyright (C) 2006-2009 Freescale Semicondutor, Inc. All rights reserved.
3 *
4 * Author: Shlomi Gridish <gridish@freescale.com>
5 * Li Yang <leoli@freescale.com>
6 *
7 * Description:
8 * QE UCC Gigabit Ethernet Driver
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/errno.h>
18 #include <linux/slab.h>
19 #include <linux/stddef.h>
20 #include <linux/interrupt.h>
21 #include <linux/netdevice.h>
22 #include <linux/etherdevice.h>
23 #include <linux/skbuff.h>
24 #include <linux/spinlock.h>
25 #include <linux/mm.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/mii.h>
28 #include <linux/phy.h>
29 #include <linux/workqueue.h>
30 #include <linux/of_mdio.h>
31 #include <linux/of_platform.h>
32
33 #include <asm/uaccess.h>
34 #include <asm/irq.h>
35 #include <asm/io.h>
36 #include <asm/immap_qe.h>
37 #include <asm/qe.h>
38 #include <asm/ucc.h>
39 #include <asm/ucc_fast.h>
40
41 #include "ucc_geth.h"
42 #include "fsl_pq_mdio.h"
43
44 #undef DEBUG
45
46 #define ugeth_printk(level, format, arg...) \
47 printk(level format "\n", ## arg)
48
49 #define ugeth_dbg(format, arg...) \
50 ugeth_printk(KERN_DEBUG , format , ## arg)
51 #define ugeth_err(format, arg...) \
52 ugeth_printk(KERN_ERR , format , ## arg)
53 #define ugeth_info(format, arg...) \
54 ugeth_printk(KERN_INFO , format , ## arg)
55 #define ugeth_warn(format, arg...) \
56 ugeth_printk(KERN_WARNING , format , ## arg)
57
58 #ifdef UGETH_VERBOSE_DEBUG
59 #define ugeth_vdbg ugeth_dbg
60 #else
61 #define ugeth_vdbg(fmt, args...) do { } while (0)
62 #endif /* UGETH_VERBOSE_DEBUG */
63 #define UGETH_MSG_DEFAULT (NETIF_MSG_IFUP << 1 ) - 1
64
65
66 static DEFINE_SPINLOCK(ugeth_lock);
67
68 static struct {
69 u32 msg_enable;
70 } debug = { -1 };
71
72 module_param_named(debug, debug.msg_enable, int, 0);
73 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 0xffff=all)");
74
75 static struct ucc_geth_info ugeth_primary_info = {
76 .uf_info = {
77 .bd_mem_part = MEM_PART_SYSTEM,
78 .rtsm = UCC_FAST_SEND_IDLES_BETWEEN_FRAMES,
79 .max_rx_buf_length = 1536,
80 /* adjusted at startup if max-speed 1000 */
81 .urfs = UCC_GETH_URFS_INIT,
82 .urfet = UCC_GETH_URFET_INIT,
83 .urfset = UCC_GETH_URFSET_INIT,
84 .utfs = UCC_GETH_UTFS_INIT,
85 .utfet = UCC_GETH_UTFET_INIT,
86 .utftt = UCC_GETH_UTFTT_INIT,
87 .ufpt = 256,
88 .mode = UCC_FAST_PROTOCOL_MODE_ETHERNET,
89 .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL,
90 .tenc = UCC_FAST_TX_ENCODING_NRZ,
91 .renc = UCC_FAST_RX_ENCODING_NRZ,
92 .tcrc = UCC_FAST_16_BIT_CRC,
93 .synl = UCC_FAST_SYNC_LEN_NOT_USED,
94 },
95 .numQueuesTx = 1,
96 .numQueuesRx = 1,
97 .extendedFilteringChainPointer = ((uint32_t) NULL),
98 .typeorlen = 3072 /*1536 */ ,
99 .nonBackToBackIfgPart1 = 0x40,
100 .nonBackToBackIfgPart2 = 0x60,
101 .miminumInterFrameGapEnforcement = 0x50,
102 .backToBackInterFrameGap = 0x60,
103 .mblinterval = 128,
104 .nortsrbytetime = 5,
105 .fracsiz = 1,
106 .strictpriorityq = 0xff,
107 .altBebTruncation = 0xa,
108 .excessDefer = 1,
109 .maxRetransmission = 0xf,
110 .collisionWindow = 0x37,
111 .receiveFlowControl = 1,
112 .transmitFlowControl = 1,
113 .maxGroupAddrInHash = 4,
114 .maxIndAddrInHash = 4,
115 .prel = 7,
116 .maxFrameLength = 1518,
117 .minFrameLength = 64,
118 .maxD1Length = 1520,
119 .maxD2Length = 1520,
120 .vlantype = 0x8100,
121 .ecamptr = ((uint32_t) NULL),
122 .eventRegMask = UCCE_OTHER,
123 .pausePeriod = 0xf000,
124 .interruptcoalescingmaxvalue = {1, 1, 1, 1, 1, 1, 1, 1},
125 .bdRingLenTx = {
126 TX_BD_RING_LEN,
127 TX_BD_RING_LEN,
128 TX_BD_RING_LEN,
129 TX_BD_RING_LEN,
130 TX_BD_RING_LEN,
131 TX_BD_RING_LEN,
132 TX_BD_RING_LEN,
133 TX_BD_RING_LEN},
134
135 .bdRingLenRx = {
136 RX_BD_RING_LEN,
137 RX_BD_RING_LEN,
138 RX_BD_RING_LEN,
139 RX_BD_RING_LEN,
140 RX_BD_RING_LEN,
141 RX_BD_RING_LEN,
142 RX_BD_RING_LEN,
143 RX_BD_RING_LEN},
144
145 .numStationAddresses = UCC_GETH_NUM_OF_STATION_ADDRESSES_1,
146 .largestexternallookupkeysize =
147 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE,
148 .statisticsMode = UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE |
149 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX |
150 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX,
151 .vlanOperationTagged = UCC_GETH_VLAN_OPERATION_TAGGED_NOP,
152 .vlanOperationNonTagged = UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP,
153 .rxQoSMode = UCC_GETH_QOS_MODE_DEFAULT,
154 .aufc = UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE,
155 .padAndCrc = MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC,
156 .numThreadsTx = UCC_GETH_NUM_OF_THREADS_1,
157 .numThreadsRx = UCC_GETH_NUM_OF_THREADS_1,
158 .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
159 .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
160 };
161
162 static struct ucc_geth_info ugeth_info[8];
163
164 #ifdef DEBUG
165 static void mem_disp(u8 *addr, int size)
166 {
167 u8 *i;
168 int size16Aling = (size >> 4) << 4;
169 int size4Aling = (size >> 2) << 2;
170 int notAlign = 0;
171 if (size % 16)
172 notAlign = 1;
173
174 for (i = addr; (u32) i < (u32) addr + size16Aling; i += 16)
175 printk("0x%08x: %08x %08x %08x %08x\r\n",
176 (u32) i,
177 *((u32 *) (i)),
178 *((u32 *) (i + 4)),
179 *((u32 *) (i + 8)), *((u32 *) (i + 12)));
180 if (notAlign == 1)
181 printk("0x%08x: ", (u32) i);
182 for (; (u32) i < (u32) addr + size4Aling; i += 4)
183 printk("%08x ", *((u32 *) (i)));
184 for (; (u32) i < (u32) addr + size; i++)
185 printk("%02x", *((u8 *) (i)));
186 if (notAlign == 1)
187 printk("\r\n");
188 }
189 #endif /* DEBUG */
190
191 static struct list_head *dequeue(struct list_head *lh)
192 {
193 unsigned long flags;
194
195 spin_lock_irqsave(&ugeth_lock, flags);
196 if (!list_empty(lh)) {
197 struct list_head *node = lh->next;
198 list_del(node);
199 spin_unlock_irqrestore(&ugeth_lock, flags);
200 return node;
201 } else {
202 spin_unlock_irqrestore(&ugeth_lock, flags);
203 return NULL;
204 }
205 }
206
207 static struct sk_buff *get_new_skb(struct ucc_geth_private *ugeth,
208 u8 __iomem *bd)
209 {
210 struct sk_buff *skb = NULL;
211
212 skb = __skb_dequeue(&ugeth->rx_recycle);
213 if (!skb)
214 skb = dev_alloc_skb(ugeth->ug_info->uf_info.max_rx_buf_length +
215 UCC_GETH_RX_DATA_BUF_ALIGNMENT);
216 if (skb == NULL)
217 return NULL;
218
219 /* We need the data buffer to be aligned properly. We will reserve
220 * as many bytes as needed to align the data properly
221 */
222 skb_reserve(skb,
223 UCC_GETH_RX_DATA_BUF_ALIGNMENT -
224 (((unsigned)skb->data) & (UCC_GETH_RX_DATA_BUF_ALIGNMENT -
225 1)));
226
227 skb->dev = ugeth->ndev;
228
229 out_be32(&((struct qe_bd __iomem *)bd)->buf,
230 dma_map_single(ugeth->dev,
231 skb->data,
232 ugeth->ug_info->uf_info.max_rx_buf_length +
233 UCC_GETH_RX_DATA_BUF_ALIGNMENT,
234 DMA_FROM_DEVICE));
235
236 out_be32((u32 __iomem *)bd,
237 (R_E | R_I | (in_be32((u32 __iomem*)bd) & R_W)));
238
239 return skb;
240 }
241
242 static int rx_bd_buffer_set(struct ucc_geth_private *ugeth, u8 rxQ)
243 {
244 u8 __iomem *bd;
245 u32 bd_status;
246 struct sk_buff *skb;
247 int i;
248
249 bd = ugeth->p_rx_bd_ring[rxQ];
250 i = 0;
251
252 do {
253 bd_status = in_be32((u32 __iomem *)bd);
254 skb = get_new_skb(ugeth, bd);
255
256 if (!skb) /* If can not allocate data buffer,
257 abort. Cleanup will be elsewhere */
258 return -ENOMEM;
259
260 ugeth->rx_skbuff[rxQ][i] = skb;
261
262 /* advance the BD pointer */
263 bd += sizeof(struct qe_bd);
264 i++;
265 } while (!(bd_status & R_W));
266
267 return 0;
268 }
269
270 static int fill_init_enet_entries(struct ucc_geth_private *ugeth,
271 u32 *p_start,
272 u8 num_entries,
273 u32 thread_size,
274 u32 thread_alignment,
275 unsigned int risc,
276 int skip_page_for_first_entry)
277 {
278 u32 init_enet_offset;
279 u8 i;
280 int snum;
281
282 for (i = 0; i < num_entries; i++) {
283 if ((snum = qe_get_snum()) < 0) {
284 if (netif_msg_ifup(ugeth))
285 ugeth_err("fill_init_enet_entries: Can not get SNUM.");
286 return snum;
287 }
288 if ((i == 0) && skip_page_for_first_entry)
289 /* First entry of Rx does not have page */
290 init_enet_offset = 0;
291 else {
292 init_enet_offset =
293 qe_muram_alloc(thread_size, thread_alignment);
294 if (IS_ERR_VALUE(init_enet_offset)) {
295 if (netif_msg_ifup(ugeth))
296 ugeth_err("fill_init_enet_entries: Can not allocate DPRAM memory.");
297 qe_put_snum((u8) snum);
298 return -ENOMEM;
299 }
300 }
301 *(p_start++) =
302 ((u8) snum << ENET_INIT_PARAM_SNUM_SHIFT) | init_enet_offset
303 | risc;
304 }
305
306 return 0;
307 }
308
309 static int return_init_enet_entries(struct ucc_geth_private *ugeth,
310 u32 *p_start,
311 u8 num_entries,
312 unsigned int risc,
313 int skip_page_for_first_entry)
314 {
315 u32 init_enet_offset;
316 u8 i;
317 int snum;
318
319 for (i = 0; i < num_entries; i++) {
320 u32 val = *p_start;
321
322 /* Check that this entry was actually valid --
323 needed in case failed in allocations */
324 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) {
325 snum =
326 (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >>
327 ENET_INIT_PARAM_SNUM_SHIFT;
328 qe_put_snum((u8) snum);
329 if (!((i == 0) && skip_page_for_first_entry)) {
330 /* First entry of Rx does not have page */
331 init_enet_offset =
332 (val & ENET_INIT_PARAM_PTR_MASK);
333 qe_muram_free(init_enet_offset);
334 }
335 *p_start++ = 0;
336 }
337 }
338
339 return 0;
340 }
341
342 #ifdef DEBUG
343 static int dump_init_enet_entries(struct ucc_geth_private *ugeth,
344 u32 __iomem *p_start,
345 u8 num_entries,
346 u32 thread_size,
347 unsigned int risc,
348 int skip_page_for_first_entry)
349 {
350 u32 init_enet_offset;
351 u8 i;
352 int snum;
353
354 for (i = 0; i < num_entries; i++) {
355 u32 val = in_be32(p_start);
356
357 /* Check that this entry was actually valid --
358 needed in case failed in allocations */
359 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) {
360 snum =
361 (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >>
362 ENET_INIT_PARAM_SNUM_SHIFT;
363 qe_put_snum((u8) snum);
364 if (!((i == 0) && skip_page_for_first_entry)) {
365 /* First entry of Rx does not have page */
366 init_enet_offset =
367 (in_be32(p_start) &
368 ENET_INIT_PARAM_PTR_MASK);
369 ugeth_info("Init enet entry %d:", i);
370 ugeth_info("Base address: 0x%08x",
371 (u32)
372 qe_muram_addr(init_enet_offset));
373 mem_disp(qe_muram_addr(init_enet_offset),
374 thread_size);
375 }
376 p_start++;
377 }
378 }
379
380 return 0;
381 }
382 #endif
383
384 static void put_enet_addr_container(struct enet_addr_container *enet_addr_cont)
385 {
386 kfree(enet_addr_cont);
387 }
388
389 static void set_mac_addr(__be16 __iomem *reg, u8 *mac)
390 {
391 out_be16(&reg[0], ((u16)mac[5] << 8) | mac[4]);
392 out_be16(&reg[1], ((u16)mac[3] << 8) | mac[2]);
393 out_be16(&reg[2], ((u16)mac[1] << 8) | mac[0]);
394 }
395
396 static int hw_clear_addr_in_paddr(struct ucc_geth_private *ugeth, u8 paddr_num)
397 {
398 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
399
400 if (!(paddr_num < NUM_OF_PADDRS)) {
401 ugeth_warn("%s: Illagel paddr_num.", __func__);
402 return -EINVAL;
403 }
404
405 p_82xx_addr_filt =
406 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram->
407 addressfiltering;
408
409 /* Writing address ff.ff.ff.ff.ff.ff disables address
410 recognition for this register */
411 out_be16(&p_82xx_addr_filt->paddr[paddr_num].h, 0xffff);
412 out_be16(&p_82xx_addr_filt->paddr[paddr_num].m, 0xffff);
413 out_be16(&p_82xx_addr_filt->paddr[paddr_num].l, 0xffff);
414
415 return 0;
416 }
417
418 static void hw_add_addr_in_hash(struct ucc_geth_private *ugeth,
419 u8 *p_enet_addr)
420 {
421 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
422 u32 cecr_subblock;
423
424 p_82xx_addr_filt =
425 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram->
426 addressfiltering;
427
428 cecr_subblock =
429 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
430
431 /* Ethernet frames are defined in Little Endian mode,
432 therefor to insert */
433 /* the address to the hash (Big Endian mode), we reverse the bytes.*/
434
435 set_mac_addr(&p_82xx_addr_filt->taddr.h, p_enet_addr);
436
437 qe_issue_cmd(QE_SET_GROUP_ADDRESS, cecr_subblock,
438 QE_CR_PROTOCOL_ETHERNET, 0);
439 }
440
441 static inline int compare_addr(u8 **addr1, u8 **addr2)
442 {
443 return memcmp(addr1, addr2, ENET_NUM_OCTETS_PER_ADDRESS);
444 }
445
446 #ifdef DEBUG
447 static void get_statistics(struct ucc_geth_private *ugeth,
448 struct ucc_geth_tx_firmware_statistics *
449 tx_firmware_statistics,
450 struct ucc_geth_rx_firmware_statistics *
451 rx_firmware_statistics,
452 struct ucc_geth_hardware_statistics *hardware_statistics)
453 {
454 struct ucc_fast __iomem *uf_regs;
455 struct ucc_geth __iomem *ug_regs;
456 struct ucc_geth_tx_firmware_statistics_pram *p_tx_fw_statistics_pram;
457 struct ucc_geth_rx_firmware_statistics_pram *p_rx_fw_statistics_pram;
458
459 ug_regs = ugeth->ug_regs;
460 uf_regs = (struct ucc_fast __iomem *) ug_regs;
461 p_tx_fw_statistics_pram = ugeth->p_tx_fw_statistics_pram;
462 p_rx_fw_statistics_pram = ugeth->p_rx_fw_statistics_pram;
463
464 /* Tx firmware only if user handed pointer and driver actually
465 gathers Tx firmware statistics */
466 if (tx_firmware_statistics && p_tx_fw_statistics_pram) {
467 tx_firmware_statistics->sicoltx =
468 in_be32(&p_tx_fw_statistics_pram->sicoltx);
469 tx_firmware_statistics->mulcoltx =
470 in_be32(&p_tx_fw_statistics_pram->mulcoltx);
471 tx_firmware_statistics->latecoltxfr =
472 in_be32(&p_tx_fw_statistics_pram->latecoltxfr);
473 tx_firmware_statistics->frabortduecol =
474 in_be32(&p_tx_fw_statistics_pram->frabortduecol);
475 tx_firmware_statistics->frlostinmactxer =
476 in_be32(&p_tx_fw_statistics_pram->frlostinmactxer);
477 tx_firmware_statistics->carriersenseertx =
478 in_be32(&p_tx_fw_statistics_pram->carriersenseertx);
479 tx_firmware_statistics->frtxok =
480 in_be32(&p_tx_fw_statistics_pram->frtxok);
481 tx_firmware_statistics->txfrexcessivedefer =
482 in_be32(&p_tx_fw_statistics_pram->txfrexcessivedefer);
483 tx_firmware_statistics->txpkts256 =
484 in_be32(&p_tx_fw_statistics_pram->txpkts256);
485 tx_firmware_statistics->txpkts512 =
486 in_be32(&p_tx_fw_statistics_pram->txpkts512);
487 tx_firmware_statistics->txpkts1024 =
488 in_be32(&p_tx_fw_statistics_pram->txpkts1024);
489 tx_firmware_statistics->txpktsjumbo =
490 in_be32(&p_tx_fw_statistics_pram->txpktsjumbo);
491 }
492
493 /* Rx firmware only if user handed pointer and driver actually
494 * gathers Rx firmware statistics */
495 if (rx_firmware_statistics && p_rx_fw_statistics_pram) {
496 int i;
497 rx_firmware_statistics->frrxfcser =
498 in_be32(&p_rx_fw_statistics_pram->frrxfcser);
499 rx_firmware_statistics->fraligner =
500 in_be32(&p_rx_fw_statistics_pram->fraligner);
501 rx_firmware_statistics->inrangelenrxer =
502 in_be32(&p_rx_fw_statistics_pram->inrangelenrxer);
503 rx_firmware_statistics->outrangelenrxer =
504 in_be32(&p_rx_fw_statistics_pram->outrangelenrxer);
505 rx_firmware_statistics->frtoolong =
506 in_be32(&p_rx_fw_statistics_pram->frtoolong);
507 rx_firmware_statistics->runt =
508 in_be32(&p_rx_fw_statistics_pram->runt);
509 rx_firmware_statistics->verylongevent =
510 in_be32(&p_rx_fw_statistics_pram->verylongevent);
511 rx_firmware_statistics->symbolerror =
512 in_be32(&p_rx_fw_statistics_pram->symbolerror);
513 rx_firmware_statistics->dropbsy =
514 in_be32(&p_rx_fw_statistics_pram->dropbsy);
515 for (i = 0; i < 0x8; i++)
516 rx_firmware_statistics->res0[i] =
517 p_rx_fw_statistics_pram->res0[i];
518 rx_firmware_statistics->mismatchdrop =
519 in_be32(&p_rx_fw_statistics_pram->mismatchdrop);
520 rx_firmware_statistics->underpkts =
521 in_be32(&p_rx_fw_statistics_pram->underpkts);
522 rx_firmware_statistics->pkts256 =
523 in_be32(&p_rx_fw_statistics_pram->pkts256);
524 rx_firmware_statistics->pkts512 =
525 in_be32(&p_rx_fw_statistics_pram->pkts512);
526 rx_firmware_statistics->pkts1024 =
527 in_be32(&p_rx_fw_statistics_pram->pkts1024);
528 rx_firmware_statistics->pktsjumbo =
529 in_be32(&p_rx_fw_statistics_pram->pktsjumbo);
530 rx_firmware_statistics->frlossinmacer =
531 in_be32(&p_rx_fw_statistics_pram->frlossinmacer);
532 rx_firmware_statistics->pausefr =
533 in_be32(&p_rx_fw_statistics_pram->pausefr);
534 for (i = 0; i < 0x4; i++)
535 rx_firmware_statistics->res1[i] =
536 p_rx_fw_statistics_pram->res1[i];
537 rx_firmware_statistics->removevlan =
538 in_be32(&p_rx_fw_statistics_pram->removevlan);
539 rx_firmware_statistics->replacevlan =
540 in_be32(&p_rx_fw_statistics_pram->replacevlan);
541 rx_firmware_statistics->insertvlan =
542 in_be32(&p_rx_fw_statistics_pram->insertvlan);
543 }
544
545 /* Hardware only if user handed pointer and driver actually
546 gathers hardware statistics */
547 if (hardware_statistics &&
548 (in_be32(&uf_regs->upsmr) & UCC_GETH_UPSMR_HSE)) {
549 hardware_statistics->tx64 = in_be32(&ug_regs->tx64);
550 hardware_statistics->tx127 = in_be32(&ug_regs->tx127);
551 hardware_statistics->tx255 = in_be32(&ug_regs->tx255);
552 hardware_statistics->rx64 = in_be32(&ug_regs->rx64);
553 hardware_statistics->rx127 = in_be32(&ug_regs->rx127);
554 hardware_statistics->rx255 = in_be32(&ug_regs->rx255);
555 hardware_statistics->txok = in_be32(&ug_regs->txok);
556 hardware_statistics->txcf = in_be16(&ug_regs->txcf);
557 hardware_statistics->tmca = in_be32(&ug_regs->tmca);
558 hardware_statistics->tbca = in_be32(&ug_regs->tbca);
559 hardware_statistics->rxfok = in_be32(&ug_regs->rxfok);
560 hardware_statistics->rxbok = in_be32(&ug_regs->rxbok);
561 hardware_statistics->rbyt = in_be32(&ug_regs->rbyt);
562 hardware_statistics->rmca = in_be32(&ug_regs->rmca);
563 hardware_statistics->rbca = in_be32(&ug_regs->rbca);
564 }
565 }
566
567 static void dump_bds(struct ucc_geth_private *ugeth)
568 {
569 int i;
570 int length;
571
572 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
573 if (ugeth->p_tx_bd_ring[i]) {
574 length =
575 (ugeth->ug_info->bdRingLenTx[i] *
576 sizeof(struct qe_bd));
577 ugeth_info("TX BDs[%d]", i);
578 mem_disp(ugeth->p_tx_bd_ring[i], length);
579 }
580 }
581 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
582 if (ugeth->p_rx_bd_ring[i]) {
583 length =
584 (ugeth->ug_info->bdRingLenRx[i] *
585 sizeof(struct qe_bd));
586 ugeth_info("RX BDs[%d]", i);
587 mem_disp(ugeth->p_rx_bd_ring[i], length);
588 }
589 }
590 }
591
592 static void dump_regs(struct ucc_geth_private *ugeth)
593 {
594 int i;
595
596 ugeth_info("UCC%d Geth registers:", ugeth->ug_info->uf_info.ucc_num);
597 ugeth_info("Base address: 0x%08x", (u32) ugeth->ug_regs);
598
599 ugeth_info("maccfg1 : addr - 0x%08x, val - 0x%08x",
600 (u32) & ugeth->ug_regs->maccfg1,
601 in_be32(&ugeth->ug_regs->maccfg1));
602 ugeth_info("maccfg2 : addr - 0x%08x, val - 0x%08x",
603 (u32) & ugeth->ug_regs->maccfg2,
604 in_be32(&ugeth->ug_regs->maccfg2));
605 ugeth_info("ipgifg : addr - 0x%08x, val - 0x%08x",
606 (u32) & ugeth->ug_regs->ipgifg,
607 in_be32(&ugeth->ug_regs->ipgifg));
608 ugeth_info("hafdup : addr - 0x%08x, val - 0x%08x",
609 (u32) & ugeth->ug_regs->hafdup,
610 in_be32(&ugeth->ug_regs->hafdup));
611 ugeth_info("ifctl : addr - 0x%08x, val - 0x%08x",
612 (u32) & ugeth->ug_regs->ifctl,
613 in_be32(&ugeth->ug_regs->ifctl));
614 ugeth_info("ifstat : addr - 0x%08x, val - 0x%08x",
615 (u32) & ugeth->ug_regs->ifstat,
616 in_be32(&ugeth->ug_regs->ifstat));
617 ugeth_info("macstnaddr1: addr - 0x%08x, val - 0x%08x",
618 (u32) & ugeth->ug_regs->macstnaddr1,
619 in_be32(&ugeth->ug_regs->macstnaddr1));
620 ugeth_info("macstnaddr2: addr - 0x%08x, val - 0x%08x",
621 (u32) & ugeth->ug_regs->macstnaddr2,
622 in_be32(&ugeth->ug_regs->macstnaddr2));
623 ugeth_info("uempr : addr - 0x%08x, val - 0x%08x",
624 (u32) & ugeth->ug_regs->uempr,
625 in_be32(&ugeth->ug_regs->uempr));
626 ugeth_info("utbipar : addr - 0x%08x, val - 0x%08x",
627 (u32) & ugeth->ug_regs->utbipar,
628 in_be32(&ugeth->ug_regs->utbipar));
629 ugeth_info("uescr : addr - 0x%08x, val - 0x%04x",
630 (u32) & ugeth->ug_regs->uescr,
631 in_be16(&ugeth->ug_regs->uescr));
632 ugeth_info("tx64 : addr - 0x%08x, val - 0x%08x",
633 (u32) & ugeth->ug_regs->tx64,
634 in_be32(&ugeth->ug_regs->tx64));
635 ugeth_info("tx127 : addr - 0x%08x, val - 0x%08x",
636 (u32) & ugeth->ug_regs->tx127,
637 in_be32(&ugeth->ug_regs->tx127));
638 ugeth_info("tx255 : addr - 0x%08x, val - 0x%08x",
639 (u32) & ugeth->ug_regs->tx255,
640 in_be32(&ugeth->ug_regs->tx255));
641 ugeth_info("rx64 : addr - 0x%08x, val - 0x%08x",
642 (u32) & ugeth->ug_regs->rx64,
643 in_be32(&ugeth->ug_regs->rx64));
644 ugeth_info("rx127 : addr - 0x%08x, val - 0x%08x",
645 (u32) & ugeth->ug_regs->rx127,
646 in_be32(&ugeth->ug_regs->rx127));
647 ugeth_info("rx255 : addr - 0x%08x, val - 0x%08x",
648 (u32) & ugeth->ug_regs->rx255,
649 in_be32(&ugeth->ug_regs->rx255));
650 ugeth_info("txok : addr - 0x%08x, val - 0x%08x",
651 (u32) & ugeth->ug_regs->txok,
652 in_be32(&ugeth->ug_regs->txok));
653 ugeth_info("txcf : addr - 0x%08x, val - 0x%04x",
654 (u32) & ugeth->ug_regs->txcf,
655 in_be16(&ugeth->ug_regs->txcf));
656 ugeth_info("tmca : addr - 0x%08x, val - 0x%08x",
657 (u32) & ugeth->ug_regs->tmca,
658 in_be32(&ugeth->ug_regs->tmca));
659 ugeth_info("tbca : addr - 0x%08x, val - 0x%08x",
660 (u32) & ugeth->ug_regs->tbca,
661 in_be32(&ugeth->ug_regs->tbca));
662 ugeth_info("rxfok : addr - 0x%08x, val - 0x%08x",
663 (u32) & ugeth->ug_regs->rxfok,
664 in_be32(&ugeth->ug_regs->rxfok));
665 ugeth_info("rxbok : addr - 0x%08x, val - 0x%08x",
666 (u32) & ugeth->ug_regs->rxbok,
667 in_be32(&ugeth->ug_regs->rxbok));
668 ugeth_info("rbyt : addr - 0x%08x, val - 0x%08x",
669 (u32) & ugeth->ug_regs->rbyt,
670 in_be32(&ugeth->ug_regs->rbyt));
671 ugeth_info("rmca : addr - 0x%08x, val - 0x%08x",
672 (u32) & ugeth->ug_regs->rmca,
673 in_be32(&ugeth->ug_regs->rmca));
674 ugeth_info("rbca : addr - 0x%08x, val - 0x%08x",
675 (u32) & ugeth->ug_regs->rbca,
676 in_be32(&ugeth->ug_regs->rbca));
677 ugeth_info("scar : addr - 0x%08x, val - 0x%08x",
678 (u32) & ugeth->ug_regs->scar,
679 in_be32(&ugeth->ug_regs->scar));
680 ugeth_info("scam : addr - 0x%08x, val - 0x%08x",
681 (u32) & ugeth->ug_regs->scam,
682 in_be32(&ugeth->ug_regs->scam));
683
684 if (ugeth->p_thread_data_tx) {
685 int numThreadsTxNumerical;
686 switch (ugeth->ug_info->numThreadsTx) {
687 case UCC_GETH_NUM_OF_THREADS_1:
688 numThreadsTxNumerical = 1;
689 break;
690 case UCC_GETH_NUM_OF_THREADS_2:
691 numThreadsTxNumerical = 2;
692 break;
693 case UCC_GETH_NUM_OF_THREADS_4:
694 numThreadsTxNumerical = 4;
695 break;
696 case UCC_GETH_NUM_OF_THREADS_6:
697 numThreadsTxNumerical = 6;
698 break;
699 case UCC_GETH_NUM_OF_THREADS_8:
700 numThreadsTxNumerical = 8;
701 break;
702 default:
703 numThreadsTxNumerical = 0;
704 break;
705 }
706
707 ugeth_info("Thread data TXs:");
708 ugeth_info("Base address: 0x%08x",
709 (u32) ugeth->p_thread_data_tx);
710 for (i = 0; i < numThreadsTxNumerical; i++) {
711 ugeth_info("Thread data TX[%d]:", i);
712 ugeth_info("Base address: 0x%08x",
713 (u32) & ugeth->p_thread_data_tx[i]);
714 mem_disp((u8 *) & ugeth->p_thread_data_tx[i],
715 sizeof(struct ucc_geth_thread_data_tx));
716 }
717 }
718 if (ugeth->p_thread_data_rx) {
719 int numThreadsRxNumerical;
720 switch (ugeth->ug_info->numThreadsRx) {
721 case UCC_GETH_NUM_OF_THREADS_1:
722 numThreadsRxNumerical = 1;
723 break;
724 case UCC_GETH_NUM_OF_THREADS_2:
725 numThreadsRxNumerical = 2;
726 break;
727 case UCC_GETH_NUM_OF_THREADS_4:
728 numThreadsRxNumerical = 4;
729 break;
730 case UCC_GETH_NUM_OF_THREADS_6:
731 numThreadsRxNumerical = 6;
732 break;
733 case UCC_GETH_NUM_OF_THREADS_8:
734 numThreadsRxNumerical = 8;
735 break;
736 default:
737 numThreadsRxNumerical = 0;
738 break;
739 }
740
741 ugeth_info("Thread data RX:");
742 ugeth_info("Base address: 0x%08x",
743 (u32) ugeth->p_thread_data_rx);
744 for (i = 0; i < numThreadsRxNumerical; i++) {
745 ugeth_info("Thread data RX[%d]:", i);
746 ugeth_info("Base address: 0x%08x",
747 (u32) & ugeth->p_thread_data_rx[i]);
748 mem_disp((u8 *) & ugeth->p_thread_data_rx[i],
749 sizeof(struct ucc_geth_thread_data_rx));
750 }
751 }
752 if (ugeth->p_exf_glbl_param) {
753 ugeth_info("EXF global param:");
754 ugeth_info("Base address: 0x%08x",
755 (u32) ugeth->p_exf_glbl_param);
756 mem_disp((u8 *) ugeth->p_exf_glbl_param,
757 sizeof(*ugeth->p_exf_glbl_param));
758 }
759 if (ugeth->p_tx_glbl_pram) {
760 ugeth_info("TX global param:");
761 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_tx_glbl_pram);
762 ugeth_info("temoder : addr - 0x%08x, val - 0x%04x",
763 (u32) & ugeth->p_tx_glbl_pram->temoder,
764 in_be16(&ugeth->p_tx_glbl_pram->temoder));
765 ugeth_info("sqptr : addr - 0x%08x, val - 0x%08x",
766 (u32) & ugeth->p_tx_glbl_pram->sqptr,
767 in_be32(&ugeth->p_tx_glbl_pram->sqptr));
768 ugeth_info("schedulerbasepointer: addr - 0x%08x, val - 0x%08x",
769 (u32) & ugeth->p_tx_glbl_pram->schedulerbasepointer,
770 in_be32(&ugeth->p_tx_glbl_pram->
771 schedulerbasepointer));
772 ugeth_info("txrmonbaseptr: addr - 0x%08x, val - 0x%08x",
773 (u32) & ugeth->p_tx_glbl_pram->txrmonbaseptr,
774 in_be32(&ugeth->p_tx_glbl_pram->txrmonbaseptr));
775 ugeth_info("tstate : addr - 0x%08x, val - 0x%08x",
776 (u32) & ugeth->p_tx_glbl_pram->tstate,
777 in_be32(&ugeth->p_tx_glbl_pram->tstate));
778 ugeth_info("iphoffset[0] : addr - 0x%08x, val - 0x%02x",
779 (u32) & ugeth->p_tx_glbl_pram->iphoffset[0],
780 ugeth->p_tx_glbl_pram->iphoffset[0]);
781 ugeth_info("iphoffset[1] : addr - 0x%08x, val - 0x%02x",
782 (u32) & ugeth->p_tx_glbl_pram->iphoffset[1],
783 ugeth->p_tx_glbl_pram->iphoffset[1]);
784 ugeth_info("iphoffset[2] : addr - 0x%08x, val - 0x%02x",
785 (u32) & ugeth->p_tx_glbl_pram->iphoffset[2],
786 ugeth->p_tx_glbl_pram->iphoffset[2]);
787 ugeth_info("iphoffset[3] : addr - 0x%08x, val - 0x%02x",
788 (u32) & ugeth->p_tx_glbl_pram->iphoffset[3],
789 ugeth->p_tx_glbl_pram->iphoffset[3]);
790 ugeth_info("iphoffset[4] : addr - 0x%08x, val - 0x%02x",
791 (u32) & ugeth->p_tx_glbl_pram->iphoffset[4],
792 ugeth->p_tx_glbl_pram->iphoffset[4]);
793 ugeth_info("iphoffset[5] : addr - 0x%08x, val - 0x%02x",
794 (u32) & ugeth->p_tx_glbl_pram->iphoffset[5],
795 ugeth->p_tx_glbl_pram->iphoffset[5]);
796 ugeth_info("iphoffset[6] : addr - 0x%08x, val - 0x%02x",
797 (u32) & ugeth->p_tx_glbl_pram->iphoffset[6],
798 ugeth->p_tx_glbl_pram->iphoffset[6]);
799 ugeth_info("iphoffset[7] : addr - 0x%08x, val - 0x%02x",
800 (u32) & ugeth->p_tx_glbl_pram->iphoffset[7],
801 ugeth->p_tx_glbl_pram->iphoffset[7]);
802 ugeth_info("vtagtable[0] : addr - 0x%08x, val - 0x%08x",
803 (u32) & ugeth->p_tx_glbl_pram->vtagtable[0],
804 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[0]));
805 ugeth_info("vtagtable[1] : addr - 0x%08x, val - 0x%08x",
806 (u32) & ugeth->p_tx_glbl_pram->vtagtable[1],
807 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[1]));
808 ugeth_info("vtagtable[2] : addr - 0x%08x, val - 0x%08x",
809 (u32) & ugeth->p_tx_glbl_pram->vtagtable[2],
810 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[2]));
811 ugeth_info("vtagtable[3] : addr - 0x%08x, val - 0x%08x",
812 (u32) & ugeth->p_tx_glbl_pram->vtagtable[3],
813 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[3]));
814 ugeth_info("vtagtable[4] : addr - 0x%08x, val - 0x%08x",
815 (u32) & ugeth->p_tx_glbl_pram->vtagtable[4],
816 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[4]));
817 ugeth_info("vtagtable[5] : addr - 0x%08x, val - 0x%08x",
818 (u32) & ugeth->p_tx_glbl_pram->vtagtable[5],
819 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[5]));
820 ugeth_info("vtagtable[6] : addr - 0x%08x, val - 0x%08x",
821 (u32) & ugeth->p_tx_glbl_pram->vtagtable[6],
822 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[6]));
823 ugeth_info("vtagtable[7] : addr - 0x%08x, val - 0x%08x",
824 (u32) & ugeth->p_tx_glbl_pram->vtagtable[7],
825 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[7]));
826 ugeth_info("tqptr : addr - 0x%08x, val - 0x%08x",
827 (u32) & ugeth->p_tx_glbl_pram->tqptr,
828 in_be32(&ugeth->p_tx_glbl_pram->tqptr));
829 }
830 if (ugeth->p_rx_glbl_pram) {
831 ugeth_info("RX global param:");
832 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_glbl_pram);
833 ugeth_info("remoder : addr - 0x%08x, val - 0x%08x",
834 (u32) & ugeth->p_rx_glbl_pram->remoder,
835 in_be32(&ugeth->p_rx_glbl_pram->remoder));
836 ugeth_info("rqptr : addr - 0x%08x, val - 0x%08x",
837 (u32) & ugeth->p_rx_glbl_pram->rqptr,
838 in_be32(&ugeth->p_rx_glbl_pram->rqptr));
839 ugeth_info("typeorlen : addr - 0x%08x, val - 0x%04x",
840 (u32) & ugeth->p_rx_glbl_pram->typeorlen,
841 in_be16(&ugeth->p_rx_glbl_pram->typeorlen));
842 ugeth_info("rxgstpack : addr - 0x%08x, val - 0x%02x",
843 (u32) & ugeth->p_rx_glbl_pram->rxgstpack,
844 ugeth->p_rx_glbl_pram->rxgstpack);
845 ugeth_info("rxrmonbaseptr : addr - 0x%08x, val - 0x%08x",
846 (u32) & ugeth->p_rx_glbl_pram->rxrmonbaseptr,
847 in_be32(&ugeth->p_rx_glbl_pram->rxrmonbaseptr));
848 ugeth_info("intcoalescingptr: addr - 0x%08x, val - 0x%08x",
849 (u32) & ugeth->p_rx_glbl_pram->intcoalescingptr,
850 in_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr));
851 ugeth_info("rstate : addr - 0x%08x, val - 0x%02x",
852 (u32) & ugeth->p_rx_glbl_pram->rstate,
853 ugeth->p_rx_glbl_pram->rstate);
854 ugeth_info("mrblr : addr - 0x%08x, val - 0x%04x",
855 (u32) & ugeth->p_rx_glbl_pram->mrblr,
856 in_be16(&ugeth->p_rx_glbl_pram->mrblr));
857 ugeth_info("rbdqptr : addr - 0x%08x, val - 0x%08x",
858 (u32) & ugeth->p_rx_glbl_pram->rbdqptr,
859 in_be32(&ugeth->p_rx_glbl_pram->rbdqptr));
860 ugeth_info("mflr : addr - 0x%08x, val - 0x%04x",
861 (u32) & ugeth->p_rx_glbl_pram->mflr,
862 in_be16(&ugeth->p_rx_glbl_pram->mflr));
863 ugeth_info("minflr : addr - 0x%08x, val - 0x%04x",
864 (u32) & ugeth->p_rx_glbl_pram->minflr,
865 in_be16(&ugeth->p_rx_glbl_pram->minflr));
866 ugeth_info("maxd1 : addr - 0x%08x, val - 0x%04x",
867 (u32) & ugeth->p_rx_glbl_pram->maxd1,
868 in_be16(&ugeth->p_rx_glbl_pram->maxd1));
869 ugeth_info("maxd2 : addr - 0x%08x, val - 0x%04x",
870 (u32) & ugeth->p_rx_glbl_pram->maxd2,
871 in_be16(&ugeth->p_rx_glbl_pram->maxd2));
872 ugeth_info("ecamptr : addr - 0x%08x, val - 0x%08x",
873 (u32) & ugeth->p_rx_glbl_pram->ecamptr,
874 in_be32(&ugeth->p_rx_glbl_pram->ecamptr));
875 ugeth_info("l2qt : addr - 0x%08x, val - 0x%08x",
876 (u32) & ugeth->p_rx_glbl_pram->l2qt,
877 in_be32(&ugeth->p_rx_glbl_pram->l2qt));
878 ugeth_info("l3qt[0] : addr - 0x%08x, val - 0x%08x",
879 (u32) & ugeth->p_rx_glbl_pram->l3qt[0],
880 in_be32(&ugeth->p_rx_glbl_pram->l3qt[0]));
881 ugeth_info("l3qt[1] : addr - 0x%08x, val - 0x%08x",
882 (u32) & ugeth->p_rx_glbl_pram->l3qt[1],
883 in_be32(&ugeth->p_rx_glbl_pram->l3qt[1]));
884 ugeth_info("l3qt[2] : addr - 0x%08x, val - 0x%08x",
885 (u32) & ugeth->p_rx_glbl_pram->l3qt[2],
886 in_be32(&ugeth->p_rx_glbl_pram->l3qt[2]));
887 ugeth_info("l3qt[3] : addr - 0x%08x, val - 0x%08x",
888 (u32) & ugeth->p_rx_glbl_pram->l3qt[3],
889 in_be32(&ugeth->p_rx_glbl_pram->l3qt[3]));
890 ugeth_info("l3qt[4] : addr - 0x%08x, val - 0x%08x",
891 (u32) & ugeth->p_rx_glbl_pram->l3qt[4],
892 in_be32(&ugeth->p_rx_glbl_pram->l3qt[4]));
893 ugeth_info("l3qt[5] : addr - 0x%08x, val - 0x%08x",
894 (u32) & ugeth->p_rx_glbl_pram->l3qt[5],
895 in_be32(&ugeth->p_rx_glbl_pram->l3qt[5]));
896 ugeth_info("l3qt[6] : addr - 0x%08x, val - 0x%08x",
897 (u32) & ugeth->p_rx_glbl_pram->l3qt[6],
898 in_be32(&ugeth->p_rx_glbl_pram->l3qt[6]));
899 ugeth_info("l3qt[7] : addr - 0x%08x, val - 0x%08x",
900 (u32) & ugeth->p_rx_glbl_pram->l3qt[7],
901 in_be32(&ugeth->p_rx_glbl_pram->l3qt[7]));
902 ugeth_info("vlantype : addr - 0x%08x, val - 0x%04x",
903 (u32) & ugeth->p_rx_glbl_pram->vlantype,
904 in_be16(&ugeth->p_rx_glbl_pram->vlantype));
905 ugeth_info("vlantci : addr - 0x%08x, val - 0x%04x",
906 (u32) & ugeth->p_rx_glbl_pram->vlantci,
907 in_be16(&ugeth->p_rx_glbl_pram->vlantci));
908 for (i = 0; i < 64; i++)
909 ugeth_info
910 ("addressfiltering[%d]: addr - 0x%08x, val - 0x%02x",
911 i,
912 (u32) & ugeth->p_rx_glbl_pram->addressfiltering[i],
913 ugeth->p_rx_glbl_pram->addressfiltering[i]);
914 ugeth_info("exfGlobalParam : addr - 0x%08x, val - 0x%08x",
915 (u32) & ugeth->p_rx_glbl_pram->exfGlobalParam,
916 in_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam));
917 }
918 if (ugeth->p_send_q_mem_reg) {
919 ugeth_info("Send Q memory registers:");
920 ugeth_info("Base address: 0x%08x",
921 (u32) ugeth->p_send_q_mem_reg);
922 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
923 ugeth_info("SQQD[%d]:", i);
924 ugeth_info("Base address: 0x%08x",
925 (u32) & ugeth->p_send_q_mem_reg->sqqd[i]);
926 mem_disp((u8 *) & ugeth->p_send_q_mem_reg->sqqd[i],
927 sizeof(struct ucc_geth_send_queue_qd));
928 }
929 }
930 if (ugeth->p_scheduler) {
931 ugeth_info("Scheduler:");
932 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_scheduler);
933 mem_disp((u8 *) ugeth->p_scheduler,
934 sizeof(*ugeth->p_scheduler));
935 }
936 if (ugeth->p_tx_fw_statistics_pram) {
937 ugeth_info("TX FW statistics pram:");
938 ugeth_info("Base address: 0x%08x",
939 (u32) ugeth->p_tx_fw_statistics_pram);
940 mem_disp((u8 *) ugeth->p_tx_fw_statistics_pram,
941 sizeof(*ugeth->p_tx_fw_statistics_pram));
942 }
943 if (ugeth->p_rx_fw_statistics_pram) {
944 ugeth_info("RX FW statistics pram:");
945 ugeth_info("Base address: 0x%08x",
946 (u32) ugeth->p_rx_fw_statistics_pram);
947 mem_disp((u8 *) ugeth->p_rx_fw_statistics_pram,
948 sizeof(*ugeth->p_rx_fw_statistics_pram));
949 }
950 if (ugeth->p_rx_irq_coalescing_tbl) {
951 ugeth_info("RX IRQ coalescing tables:");
952 ugeth_info("Base address: 0x%08x",
953 (u32) ugeth->p_rx_irq_coalescing_tbl);
954 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
955 ugeth_info("RX IRQ coalescing table entry[%d]:", i);
956 ugeth_info("Base address: 0x%08x",
957 (u32) & ugeth->p_rx_irq_coalescing_tbl->
958 coalescingentry[i]);
959 ugeth_info
960 ("interruptcoalescingmaxvalue: addr - 0x%08x, val - 0x%08x",
961 (u32) & ugeth->p_rx_irq_coalescing_tbl->
962 coalescingentry[i].interruptcoalescingmaxvalue,
963 in_be32(&ugeth->p_rx_irq_coalescing_tbl->
964 coalescingentry[i].
965 interruptcoalescingmaxvalue));
966 ugeth_info
967 ("interruptcoalescingcounter : addr - 0x%08x, val - 0x%08x",
968 (u32) & ugeth->p_rx_irq_coalescing_tbl->
969 coalescingentry[i].interruptcoalescingcounter,
970 in_be32(&ugeth->p_rx_irq_coalescing_tbl->
971 coalescingentry[i].
972 interruptcoalescingcounter));
973 }
974 }
975 if (ugeth->p_rx_bd_qs_tbl) {
976 ugeth_info("RX BD QS tables:");
977 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_bd_qs_tbl);
978 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
979 ugeth_info("RX BD QS table[%d]:", i);
980 ugeth_info("Base address: 0x%08x",
981 (u32) & ugeth->p_rx_bd_qs_tbl[i]);
982 ugeth_info
983 ("bdbaseptr : addr - 0x%08x, val - 0x%08x",
984 (u32) & ugeth->p_rx_bd_qs_tbl[i].bdbaseptr,
985 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr));
986 ugeth_info
987 ("bdptr : addr - 0x%08x, val - 0x%08x",
988 (u32) & ugeth->p_rx_bd_qs_tbl[i].bdptr,
989 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdptr));
990 ugeth_info
991 ("externalbdbaseptr: addr - 0x%08x, val - 0x%08x",
992 (u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
993 in_be32(&ugeth->p_rx_bd_qs_tbl[i].
994 externalbdbaseptr));
995 ugeth_info
996 ("externalbdptr : addr - 0x%08x, val - 0x%08x",
997 (u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdptr,
998 in_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdptr));
999 ugeth_info("ucode RX Prefetched BDs:");
1000 ugeth_info("Base address: 0x%08x",
1001 (u32)
1002 qe_muram_addr(in_be32
1003 (&ugeth->p_rx_bd_qs_tbl[i].
1004 bdbaseptr)));
1005 mem_disp((u8 *)
1006 qe_muram_addr(in_be32
1007 (&ugeth->p_rx_bd_qs_tbl[i].
1008 bdbaseptr)),
1009 sizeof(struct ucc_geth_rx_prefetched_bds));
1010 }
1011 }
1012 if (ugeth->p_init_enet_param_shadow) {
1013 int size;
1014 ugeth_info("Init enet param shadow:");
1015 ugeth_info("Base address: 0x%08x",
1016 (u32) ugeth->p_init_enet_param_shadow);
1017 mem_disp((u8 *) ugeth->p_init_enet_param_shadow,
1018 sizeof(*ugeth->p_init_enet_param_shadow));
1019
1020 size = sizeof(struct ucc_geth_thread_rx_pram);
1021 if (ugeth->ug_info->rxExtendedFiltering) {
1022 size +=
1023 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
1024 if (ugeth->ug_info->largestexternallookupkeysize ==
1025 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
1026 size +=
1027 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
1028 if (ugeth->ug_info->largestexternallookupkeysize ==
1029 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
1030 size +=
1031 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
1032 }
1033
1034 dump_init_enet_entries(ugeth,
1035 &(ugeth->p_init_enet_param_shadow->
1036 txthread[0]),
1037 ENET_INIT_PARAM_MAX_ENTRIES_TX,
1038 sizeof(struct ucc_geth_thread_tx_pram),
1039 ugeth->ug_info->riscTx, 0);
1040 dump_init_enet_entries(ugeth,
1041 &(ugeth->p_init_enet_param_shadow->
1042 rxthread[0]),
1043 ENET_INIT_PARAM_MAX_ENTRIES_RX, size,
1044 ugeth->ug_info->riscRx, 1);
1045 }
1046 }
1047 #endif /* DEBUG */
1048
1049 static void init_default_reg_vals(u32 __iomem *upsmr_register,
1050 u32 __iomem *maccfg1_register,
1051 u32 __iomem *maccfg2_register)
1052 {
1053 out_be32(upsmr_register, UCC_GETH_UPSMR_INIT);
1054 out_be32(maccfg1_register, UCC_GETH_MACCFG1_INIT);
1055 out_be32(maccfg2_register, UCC_GETH_MACCFG2_INIT);
1056 }
1057
1058 static int init_half_duplex_params(int alt_beb,
1059 int back_pressure_no_backoff,
1060 int no_backoff,
1061 int excess_defer,
1062 u8 alt_beb_truncation,
1063 u8 max_retransmissions,
1064 u8 collision_window,
1065 u32 __iomem *hafdup_register)
1066 {
1067 u32 value = 0;
1068
1069 if ((alt_beb_truncation > HALFDUP_ALT_BEB_TRUNCATION_MAX) ||
1070 (max_retransmissions > HALFDUP_MAX_RETRANSMISSION_MAX) ||
1071 (collision_window > HALFDUP_COLLISION_WINDOW_MAX))
1072 return -EINVAL;
1073
1074 value = (u32) (alt_beb_truncation << HALFDUP_ALT_BEB_TRUNCATION_SHIFT);
1075
1076 if (alt_beb)
1077 value |= HALFDUP_ALT_BEB;
1078 if (back_pressure_no_backoff)
1079 value |= HALFDUP_BACK_PRESSURE_NO_BACKOFF;
1080 if (no_backoff)
1081 value |= HALFDUP_NO_BACKOFF;
1082 if (excess_defer)
1083 value |= HALFDUP_EXCESSIVE_DEFER;
1084
1085 value |= (max_retransmissions << HALFDUP_MAX_RETRANSMISSION_SHIFT);
1086
1087 value |= collision_window;
1088
1089 out_be32(hafdup_register, value);
1090 return 0;
1091 }
1092
1093 static int init_inter_frame_gap_params(u8 non_btb_cs_ipg,
1094 u8 non_btb_ipg,
1095 u8 min_ifg,
1096 u8 btb_ipg,
1097 u32 __iomem *ipgifg_register)
1098 {
1099 u32 value = 0;
1100
1101 /* Non-Back-to-back IPG part 1 should be <= Non-Back-to-back
1102 IPG part 2 */
1103 if (non_btb_cs_ipg > non_btb_ipg)
1104 return -EINVAL;
1105
1106 if ((non_btb_cs_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX) ||
1107 (non_btb_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX) ||
1108 /*(min_ifg > IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX) || */
1109 (btb_ipg > IPGIFG_BACK_TO_BACK_IFG_MAX))
1110 return -EINVAL;
1111
1112 value |=
1113 ((non_btb_cs_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT) &
1114 IPGIFG_NBTB_CS_IPG_MASK);
1115 value |=
1116 ((non_btb_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT) &
1117 IPGIFG_NBTB_IPG_MASK);
1118 value |=
1119 ((min_ifg << IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT) &
1120 IPGIFG_MIN_IFG_MASK);
1121 value |= (btb_ipg & IPGIFG_BTB_IPG_MASK);
1122
1123 out_be32(ipgifg_register, value);
1124 return 0;
1125 }
1126
1127 int init_flow_control_params(u32 automatic_flow_control_mode,
1128 int rx_flow_control_enable,
1129 int tx_flow_control_enable,
1130 u16 pause_period,
1131 u16 extension_field,
1132 u32 __iomem *upsmr_register,
1133 u32 __iomem *uempr_register,
1134 u32 __iomem *maccfg1_register)
1135 {
1136 u32 value = 0;
1137
1138 /* Set UEMPR register */
1139 value = (u32) pause_period << UEMPR_PAUSE_TIME_VALUE_SHIFT;
1140 value |= (u32) extension_field << UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT;
1141 out_be32(uempr_register, value);
1142
1143 /* Set UPSMR register */
1144 setbits32(upsmr_register, automatic_flow_control_mode);
1145
1146 value = in_be32(maccfg1_register);
1147 if (rx_flow_control_enable)
1148 value |= MACCFG1_FLOW_RX;
1149 if (tx_flow_control_enable)
1150 value |= MACCFG1_FLOW_TX;
1151 out_be32(maccfg1_register, value);
1152
1153 return 0;
1154 }
1155
1156 static int init_hw_statistics_gathering_mode(int enable_hardware_statistics,
1157 int auto_zero_hardware_statistics,
1158 u32 __iomem *upsmr_register,
1159 u16 __iomem *uescr_register)
1160 {
1161 u16 uescr_value = 0;
1162
1163 /* Enable hardware statistics gathering if requested */
1164 if (enable_hardware_statistics)
1165 setbits32(upsmr_register, UCC_GETH_UPSMR_HSE);
1166
1167 /* Clear hardware statistics counters */
1168 uescr_value = in_be16(uescr_register);
1169 uescr_value |= UESCR_CLRCNT;
1170 /* Automatically zero hardware statistics counters on read,
1171 if requested */
1172 if (auto_zero_hardware_statistics)
1173 uescr_value |= UESCR_AUTOZ;
1174 out_be16(uescr_register, uescr_value);
1175
1176 return 0;
1177 }
1178
1179 static int init_firmware_statistics_gathering_mode(int
1180 enable_tx_firmware_statistics,
1181 int enable_rx_firmware_statistics,
1182 u32 __iomem *tx_rmon_base_ptr,
1183 u32 tx_firmware_statistics_structure_address,
1184 u32 __iomem *rx_rmon_base_ptr,
1185 u32 rx_firmware_statistics_structure_address,
1186 u16 __iomem *temoder_register,
1187 u32 __iomem *remoder_register)
1188 {
1189 /* Note: this function does not check if */
1190 /* the parameters it receives are NULL */
1191
1192 if (enable_tx_firmware_statistics) {
1193 out_be32(tx_rmon_base_ptr,
1194 tx_firmware_statistics_structure_address);
1195 setbits16(temoder_register, TEMODER_TX_RMON_STATISTICS_ENABLE);
1196 }
1197
1198 if (enable_rx_firmware_statistics) {
1199 out_be32(rx_rmon_base_ptr,
1200 rx_firmware_statistics_structure_address);
1201 setbits32(remoder_register, REMODER_RX_RMON_STATISTICS_ENABLE);
1202 }
1203
1204 return 0;
1205 }
1206
1207 static int init_mac_station_addr_regs(u8 address_byte_0,
1208 u8 address_byte_1,
1209 u8 address_byte_2,
1210 u8 address_byte_3,
1211 u8 address_byte_4,
1212 u8 address_byte_5,
1213 u32 __iomem *macstnaddr1_register,
1214 u32 __iomem *macstnaddr2_register)
1215 {
1216 u32 value = 0;
1217
1218 /* Example: for a station address of 0x12345678ABCD, */
1219 /* 0x12 is byte 0, 0x34 is byte 1 and so on and 0xCD is byte 5 */
1220
1221 /* MACSTNADDR1 Register: */
1222
1223 /* 0 7 8 15 */
1224 /* station address byte 5 station address byte 4 */
1225 /* 16 23 24 31 */
1226 /* station address byte 3 station address byte 2 */
1227 value |= (u32) ((address_byte_2 << 0) & 0x000000FF);
1228 value |= (u32) ((address_byte_3 << 8) & 0x0000FF00);
1229 value |= (u32) ((address_byte_4 << 16) & 0x00FF0000);
1230 value |= (u32) ((address_byte_5 << 24) & 0xFF000000);
1231
1232 out_be32(macstnaddr1_register, value);
1233
1234 /* MACSTNADDR2 Register: */
1235
1236 /* 0 7 8 15 */
1237 /* station address byte 1 station address byte 0 */
1238 /* 16 23 24 31 */
1239 /* reserved reserved */
1240 value = 0;
1241 value |= (u32) ((address_byte_0 << 16) & 0x00FF0000);
1242 value |= (u32) ((address_byte_1 << 24) & 0xFF000000);
1243
1244 out_be32(macstnaddr2_register, value);
1245
1246 return 0;
1247 }
1248
1249 static int init_check_frame_length_mode(int length_check,
1250 u32 __iomem *maccfg2_register)
1251 {
1252 u32 value = 0;
1253
1254 value = in_be32(maccfg2_register);
1255
1256 if (length_check)
1257 value |= MACCFG2_LC;
1258 else
1259 value &= ~MACCFG2_LC;
1260
1261 out_be32(maccfg2_register, value);
1262 return 0;
1263 }
1264
1265 static int init_preamble_length(u8 preamble_length,
1266 u32 __iomem *maccfg2_register)
1267 {
1268 if ((preamble_length < 3) || (preamble_length > 7))
1269 return -EINVAL;
1270
1271 clrsetbits_be32(maccfg2_register, MACCFG2_PREL_MASK,
1272 preamble_length << MACCFG2_PREL_SHIFT);
1273
1274 return 0;
1275 }
1276
1277 static int init_rx_parameters(int reject_broadcast,
1278 int receive_short_frames,
1279 int promiscuous, u32 __iomem *upsmr_register)
1280 {
1281 u32 value = 0;
1282
1283 value = in_be32(upsmr_register);
1284
1285 if (reject_broadcast)
1286 value |= UCC_GETH_UPSMR_BRO;
1287 else
1288 value &= ~UCC_GETH_UPSMR_BRO;
1289
1290 if (receive_short_frames)
1291 value |= UCC_GETH_UPSMR_RSH;
1292 else
1293 value &= ~UCC_GETH_UPSMR_RSH;
1294
1295 if (promiscuous)
1296 value |= UCC_GETH_UPSMR_PRO;
1297 else
1298 value &= ~UCC_GETH_UPSMR_PRO;
1299
1300 out_be32(upsmr_register, value);
1301
1302 return 0;
1303 }
1304
1305 static int init_max_rx_buff_len(u16 max_rx_buf_len,
1306 u16 __iomem *mrblr_register)
1307 {
1308 /* max_rx_buf_len value must be a multiple of 128 */
1309 if ((max_rx_buf_len == 0)
1310 || (max_rx_buf_len % UCC_GETH_MRBLR_ALIGNMENT))
1311 return -EINVAL;
1312
1313 out_be16(mrblr_register, max_rx_buf_len);
1314 return 0;
1315 }
1316
1317 static int init_min_frame_len(u16 min_frame_length,
1318 u16 __iomem *minflr_register,
1319 u16 __iomem *mrblr_register)
1320 {
1321 u16 mrblr_value = 0;
1322
1323 mrblr_value = in_be16(mrblr_register);
1324 if (min_frame_length >= (mrblr_value - 4))
1325 return -EINVAL;
1326
1327 out_be16(minflr_register, min_frame_length);
1328 return 0;
1329 }
1330
1331 static int adjust_enet_interface(struct ucc_geth_private *ugeth)
1332 {
1333 struct ucc_geth_info *ug_info;
1334 struct ucc_geth __iomem *ug_regs;
1335 struct ucc_fast __iomem *uf_regs;
1336 int ret_val;
1337 u32 upsmr, maccfg2, tbiBaseAddress;
1338 u16 value;
1339
1340 ugeth_vdbg("%s: IN", __func__);
1341
1342 ug_info = ugeth->ug_info;
1343 ug_regs = ugeth->ug_regs;
1344 uf_regs = ugeth->uccf->uf_regs;
1345
1346 /* Set MACCFG2 */
1347 maccfg2 = in_be32(&ug_regs->maccfg2);
1348 maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
1349 if ((ugeth->max_speed == SPEED_10) ||
1350 (ugeth->max_speed == SPEED_100))
1351 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
1352 else if (ugeth->max_speed == SPEED_1000)
1353 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
1354 maccfg2 |= ug_info->padAndCrc;
1355 out_be32(&ug_regs->maccfg2, maccfg2);
1356
1357 /* Set UPSMR */
1358 upsmr = in_be32(&uf_regs->upsmr);
1359 upsmr &= ~(UCC_GETH_UPSMR_RPM | UCC_GETH_UPSMR_R10M |
1360 UCC_GETH_UPSMR_TBIM | UCC_GETH_UPSMR_RMM);
1361 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1362 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1363 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1364 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1365 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
1366 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1367 if (ugeth->phy_interface != PHY_INTERFACE_MODE_RMII)
1368 upsmr |= UCC_GETH_UPSMR_RPM;
1369 switch (ugeth->max_speed) {
1370 case SPEED_10:
1371 upsmr |= UCC_GETH_UPSMR_R10M;
1372 /* FALLTHROUGH */
1373 case SPEED_100:
1374 if (ugeth->phy_interface != PHY_INTERFACE_MODE_RTBI)
1375 upsmr |= UCC_GETH_UPSMR_RMM;
1376 }
1377 }
1378 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1379 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1380 upsmr |= UCC_GETH_UPSMR_TBIM;
1381 }
1382 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_SGMII))
1383 upsmr |= UCC_GETH_UPSMR_SGMM;
1384
1385 out_be32(&uf_regs->upsmr, upsmr);
1386
1387 /* Disable autonegotiation in tbi mode, because by default it
1388 comes up in autonegotiation mode. */
1389 /* Note that this depends on proper setting in utbipar register. */
1390 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1391 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1392 tbiBaseAddress = in_be32(&ug_regs->utbipar);
1393 tbiBaseAddress &= UTBIPAR_PHY_ADDRESS_MASK;
1394 tbiBaseAddress >>= UTBIPAR_PHY_ADDRESS_SHIFT;
1395 value = ugeth->phydev->bus->read(ugeth->phydev->bus,
1396 (u8) tbiBaseAddress, ENET_TBI_MII_CR);
1397 value &= ~0x1000; /* Turn off autonegotiation */
1398 ugeth->phydev->bus->write(ugeth->phydev->bus,
1399 (u8) tbiBaseAddress, ENET_TBI_MII_CR, value);
1400 }
1401
1402 init_check_frame_length_mode(ug_info->lengthCheckRx, &ug_regs->maccfg2);
1403
1404 ret_val = init_preamble_length(ug_info->prel, &ug_regs->maccfg2);
1405 if (ret_val != 0) {
1406 if (netif_msg_probe(ugeth))
1407 ugeth_err("%s: Preamble length must be between 3 and 7 inclusive.",
1408 __func__);
1409 return ret_val;
1410 }
1411
1412 return 0;
1413 }
1414
1415 static int ugeth_graceful_stop_tx(struct ucc_geth_private *ugeth)
1416 {
1417 struct ucc_fast_private *uccf;
1418 u32 cecr_subblock;
1419 u32 temp;
1420 int i = 10;
1421
1422 uccf = ugeth->uccf;
1423
1424 /* Mask GRACEFUL STOP TX interrupt bit and clear it */
1425 clrbits32(uccf->p_uccm, UCC_GETH_UCCE_GRA);
1426 out_be32(uccf->p_ucce, UCC_GETH_UCCE_GRA); /* clear by writing 1 */
1427
1428 /* Issue host command */
1429 cecr_subblock =
1430 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1431 qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
1432 QE_CR_PROTOCOL_ETHERNET, 0);
1433
1434 /* Wait for command to complete */
1435 do {
1436 msleep(10);
1437 temp = in_be32(uccf->p_ucce);
1438 } while (!(temp & UCC_GETH_UCCE_GRA) && --i);
1439
1440 uccf->stopped_tx = 1;
1441
1442 return 0;
1443 }
1444
1445 static int ugeth_graceful_stop_rx(struct ucc_geth_private *ugeth)
1446 {
1447 struct ucc_fast_private *uccf;
1448 u32 cecr_subblock;
1449 u8 temp;
1450 int i = 10;
1451
1452 uccf = ugeth->uccf;
1453
1454 /* Clear acknowledge bit */
1455 temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack);
1456 temp &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
1457 out_8(&ugeth->p_rx_glbl_pram->rxgstpack, temp);
1458
1459 /* Keep issuing command and checking acknowledge bit until
1460 it is asserted, according to spec */
1461 do {
1462 /* Issue host command */
1463 cecr_subblock =
1464 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.
1465 ucc_num);
1466 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
1467 QE_CR_PROTOCOL_ETHERNET, 0);
1468 msleep(10);
1469 temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack);
1470 } while (!(temp & GRACEFUL_STOP_ACKNOWLEDGE_RX) && --i);
1471
1472 uccf->stopped_rx = 1;
1473
1474 return 0;
1475 }
1476
1477 static int ugeth_restart_tx(struct ucc_geth_private *ugeth)
1478 {
1479 struct ucc_fast_private *uccf;
1480 u32 cecr_subblock;
1481
1482 uccf = ugeth->uccf;
1483
1484 cecr_subblock =
1485 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1486 qe_issue_cmd(QE_RESTART_TX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET, 0);
1487 uccf->stopped_tx = 0;
1488
1489 return 0;
1490 }
1491
1492 static int ugeth_restart_rx(struct ucc_geth_private *ugeth)
1493 {
1494 struct ucc_fast_private *uccf;
1495 u32 cecr_subblock;
1496
1497 uccf = ugeth->uccf;
1498
1499 cecr_subblock =
1500 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1501 qe_issue_cmd(QE_RESTART_RX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
1502 0);
1503 uccf->stopped_rx = 0;
1504
1505 return 0;
1506 }
1507
1508 static int ugeth_enable(struct ucc_geth_private *ugeth, enum comm_dir mode)
1509 {
1510 struct ucc_fast_private *uccf;
1511 int enabled_tx, enabled_rx;
1512
1513 uccf = ugeth->uccf;
1514
1515 /* check if the UCC number is in range. */
1516 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
1517 if (netif_msg_probe(ugeth))
1518 ugeth_err("%s: ucc_num out of range.", __func__);
1519 return -EINVAL;
1520 }
1521
1522 enabled_tx = uccf->enabled_tx;
1523 enabled_rx = uccf->enabled_rx;
1524
1525 /* Get Tx and Rx going again, in case this channel was actively
1526 disabled. */
1527 if ((mode & COMM_DIR_TX) && (!enabled_tx) && uccf->stopped_tx)
1528 ugeth_restart_tx(ugeth);
1529 if ((mode & COMM_DIR_RX) && (!enabled_rx) && uccf->stopped_rx)
1530 ugeth_restart_rx(ugeth);
1531
1532 ucc_fast_enable(uccf, mode); /* OK to do even if not disabled */
1533
1534 return 0;
1535
1536 }
1537
1538 static int ugeth_disable(struct ucc_geth_private *ugeth, enum comm_dir mode)
1539 {
1540 struct ucc_fast_private *uccf;
1541
1542 uccf = ugeth->uccf;
1543
1544 /* check if the UCC number is in range. */
1545 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
1546 if (netif_msg_probe(ugeth))
1547 ugeth_err("%s: ucc_num out of range.", __func__);
1548 return -EINVAL;
1549 }
1550
1551 /* Stop any transmissions */
1552 if ((mode & COMM_DIR_TX) && uccf->enabled_tx && !uccf->stopped_tx)
1553 ugeth_graceful_stop_tx(ugeth);
1554
1555 /* Stop any receptions */
1556 if ((mode & COMM_DIR_RX) && uccf->enabled_rx && !uccf->stopped_rx)
1557 ugeth_graceful_stop_rx(ugeth);
1558
1559 ucc_fast_disable(ugeth->uccf, mode); /* OK to do even if not enabled */
1560
1561 return 0;
1562 }
1563
1564 /* Called every time the controller might need to be made
1565 * aware of new link state. The PHY code conveys this
1566 * information through variables in the ugeth structure, and this
1567 * function converts those variables into the appropriate
1568 * register values, and can bring down the device if needed.
1569 */
1570
1571 static void adjust_link(struct net_device *dev)
1572 {
1573 struct ucc_geth_private *ugeth = netdev_priv(dev);
1574 struct ucc_geth __iomem *ug_regs;
1575 struct ucc_fast __iomem *uf_regs;
1576 struct phy_device *phydev = ugeth->phydev;
1577 unsigned long flags;
1578 int new_state = 0;
1579
1580 ug_regs = ugeth->ug_regs;
1581 uf_regs = ugeth->uccf->uf_regs;
1582
1583 spin_lock_irqsave(&ugeth->lock, flags);
1584
1585 if (phydev->link) {
1586 u32 tempval = in_be32(&ug_regs->maccfg2);
1587 u32 upsmr = in_be32(&uf_regs->upsmr);
1588 /* Now we make sure that we can be in full duplex mode.
1589 * If not, we operate in half-duplex mode. */
1590 if (phydev->duplex != ugeth->oldduplex) {
1591 new_state = 1;
1592 if (!(phydev->duplex))
1593 tempval &= ~(MACCFG2_FDX);
1594 else
1595 tempval |= MACCFG2_FDX;
1596 ugeth->oldduplex = phydev->duplex;
1597 }
1598
1599 if (phydev->speed != ugeth->oldspeed) {
1600 new_state = 1;
1601 switch (phydev->speed) {
1602 case SPEED_1000:
1603 tempval = ((tempval &
1604 ~(MACCFG2_INTERFACE_MODE_MASK)) |
1605 MACCFG2_INTERFACE_MODE_BYTE);
1606 break;
1607 case SPEED_100:
1608 case SPEED_10:
1609 tempval = ((tempval &
1610 ~(MACCFG2_INTERFACE_MODE_MASK)) |
1611 MACCFG2_INTERFACE_MODE_NIBBLE);
1612 /* if reduced mode, re-set UPSMR.R10M */
1613 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1614 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1615 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1616 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1617 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
1618 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1619 if (phydev->speed == SPEED_10)
1620 upsmr |= UCC_GETH_UPSMR_R10M;
1621 else
1622 upsmr &= ~UCC_GETH_UPSMR_R10M;
1623 }
1624 break;
1625 default:
1626 if (netif_msg_link(ugeth))
1627 ugeth_warn(
1628 "%s: Ack! Speed (%d) is not 10/100/1000!",
1629 dev->name, phydev->speed);
1630 break;
1631 }
1632 ugeth->oldspeed = phydev->speed;
1633 }
1634
1635 out_be32(&ug_regs->maccfg2, tempval);
1636 out_be32(&uf_regs->upsmr, upsmr);
1637
1638 if (!ugeth->oldlink) {
1639 new_state = 1;
1640 ugeth->oldlink = 1;
1641 }
1642 } else if (ugeth->oldlink) {
1643 new_state = 1;
1644 ugeth->oldlink = 0;
1645 ugeth->oldspeed = 0;
1646 ugeth->oldduplex = -1;
1647 }
1648
1649 if (new_state && netif_msg_link(ugeth))
1650 phy_print_status(phydev);
1651
1652 spin_unlock_irqrestore(&ugeth->lock, flags);
1653 }
1654
1655 /* Initialize TBI PHY interface for communicating with the
1656 * SERDES lynx PHY on the chip. We communicate with this PHY
1657 * through the MDIO bus on each controller, treating it as a
1658 * "normal" PHY at the address found in the UTBIPA register. We assume
1659 * that the UTBIPA register is valid. Either the MDIO bus code will set
1660 * it to a value that doesn't conflict with other PHYs on the bus, or the
1661 * value doesn't matter, as there are no other PHYs on the bus.
1662 */
1663 static void uec_configure_serdes(struct net_device *dev)
1664 {
1665 struct ucc_geth_private *ugeth = netdev_priv(dev);
1666 struct ucc_geth_info *ug_info = ugeth->ug_info;
1667 struct phy_device *tbiphy;
1668
1669 if (!ug_info->tbi_node) {
1670 dev_warn(&dev->dev, "SGMII mode requires that the device "
1671 "tree specify a tbi-handle\n");
1672 return;
1673 }
1674
1675 tbiphy = of_phy_find_device(ug_info->tbi_node);
1676 if (!tbiphy) {
1677 dev_err(&dev->dev, "error: Could not get TBI device\n");
1678 return;
1679 }
1680
1681 /*
1682 * If the link is already up, we must already be ok, and don't need to
1683 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1684 * everything for us? Resetting it takes the link down and requires
1685 * several seconds for it to come back.
1686 */
1687 if (phy_read(tbiphy, ENET_TBI_MII_SR) & TBISR_LSTATUS)
1688 return;
1689
1690 /* Single clk mode, mii mode off(for serdes communication) */
1691 phy_write(tbiphy, ENET_TBI_MII_ANA, TBIANA_SETTINGS);
1692
1693 phy_write(tbiphy, ENET_TBI_MII_TBICON, TBICON_CLK_SELECT);
1694
1695 phy_write(tbiphy, ENET_TBI_MII_CR, TBICR_SETTINGS);
1696 }
1697
1698 /* Configure the PHY for dev.
1699 * returns 0 if success. -1 if failure
1700 */
1701 static int init_phy(struct net_device *dev)
1702 {
1703 struct ucc_geth_private *priv = netdev_priv(dev);
1704 struct ucc_geth_info *ug_info = priv->ug_info;
1705 struct phy_device *phydev;
1706
1707 priv->oldlink = 0;
1708 priv->oldspeed = 0;
1709 priv->oldduplex = -1;
1710
1711 phydev = of_phy_connect(dev, ug_info->phy_node, &adjust_link, 0,
1712 priv->phy_interface);
1713 if (!phydev)
1714 phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1715 priv->phy_interface);
1716 if (!phydev) {
1717 dev_err(&dev->dev, "Could not attach to PHY\n");
1718 return -ENODEV;
1719 }
1720
1721 if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII)
1722 uec_configure_serdes(dev);
1723
1724 phydev->supported &= (ADVERTISED_10baseT_Half |
1725 ADVERTISED_10baseT_Full |
1726 ADVERTISED_100baseT_Half |
1727 ADVERTISED_100baseT_Full);
1728
1729 if (priv->max_speed == SPEED_1000)
1730 phydev->supported |= ADVERTISED_1000baseT_Full;
1731
1732 phydev->advertising = phydev->supported;
1733
1734 priv->phydev = phydev;
1735
1736 return 0;
1737 }
1738
1739 static void ugeth_dump_regs(struct ucc_geth_private *ugeth)
1740 {
1741 #ifdef DEBUG
1742 ucc_fast_dump_regs(ugeth->uccf);
1743 dump_regs(ugeth);
1744 dump_bds(ugeth);
1745 #endif
1746 }
1747
1748 static int ugeth_82xx_filtering_clear_all_addr_in_hash(struct ucc_geth_private *
1749 ugeth,
1750 enum enet_addr_type
1751 enet_addr_type)
1752 {
1753 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
1754 struct ucc_fast_private *uccf;
1755 enum comm_dir comm_dir;
1756 struct list_head *p_lh;
1757 u16 i, num;
1758 u32 __iomem *addr_h;
1759 u32 __iomem *addr_l;
1760 u8 *p_counter;
1761
1762 uccf = ugeth->uccf;
1763
1764 p_82xx_addr_filt =
1765 (struct ucc_geth_82xx_address_filtering_pram __iomem *)
1766 ugeth->p_rx_glbl_pram->addressfiltering;
1767
1768 if (enet_addr_type == ENET_ADDR_TYPE_GROUP) {
1769 addr_h = &(p_82xx_addr_filt->gaddr_h);
1770 addr_l = &(p_82xx_addr_filt->gaddr_l);
1771 p_lh = &ugeth->group_hash_q;
1772 p_counter = &(ugeth->numGroupAddrInHash);
1773 } else if (enet_addr_type == ENET_ADDR_TYPE_INDIVIDUAL) {
1774 addr_h = &(p_82xx_addr_filt->iaddr_h);
1775 addr_l = &(p_82xx_addr_filt->iaddr_l);
1776 p_lh = &ugeth->ind_hash_q;
1777 p_counter = &(ugeth->numIndAddrInHash);
1778 } else
1779 return -EINVAL;
1780
1781 comm_dir = 0;
1782 if (uccf->enabled_tx)
1783 comm_dir |= COMM_DIR_TX;
1784 if (uccf->enabled_rx)
1785 comm_dir |= COMM_DIR_RX;
1786 if (comm_dir)
1787 ugeth_disable(ugeth, comm_dir);
1788
1789 /* Clear the hash table. */
1790 out_be32(addr_h, 0x00000000);
1791 out_be32(addr_l, 0x00000000);
1792
1793 if (!p_lh)
1794 return 0;
1795
1796 num = *p_counter;
1797
1798 /* Delete all remaining CQ elements */
1799 for (i = 0; i < num; i++)
1800 put_enet_addr_container(ENET_ADDR_CONT_ENTRY(dequeue(p_lh)));
1801
1802 *p_counter = 0;
1803
1804 if (comm_dir)
1805 ugeth_enable(ugeth, comm_dir);
1806
1807 return 0;
1808 }
1809
1810 static int ugeth_82xx_filtering_clear_addr_in_paddr(struct ucc_geth_private *ugeth,
1811 u8 paddr_num)
1812 {
1813 ugeth->indAddrRegUsed[paddr_num] = 0; /* mark this paddr as not used */
1814 return hw_clear_addr_in_paddr(ugeth, paddr_num);/* clear in hardware */
1815 }
1816
1817 static void ucc_geth_memclean(struct ucc_geth_private *ugeth)
1818 {
1819 u16 i, j;
1820 u8 __iomem *bd;
1821
1822 if (!ugeth)
1823 return;
1824
1825 if (ugeth->uccf) {
1826 ucc_fast_free(ugeth->uccf);
1827 ugeth->uccf = NULL;
1828 }
1829
1830 if (ugeth->p_thread_data_tx) {
1831 qe_muram_free(ugeth->thread_dat_tx_offset);
1832 ugeth->p_thread_data_tx = NULL;
1833 }
1834 if (ugeth->p_thread_data_rx) {
1835 qe_muram_free(ugeth->thread_dat_rx_offset);
1836 ugeth->p_thread_data_rx = NULL;
1837 }
1838 if (ugeth->p_exf_glbl_param) {
1839 qe_muram_free(ugeth->exf_glbl_param_offset);
1840 ugeth->p_exf_glbl_param = NULL;
1841 }
1842 if (ugeth->p_rx_glbl_pram) {
1843 qe_muram_free(ugeth->rx_glbl_pram_offset);
1844 ugeth->p_rx_glbl_pram = NULL;
1845 }
1846 if (ugeth->p_tx_glbl_pram) {
1847 qe_muram_free(ugeth->tx_glbl_pram_offset);
1848 ugeth->p_tx_glbl_pram = NULL;
1849 }
1850 if (ugeth->p_send_q_mem_reg) {
1851 qe_muram_free(ugeth->send_q_mem_reg_offset);
1852 ugeth->p_send_q_mem_reg = NULL;
1853 }
1854 if (ugeth->p_scheduler) {
1855 qe_muram_free(ugeth->scheduler_offset);
1856 ugeth->p_scheduler = NULL;
1857 }
1858 if (ugeth->p_tx_fw_statistics_pram) {
1859 qe_muram_free(ugeth->tx_fw_statistics_pram_offset);
1860 ugeth->p_tx_fw_statistics_pram = NULL;
1861 }
1862 if (ugeth->p_rx_fw_statistics_pram) {
1863 qe_muram_free(ugeth->rx_fw_statistics_pram_offset);
1864 ugeth->p_rx_fw_statistics_pram = NULL;
1865 }
1866 if (ugeth->p_rx_irq_coalescing_tbl) {
1867 qe_muram_free(ugeth->rx_irq_coalescing_tbl_offset);
1868 ugeth->p_rx_irq_coalescing_tbl = NULL;
1869 }
1870 if (ugeth->p_rx_bd_qs_tbl) {
1871 qe_muram_free(ugeth->rx_bd_qs_tbl_offset);
1872 ugeth->p_rx_bd_qs_tbl = NULL;
1873 }
1874 if (ugeth->p_init_enet_param_shadow) {
1875 return_init_enet_entries(ugeth,
1876 &(ugeth->p_init_enet_param_shadow->
1877 rxthread[0]),
1878 ENET_INIT_PARAM_MAX_ENTRIES_RX,
1879 ugeth->ug_info->riscRx, 1);
1880 return_init_enet_entries(ugeth,
1881 &(ugeth->p_init_enet_param_shadow->
1882 txthread[0]),
1883 ENET_INIT_PARAM_MAX_ENTRIES_TX,
1884 ugeth->ug_info->riscTx, 0);
1885 kfree(ugeth->p_init_enet_param_shadow);
1886 ugeth->p_init_enet_param_shadow = NULL;
1887 }
1888 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
1889 bd = ugeth->p_tx_bd_ring[i];
1890 if (!bd)
1891 continue;
1892 for (j = 0; j < ugeth->ug_info->bdRingLenTx[i]; j++) {
1893 if (ugeth->tx_skbuff[i][j]) {
1894 dma_unmap_single(ugeth->dev,
1895 in_be32(&((struct qe_bd __iomem *)bd)->buf),
1896 (in_be32((u32 __iomem *)bd) &
1897 BD_LENGTH_MASK),
1898 DMA_TO_DEVICE);
1899 dev_kfree_skb_any(ugeth->tx_skbuff[i][j]);
1900 ugeth->tx_skbuff[i][j] = NULL;
1901 }
1902 }
1903
1904 kfree(ugeth->tx_skbuff[i]);
1905
1906 if (ugeth->p_tx_bd_ring[i]) {
1907 if (ugeth->ug_info->uf_info.bd_mem_part ==
1908 MEM_PART_SYSTEM)
1909 kfree((void *)ugeth->tx_bd_ring_offset[i]);
1910 else if (ugeth->ug_info->uf_info.bd_mem_part ==
1911 MEM_PART_MURAM)
1912 qe_muram_free(ugeth->tx_bd_ring_offset[i]);
1913 ugeth->p_tx_bd_ring[i] = NULL;
1914 }
1915 }
1916 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
1917 if (ugeth->p_rx_bd_ring[i]) {
1918 /* Return existing data buffers in ring */
1919 bd = ugeth->p_rx_bd_ring[i];
1920 for (j = 0; j < ugeth->ug_info->bdRingLenRx[i]; j++) {
1921 if (ugeth->rx_skbuff[i][j]) {
1922 dma_unmap_single(ugeth->dev,
1923 in_be32(&((struct qe_bd __iomem *)bd)->buf),
1924 ugeth->ug_info->
1925 uf_info.max_rx_buf_length +
1926 UCC_GETH_RX_DATA_BUF_ALIGNMENT,
1927 DMA_FROM_DEVICE);
1928 dev_kfree_skb_any(
1929 ugeth->rx_skbuff[i][j]);
1930 ugeth->rx_skbuff[i][j] = NULL;
1931 }
1932 bd += sizeof(struct qe_bd);
1933 }
1934
1935 kfree(ugeth->rx_skbuff[i]);
1936
1937 if (ugeth->ug_info->uf_info.bd_mem_part ==
1938 MEM_PART_SYSTEM)
1939 kfree((void *)ugeth->rx_bd_ring_offset[i]);
1940 else if (ugeth->ug_info->uf_info.bd_mem_part ==
1941 MEM_PART_MURAM)
1942 qe_muram_free(ugeth->rx_bd_ring_offset[i]);
1943 ugeth->p_rx_bd_ring[i] = NULL;
1944 }
1945 }
1946 while (!list_empty(&ugeth->group_hash_q))
1947 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
1948 (dequeue(&ugeth->group_hash_q)));
1949 while (!list_empty(&ugeth->ind_hash_q))
1950 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
1951 (dequeue(&ugeth->ind_hash_q)));
1952 if (ugeth->ug_regs) {
1953 iounmap(ugeth->ug_regs);
1954 ugeth->ug_regs = NULL;
1955 }
1956
1957 skb_queue_purge(&ugeth->rx_recycle);
1958 }
1959
1960 static void ucc_geth_set_multi(struct net_device *dev)
1961 {
1962 struct ucc_geth_private *ugeth;
1963 struct dev_mc_list *dmi;
1964 struct ucc_fast __iomem *uf_regs;
1965 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
1966 int i;
1967
1968 ugeth = netdev_priv(dev);
1969
1970 uf_regs = ugeth->uccf->uf_regs;
1971
1972 if (dev->flags & IFF_PROMISC) {
1973 setbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO);
1974 } else {
1975 clrbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO);
1976
1977 p_82xx_addr_filt =
1978 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->
1979 p_rx_glbl_pram->addressfiltering;
1980
1981 if (dev->flags & IFF_ALLMULTI) {
1982 /* Catch all multicast addresses, so set the
1983 * filter to all 1's.
1984 */
1985 out_be32(&p_82xx_addr_filt->gaddr_h, 0xffffffff);
1986 out_be32(&p_82xx_addr_filt->gaddr_l, 0xffffffff);
1987 } else {
1988 /* Clear filter and add the addresses in the list.
1989 */
1990 out_be32(&p_82xx_addr_filt->gaddr_h, 0x0);
1991 out_be32(&p_82xx_addr_filt->gaddr_l, 0x0);
1992
1993 dmi = dev->mc_list;
1994
1995 for (i = 0; i < dev->mc_count; i++, dmi = dmi->next) {
1996
1997 /* Only support group multicast for now.
1998 */
1999 if (!(dmi->dmi_addr[0] & 1))
2000 continue;
2001
2002 /* Ask CPM to run CRC and set bit in
2003 * filter mask.
2004 */
2005 hw_add_addr_in_hash(ugeth, dmi->dmi_addr);
2006 }
2007 }
2008 }
2009 }
2010
2011 static void ucc_geth_stop(struct ucc_geth_private *ugeth)
2012 {
2013 struct ucc_geth __iomem *ug_regs = ugeth->ug_regs;
2014 struct phy_device *phydev = ugeth->phydev;
2015
2016 ugeth_vdbg("%s: IN", __func__);
2017
2018 /* Disable the controller */
2019 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
2020
2021 /* Tell the kernel the link is down */
2022 phy_stop(phydev);
2023
2024 /* Mask all interrupts */
2025 out_be32(ugeth->uccf->p_uccm, 0x00000000);
2026
2027 /* Clear all interrupts */
2028 out_be32(ugeth->uccf->p_ucce, 0xffffffff);
2029
2030 /* Disable Rx and Tx */
2031 clrbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
2032
2033 phy_disconnect(ugeth->phydev);
2034 ugeth->phydev = NULL;
2035
2036 ucc_geth_memclean(ugeth);
2037 }
2038
2039 static int ucc_struct_init(struct ucc_geth_private *ugeth)
2040 {
2041 struct ucc_geth_info *ug_info;
2042 struct ucc_fast_info *uf_info;
2043 int i;
2044
2045 ug_info = ugeth->ug_info;
2046 uf_info = &ug_info->uf_info;
2047
2048 if (!((uf_info->bd_mem_part == MEM_PART_SYSTEM) ||
2049 (uf_info->bd_mem_part == MEM_PART_MURAM))) {
2050 if (netif_msg_probe(ugeth))
2051 ugeth_err("%s: Bad memory partition value.",
2052 __func__);
2053 return -EINVAL;
2054 }
2055
2056 /* Rx BD lengths */
2057 for (i = 0; i < ug_info->numQueuesRx; i++) {
2058 if ((ug_info->bdRingLenRx[i] < UCC_GETH_RX_BD_RING_SIZE_MIN) ||
2059 (ug_info->bdRingLenRx[i] %
2060 UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT)) {
2061 if (netif_msg_probe(ugeth))
2062 ugeth_err
2063 ("%s: Rx BD ring length must be multiple of 4, no smaller than 8.",
2064 __func__);
2065 return -EINVAL;
2066 }
2067 }
2068
2069 /* Tx BD lengths */
2070 for (i = 0; i < ug_info->numQueuesTx; i++) {
2071 if (ug_info->bdRingLenTx[i] < UCC_GETH_TX_BD_RING_SIZE_MIN) {
2072 if (netif_msg_probe(ugeth))
2073 ugeth_err
2074 ("%s: Tx BD ring length must be no smaller than 2.",
2075 __func__);
2076 return -EINVAL;
2077 }
2078 }
2079
2080 /* mrblr */
2081 if ((uf_info->max_rx_buf_length == 0) ||
2082 (uf_info->max_rx_buf_length % UCC_GETH_MRBLR_ALIGNMENT)) {
2083 if (netif_msg_probe(ugeth))
2084 ugeth_err
2085 ("%s: max_rx_buf_length must be non-zero multiple of 128.",
2086 __func__);
2087 return -EINVAL;
2088 }
2089
2090 /* num Tx queues */
2091 if (ug_info->numQueuesTx > NUM_TX_QUEUES) {
2092 if (netif_msg_probe(ugeth))
2093 ugeth_err("%s: number of tx queues too large.", __func__);
2094 return -EINVAL;
2095 }
2096
2097 /* num Rx queues */
2098 if (ug_info->numQueuesRx > NUM_RX_QUEUES) {
2099 if (netif_msg_probe(ugeth))
2100 ugeth_err("%s: number of rx queues too large.", __func__);
2101 return -EINVAL;
2102 }
2103
2104 /* l2qt */
2105 for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++) {
2106 if (ug_info->l2qt[i] >= ug_info->numQueuesRx) {
2107 if (netif_msg_probe(ugeth))
2108 ugeth_err
2109 ("%s: VLAN priority table entry must not be"
2110 " larger than number of Rx queues.",
2111 __func__);
2112 return -EINVAL;
2113 }
2114 }
2115
2116 /* l3qt */
2117 for (i = 0; i < UCC_GETH_IP_PRIORITY_MAX; i++) {
2118 if (ug_info->l3qt[i] >= ug_info->numQueuesRx) {
2119 if (netif_msg_probe(ugeth))
2120 ugeth_err
2121 ("%s: IP priority table entry must not be"
2122 " larger than number of Rx queues.",
2123 __func__);
2124 return -EINVAL;
2125 }
2126 }
2127
2128 if (ug_info->cam && !ug_info->ecamptr) {
2129 if (netif_msg_probe(ugeth))
2130 ugeth_err("%s: If cam mode is chosen, must supply cam ptr.",
2131 __func__);
2132 return -EINVAL;
2133 }
2134
2135 if ((ug_info->numStationAddresses !=
2136 UCC_GETH_NUM_OF_STATION_ADDRESSES_1)
2137 && ug_info->rxExtendedFiltering) {
2138 if (netif_msg_probe(ugeth))
2139 ugeth_err("%s: Number of station addresses greater than 1 "
2140 "not allowed in extended parsing mode.",
2141 __func__);
2142 return -EINVAL;
2143 }
2144
2145 /* Generate uccm_mask for receive */
2146 uf_info->uccm_mask = ug_info->eventRegMask & UCCE_OTHER;/* Errors */
2147 for (i = 0; i < ug_info->numQueuesRx; i++)
2148 uf_info->uccm_mask |= (UCC_GETH_UCCE_RXF0 << i);
2149
2150 for (i = 0; i < ug_info->numQueuesTx; i++)
2151 uf_info->uccm_mask |= (UCC_GETH_UCCE_TXB0 << i);
2152 /* Initialize the general fast UCC block. */
2153 if (ucc_fast_init(uf_info, &ugeth->uccf)) {
2154 if (netif_msg_probe(ugeth))
2155 ugeth_err("%s: Failed to init uccf.", __func__);
2156 return -ENOMEM;
2157 }
2158
2159 /* read the number of risc engines, update the riscTx and riscRx
2160 * if there are 4 riscs in QE
2161 */
2162 if (qe_get_num_of_risc() == 4) {
2163 ug_info->riscTx = QE_RISC_ALLOCATION_FOUR_RISCS;
2164 ug_info->riscRx = QE_RISC_ALLOCATION_FOUR_RISCS;
2165 }
2166
2167 ugeth->ug_regs = ioremap(uf_info->regs, sizeof(*ugeth->ug_regs));
2168 if (!ugeth->ug_regs) {
2169 if (netif_msg_probe(ugeth))
2170 ugeth_err("%s: Failed to ioremap regs.", __func__);
2171 return -ENOMEM;
2172 }
2173
2174 skb_queue_head_init(&ugeth->rx_recycle);
2175
2176 return 0;
2177 }
2178
2179 static int ucc_geth_startup(struct ucc_geth_private *ugeth)
2180 {
2181 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
2182 struct ucc_geth_init_pram __iomem *p_init_enet_pram;
2183 struct ucc_fast_private *uccf;
2184 struct ucc_geth_info *ug_info;
2185 struct ucc_fast_info *uf_info;
2186 struct ucc_fast __iomem *uf_regs;
2187 struct ucc_geth __iomem *ug_regs;
2188 int ret_val = -EINVAL;
2189 u32 remoder = UCC_GETH_REMODER_INIT;
2190 u32 init_enet_pram_offset, cecr_subblock, command;
2191 u32 ifstat, i, j, size, l2qt, l3qt, length;
2192 u16 temoder = UCC_GETH_TEMODER_INIT;
2193 u16 test;
2194 u8 function_code = 0;
2195 u8 __iomem *bd;
2196 u8 __iomem *endOfRing;
2197 u8 numThreadsRxNumerical, numThreadsTxNumerical;
2198
2199 ugeth_vdbg("%s: IN", __func__);
2200 uccf = ugeth->uccf;
2201 ug_info = ugeth->ug_info;
2202 uf_info = &ug_info->uf_info;
2203 uf_regs = uccf->uf_regs;
2204 ug_regs = ugeth->ug_regs;
2205
2206 switch (ug_info->numThreadsRx) {
2207 case UCC_GETH_NUM_OF_THREADS_1:
2208 numThreadsRxNumerical = 1;
2209 break;
2210 case UCC_GETH_NUM_OF_THREADS_2:
2211 numThreadsRxNumerical = 2;
2212 break;
2213 case UCC_GETH_NUM_OF_THREADS_4:
2214 numThreadsRxNumerical = 4;
2215 break;
2216 case UCC_GETH_NUM_OF_THREADS_6:
2217 numThreadsRxNumerical = 6;
2218 break;
2219 case UCC_GETH_NUM_OF_THREADS_8:
2220 numThreadsRxNumerical = 8;
2221 break;
2222 default:
2223 if (netif_msg_ifup(ugeth))
2224 ugeth_err("%s: Bad number of Rx threads value.",
2225 __func__);
2226 return -EINVAL;
2227 break;
2228 }
2229
2230 switch (ug_info->numThreadsTx) {
2231 case UCC_GETH_NUM_OF_THREADS_1:
2232 numThreadsTxNumerical = 1;
2233 break;
2234 case UCC_GETH_NUM_OF_THREADS_2:
2235 numThreadsTxNumerical = 2;
2236 break;
2237 case UCC_GETH_NUM_OF_THREADS_4:
2238 numThreadsTxNumerical = 4;
2239 break;
2240 case UCC_GETH_NUM_OF_THREADS_6:
2241 numThreadsTxNumerical = 6;
2242 break;
2243 case UCC_GETH_NUM_OF_THREADS_8:
2244 numThreadsTxNumerical = 8;
2245 break;
2246 default:
2247 if (netif_msg_ifup(ugeth))
2248 ugeth_err("%s: Bad number of Tx threads value.",
2249 __func__);
2250 return -EINVAL;
2251 break;
2252 }
2253
2254 /* Calculate rx_extended_features */
2255 ugeth->rx_non_dynamic_extended_features = ug_info->ipCheckSumCheck ||
2256 ug_info->ipAddressAlignment ||
2257 (ug_info->numStationAddresses !=
2258 UCC_GETH_NUM_OF_STATION_ADDRESSES_1);
2259
2260 ugeth->rx_extended_features = ugeth->rx_non_dynamic_extended_features ||
2261 (ug_info->vlanOperationTagged != UCC_GETH_VLAN_OPERATION_TAGGED_NOP)
2262 || (ug_info->vlanOperationNonTagged !=
2263 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP);
2264
2265 init_default_reg_vals(&uf_regs->upsmr,
2266 &ug_regs->maccfg1, &ug_regs->maccfg2);
2267
2268 /* Set UPSMR */
2269 /* For more details see the hardware spec. */
2270 init_rx_parameters(ug_info->bro,
2271 ug_info->rsh, ug_info->pro, &uf_regs->upsmr);
2272
2273 /* We're going to ignore other registers for now, */
2274 /* except as needed to get up and running */
2275
2276 /* Set MACCFG1 */
2277 /* For more details see the hardware spec. */
2278 init_flow_control_params(ug_info->aufc,
2279 ug_info->receiveFlowControl,
2280 ug_info->transmitFlowControl,
2281 ug_info->pausePeriod,
2282 ug_info->extensionField,
2283 &uf_regs->upsmr,
2284 &ug_regs->uempr, &ug_regs->maccfg1);
2285
2286 setbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
2287
2288 /* Set IPGIFG */
2289 /* For more details see the hardware spec. */
2290 ret_val = init_inter_frame_gap_params(ug_info->nonBackToBackIfgPart1,
2291 ug_info->nonBackToBackIfgPart2,
2292 ug_info->
2293 miminumInterFrameGapEnforcement,
2294 ug_info->backToBackInterFrameGap,
2295 &ug_regs->ipgifg);
2296 if (ret_val != 0) {
2297 if (netif_msg_ifup(ugeth))
2298 ugeth_err("%s: IPGIFG initialization parameter too large.",
2299 __func__);
2300 return ret_val;
2301 }
2302
2303 /* Set HAFDUP */
2304 /* For more details see the hardware spec. */
2305 ret_val = init_half_duplex_params(ug_info->altBeb,
2306 ug_info->backPressureNoBackoff,
2307 ug_info->noBackoff,
2308 ug_info->excessDefer,
2309 ug_info->altBebTruncation,
2310 ug_info->maxRetransmission,
2311 ug_info->collisionWindow,
2312 &ug_regs->hafdup);
2313 if (ret_val != 0) {
2314 if (netif_msg_ifup(ugeth))
2315 ugeth_err("%s: Half Duplex initialization parameter too large.",
2316 __func__);
2317 return ret_val;
2318 }
2319
2320 /* Set IFSTAT */
2321 /* For more details see the hardware spec. */
2322 /* Read only - resets upon read */
2323 ifstat = in_be32(&ug_regs->ifstat);
2324
2325 /* Clear UEMPR */
2326 /* For more details see the hardware spec. */
2327 out_be32(&ug_regs->uempr, 0);
2328
2329 /* Set UESCR */
2330 /* For more details see the hardware spec. */
2331 init_hw_statistics_gathering_mode((ug_info->statisticsMode &
2332 UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE),
2333 0, &uf_regs->upsmr, &ug_regs->uescr);
2334
2335 /* Allocate Tx bds */
2336 for (j = 0; j < ug_info->numQueuesTx; j++) {
2337 /* Allocate in multiple of
2338 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT,
2339 according to spec */
2340 length = ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd))
2341 / UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2342 * UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
2343 if ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)) %
2344 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2345 length += UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
2346 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2347 u32 align = 4;
2348 if (UCC_GETH_TX_BD_RING_ALIGNMENT > 4)
2349 align = UCC_GETH_TX_BD_RING_ALIGNMENT;
2350 ugeth->tx_bd_ring_offset[j] =
2351 (u32) kmalloc((u32) (length + align), GFP_KERNEL);
2352
2353 if (ugeth->tx_bd_ring_offset[j] != 0)
2354 ugeth->p_tx_bd_ring[j] =
2355 (u8 __iomem *)((ugeth->tx_bd_ring_offset[j] +
2356 align) & ~(align - 1));
2357 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2358 ugeth->tx_bd_ring_offset[j] =
2359 qe_muram_alloc(length,
2360 UCC_GETH_TX_BD_RING_ALIGNMENT);
2361 if (!IS_ERR_VALUE(ugeth->tx_bd_ring_offset[j]))
2362 ugeth->p_tx_bd_ring[j] =
2363 (u8 __iomem *) qe_muram_addr(ugeth->
2364 tx_bd_ring_offset[j]);
2365 }
2366 if (!ugeth->p_tx_bd_ring[j]) {
2367 if (netif_msg_ifup(ugeth))
2368 ugeth_err
2369 ("%s: Can not allocate memory for Tx bd rings.",
2370 __func__);
2371 return -ENOMEM;
2372 }
2373 /* Zero unused end of bd ring, according to spec */
2374 memset_io((void __iomem *)(ugeth->p_tx_bd_ring[j] +
2375 ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)), 0,
2376 length - ug_info->bdRingLenTx[j] * sizeof(struct qe_bd));
2377 }
2378
2379 /* Allocate Rx bds */
2380 for (j = 0; j < ug_info->numQueuesRx; j++) {
2381 length = ug_info->bdRingLenRx[j] * sizeof(struct qe_bd);
2382 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2383 u32 align = 4;
2384 if (UCC_GETH_RX_BD_RING_ALIGNMENT > 4)
2385 align = UCC_GETH_RX_BD_RING_ALIGNMENT;
2386 ugeth->rx_bd_ring_offset[j] =
2387 (u32) kmalloc((u32) (length + align), GFP_KERNEL);
2388 if (ugeth->rx_bd_ring_offset[j] != 0)
2389 ugeth->p_rx_bd_ring[j] =
2390 (u8 __iomem *)((ugeth->rx_bd_ring_offset[j] +
2391 align) & ~(align - 1));
2392 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2393 ugeth->rx_bd_ring_offset[j] =
2394 qe_muram_alloc(length,
2395 UCC_GETH_RX_BD_RING_ALIGNMENT);
2396 if (!IS_ERR_VALUE(ugeth->rx_bd_ring_offset[j]))
2397 ugeth->p_rx_bd_ring[j] =
2398 (u8 __iomem *) qe_muram_addr(ugeth->
2399 rx_bd_ring_offset[j]);
2400 }
2401 if (!ugeth->p_rx_bd_ring[j]) {
2402 if (netif_msg_ifup(ugeth))
2403 ugeth_err
2404 ("%s: Can not allocate memory for Rx bd rings.",
2405 __func__);
2406 return -ENOMEM;
2407 }
2408 }
2409
2410 /* Init Tx bds */
2411 for (j = 0; j < ug_info->numQueuesTx; j++) {
2412 /* Setup the skbuff rings */
2413 ugeth->tx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) *
2414 ugeth->ug_info->bdRingLenTx[j],
2415 GFP_KERNEL);
2416
2417 if (ugeth->tx_skbuff[j] == NULL) {
2418 if (netif_msg_ifup(ugeth))
2419 ugeth_err("%s: Could not allocate tx_skbuff",
2420 __func__);
2421 return -ENOMEM;
2422 }
2423
2424 for (i = 0; i < ugeth->ug_info->bdRingLenTx[j]; i++)
2425 ugeth->tx_skbuff[j][i] = NULL;
2426
2427 ugeth->skb_curtx[j] = ugeth->skb_dirtytx[j] = 0;
2428 bd = ugeth->confBd[j] = ugeth->txBd[j] = ugeth->p_tx_bd_ring[j];
2429 for (i = 0; i < ug_info->bdRingLenTx[j]; i++) {
2430 /* clear bd buffer */
2431 out_be32(&((struct qe_bd __iomem *)bd)->buf, 0);
2432 /* set bd status and length */
2433 out_be32((u32 __iomem *)bd, 0);
2434 bd += sizeof(struct qe_bd);
2435 }
2436 bd -= sizeof(struct qe_bd);
2437 /* set bd status and length */
2438 out_be32((u32 __iomem *)bd, T_W); /* for last BD set Wrap bit */
2439 }
2440
2441 /* Init Rx bds */
2442 for (j = 0; j < ug_info->numQueuesRx; j++) {
2443 /* Setup the skbuff rings */
2444 ugeth->rx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) *
2445 ugeth->ug_info->bdRingLenRx[j],
2446 GFP_KERNEL);
2447
2448 if (ugeth->rx_skbuff[j] == NULL) {
2449 if (netif_msg_ifup(ugeth))
2450 ugeth_err("%s: Could not allocate rx_skbuff",
2451 __func__);
2452 return -ENOMEM;
2453 }
2454
2455 for (i = 0; i < ugeth->ug_info->bdRingLenRx[j]; i++)
2456 ugeth->rx_skbuff[j][i] = NULL;
2457
2458 ugeth->skb_currx[j] = 0;
2459 bd = ugeth->rxBd[j] = ugeth->p_rx_bd_ring[j];
2460 for (i = 0; i < ug_info->bdRingLenRx[j]; i++) {
2461 /* set bd status and length */
2462 out_be32((u32 __iomem *)bd, R_I);
2463 /* clear bd buffer */
2464 out_be32(&((struct qe_bd __iomem *)bd)->buf, 0);
2465 bd += sizeof(struct qe_bd);
2466 }
2467 bd -= sizeof(struct qe_bd);
2468 /* set bd status and length */
2469 out_be32((u32 __iomem *)bd, R_W); /* for last BD set Wrap bit */
2470 }
2471
2472 /*
2473 * Global PRAM
2474 */
2475 /* Tx global PRAM */
2476 /* Allocate global tx parameter RAM page */
2477 ugeth->tx_glbl_pram_offset =
2478 qe_muram_alloc(sizeof(struct ucc_geth_tx_global_pram),
2479 UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT);
2480 if (IS_ERR_VALUE(ugeth->tx_glbl_pram_offset)) {
2481 if (netif_msg_ifup(ugeth))
2482 ugeth_err
2483 ("%s: Can not allocate DPRAM memory for p_tx_glbl_pram.",
2484 __func__);
2485 return -ENOMEM;
2486 }
2487 ugeth->p_tx_glbl_pram =
2488 (struct ucc_geth_tx_global_pram __iomem *) qe_muram_addr(ugeth->
2489 tx_glbl_pram_offset);
2490 /* Zero out p_tx_glbl_pram */
2491 memset_io((void __iomem *)ugeth->p_tx_glbl_pram, 0, sizeof(struct ucc_geth_tx_global_pram));
2492
2493 /* Fill global PRAM */
2494
2495 /* TQPTR */
2496 /* Size varies with number of Tx threads */
2497 ugeth->thread_dat_tx_offset =
2498 qe_muram_alloc(numThreadsTxNumerical *
2499 sizeof(struct ucc_geth_thread_data_tx) +
2500 32 * (numThreadsTxNumerical == 1),
2501 UCC_GETH_THREAD_DATA_ALIGNMENT);
2502 if (IS_ERR_VALUE(ugeth->thread_dat_tx_offset)) {
2503 if (netif_msg_ifup(ugeth))
2504 ugeth_err
2505 ("%s: Can not allocate DPRAM memory for p_thread_data_tx.",
2506 __func__);
2507 return -ENOMEM;
2508 }
2509
2510 ugeth->p_thread_data_tx =
2511 (struct ucc_geth_thread_data_tx __iomem *) qe_muram_addr(ugeth->
2512 thread_dat_tx_offset);
2513 out_be32(&ugeth->p_tx_glbl_pram->tqptr, ugeth->thread_dat_tx_offset);
2514
2515 /* vtagtable */
2516 for (i = 0; i < UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX; i++)
2517 out_be32(&ugeth->p_tx_glbl_pram->vtagtable[i],
2518 ug_info->vtagtable[i]);
2519
2520 /* iphoffset */
2521 for (i = 0; i < TX_IP_OFFSET_ENTRY_MAX; i++)
2522 out_8(&ugeth->p_tx_glbl_pram->iphoffset[i],
2523 ug_info->iphoffset[i]);
2524
2525 /* SQPTR */
2526 /* Size varies with number of Tx queues */
2527 ugeth->send_q_mem_reg_offset =
2528 qe_muram_alloc(ug_info->numQueuesTx *
2529 sizeof(struct ucc_geth_send_queue_qd),
2530 UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
2531 if (IS_ERR_VALUE(ugeth->send_q_mem_reg_offset)) {
2532 if (netif_msg_ifup(ugeth))
2533 ugeth_err
2534 ("%s: Can not allocate DPRAM memory for p_send_q_mem_reg.",
2535 __func__);
2536 return -ENOMEM;
2537 }
2538
2539 ugeth->p_send_q_mem_reg =
2540 (struct ucc_geth_send_queue_mem_region __iomem *) qe_muram_addr(ugeth->
2541 send_q_mem_reg_offset);
2542 out_be32(&ugeth->p_tx_glbl_pram->sqptr, ugeth->send_q_mem_reg_offset);
2543
2544 /* Setup the table */
2545 /* Assume BD rings are already established */
2546 for (i = 0; i < ug_info->numQueuesTx; i++) {
2547 endOfRing =
2548 ugeth->p_tx_bd_ring[i] + (ug_info->bdRingLenTx[i] -
2549 1) * sizeof(struct qe_bd);
2550 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
2551 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2552 (u32) virt_to_phys(ugeth->p_tx_bd_ring[i]));
2553 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2554 last_bd_completed_address,
2555 (u32) virt_to_phys(endOfRing));
2556 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
2557 MEM_PART_MURAM) {
2558 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2559 (u32) immrbar_virt_to_phys(ugeth->
2560 p_tx_bd_ring[i]));
2561 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2562 last_bd_completed_address,
2563 (u32) immrbar_virt_to_phys(endOfRing));
2564 }
2565 }
2566
2567 /* schedulerbasepointer */
2568
2569 if (ug_info->numQueuesTx > 1) {
2570 /* scheduler exists only if more than 1 tx queue */
2571 ugeth->scheduler_offset =
2572 qe_muram_alloc(sizeof(struct ucc_geth_scheduler),
2573 UCC_GETH_SCHEDULER_ALIGNMENT);
2574 if (IS_ERR_VALUE(ugeth->scheduler_offset)) {
2575 if (netif_msg_ifup(ugeth))
2576 ugeth_err
2577 ("%s: Can not allocate DPRAM memory for p_scheduler.",
2578 __func__);
2579 return -ENOMEM;
2580 }
2581
2582 ugeth->p_scheduler =
2583 (struct ucc_geth_scheduler __iomem *) qe_muram_addr(ugeth->
2584 scheduler_offset);
2585 out_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer,
2586 ugeth->scheduler_offset);
2587 /* Zero out p_scheduler */
2588 memset_io((void __iomem *)ugeth->p_scheduler, 0, sizeof(struct ucc_geth_scheduler));
2589
2590 /* Set values in scheduler */
2591 out_be32(&ugeth->p_scheduler->mblinterval,
2592 ug_info->mblinterval);
2593 out_be16(&ugeth->p_scheduler->nortsrbytetime,
2594 ug_info->nortsrbytetime);
2595 out_8(&ugeth->p_scheduler->fracsiz, ug_info->fracsiz);
2596 out_8(&ugeth->p_scheduler->strictpriorityq,
2597 ug_info->strictpriorityq);
2598 out_8(&ugeth->p_scheduler->txasap, ug_info->txasap);
2599 out_8(&ugeth->p_scheduler->extrabw, ug_info->extrabw);
2600 for (i = 0; i < NUM_TX_QUEUES; i++)
2601 out_8(&ugeth->p_scheduler->weightfactor[i],
2602 ug_info->weightfactor[i]);
2603
2604 /* Set pointers to cpucount registers in scheduler */
2605 ugeth->p_cpucount[0] = &(ugeth->p_scheduler->cpucount0);
2606 ugeth->p_cpucount[1] = &(ugeth->p_scheduler->cpucount1);
2607 ugeth->p_cpucount[2] = &(ugeth->p_scheduler->cpucount2);
2608 ugeth->p_cpucount[3] = &(ugeth->p_scheduler->cpucount3);
2609 ugeth->p_cpucount[4] = &(ugeth->p_scheduler->cpucount4);
2610 ugeth->p_cpucount[5] = &(ugeth->p_scheduler->cpucount5);
2611 ugeth->p_cpucount[6] = &(ugeth->p_scheduler->cpucount6);
2612 ugeth->p_cpucount[7] = &(ugeth->p_scheduler->cpucount7);
2613 }
2614
2615 /* schedulerbasepointer */
2616 /* TxRMON_PTR (statistics) */
2617 if (ug_info->
2618 statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX) {
2619 ugeth->tx_fw_statistics_pram_offset =
2620 qe_muram_alloc(sizeof
2621 (struct ucc_geth_tx_firmware_statistics_pram),
2622 UCC_GETH_TX_STATISTICS_ALIGNMENT);
2623 if (IS_ERR_VALUE(ugeth->tx_fw_statistics_pram_offset)) {
2624 if (netif_msg_ifup(ugeth))
2625 ugeth_err
2626 ("%s: Can not allocate DPRAM memory for"
2627 " p_tx_fw_statistics_pram.",
2628 __func__);
2629 return -ENOMEM;
2630 }
2631 ugeth->p_tx_fw_statistics_pram =
2632 (struct ucc_geth_tx_firmware_statistics_pram __iomem *)
2633 qe_muram_addr(ugeth->tx_fw_statistics_pram_offset);
2634 /* Zero out p_tx_fw_statistics_pram */
2635 memset_io((void __iomem *)ugeth->p_tx_fw_statistics_pram,
2636 0, sizeof(struct ucc_geth_tx_firmware_statistics_pram));
2637 }
2638
2639 /* temoder */
2640 /* Already has speed set */
2641
2642 if (ug_info->numQueuesTx > 1)
2643 temoder |= TEMODER_SCHEDULER_ENABLE;
2644 if (ug_info->ipCheckSumGenerate)
2645 temoder |= TEMODER_IP_CHECKSUM_GENERATE;
2646 temoder |= ((ug_info->numQueuesTx - 1) << TEMODER_NUM_OF_QUEUES_SHIFT);
2647 out_be16(&ugeth->p_tx_glbl_pram->temoder, temoder);
2648
2649 test = in_be16(&ugeth->p_tx_glbl_pram->temoder);
2650
2651 /* Function code register value to be used later */
2652 function_code = UCC_BMR_BO_BE | UCC_BMR_GBL;
2653 /* Required for QE */
2654
2655 /* function code register */
2656 out_be32(&ugeth->p_tx_glbl_pram->tstate, ((u32) function_code) << 24);
2657
2658 /* Rx global PRAM */
2659 /* Allocate global rx parameter RAM page */
2660 ugeth->rx_glbl_pram_offset =
2661 qe_muram_alloc(sizeof(struct ucc_geth_rx_global_pram),
2662 UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT);
2663 if (IS_ERR_VALUE(ugeth->rx_glbl_pram_offset)) {
2664 if (netif_msg_ifup(ugeth))
2665 ugeth_err
2666 ("%s: Can not allocate DPRAM memory for p_rx_glbl_pram.",
2667 __func__);
2668 return -ENOMEM;
2669 }
2670 ugeth->p_rx_glbl_pram =
2671 (struct ucc_geth_rx_global_pram __iomem *) qe_muram_addr(ugeth->
2672 rx_glbl_pram_offset);
2673 /* Zero out p_rx_glbl_pram */
2674 memset_io((void __iomem *)ugeth->p_rx_glbl_pram, 0, sizeof(struct ucc_geth_rx_global_pram));
2675
2676 /* Fill global PRAM */
2677
2678 /* RQPTR */
2679 /* Size varies with number of Rx threads */
2680 ugeth->thread_dat_rx_offset =
2681 qe_muram_alloc(numThreadsRxNumerical *
2682 sizeof(struct ucc_geth_thread_data_rx),
2683 UCC_GETH_THREAD_DATA_ALIGNMENT);
2684 if (IS_ERR_VALUE(ugeth->thread_dat_rx_offset)) {
2685 if (netif_msg_ifup(ugeth))
2686 ugeth_err
2687 ("%s: Can not allocate DPRAM memory for p_thread_data_rx.",
2688 __func__);
2689 return -ENOMEM;
2690 }
2691
2692 ugeth->p_thread_data_rx =
2693 (struct ucc_geth_thread_data_rx __iomem *) qe_muram_addr(ugeth->
2694 thread_dat_rx_offset);
2695 out_be32(&ugeth->p_rx_glbl_pram->rqptr, ugeth->thread_dat_rx_offset);
2696
2697 /* typeorlen */
2698 out_be16(&ugeth->p_rx_glbl_pram->typeorlen, ug_info->typeorlen);
2699
2700 /* rxrmonbaseptr (statistics) */
2701 if (ug_info->
2702 statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX) {
2703 ugeth->rx_fw_statistics_pram_offset =
2704 qe_muram_alloc(sizeof
2705 (struct ucc_geth_rx_firmware_statistics_pram),
2706 UCC_GETH_RX_STATISTICS_ALIGNMENT);
2707 if (IS_ERR_VALUE(ugeth->rx_fw_statistics_pram_offset)) {
2708 if (netif_msg_ifup(ugeth))
2709 ugeth_err
2710 ("%s: Can not allocate DPRAM memory for"
2711 " p_rx_fw_statistics_pram.", __func__);
2712 return -ENOMEM;
2713 }
2714 ugeth->p_rx_fw_statistics_pram =
2715 (struct ucc_geth_rx_firmware_statistics_pram __iomem *)
2716 qe_muram_addr(ugeth->rx_fw_statistics_pram_offset);
2717 /* Zero out p_rx_fw_statistics_pram */
2718 memset_io((void __iomem *)ugeth->p_rx_fw_statistics_pram, 0,
2719 sizeof(struct ucc_geth_rx_firmware_statistics_pram));
2720 }
2721
2722 /* intCoalescingPtr */
2723
2724 /* Size varies with number of Rx queues */
2725 ugeth->rx_irq_coalescing_tbl_offset =
2726 qe_muram_alloc(ug_info->numQueuesRx *
2727 sizeof(struct ucc_geth_rx_interrupt_coalescing_entry)
2728 + 4, UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT);
2729 if (IS_ERR_VALUE(ugeth->rx_irq_coalescing_tbl_offset)) {
2730 if (netif_msg_ifup(ugeth))
2731 ugeth_err
2732 ("%s: Can not allocate DPRAM memory for"
2733 " p_rx_irq_coalescing_tbl.", __func__);
2734 return -ENOMEM;
2735 }
2736
2737 ugeth->p_rx_irq_coalescing_tbl =
2738 (struct ucc_geth_rx_interrupt_coalescing_table __iomem *)
2739 qe_muram_addr(ugeth->rx_irq_coalescing_tbl_offset);
2740 out_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr,
2741 ugeth->rx_irq_coalescing_tbl_offset);
2742
2743 /* Fill interrupt coalescing table */
2744 for (i = 0; i < ug_info->numQueuesRx; i++) {
2745 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
2746 interruptcoalescingmaxvalue,
2747 ug_info->interruptcoalescingmaxvalue[i]);
2748 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
2749 interruptcoalescingcounter,
2750 ug_info->interruptcoalescingmaxvalue[i]);
2751 }
2752
2753 /* MRBLR */
2754 init_max_rx_buff_len(uf_info->max_rx_buf_length,
2755 &ugeth->p_rx_glbl_pram->mrblr);
2756 /* MFLR */
2757 out_be16(&ugeth->p_rx_glbl_pram->mflr, ug_info->maxFrameLength);
2758 /* MINFLR */
2759 init_min_frame_len(ug_info->minFrameLength,
2760 &ugeth->p_rx_glbl_pram->minflr,
2761 &ugeth->p_rx_glbl_pram->mrblr);
2762 /* MAXD1 */
2763 out_be16(&ugeth->p_rx_glbl_pram->maxd1, ug_info->maxD1Length);
2764 /* MAXD2 */
2765 out_be16(&ugeth->p_rx_glbl_pram->maxd2, ug_info->maxD2Length);
2766
2767 /* l2qt */
2768 l2qt = 0;
2769 for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++)
2770 l2qt |= (ug_info->l2qt[i] << (28 - 4 * i));
2771 out_be32(&ugeth->p_rx_glbl_pram->l2qt, l2qt);
2772
2773 /* l3qt */
2774 for (j = 0; j < UCC_GETH_IP_PRIORITY_MAX; j += 8) {
2775 l3qt = 0;
2776 for (i = 0; i < 8; i++)
2777 l3qt |= (ug_info->l3qt[j + i] << (28 - 4 * i));
2778 out_be32(&ugeth->p_rx_glbl_pram->l3qt[j/8], l3qt);
2779 }
2780
2781 /* vlantype */
2782 out_be16(&ugeth->p_rx_glbl_pram->vlantype, ug_info->vlantype);
2783
2784 /* vlantci */
2785 out_be16(&ugeth->p_rx_glbl_pram->vlantci, ug_info->vlantci);
2786
2787 /* ecamptr */
2788 out_be32(&ugeth->p_rx_glbl_pram->ecamptr, ug_info->ecamptr);
2789
2790 /* RBDQPTR */
2791 /* Size varies with number of Rx queues */
2792 ugeth->rx_bd_qs_tbl_offset =
2793 qe_muram_alloc(ug_info->numQueuesRx *
2794 (sizeof(struct ucc_geth_rx_bd_queues_entry) +
2795 sizeof(struct ucc_geth_rx_prefetched_bds)),
2796 UCC_GETH_RX_BD_QUEUES_ALIGNMENT);
2797 if (IS_ERR_VALUE(ugeth->rx_bd_qs_tbl_offset)) {
2798 if (netif_msg_ifup(ugeth))
2799 ugeth_err
2800 ("%s: Can not allocate DPRAM memory for p_rx_bd_qs_tbl.",
2801 __func__);
2802 return -ENOMEM;
2803 }
2804
2805 ugeth->p_rx_bd_qs_tbl =
2806 (struct ucc_geth_rx_bd_queues_entry __iomem *) qe_muram_addr(ugeth->
2807 rx_bd_qs_tbl_offset);
2808 out_be32(&ugeth->p_rx_glbl_pram->rbdqptr, ugeth->rx_bd_qs_tbl_offset);
2809 /* Zero out p_rx_bd_qs_tbl */
2810 memset_io((void __iomem *)ugeth->p_rx_bd_qs_tbl,
2811 0,
2812 ug_info->numQueuesRx * (sizeof(struct ucc_geth_rx_bd_queues_entry) +
2813 sizeof(struct ucc_geth_rx_prefetched_bds)));
2814
2815 /* Setup the table */
2816 /* Assume BD rings are already established */
2817 for (i = 0; i < ug_info->numQueuesRx; i++) {
2818 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
2819 out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
2820 (u32) virt_to_phys(ugeth->p_rx_bd_ring[i]));
2821 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
2822 MEM_PART_MURAM) {
2823 out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
2824 (u32) immrbar_virt_to_phys(ugeth->
2825 p_rx_bd_ring[i]));
2826 }
2827 /* rest of fields handled by QE */
2828 }
2829
2830 /* remoder */
2831 /* Already has speed set */
2832
2833 if (ugeth->rx_extended_features)
2834 remoder |= REMODER_RX_EXTENDED_FEATURES;
2835 if (ug_info->rxExtendedFiltering)
2836 remoder |= REMODER_RX_EXTENDED_FILTERING;
2837 if (ug_info->dynamicMaxFrameLength)
2838 remoder |= REMODER_DYNAMIC_MAX_FRAME_LENGTH;
2839 if (ug_info->dynamicMinFrameLength)
2840 remoder |= REMODER_DYNAMIC_MIN_FRAME_LENGTH;
2841 remoder |=
2842 ug_info->vlanOperationTagged << REMODER_VLAN_OPERATION_TAGGED_SHIFT;
2843 remoder |=
2844 ug_info->
2845 vlanOperationNonTagged << REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT;
2846 remoder |= ug_info->rxQoSMode << REMODER_RX_QOS_MODE_SHIFT;
2847 remoder |= ((ug_info->numQueuesRx - 1) << REMODER_NUM_OF_QUEUES_SHIFT);
2848 if (ug_info->ipCheckSumCheck)
2849 remoder |= REMODER_IP_CHECKSUM_CHECK;
2850 if (ug_info->ipAddressAlignment)
2851 remoder |= REMODER_IP_ADDRESS_ALIGNMENT;
2852 out_be32(&ugeth->p_rx_glbl_pram->remoder, remoder);
2853
2854 /* Note that this function must be called */
2855 /* ONLY AFTER p_tx_fw_statistics_pram */
2856 /* andp_UccGethRxFirmwareStatisticsPram are allocated ! */
2857 init_firmware_statistics_gathering_mode((ug_info->
2858 statisticsMode &
2859 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX),
2860 (ug_info->statisticsMode &
2861 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX),
2862 &ugeth->p_tx_glbl_pram->txrmonbaseptr,
2863 ugeth->tx_fw_statistics_pram_offset,
2864 &ugeth->p_rx_glbl_pram->rxrmonbaseptr,
2865 ugeth->rx_fw_statistics_pram_offset,
2866 &ugeth->p_tx_glbl_pram->temoder,
2867 &ugeth->p_rx_glbl_pram->remoder);
2868
2869 /* function code register */
2870 out_8(&ugeth->p_rx_glbl_pram->rstate, function_code);
2871
2872 /* initialize extended filtering */
2873 if (ug_info->rxExtendedFiltering) {
2874 if (!ug_info->extendedFilteringChainPointer) {
2875 if (netif_msg_ifup(ugeth))
2876 ugeth_err("%s: Null Extended Filtering Chain Pointer.",
2877 __func__);
2878 return -EINVAL;
2879 }
2880
2881 /* Allocate memory for extended filtering Mode Global
2882 Parameters */
2883 ugeth->exf_glbl_param_offset =
2884 qe_muram_alloc(sizeof(struct ucc_geth_exf_global_pram),
2885 UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT);
2886 if (IS_ERR_VALUE(ugeth->exf_glbl_param_offset)) {
2887 if (netif_msg_ifup(ugeth))
2888 ugeth_err
2889 ("%s: Can not allocate DPRAM memory for"
2890 " p_exf_glbl_param.", __func__);
2891 return -ENOMEM;
2892 }
2893
2894 ugeth->p_exf_glbl_param =
2895 (struct ucc_geth_exf_global_pram __iomem *) qe_muram_addr(ugeth->
2896 exf_glbl_param_offset);
2897 out_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam,
2898 ugeth->exf_glbl_param_offset);
2899 out_be32(&ugeth->p_exf_glbl_param->l2pcdptr,
2900 (u32) ug_info->extendedFilteringChainPointer);
2901
2902 } else { /* initialize 82xx style address filtering */
2903
2904 /* Init individual address recognition registers to disabled */
2905
2906 for (j = 0; j < NUM_OF_PADDRS; j++)
2907 ugeth_82xx_filtering_clear_addr_in_paddr(ugeth, (u8) j);
2908
2909 p_82xx_addr_filt =
2910 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->
2911 p_rx_glbl_pram->addressfiltering;
2912
2913 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
2914 ENET_ADDR_TYPE_GROUP);
2915 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
2916 ENET_ADDR_TYPE_INDIVIDUAL);
2917 }
2918
2919 /*
2920 * Initialize UCC at QE level
2921 */
2922
2923 command = QE_INIT_TX_RX;
2924
2925 /* Allocate shadow InitEnet command parameter structure.
2926 * This is needed because after the InitEnet command is executed,
2927 * the structure in DPRAM is released, because DPRAM is a premium
2928 * resource.
2929 * This shadow structure keeps a copy of what was done so that the
2930 * allocated resources can be released when the channel is freed.
2931 */
2932 if (!(ugeth->p_init_enet_param_shadow =
2933 kmalloc(sizeof(struct ucc_geth_init_pram), GFP_KERNEL))) {
2934 if (netif_msg_ifup(ugeth))
2935 ugeth_err
2936 ("%s: Can not allocate memory for"
2937 " p_UccInitEnetParamShadows.", __func__);
2938 return -ENOMEM;
2939 }
2940 /* Zero out *p_init_enet_param_shadow */
2941 memset((char *)ugeth->p_init_enet_param_shadow,
2942 0, sizeof(struct ucc_geth_init_pram));
2943
2944 /* Fill shadow InitEnet command parameter structure */
2945
2946 ugeth->p_init_enet_param_shadow->resinit1 =
2947 ENET_INIT_PARAM_MAGIC_RES_INIT1;
2948 ugeth->p_init_enet_param_shadow->resinit2 =
2949 ENET_INIT_PARAM_MAGIC_RES_INIT2;
2950 ugeth->p_init_enet_param_shadow->resinit3 =
2951 ENET_INIT_PARAM_MAGIC_RES_INIT3;
2952 ugeth->p_init_enet_param_shadow->resinit4 =
2953 ENET_INIT_PARAM_MAGIC_RES_INIT4;
2954 ugeth->p_init_enet_param_shadow->resinit5 =
2955 ENET_INIT_PARAM_MAGIC_RES_INIT5;
2956 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2957 ((u32) ug_info->numThreadsRx) << ENET_INIT_PARAM_RGF_SHIFT;
2958 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2959 ((u32) ug_info->numThreadsTx) << ENET_INIT_PARAM_TGF_SHIFT;
2960
2961 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2962 ugeth->rx_glbl_pram_offset | ug_info->riscRx;
2963 if ((ug_info->largestexternallookupkeysize !=
2964 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE)
2965 && (ug_info->largestexternallookupkeysize !=
2966 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
2967 && (ug_info->largestexternallookupkeysize !=
2968 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES)) {
2969 if (netif_msg_ifup(ugeth))
2970 ugeth_err("%s: Invalid largest External Lookup Key Size.",
2971 __func__);
2972 return -EINVAL;
2973 }
2974 ugeth->p_init_enet_param_shadow->largestexternallookupkeysize =
2975 ug_info->largestexternallookupkeysize;
2976 size = sizeof(struct ucc_geth_thread_rx_pram);
2977 if (ug_info->rxExtendedFiltering) {
2978 size += THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
2979 if (ug_info->largestexternallookupkeysize ==
2980 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
2981 size +=
2982 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
2983 if (ug_info->largestexternallookupkeysize ==
2984 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
2985 size +=
2986 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
2987 }
2988
2989 if ((ret_val = fill_init_enet_entries(ugeth, &(ugeth->
2990 p_init_enet_param_shadow->rxthread[0]),
2991 (u8) (numThreadsRxNumerical + 1)
2992 /* Rx needs one extra for terminator */
2993 , size, UCC_GETH_THREAD_RX_PRAM_ALIGNMENT,
2994 ug_info->riscRx, 1)) != 0) {
2995 if (netif_msg_ifup(ugeth))
2996 ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
2997 __func__);
2998 return ret_val;
2999 }
3000
3001 ugeth->p_init_enet_param_shadow->txglobal =
3002 ugeth->tx_glbl_pram_offset | ug_info->riscTx;
3003 if ((ret_val =
3004 fill_init_enet_entries(ugeth,
3005 &(ugeth->p_init_enet_param_shadow->
3006 txthread[0]), numThreadsTxNumerical,
3007 sizeof(struct ucc_geth_thread_tx_pram),
3008 UCC_GETH_THREAD_TX_PRAM_ALIGNMENT,
3009 ug_info->riscTx, 0)) != 0) {
3010 if (netif_msg_ifup(ugeth))
3011 ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
3012 __func__);
3013 return ret_val;
3014 }
3015
3016 /* Load Rx bds with buffers */
3017 for (i = 0; i < ug_info->numQueuesRx; i++) {
3018 if ((ret_val = rx_bd_buffer_set(ugeth, (u8) i)) != 0) {
3019 if (netif_msg_ifup(ugeth))
3020 ugeth_err("%s: Can not fill Rx bds with buffers.",
3021 __func__);
3022 return ret_val;
3023 }
3024 }
3025
3026 /* Allocate InitEnet command parameter structure */
3027 init_enet_pram_offset = qe_muram_alloc(sizeof(struct ucc_geth_init_pram), 4);
3028 if (IS_ERR_VALUE(init_enet_pram_offset)) {
3029 if (netif_msg_ifup(ugeth))
3030 ugeth_err
3031 ("%s: Can not allocate DPRAM memory for p_init_enet_pram.",
3032 __func__);
3033 return -ENOMEM;
3034 }
3035 p_init_enet_pram =
3036 (struct ucc_geth_init_pram __iomem *) qe_muram_addr(init_enet_pram_offset);
3037
3038 /* Copy shadow InitEnet command parameter structure into PRAM */
3039 out_8(&p_init_enet_pram->resinit1,
3040 ugeth->p_init_enet_param_shadow->resinit1);
3041 out_8(&p_init_enet_pram->resinit2,
3042 ugeth->p_init_enet_param_shadow->resinit2);
3043 out_8(&p_init_enet_pram->resinit3,
3044 ugeth->p_init_enet_param_shadow->resinit3);
3045 out_8(&p_init_enet_pram->resinit4,
3046 ugeth->p_init_enet_param_shadow->resinit4);
3047 out_be16(&p_init_enet_pram->resinit5,
3048 ugeth->p_init_enet_param_shadow->resinit5);
3049 out_8(&p_init_enet_pram->largestexternallookupkeysize,
3050 ugeth->p_init_enet_param_shadow->largestexternallookupkeysize);
3051 out_be32(&p_init_enet_pram->rgftgfrxglobal,
3052 ugeth->p_init_enet_param_shadow->rgftgfrxglobal);
3053 for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_RX; i++)
3054 out_be32(&p_init_enet_pram->rxthread[i],
3055 ugeth->p_init_enet_param_shadow->rxthread[i]);
3056 out_be32(&p_init_enet_pram->txglobal,
3057 ugeth->p_init_enet_param_shadow->txglobal);
3058 for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_TX; i++)
3059 out_be32(&p_init_enet_pram->txthread[i],
3060 ugeth->p_init_enet_param_shadow->txthread[i]);
3061
3062 /* Issue QE command */
3063 cecr_subblock =
3064 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
3065 qe_issue_cmd(command, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
3066 init_enet_pram_offset);
3067
3068 /* Free InitEnet command parameter */
3069 qe_muram_free(init_enet_pram_offset);
3070
3071 return 0;
3072 }
3073
3074 /* This is called by the kernel when a frame is ready for transmission. */
3075 /* It is pointed to by the dev->hard_start_xmit function pointer */
3076 static int ucc_geth_start_xmit(struct sk_buff *skb, struct net_device *dev)
3077 {
3078 struct ucc_geth_private *ugeth = netdev_priv(dev);
3079 #ifdef CONFIG_UGETH_TX_ON_DEMAND
3080 struct ucc_fast_private *uccf;
3081 #endif
3082 u8 __iomem *bd; /* BD pointer */
3083 u32 bd_status;
3084 u8 txQ = 0;
3085 unsigned long flags;
3086
3087 ugeth_vdbg("%s: IN", __func__);
3088
3089 spin_lock_irqsave(&ugeth->lock, flags);
3090
3091 dev->stats.tx_bytes += skb->len;
3092
3093 /* Start from the next BD that should be filled */
3094 bd = ugeth->txBd[txQ];
3095 bd_status = in_be32((u32 __iomem *)bd);
3096 /* Save the skb pointer so we can free it later */
3097 ugeth->tx_skbuff[txQ][ugeth->skb_curtx[txQ]] = skb;
3098
3099 /* Update the current skb pointer (wrapping if this was the last) */
3100 ugeth->skb_curtx[txQ] =
3101 (ugeth->skb_curtx[txQ] +
3102 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3103
3104 /* set up the buffer descriptor */
3105 out_be32(&((struct qe_bd __iomem *)bd)->buf,
3106 dma_map_single(ugeth->dev, skb->data,
3107 skb->len, DMA_TO_DEVICE));
3108
3109 /* printk(KERN_DEBUG"skb->data is 0x%x\n",skb->data); */
3110
3111 bd_status = (bd_status & T_W) | T_R | T_I | T_L | skb->len;
3112
3113 /* set bd status and length */
3114 out_be32((u32 __iomem *)bd, bd_status);
3115
3116 dev->trans_start = jiffies;
3117
3118 /* Move to next BD in the ring */
3119 if (!(bd_status & T_W))
3120 bd += sizeof(struct qe_bd);
3121 else
3122 bd = ugeth->p_tx_bd_ring[txQ];
3123
3124 /* If the next BD still needs to be cleaned up, then the bds
3125 are full. We need to tell the kernel to stop sending us stuff. */
3126 if (bd == ugeth->confBd[txQ]) {
3127 if (!netif_queue_stopped(dev))
3128 netif_stop_queue(dev);
3129 }
3130
3131 ugeth->txBd[txQ] = bd;
3132
3133 if (ugeth->p_scheduler) {
3134 ugeth->cpucount[txQ]++;
3135 /* Indicate to QE that there are more Tx bds ready for
3136 transmission */
3137 /* This is done by writing a running counter of the bd
3138 count to the scheduler PRAM. */
3139 out_be16(ugeth->p_cpucount[txQ], ugeth->cpucount[txQ]);
3140 }
3141
3142 #ifdef CONFIG_UGETH_TX_ON_DEMAND
3143 uccf = ugeth->uccf;
3144 out_be16(uccf->p_utodr, UCC_FAST_TOD);
3145 #endif
3146 spin_unlock_irqrestore(&ugeth->lock, flags);
3147
3148 return NETDEV_TX_OK;
3149 }
3150
3151 static int ucc_geth_rx(struct ucc_geth_private *ugeth, u8 rxQ, int rx_work_limit)
3152 {
3153 struct sk_buff *skb;
3154 u8 __iomem *bd;
3155 u16 length, howmany = 0;
3156 u32 bd_status;
3157 u8 *bdBuffer;
3158 struct net_device *dev;
3159
3160 ugeth_vdbg("%s: IN", __func__);
3161
3162 dev = ugeth->ndev;
3163
3164 /* collect received buffers */
3165 bd = ugeth->rxBd[rxQ];
3166
3167 bd_status = in_be32((u32 __iomem *)bd);
3168
3169 /* while there are received buffers and BD is full (~R_E) */
3170 while (!((bd_status & (R_E)) || (--rx_work_limit < 0))) {
3171 bdBuffer = (u8 *) in_be32(&((struct qe_bd __iomem *)bd)->buf);
3172 length = (u16) ((bd_status & BD_LENGTH_MASK) - 4);
3173 skb = ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]];
3174
3175 /* determine whether buffer is first, last, first and last
3176 (single buffer frame) or middle (not first and not last) */
3177 if (!skb ||
3178 (!(bd_status & (R_F | R_L))) ||
3179 (bd_status & R_ERRORS_FATAL)) {
3180 if (netif_msg_rx_err(ugeth))
3181 ugeth_err("%s, %d: ERROR!!! skb - 0x%08x",
3182 __func__, __LINE__, (u32) skb);
3183 if (skb) {
3184 skb->data = skb->head + NET_SKB_PAD;
3185 __skb_queue_head(&ugeth->rx_recycle, skb);
3186 }
3187
3188 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = NULL;
3189 dev->stats.rx_dropped++;
3190 } else {
3191 dev->stats.rx_packets++;
3192 howmany++;
3193
3194 /* Prep the skb for the packet */
3195 skb_put(skb, length);
3196
3197 /* Tell the skb what kind of packet this is */
3198 skb->protocol = eth_type_trans(skb, ugeth->ndev);
3199
3200 dev->stats.rx_bytes += length;
3201 /* Send the packet up the stack */
3202 netif_receive_skb(skb);
3203 }
3204
3205 skb = get_new_skb(ugeth, bd);
3206 if (!skb) {
3207 if (netif_msg_rx_err(ugeth))
3208 ugeth_warn("%s: No Rx Data Buffer", __func__);
3209 dev->stats.rx_dropped++;
3210 break;
3211 }
3212
3213 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = skb;
3214
3215 /* update to point at the next skb */
3216 ugeth->skb_currx[rxQ] =
3217 (ugeth->skb_currx[rxQ] +
3218 1) & RX_RING_MOD_MASK(ugeth->ug_info->bdRingLenRx[rxQ]);
3219
3220 if (bd_status & R_W)
3221 bd = ugeth->p_rx_bd_ring[rxQ];
3222 else
3223 bd += sizeof(struct qe_bd);
3224
3225 bd_status = in_be32((u32 __iomem *)bd);
3226 }
3227
3228 ugeth->rxBd[rxQ] = bd;
3229 return howmany;
3230 }
3231
3232 static int ucc_geth_tx(struct net_device *dev, u8 txQ)
3233 {
3234 /* Start from the next BD that should be filled */
3235 struct ucc_geth_private *ugeth = netdev_priv(dev);
3236 u8 __iomem *bd; /* BD pointer */
3237 u32 bd_status;
3238
3239 bd = ugeth->confBd[txQ];
3240 bd_status = in_be32((u32 __iomem *)bd);
3241
3242 /* Normal processing. */
3243 while ((bd_status & T_R) == 0) {
3244 struct sk_buff *skb;
3245
3246 /* BD contains already transmitted buffer. */
3247 /* Handle the transmitted buffer and release */
3248 /* the BD to be used with the current frame */
3249
3250 if ((bd == ugeth->txBd[txQ]) && (netif_queue_stopped(dev) == 0))
3251 break;
3252
3253 dev->stats.tx_packets++;
3254
3255 skb = ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]];
3256
3257 if (skb_queue_len(&ugeth->rx_recycle) < RX_BD_RING_LEN &&
3258 skb_recycle_check(skb,
3259 ugeth->ug_info->uf_info.max_rx_buf_length +
3260 UCC_GETH_RX_DATA_BUF_ALIGNMENT))
3261 __skb_queue_head(&ugeth->rx_recycle, skb);
3262 else
3263 dev_kfree_skb(skb);
3264
3265 ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]] = NULL;
3266 ugeth->skb_dirtytx[txQ] =
3267 (ugeth->skb_dirtytx[txQ] +
3268 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3269
3270 /* We freed a buffer, so now we can restart transmission */
3271 if (netif_queue_stopped(dev))
3272 netif_wake_queue(dev);
3273
3274 /* Advance the confirmation BD pointer */
3275 if (!(bd_status & T_W))
3276 bd += sizeof(struct qe_bd);
3277 else
3278 bd = ugeth->p_tx_bd_ring[txQ];
3279 bd_status = in_be32((u32 __iomem *)bd);
3280 }
3281 ugeth->confBd[txQ] = bd;
3282 return 0;
3283 }
3284
3285 static int ucc_geth_poll(struct napi_struct *napi, int budget)
3286 {
3287 struct ucc_geth_private *ugeth = container_of(napi, struct ucc_geth_private, napi);
3288 struct ucc_geth_info *ug_info;
3289 int howmany, i;
3290
3291 ug_info = ugeth->ug_info;
3292
3293 /* Tx event processing */
3294 spin_lock(&ugeth->lock);
3295 for (i = 0; i < ug_info->numQueuesTx; i++)
3296 ucc_geth_tx(ugeth->ndev, i);
3297 spin_unlock(&ugeth->lock);
3298
3299 howmany = 0;
3300 for (i = 0; i < ug_info->numQueuesRx; i++)
3301 howmany += ucc_geth_rx(ugeth, i, budget - howmany);
3302
3303 if (howmany < budget) {
3304 napi_complete(napi);
3305 setbits32(ugeth->uccf->p_uccm, UCCE_RX_EVENTS | UCCE_TX_EVENTS);
3306 }
3307
3308 return howmany;
3309 }
3310
3311 static irqreturn_t ucc_geth_irq_handler(int irq, void *info)
3312 {
3313 struct net_device *dev = info;
3314 struct ucc_geth_private *ugeth = netdev_priv(dev);
3315 struct ucc_fast_private *uccf;
3316 struct ucc_geth_info *ug_info;
3317 register u32 ucce;
3318 register u32 uccm;
3319
3320 ugeth_vdbg("%s: IN", __func__);
3321
3322 uccf = ugeth->uccf;
3323 ug_info = ugeth->ug_info;
3324
3325 /* read and clear events */
3326 ucce = (u32) in_be32(uccf->p_ucce);
3327 uccm = (u32) in_be32(uccf->p_uccm);
3328 ucce &= uccm;
3329 out_be32(uccf->p_ucce, ucce);
3330
3331 /* check for receive events that require processing */
3332 if (ucce & (UCCE_RX_EVENTS | UCCE_TX_EVENTS)) {
3333 if (napi_schedule_prep(&ugeth->napi)) {
3334 uccm &= ~(UCCE_RX_EVENTS | UCCE_TX_EVENTS);
3335 out_be32(uccf->p_uccm, uccm);
3336 __napi_schedule(&ugeth->napi);
3337 }
3338 }
3339
3340 /* Errors and other events */
3341 if (ucce & UCCE_OTHER) {
3342 if (ucce & UCC_GETH_UCCE_BSY)
3343 dev->stats.rx_errors++;
3344 if (ucce & UCC_GETH_UCCE_TXE)
3345 dev->stats.tx_errors++;
3346 }
3347
3348 return IRQ_HANDLED;
3349 }
3350
3351 #ifdef CONFIG_NET_POLL_CONTROLLER
3352 /*
3353 * Polling 'interrupt' - used by things like netconsole to send skbs
3354 * without having to re-enable interrupts. It's not called while
3355 * the interrupt routine is executing.
3356 */
3357 static void ucc_netpoll(struct net_device *dev)
3358 {
3359 struct ucc_geth_private *ugeth = netdev_priv(dev);
3360 int irq = ugeth->ug_info->uf_info.irq;
3361
3362 disable_irq(irq);
3363 ucc_geth_irq_handler(irq, dev);
3364 enable_irq(irq);
3365 }
3366 #endif /* CONFIG_NET_POLL_CONTROLLER */
3367
3368 static int ucc_geth_set_mac_addr(struct net_device *dev, void *p)
3369 {
3370 struct ucc_geth_private *ugeth = netdev_priv(dev);
3371 struct sockaddr *addr = p;
3372
3373 if (!is_valid_ether_addr(addr->sa_data))
3374 return -EADDRNOTAVAIL;
3375
3376 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3377
3378 /*
3379 * If device is not running, we will set mac addr register
3380 * when opening the device.
3381 */
3382 if (!netif_running(dev))
3383 return 0;
3384
3385 spin_lock_irq(&ugeth->lock);
3386 init_mac_station_addr_regs(dev->dev_addr[0],
3387 dev->dev_addr[1],
3388 dev->dev_addr[2],
3389 dev->dev_addr[3],
3390 dev->dev_addr[4],
3391 dev->dev_addr[5],
3392 &ugeth->ug_regs->macstnaddr1,
3393 &ugeth->ug_regs->macstnaddr2);
3394 spin_unlock_irq(&ugeth->lock);
3395
3396 return 0;
3397 }
3398
3399 static int ucc_geth_init_mac(struct ucc_geth_private *ugeth)
3400 {
3401 struct net_device *dev = ugeth->ndev;
3402 int err;
3403
3404 err = ucc_struct_init(ugeth);
3405 if (err) {
3406 if (netif_msg_ifup(ugeth))
3407 ugeth_err("%s: Cannot configure internal struct, "
3408 "aborting.", dev->name);
3409 goto err;
3410 }
3411
3412 err = ucc_geth_startup(ugeth);
3413 if (err) {
3414 if (netif_msg_ifup(ugeth))
3415 ugeth_err("%s: Cannot configure net device, aborting.",
3416 dev->name);
3417 goto err;
3418 }
3419
3420 err = adjust_enet_interface(ugeth);
3421 if (err) {
3422 if (netif_msg_ifup(ugeth))
3423 ugeth_err("%s: Cannot configure net device, aborting.",
3424 dev->name);
3425 goto err;
3426 }
3427
3428 /* Set MACSTNADDR1, MACSTNADDR2 */
3429 /* For more details see the hardware spec. */
3430 init_mac_station_addr_regs(dev->dev_addr[0],
3431 dev->dev_addr[1],
3432 dev->dev_addr[2],
3433 dev->dev_addr[3],
3434 dev->dev_addr[4],
3435 dev->dev_addr[5],
3436 &ugeth->ug_regs->macstnaddr1,
3437 &ugeth->ug_regs->macstnaddr2);
3438
3439 err = ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
3440 if (err) {
3441 if (netif_msg_ifup(ugeth))
3442 ugeth_err("%s: Cannot enable net device, aborting.", dev->name);
3443 goto err;
3444 }
3445
3446 return 0;
3447 err:
3448 ucc_geth_stop(ugeth);
3449 return err;
3450 }
3451
3452 /* Called when something needs to use the ethernet device */
3453 /* Returns 0 for success. */
3454 static int ucc_geth_open(struct net_device *dev)
3455 {
3456 struct ucc_geth_private *ugeth = netdev_priv(dev);
3457 int err;
3458
3459 ugeth_vdbg("%s: IN", __func__);
3460
3461 /* Test station address */
3462 if (dev->dev_addr[0] & ENET_GROUP_ADDR) {
3463 if (netif_msg_ifup(ugeth))
3464 ugeth_err("%s: Multicast address used for station "
3465 "address - is this what you wanted?",
3466 __func__);
3467 return -EINVAL;
3468 }
3469
3470 err = init_phy(dev);
3471 if (err) {
3472 if (netif_msg_ifup(ugeth))
3473 ugeth_err("%s: Cannot initialize PHY, aborting.",
3474 dev->name);
3475 return err;
3476 }
3477
3478 err = ucc_geth_init_mac(ugeth);
3479 if (err) {
3480 if (netif_msg_ifup(ugeth))
3481 ugeth_err("%s: Cannot initialize MAC, aborting.",
3482 dev->name);
3483 goto err;
3484 }
3485
3486 err = request_irq(ugeth->ug_info->uf_info.irq, ucc_geth_irq_handler,
3487 0, "UCC Geth", dev);
3488 if (err) {
3489 if (netif_msg_ifup(ugeth))
3490 ugeth_err("%s: Cannot get IRQ for net device, aborting.",
3491 dev->name);
3492 goto err;
3493 }
3494
3495 phy_start(ugeth->phydev);
3496 napi_enable(&ugeth->napi);
3497 netif_start_queue(dev);
3498
3499 device_set_wakeup_capable(&dev->dev,
3500 qe_alive_during_sleep() || ugeth->phydev->irq);
3501 device_set_wakeup_enable(&dev->dev, ugeth->wol_en);
3502
3503 return err;
3504
3505 err:
3506 ucc_geth_stop(ugeth);
3507 return err;
3508 }
3509
3510 /* Stops the kernel queue, and halts the controller */
3511 static int ucc_geth_close(struct net_device *dev)
3512 {
3513 struct ucc_geth_private *ugeth = netdev_priv(dev);
3514
3515 ugeth_vdbg("%s: IN", __func__);
3516
3517 napi_disable(&ugeth->napi);
3518
3519 ucc_geth_stop(ugeth);
3520
3521 free_irq(ugeth->ug_info->uf_info.irq, ugeth->ndev);
3522
3523 netif_stop_queue(dev);
3524
3525 return 0;
3526 }
3527
3528 /* Reopen device. This will reset the MAC and PHY. */
3529 static void ucc_geth_timeout_work(struct work_struct *work)
3530 {
3531 struct ucc_geth_private *ugeth;
3532 struct net_device *dev;
3533
3534 ugeth = container_of(work, struct ucc_geth_private, timeout_work);
3535 dev = ugeth->ndev;
3536
3537 ugeth_vdbg("%s: IN", __func__);
3538
3539 dev->stats.tx_errors++;
3540
3541 ugeth_dump_regs(ugeth);
3542
3543 if (dev->flags & IFF_UP) {
3544 /*
3545 * Must reset MAC *and* PHY. This is done by reopening
3546 * the device.
3547 */
3548 ucc_geth_close(dev);
3549 ucc_geth_open(dev);
3550 }
3551
3552 netif_tx_schedule_all(dev);
3553 }
3554
3555 /*
3556 * ucc_geth_timeout gets called when a packet has not been
3557 * transmitted after a set amount of time.
3558 */
3559 static void ucc_geth_timeout(struct net_device *dev)
3560 {
3561 struct ucc_geth_private *ugeth = netdev_priv(dev);
3562
3563 netif_carrier_off(dev);
3564 schedule_work(&ugeth->timeout_work);
3565 }
3566
3567
3568 #ifdef CONFIG_PM
3569
3570 static int ucc_geth_suspend(struct of_device *ofdev, pm_message_t state)
3571 {
3572 struct net_device *ndev = dev_get_drvdata(&ofdev->dev);
3573 struct ucc_geth_private *ugeth = netdev_priv(ndev);
3574
3575 if (!netif_running(ndev))
3576 return 0;
3577
3578 napi_disable(&ugeth->napi);
3579
3580 /*
3581 * Disable the controller, otherwise we'll wakeup on any network
3582 * activity.
3583 */
3584 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
3585
3586 if (ugeth->wol_en & WAKE_MAGIC) {
3587 setbits32(ugeth->uccf->p_uccm, UCC_GETH_UCCE_MPD);
3588 setbits32(&ugeth->ug_regs->maccfg2, MACCFG2_MPE);
3589 ucc_fast_enable(ugeth->uccf, COMM_DIR_RX_AND_TX);
3590 } else if (!(ugeth->wol_en & WAKE_PHY)) {
3591 phy_stop(ugeth->phydev);
3592 }
3593
3594 return 0;
3595 }
3596
3597 static int ucc_geth_resume(struct of_device *ofdev)
3598 {
3599 struct net_device *ndev = dev_get_drvdata(&ofdev->dev);
3600 struct ucc_geth_private *ugeth = netdev_priv(ndev);
3601 int err;
3602
3603 if (!netif_running(ndev))
3604 return 0;
3605
3606 if (qe_alive_during_sleep()) {
3607 if (ugeth->wol_en & WAKE_MAGIC) {
3608 ucc_fast_disable(ugeth->uccf, COMM_DIR_RX_AND_TX);
3609 clrbits32(&ugeth->ug_regs->maccfg2, MACCFG2_MPE);
3610 clrbits32(ugeth->uccf->p_uccm, UCC_GETH_UCCE_MPD);
3611 }
3612 ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
3613 } else {
3614 /*
3615 * Full reinitialization is required if QE shuts down
3616 * during sleep.
3617 */
3618 ucc_geth_memclean(ugeth);
3619
3620 err = ucc_geth_init_mac(ugeth);
3621 if (err) {
3622 ugeth_err("%s: Cannot initialize MAC, aborting.",
3623 ndev->name);
3624 return err;
3625 }
3626 }
3627
3628 ugeth->oldlink = 0;
3629 ugeth->oldspeed = 0;
3630 ugeth->oldduplex = -1;
3631
3632 phy_stop(ugeth->phydev);
3633 phy_start(ugeth->phydev);
3634
3635 napi_enable(&ugeth->napi);
3636 netif_start_queue(ndev);
3637
3638 return 0;
3639 }
3640
3641 #else
3642 #define ucc_geth_suspend NULL
3643 #define ucc_geth_resume NULL
3644 #endif
3645
3646 static phy_interface_t to_phy_interface(const char *phy_connection_type)
3647 {
3648 if (strcasecmp(phy_connection_type, "mii") == 0)
3649 return PHY_INTERFACE_MODE_MII;
3650 if (strcasecmp(phy_connection_type, "gmii") == 0)
3651 return PHY_INTERFACE_MODE_GMII;
3652 if (strcasecmp(phy_connection_type, "tbi") == 0)
3653 return PHY_INTERFACE_MODE_TBI;
3654 if (strcasecmp(phy_connection_type, "rmii") == 0)
3655 return PHY_INTERFACE_MODE_RMII;
3656 if (strcasecmp(phy_connection_type, "rgmii") == 0)
3657 return PHY_INTERFACE_MODE_RGMII;
3658 if (strcasecmp(phy_connection_type, "rgmii-id") == 0)
3659 return PHY_INTERFACE_MODE_RGMII_ID;
3660 if (strcasecmp(phy_connection_type, "rgmii-txid") == 0)
3661 return PHY_INTERFACE_MODE_RGMII_TXID;
3662 if (strcasecmp(phy_connection_type, "rgmii-rxid") == 0)
3663 return PHY_INTERFACE_MODE_RGMII_RXID;
3664 if (strcasecmp(phy_connection_type, "rtbi") == 0)
3665 return PHY_INTERFACE_MODE_RTBI;
3666 if (strcasecmp(phy_connection_type, "sgmii") == 0)
3667 return PHY_INTERFACE_MODE_SGMII;
3668
3669 return PHY_INTERFACE_MODE_MII;
3670 }
3671
3672 static const struct net_device_ops ucc_geth_netdev_ops = {
3673 .ndo_open = ucc_geth_open,
3674 .ndo_stop = ucc_geth_close,
3675 .ndo_start_xmit = ucc_geth_start_xmit,
3676 .ndo_validate_addr = eth_validate_addr,
3677 .ndo_set_mac_address = ucc_geth_set_mac_addr,
3678 .ndo_change_mtu = eth_change_mtu,
3679 .ndo_set_multicast_list = ucc_geth_set_multi,
3680 .ndo_tx_timeout = ucc_geth_timeout,
3681 #ifdef CONFIG_NET_POLL_CONTROLLER
3682 .ndo_poll_controller = ucc_netpoll,
3683 #endif
3684 };
3685
3686 static int ucc_geth_probe(struct of_device* ofdev, const struct of_device_id *match)
3687 {
3688 struct device *device = &ofdev->dev;
3689 struct device_node *np = ofdev->node;
3690 struct net_device *dev = NULL;
3691 struct ucc_geth_private *ugeth = NULL;
3692 struct ucc_geth_info *ug_info;
3693 struct resource res;
3694 int err, ucc_num, max_speed = 0;
3695 const unsigned int *prop;
3696 const char *sprop;
3697 const void *mac_addr;
3698 phy_interface_t phy_interface;
3699 static const int enet_to_speed[] = {
3700 SPEED_10, SPEED_10, SPEED_10,
3701 SPEED_100, SPEED_100, SPEED_100,
3702 SPEED_1000, SPEED_1000, SPEED_1000, SPEED_1000,
3703 };
3704 static const phy_interface_t enet_to_phy_interface[] = {
3705 PHY_INTERFACE_MODE_MII, PHY_INTERFACE_MODE_RMII,
3706 PHY_INTERFACE_MODE_RGMII, PHY_INTERFACE_MODE_MII,
3707 PHY_INTERFACE_MODE_RMII, PHY_INTERFACE_MODE_RGMII,
3708 PHY_INTERFACE_MODE_GMII, PHY_INTERFACE_MODE_RGMII,
3709 PHY_INTERFACE_MODE_TBI, PHY_INTERFACE_MODE_RTBI,
3710 PHY_INTERFACE_MODE_SGMII,
3711 };
3712
3713 ugeth_vdbg("%s: IN", __func__);
3714
3715 prop = of_get_property(np, "cell-index", NULL);
3716 if (!prop) {
3717 prop = of_get_property(np, "device-id", NULL);
3718 if (!prop)
3719 return -ENODEV;
3720 }
3721
3722 ucc_num = *prop - 1;
3723 if ((ucc_num < 0) || (ucc_num > 7))
3724 return -ENODEV;
3725
3726 ug_info = &ugeth_info[ucc_num];
3727 if (ug_info == NULL) {
3728 if (netif_msg_probe(&debug))
3729 ugeth_err("%s: [%d] Missing additional data!",
3730 __func__, ucc_num);
3731 return -ENODEV;
3732 }
3733
3734 ug_info->uf_info.ucc_num = ucc_num;
3735
3736 sprop = of_get_property(np, "rx-clock-name", NULL);
3737 if (sprop) {
3738 ug_info->uf_info.rx_clock = qe_clock_source(sprop);
3739 if ((ug_info->uf_info.rx_clock < QE_CLK_NONE) ||
3740 (ug_info->uf_info.rx_clock > QE_CLK24)) {
3741 printk(KERN_ERR
3742 "ucc_geth: invalid rx-clock-name property\n");
3743 return -EINVAL;
3744 }
3745 } else {
3746 prop = of_get_property(np, "rx-clock", NULL);
3747 if (!prop) {
3748 /* If both rx-clock-name and rx-clock are missing,
3749 we want to tell people to use rx-clock-name. */
3750 printk(KERN_ERR
3751 "ucc_geth: missing rx-clock-name property\n");
3752 return -EINVAL;
3753 }
3754 if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) {
3755 printk(KERN_ERR
3756 "ucc_geth: invalid rx-clock propperty\n");
3757 return -EINVAL;
3758 }
3759 ug_info->uf_info.rx_clock = *prop;
3760 }
3761
3762 sprop = of_get_property(np, "tx-clock-name", NULL);
3763 if (sprop) {
3764 ug_info->uf_info.tx_clock = qe_clock_source(sprop);
3765 if ((ug_info->uf_info.tx_clock < QE_CLK_NONE) ||
3766 (ug_info->uf_info.tx_clock > QE_CLK24)) {
3767 printk(KERN_ERR
3768 "ucc_geth: invalid tx-clock-name property\n");
3769 return -EINVAL;
3770 }
3771 } else {
3772 prop = of_get_property(np, "tx-clock", NULL);
3773 if (!prop) {
3774 printk(KERN_ERR
3775 "ucc_geth: mising tx-clock-name property\n");
3776 return -EINVAL;
3777 }
3778 if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) {
3779 printk(KERN_ERR
3780 "ucc_geth: invalid tx-clock property\n");
3781 return -EINVAL;
3782 }
3783 ug_info->uf_info.tx_clock = *prop;
3784 }
3785
3786 err = of_address_to_resource(np, 0, &res);
3787 if (err)
3788 return -EINVAL;
3789
3790 ug_info->uf_info.regs = res.start;
3791 ug_info->uf_info.irq = irq_of_parse_and_map(np, 0);
3792
3793 ug_info->phy_node = of_parse_phandle(np, "phy-handle", 0);
3794
3795 /* Find the TBI PHY node. If it's not there, we don't support SGMII */
3796 ug_info->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
3797
3798 /* get the phy interface type, or default to MII */
3799 prop = of_get_property(np, "phy-connection-type", NULL);
3800 if (!prop) {
3801 /* handle interface property present in old trees */
3802 prop = of_get_property(ug_info->phy_node, "interface", NULL);
3803 if (prop != NULL) {
3804 phy_interface = enet_to_phy_interface[*prop];
3805 max_speed = enet_to_speed[*prop];
3806 } else
3807 phy_interface = PHY_INTERFACE_MODE_MII;
3808 } else {
3809 phy_interface = to_phy_interface((const char *)prop);
3810 }
3811
3812 /* get speed, or derive from PHY interface */
3813 if (max_speed == 0)
3814 switch (phy_interface) {
3815 case PHY_INTERFACE_MODE_GMII:
3816 case PHY_INTERFACE_MODE_RGMII:
3817 case PHY_INTERFACE_MODE_RGMII_ID:
3818 case PHY_INTERFACE_MODE_RGMII_RXID:
3819 case PHY_INTERFACE_MODE_RGMII_TXID:
3820 case PHY_INTERFACE_MODE_TBI:
3821 case PHY_INTERFACE_MODE_RTBI:
3822 case PHY_INTERFACE_MODE_SGMII:
3823 max_speed = SPEED_1000;
3824 break;
3825 default:
3826 max_speed = SPEED_100;
3827 break;
3828 }
3829
3830 if (max_speed == SPEED_1000) {
3831 /* configure muram FIFOs for gigabit operation */
3832 ug_info->uf_info.urfs = UCC_GETH_URFS_GIGA_INIT;
3833 ug_info->uf_info.urfet = UCC_GETH_URFET_GIGA_INIT;
3834 ug_info->uf_info.urfset = UCC_GETH_URFSET_GIGA_INIT;
3835 ug_info->uf_info.utfs = UCC_GETH_UTFS_GIGA_INIT;
3836 ug_info->uf_info.utfet = UCC_GETH_UTFET_GIGA_INIT;
3837 ug_info->uf_info.utftt = UCC_GETH_UTFTT_GIGA_INIT;
3838 ug_info->numThreadsTx = UCC_GETH_NUM_OF_THREADS_4;
3839
3840 /* If QE's snum number is 46 which means we need to support
3841 * 4 UECs at 1000Base-T simultaneously, we need to allocate
3842 * more Threads to Rx.
3843 */
3844 if (qe_get_num_of_snums() == 46)
3845 ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_6;
3846 else
3847 ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_4;
3848 }
3849
3850 if (netif_msg_probe(&debug))
3851 printk(KERN_INFO "ucc_geth: UCC%1d at 0x%8x (irq = %d) \n",
3852 ug_info->uf_info.ucc_num + 1, ug_info->uf_info.regs,
3853 ug_info->uf_info.irq);
3854
3855 /* Create an ethernet device instance */
3856 dev = alloc_etherdev(sizeof(*ugeth));
3857
3858 if (dev == NULL)
3859 return -ENOMEM;
3860
3861 ugeth = netdev_priv(dev);
3862 spin_lock_init(&ugeth->lock);
3863
3864 /* Create CQs for hash tables */
3865 INIT_LIST_HEAD(&ugeth->group_hash_q);
3866 INIT_LIST_HEAD(&ugeth->ind_hash_q);
3867
3868 dev_set_drvdata(device, dev);
3869
3870 /* Set the dev->base_addr to the gfar reg region */
3871 dev->base_addr = (unsigned long)(ug_info->uf_info.regs);
3872
3873 SET_NETDEV_DEV(dev, device);
3874
3875 /* Fill in the dev structure */
3876 uec_set_ethtool_ops(dev);
3877 dev->netdev_ops = &ucc_geth_netdev_ops;
3878 dev->watchdog_timeo = TX_TIMEOUT;
3879 INIT_WORK(&ugeth->timeout_work, ucc_geth_timeout_work);
3880 netif_napi_add(dev, &ugeth->napi, ucc_geth_poll, 64);
3881 dev->mtu = 1500;
3882
3883 ugeth->msg_enable = netif_msg_init(debug.msg_enable, UGETH_MSG_DEFAULT);
3884 ugeth->phy_interface = phy_interface;
3885 ugeth->max_speed = max_speed;
3886
3887 err = register_netdev(dev);
3888 if (err) {
3889 if (netif_msg_probe(ugeth))
3890 ugeth_err("%s: Cannot register net device, aborting.",
3891 dev->name);
3892 free_netdev(dev);
3893 return err;
3894 }
3895
3896 mac_addr = of_get_mac_address(np);
3897 if (mac_addr)
3898 memcpy(dev->dev_addr, mac_addr, 6);
3899
3900 ugeth->ug_info = ug_info;
3901 ugeth->dev = device;
3902 ugeth->ndev = dev;
3903 ugeth->node = np;
3904
3905 return 0;
3906 }
3907
3908 static int ucc_geth_remove(struct of_device* ofdev)
3909 {
3910 struct device *device = &ofdev->dev;
3911 struct net_device *dev = dev_get_drvdata(device);
3912 struct ucc_geth_private *ugeth = netdev_priv(dev);
3913
3914 unregister_netdev(dev);
3915 free_netdev(dev);
3916 ucc_geth_memclean(ugeth);
3917 dev_set_drvdata(device, NULL);
3918
3919 return 0;
3920 }
3921
3922 static struct of_device_id ucc_geth_match[] = {
3923 {
3924 .type = "network",
3925 .compatible = "ucc_geth",
3926 },
3927 {},
3928 };
3929
3930 MODULE_DEVICE_TABLE(of, ucc_geth_match);
3931
3932 static struct of_platform_driver ucc_geth_driver = {
3933 .name = DRV_NAME,
3934 .match_table = ucc_geth_match,
3935 .probe = ucc_geth_probe,
3936 .remove = ucc_geth_remove,
3937 .suspend = ucc_geth_suspend,
3938 .resume = ucc_geth_resume,
3939 };
3940
3941 static int __init ucc_geth_init(void)
3942 {
3943 int i, ret;
3944
3945 if (netif_msg_drv(&debug))
3946 printk(KERN_INFO "ucc_geth: " DRV_DESC "\n");
3947 for (i = 0; i < 8; i++)
3948 memcpy(&(ugeth_info[i]), &ugeth_primary_info,
3949 sizeof(ugeth_primary_info));
3950
3951 ret = of_register_platform_driver(&ucc_geth_driver);
3952
3953 return ret;
3954 }
3955
3956 static void __exit ucc_geth_exit(void)
3957 {
3958 of_unregister_platform_driver(&ucc_geth_driver);
3959 }
3960
3961 module_init(ucc_geth_init);
3962 module_exit(ucc_geth_exit);
3963
3964 MODULE_AUTHOR("Freescale Semiconductor, Inc");
3965 MODULE_DESCRIPTION(DRV_DESC);
3966 MODULE_VERSION(DRV_VERSION);
3967 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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