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[deliverable/linux.git] / drivers / net / usb / asix.c
1 /*
2 * ASIX AX8817X based USB 2.0 Ethernet Devices
3 * Copyright (C) 2003-2006 David Hollis <dhollis@davehollis.com>
4 * Copyright (C) 2005 Phil Chang <pchang23@sbcglobal.net>
5 * Copyright (C) 2006 James Painter <jamie.painter@iname.com>
6 * Copyright (c) 2002-2003 TiVo Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23 // #define DEBUG // error path messages, extra info
24 // #define VERBOSE // more; success messages
25
26 #include <linux/module.h>
27 #include <linux/kmod.h>
28 #include <linux/init.h>
29 #include <linux/netdevice.h>
30 #include <linux/etherdevice.h>
31 #include <linux/ethtool.h>
32 #include <linux/workqueue.h>
33 #include <linux/mii.h>
34 #include <linux/usb.h>
35 #include <linux/crc32.h>
36 #include <linux/usb/usbnet.h>
37 #include <linux/slab.h>
38
39 #define DRIVER_VERSION "08-Nov-2011"
40 #define DRIVER_NAME "asix"
41
42 /* ASIX AX8817X based USB 2.0 Ethernet Devices */
43
44 #define AX_CMD_SET_SW_MII 0x06
45 #define AX_CMD_READ_MII_REG 0x07
46 #define AX_CMD_WRITE_MII_REG 0x08
47 #define AX_CMD_SET_HW_MII 0x0a
48 #define AX_CMD_READ_EEPROM 0x0b
49 #define AX_CMD_WRITE_EEPROM 0x0c
50 #define AX_CMD_WRITE_ENABLE 0x0d
51 #define AX_CMD_WRITE_DISABLE 0x0e
52 #define AX_CMD_READ_RX_CTL 0x0f
53 #define AX_CMD_WRITE_RX_CTL 0x10
54 #define AX_CMD_READ_IPG012 0x11
55 #define AX_CMD_WRITE_IPG0 0x12
56 #define AX_CMD_WRITE_IPG1 0x13
57 #define AX_CMD_READ_NODE_ID 0x13
58 #define AX_CMD_WRITE_NODE_ID 0x14
59 #define AX_CMD_WRITE_IPG2 0x14
60 #define AX_CMD_WRITE_MULTI_FILTER 0x16
61 #define AX88172_CMD_READ_NODE_ID 0x17
62 #define AX_CMD_READ_PHY_ID 0x19
63 #define AX_CMD_READ_MEDIUM_STATUS 0x1a
64 #define AX_CMD_WRITE_MEDIUM_MODE 0x1b
65 #define AX_CMD_READ_MONITOR_MODE 0x1c
66 #define AX_CMD_WRITE_MONITOR_MODE 0x1d
67 #define AX_CMD_READ_GPIOS 0x1e
68 #define AX_CMD_WRITE_GPIOS 0x1f
69 #define AX_CMD_SW_RESET 0x20
70 #define AX_CMD_SW_PHY_STATUS 0x21
71 #define AX_CMD_SW_PHY_SELECT 0x22
72
73 #define AX_MONITOR_MODE 0x01
74 #define AX_MONITOR_LINK 0x02
75 #define AX_MONITOR_MAGIC 0x04
76 #define AX_MONITOR_HSFS 0x10
77
78 /* AX88172 Medium Status Register values */
79 #define AX88172_MEDIUM_FD 0x02
80 #define AX88172_MEDIUM_TX 0x04
81 #define AX88172_MEDIUM_FC 0x10
82 #define AX88172_MEDIUM_DEFAULT \
83 ( AX88172_MEDIUM_FD | AX88172_MEDIUM_TX | AX88172_MEDIUM_FC )
84
85 #define AX_MCAST_FILTER_SIZE 8
86 #define AX_MAX_MCAST 64
87
88 #define AX_SWRESET_CLEAR 0x00
89 #define AX_SWRESET_RR 0x01
90 #define AX_SWRESET_RT 0x02
91 #define AX_SWRESET_PRTE 0x04
92 #define AX_SWRESET_PRL 0x08
93 #define AX_SWRESET_BZ 0x10
94 #define AX_SWRESET_IPRL 0x20
95 #define AX_SWRESET_IPPD 0x40
96
97 #define AX88772_IPG0_DEFAULT 0x15
98 #define AX88772_IPG1_DEFAULT 0x0c
99 #define AX88772_IPG2_DEFAULT 0x12
100
101 /* AX88772 & AX88178 Medium Mode Register */
102 #define AX_MEDIUM_PF 0x0080
103 #define AX_MEDIUM_JFE 0x0040
104 #define AX_MEDIUM_TFC 0x0020
105 #define AX_MEDIUM_RFC 0x0010
106 #define AX_MEDIUM_ENCK 0x0008
107 #define AX_MEDIUM_AC 0x0004
108 #define AX_MEDIUM_FD 0x0002
109 #define AX_MEDIUM_GM 0x0001
110 #define AX_MEDIUM_SM 0x1000
111 #define AX_MEDIUM_SBP 0x0800
112 #define AX_MEDIUM_PS 0x0200
113 #define AX_MEDIUM_RE 0x0100
114
115 #define AX88178_MEDIUM_DEFAULT \
116 (AX_MEDIUM_PS | AX_MEDIUM_FD | AX_MEDIUM_AC | \
117 AX_MEDIUM_RFC | AX_MEDIUM_TFC | AX_MEDIUM_JFE | \
118 AX_MEDIUM_RE)
119
120 #define AX88772_MEDIUM_DEFAULT \
121 (AX_MEDIUM_FD | AX_MEDIUM_RFC | \
122 AX_MEDIUM_TFC | AX_MEDIUM_PS | \
123 AX_MEDIUM_AC | AX_MEDIUM_RE)
124
125 /* AX88772 & AX88178 RX_CTL values */
126 #define AX_RX_CTL_SO 0x0080
127 #define AX_RX_CTL_AP 0x0020
128 #define AX_RX_CTL_AM 0x0010
129 #define AX_RX_CTL_AB 0x0008
130 #define AX_RX_CTL_SEP 0x0004
131 #define AX_RX_CTL_AMALL 0x0002
132 #define AX_RX_CTL_PRO 0x0001
133 #define AX_RX_CTL_MFB_2048 0x0000
134 #define AX_RX_CTL_MFB_4096 0x0100
135 #define AX_RX_CTL_MFB_8192 0x0200
136 #define AX_RX_CTL_MFB_16384 0x0300
137
138 #define AX_DEFAULT_RX_CTL (AX_RX_CTL_SO | AX_RX_CTL_AB)
139
140 /* GPIO 0 .. 2 toggles */
141 #define AX_GPIO_GPO0EN 0x01 /* GPIO0 Output enable */
142 #define AX_GPIO_GPO_0 0x02 /* GPIO0 Output value */
143 #define AX_GPIO_GPO1EN 0x04 /* GPIO1 Output enable */
144 #define AX_GPIO_GPO_1 0x08 /* GPIO1 Output value */
145 #define AX_GPIO_GPO2EN 0x10 /* GPIO2 Output enable */
146 #define AX_GPIO_GPO_2 0x20 /* GPIO2 Output value */
147 #define AX_GPIO_RESERVED 0x40 /* Reserved */
148 #define AX_GPIO_RSE 0x80 /* Reload serial EEPROM */
149
150 #define AX_EEPROM_MAGIC 0xdeadbeef
151 #define AX88172_EEPROM_LEN 0x40
152 #define AX88772_EEPROM_LEN 0xff
153
154 #define PHY_MODE_MARVELL 0x0000
155 #define MII_MARVELL_LED_CTRL 0x0018
156 #define MII_MARVELL_STATUS 0x001b
157 #define MII_MARVELL_CTRL 0x0014
158
159 #define MARVELL_LED_MANUAL 0x0019
160
161 #define MARVELL_STATUS_HWCFG 0x0004
162
163 #define MARVELL_CTRL_TXDELAY 0x0002
164 #define MARVELL_CTRL_RXDELAY 0x0080
165
166 #define PHY_MODE_RTL8211CL 0x000C
167
168 /* This structure cannot exceed sizeof(unsigned long [5]) AKA 20 bytes */
169 struct asix_data {
170 u8 multi_filter[AX_MCAST_FILTER_SIZE];
171 u8 mac_addr[ETH_ALEN];
172 u8 phymode;
173 u8 ledmode;
174 u8 eeprom_len;
175 };
176
177 struct ax88172_int_data {
178 __le16 res1;
179 u8 link;
180 __le16 res2;
181 u8 status;
182 __le16 res3;
183 } __packed;
184
185 static int asix_read_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index,
186 u16 size, void *data)
187 {
188 void *buf;
189 int err = -ENOMEM;
190
191 netdev_dbg(dev->net, "asix_read_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n",
192 cmd, value, index, size);
193
194 buf = kmalloc(size, GFP_KERNEL);
195 if (!buf)
196 goto out;
197
198 err = usb_control_msg(
199 dev->udev,
200 usb_rcvctrlpipe(dev->udev, 0),
201 cmd,
202 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
203 value,
204 index,
205 buf,
206 size,
207 USB_CTRL_GET_TIMEOUT);
208 if (err == size)
209 memcpy(data, buf, size);
210 else if (err >= 0)
211 err = -EINVAL;
212 kfree(buf);
213
214 out:
215 return err;
216 }
217
218 static int asix_write_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index,
219 u16 size, void *data)
220 {
221 void *buf = NULL;
222 int err = -ENOMEM;
223
224 netdev_dbg(dev->net, "asix_write_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n",
225 cmd, value, index, size);
226
227 if (data) {
228 buf = kmemdup(data, size, GFP_KERNEL);
229 if (!buf)
230 goto out;
231 }
232
233 err = usb_control_msg(
234 dev->udev,
235 usb_sndctrlpipe(dev->udev, 0),
236 cmd,
237 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
238 value,
239 index,
240 buf,
241 size,
242 USB_CTRL_SET_TIMEOUT);
243 kfree(buf);
244
245 out:
246 return err;
247 }
248
249 static void asix_async_cmd_callback(struct urb *urb)
250 {
251 struct usb_ctrlrequest *req = (struct usb_ctrlrequest *)urb->context;
252 int status = urb->status;
253
254 if (status < 0)
255 printk(KERN_DEBUG "asix_async_cmd_callback() failed with %d",
256 status);
257
258 kfree(req);
259 usb_free_urb(urb);
260 }
261
262 static void
263 asix_write_cmd_async(struct usbnet *dev, u8 cmd, u16 value, u16 index,
264 u16 size, void *data)
265 {
266 struct usb_ctrlrequest *req;
267 int status;
268 struct urb *urb;
269
270 netdev_dbg(dev->net, "asix_write_cmd_async() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n",
271 cmd, value, index, size);
272
273 urb = usb_alloc_urb(0, GFP_ATOMIC);
274 if (!urb) {
275 netdev_err(dev->net, "Error allocating URB in write_cmd_async!\n");
276 return;
277 }
278
279 req = kmalloc(sizeof(struct usb_ctrlrequest), GFP_ATOMIC);
280 if (!req) {
281 netdev_err(dev->net, "Failed to allocate memory for control request\n");
282 usb_free_urb(urb);
283 return;
284 }
285
286 req->bRequestType = USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE;
287 req->bRequest = cmd;
288 req->wValue = cpu_to_le16(value);
289 req->wIndex = cpu_to_le16(index);
290 req->wLength = cpu_to_le16(size);
291
292 usb_fill_control_urb(urb, dev->udev,
293 usb_sndctrlpipe(dev->udev, 0),
294 (void *)req, data, size,
295 asix_async_cmd_callback, req);
296
297 status = usb_submit_urb(urb, GFP_ATOMIC);
298 if (status < 0) {
299 netdev_err(dev->net, "Error submitting the control message: status=%d\n",
300 status);
301 kfree(req);
302 usb_free_urb(urb);
303 }
304 }
305
306 static int asix_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
307 {
308 u8 *head;
309 u32 header;
310 char *packet;
311 struct sk_buff *ax_skb;
312 u16 size;
313
314 head = (u8 *) skb->data;
315 memcpy(&header, head, sizeof(header));
316 le32_to_cpus(&header);
317 packet = head + sizeof(header);
318
319 skb_pull(skb, 4);
320
321 while (skb->len > 0) {
322 if ((header & 0x07ff) != ((~header >> 16) & 0x07ff))
323 netdev_err(dev->net, "asix_rx_fixup() Bad Header Length\n");
324
325 /* get the packet length */
326 size = (u16) (header & 0x000007ff);
327
328 if ((skb->len) - ((size + 1) & 0xfffe) == 0) {
329 u8 alignment = (unsigned long)skb->data & 0x3;
330 if (alignment != 0x2) {
331 /*
332 * not 16bit aligned so use the room provided by
333 * the 32 bit header to align the data
334 *
335 * note we want 16bit alignment as MAC header is
336 * 14bytes thus ip header will be aligned on
337 * 32bit boundary so accessing ipheader elements
338 * using a cast to struct ip header wont cause
339 * an unaligned accesses.
340 */
341 u8 realignment = (alignment + 2) & 0x3;
342 memmove(skb->data - realignment,
343 skb->data,
344 size);
345 skb->data -= realignment;
346 skb_set_tail_pointer(skb, size);
347 }
348 return 2;
349 }
350
351 if (size > dev->net->mtu + ETH_HLEN) {
352 netdev_err(dev->net, "asix_rx_fixup() Bad RX Length %d\n",
353 size);
354 return 0;
355 }
356 ax_skb = skb_clone(skb, GFP_ATOMIC);
357 if (ax_skb) {
358 u8 alignment = (unsigned long)packet & 0x3;
359 ax_skb->len = size;
360
361 if (alignment != 0x2) {
362 /*
363 * not 16bit aligned use the room provided by
364 * the 32 bit header to align the data
365 */
366 u8 realignment = (alignment + 2) & 0x3;
367 memmove(packet - realignment, packet, size);
368 packet -= realignment;
369 }
370 ax_skb->data = packet;
371 skb_set_tail_pointer(ax_skb, size);
372 usbnet_skb_return(dev, ax_skb);
373 } else {
374 return 0;
375 }
376
377 skb_pull(skb, (size + 1) & 0xfffe);
378
379 if (skb->len == 0)
380 break;
381
382 head = (u8 *) skb->data;
383 memcpy(&header, head, sizeof(header));
384 le32_to_cpus(&header);
385 packet = head + sizeof(header);
386 skb_pull(skb, 4);
387 }
388
389 if (skb->len < 0) {
390 netdev_err(dev->net, "asix_rx_fixup() Bad SKB Length %d\n",
391 skb->len);
392 return 0;
393 }
394 return 1;
395 }
396
397 static struct sk_buff *asix_tx_fixup(struct usbnet *dev, struct sk_buff *skb,
398 gfp_t flags)
399 {
400 int padlen;
401 int headroom = skb_headroom(skb);
402 int tailroom = skb_tailroom(skb);
403 u32 packet_len;
404 u32 padbytes = 0xffff0000;
405
406 padlen = ((skb->len + 4) % 512) ? 0 : 4;
407
408 if ((!skb_cloned(skb)) &&
409 ((headroom + tailroom) >= (4 + padlen))) {
410 if ((headroom < 4) || (tailroom < padlen)) {
411 skb->data = memmove(skb->head + 4, skb->data, skb->len);
412 skb_set_tail_pointer(skb, skb->len);
413 }
414 } else {
415 struct sk_buff *skb2;
416 skb2 = skb_copy_expand(skb, 4, padlen, flags);
417 dev_kfree_skb_any(skb);
418 skb = skb2;
419 if (!skb)
420 return NULL;
421 }
422
423 skb_push(skb, 4);
424 packet_len = (((skb->len - 4) ^ 0x0000ffff) << 16) + (skb->len - 4);
425 cpu_to_le32s(&packet_len);
426 skb_copy_to_linear_data(skb, &packet_len, sizeof(packet_len));
427
428 if ((skb->len % 512) == 0) {
429 cpu_to_le32s(&padbytes);
430 memcpy(skb_tail_pointer(skb), &padbytes, sizeof(padbytes));
431 skb_put(skb, sizeof(padbytes));
432 }
433 return skb;
434 }
435
436 static void asix_status(struct usbnet *dev, struct urb *urb)
437 {
438 struct ax88172_int_data *event;
439 int link;
440
441 if (urb->actual_length < 8)
442 return;
443
444 event = urb->transfer_buffer;
445 link = event->link & 0x01;
446 if (netif_carrier_ok(dev->net) != link) {
447 if (link) {
448 netif_carrier_on(dev->net);
449 usbnet_defer_kevent (dev, EVENT_LINK_RESET );
450 } else
451 netif_carrier_off(dev->net);
452 netdev_dbg(dev->net, "Link Status is: %d\n", link);
453 }
454 }
455
456 static inline int asix_set_sw_mii(struct usbnet *dev)
457 {
458 int ret;
459 ret = asix_write_cmd(dev, AX_CMD_SET_SW_MII, 0x0000, 0, 0, NULL);
460 if (ret < 0)
461 netdev_err(dev->net, "Failed to enable software MII access\n");
462 return ret;
463 }
464
465 static inline int asix_set_hw_mii(struct usbnet *dev)
466 {
467 int ret;
468 ret = asix_write_cmd(dev, AX_CMD_SET_HW_MII, 0x0000, 0, 0, NULL);
469 if (ret < 0)
470 netdev_err(dev->net, "Failed to enable hardware MII access\n");
471 return ret;
472 }
473
474 static inline int asix_get_phy_addr(struct usbnet *dev)
475 {
476 u8 buf[2];
477 int ret = asix_read_cmd(dev, AX_CMD_READ_PHY_ID, 0, 0, 2, buf);
478
479 netdev_dbg(dev->net, "asix_get_phy_addr()\n");
480
481 if (ret < 0) {
482 netdev_err(dev->net, "Error reading PHYID register: %02x\n", ret);
483 goto out;
484 }
485 netdev_dbg(dev->net, "asix_get_phy_addr() returning 0x%04x\n",
486 *((__le16 *)buf));
487 ret = buf[1];
488
489 out:
490 return ret;
491 }
492
493 static int asix_sw_reset(struct usbnet *dev, u8 flags)
494 {
495 int ret;
496
497 ret = asix_write_cmd(dev, AX_CMD_SW_RESET, flags, 0, 0, NULL);
498 if (ret < 0)
499 netdev_err(dev->net, "Failed to send software reset: %02x\n", ret);
500
501 return ret;
502 }
503
504 static u16 asix_read_rx_ctl(struct usbnet *dev)
505 {
506 __le16 v;
507 int ret = asix_read_cmd(dev, AX_CMD_READ_RX_CTL, 0, 0, 2, &v);
508
509 if (ret < 0) {
510 netdev_err(dev->net, "Error reading RX_CTL register: %02x\n", ret);
511 goto out;
512 }
513 ret = le16_to_cpu(v);
514 out:
515 return ret;
516 }
517
518 static int asix_write_rx_ctl(struct usbnet *dev, u16 mode)
519 {
520 int ret;
521
522 netdev_dbg(dev->net, "asix_write_rx_ctl() - mode = 0x%04x\n", mode);
523 ret = asix_write_cmd(dev, AX_CMD_WRITE_RX_CTL, mode, 0, 0, NULL);
524 if (ret < 0)
525 netdev_err(dev->net, "Failed to write RX_CTL mode to 0x%04x: %02x\n",
526 mode, ret);
527
528 return ret;
529 }
530
531 static u16 asix_read_medium_status(struct usbnet *dev)
532 {
533 __le16 v;
534 int ret = asix_read_cmd(dev, AX_CMD_READ_MEDIUM_STATUS, 0, 0, 2, &v);
535
536 if (ret < 0) {
537 netdev_err(dev->net, "Error reading Medium Status register: %02x\n",
538 ret);
539 return ret; /* TODO: callers not checking for error ret */
540 }
541
542 return le16_to_cpu(v);
543
544 }
545
546 static int asix_write_medium_mode(struct usbnet *dev, u16 mode)
547 {
548 int ret;
549
550 netdev_dbg(dev->net, "asix_write_medium_mode() - mode = 0x%04x\n", mode);
551 ret = asix_write_cmd(dev, AX_CMD_WRITE_MEDIUM_MODE, mode, 0, 0, NULL);
552 if (ret < 0)
553 netdev_err(dev->net, "Failed to write Medium Mode mode to 0x%04x: %02x\n",
554 mode, ret);
555
556 return ret;
557 }
558
559 static int asix_write_gpio(struct usbnet *dev, u16 value, int sleep)
560 {
561 int ret;
562
563 netdev_dbg(dev->net, "asix_write_gpio() - value = 0x%04x\n", value);
564 ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS, value, 0, 0, NULL);
565 if (ret < 0)
566 netdev_err(dev->net, "Failed to write GPIO value 0x%04x: %02x\n",
567 value, ret);
568
569 if (sleep)
570 msleep(sleep);
571
572 return ret;
573 }
574
575 /*
576 * AX88772 & AX88178 have a 16-bit RX_CTL value
577 */
578 static void asix_set_multicast(struct net_device *net)
579 {
580 struct usbnet *dev = netdev_priv(net);
581 struct asix_data *data = (struct asix_data *)&dev->data;
582 u16 rx_ctl = AX_DEFAULT_RX_CTL;
583
584 if (net->flags & IFF_PROMISC) {
585 rx_ctl |= AX_RX_CTL_PRO;
586 } else if (net->flags & IFF_ALLMULTI ||
587 netdev_mc_count(net) > AX_MAX_MCAST) {
588 rx_ctl |= AX_RX_CTL_AMALL;
589 } else if (netdev_mc_empty(net)) {
590 /* just broadcast and directed */
591 } else {
592 /* We use the 20 byte dev->data
593 * for our 8 byte filter buffer
594 * to avoid allocating memory that
595 * is tricky to free later */
596 struct netdev_hw_addr *ha;
597 u32 crc_bits;
598
599 memset(data->multi_filter, 0, AX_MCAST_FILTER_SIZE);
600
601 /* Build the multicast hash filter. */
602 netdev_for_each_mc_addr(ha, net) {
603 crc_bits = ether_crc(ETH_ALEN, ha->addr) >> 26;
604 data->multi_filter[crc_bits >> 3] |=
605 1 << (crc_bits & 7);
606 }
607
608 asix_write_cmd_async(dev, AX_CMD_WRITE_MULTI_FILTER, 0, 0,
609 AX_MCAST_FILTER_SIZE, data->multi_filter);
610
611 rx_ctl |= AX_RX_CTL_AM;
612 }
613
614 asix_write_cmd_async(dev, AX_CMD_WRITE_RX_CTL, rx_ctl, 0, 0, NULL);
615 }
616
617 static int asix_mdio_read(struct net_device *netdev, int phy_id, int loc)
618 {
619 struct usbnet *dev = netdev_priv(netdev);
620 __le16 res;
621
622 mutex_lock(&dev->phy_mutex);
623 asix_set_sw_mii(dev);
624 asix_read_cmd(dev, AX_CMD_READ_MII_REG, phy_id,
625 (__u16)loc, 2, &res);
626 asix_set_hw_mii(dev);
627 mutex_unlock(&dev->phy_mutex);
628
629 netdev_dbg(dev->net, "asix_mdio_read() phy_id=0x%02x, loc=0x%02x, returns=0x%04x\n",
630 phy_id, loc, le16_to_cpu(res));
631
632 return le16_to_cpu(res);
633 }
634
635 static void
636 asix_mdio_write(struct net_device *netdev, int phy_id, int loc, int val)
637 {
638 struct usbnet *dev = netdev_priv(netdev);
639 __le16 res = cpu_to_le16(val);
640
641 netdev_dbg(dev->net, "asix_mdio_write() phy_id=0x%02x, loc=0x%02x, val=0x%04x\n",
642 phy_id, loc, val);
643 mutex_lock(&dev->phy_mutex);
644 asix_set_sw_mii(dev);
645 asix_write_cmd(dev, AX_CMD_WRITE_MII_REG, phy_id, (__u16)loc, 2, &res);
646 asix_set_hw_mii(dev);
647 mutex_unlock(&dev->phy_mutex);
648 }
649
650 /* Get the PHY Identifier from the PHYSID1 & PHYSID2 MII registers */
651 static u32 asix_get_phyid(struct usbnet *dev)
652 {
653 int phy_reg;
654 u32 phy_id;
655 int i;
656
657 /* Poll for the rare case the FW or phy isn't ready yet. */
658 for (i = 0; i < 100; i++) {
659 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID1);
660 if (phy_reg != 0 && phy_reg != 0xFFFF)
661 break;
662 mdelay(1);
663 }
664
665 if (phy_reg <= 0 || phy_reg == 0xFFFF)
666 return 0;
667
668 phy_id = (phy_reg & 0xffff) << 16;
669
670 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID2);
671 if (phy_reg < 0)
672 return 0;
673
674 phy_id |= (phy_reg & 0xffff);
675
676 return phy_id;
677 }
678
679 static void
680 asix_get_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo)
681 {
682 struct usbnet *dev = netdev_priv(net);
683 u8 opt;
684
685 if (asix_read_cmd(dev, AX_CMD_READ_MONITOR_MODE, 0, 0, 1, &opt) < 0) {
686 wolinfo->supported = 0;
687 wolinfo->wolopts = 0;
688 return;
689 }
690 wolinfo->supported = WAKE_PHY | WAKE_MAGIC;
691 wolinfo->wolopts = 0;
692 }
693
694 static int
695 asix_set_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo)
696 {
697 struct usbnet *dev = netdev_priv(net);
698 u8 opt = 0;
699
700 if (wolinfo->wolopts & WAKE_PHY)
701 opt |= AX_MONITOR_LINK;
702 if (wolinfo->wolopts & WAKE_MAGIC)
703 opt |= AX_MONITOR_MAGIC;
704
705 if (asix_write_cmd(dev, AX_CMD_WRITE_MONITOR_MODE,
706 opt, 0, 0, NULL) < 0)
707 return -EINVAL;
708
709 return 0;
710 }
711
712 static int asix_get_eeprom_len(struct net_device *net)
713 {
714 struct usbnet *dev = netdev_priv(net);
715 struct asix_data *data = (struct asix_data *)&dev->data;
716
717 return data->eeprom_len;
718 }
719
720 static int asix_get_eeprom(struct net_device *net,
721 struct ethtool_eeprom *eeprom, u8 *data)
722 {
723 struct usbnet *dev = netdev_priv(net);
724 __le16 *ebuf = (__le16 *)data;
725 int i;
726
727 /* Crude hack to ensure that we don't overwrite memory
728 * if an odd length is supplied
729 */
730 if (eeprom->len % 2)
731 return -EINVAL;
732
733 eeprom->magic = AX_EEPROM_MAGIC;
734
735 /* ax8817x returns 2 bytes from eeprom on read */
736 for (i=0; i < eeprom->len / 2; i++) {
737 if (asix_read_cmd(dev, AX_CMD_READ_EEPROM,
738 eeprom->offset + i, 0, 2, &ebuf[i]) < 0)
739 return -EINVAL;
740 }
741 return 0;
742 }
743
744 static void asix_get_drvinfo (struct net_device *net,
745 struct ethtool_drvinfo *info)
746 {
747 struct usbnet *dev = netdev_priv(net);
748 struct asix_data *data = (struct asix_data *)&dev->data;
749
750 /* Inherit standard device info */
751 usbnet_get_drvinfo(net, info);
752 strncpy (info->driver, DRIVER_NAME, sizeof info->driver);
753 strncpy (info->version, DRIVER_VERSION, sizeof info->version);
754 info->eedump_len = data->eeprom_len;
755 }
756
757 static u32 asix_get_link(struct net_device *net)
758 {
759 struct usbnet *dev = netdev_priv(net);
760
761 return mii_link_ok(&dev->mii);
762 }
763
764 static int asix_ioctl (struct net_device *net, struct ifreq *rq, int cmd)
765 {
766 struct usbnet *dev = netdev_priv(net);
767
768 return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
769 }
770
771 static int asix_set_mac_address(struct net_device *net, void *p)
772 {
773 struct usbnet *dev = netdev_priv(net);
774 struct asix_data *data = (struct asix_data *)&dev->data;
775 struct sockaddr *addr = p;
776
777 if (netif_running(net))
778 return -EBUSY;
779 if (!is_valid_ether_addr(addr->sa_data))
780 return -EADDRNOTAVAIL;
781
782 memcpy(net->dev_addr, addr->sa_data, ETH_ALEN);
783
784 /* We use the 20 byte dev->data
785 * for our 6 byte mac buffer
786 * to avoid allocating memory that
787 * is tricky to free later */
788 memcpy(data->mac_addr, addr->sa_data, ETH_ALEN);
789 asix_write_cmd_async(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN,
790 data->mac_addr);
791
792 return 0;
793 }
794
795 /* We need to override some ethtool_ops so we require our
796 own structure so we don't interfere with other usbnet
797 devices that may be connected at the same time. */
798 static const struct ethtool_ops ax88172_ethtool_ops = {
799 .get_drvinfo = asix_get_drvinfo,
800 .get_link = asix_get_link,
801 .get_msglevel = usbnet_get_msglevel,
802 .set_msglevel = usbnet_set_msglevel,
803 .get_wol = asix_get_wol,
804 .set_wol = asix_set_wol,
805 .get_eeprom_len = asix_get_eeprom_len,
806 .get_eeprom = asix_get_eeprom,
807 .get_settings = usbnet_get_settings,
808 .set_settings = usbnet_set_settings,
809 .nway_reset = usbnet_nway_reset,
810 };
811
812 static void ax88172_set_multicast(struct net_device *net)
813 {
814 struct usbnet *dev = netdev_priv(net);
815 struct asix_data *data = (struct asix_data *)&dev->data;
816 u8 rx_ctl = 0x8c;
817
818 if (net->flags & IFF_PROMISC) {
819 rx_ctl |= 0x01;
820 } else if (net->flags & IFF_ALLMULTI ||
821 netdev_mc_count(net) > AX_MAX_MCAST) {
822 rx_ctl |= 0x02;
823 } else if (netdev_mc_empty(net)) {
824 /* just broadcast and directed */
825 } else {
826 /* We use the 20 byte dev->data
827 * for our 8 byte filter buffer
828 * to avoid allocating memory that
829 * is tricky to free later */
830 struct netdev_hw_addr *ha;
831 u32 crc_bits;
832
833 memset(data->multi_filter, 0, AX_MCAST_FILTER_SIZE);
834
835 /* Build the multicast hash filter. */
836 netdev_for_each_mc_addr(ha, net) {
837 crc_bits = ether_crc(ETH_ALEN, ha->addr) >> 26;
838 data->multi_filter[crc_bits >> 3] |=
839 1 << (crc_bits & 7);
840 }
841
842 asix_write_cmd_async(dev, AX_CMD_WRITE_MULTI_FILTER, 0, 0,
843 AX_MCAST_FILTER_SIZE, data->multi_filter);
844
845 rx_ctl |= 0x10;
846 }
847
848 asix_write_cmd_async(dev, AX_CMD_WRITE_RX_CTL, rx_ctl, 0, 0, NULL);
849 }
850
851 static int ax88172_link_reset(struct usbnet *dev)
852 {
853 u8 mode;
854 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
855
856 mii_check_media(&dev->mii, 1, 1);
857 mii_ethtool_gset(&dev->mii, &ecmd);
858 mode = AX88172_MEDIUM_DEFAULT;
859
860 if (ecmd.duplex != DUPLEX_FULL)
861 mode |= ~AX88172_MEDIUM_FD;
862
863 netdev_dbg(dev->net, "ax88172_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
864 ethtool_cmd_speed(&ecmd), ecmd.duplex, mode);
865
866 asix_write_medium_mode(dev, mode);
867
868 return 0;
869 }
870
871 static const struct net_device_ops ax88172_netdev_ops = {
872 .ndo_open = usbnet_open,
873 .ndo_stop = usbnet_stop,
874 .ndo_start_xmit = usbnet_start_xmit,
875 .ndo_tx_timeout = usbnet_tx_timeout,
876 .ndo_change_mtu = usbnet_change_mtu,
877 .ndo_set_mac_address = eth_mac_addr,
878 .ndo_validate_addr = eth_validate_addr,
879 .ndo_do_ioctl = asix_ioctl,
880 .ndo_set_rx_mode = ax88172_set_multicast,
881 };
882
883 static int ax88172_bind(struct usbnet *dev, struct usb_interface *intf)
884 {
885 int ret = 0;
886 u8 buf[ETH_ALEN];
887 int i;
888 unsigned long gpio_bits = dev->driver_info->data;
889 struct asix_data *data = (struct asix_data *)&dev->data;
890
891 data->eeprom_len = AX88172_EEPROM_LEN;
892
893 usbnet_get_endpoints(dev,intf);
894
895 /* Toggle the GPIOs in a manufacturer/model specific way */
896 for (i = 2; i >= 0; i--) {
897 ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS,
898 (gpio_bits >> (i * 8)) & 0xff, 0, 0, NULL);
899 if (ret < 0)
900 goto out;
901 msleep(5);
902 }
903
904 ret = asix_write_rx_ctl(dev, 0x80);
905 if (ret < 0)
906 goto out;
907
908 /* Get the MAC address */
909 ret = asix_read_cmd(dev, AX88172_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf);
910 if (ret < 0) {
911 dbg("read AX_CMD_READ_NODE_ID failed: %d", ret);
912 goto out;
913 }
914 memcpy(dev->net->dev_addr, buf, ETH_ALEN);
915
916 /* Initialize MII structure */
917 dev->mii.dev = dev->net;
918 dev->mii.mdio_read = asix_mdio_read;
919 dev->mii.mdio_write = asix_mdio_write;
920 dev->mii.phy_id_mask = 0x3f;
921 dev->mii.reg_num_mask = 0x1f;
922 dev->mii.phy_id = asix_get_phy_addr(dev);
923
924 dev->net->netdev_ops = &ax88172_netdev_ops;
925 dev->net->ethtool_ops = &ax88172_ethtool_ops;
926
927 asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
928 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
929 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
930 mii_nway_restart(&dev->mii);
931
932 return 0;
933
934 out:
935 return ret;
936 }
937
938 static const struct ethtool_ops ax88772_ethtool_ops = {
939 .get_drvinfo = asix_get_drvinfo,
940 .get_link = asix_get_link,
941 .get_msglevel = usbnet_get_msglevel,
942 .set_msglevel = usbnet_set_msglevel,
943 .get_wol = asix_get_wol,
944 .set_wol = asix_set_wol,
945 .get_eeprom_len = asix_get_eeprom_len,
946 .get_eeprom = asix_get_eeprom,
947 .get_settings = usbnet_get_settings,
948 .set_settings = usbnet_set_settings,
949 .nway_reset = usbnet_nway_reset,
950 };
951
952 static int ax88772_link_reset(struct usbnet *dev)
953 {
954 u16 mode;
955 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
956
957 mii_check_media(&dev->mii, 1, 1);
958 mii_ethtool_gset(&dev->mii, &ecmd);
959 mode = AX88772_MEDIUM_DEFAULT;
960
961 if (ethtool_cmd_speed(&ecmd) != SPEED_100)
962 mode &= ~AX_MEDIUM_PS;
963
964 if (ecmd.duplex != DUPLEX_FULL)
965 mode &= ~AX_MEDIUM_FD;
966
967 netdev_dbg(dev->net, "ax88772_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
968 ethtool_cmd_speed(&ecmd), ecmd.duplex, mode);
969
970 asix_write_medium_mode(dev, mode);
971
972 return 0;
973 }
974
975 static int ax88772_reset(struct usbnet *dev)
976 {
977 int ret, embd_phy;
978 u16 rx_ctl;
979
980 ret = asix_write_gpio(dev,
981 AX_GPIO_RSE | AX_GPIO_GPO_2 | AX_GPIO_GPO2EN, 5);
982 if (ret < 0)
983 goto out;
984
985 embd_phy = ((asix_get_phy_addr(dev) & 0x1f) == 0x10 ? 1 : 0);
986
987 ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, embd_phy, 0, 0, NULL);
988 if (ret < 0) {
989 dbg("Select PHY #1 failed: %d", ret);
990 goto out;
991 }
992
993 ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL);
994 if (ret < 0)
995 goto out;
996
997 msleep(150);
998
999 ret = asix_sw_reset(dev, AX_SWRESET_CLEAR);
1000 if (ret < 0)
1001 goto out;
1002
1003 msleep(150);
1004
1005 if (embd_phy) {
1006 ret = asix_sw_reset(dev, AX_SWRESET_IPRL);
1007 if (ret < 0)
1008 goto out;
1009 } else {
1010 ret = asix_sw_reset(dev, AX_SWRESET_PRTE);
1011 if (ret < 0)
1012 goto out;
1013 }
1014
1015 msleep(150);
1016 rx_ctl = asix_read_rx_ctl(dev);
1017 dbg("RX_CTL is 0x%04x after software reset", rx_ctl);
1018 ret = asix_write_rx_ctl(dev, 0x0000);
1019 if (ret < 0)
1020 goto out;
1021
1022 rx_ctl = asix_read_rx_ctl(dev);
1023 dbg("RX_CTL is 0x%04x setting to 0x0000", rx_ctl);
1024
1025 ret = asix_sw_reset(dev, AX_SWRESET_PRL);
1026 if (ret < 0)
1027 goto out;
1028
1029 msleep(150);
1030
1031 ret = asix_sw_reset(dev, AX_SWRESET_IPRL | AX_SWRESET_PRL);
1032 if (ret < 0)
1033 goto out;
1034
1035 msleep(150);
1036
1037 asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
1038 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
1039 ADVERTISE_ALL | ADVERTISE_CSMA);
1040 mii_nway_restart(&dev->mii);
1041
1042 ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT);
1043 if (ret < 0)
1044 goto out;
1045
1046 ret = asix_write_cmd(dev, AX_CMD_WRITE_IPG0,
1047 AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT,
1048 AX88772_IPG2_DEFAULT, 0, NULL);
1049 if (ret < 0) {
1050 dbg("Write IPG,IPG1,IPG2 failed: %d", ret);
1051 goto out;
1052 }
1053
1054 /* Set RX_CTL to default values with 2k buffer, and enable cactus */
1055 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL);
1056 if (ret < 0)
1057 goto out;
1058
1059 rx_ctl = asix_read_rx_ctl(dev);
1060 dbg("RX_CTL is 0x%04x after all initializations", rx_ctl);
1061
1062 rx_ctl = asix_read_medium_status(dev);
1063 dbg("Medium Status is 0x%04x after all initializations", rx_ctl);
1064
1065 return 0;
1066
1067 out:
1068 return ret;
1069
1070 }
1071
1072 static const struct net_device_ops ax88772_netdev_ops = {
1073 .ndo_open = usbnet_open,
1074 .ndo_stop = usbnet_stop,
1075 .ndo_start_xmit = usbnet_start_xmit,
1076 .ndo_tx_timeout = usbnet_tx_timeout,
1077 .ndo_change_mtu = usbnet_change_mtu,
1078 .ndo_set_mac_address = asix_set_mac_address,
1079 .ndo_validate_addr = eth_validate_addr,
1080 .ndo_do_ioctl = asix_ioctl,
1081 .ndo_set_rx_mode = asix_set_multicast,
1082 };
1083
1084 static int ax88772_bind(struct usbnet *dev, struct usb_interface *intf)
1085 {
1086 int ret, embd_phy;
1087 struct asix_data *data = (struct asix_data *)&dev->data;
1088 u8 buf[ETH_ALEN];
1089 u32 phyid;
1090
1091 data->eeprom_len = AX88772_EEPROM_LEN;
1092
1093 usbnet_get_endpoints(dev,intf);
1094
1095 /* Get the MAC address */
1096 ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf);
1097 if (ret < 0) {
1098 dbg("Failed to read MAC address: %d", ret);
1099 return ret;
1100 }
1101 memcpy(dev->net->dev_addr, buf, ETH_ALEN);
1102
1103 /* Initialize MII structure */
1104 dev->mii.dev = dev->net;
1105 dev->mii.mdio_read = asix_mdio_read;
1106 dev->mii.mdio_write = asix_mdio_write;
1107 dev->mii.phy_id_mask = 0x1f;
1108 dev->mii.reg_num_mask = 0x1f;
1109 dev->mii.phy_id = asix_get_phy_addr(dev);
1110
1111 dev->net->netdev_ops = &ax88772_netdev_ops;
1112 dev->net->ethtool_ops = &ax88772_ethtool_ops;
1113
1114 embd_phy = ((dev->mii.phy_id & 0x1f) == 0x10 ? 1 : 0);
1115
1116 /* Reset the PHY to normal operation mode */
1117 ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, embd_phy, 0, 0, NULL);
1118 if (ret < 0) {
1119 dbg("Select PHY #1 failed: %d", ret);
1120 return ret;
1121 }
1122
1123 ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL);
1124 if (ret < 0)
1125 return ret;
1126
1127 msleep(150);
1128
1129 ret = asix_sw_reset(dev, AX_SWRESET_CLEAR);
1130 if (ret < 0)
1131 return ret;
1132
1133 msleep(150);
1134
1135 ret = asix_sw_reset(dev, embd_phy ? AX_SWRESET_IPRL : AX_SWRESET_PRTE);
1136
1137 /* Read PHYID register *AFTER* the PHY was reset properly */
1138 phyid = asix_get_phyid(dev);
1139 dbg("PHYID=0x%08x", phyid);
1140
1141 /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */
1142 if (dev->driver_info->flags & FLAG_FRAMING_AX) {
1143 /* hard_mtu is still the default - the device does not support
1144 jumbo eth frames */
1145 dev->rx_urb_size = 2048;
1146 }
1147
1148 return 0;
1149 }
1150
1151 static struct ethtool_ops ax88178_ethtool_ops = {
1152 .get_drvinfo = asix_get_drvinfo,
1153 .get_link = asix_get_link,
1154 .get_msglevel = usbnet_get_msglevel,
1155 .set_msglevel = usbnet_set_msglevel,
1156 .get_wol = asix_get_wol,
1157 .set_wol = asix_set_wol,
1158 .get_eeprom_len = asix_get_eeprom_len,
1159 .get_eeprom = asix_get_eeprom,
1160 .get_settings = usbnet_get_settings,
1161 .set_settings = usbnet_set_settings,
1162 .nway_reset = usbnet_nway_reset,
1163 };
1164
1165 static int marvell_phy_init(struct usbnet *dev)
1166 {
1167 struct asix_data *data = (struct asix_data *)&dev->data;
1168 u16 reg;
1169
1170 netdev_dbg(dev->net, "marvell_phy_init()\n");
1171
1172 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_MARVELL_STATUS);
1173 netdev_dbg(dev->net, "MII_MARVELL_STATUS = 0x%04x\n", reg);
1174
1175 asix_mdio_write(dev->net, dev->mii.phy_id, MII_MARVELL_CTRL,
1176 MARVELL_CTRL_RXDELAY | MARVELL_CTRL_TXDELAY);
1177
1178 if (data->ledmode) {
1179 reg = asix_mdio_read(dev->net, dev->mii.phy_id,
1180 MII_MARVELL_LED_CTRL);
1181 netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (1) = 0x%04x\n", reg);
1182
1183 reg &= 0xf8ff;
1184 reg |= (1 + 0x0100);
1185 asix_mdio_write(dev->net, dev->mii.phy_id,
1186 MII_MARVELL_LED_CTRL, reg);
1187
1188 reg = asix_mdio_read(dev->net, dev->mii.phy_id,
1189 MII_MARVELL_LED_CTRL);
1190 netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (2) = 0x%04x\n", reg);
1191 reg &= 0xfc0f;
1192 }
1193
1194 return 0;
1195 }
1196
1197 static int rtl8211cl_phy_init(struct usbnet *dev)
1198 {
1199 struct asix_data *data = (struct asix_data *)&dev->data;
1200
1201 netdev_dbg(dev->net, "rtl8211cl_phy_init()\n");
1202
1203 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0005);
1204 asix_mdio_write (dev->net, dev->mii.phy_id, 0x0c, 0);
1205 asix_mdio_write (dev->net, dev->mii.phy_id, 0x01,
1206 asix_mdio_read (dev->net, dev->mii.phy_id, 0x01) | 0x0080);
1207 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0);
1208
1209 if (data->ledmode == 12) {
1210 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0002);
1211 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1a, 0x00cb);
1212 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0);
1213 }
1214
1215 return 0;
1216 }
1217
1218 static int marvell_led_status(struct usbnet *dev, u16 speed)
1219 {
1220 u16 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL);
1221
1222 netdev_dbg(dev->net, "marvell_led_status() read 0x%04x\n", reg);
1223
1224 /* Clear out the center LED bits - 0x03F0 */
1225 reg &= 0xfc0f;
1226
1227 switch (speed) {
1228 case SPEED_1000:
1229 reg |= 0x03e0;
1230 break;
1231 case SPEED_100:
1232 reg |= 0x03b0;
1233 break;
1234 default:
1235 reg |= 0x02f0;
1236 }
1237
1238 netdev_dbg(dev->net, "marvell_led_status() writing 0x%04x\n", reg);
1239 asix_mdio_write(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL, reg);
1240
1241 return 0;
1242 }
1243
1244 static int ax88178_reset(struct usbnet *dev)
1245 {
1246 struct asix_data *data = (struct asix_data *)&dev->data;
1247 int ret;
1248 __le16 eeprom;
1249 u8 status;
1250 int gpio0 = 0;
1251 u32 phyid;
1252
1253 asix_read_cmd(dev, AX_CMD_READ_GPIOS, 0, 0, 1, &status);
1254 dbg("GPIO Status: 0x%04x", status);
1255
1256 asix_write_cmd(dev, AX_CMD_WRITE_ENABLE, 0, 0, 0, NULL);
1257 asix_read_cmd(dev, AX_CMD_READ_EEPROM, 0x0017, 0, 2, &eeprom);
1258 asix_write_cmd(dev, AX_CMD_WRITE_DISABLE, 0, 0, 0, NULL);
1259
1260 dbg("EEPROM index 0x17 is 0x%04x", eeprom);
1261
1262 if (eeprom == cpu_to_le16(0xffff)) {
1263 data->phymode = PHY_MODE_MARVELL;
1264 data->ledmode = 0;
1265 gpio0 = 1;
1266 } else {
1267 data->phymode = le16_to_cpu(eeprom) & 0x7F;
1268 data->ledmode = le16_to_cpu(eeprom) >> 8;
1269 gpio0 = (le16_to_cpu(eeprom) & 0x80) ? 0 : 1;
1270 }
1271 dbg("GPIO0: %d, PhyMode: %d", gpio0, data->phymode);
1272
1273 /* Power up external GigaPHY through AX88178 GPIO pin */
1274 asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_1 | AX_GPIO_GPO1EN, 40);
1275 if ((le16_to_cpu(eeprom) >> 8) != 1) {
1276 asix_write_gpio(dev, 0x003c, 30);
1277 asix_write_gpio(dev, 0x001c, 300);
1278 asix_write_gpio(dev, 0x003c, 30);
1279 } else {
1280 dbg("gpio phymode == 1 path");
1281 asix_write_gpio(dev, AX_GPIO_GPO1EN, 30);
1282 asix_write_gpio(dev, AX_GPIO_GPO1EN | AX_GPIO_GPO_1, 30);
1283 }
1284
1285 /* Read PHYID register *AFTER* powering up PHY */
1286 phyid = asix_get_phyid(dev);
1287 dbg("PHYID=0x%08x", phyid);
1288
1289 /* Set AX88178 to enable MII/GMII/RGMII interface for external PHY */
1290 asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, 0, 0, 0, NULL);
1291
1292 asix_sw_reset(dev, 0);
1293 msleep(150);
1294
1295 asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD);
1296 msleep(150);
1297
1298 asix_write_rx_ctl(dev, 0);
1299
1300 if (data->phymode == PHY_MODE_MARVELL) {
1301 marvell_phy_init(dev);
1302 msleep(60);
1303 } else if (data->phymode == PHY_MODE_RTL8211CL)
1304 rtl8211cl_phy_init(dev);
1305
1306 asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR,
1307 BMCR_RESET | BMCR_ANENABLE);
1308 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
1309 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1310 asix_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000,
1311 ADVERTISE_1000FULL);
1312
1313 mii_nway_restart(&dev->mii);
1314
1315 ret = asix_write_medium_mode(dev, AX88178_MEDIUM_DEFAULT);
1316 if (ret < 0)
1317 return ret;
1318
1319 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL);
1320 if (ret < 0)
1321 return ret;
1322
1323 return 0;
1324 }
1325
1326 static int ax88178_link_reset(struct usbnet *dev)
1327 {
1328 u16 mode;
1329 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
1330 struct asix_data *data = (struct asix_data *)&dev->data;
1331 u32 speed;
1332
1333 netdev_dbg(dev->net, "ax88178_link_reset()\n");
1334
1335 mii_check_media(&dev->mii, 1, 1);
1336 mii_ethtool_gset(&dev->mii, &ecmd);
1337 mode = AX88178_MEDIUM_DEFAULT;
1338 speed = ethtool_cmd_speed(&ecmd);
1339
1340 if (speed == SPEED_1000)
1341 mode |= AX_MEDIUM_GM;
1342 else if (speed == SPEED_100)
1343 mode |= AX_MEDIUM_PS;
1344 else
1345 mode &= ~(AX_MEDIUM_PS | AX_MEDIUM_GM);
1346
1347 mode |= AX_MEDIUM_ENCK;
1348
1349 if (ecmd.duplex == DUPLEX_FULL)
1350 mode |= AX_MEDIUM_FD;
1351 else
1352 mode &= ~AX_MEDIUM_FD;
1353
1354 netdev_dbg(dev->net, "ax88178_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
1355 speed, ecmd.duplex, mode);
1356
1357 asix_write_medium_mode(dev, mode);
1358
1359 if (data->phymode == PHY_MODE_MARVELL && data->ledmode)
1360 marvell_led_status(dev, speed);
1361
1362 return 0;
1363 }
1364
1365 static void ax88178_set_mfb(struct usbnet *dev)
1366 {
1367 u16 mfb = AX_RX_CTL_MFB_16384;
1368 u16 rxctl;
1369 u16 medium;
1370 int old_rx_urb_size = dev->rx_urb_size;
1371
1372 if (dev->hard_mtu < 2048) {
1373 dev->rx_urb_size = 2048;
1374 mfb = AX_RX_CTL_MFB_2048;
1375 } else if (dev->hard_mtu < 4096) {
1376 dev->rx_urb_size = 4096;
1377 mfb = AX_RX_CTL_MFB_4096;
1378 } else if (dev->hard_mtu < 8192) {
1379 dev->rx_urb_size = 8192;
1380 mfb = AX_RX_CTL_MFB_8192;
1381 } else if (dev->hard_mtu < 16384) {
1382 dev->rx_urb_size = 16384;
1383 mfb = AX_RX_CTL_MFB_16384;
1384 }
1385
1386 rxctl = asix_read_rx_ctl(dev);
1387 asix_write_rx_ctl(dev, (rxctl & ~AX_RX_CTL_MFB_16384) | mfb);
1388
1389 medium = asix_read_medium_status(dev);
1390 if (dev->net->mtu > 1500)
1391 medium |= AX_MEDIUM_JFE;
1392 else
1393 medium &= ~AX_MEDIUM_JFE;
1394 asix_write_medium_mode(dev, medium);
1395
1396 if (dev->rx_urb_size > old_rx_urb_size)
1397 usbnet_unlink_rx_urbs(dev);
1398 }
1399
1400 static int ax88178_change_mtu(struct net_device *net, int new_mtu)
1401 {
1402 struct usbnet *dev = netdev_priv(net);
1403 int ll_mtu = new_mtu + net->hard_header_len + 4;
1404
1405 netdev_dbg(dev->net, "ax88178_change_mtu() new_mtu=%d\n", new_mtu);
1406
1407 if (new_mtu <= 0 || ll_mtu > 16384)
1408 return -EINVAL;
1409
1410 if ((ll_mtu % dev->maxpacket) == 0)
1411 return -EDOM;
1412
1413 net->mtu = new_mtu;
1414 dev->hard_mtu = net->mtu + net->hard_header_len;
1415 ax88178_set_mfb(dev);
1416
1417 return 0;
1418 }
1419
1420 static const struct net_device_ops ax88178_netdev_ops = {
1421 .ndo_open = usbnet_open,
1422 .ndo_stop = usbnet_stop,
1423 .ndo_start_xmit = usbnet_start_xmit,
1424 .ndo_tx_timeout = usbnet_tx_timeout,
1425 .ndo_set_mac_address = asix_set_mac_address,
1426 .ndo_validate_addr = eth_validate_addr,
1427 .ndo_set_rx_mode = asix_set_multicast,
1428 .ndo_do_ioctl = asix_ioctl,
1429 .ndo_change_mtu = ax88178_change_mtu,
1430 };
1431
1432 static int ax88178_bind(struct usbnet *dev, struct usb_interface *intf)
1433 {
1434 int ret;
1435 u8 buf[ETH_ALEN];
1436 struct asix_data *data = (struct asix_data *)&dev->data;
1437
1438 data->eeprom_len = AX88772_EEPROM_LEN;
1439
1440 usbnet_get_endpoints(dev,intf);
1441
1442 /* Get the MAC address */
1443 ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf);
1444 if (ret < 0) {
1445 dbg("Failed to read MAC address: %d", ret);
1446 return ret;
1447 }
1448 memcpy(dev->net->dev_addr, buf, ETH_ALEN);
1449
1450 /* Initialize MII structure */
1451 dev->mii.dev = dev->net;
1452 dev->mii.mdio_read = asix_mdio_read;
1453 dev->mii.mdio_write = asix_mdio_write;
1454 dev->mii.phy_id_mask = 0x1f;
1455 dev->mii.reg_num_mask = 0xff;
1456 dev->mii.supports_gmii = 1;
1457 dev->mii.phy_id = asix_get_phy_addr(dev);
1458
1459 dev->net->netdev_ops = &ax88178_netdev_ops;
1460 dev->net->ethtool_ops = &ax88178_ethtool_ops;
1461
1462 /* Blink LEDS so users know driver saw dongle */
1463 asix_sw_reset(dev, 0);
1464 msleep(150);
1465
1466 asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD);
1467 msleep(150);
1468
1469 /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */
1470 if (dev->driver_info->flags & FLAG_FRAMING_AX) {
1471 /* hard_mtu is still the default - the device does not support
1472 jumbo eth frames */
1473 dev->rx_urb_size = 2048;
1474 }
1475
1476 return 0;
1477 }
1478
1479 static const struct driver_info ax8817x_info = {
1480 .description = "ASIX AX8817x USB 2.0 Ethernet",
1481 .bind = ax88172_bind,
1482 .status = asix_status,
1483 .link_reset = ax88172_link_reset,
1484 .reset = ax88172_link_reset,
1485 .flags = FLAG_ETHER | FLAG_LINK_INTR,
1486 .data = 0x00130103,
1487 };
1488
1489 static const struct driver_info dlink_dub_e100_info = {
1490 .description = "DLink DUB-E100 USB Ethernet",
1491 .bind = ax88172_bind,
1492 .status = asix_status,
1493 .link_reset = ax88172_link_reset,
1494 .reset = ax88172_link_reset,
1495 .flags = FLAG_ETHER | FLAG_LINK_INTR,
1496 .data = 0x009f9d9f,
1497 };
1498
1499 static const struct driver_info netgear_fa120_info = {
1500 .description = "Netgear FA-120 USB Ethernet",
1501 .bind = ax88172_bind,
1502 .status = asix_status,
1503 .link_reset = ax88172_link_reset,
1504 .reset = ax88172_link_reset,
1505 .flags = FLAG_ETHER | FLAG_LINK_INTR,
1506 .data = 0x00130103,
1507 };
1508
1509 static const struct driver_info hawking_uf200_info = {
1510 .description = "Hawking UF200 USB Ethernet",
1511 .bind = ax88172_bind,
1512 .status = asix_status,
1513 .link_reset = ax88172_link_reset,
1514 .reset = ax88172_link_reset,
1515 .flags = FLAG_ETHER | FLAG_LINK_INTR,
1516 .data = 0x001f1d1f,
1517 };
1518
1519 static const struct driver_info ax88772_info = {
1520 .description = "ASIX AX88772 USB 2.0 Ethernet",
1521 .bind = ax88772_bind,
1522 .status = asix_status,
1523 .link_reset = ax88772_link_reset,
1524 .reset = ax88772_reset,
1525 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR,
1526 .rx_fixup = asix_rx_fixup,
1527 .tx_fixup = asix_tx_fixup,
1528 };
1529
1530 static const struct driver_info ax88178_info = {
1531 .description = "ASIX AX88178 USB 2.0 Ethernet",
1532 .bind = ax88178_bind,
1533 .status = asix_status,
1534 .link_reset = ax88178_link_reset,
1535 .reset = ax88178_reset,
1536 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR,
1537 .rx_fixup = asix_rx_fixup,
1538 .tx_fixup = asix_tx_fixup,
1539 };
1540
1541 static const struct usb_device_id products [] = {
1542 {
1543 // Linksys USB200M
1544 USB_DEVICE (0x077b, 0x2226),
1545 .driver_info = (unsigned long) &ax8817x_info,
1546 }, {
1547 // Netgear FA120
1548 USB_DEVICE (0x0846, 0x1040),
1549 .driver_info = (unsigned long) &netgear_fa120_info,
1550 }, {
1551 // DLink DUB-E100
1552 USB_DEVICE (0x2001, 0x1a00),
1553 .driver_info = (unsigned long) &dlink_dub_e100_info,
1554 }, {
1555 // Intellinet, ST Lab USB Ethernet
1556 USB_DEVICE (0x0b95, 0x1720),
1557 .driver_info = (unsigned long) &ax8817x_info,
1558 }, {
1559 // Hawking UF200, TrendNet TU2-ET100
1560 USB_DEVICE (0x07b8, 0x420a),
1561 .driver_info = (unsigned long) &hawking_uf200_info,
1562 }, {
1563 // Billionton Systems, USB2AR
1564 USB_DEVICE (0x08dd, 0x90ff),
1565 .driver_info = (unsigned long) &ax8817x_info,
1566 }, {
1567 // ATEN UC210T
1568 USB_DEVICE (0x0557, 0x2009),
1569 .driver_info = (unsigned long) &ax8817x_info,
1570 }, {
1571 // Buffalo LUA-U2-KTX
1572 USB_DEVICE (0x0411, 0x003d),
1573 .driver_info = (unsigned long) &ax8817x_info,
1574 }, {
1575 // Buffalo LUA-U2-GT 10/100/1000
1576 USB_DEVICE (0x0411, 0x006e),
1577 .driver_info = (unsigned long) &ax88178_info,
1578 }, {
1579 // Sitecom LN-029 "USB 2.0 10/100 Ethernet adapter"
1580 USB_DEVICE (0x6189, 0x182d),
1581 .driver_info = (unsigned long) &ax8817x_info,
1582 }, {
1583 // corega FEther USB2-TX
1584 USB_DEVICE (0x07aa, 0x0017),
1585 .driver_info = (unsigned long) &ax8817x_info,
1586 }, {
1587 // Surecom EP-1427X-2
1588 USB_DEVICE (0x1189, 0x0893),
1589 .driver_info = (unsigned long) &ax8817x_info,
1590 }, {
1591 // goodway corp usb gwusb2e
1592 USB_DEVICE (0x1631, 0x6200),
1593 .driver_info = (unsigned long) &ax8817x_info,
1594 }, {
1595 // JVC MP-PRX1 Port Replicator
1596 USB_DEVICE (0x04f1, 0x3008),
1597 .driver_info = (unsigned long) &ax8817x_info,
1598 }, {
1599 // ASIX AX88772B 10/100
1600 USB_DEVICE (0x0b95, 0x772b),
1601 .driver_info = (unsigned long) &ax88772_info,
1602 }, {
1603 // ASIX AX88772 10/100
1604 USB_DEVICE (0x0b95, 0x7720),
1605 .driver_info = (unsigned long) &ax88772_info,
1606 }, {
1607 // ASIX AX88178 10/100/1000
1608 USB_DEVICE (0x0b95, 0x1780),
1609 .driver_info = (unsigned long) &ax88178_info,
1610 }, {
1611 // Logitec LAN-GTJ/U2A
1612 USB_DEVICE (0x0789, 0x0160),
1613 .driver_info = (unsigned long) &ax88178_info,
1614 }, {
1615 // Linksys USB200M Rev 2
1616 USB_DEVICE (0x13b1, 0x0018),
1617 .driver_info = (unsigned long) &ax88772_info,
1618 }, {
1619 // 0Q0 cable ethernet
1620 USB_DEVICE (0x1557, 0x7720),
1621 .driver_info = (unsigned long) &ax88772_info,
1622 }, {
1623 // DLink DUB-E100 H/W Ver B1
1624 USB_DEVICE (0x07d1, 0x3c05),
1625 .driver_info = (unsigned long) &ax88772_info,
1626 }, {
1627 // DLink DUB-E100 H/W Ver B1 Alternate
1628 USB_DEVICE (0x2001, 0x3c05),
1629 .driver_info = (unsigned long) &ax88772_info,
1630 }, {
1631 // Linksys USB1000
1632 USB_DEVICE (0x1737, 0x0039),
1633 .driver_info = (unsigned long) &ax88178_info,
1634 }, {
1635 // IO-DATA ETG-US2
1636 USB_DEVICE (0x04bb, 0x0930),
1637 .driver_info = (unsigned long) &ax88178_info,
1638 }, {
1639 // Belkin F5D5055
1640 USB_DEVICE(0x050d, 0x5055),
1641 .driver_info = (unsigned long) &ax88178_info,
1642 }, {
1643 // Apple USB Ethernet Adapter
1644 USB_DEVICE(0x05ac, 0x1402),
1645 .driver_info = (unsigned long) &ax88772_info,
1646 }, {
1647 // Cables-to-Go USB Ethernet Adapter
1648 USB_DEVICE(0x0b95, 0x772a),
1649 .driver_info = (unsigned long) &ax88772_info,
1650 }, {
1651 // ABOCOM for pci
1652 USB_DEVICE(0x14ea, 0xab11),
1653 .driver_info = (unsigned long) &ax88178_info,
1654 }, {
1655 // ASIX 88772a
1656 USB_DEVICE(0x0db0, 0xa877),
1657 .driver_info = (unsigned long) &ax88772_info,
1658 },
1659 { }, // END
1660 };
1661 MODULE_DEVICE_TABLE(usb, products);
1662
1663 static struct usb_driver asix_driver = {
1664 .name = DRIVER_NAME,
1665 .id_table = products,
1666 .probe = usbnet_probe,
1667 .suspend = usbnet_suspend,
1668 .resume = usbnet_resume,
1669 .disconnect = usbnet_disconnect,
1670 .supports_autosuspend = 1,
1671 };
1672
1673 static int __init asix_init(void)
1674 {
1675 return usb_register(&asix_driver);
1676 }
1677 module_init(asix_init);
1678
1679 static void __exit asix_exit(void)
1680 {
1681 usb_deregister(&asix_driver);
1682 }
1683 module_exit(asix_exit);
1684
1685 MODULE_AUTHOR("David Hollis");
1686 MODULE_VERSION(DRIVER_VERSION);
1687 MODULE_DESCRIPTION("ASIX AX8817X based USB 2.0 Ethernet Devices");
1688 MODULE_LICENSE("GPL");
1689
Linux kernel - Deliverables
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