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net: asix: Move declaration of ax88172a_info to shared header
[deliverable/linux.git] / drivers / net / usb / r8152.c
1 /*
2 * Copyright (c) 2013 Realtek Semiconductor Corp. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * version 2 as published by the Free Software Foundation.
7 *
8 */
9
10 #include <linux/init.h>
11 #include <linux/signal.h>
12 #include <linux/slab.h>
13 #include <linux/module.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/mii.h>
17 #include <linux/ethtool.h>
18 #include <linux/usb.h>
19 #include <linux/crc32.h>
20 #include <linux/if_vlan.h>
21 #include <linux/uaccess.h>
22
23 /* Version Information */
24 #define DRIVER_VERSION "v1.0.0 (2013/05/03)"
25 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
26 #define DRIVER_DESC "Realtek RTL8152 Based USB 2.0 Ethernet Adapters"
27 #define MODULENAME "r8152"
28
29 #define R8152_PHY_ID 32
30
31 #define PLA_IDR 0xc000
32 #define PLA_RCR 0xc010
33 #define PLA_RMS 0xc016
34 #define PLA_RXFIFO_CTRL0 0xc0a0
35 #define PLA_RXFIFO_CTRL1 0xc0a4
36 #define PLA_RXFIFO_CTRL2 0xc0a8
37 #define PLA_FMC 0xc0b4
38 #define PLA_CFG_WOL 0xc0b6
39 #define PLA_MAR 0xcd00
40 #define PAL_BDC_CR 0xd1a0
41 #define PLA_LEDSEL 0xdd90
42 #define PLA_LED_FEATURE 0xdd92
43 #define PLA_PHYAR 0xde00
44 #define PLA_GPHY_INTR_IMR 0xe022
45 #define PLA_EEE_CR 0xe040
46 #define PLA_EEEP_CR 0xe080
47 #define PLA_MAC_PWR_CTRL 0xe0c0
48 #define PLA_TCR0 0xe610
49 #define PLA_TCR1 0xe612
50 #define PLA_TXFIFO_CTRL 0xe618
51 #define PLA_RSTTELLY 0xe800
52 #define PLA_CR 0xe813
53 #define PLA_CRWECR 0xe81c
54 #define PLA_CONFIG5 0xe822
55 #define PLA_PHY_PWR 0xe84c
56 #define PLA_OOB_CTRL 0xe84f
57 #define PLA_CPCR 0xe854
58 #define PLA_MISC_0 0xe858
59 #define PLA_MISC_1 0xe85a
60 #define PLA_OCP_GPHY_BASE 0xe86c
61 #define PLA_TELLYCNT 0xe890
62 #define PLA_SFF_STS_7 0xe8de
63 #define PLA_PHYSTATUS 0xe908
64 #define PLA_BP_BA 0xfc26
65 #define PLA_BP_0 0xfc28
66 #define PLA_BP_1 0xfc2a
67 #define PLA_BP_2 0xfc2c
68 #define PLA_BP_3 0xfc2e
69 #define PLA_BP_4 0xfc30
70 #define PLA_BP_5 0xfc32
71 #define PLA_BP_6 0xfc34
72 #define PLA_BP_7 0xfc36
73
74 #define USB_DEV_STAT 0xb808
75 #define USB_USB_CTRL 0xd406
76 #define USB_PHY_CTRL 0xd408
77 #define USB_TX_AGG 0xd40a
78 #define USB_RX_BUF_TH 0xd40c
79 #define USB_USB_TIMER 0xd428
80 #define USB_PM_CTRL_STATUS 0xd432
81 #define USB_TX_DMA 0xd434
82 #define USB_UPS_CTRL 0xd800
83 #define USB_BP_BA 0xfc26
84 #define USB_BP_0 0xfc28
85 #define USB_BP_1 0xfc2a
86 #define USB_BP_2 0xfc2c
87 #define USB_BP_3 0xfc2e
88 #define USB_BP_4 0xfc30
89 #define USB_BP_5 0xfc32
90 #define USB_BP_6 0xfc34
91 #define USB_BP_7 0xfc36
92
93 /* OCP Registers */
94 #define OCP_ALDPS_CONFIG 0x2010
95 #define OCP_EEE_CONFIG1 0x2080
96 #define OCP_EEE_CONFIG2 0x2092
97 #define OCP_EEE_CONFIG3 0x2094
98 #define OCP_EEE_AR 0xa41a
99 #define OCP_EEE_DATA 0xa41c
100
101 /* PLA_RCR */
102 #define RCR_AAP 0x00000001
103 #define RCR_APM 0x00000002
104 #define RCR_AM 0x00000004
105 #define RCR_AB 0x00000008
106 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
107
108 /* PLA_RXFIFO_CTRL0 */
109 #define RXFIFO_THR1_NORMAL 0x00080002
110 #define RXFIFO_THR1_OOB 0x01800003
111
112 /* PLA_RXFIFO_CTRL1 */
113 #define RXFIFO_THR2_FULL 0x00000060
114 #define RXFIFO_THR2_HIGH 0x00000038
115 #define RXFIFO_THR2_OOB 0x0000004a
116
117 /* PLA_RXFIFO_CTRL2 */
118 #define RXFIFO_THR3_FULL 0x00000078
119 #define RXFIFO_THR3_HIGH 0x00000048
120 #define RXFIFO_THR3_OOB 0x0000005a
121
122 /* PLA_TXFIFO_CTRL */
123 #define TXFIFO_THR_NORMAL 0x00400008
124
125 /* PLA_FMC */
126 #define FMC_FCR_MCU_EN 0x0001
127
128 /* PLA_EEEP_CR */
129 #define EEEP_CR_EEEP_TX 0x0002
130
131 /* PLA_TCR0 */
132 #define TCR0_TX_EMPTY 0x0800
133 #define TCR0_AUTO_FIFO 0x0080
134
135 /* PLA_TCR1 */
136 #define VERSION_MASK 0x7cf0
137
138 /* PLA_CR */
139 #define CR_RST 0x10
140 #define CR_RE 0x08
141 #define CR_TE 0x04
142
143 /* PLA_CRWECR */
144 #define CRWECR_NORAML 0x00
145 #define CRWECR_CONFIG 0xc0
146
147 /* PLA_OOB_CTRL */
148 #define NOW_IS_OOB 0x80
149 #define TXFIFO_EMPTY 0x20
150 #define RXFIFO_EMPTY 0x10
151 #define LINK_LIST_READY 0x02
152 #define DIS_MCU_CLROOB 0x01
153 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
154
155 /* PLA_MISC_1 */
156 #define RXDY_GATED_EN 0x0008
157
158 /* PLA_SFF_STS_7 */
159 #define RE_INIT_LL 0x8000
160 #define MCU_BORW_EN 0x4000
161
162 /* PLA_CPCR */
163 #define CPCR_RX_VLAN 0x0040
164
165 /* PLA_CFG_WOL */
166 #define MAGIC_EN 0x0001
167
168 /* PAL_BDC_CR */
169 #define ALDPS_PROXY_MODE 0x0001
170
171 /* PLA_CONFIG5 */
172 #define LAN_WAKE_EN 0x0002
173
174 /* PLA_LED_FEATURE */
175 #define LED_MODE_MASK 0x0700
176
177 /* PLA_PHY_PWR */
178 #define TX_10M_IDLE_EN 0x0080
179 #define PFM_PWM_SWITCH 0x0040
180
181 /* PLA_MAC_PWR_CTRL */
182 #define D3_CLK_GATED_EN 0x00004000
183 #define MCU_CLK_RATIO 0x07010f07
184 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
185
186 /* PLA_GPHY_INTR_IMR */
187 #define GPHY_STS_MSK 0x0001
188 #define SPEED_DOWN_MSK 0x0002
189 #define SPDWN_RXDV_MSK 0x0004
190 #define SPDWN_LINKCHG_MSK 0x0008
191
192 /* PLA_PHYAR */
193 #define PHYAR_FLAG 0x80000000
194
195 /* PLA_EEE_CR */
196 #define EEE_RX_EN 0x0001
197 #define EEE_TX_EN 0x0002
198
199 /* USB_DEV_STAT */
200 #define STAT_SPEED_MASK 0x0006
201 #define STAT_SPEED_HIGH 0x0000
202 #define STAT_SPEED_FULL 0x0001
203
204 /* USB_TX_AGG */
205 #define TX_AGG_MAX_THRESHOLD 0x03
206
207 /* USB_RX_BUF_TH */
208 #define RX_BUF_THR 0x7a120180
209
210 /* USB_TX_DMA */
211 #define TEST_MODE_DISABLE 0x00000001
212 #define TX_SIZE_ADJUST1 0x00000100
213
214 /* USB_UPS_CTRL */
215 #define POWER_CUT 0x0100
216
217 /* USB_PM_CTRL_STATUS */
218 #define RWSUME_INDICATE 0x0001
219
220 /* USB_USB_CTRL */
221 #define RX_AGG_DISABLE 0x0010
222
223 /* OCP_ALDPS_CONFIG */
224 #define ENPWRSAVE 0x8000
225 #define ENPDNPS 0x0200
226 #define LINKENA 0x0100
227 #define DIS_SDSAVE 0x0010
228
229 /* OCP_EEE_CONFIG1 */
230 #define RG_TXLPI_MSK_HFDUP 0x8000
231 #define RG_MATCLR_EN 0x4000
232 #define EEE_10_CAP 0x2000
233 #define EEE_NWAY_EN 0x1000
234 #define TX_QUIET_EN 0x0200
235 #define RX_QUIET_EN 0x0100
236 #define SDRISETIME 0x0010 /* bit 4 ~ 6 */
237 #define RG_RXLPI_MSK_HFDUP 0x0008
238 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
239
240 /* OCP_EEE_CONFIG2 */
241 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
242 #define RG_DACQUIET_EN 0x0400
243 #define RG_LDVQUIET_EN 0x0200
244 #define RG_CKRSEL 0x0020
245 #define RG_EEEPRG_EN 0x0010
246
247 /* OCP_EEE_CONFIG3 */
248 #define FST_SNR_EYE_R 0x1500 /* bit 7 ~ 15 */
249 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
250 #define MSK_PH 0x0006 /* bit 0 ~ 3 */
251
252 /* OCP_EEE_AR */
253 /* bit[15:14] function */
254 #define FUN_ADDR 0x0000
255 #define FUN_DATA 0x4000
256 /* bit[4:0] device addr */
257 #define DEVICE_ADDR 0x0007
258
259 /* OCP_EEE_DATA */
260 #define EEE_ADDR 0x003C
261 #define EEE_DATA 0x0002
262
263 enum rtl_register_content {
264 _100bps = 0x08,
265 _10bps = 0x04,
266 LINK_STATUS = 0x02,
267 FULL_DUP = 0x01,
268 };
269
270 #define RTL8152_REQT_READ 0xc0
271 #define RTL8152_REQT_WRITE 0x40
272 #define RTL8152_REQ_GET_REGS 0x05
273 #define RTL8152_REQ_SET_REGS 0x05
274
275 #define BYTE_EN_DWORD 0xff
276 #define BYTE_EN_WORD 0x33
277 #define BYTE_EN_BYTE 0x11
278 #define BYTE_EN_SIX_BYTES 0x3f
279 #define BYTE_EN_START_MASK 0x0f
280 #define BYTE_EN_END_MASK 0xf0
281
282 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
283 #define RTL8152_TX_TIMEOUT (HZ)
284
285 /* rtl8152 flags */
286 enum rtl8152_flags {
287 RTL8152_UNPLUG = 0,
288 RX_URB_FAIL,
289 RTL8152_SET_RX_MODE,
290 WORK_ENABLE
291 };
292
293 /* Define these values to match your device */
294 #define VENDOR_ID_REALTEK 0x0bda
295 #define PRODUCT_ID_RTL8152 0x8152
296
297 #define MCU_TYPE_PLA 0x0100
298 #define MCU_TYPE_USB 0x0000
299
300 struct rx_desc {
301 u32 opts1;
302 #define RX_LEN_MASK 0x7fff
303 u32 opts2;
304 u32 opts3;
305 u32 opts4;
306 u32 opts5;
307 u32 opts6;
308 };
309
310 struct tx_desc {
311 u32 opts1;
312 #define TX_FS (1 << 31) /* First segment of a packet */
313 #define TX_LS (1 << 30) /* Final segment of a packet */
314 #define TX_LEN_MASK 0xffff
315 u32 opts2;
316 };
317
318 struct r8152 {
319 unsigned long flags;
320 struct usb_device *udev;
321 struct tasklet_struct tl;
322 struct net_device *netdev;
323 struct urb *rx_urb, *tx_urb;
324 struct sk_buff *tx_skb, *rx_skb;
325 struct delayed_work schedule;
326 struct mii_if_info mii;
327 u32 msg_enable;
328 u16 ocp_base;
329 u8 version;
330 u8 speed;
331 };
332
333 enum rtl_version {
334 RTL_VER_UNKNOWN = 0,
335 RTL_VER_01,
336 RTL_VER_02
337 };
338
339 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
340 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
341 */
342 static const int multicast_filter_limit = 32;
343
344 static
345 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
346 {
347 int ret;
348 void *tmp;
349
350 tmp = kmalloc(size, GFP_KERNEL);
351 if (!tmp)
352 return -ENOMEM;
353
354 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
355 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
356 value, index, tmp, size, 500);
357
358 memcpy(data, tmp, size);
359 kfree(tmp);
360
361 return ret;
362 }
363
364 static
365 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
366 {
367 int ret;
368 void *tmp;
369
370 tmp = kmalloc(size, GFP_KERNEL);
371 if (!tmp)
372 return -ENOMEM;
373
374 memcpy(tmp, data, size);
375
376 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
377 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
378 value, index, tmp, size, 500);
379
380 kfree(tmp);
381 return ret;
382 }
383
384 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
385 void *data, u16 type)
386 {
387 u16 limit = 64;
388 int ret = 0;
389
390 if (test_bit(RTL8152_UNPLUG, &tp->flags))
391 return -ENODEV;
392
393 /* both size and indix must be 4 bytes align */
394 if ((size & 3) || !size || (index & 3) || !data)
395 return -EPERM;
396
397 if ((u32)index + (u32)size > 0xffff)
398 return -EPERM;
399
400 while (size) {
401 if (size > limit) {
402 ret = get_registers(tp, index, type, limit, data);
403 if (ret < 0)
404 break;
405
406 index += limit;
407 data += limit;
408 size -= limit;
409 } else {
410 ret = get_registers(tp, index, type, size, data);
411 if (ret < 0)
412 break;
413
414 index += size;
415 data += size;
416 size = 0;
417 break;
418 }
419 }
420
421 return ret;
422 }
423
424 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
425 u16 size, void *data, u16 type)
426 {
427 int ret;
428 u16 byteen_start, byteen_end, byen;
429 u16 limit = 512;
430
431 if (test_bit(RTL8152_UNPLUG, &tp->flags))
432 return -ENODEV;
433
434 /* both size and indix must be 4 bytes align */
435 if ((size & 3) || !size || (index & 3) || !data)
436 return -EPERM;
437
438 if ((u32)index + (u32)size > 0xffff)
439 return -EPERM;
440
441 byteen_start = byteen & BYTE_EN_START_MASK;
442 byteen_end = byteen & BYTE_EN_END_MASK;
443
444 byen = byteen_start | (byteen_start << 4);
445 ret = set_registers(tp, index, type | byen, 4, data);
446 if (ret < 0)
447 goto error1;
448
449 index += 4;
450 data += 4;
451 size -= 4;
452
453 if (size) {
454 size -= 4;
455
456 while (size) {
457 if (size > limit) {
458 ret = set_registers(tp, index,
459 type | BYTE_EN_DWORD,
460 limit, data);
461 if (ret < 0)
462 goto error1;
463
464 index += limit;
465 data += limit;
466 size -= limit;
467 } else {
468 ret = set_registers(tp, index,
469 type | BYTE_EN_DWORD,
470 size, data);
471 if (ret < 0)
472 goto error1;
473
474 index += size;
475 data += size;
476 size = 0;
477 break;
478 }
479 }
480
481 byen = byteen_end | (byteen_end >> 4);
482 ret = set_registers(tp, index, type | byen, 4, data);
483 if (ret < 0)
484 goto error1;
485 }
486
487 error1:
488 return ret;
489 }
490
491 static inline
492 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
493 {
494 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
495 }
496
497 static inline
498 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
499 {
500 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
501 }
502
503 static inline
504 int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
505 {
506 return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
507 }
508
509 static inline
510 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
511 {
512 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
513 }
514
515 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
516 {
517 __le32 data;
518
519 generic_ocp_read(tp, index, sizeof(data), &data, type);
520
521 return __le32_to_cpu(data);
522 }
523
524 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
525 {
526 __le32 tmp = __cpu_to_le32(data);
527
528 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
529 }
530
531 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
532 {
533 u32 data;
534 __le32 tmp;
535 u8 shift = index & 2;
536
537 index &= ~3;
538
539 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
540
541 data = __le32_to_cpu(tmp);
542 data >>= (shift * 8);
543 data &= 0xffff;
544
545 return (u16)data;
546 }
547
548 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
549 {
550 u32 mask = 0xffff;
551 __le32 tmp;
552 u16 byen = BYTE_EN_WORD;
553 u8 shift = index & 2;
554
555 data &= mask;
556
557 if (index & 2) {
558 byen <<= shift;
559 mask <<= (shift * 8);
560 data <<= (shift * 8);
561 index &= ~3;
562 }
563
564 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
565
566 data |= __le32_to_cpu(tmp) & ~mask;
567 tmp = __cpu_to_le32(data);
568
569 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
570 }
571
572 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
573 {
574 u32 data;
575 __le32 tmp;
576 u8 shift = index & 3;
577
578 index &= ~3;
579
580 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
581
582 data = __le32_to_cpu(tmp);
583 data >>= (shift * 8);
584 data &= 0xff;
585
586 return (u8)data;
587 }
588
589 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
590 {
591 u32 mask = 0xff;
592 __le32 tmp;
593 u16 byen = BYTE_EN_BYTE;
594 u8 shift = index & 3;
595
596 data &= mask;
597
598 if (index & 3) {
599 byen <<= shift;
600 mask <<= (shift * 8);
601 data <<= (shift * 8);
602 index &= ~3;
603 }
604
605 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
606
607 data |= __le32_to_cpu(tmp) & ~mask;
608 tmp = __cpu_to_le32(data);
609
610 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
611 }
612
613 static void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
614 {
615 u32 ocp_data;
616 int i;
617
618 ocp_data = PHYAR_FLAG | ((reg_addr & 0x1f) << 16) |
619 (value & 0xffff);
620
621 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_PHYAR, ocp_data);
622
623 for (i = 20; i > 0; i--) {
624 udelay(25);
625 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_PHYAR);
626 if (!(ocp_data & PHYAR_FLAG))
627 break;
628 }
629 udelay(20);
630 }
631
632 static int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
633 {
634 u32 ocp_data;
635 int i;
636
637 ocp_data = (reg_addr & 0x1f) << 16;
638 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_PHYAR, ocp_data);
639
640 for (i = 20; i > 0; i--) {
641 udelay(25);
642 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_PHYAR);
643 if (ocp_data & PHYAR_FLAG)
644 break;
645 }
646 udelay(20);
647
648 if (!(ocp_data & PHYAR_FLAG))
649 return -EAGAIN;
650
651 return (u16)(ocp_data & 0xffff);
652 }
653
654 static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
655 {
656 struct r8152 *tp = netdev_priv(netdev);
657
658 if (phy_id != R8152_PHY_ID)
659 return -EINVAL;
660
661 return r8152_mdio_read(tp, reg);
662 }
663
664 static
665 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
666 {
667 struct r8152 *tp = netdev_priv(netdev);
668
669 if (phy_id != R8152_PHY_ID)
670 return;
671
672 r8152_mdio_write(tp, reg, val);
673 }
674
675 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
676 {
677 u16 ocp_base, ocp_index;
678
679 ocp_base = addr & 0xf000;
680 if (ocp_base != tp->ocp_base) {
681 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
682 tp->ocp_base = ocp_base;
683 }
684
685 ocp_index = (addr & 0x0fff) | 0xb000;
686 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
687 }
688
689 static inline void set_ethernet_addr(struct r8152 *tp)
690 {
691 struct net_device *dev = tp->netdev;
692 u8 node_id[8] = {0};
693
694 if (pla_ocp_read(tp, PLA_IDR, sizeof(node_id), node_id) < 0)
695 netif_notice(tp, probe, dev, "inet addr fail\n");
696 else {
697 memcpy(dev->dev_addr, node_id, dev->addr_len);
698 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
699 }
700 }
701
702 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
703 {
704 struct r8152 *tp = netdev_priv(netdev);
705 struct sockaddr *addr = p;
706
707 if (!is_valid_ether_addr(addr->sa_data))
708 return -EADDRNOTAVAIL;
709
710 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
711
712 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
713 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
714 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
715
716 return 0;
717 }
718
719 static int alloc_all_urbs(struct r8152 *tp)
720 {
721 tp->rx_urb = usb_alloc_urb(0, GFP_KERNEL);
722 if (!tp->rx_urb)
723 return 0;
724 tp->tx_urb = usb_alloc_urb(0, GFP_KERNEL);
725 if (!tp->tx_urb) {
726 usb_free_urb(tp->rx_urb);
727 return 0;
728 }
729
730 return 1;
731 }
732
733 static void free_all_urbs(struct r8152 *tp)
734 {
735 usb_free_urb(tp->rx_urb);
736 usb_free_urb(tp->tx_urb);
737 }
738
739 static struct net_device_stats *rtl8152_get_stats(struct net_device *dev)
740 {
741 return &dev->stats;
742 }
743
744 static void read_bulk_callback(struct urb *urb)
745 {
746 struct r8152 *tp;
747 unsigned pkt_len;
748 struct sk_buff *skb;
749 struct net_device *netdev;
750 struct net_device_stats *stats;
751 int status = urb->status;
752 int result;
753 struct rx_desc *rx_desc;
754
755 tp = urb->context;
756 if (!tp)
757 return;
758 if (test_bit(RTL8152_UNPLUG, &tp->flags))
759 return;
760 netdev = tp->netdev;
761 if (!netif_device_present(netdev))
762 return;
763
764 stats = rtl8152_get_stats(netdev);
765 switch (status) {
766 case 0:
767 break;
768 case -ESHUTDOWN:
769 set_bit(RTL8152_UNPLUG, &tp->flags);
770 netif_device_detach(tp->netdev);
771 case -ENOENT:
772 return; /* the urb is in unlink state */
773 case -ETIME:
774 pr_warn_ratelimited("may be reset is needed?..\n");
775 goto goon;
776 default:
777 pr_warn_ratelimited("Rx status %d\n", status);
778 goto goon;
779 }
780
781 /* protect against short packets (tell me why we got some?!?) */
782 if (urb->actual_length < sizeof(*rx_desc))
783 goto goon;
784
785
786 rx_desc = (struct rx_desc *)urb->transfer_buffer;
787 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
788 if (urb->actual_length < sizeof(struct rx_desc) + pkt_len)
789 goto goon;
790
791 skb = netdev_alloc_skb_ip_align(netdev, pkt_len);
792 if (!skb)
793 goto goon;
794
795 memcpy(skb->data, tp->rx_skb->data + sizeof(struct rx_desc), pkt_len);
796 skb_put(skb, pkt_len);
797 skb->protocol = eth_type_trans(skb, netdev);
798 netif_rx(skb);
799 stats->rx_packets++;
800 stats->rx_bytes += pkt_len;
801 goon:
802 usb_fill_bulk_urb(tp->rx_urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
803 tp->rx_skb->data, RTL8152_RMS + sizeof(struct rx_desc),
804 (usb_complete_t)read_bulk_callback, tp);
805 result = usb_submit_urb(tp->rx_urb, GFP_ATOMIC);
806 if (result == -ENODEV) {
807 netif_device_detach(tp->netdev);
808 } else if (result) {
809 set_bit(RX_URB_FAIL, &tp->flags);
810 goto resched;
811 } else {
812 clear_bit(RX_URB_FAIL, &tp->flags);
813 }
814
815 return;
816 resched:
817 tasklet_schedule(&tp->tl);
818 }
819
820 static void rx_fixup(unsigned long data)
821 {
822 struct r8152 *tp;
823 int status;
824
825 tp = (struct r8152 *)data;
826 if (!test_bit(WORK_ENABLE, &tp->flags))
827 return;
828
829 status = usb_submit_urb(tp->rx_urb, GFP_ATOMIC);
830 if (status == -ENODEV) {
831 netif_device_detach(tp->netdev);
832 } else if (status) {
833 set_bit(RX_URB_FAIL, &tp->flags);
834 goto tlsched;
835 } else {
836 clear_bit(RX_URB_FAIL, &tp->flags);
837 }
838
839 return;
840 tlsched:
841 tasklet_schedule(&tp->tl);
842 }
843
844 static void write_bulk_callback(struct urb *urb)
845 {
846 struct r8152 *tp;
847 int status = urb->status;
848
849 tp = urb->context;
850 if (!tp)
851 return;
852 dev_kfree_skb_irq(tp->tx_skb);
853 if (!netif_device_present(tp->netdev))
854 return;
855 if (status)
856 dev_info(&urb->dev->dev, "%s: Tx status %d\n",
857 tp->netdev->name, status);
858 tp->netdev->trans_start = jiffies;
859 netif_wake_queue(tp->netdev);
860 }
861
862 static void rtl8152_tx_timeout(struct net_device *netdev)
863 {
864 struct r8152 *tp = netdev_priv(netdev);
865 struct net_device_stats *stats = rtl8152_get_stats(netdev);
866 netif_warn(tp, tx_err, netdev, "Tx timeout.\n");
867 usb_unlink_urb(tp->tx_urb);
868 stats->tx_errors++;
869 }
870
871 static void rtl8152_set_rx_mode(struct net_device *netdev)
872 {
873 struct r8152 *tp = netdev_priv(netdev);
874
875 if (tp->speed & LINK_STATUS)
876 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
877 }
878
879 static void _rtl8152_set_rx_mode(struct net_device *netdev)
880 {
881 struct r8152 *tp = netdev_priv(netdev);
882 u32 mc_filter[2]; /* Multicast hash filter */
883 __le32 tmp[2];
884 u32 ocp_data;
885
886 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
887 netif_stop_queue(netdev);
888 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
889 ocp_data &= ~RCR_ACPT_ALL;
890 ocp_data |= RCR_AB | RCR_APM;
891
892 if (netdev->flags & IFF_PROMISC) {
893 /* Unconditionally log net taps. */
894 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
895 ocp_data |= RCR_AM | RCR_AAP;
896 mc_filter[1] = mc_filter[0] = 0xffffffff;
897 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
898 (netdev->flags & IFF_ALLMULTI)) {
899 /* Too many to filter perfectly -- accept all multicasts. */
900 ocp_data |= RCR_AM;
901 mc_filter[1] = mc_filter[0] = 0xffffffff;
902 } else {
903 struct netdev_hw_addr *ha;
904
905 mc_filter[1] = mc_filter[0] = 0;
906 netdev_for_each_mc_addr(ha, netdev) {
907 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
908 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
909 ocp_data |= RCR_AM;
910 }
911 }
912
913 tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
914 tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
915
916 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
917 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
918 netif_wake_queue(netdev);
919 }
920
921 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
922 struct net_device *netdev)
923 {
924 struct r8152 *tp = netdev_priv(netdev);
925 struct net_device_stats *stats = rtl8152_get_stats(netdev);
926 struct tx_desc *tx_desc;
927 unsigned int len;
928 int res;
929
930 netif_stop_queue(netdev);
931 len = skb->len;
932 if (skb_header_cloned(skb) || skb_headroom(skb) < sizeof(*tx_desc)) {
933 struct sk_buff *tx_skb;
934
935 tx_skb = skb_copy_expand(skb, sizeof(*tx_desc), 0, GFP_ATOMIC);
936 dev_kfree_skb_any(skb);
937 if (!tx_skb) {
938 stats->tx_dropped++;
939 netif_wake_queue(netdev);
940 return NETDEV_TX_OK;
941 }
942 skb = tx_skb;
943 }
944 tx_desc = (struct tx_desc *)skb_push(skb, sizeof(*tx_desc));
945 memset(tx_desc, 0, sizeof(*tx_desc));
946 tx_desc->opts1 = cpu_to_le32((len & TX_LEN_MASK) | TX_FS | TX_LS);
947 tp->tx_skb = skb;
948 skb_tx_timestamp(skb);
949 usb_fill_bulk_urb(tp->tx_urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
950 skb->data, skb->len,
951 (usb_complete_t)write_bulk_callback, tp);
952 res = usb_submit_urb(tp->tx_urb, GFP_ATOMIC);
953 if (res) {
954 /* Can we get/handle EPIPE here? */
955 if (res == -ENODEV) {
956 netif_device_detach(tp->netdev);
957 } else {
958 netif_warn(tp, tx_err, netdev,
959 "failed tx_urb %d\n", res);
960 stats->tx_errors++;
961 netif_start_queue(netdev);
962 }
963 } else {
964 stats->tx_packets++;
965 stats->tx_bytes += skb->len;
966 }
967
968 return NETDEV_TX_OK;
969 }
970
971 static void r8152b_reset_packet_filter(struct r8152 *tp)
972 {
973 u32 ocp_data;
974
975 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
976 ocp_data &= ~FMC_FCR_MCU_EN;
977 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
978 ocp_data |= FMC_FCR_MCU_EN;
979 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
980 }
981
982 static void rtl8152_nic_reset(struct r8152 *tp)
983 {
984 int i;
985
986 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
987
988 for (i = 0; i < 1000; i++) {
989 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
990 break;
991 udelay(100);
992 }
993 }
994
995 static inline u8 rtl8152_get_speed(struct r8152 *tp)
996 {
997 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
998 }
999
1000 static int rtl8152_enable(struct r8152 *tp)
1001 {
1002 u32 ocp_data;
1003 u8 speed;
1004
1005 speed = rtl8152_get_speed(tp);
1006 if (speed & _100bps) {
1007 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
1008 ocp_data &= ~EEEP_CR_EEEP_TX;
1009 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
1010 } else {
1011 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
1012 ocp_data |= EEEP_CR_EEEP_TX;
1013 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
1014 }
1015
1016 r8152b_reset_packet_filter(tp);
1017
1018 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
1019 ocp_data |= CR_RE | CR_TE;
1020 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
1021
1022 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
1023 ocp_data &= ~RXDY_GATED_EN;
1024 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
1025
1026 usb_fill_bulk_urb(tp->rx_urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
1027 tp->rx_skb->data, RTL8152_RMS + sizeof(struct rx_desc),
1028 (usb_complete_t)read_bulk_callback, tp);
1029
1030 return usb_submit_urb(tp->rx_urb, GFP_KERNEL);
1031 }
1032
1033 static void rtl8152_disable(struct r8152 *tp)
1034 {
1035 u32 ocp_data;
1036 int i;
1037
1038 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1039 ocp_data &= ~RCR_ACPT_ALL;
1040 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1041
1042 usb_kill_urb(tp->tx_urb);
1043
1044 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
1045 ocp_data |= RXDY_GATED_EN;
1046 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
1047
1048 for (i = 0; i < 1000; i++) {
1049 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1050 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
1051 break;
1052 mdelay(1);
1053 }
1054
1055 for (i = 0; i < 1000; i++) {
1056 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
1057 break;
1058 mdelay(1);
1059 }
1060
1061 usb_kill_urb(tp->rx_urb);
1062
1063 rtl8152_nic_reset(tp);
1064 }
1065
1066 static void r8152b_exit_oob(struct r8152 *tp)
1067 {
1068 u32 ocp_data;
1069 int i;
1070
1071 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1072 ocp_data &= ~RCR_ACPT_ALL;
1073 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1074
1075 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
1076 ocp_data |= RXDY_GATED_EN;
1077 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
1078
1079 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1080 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
1081
1082 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1083 ocp_data &= ~NOW_IS_OOB;
1084 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
1085
1086 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
1087 ocp_data &= ~MCU_BORW_EN;
1088 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
1089
1090 for (i = 0; i < 1000; i++) {
1091 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1092 if (ocp_data & LINK_LIST_READY)
1093 break;
1094 mdelay(1);
1095 }
1096
1097 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
1098 ocp_data |= RE_INIT_LL;
1099 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
1100
1101 for (i = 0; i < 1000; i++) {
1102 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1103 if (ocp_data & LINK_LIST_READY)
1104 break;
1105 mdelay(1);
1106 }
1107
1108 rtl8152_nic_reset(tp);
1109
1110 /* rx share fifo credit full threshold */
1111 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
1112
1113 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_DEV_STAT);
1114 ocp_data &= STAT_SPEED_MASK;
1115 if (ocp_data == STAT_SPEED_FULL) {
1116 /* rx share fifo credit near full threshold */
1117 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
1118 RXFIFO_THR2_FULL);
1119 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
1120 RXFIFO_THR3_FULL);
1121 } else {
1122 /* rx share fifo credit near full threshold */
1123 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
1124 RXFIFO_THR2_HIGH);
1125 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
1126 RXFIFO_THR3_HIGH);
1127 }
1128
1129 /* TX share fifo free credit full threshold */
1130 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
1131
1132 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
1133 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_BUF_THR);
1134 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
1135 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
1136
1137 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
1138 ocp_data &= ~CPCR_RX_VLAN;
1139 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
1140
1141 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
1142
1143 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
1144 ocp_data |= TCR0_AUTO_FIFO;
1145 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
1146 }
1147
1148 static void r8152b_enter_oob(struct r8152 *tp)
1149 {
1150 u32 ocp_data;
1151 int i;
1152
1153 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1154 ocp_data &= ~NOW_IS_OOB;
1155 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
1156
1157 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
1158 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
1159 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
1160
1161 rtl8152_disable(tp);
1162
1163 for (i = 0; i < 1000; i++) {
1164 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1165 if (ocp_data & LINK_LIST_READY)
1166 break;
1167 mdelay(1);
1168 }
1169
1170 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
1171 ocp_data |= RE_INIT_LL;
1172 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
1173
1174 for (i = 0; i < 1000; i++) {
1175 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1176 if (ocp_data & LINK_LIST_READY)
1177 break;
1178 mdelay(1);
1179 }
1180
1181 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
1182
1183 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
1184 ocp_data |= MAGIC_EN;
1185 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
1186
1187 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
1188 ocp_data |= CPCR_RX_VLAN;
1189 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
1190
1191 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
1192 ocp_data |= ALDPS_PROXY_MODE;
1193 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
1194
1195 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1196 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
1197 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
1198
1199 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5, LAN_WAKE_EN);
1200
1201 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
1202 ocp_data &= ~RXDY_GATED_EN;
1203 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
1204
1205 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1206 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
1207 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1208 }
1209
1210 static void r8152b_disable_aldps(struct r8152 *tp)
1211 {
1212 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
1213 msleep(20);
1214 }
1215
1216 static inline void r8152b_enable_aldps(struct r8152 *tp)
1217 {
1218 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
1219 LINKENA | DIS_SDSAVE);
1220 }
1221
1222 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
1223 {
1224 u16 bmcr, anar;
1225 int ret = 0;
1226
1227 cancel_delayed_work_sync(&tp->schedule);
1228 anar = r8152_mdio_read(tp, MII_ADVERTISE);
1229 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1230 ADVERTISE_100HALF | ADVERTISE_100FULL);
1231
1232 if (autoneg == AUTONEG_DISABLE) {
1233 if (speed == SPEED_10) {
1234 bmcr = 0;
1235 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
1236 } else if (speed == SPEED_100) {
1237 bmcr = BMCR_SPEED100;
1238 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
1239 } else {
1240 ret = -EINVAL;
1241 goto out;
1242 }
1243
1244 if (duplex == DUPLEX_FULL)
1245 bmcr |= BMCR_FULLDPLX;
1246 } else {
1247 if (speed == SPEED_10) {
1248 if (duplex == DUPLEX_FULL)
1249 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
1250 else
1251 anar |= ADVERTISE_10HALF;
1252 } else if (speed == SPEED_100) {
1253 if (duplex == DUPLEX_FULL) {
1254 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
1255 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
1256 } else {
1257 anar |= ADVERTISE_10HALF;
1258 anar |= ADVERTISE_100HALF;
1259 }
1260 } else {
1261 ret = -EINVAL;
1262 goto out;
1263 }
1264
1265 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1266 }
1267
1268 r8152_mdio_write(tp, MII_ADVERTISE, anar);
1269 r8152_mdio_write(tp, MII_BMCR, bmcr);
1270
1271 out:
1272 schedule_delayed_work(&tp->schedule, 5 * HZ);
1273
1274 return ret;
1275 }
1276
1277 static void rtl8152_down(struct r8152 *tp)
1278 {
1279 u32 ocp_data;
1280
1281 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
1282 ocp_data &= ~POWER_CUT;
1283 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
1284
1285 r8152b_disable_aldps(tp);
1286 r8152b_enter_oob(tp);
1287 r8152b_enable_aldps(tp);
1288 }
1289
1290 static void set_carrier(struct r8152 *tp)
1291 {
1292 struct net_device *netdev = tp->netdev;
1293 u8 speed;
1294
1295 speed = rtl8152_get_speed(tp);
1296
1297 if (speed & LINK_STATUS) {
1298 if (!(tp->speed & LINK_STATUS)) {
1299 rtl8152_enable(tp);
1300 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
1301 netif_carrier_on(netdev);
1302 }
1303 } else {
1304 if (tp->speed & LINK_STATUS) {
1305 netif_carrier_off(netdev);
1306 rtl8152_disable(tp);
1307 }
1308 }
1309 tp->speed = speed;
1310 }
1311
1312 static void rtl_work_func_t(struct work_struct *work)
1313 {
1314 struct r8152 *tp = container_of(work, struct r8152, schedule.work);
1315
1316 if (!test_bit(WORK_ENABLE, &tp->flags))
1317 goto out1;
1318
1319 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1320 goto out1;
1321
1322 set_carrier(tp);
1323
1324 if (test_bit(RTL8152_SET_RX_MODE, &tp->flags))
1325 _rtl8152_set_rx_mode(tp->netdev);
1326
1327 schedule_delayed_work(&tp->schedule, HZ);
1328
1329 out1:
1330 return;
1331 }
1332
1333 static int rtl8152_open(struct net_device *netdev)
1334 {
1335 struct r8152 *tp = netdev_priv(netdev);
1336 int res = 0;
1337
1338 tp->speed = rtl8152_get_speed(tp);
1339 if (tp->speed & LINK_STATUS) {
1340 res = rtl8152_enable(tp);
1341 if (res) {
1342 if (res == -ENODEV)
1343 netif_device_detach(tp->netdev);
1344
1345 netif_err(tp, ifup, netdev,
1346 "rtl8152_open failed: %d\n", res);
1347 return res;
1348 }
1349
1350 netif_carrier_on(netdev);
1351 } else {
1352 netif_stop_queue(netdev);
1353 netif_carrier_off(netdev);
1354 }
1355
1356 rtl8152_set_speed(tp, AUTONEG_ENABLE, SPEED_100, DUPLEX_FULL);
1357 netif_start_queue(netdev);
1358 set_bit(WORK_ENABLE, &tp->flags);
1359 schedule_delayed_work(&tp->schedule, 0);
1360
1361 return res;
1362 }
1363
1364 static int rtl8152_close(struct net_device *netdev)
1365 {
1366 struct r8152 *tp = netdev_priv(netdev);
1367 int res = 0;
1368
1369 clear_bit(WORK_ENABLE, &tp->flags);
1370 cancel_delayed_work_sync(&tp->schedule);
1371 netif_stop_queue(netdev);
1372 rtl8152_disable(tp);
1373
1374 return res;
1375 }
1376
1377 static void rtl_clear_bp(struct r8152 *tp)
1378 {
1379 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_0, 0);
1380 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_2, 0);
1381 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_4, 0);
1382 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_6, 0);
1383 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_0, 0);
1384 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_2, 0);
1385 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_4, 0);
1386 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_6, 0);
1387 mdelay(3);
1388 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_BA, 0);
1389 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_BA, 0);
1390 }
1391
1392 static void r8152b_enable_eee(struct r8152 *tp)
1393 {
1394 u32 ocp_data;
1395
1396 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
1397 ocp_data |= EEE_RX_EN | EEE_TX_EN;
1398 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
1399 ocp_reg_write(tp, OCP_EEE_CONFIG1, RG_TXLPI_MSK_HFDUP | RG_MATCLR_EN |
1400 EEE_10_CAP | EEE_NWAY_EN |
1401 TX_QUIET_EN | RX_QUIET_EN |
1402 SDRISETIME | RG_RXLPI_MSK_HFDUP |
1403 SDFALLTIME);
1404 ocp_reg_write(tp, OCP_EEE_CONFIG2, RG_LPIHYS_NUM | RG_DACQUIET_EN |
1405 RG_LDVQUIET_EN | RG_CKRSEL |
1406 RG_EEEPRG_EN);
1407 ocp_reg_write(tp, OCP_EEE_CONFIG3, FST_SNR_EYE_R | RG_LFS_SEL | MSK_PH);
1408 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | DEVICE_ADDR);
1409 ocp_reg_write(tp, OCP_EEE_DATA, EEE_ADDR);
1410 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | DEVICE_ADDR);
1411 ocp_reg_write(tp, OCP_EEE_DATA, EEE_DATA);
1412 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
1413 }
1414
1415 static void r8152b_enable_fc(struct r8152 *tp)
1416 {
1417 u16 anar;
1418
1419 anar = r8152_mdio_read(tp, MII_ADVERTISE);
1420 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1421 r8152_mdio_write(tp, MII_ADVERTISE, anar);
1422 }
1423
1424 static void r8152b_hw_phy_cfg(struct r8152 *tp)
1425 {
1426 r8152_mdio_write(tp, MII_BMCR, BMCR_ANENABLE);
1427 r8152b_disable_aldps(tp);
1428 }
1429
1430 static void r8152b_init(struct r8152 *tp)
1431 {
1432 u32 ocp_data;
1433 int i;
1434
1435 rtl_clear_bp(tp);
1436
1437 if (tp->version == RTL_VER_01) {
1438 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
1439 ocp_data &= ~LED_MODE_MASK;
1440 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
1441 }
1442
1443 r8152b_hw_phy_cfg(tp);
1444
1445 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
1446 ocp_data &= ~POWER_CUT;
1447 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
1448
1449 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
1450 ocp_data &= ~RWSUME_INDICATE;
1451 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
1452
1453 r8152b_exit_oob(tp);
1454
1455 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
1456 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
1457 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
1458 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
1459 ocp_data &= ~MCU_CLK_RATIO_MASK;
1460 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
1461 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
1462 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
1463 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
1464 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
1465
1466 r8152b_enable_eee(tp);
1467 r8152b_enable_aldps(tp);
1468 r8152b_enable_fc(tp);
1469
1470 r8152_mdio_write(tp, MII_BMCR, BMCR_RESET | BMCR_ANENABLE |
1471 BMCR_ANRESTART);
1472 for (i = 0; i < 100; i++) {
1473 udelay(100);
1474 if (!(r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET))
1475 break;
1476 }
1477
1478 /* disable rx aggregation */
1479 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
1480 ocp_data |= RX_AGG_DISABLE;
1481 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
1482 }
1483
1484 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
1485 {
1486 struct r8152 *tp = usb_get_intfdata(intf);
1487
1488 netif_device_detach(tp->netdev);
1489
1490 if (netif_running(tp->netdev)) {
1491 clear_bit(WORK_ENABLE, &tp->flags);
1492 cancel_delayed_work_sync(&tp->schedule);
1493 }
1494
1495 rtl8152_down(tp);
1496
1497 return 0;
1498 }
1499
1500 static int rtl8152_resume(struct usb_interface *intf)
1501 {
1502 struct r8152 *tp = usb_get_intfdata(intf);
1503
1504 r8152b_init(tp);
1505 netif_device_attach(tp->netdev);
1506 if (netif_running(tp->netdev)) {
1507 rtl8152_enable(tp);
1508 set_bit(WORK_ENABLE, &tp->flags);
1509 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
1510 schedule_delayed_work(&tp->schedule, 0);
1511 }
1512
1513 return 0;
1514 }
1515
1516 static void rtl8152_get_drvinfo(struct net_device *netdev,
1517 struct ethtool_drvinfo *info)
1518 {
1519 struct r8152 *tp = netdev_priv(netdev);
1520
1521 strncpy(info->driver, MODULENAME, ETHTOOL_BUSINFO_LEN);
1522 strncpy(info->version, DRIVER_VERSION, ETHTOOL_BUSINFO_LEN);
1523 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
1524 }
1525
1526 static
1527 int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1528 {
1529 struct r8152 *tp = netdev_priv(netdev);
1530
1531 if (!tp->mii.mdio_read)
1532 return -EOPNOTSUPP;
1533
1534 return mii_ethtool_gset(&tp->mii, cmd);
1535 }
1536
1537 static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1538 {
1539 struct r8152 *tp = netdev_priv(dev);
1540
1541 return rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex);
1542 }
1543
1544 static struct ethtool_ops ops = {
1545 .get_drvinfo = rtl8152_get_drvinfo,
1546 .get_settings = rtl8152_get_settings,
1547 .set_settings = rtl8152_set_settings,
1548 .get_link = ethtool_op_get_link,
1549 };
1550
1551 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
1552 {
1553 struct r8152 *tp = netdev_priv(netdev);
1554 struct mii_ioctl_data *data = if_mii(rq);
1555 int res = 0;
1556
1557 switch (cmd) {
1558 case SIOCGMIIPHY:
1559 data->phy_id = R8152_PHY_ID; /* Internal PHY */
1560 break;
1561
1562 case SIOCGMIIREG:
1563 data->val_out = r8152_mdio_read(tp, data->reg_num);
1564 break;
1565
1566 case SIOCSMIIREG:
1567 if (!capable(CAP_NET_ADMIN)) {
1568 res = -EPERM;
1569 break;
1570 }
1571 r8152_mdio_write(tp, data->reg_num, data->val_in);
1572 break;
1573
1574 default:
1575 res = -EOPNOTSUPP;
1576 }
1577
1578 return res;
1579 }
1580
1581 static const struct net_device_ops rtl8152_netdev_ops = {
1582 .ndo_open = rtl8152_open,
1583 .ndo_stop = rtl8152_close,
1584 .ndo_do_ioctl = rtl8152_ioctl,
1585 .ndo_start_xmit = rtl8152_start_xmit,
1586 .ndo_tx_timeout = rtl8152_tx_timeout,
1587 .ndo_set_rx_mode = rtl8152_set_rx_mode,
1588 .ndo_set_mac_address = rtl8152_set_mac_address,
1589
1590 .ndo_change_mtu = eth_change_mtu,
1591 .ndo_validate_addr = eth_validate_addr,
1592 };
1593
1594 static void r8152b_get_version(struct r8152 *tp)
1595 {
1596 u32 ocp_data;
1597 u16 version;
1598
1599 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
1600 version = (u16)(ocp_data & VERSION_MASK);
1601
1602 switch (version) {
1603 case 0x4c00:
1604 tp->version = RTL_VER_01;
1605 break;
1606 case 0x4c10:
1607 tp->version = RTL_VER_02;
1608 break;
1609 default:
1610 netif_info(tp, probe, tp->netdev,
1611 "Unknown version 0x%04x\n", version);
1612 break;
1613 }
1614 }
1615
1616 static int rtl8152_probe(struct usb_interface *intf,
1617 const struct usb_device_id *id)
1618 {
1619 struct usb_device *udev = interface_to_usbdev(intf);
1620 struct r8152 *tp;
1621 struct net_device *netdev;
1622
1623 if (udev->actconfig->desc.bConfigurationValue != 1) {
1624 usb_driver_set_configuration(udev, 1);
1625 return -ENODEV;
1626 }
1627
1628 netdev = alloc_etherdev(sizeof(struct r8152));
1629 if (!netdev) {
1630 dev_err(&intf->dev, "Out of memory");
1631 return -ENOMEM;
1632 }
1633
1634 tp = netdev_priv(netdev);
1635 tp->msg_enable = 0x7FFF;
1636
1637 tasklet_init(&tp->tl, rx_fixup, (unsigned long)tp);
1638 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
1639
1640 tp->udev = udev;
1641 tp->netdev = netdev;
1642 netdev->netdev_ops = &rtl8152_netdev_ops;
1643 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
1644 netdev->features &= ~NETIF_F_IP_CSUM;
1645 SET_ETHTOOL_OPS(netdev, &ops);
1646 tp->speed = 0;
1647
1648 tp->mii.dev = netdev;
1649 tp->mii.mdio_read = read_mii_word;
1650 tp->mii.mdio_write = write_mii_word;
1651 tp->mii.phy_id_mask = 0x3f;
1652 tp->mii.reg_num_mask = 0x1f;
1653 tp->mii.phy_id = R8152_PHY_ID;
1654 tp->mii.supports_gmii = 0;
1655
1656 r8152b_get_version(tp);
1657 r8152b_init(tp);
1658 set_ethernet_addr(tp);
1659
1660 if (!alloc_all_urbs(tp)) {
1661 netif_err(tp, probe, netdev, "out of memory");
1662 goto out;
1663 }
1664
1665 tp->rx_skb = netdev_alloc_skb(netdev,
1666 RTL8152_RMS + sizeof(struct rx_desc));
1667 if (!tp->rx_skb)
1668 goto out1;
1669
1670 usb_set_intfdata(intf, tp);
1671 SET_NETDEV_DEV(netdev, &intf->dev);
1672
1673
1674 if (register_netdev(netdev) != 0) {
1675 netif_err(tp, probe, netdev, "couldn't register the device");
1676 goto out2;
1677 }
1678
1679 netif_info(tp, probe, netdev, "%s", DRIVER_VERSION);
1680
1681 return 0;
1682
1683 out2:
1684 usb_set_intfdata(intf, NULL);
1685 dev_kfree_skb(tp->rx_skb);
1686 out1:
1687 free_all_urbs(tp);
1688 out:
1689 free_netdev(netdev);
1690 return -EIO;
1691 }
1692
1693 static void rtl8152_unload(struct r8152 *tp)
1694 {
1695 u32 ocp_data;
1696
1697 if (tp->version != RTL_VER_01) {
1698 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
1699 ocp_data |= POWER_CUT;
1700 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
1701 }
1702
1703 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
1704 ocp_data &= ~RWSUME_INDICATE;
1705 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
1706 }
1707
1708 static void rtl8152_disconnect(struct usb_interface *intf)
1709 {
1710 struct r8152 *tp = usb_get_intfdata(intf);
1711
1712 usb_set_intfdata(intf, NULL);
1713 if (tp) {
1714 set_bit(RTL8152_UNPLUG, &tp->flags);
1715 tasklet_kill(&tp->tl);
1716 unregister_netdev(tp->netdev);
1717 rtl8152_unload(tp);
1718 free_all_urbs(tp);
1719 if (tp->rx_skb)
1720 dev_kfree_skb(tp->rx_skb);
1721 free_netdev(tp->netdev);
1722 }
1723 }
1724
1725 /* table of devices that work with this driver */
1726 static struct usb_device_id rtl8152_table[] = {
1727 {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8152)},
1728 {}
1729 };
1730
1731 MODULE_DEVICE_TABLE(usb, rtl8152_table);
1732
1733 static struct usb_driver rtl8152_driver = {
1734 .name = MODULENAME,
1735 .probe = rtl8152_probe,
1736 .disconnect = rtl8152_disconnect,
1737 .id_table = rtl8152_table,
1738 .suspend = rtl8152_suspend,
1739 .resume = rtl8152_resume
1740 };
1741
1742 module_usb_driver(rtl8152_driver);
1743
1744 MODULE_AUTHOR(DRIVER_AUTHOR);
1745 MODULE_DESCRIPTION(DRIVER_DESC);
1746 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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