Merge tag 'master-2014-11-25' of git://git.kernel.org/pub/scm/linux/kernel/git/linvil...
[deliverable/linux.git] / drivers / net / usb / r8152.c
1 /*
2 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * version 2 as published by the Free Software Foundation.
7 *
8 */
9
10 #include <linux/signal.h>
11 #include <linux/slab.h>
12 #include <linux/module.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/mii.h>
16 #include <linux/ethtool.h>
17 #include <linux/usb.h>
18 #include <linux/crc32.h>
19 #include <linux/if_vlan.h>
20 #include <linux/uaccess.h>
21 #include <linux/list.h>
22 #include <linux/ip.h>
23 #include <linux/ipv6.h>
24 #include <net/ip6_checksum.h>
25 #include <uapi/linux/mdio.h>
26 #include <linux/mdio.h>
27
28 /* Version Information */
29 #define DRIVER_VERSION "v1.07.0 (2014/10/09)"
30 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
31 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
32 #define MODULENAME "r8152"
33
34 #define R8152_PHY_ID 32
35
36 #define PLA_IDR 0xc000
37 #define PLA_RCR 0xc010
38 #define PLA_RMS 0xc016
39 #define PLA_RXFIFO_CTRL0 0xc0a0
40 #define PLA_RXFIFO_CTRL1 0xc0a4
41 #define PLA_RXFIFO_CTRL2 0xc0a8
42 #define PLA_FMC 0xc0b4
43 #define PLA_CFG_WOL 0xc0b6
44 #define PLA_TEREDO_CFG 0xc0bc
45 #define PLA_MAR 0xcd00
46 #define PLA_BACKUP 0xd000
47 #define PAL_BDC_CR 0xd1a0
48 #define PLA_TEREDO_TIMER 0xd2cc
49 #define PLA_REALWOW_TIMER 0xd2e8
50 #define PLA_LEDSEL 0xdd90
51 #define PLA_LED_FEATURE 0xdd92
52 #define PLA_PHYAR 0xde00
53 #define PLA_BOOT_CTRL 0xe004
54 #define PLA_GPHY_INTR_IMR 0xe022
55 #define PLA_EEE_CR 0xe040
56 #define PLA_EEEP_CR 0xe080
57 #define PLA_MAC_PWR_CTRL 0xe0c0
58 #define PLA_MAC_PWR_CTRL2 0xe0ca
59 #define PLA_MAC_PWR_CTRL3 0xe0cc
60 #define PLA_MAC_PWR_CTRL4 0xe0ce
61 #define PLA_WDT6_CTRL 0xe428
62 #define PLA_TCR0 0xe610
63 #define PLA_TCR1 0xe612
64 #define PLA_MTPS 0xe615
65 #define PLA_TXFIFO_CTRL 0xe618
66 #define PLA_RSTTALLY 0xe800
67 #define PLA_CR 0xe813
68 #define PLA_CRWECR 0xe81c
69 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
70 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
71 #define PLA_CONFIG5 0xe822
72 #define PLA_PHY_PWR 0xe84c
73 #define PLA_OOB_CTRL 0xe84f
74 #define PLA_CPCR 0xe854
75 #define PLA_MISC_0 0xe858
76 #define PLA_MISC_1 0xe85a
77 #define PLA_OCP_GPHY_BASE 0xe86c
78 #define PLA_TALLYCNT 0xe890
79 #define PLA_SFF_STS_7 0xe8de
80 #define PLA_PHYSTATUS 0xe908
81 #define PLA_BP_BA 0xfc26
82 #define PLA_BP_0 0xfc28
83 #define PLA_BP_1 0xfc2a
84 #define PLA_BP_2 0xfc2c
85 #define PLA_BP_3 0xfc2e
86 #define PLA_BP_4 0xfc30
87 #define PLA_BP_5 0xfc32
88 #define PLA_BP_6 0xfc34
89 #define PLA_BP_7 0xfc36
90 #define PLA_BP_EN 0xfc38
91
92 #define USB_U2P3_CTRL 0xb460
93 #define USB_DEV_STAT 0xb808
94 #define USB_USB_CTRL 0xd406
95 #define USB_PHY_CTRL 0xd408
96 #define USB_TX_AGG 0xd40a
97 #define USB_RX_BUF_TH 0xd40c
98 #define USB_USB_TIMER 0xd428
99 #define USB_RX_EARLY_AGG 0xd42c
100 #define USB_PM_CTRL_STATUS 0xd432
101 #define USB_TX_DMA 0xd434
102 #define USB_TOLERANCE 0xd490
103 #define USB_LPM_CTRL 0xd41a
104 #define USB_UPS_CTRL 0xd800
105 #define USB_MISC_0 0xd81a
106 #define USB_POWER_CUT 0xd80a
107 #define USB_AFE_CTRL2 0xd824
108 #define USB_WDT11_CTRL 0xe43c
109 #define USB_BP_BA 0xfc26
110 #define USB_BP_0 0xfc28
111 #define USB_BP_1 0xfc2a
112 #define USB_BP_2 0xfc2c
113 #define USB_BP_3 0xfc2e
114 #define USB_BP_4 0xfc30
115 #define USB_BP_5 0xfc32
116 #define USB_BP_6 0xfc34
117 #define USB_BP_7 0xfc36
118 #define USB_BP_EN 0xfc38
119
120 /* OCP Registers */
121 #define OCP_ALDPS_CONFIG 0x2010
122 #define OCP_EEE_CONFIG1 0x2080
123 #define OCP_EEE_CONFIG2 0x2092
124 #define OCP_EEE_CONFIG3 0x2094
125 #define OCP_BASE_MII 0xa400
126 #define OCP_EEE_AR 0xa41a
127 #define OCP_EEE_DATA 0xa41c
128 #define OCP_PHY_STATUS 0xa420
129 #define OCP_POWER_CFG 0xa430
130 #define OCP_EEE_CFG 0xa432
131 #define OCP_SRAM_ADDR 0xa436
132 #define OCP_SRAM_DATA 0xa438
133 #define OCP_DOWN_SPEED 0xa442
134 #define OCP_EEE_ABLE 0xa5c4
135 #define OCP_EEE_ADV 0xa5d0
136 #define OCP_EEE_LPABLE 0xa5d2
137 #define OCP_ADC_CFG 0xbc06
138
139 /* SRAM Register */
140 #define SRAM_LPF_CFG 0x8012
141 #define SRAM_10M_AMP1 0x8080
142 #define SRAM_10M_AMP2 0x8082
143 #define SRAM_IMPEDANCE 0x8084
144
145 /* PLA_RCR */
146 #define RCR_AAP 0x00000001
147 #define RCR_APM 0x00000002
148 #define RCR_AM 0x00000004
149 #define RCR_AB 0x00000008
150 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
151
152 /* PLA_RXFIFO_CTRL0 */
153 #define RXFIFO_THR1_NORMAL 0x00080002
154 #define RXFIFO_THR1_OOB 0x01800003
155
156 /* PLA_RXFIFO_CTRL1 */
157 #define RXFIFO_THR2_FULL 0x00000060
158 #define RXFIFO_THR2_HIGH 0x00000038
159 #define RXFIFO_THR2_OOB 0x0000004a
160 #define RXFIFO_THR2_NORMAL 0x00a0
161
162 /* PLA_RXFIFO_CTRL2 */
163 #define RXFIFO_THR3_FULL 0x00000078
164 #define RXFIFO_THR3_HIGH 0x00000048
165 #define RXFIFO_THR3_OOB 0x0000005a
166 #define RXFIFO_THR3_NORMAL 0x0110
167
168 /* PLA_TXFIFO_CTRL */
169 #define TXFIFO_THR_NORMAL 0x00400008
170 #define TXFIFO_THR_NORMAL2 0x01000008
171
172 /* PLA_FMC */
173 #define FMC_FCR_MCU_EN 0x0001
174
175 /* PLA_EEEP_CR */
176 #define EEEP_CR_EEEP_TX 0x0002
177
178 /* PLA_WDT6_CTRL */
179 #define WDT6_SET_MODE 0x0010
180
181 /* PLA_TCR0 */
182 #define TCR0_TX_EMPTY 0x0800
183 #define TCR0_AUTO_FIFO 0x0080
184
185 /* PLA_TCR1 */
186 #define VERSION_MASK 0x7cf0
187
188 /* PLA_MTPS */
189 #define MTPS_JUMBO (12 * 1024 / 64)
190 #define MTPS_DEFAULT (6 * 1024 / 64)
191
192 /* PLA_RSTTALLY */
193 #define TALLY_RESET 0x0001
194
195 /* PLA_CR */
196 #define CR_RST 0x10
197 #define CR_RE 0x08
198 #define CR_TE 0x04
199
200 /* PLA_CRWECR */
201 #define CRWECR_NORAML 0x00
202 #define CRWECR_CONFIG 0xc0
203
204 /* PLA_OOB_CTRL */
205 #define NOW_IS_OOB 0x80
206 #define TXFIFO_EMPTY 0x20
207 #define RXFIFO_EMPTY 0x10
208 #define LINK_LIST_READY 0x02
209 #define DIS_MCU_CLROOB 0x01
210 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
211
212 /* PLA_MISC_1 */
213 #define RXDY_GATED_EN 0x0008
214
215 /* PLA_SFF_STS_7 */
216 #define RE_INIT_LL 0x8000
217 #define MCU_BORW_EN 0x4000
218
219 /* PLA_CPCR */
220 #define CPCR_RX_VLAN 0x0040
221
222 /* PLA_CFG_WOL */
223 #define MAGIC_EN 0x0001
224
225 /* PLA_TEREDO_CFG */
226 #define TEREDO_SEL 0x8000
227 #define TEREDO_WAKE_MASK 0x7f00
228 #define TEREDO_RS_EVENT_MASK 0x00fe
229 #define OOB_TEREDO_EN 0x0001
230
231 /* PAL_BDC_CR */
232 #define ALDPS_PROXY_MODE 0x0001
233
234 /* PLA_CONFIG34 */
235 #define LINK_ON_WAKE_EN 0x0010
236 #define LINK_OFF_WAKE_EN 0x0008
237
238 /* PLA_CONFIG5 */
239 #define BWF_EN 0x0040
240 #define MWF_EN 0x0020
241 #define UWF_EN 0x0010
242 #define LAN_WAKE_EN 0x0002
243
244 /* PLA_LED_FEATURE */
245 #define LED_MODE_MASK 0x0700
246
247 /* PLA_PHY_PWR */
248 #define TX_10M_IDLE_EN 0x0080
249 #define PFM_PWM_SWITCH 0x0040
250
251 /* PLA_MAC_PWR_CTRL */
252 #define D3_CLK_GATED_EN 0x00004000
253 #define MCU_CLK_RATIO 0x07010f07
254 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
255 #define ALDPS_SPDWN_RATIO 0x0f87
256
257 /* PLA_MAC_PWR_CTRL2 */
258 #define EEE_SPDWN_RATIO 0x8007
259
260 /* PLA_MAC_PWR_CTRL3 */
261 #define PKT_AVAIL_SPDWN_EN 0x0100
262 #define SUSPEND_SPDWN_EN 0x0004
263 #define U1U2_SPDWN_EN 0x0002
264 #define L1_SPDWN_EN 0x0001
265
266 /* PLA_MAC_PWR_CTRL4 */
267 #define PWRSAVE_SPDWN_EN 0x1000
268 #define RXDV_SPDWN_EN 0x0800
269 #define TX10MIDLE_EN 0x0100
270 #define TP100_SPDWN_EN 0x0020
271 #define TP500_SPDWN_EN 0x0010
272 #define TP1000_SPDWN_EN 0x0008
273 #define EEE_SPDWN_EN 0x0001
274
275 /* PLA_GPHY_INTR_IMR */
276 #define GPHY_STS_MSK 0x0001
277 #define SPEED_DOWN_MSK 0x0002
278 #define SPDWN_RXDV_MSK 0x0004
279 #define SPDWN_LINKCHG_MSK 0x0008
280
281 /* PLA_PHYAR */
282 #define PHYAR_FLAG 0x80000000
283
284 /* PLA_EEE_CR */
285 #define EEE_RX_EN 0x0001
286 #define EEE_TX_EN 0x0002
287
288 /* PLA_BOOT_CTRL */
289 #define AUTOLOAD_DONE 0x0002
290
291 /* USB_DEV_STAT */
292 #define STAT_SPEED_MASK 0x0006
293 #define STAT_SPEED_HIGH 0x0000
294 #define STAT_SPEED_FULL 0x0002
295
296 /* USB_TX_AGG */
297 #define TX_AGG_MAX_THRESHOLD 0x03
298
299 /* USB_RX_BUF_TH */
300 #define RX_THR_SUPPER 0x0c350180
301 #define RX_THR_HIGH 0x7a120180
302 #define RX_THR_SLOW 0xffff0180
303
304 /* USB_TX_DMA */
305 #define TEST_MODE_DISABLE 0x00000001
306 #define TX_SIZE_ADJUST1 0x00000100
307
308 /* USB_UPS_CTRL */
309 #define POWER_CUT 0x0100
310
311 /* USB_PM_CTRL_STATUS */
312 #define RESUME_INDICATE 0x0001
313
314 /* USB_USB_CTRL */
315 #define RX_AGG_DISABLE 0x0010
316
317 /* USB_U2P3_CTRL */
318 #define U2P3_ENABLE 0x0001
319
320 /* USB_POWER_CUT */
321 #define PWR_EN 0x0001
322 #define PHASE2_EN 0x0008
323
324 /* USB_MISC_0 */
325 #define PCUT_STATUS 0x0001
326
327 /* USB_RX_EARLY_AGG */
328 #define EARLY_AGG_SUPPER 0x0e832981
329 #define EARLY_AGG_HIGH 0x0e837a12
330 #define EARLY_AGG_SLOW 0x0e83ffff
331
332 /* USB_WDT11_CTRL */
333 #define TIMER11_EN 0x0001
334
335 /* USB_LPM_CTRL */
336 #define LPM_TIMER_MASK 0x0c
337 #define LPM_TIMER_500MS 0x04 /* 500 ms */
338 #define LPM_TIMER_500US 0x0c /* 500 us */
339
340 /* USB_AFE_CTRL2 */
341 #define SEN_VAL_MASK 0xf800
342 #define SEN_VAL_NORMAL 0xa000
343 #define SEL_RXIDLE 0x0100
344
345 /* OCP_ALDPS_CONFIG */
346 #define ENPWRSAVE 0x8000
347 #define ENPDNPS 0x0200
348 #define LINKENA 0x0100
349 #define DIS_SDSAVE 0x0010
350
351 /* OCP_PHY_STATUS */
352 #define PHY_STAT_MASK 0x0007
353 #define PHY_STAT_LAN_ON 3
354 #define PHY_STAT_PWRDN 5
355
356 /* OCP_POWER_CFG */
357 #define EEE_CLKDIV_EN 0x8000
358 #define EN_ALDPS 0x0004
359 #define EN_10M_PLLOFF 0x0001
360
361 /* OCP_EEE_CONFIG1 */
362 #define RG_TXLPI_MSK_HFDUP 0x8000
363 #define RG_MATCLR_EN 0x4000
364 #define EEE_10_CAP 0x2000
365 #define EEE_NWAY_EN 0x1000
366 #define TX_QUIET_EN 0x0200
367 #define RX_QUIET_EN 0x0100
368 #define sd_rise_time_mask 0x0070
369 #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
370 #define RG_RXLPI_MSK_HFDUP 0x0008
371 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
372
373 /* OCP_EEE_CONFIG2 */
374 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
375 #define RG_DACQUIET_EN 0x0400
376 #define RG_LDVQUIET_EN 0x0200
377 #define RG_CKRSEL 0x0020
378 #define RG_EEEPRG_EN 0x0010
379
380 /* OCP_EEE_CONFIG3 */
381 #define fast_snr_mask 0xff80
382 #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
383 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
384 #define MSK_PH 0x0006 /* bit 0 ~ 3 */
385
386 /* OCP_EEE_AR */
387 /* bit[15:14] function */
388 #define FUN_ADDR 0x0000
389 #define FUN_DATA 0x4000
390 /* bit[4:0] device addr */
391
392 /* OCP_EEE_CFG */
393 #define CTAP_SHORT_EN 0x0040
394 #define EEE10_EN 0x0010
395
396 /* OCP_DOWN_SPEED */
397 #define EN_10M_BGOFF 0x0080
398
399 /* OCP_ADC_CFG */
400 #define CKADSEL_L 0x0100
401 #define ADC_EN 0x0080
402 #define EN_EMI_L 0x0040
403
404 /* SRAM_LPF_CFG */
405 #define LPF_AUTO_TUNE 0x8000
406
407 /* SRAM_10M_AMP1 */
408 #define GDAC_IB_UPALL 0x0008
409
410 /* SRAM_10M_AMP2 */
411 #define AMP_DN 0x0200
412
413 /* SRAM_IMPEDANCE */
414 #define RX_DRIVING_MASK 0x6000
415
416 enum rtl_register_content {
417 _1000bps = 0x10,
418 _100bps = 0x08,
419 _10bps = 0x04,
420 LINK_STATUS = 0x02,
421 FULL_DUP = 0x01,
422 };
423
424 #define RTL8152_MAX_TX 4
425 #define RTL8152_MAX_RX 10
426 #define INTBUFSIZE 2
427 #define CRC_SIZE 4
428 #define TX_ALIGN 4
429 #define RX_ALIGN 8
430
431 #define INTR_LINK 0x0004
432
433 #define RTL8152_REQT_READ 0xc0
434 #define RTL8152_REQT_WRITE 0x40
435 #define RTL8152_REQ_GET_REGS 0x05
436 #define RTL8152_REQ_SET_REGS 0x05
437
438 #define BYTE_EN_DWORD 0xff
439 #define BYTE_EN_WORD 0x33
440 #define BYTE_EN_BYTE 0x11
441 #define BYTE_EN_SIX_BYTES 0x3f
442 #define BYTE_EN_START_MASK 0x0f
443 #define BYTE_EN_END_MASK 0xf0
444
445 #define RTL8153_MAX_PACKET 9216 /* 9K */
446 #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN)
447 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
448 #define RTL8153_RMS RTL8153_MAX_PACKET
449 #define RTL8152_TX_TIMEOUT (5 * HZ)
450
451 /* rtl8152 flags */
452 enum rtl8152_flags {
453 RTL8152_UNPLUG = 0,
454 RTL8152_SET_RX_MODE,
455 WORK_ENABLE,
456 RTL8152_LINK_CHG,
457 SELECTIVE_SUSPEND,
458 PHY_RESET,
459 SCHEDULE_TASKLET,
460 };
461
462 /* Define these values to match your device */
463 #define VENDOR_ID_REALTEK 0x0bda
464 #define PRODUCT_ID_RTL8152 0x8152
465 #define PRODUCT_ID_RTL8153 0x8153
466
467 #define VENDOR_ID_SAMSUNG 0x04e8
468 #define PRODUCT_ID_SAMSUNG 0xa101
469
470 #define MCU_TYPE_PLA 0x0100
471 #define MCU_TYPE_USB 0x0000
472
473 #define REALTEK_USB_DEVICE(vend, prod) \
474 USB_DEVICE_INTERFACE_CLASS(vend, prod, USB_CLASS_VENDOR_SPEC)
475
476 struct tally_counter {
477 __le64 tx_packets;
478 __le64 rx_packets;
479 __le64 tx_errors;
480 __le32 rx_errors;
481 __le16 rx_missed;
482 __le16 align_errors;
483 __le32 tx_one_collision;
484 __le32 tx_multi_collision;
485 __le64 rx_unicast;
486 __le64 rx_broadcast;
487 __le32 rx_multicast;
488 __le16 tx_aborted;
489 __le16 tx_underun;
490 };
491
492 struct rx_desc {
493 __le32 opts1;
494 #define RX_LEN_MASK 0x7fff
495
496 __le32 opts2;
497 #define RD_UDP_CS (1 << 23)
498 #define RD_TCP_CS (1 << 22)
499 #define RD_IPV6_CS (1 << 20)
500 #define RD_IPV4_CS (1 << 19)
501
502 __le32 opts3;
503 #define IPF (1 << 23) /* IP checksum fail */
504 #define UDPF (1 << 22) /* UDP checksum fail */
505 #define TCPF (1 << 21) /* TCP checksum fail */
506 #define RX_VLAN_TAG (1 << 16)
507
508 __le32 opts4;
509 __le32 opts5;
510 __le32 opts6;
511 };
512
513 struct tx_desc {
514 __le32 opts1;
515 #define TX_FS (1 << 31) /* First segment of a packet */
516 #define TX_LS (1 << 30) /* Final segment of a packet */
517 #define GTSENDV4 (1 << 28)
518 #define GTSENDV6 (1 << 27)
519 #define GTTCPHO_SHIFT 18
520 #define GTTCPHO_MAX 0x7fU
521 #define TX_LEN_MAX 0x3ffffU
522
523 __le32 opts2;
524 #define UDP_CS (1 << 31) /* Calculate UDP/IP checksum */
525 #define TCP_CS (1 << 30) /* Calculate TCP/IP checksum */
526 #define IPV4_CS (1 << 29) /* Calculate IPv4 checksum */
527 #define IPV6_CS (1 << 28) /* Calculate IPv6 checksum */
528 #define MSS_SHIFT 17
529 #define MSS_MAX 0x7ffU
530 #define TCPHO_SHIFT 17
531 #define TCPHO_MAX 0x7ffU
532 #define TX_VLAN_TAG (1 << 16)
533 };
534
535 struct r8152;
536
537 struct rx_agg {
538 struct list_head list;
539 struct urb *urb;
540 struct r8152 *context;
541 void *buffer;
542 void *head;
543 };
544
545 struct tx_agg {
546 struct list_head list;
547 struct urb *urb;
548 struct r8152 *context;
549 void *buffer;
550 void *head;
551 u32 skb_num;
552 u32 skb_len;
553 };
554
555 struct r8152 {
556 unsigned long flags;
557 struct usb_device *udev;
558 struct tasklet_struct tl;
559 struct usb_interface *intf;
560 struct net_device *netdev;
561 struct urb *intr_urb;
562 struct tx_agg tx_info[RTL8152_MAX_TX];
563 struct rx_agg rx_info[RTL8152_MAX_RX];
564 struct list_head rx_done, tx_free;
565 struct sk_buff_head tx_queue;
566 spinlock_t rx_lock, tx_lock;
567 struct delayed_work schedule;
568 struct mii_if_info mii;
569 struct mutex control; /* use for hw setting */
570
571 struct rtl_ops {
572 void (*init)(struct r8152 *);
573 int (*enable)(struct r8152 *);
574 void (*disable)(struct r8152 *);
575 void (*up)(struct r8152 *);
576 void (*down)(struct r8152 *);
577 void (*unload)(struct r8152 *);
578 int (*eee_get)(struct r8152 *, struct ethtool_eee *);
579 int (*eee_set)(struct r8152 *, struct ethtool_eee *);
580 } rtl_ops;
581
582 int intr_interval;
583 u32 saved_wolopts;
584 u32 msg_enable;
585 u32 tx_qlen;
586 u16 ocp_base;
587 u8 *intr_buff;
588 u8 version;
589 u8 speed;
590 };
591
592 enum rtl_version {
593 RTL_VER_UNKNOWN = 0,
594 RTL_VER_01,
595 RTL_VER_02,
596 RTL_VER_03,
597 RTL_VER_04,
598 RTL_VER_05,
599 RTL_VER_MAX
600 };
601
602 enum tx_csum_stat {
603 TX_CSUM_SUCCESS = 0,
604 TX_CSUM_TSO,
605 TX_CSUM_NONE
606 };
607
608 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
609 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
610 */
611 static const int multicast_filter_limit = 32;
612 static unsigned int agg_buf_sz = 16384;
613
614 #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \
615 VLAN_ETH_HLEN - VLAN_HLEN)
616
617 static
618 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
619 {
620 int ret;
621 void *tmp;
622
623 tmp = kmalloc(size, GFP_KERNEL);
624 if (!tmp)
625 return -ENOMEM;
626
627 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
628 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
629 value, index, tmp, size, 500);
630
631 memcpy(data, tmp, size);
632 kfree(tmp);
633
634 return ret;
635 }
636
637 static
638 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
639 {
640 int ret;
641 void *tmp;
642
643 tmp = kmemdup(data, size, GFP_KERNEL);
644 if (!tmp)
645 return -ENOMEM;
646
647 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
648 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
649 value, index, tmp, size, 500);
650
651 kfree(tmp);
652
653 return ret;
654 }
655
656 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
657 void *data, u16 type)
658 {
659 u16 limit = 64;
660 int ret = 0;
661
662 if (test_bit(RTL8152_UNPLUG, &tp->flags))
663 return -ENODEV;
664
665 /* both size and indix must be 4 bytes align */
666 if ((size & 3) || !size || (index & 3) || !data)
667 return -EPERM;
668
669 if ((u32)index + (u32)size > 0xffff)
670 return -EPERM;
671
672 while (size) {
673 if (size > limit) {
674 ret = get_registers(tp, index, type, limit, data);
675 if (ret < 0)
676 break;
677
678 index += limit;
679 data += limit;
680 size -= limit;
681 } else {
682 ret = get_registers(tp, index, type, size, data);
683 if (ret < 0)
684 break;
685
686 index += size;
687 data += size;
688 size = 0;
689 break;
690 }
691 }
692
693 return ret;
694 }
695
696 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
697 u16 size, void *data, u16 type)
698 {
699 int ret;
700 u16 byteen_start, byteen_end, byen;
701 u16 limit = 512;
702
703 if (test_bit(RTL8152_UNPLUG, &tp->flags))
704 return -ENODEV;
705
706 /* both size and indix must be 4 bytes align */
707 if ((size & 3) || !size || (index & 3) || !data)
708 return -EPERM;
709
710 if ((u32)index + (u32)size > 0xffff)
711 return -EPERM;
712
713 byteen_start = byteen & BYTE_EN_START_MASK;
714 byteen_end = byteen & BYTE_EN_END_MASK;
715
716 byen = byteen_start | (byteen_start << 4);
717 ret = set_registers(tp, index, type | byen, 4, data);
718 if (ret < 0)
719 goto error1;
720
721 index += 4;
722 data += 4;
723 size -= 4;
724
725 if (size) {
726 size -= 4;
727
728 while (size) {
729 if (size > limit) {
730 ret = set_registers(tp, index,
731 type | BYTE_EN_DWORD,
732 limit, data);
733 if (ret < 0)
734 goto error1;
735
736 index += limit;
737 data += limit;
738 size -= limit;
739 } else {
740 ret = set_registers(tp, index,
741 type | BYTE_EN_DWORD,
742 size, data);
743 if (ret < 0)
744 goto error1;
745
746 index += size;
747 data += size;
748 size = 0;
749 break;
750 }
751 }
752
753 byen = byteen_end | (byteen_end >> 4);
754 ret = set_registers(tp, index, type | byen, 4, data);
755 if (ret < 0)
756 goto error1;
757 }
758
759 error1:
760 return ret;
761 }
762
763 static inline
764 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
765 {
766 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
767 }
768
769 static inline
770 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
771 {
772 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
773 }
774
775 static inline
776 int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
777 {
778 return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
779 }
780
781 static inline
782 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
783 {
784 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
785 }
786
787 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
788 {
789 __le32 data;
790
791 generic_ocp_read(tp, index, sizeof(data), &data, type);
792
793 return __le32_to_cpu(data);
794 }
795
796 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
797 {
798 __le32 tmp = __cpu_to_le32(data);
799
800 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
801 }
802
803 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
804 {
805 u32 data;
806 __le32 tmp;
807 u8 shift = index & 2;
808
809 index &= ~3;
810
811 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
812
813 data = __le32_to_cpu(tmp);
814 data >>= (shift * 8);
815 data &= 0xffff;
816
817 return (u16)data;
818 }
819
820 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
821 {
822 u32 mask = 0xffff;
823 __le32 tmp;
824 u16 byen = BYTE_EN_WORD;
825 u8 shift = index & 2;
826
827 data &= mask;
828
829 if (index & 2) {
830 byen <<= shift;
831 mask <<= (shift * 8);
832 data <<= (shift * 8);
833 index &= ~3;
834 }
835
836 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
837
838 data |= __le32_to_cpu(tmp) & ~mask;
839 tmp = __cpu_to_le32(data);
840
841 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
842 }
843
844 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
845 {
846 u32 data;
847 __le32 tmp;
848 u8 shift = index & 3;
849
850 index &= ~3;
851
852 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
853
854 data = __le32_to_cpu(tmp);
855 data >>= (shift * 8);
856 data &= 0xff;
857
858 return (u8)data;
859 }
860
861 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
862 {
863 u32 mask = 0xff;
864 __le32 tmp;
865 u16 byen = BYTE_EN_BYTE;
866 u8 shift = index & 3;
867
868 data &= mask;
869
870 if (index & 3) {
871 byen <<= shift;
872 mask <<= (shift * 8);
873 data <<= (shift * 8);
874 index &= ~3;
875 }
876
877 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
878
879 data |= __le32_to_cpu(tmp) & ~mask;
880 tmp = __cpu_to_le32(data);
881
882 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
883 }
884
885 static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
886 {
887 u16 ocp_base, ocp_index;
888
889 ocp_base = addr & 0xf000;
890 if (ocp_base != tp->ocp_base) {
891 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
892 tp->ocp_base = ocp_base;
893 }
894
895 ocp_index = (addr & 0x0fff) | 0xb000;
896 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
897 }
898
899 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
900 {
901 u16 ocp_base, ocp_index;
902
903 ocp_base = addr & 0xf000;
904 if (ocp_base != tp->ocp_base) {
905 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
906 tp->ocp_base = ocp_base;
907 }
908
909 ocp_index = (addr & 0x0fff) | 0xb000;
910 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
911 }
912
913 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
914 {
915 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
916 }
917
918 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
919 {
920 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
921 }
922
923 static void sram_write(struct r8152 *tp, u16 addr, u16 data)
924 {
925 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
926 ocp_reg_write(tp, OCP_SRAM_DATA, data);
927 }
928
929 static u16 sram_read(struct r8152 *tp, u16 addr)
930 {
931 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
932 return ocp_reg_read(tp, OCP_SRAM_DATA);
933 }
934
935 static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
936 {
937 struct r8152 *tp = netdev_priv(netdev);
938 int ret;
939
940 if (test_bit(RTL8152_UNPLUG, &tp->flags))
941 return -ENODEV;
942
943 if (phy_id != R8152_PHY_ID)
944 return -EINVAL;
945
946 ret = r8152_mdio_read(tp, reg);
947
948 return ret;
949 }
950
951 static
952 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
953 {
954 struct r8152 *tp = netdev_priv(netdev);
955
956 if (test_bit(RTL8152_UNPLUG, &tp->flags))
957 return;
958
959 if (phy_id != R8152_PHY_ID)
960 return;
961
962 r8152_mdio_write(tp, reg, val);
963 }
964
965 static int
966 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
967
968 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
969 {
970 struct r8152 *tp = netdev_priv(netdev);
971 struct sockaddr *addr = p;
972 int ret = -EADDRNOTAVAIL;
973
974 if (!is_valid_ether_addr(addr->sa_data))
975 goto out1;
976
977 ret = usb_autopm_get_interface(tp->intf);
978 if (ret < 0)
979 goto out1;
980
981 mutex_lock(&tp->control);
982
983 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
984
985 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
986 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
987 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
988
989 mutex_unlock(&tp->control);
990
991 usb_autopm_put_interface(tp->intf);
992 out1:
993 return ret;
994 }
995
996 static int set_ethernet_addr(struct r8152 *tp)
997 {
998 struct net_device *dev = tp->netdev;
999 struct sockaddr sa;
1000 int ret;
1001
1002 if (tp->version == RTL_VER_01)
1003 ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data);
1004 else
1005 ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data);
1006
1007 if (ret < 0) {
1008 netif_err(tp, probe, dev, "Get ether addr fail\n");
1009 } else if (!is_valid_ether_addr(sa.sa_data)) {
1010 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1011 sa.sa_data);
1012 eth_hw_addr_random(dev);
1013 ether_addr_copy(sa.sa_data, dev->dev_addr);
1014 ret = rtl8152_set_mac_address(dev, &sa);
1015 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1016 sa.sa_data);
1017 } else {
1018 if (tp->version == RTL_VER_01)
1019 ether_addr_copy(dev->dev_addr, sa.sa_data);
1020 else
1021 ret = rtl8152_set_mac_address(dev, &sa);
1022 }
1023
1024 return ret;
1025 }
1026
1027 static void read_bulk_callback(struct urb *urb)
1028 {
1029 struct net_device *netdev;
1030 int status = urb->status;
1031 struct rx_agg *agg;
1032 struct r8152 *tp;
1033 int result;
1034
1035 agg = urb->context;
1036 if (!agg)
1037 return;
1038
1039 tp = agg->context;
1040 if (!tp)
1041 return;
1042
1043 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1044 return;
1045
1046 if (!test_bit(WORK_ENABLE, &tp->flags))
1047 return;
1048
1049 netdev = tp->netdev;
1050
1051 /* When link down, the driver would cancel all bulks. */
1052 /* This avoid the re-submitting bulk */
1053 if (!netif_carrier_ok(netdev))
1054 return;
1055
1056 usb_mark_last_busy(tp->udev);
1057
1058 switch (status) {
1059 case 0:
1060 if (urb->actual_length < ETH_ZLEN)
1061 break;
1062
1063 spin_lock(&tp->rx_lock);
1064 list_add_tail(&agg->list, &tp->rx_done);
1065 spin_unlock(&tp->rx_lock);
1066 tasklet_schedule(&tp->tl);
1067 return;
1068 case -ESHUTDOWN:
1069 set_bit(RTL8152_UNPLUG, &tp->flags);
1070 netif_device_detach(tp->netdev);
1071 return;
1072 case -ENOENT:
1073 return; /* the urb is in unlink state */
1074 case -ETIME:
1075 if (net_ratelimit())
1076 netdev_warn(netdev, "maybe reset is needed?\n");
1077 break;
1078 default:
1079 if (net_ratelimit())
1080 netdev_warn(netdev, "Rx status %d\n", status);
1081 break;
1082 }
1083
1084 result = r8152_submit_rx(tp, agg, GFP_ATOMIC);
1085 if (result == -ENODEV) {
1086 netif_device_detach(tp->netdev);
1087 } else if (result) {
1088 spin_lock(&tp->rx_lock);
1089 list_add_tail(&agg->list, &tp->rx_done);
1090 spin_unlock(&tp->rx_lock);
1091 tasklet_schedule(&tp->tl);
1092 }
1093 }
1094
1095 static void write_bulk_callback(struct urb *urb)
1096 {
1097 struct net_device_stats *stats;
1098 struct net_device *netdev;
1099 struct tx_agg *agg;
1100 struct r8152 *tp;
1101 int status = urb->status;
1102
1103 agg = urb->context;
1104 if (!agg)
1105 return;
1106
1107 tp = agg->context;
1108 if (!tp)
1109 return;
1110
1111 netdev = tp->netdev;
1112 stats = &netdev->stats;
1113 if (status) {
1114 if (net_ratelimit())
1115 netdev_warn(netdev, "Tx status %d\n", status);
1116 stats->tx_errors += agg->skb_num;
1117 } else {
1118 stats->tx_packets += agg->skb_num;
1119 stats->tx_bytes += agg->skb_len;
1120 }
1121
1122 spin_lock(&tp->tx_lock);
1123 list_add_tail(&agg->list, &tp->tx_free);
1124 spin_unlock(&tp->tx_lock);
1125
1126 usb_autopm_put_interface_async(tp->intf);
1127
1128 if (!netif_carrier_ok(netdev))
1129 return;
1130
1131 if (!test_bit(WORK_ENABLE, &tp->flags))
1132 return;
1133
1134 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1135 return;
1136
1137 if (!skb_queue_empty(&tp->tx_queue))
1138 tasklet_schedule(&tp->tl);
1139 }
1140
1141 static void intr_callback(struct urb *urb)
1142 {
1143 struct r8152 *tp;
1144 __le16 *d;
1145 int status = urb->status;
1146 int res;
1147
1148 tp = urb->context;
1149 if (!tp)
1150 return;
1151
1152 if (!test_bit(WORK_ENABLE, &tp->flags))
1153 return;
1154
1155 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1156 return;
1157
1158 switch (status) {
1159 case 0: /* success */
1160 break;
1161 case -ECONNRESET: /* unlink */
1162 case -ESHUTDOWN:
1163 netif_device_detach(tp->netdev);
1164 case -ENOENT:
1165 case -EPROTO:
1166 netif_info(tp, intr, tp->netdev,
1167 "Stop submitting intr, status %d\n", status);
1168 return;
1169 case -EOVERFLOW:
1170 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1171 goto resubmit;
1172 /* -EPIPE: should clear the halt */
1173 default:
1174 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1175 goto resubmit;
1176 }
1177
1178 d = urb->transfer_buffer;
1179 if (INTR_LINK & __le16_to_cpu(d[0])) {
1180 if (!(tp->speed & LINK_STATUS)) {
1181 set_bit(RTL8152_LINK_CHG, &tp->flags);
1182 schedule_delayed_work(&tp->schedule, 0);
1183 }
1184 } else {
1185 if (tp->speed & LINK_STATUS) {
1186 set_bit(RTL8152_LINK_CHG, &tp->flags);
1187 schedule_delayed_work(&tp->schedule, 0);
1188 }
1189 }
1190
1191 resubmit:
1192 res = usb_submit_urb(urb, GFP_ATOMIC);
1193 if (res == -ENODEV)
1194 netif_device_detach(tp->netdev);
1195 else if (res)
1196 netif_err(tp, intr, tp->netdev,
1197 "can't resubmit intr, status %d\n", res);
1198 }
1199
1200 static inline void *rx_agg_align(void *data)
1201 {
1202 return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1203 }
1204
1205 static inline void *tx_agg_align(void *data)
1206 {
1207 return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1208 }
1209
1210 static void free_all_mem(struct r8152 *tp)
1211 {
1212 int i;
1213
1214 for (i = 0; i < RTL8152_MAX_RX; i++) {
1215 usb_free_urb(tp->rx_info[i].urb);
1216 tp->rx_info[i].urb = NULL;
1217
1218 kfree(tp->rx_info[i].buffer);
1219 tp->rx_info[i].buffer = NULL;
1220 tp->rx_info[i].head = NULL;
1221 }
1222
1223 for (i = 0; i < RTL8152_MAX_TX; i++) {
1224 usb_free_urb(tp->tx_info[i].urb);
1225 tp->tx_info[i].urb = NULL;
1226
1227 kfree(tp->tx_info[i].buffer);
1228 tp->tx_info[i].buffer = NULL;
1229 tp->tx_info[i].head = NULL;
1230 }
1231
1232 usb_free_urb(tp->intr_urb);
1233 tp->intr_urb = NULL;
1234
1235 kfree(tp->intr_buff);
1236 tp->intr_buff = NULL;
1237 }
1238
1239 static int alloc_all_mem(struct r8152 *tp)
1240 {
1241 struct net_device *netdev = tp->netdev;
1242 struct usb_interface *intf = tp->intf;
1243 struct usb_host_interface *alt = intf->cur_altsetting;
1244 struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
1245 struct urb *urb;
1246 int node, i;
1247 u8 *buf;
1248
1249 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1250
1251 spin_lock_init(&tp->rx_lock);
1252 spin_lock_init(&tp->tx_lock);
1253 INIT_LIST_HEAD(&tp->rx_done);
1254 INIT_LIST_HEAD(&tp->tx_free);
1255 skb_queue_head_init(&tp->tx_queue);
1256
1257 for (i = 0; i < RTL8152_MAX_RX; i++) {
1258 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1259 if (!buf)
1260 goto err1;
1261
1262 if (buf != rx_agg_align(buf)) {
1263 kfree(buf);
1264 buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL,
1265 node);
1266 if (!buf)
1267 goto err1;
1268 }
1269
1270 urb = usb_alloc_urb(0, GFP_KERNEL);
1271 if (!urb) {
1272 kfree(buf);
1273 goto err1;
1274 }
1275
1276 INIT_LIST_HEAD(&tp->rx_info[i].list);
1277 tp->rx_info[i].context = tp;
1278 tp->rx_info[i].urb = urb;
1279 tp->rx_info[i].buffer = buf;
1280 tp->rx_info[i].head = rx_agg_align(buf);
1281 }
1282
1283 for (i = 0; i < RTL8152_MAX_TX; i++) {
1284 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1285 if (!buf)
1286 goto err1;
1287
1288 if (buf != tx_agg_align(buf)) {
1289 kfree(buf);
1290 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
1291 node);
1292 if (!buf)
1293 goto err1;
1294 }
1295
1296 urb = usb_alloc_urb(0, GFP_KERNEL);
1297 if (!urb) {
1298 kfree(buf);
1299 goto err1;
1300 }
1301
1302 INIT_LIST_HEAD(&tp->tx_info[i].list);
1303 tp->tx_info[i].context = tp;
1304 tp->tx_info[i].urb = urb;
1305 tp->tx_info[i].buffer = buf;
1306 tp->tx_info[i].head = tx_agg_align(buf);
1307
1308 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1309 }
1310
1311 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1312 if (!tp->intr_urb)
1313 goto err1;
1314
1315 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1316 if (!tp->intr_buff)
1317 goto err1;
1318
1319 tp->intr_interval = (int)ep_intr->desc.bInterval;
1320 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
1321 tp->intr_buff, INTBUFSIZE, intr_callback,
1322 tp, tp->intr_interval);
1323
1324 return 0;
1325
1326 err1:
1327 free_all_mem(tp);
1328 return -ENOMEM;
1329 }
1330
1331 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1332 {
1333 struct tx_agg *agg = NULL;
1334 unsigned long flags;
1335
1336 if (list_empty(&tp->tx_free))
1337 return NULL;
1338
1339 spin_lock_irqsave(&tp->tx_lock, flags);
1340 if (!list_empty(&tp->tx_free)) {
1341 struct list_head *cursor;
1342
1343 cursor = tp->tx_free.next;
1344 list_del_init(cursor);
1345 agg = list_entry(cursor, struct tx_agg, list);
1346 }
1347 spin_unlock_irqrestore(&tp->tx_lock, flags);
1348
1349 return agg;
1350 }
1351
1352 static inline __be16 get_protocol(struct sk_buff *skb)
1353 {
1354 __be16 protocol;
1355
1356 if (skb->protocol == htons(ETH_P_8021Q))
1357 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
1358 else
1359 protocol = skb->protocol;
1360
1361 return protocol;
1362 }
1363
1364 /* r8152_csum_workaround()
1365 * The hw limites the value the transport offset. When the offset is out of the
1366 * range, calculate the checksum by sw.
1367 */
1368 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1369 struct sk_buff_head *list)
1370 {
1371 if (skb_shinfo(skb)->gso_size) {
1372 netdev_features_t features = tp->netdev->features;
1373 struct sk_buff_head seg_list;
1374 struct sk_buff *segs, *nskb;
1375
1376 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
1377 segs = skb_gso_segment(skb, features);
1378 if (IS_ERR(segs) || !segs)
1379 goto drop;
1380
1381 __skb_queue_head_init(&seg_list);
1382
1383 do {
1384 nskb = segs;
1385 segs = segs->next;
1386 nskb->next = NULL;
1387 __skb_queue_tail(&seg_list, nskb);
1388 } while (segs);
1389
1390 skb_queue_splice(&seg_list, list);
1391 dev_kfree_skb(skb);
1392 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1393 if (skb_checksum_help(skb) < 0)
1394 goto drop;
1395
1396 __skb_queue_head(list, skb);
1397 } else {
1398 struct net_device_stats *stats;
1399
1400 drop:
1401 stats = &tp->netdev->stats;
1402 stats->tx_dropped++;
1403 dev_kfree_skb(skb);
1404 }
1405 }
1406
1407 /* msdn_giant_send_check()
1408 * According to the document of microsoft, the TCP Pseudo Header excludes the
1409 * packet length for IPv6 TCP large packets.
1410 */
1411 static int msdn_giant_send_check(struct sk_buff *skb)
1412 {
1413 const struct ipv6hdr *ipv6h;
1414 struct tcphdr *th;
1415 int ret;
1416
1417 ret = skb_cow_head(skb, 0);
1418 if (ret)
1419 return ret;
1420
1421 ipv6h = ipv6_hdr(skb);
1422 th = tcp_hdr(skb);
1423
1424 th->check = 0;
1425 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
1426
1427 return ret;
1428 }
1429
1430 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
1431 {
1432 if (vlan_tx_tag_present(skb)) {
1433 u32 opts2;
1434
1435 opts2 = TX_VLAN_TAG | swab16(vlan_tx_tag_get(skb));
1436 desc->opts2 |= cpu_to_le32(opts2);
1437 }
1438 }
1439
1440 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
1441 {
1442 u32 opts2 = le32_to_cpu(desc->opts2);
1443
1444 if (opts2 & RX_VLAN_TAG)
1445 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1446 swab16(opts2 & 0xffff));
1447 }
1448
1449 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1450 struct sk_buff *skb, u32 len, u32 transport_offset)
1451 {
1452 u32 mss = skb_shinfo(skb)->gso_size;
1453 u32 opts1, opts2 = 0;
1454 int ret = TX_CSUM_SUCCESS;
1455
1456 WARN_ON_ONCE(len > TX_LEN_MAX);
1457
1458 opts1 = len | TX_FS | TX_LS;
1459
1460 if (mss) {
1461 if (transport_offset > GTTCPHO_MAX) {
1462 netif_warn(tp, tx_err, tp->netdev,
1463 "Invalid transport offset 0x%x for TSO\n",
1464 transport_offset);
1465 ret = TX_CSUM_TSO;
1466 goto unavailable;
1467 }
1468
1469 switch (get_protocol(skb)) {
1470 case htons(ETH_P_IP):
1471 opts1 |= GTSENDV4;
1472 break;
1473
1474 case htons(ETH_P_IPV6):
1475 if (msdn_giant_send_check(skb)) {
1476 ret = TX_CSUM_TSO;
1477 goto unavailable;
1478 }
1479 opts1 |= GTSENDV6;
1480 break;
1481
1482 default:
1483 WARN_ON_ONCE(1);
1484 break;
1485 }
1486
1487 opts1 |= transport_offset << GTTCPHO_SHIFT;
1488 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
1489 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1490 u8 ip_protocol;
1491
1492 if (transport_offset > TCPHO_MAX) {
1493 netif_warn(tp, tx_err, tp->netdev,
1494 "Invalid transport offset 0x%x\n",
1495 transport_offset);
1496 ret = TX_CSUM_NONE;
1497 goto unavailable;
1498 }
1499
1500 switch (get_protocol(skb)) {
1501 case htons(ETH_P_IP):
1502 opts2 |= IPV4_CS;
1503 ip_protocol = ip_hdr(skb)->protocol;
1504 break;
1505
1506 case htons(ETH_P_IPV6):
1507 opts2 |= IPV6_CS;
1508 ip_protocol = ipv6_hdr(skb)->nexthdr;
1509 break;
1510
1511 default:
1512 ip_protocol = IPPROTO_RAW;
1513 break;
1514 }
1515
1516 if (ip_protocol == IPPROTO_TCP)
1517 opts2 |= TCP_CS;
1518 else if (ip_protocol == IPPROTO_UDP)
1519 opts2 |= UDP_CS;
1520 else
1521 WARN_ON_ONCE(1);
1522
1523 opts2 |= transport_offset << TCPHO_SHIFT;
1524 }
1525
1526 desc->opts2 = cpu_to_le32(opts2);
1527 desc->opts1 = cpu_to_le32(opts1);
1528
1529 unavailable:
1530 return ret;
1531 }
1532
1533 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
1534 {
1535 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1536 int remain, ret;
1537 u8 *tx_data;
1538
1539 __skb_queue_head_init(&skb_head);
1540 spin_lock(&tx_queue->lock);
1541 skb_queue_splice_init(tx_queue, &skb_head);
1542 spin_unlock(&tx_queue->lock);
1543
1544 tx_data = agg->head;
1545 agg->skb_num = 0;
1546 agg->skb_len = 0;
1547 remain = agg_buf_sz;
1548
1549 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
1550 struct tx_desc *tx_desc;
1551 struct sk_buff *skb;
1552 unsigned int len;
1553 u32 offset;
1554
1555 skb = __skb_dequeue(&skb_head);
1556 if (!skb)
1557 break;
1558
1559 len = skb->len + sizeof(*tx_desc);
1560
1561 if (len > remain) {
1562 __skb_queue_head(&skb_head, skb);
1563 break;
1564 }
1565
1566 tx_data = tx_agg_align(tx_data);
1567 tx_desc = (struct tx_desc *)tx_data;
1568
1569 offset = (u32)skb_transport_offset(skb);
1570
1571 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
1572 r8152_csum_workaround(tp, skb, &skb_head);
1573 continue;
1574 }
1575
1576 rtl_tx_vlan_tag(tx_desc, skb);
1577
1578 tx_data += sizeof(*tx_desc);
1579
1580 len = skb->len;
1581 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
1582 struct net_device_stats *stats = &tp->netdev->stats;
1583
1584 stats->tx_dropped++;
1585 dev_kfree_skb_any(skb);
1586 tx_data -= sizeof(*tx_desc);
1587 continue;
1588 }
1589
1590 tx_data += len;
1591 agg->skb_len += len;
1592 agg->skb_num++;
1593
1594 dev_kfree_skb_any(skb);
1595
1596 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
1597 }
1598
1599 if (!skb_queue_empty(&skb_head)) {
1600 spin_lock(&tx_queue->lock);
1601 skb_queue_splice(&skb_head, tx_queue);
1602 spin_unlock(&tx_queue->lock);
1603 }
1604
1605 netif_tx_lock(tp->netdev);
1606
1607 if (netif_queue_stopped(tp->netdev) &&
1608 skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
1609 netif_wake_queue(tp->netdev);
1610
1611 netif_tx_unlock(tp->netdev);
1612
1613 ret = usb_autopm_get_interface_async(tp->intf);
1614 if (ret < 0)
1615 goto out_tx_fill;
1616
1617 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1618 agg->head, (int)(tx_data - (u8 *)agg->head),
1619 (usb_complete_t)write_bulk_callback, agg);
1620
1621 ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
1622 if (ret < 0)
1623 usb_autopm_put_interface_async(tp->intf);
1624
1625 out_tx_fill:
1626 return ret;
1627 }
1628
1629 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
1630 {
1631 u8 checksum = CHECKSUM_NONE;
1632 u32 opts2, opts3;
1633
1634 if (tp->version == RTL_VER_01)
1635 goto return_result;
1636
1637 opts2 = le32_to_cpu(rx_desc->opts2);
1638 opts3 = le32_to_cpu(rx_desc->opts3);
1639
1640 if (opts2 & RD_IPV4_CS) {
1641 if (opts3 & IPF)
1642 checksum = CHECKSUM_NONE;
1643 else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF))
1644 checksum = CHECKSUM_NONE;
1645 else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF))
1646 checksum = CHECKSUM_NONE;
1647 else
1648 checksum = CHECKSUM_UNNECESSARY;
1649 } else if (RD_IPV6_CS) {
1650 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
1651 checksum = CHECKSUM_UNNECESSARY;
1652 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
1653 checksum = CHECKSUM_UNNECESSARY;
1654 }
1655
1656 return_result:
1657 return checksum;
1658 }
1659
1660 static void rx_bottom(struct r8152 *tp)
1661 {
1662 unsigned long flags;
1663 struct list_head *cursor, *next, rx_queue;
1664
1665 if (list_empty(&tp->rx_done))
1666 return;
1667
1668 INIT_LIST_HEAD(&rx_queue);
1669 spin_lock_irqsave(&tp->rx_lock, flags);
1670 list_splice_init(&tp->rx_done, &rx_queue);
1671 spin_unlock_irqrestore(&tp->rx_lock, flags);
1672
1673 list_for_each_safe(cursor, next, &rx_queue) {
1674 struct rx_desc *rx_desc;
1675 struct rx_agg *agg;
1676 int len_used = 0;
1677 struct urb *urb;
1678 u8 *rx_data;
1679 int ret;
1680
1681 list_del_init(cursor);
1682
1683 agg = list_entry(cursor, struct rx_agg, list);
1684 urb = agg->urb;
1685 if (urb->actual_length < ETH_ZLEN)
1686 goto submit;
1687
1688 rx_desc = agg->head;
1689 rx_data = agg->head;
1690 len_used += sizeof(struct rx_desc);
1691
1692 while (urb->actual_length > len_used) {
1693 struct net_device *netdev = tp->netdev;
1694 struct net_device_stats *stats = &netdev->stats;
1695 unsigned int pkt_len;
1696 struct sk_buff *skb;
1697
1698 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1699 if (pkt_len < ETH_ZLEN)
1700 break;
1701
1702 len_used += pkt_len;
1703 if (urb->actual_length < len_used)
1704 break;
1705
1706 pkt_len -= CRC_SIZE;
1707 rx_data += sizeof(struct rx_desc);
1708
1709 skb = netdev_alloc_skb_ip_align(netdev, pkt_len);
1710 if (!skb) {
1711 stats->rx_dropped++;
1712 goto find_next_rx;
1713 }
1714
1715 skb->ip_summed = r8152_rx_csum(tp, rx_desc);
1716 memcpy(skb->data, rx_data, pkt_len);
1717 skb_put(skb, pkt_len);
1718 skb->protocol = eth_type_trans(skb, netdev);
1719 rtl_rx_vlan_tag(rx_desc, skb);
1720 netif_receive_skb(skb);
1721 stats->rx_packets++;
1722 stats->rx_bytes += pkt_len;
1723
1724 find_next_rx:
1725 rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE);
1726 rx_desc = (struct rx_desc *)rx_data;
1727 len_used = (int)(rx_data - (u8 *)agg->head);
1728 len_used += sizeof(struct rx_desc);
1729 }
1730
1731 submit:
1732 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
1733 if (ret && ret != -ENODEV) {
1734 spin_lock_irqsave(&tp->rx_lock, flags);
1735 list_add_tail(&agg->list, &tp->rx_done);
1736 spin_unlock_irqrestore(&tp->rx_lock, flags);
1737 tasklet_schedule(&tp->tl);
1738 }
1739 }
1740 }
1741
1742 static void tx_bottom(struct r8152 *tp)
1743 {
1744 int res;
1745
1746 do {
1747 struct tx_agg *agg;
1748
1749 if (skb_queue_empty(&tp->tx_queue))
1750 break;
1751
1752 agg = r8152_get_tx_agg(tp);
1753 if (!agg)
1754 break;
1755
1756 res = r8152_tx_agg_fill(tp, agg);
1757 if (res) {
1758 struct net_device *netdev = tp->netdev;
1759
1760 if (res == -ENODEV) {
1761 netif_device_detach(netdev);
1762 } else {
1763 struct net_device_stats *stats = &netdev->stats;
1764 unsigned long flags;
1765
1766 netif_warn(tp, tx_err, netdev,
1767 "failed tx_urb %d\n", res);
1768 stats->tx_dropped += agg->skb_num;
1769
1770 spin_lock_irqsave(&tp->tx_lock, flags);
1771 list_add_tail(&agg->list, &tp->tx_free);
1772 spin_unlock_irqrestore(&tp->tx_lock, flags);
1773 }
1774 }
1775 } while (res == 0);
1776 }
1777
1778 static void bottom_half(unsigned long data)
1779 {
1780 struct r8152 *tp;
1781
1782 tp = (struct r8152 *)data;
1783
1784 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1785 return;
1786
1787 if (!test_bit(WORK_ENABLE, &tp->flags))
1788 return;
1789
1790 /* When link down, the driver would cancel all bulks. */
1791 /* This avoid the re-submitting bulk */
1792 if (!netif_carrier_ok(tp->netdev))
1793 return;
1794
1795 rx_bottom(tp);
1796 tx_bottom(tp);
1797 }
1798
1799 static
1800 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
1801 {
1802 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
1803 agg->head, agg_buf_sz,
1804 (usb_complete_t)read_bulk_callback, agg);
1805
1806 return usb_submit_urb(agg->urb, mem_flags);
1807 }
1808
1809 static void rtl_drop_queued_tx(struct r8152 *tp)
1810 {
1811 struct net_device_stats *stats = &tp->netdev->stats;
1812 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1813 struct sk_buff *skb;
1814
1815 if (skb_queue_empty(tx_queue))
1816 return;
1817
1818 __skb_queue_head_init(&skb_head);
1819 spin_lock_bh(&tx_queue->lock);
1820 skb_queue_splice_init(tx_queue, &skb_head);
1821 spin_unlock_bh(&tx_queue->lock);
1822
1823 while ((skb = __skb_dequeue(&skb_head))) {
1824 dev_kfree_skb(skb);
1825 stats->tx_dropped++;
1826 }
1827 }
1828
1829 static void rtl8152_tx_timeout(struct net_device *netdev)
1830 {
1831 struct r8152 *tp = netdev_priv(netdev);
1832 int i;
1833
1834 netif_warn(tp, tx_err, netdev, "Tx timeout\n");
1835 for (i = 0; i < RTL8152_MAX_TX; i++)
1836 usb_unlink_urb(tp->tx_info[i].urb);
1837 }
1838
1839 static void rtl8152_set_rx_mode(struct net_device *netdev)
1840 {
1841 struct r8152 *tp = netdev_priv(netdev);
1842
1843 if (tp->speed & LINK_STATUS) {
1844 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
1845 schedule_delayed_work(&tp->schedule, 0);
1846 }
1847 }
1848
1849 static void _rtl8152_set_rx_mode(struct net_device *netdev)
1850 {
1851 struct r8152 *tp = netdev_priv(netdev);
1852 u32 mc_filter[2]; /* Multicast hash filter */
1853 __le32 tmp[2];
1854 u32 ocp_data;
1855
1856 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
1857 netif_stop_queue(netdev);
1858 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1859 ocp_data &= ~RCR_ACPT_ALL;
1860 ocp_data |= RCR_AB | RCR_APM;
1861
1862 if (netdev->flags & IFF_PROMISC) {
1863 /* Unconditionally log net taps. */
1864 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
1865 ocp_data |= RCR_AM | RCR_AAP;
1866 mc_filter[1] = 0xffffffff;
1867 mc_filter[0] = 0xffffffff;
1868 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
1869 (netdev->flags & IFF_ALLMULTI)) {
1870 /* Too many to filter perfectly -- accept all multicasts. */
1871 ocp_data |= RCR_AM;
1872 mc_filter[1] = 0xffffffff;
1873 mc_filter[0] = 0xffffffff;
1874 } else {
1875 struct netdev_hw_addr *ha;
1876
1877 mc_filter[1] = 0;
1878 mc_filter[0] = 0;
1879 netdev_for_each_mc_addr(ha, netdev) {
1880 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1881
1882 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1883 ocp_data |= RCR_AM;
1884 }
1885 }
1886
1887 tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
1888 tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
1889
1890 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
1891 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1892 netif_wake_queue(netdev);
1893 }
1894
1895 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
1896 struct net_device *netdev)
1897 {
1898 struct r8152 *tp = netdev_priv(netdev);
1899
1900 skb_tx_timestamp(skb);
1901
1902 skb_queue_tail(&tp->tx_queue, skb);
1903
1904 if (!list_empty(&tp->tx_free)) {
1905 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
1906 set_bit(SCHEDULE_TASKLET, &tp->flags);
1907 schedule_delayed_work(&tp->schedule, 0);
1908 } else {
1909 usb_mark_last_busy(tp->udev);
1910 tasklet_schedule(&tp->tl);
1911 }
1912 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
1913 netif_stop_queue(netdev);
1914 }
1915
1916 return NETDEV_TX_OK;
1917 }
1918
1919 static void r8152b_reset_packet_filter(struct r8152 *tp)
1920 {
1921 u32 ocp_data;
1922
1923 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
1924 ocp_data &= ~FMC_FCR_MCU_EN;
1925 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
1926 ocp_data |= FMC_FCR_MCU_EN;
1927 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
1928 }
1929
1930 static void rtl8152_nic_reset(struct r8152 *tp)
1931 {
1932 int i;
1933
1934 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
1935
1936 for (i = 0; i < 1000; i++) {
1937 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
1938 break;
1939 usleep_range(100, 400);
1940 }
1941 }
1942
1943 static void set_tx_qlen(struct r8152 *tp)
1944 {
1945 struct net_device *netdev = tp->netdev;
1946
1947 tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN +
1948 sizeof(struct tx_desc));
1949 }
1950
1951 static inline u8 rtl8152_get_speed(struct r8152 *tp)
1952 {
1953 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
1954 }
1955
1956 static void rtl_set_eee_plus(struct r8152 *tp)
1957 {
1958 u32 ocp_data;
1959 u8 speed;
1960
1961 speed = rtl8152_get_speed(tp);
1962 if (speed & _10bps) {
1963 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
1964 ocp_data |= EEEP_CR_EEEP_TX;
1965 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
1966 } else {
1967 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
1968 ocp_data &= ~EEEP_CR_EEEP_TX;
1969 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
1970 }
1971 }
1972
1973 static void rxdy_gated_en(struct r8152 *tp, bool enable)
1974 {
1975 u32 ocp_data;
1976
1977 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
1978 if (enable)
1979 ocp_data |= RXDY_GATED_EN;
1980 else
1981 ocp_data &= ~RXDY_GATED_EN;
1982 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
1983 }
1984
1985 static int rtl_start_rx(struct r8152 *tp)
1986 {
1987 int i, ret = 0;
1988
1989 INIT_LIST_HEAD(&tp->rx_done);
1990 for (i = 0; i < RTL8152_MAX_RX; i++) {
1991 INIT_LIST_HEAD(&tp->rx_info[i].list);
1992 ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
1993 if (ret)
1994 break;
1995 }
1996
1997 return ret;
1998 }
1999
2000 static int rtl_stop_rx(struct r8152 *tp)
2001 {
2002 int i;
2003
2004 for (i = 0; i < RTL8152_MAX_RX; i++)
2005 usb_kill_urb(tp->rx_info[i].urb);
2006
2007 return 0;
2008 }
2009
2010 static int rtl_enable(struct r8152 *tp)
2011 {
2012 u32 ocp_data;
2013
2014 r8152b_reset_packet_filter(tp);
2015
2016 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2017 ocp_data |= CR_RE | CR_TE;
2018 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2019
2020 rxdy_gated_en(tp, false);
2021
2022 return rtl_start_rx(tp);
2023 }
2024
2025 static int rtl8152_enable(struct r8152 *tp)
2026 {
2027 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2028 return -ENODEV;
2029
2030 set_tx_qlen(tp);
2031 rtl_set_eee_plus(tp);
2032
2033 return rtl_enable(tp);
2034 }
2035
2036 static void r8153_set_rx_agg(struct r8152 *tp)
2037 {
2038 u8 speed;
2039
2040 speed = rtl8152_get_speed(tp);
2041 if (speed & _1000bps) {
2042 if (tp->udev->speed == USB_SPEED_SUPER) {
2043 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH,
2044 RX_THR_SUPPER);
2045 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
2046 EARLY_AGG_SUPPER);
2047 } else {
2048 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH,
2049 RX_THR_HIGH);
2050 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
2051 EARLY_AGG_HIGH);
2052 }
2053 } else {
2054 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_SLOW);
2055 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
2056 EARLY_AGG_SLOW);
2057 }
2058 }
2059
2060 static int rtl8153_enable(struct r8152 *tp)
2061 {
2062 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2063 return -ENODEV;
2064
2065 set_tx_qlen(tp);
2066 rtl_set_eee_plus(tp);
2067 r8153_set_rx_agg(tp);
2068
2069 return rtl_enable(tp);
2070 }
2071
2072 static void rtl_disable(struct r8152 *tp)
2073 {
2074 u32 ocp_data;
2075 int i;
2076
2077 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2078 rtl_drop_queued_tx(tp);
2079 return;
2080 }
2081
2082 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2083 ocp_data &= ~RCR_ACPT_ALL;
2084 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2085
2086 rtl_drop_queued_tx(tp);
2087
2088 for (i = 0; i < RTL8152_MAX_TX; i++)
2089 usb_kill_urb(tp->tx_info[i].urb);
2090
2091 rxdy_gated_en(tp, true);
2092
2093 for (i = 0; i < 1000; i++) {
2094 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2095 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2096 break;
2097 usleep_range(1000, 2000);
2098 }
2099
2100 for (i = 0; i < 1000; i++) {
2101 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2102 break;
2103 usleep_range(1000, 2000);
2104 }
2105
2106 rtl_stop_rx(tp);
2107
2108 rtl8152_nic_reset(tp);
2109 }
2110
2111 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2112 {
2113 u32 ocp_data;
2114
2115 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2116 if (enable)
2117 ocp_data |= POWER_CUT;
2118 else
2119 ocp_data &= ~POWER_CUT;
2120 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2121
2122 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2123 ocp_data &= ~RESUME_INDICATE;
2124 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2125 }
2126
2127 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
2128 {
2129 u32 ocp_data;
2130
2131 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2132 if (enable)
2133 ocp_data |= CPCR_RX_VLAN;
2134 else
2135 ocp_data &= ~CPCR_RX_VLAN;
2136 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2137 }
2138
2139 static int rtl8152_set_features(struct net_device *dev,
2140 netdev_features_t features)
2141 {
2142 netdev_features_t changed = features ^ dev->features;
2143 struct r8152 *tp = netdev_priv(dev);
2144 int ret;
2145
2146 ret = usb_autopm_get_interface(tp->intf);
2147 if (ret < 0)
2148 goto out;
2149
2150 mutex_lock(&tp->control);
2151
2152 if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
2153 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2154 rtl_rx_vlan_en(tp, true);
2155 else
2156 rtl_rx_vlan_en(tp, false);
2157 }
2158
2159 mutex_unlock(&tp->control);
2160
2161 usb_autopm_put_interface(tp->intf);
2162
2163 out:
2164 return ret;
2165 }
2166
2167 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2168
2169 static u32 __rtl_get_wol(struct r8152 *tp)
2170 {
2171 u32 ocp_data;
2172 u32 wolopts = 0;
2173
2174 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2175 if (!(ocp_data & LAN_WAKE_EN))
2176 return 0;
2177
2178 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2179 if (ocp_data & LINK_ON_WAKE_EN)
2180 wolopts |= WAKE_PHY;
2181
2182 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2183 if (ocp_data & UWF_EN)
2184 wolopts |= WAKE_UCAST;
2185 if (ocp_data & BWF_EN)
2186 wolopts |= WAKE_BCAST;
2187 if (ocp_data & MWF_EN)
2188 wolopts |= WAKE_MCAST;
2189
2190 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2191 if (ocp_data & MAGIC_EN)
2192 wolopts |= WAKE_MAGIC;
2193
2194 return wolopts;
2195 }
2196
2197 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
2198 {
2199 u32 ocp_data;
2200
2201 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2202
2203 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2204 ocp_data &= ~LINK_ON_WAKE_EN;
2205 if (wolopts & WAKE_PHY)
2206 ocp_data |= LINK_ON_WAKE_EN;
2207 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2208
2209 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2210 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN | LAN_WAKE_EN);
2211 if (wolopts & WAKE_UCAST)
2212 ocp_data |= UWF_EN;
2213 if (wolopts & WAKE_BCAST)
2214 ocp_data |= BWF_EN;
2215 if (wolopts & WAKE_MCAST)
2216 ocp_data |= MWF_EN;
2217 if (wolopts & WAKE_ANY)
2218 ocp_data |= LAN_WAKE_EN;
2219 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
2220
2221 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2222
2223 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2224 ocp_data &= ~MAGIC_EN;
2225 if (wolopts & WAKE_MAGIC)
2226 ocp_data |= MAGIC_EN;
2227 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
2228
2229 if (wolopts & WAKE_ANY)
2230 device_set_wakeup_enable(&tp->udev->dev, true);
2231 else
2232 device_set_wakeup_enable(&tp->udev->dev, false);
2233 }
2234
2235 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
2236 {
2237 if (enable) {
2238 u32 ocp_data;
2239
2240 __rtl_set_wol(tp, WAKE_ANY);
2241
2242 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2243
2244 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2245 ocp_data |= LINK_OFF_WAKE_EN;
2246 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2247
2248 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2249 } else {
2250 __rtl_set_wol(tp, tp->saved_wolopts);
2251 }
2252 }
2253
2254 static void rtl_phy_reset(struct r8152 *tp)
2255 {
2256 u16 data;
2257 int i;
2258
2259 clear_bit(PHY_RESET, &tp->flags);
2260
2261 data = r8152_mdio_read(tp, MII_BMCR);
2262
2263 /* don't reset again before the previous one complete */
2264 if (data & BMCR_RESET)
2265 return;
2266
2267 data |= BMCR_RESET;
2268 r8152_mdio_write(tp, MII_BMCR, data);
2269
2270 for (i = 0; i < 50; i++) {
2271 msleep(20);
2272 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
2273 break;
2274 }
2275 }
2276
2277 static void r8153_teredo_off(struct r8152 *tp)
2278 {
2279 u32 ocp_data;
2280
2281 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2282 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN);
2283 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2284
2285 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
2286 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
2287 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
2288 }
2289
2290 static void r8152b_disable_aldps(struct r8152 *tp)
2291 {
2292 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
2293 msleep(20);
2294 }
2295
2296 static inline void r8152b_enable_aldps(struct r8152 *tp)
2297 {
2298 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
2299 LINKENA | DIS_SDSAVE);
2300 }
2301
2302 static void rtl8152_disable(struct r8152 *tp)
2303 {
2304 r8152b_disable_aldps(tp);
2305 rtl_disable(tp);
2306 r8152b_enable_aldps(tp);
2307 }
2308
2309 static void r8152b_hw_phy_cfg(struct r8152 *tp)
2310 {
2311 u16 data;
2312
2313 data = r8152_mdio_read(tp, MII_BMCR);
2314 if (data & BMCR_PDOWN) {
2315 data &= ~BMCR_PDOWN;
2316 r8152_mdio_write(tp, MII_BMCR, data);
2317 }
2318
2319 set_bit(PHY_RESET, &tp->flags);
2320 }
2321
2322 static void r8152b_exit_oob(struct r8152 *tp)
2323 {
2324 u32 ocp_data;
2325 int i;
2326
2327 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2328 ocp_data &= ~RCR_ACPT_ALL;
2329 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2330
2331 rxdy_gated_en(tp, true);
2332 r8153_teredo_off(tp);
2333 r8152b_hw_phy_cfg(tp);
2334
2335 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2336 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
2337
2338 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2339 ocp_data &= ~NOW_IS_OOB;
2340 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2341
2342 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2343 ocp_data &= ~MCU_BORW_EN;
2344 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2345
2346 for (i = 0; i < 1000; i++) {
2347 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2348 if (ocp_data & LINK_LIST_READY)
2349 break;
2350 usleep_range(1000, 2000);
2351 }
2352
2353 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2354 ocp_data |= RE_INIT_LL;
2355 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2356
2357 for (i = 0; i < 1000; i++) {
2358 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2359 if (ocp_data & LINK_LIST_READY)
2360 break;
2361 usleep_range(1000, 2000);
2362 }
2363
2364 rtl8152_nic_reset(tp);
2365
2366 /* rx share fifo credit full threshold */
2367 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2368
2369 if (tp->udev->speed == USB_SPEED_FULL ||
2370 tp->udev->speed == USB_SPEED_LOW) {
2371 /* rx share fifo credit near full threshold */
2372 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2373 RXFIFO_THR2_FULL);
2374 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2375 RXFIFO_THR3_FULL);
2376 } else {
2377 /* rx share fifo credit near full threshold */
2378 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2379 RXFIFO_THR2_HIGH);
2380 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2381 RXFIFO_THR3_HIGH);
2382 }
2383
2384 /* TX share fifo free credit full threshold */
2385 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
2386
2387 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
2388 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
2389 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
2390 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
2391
2392 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
2393
2394 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2395
2396 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2397 ocp_data |= TCR0_AUTO_FIFO;
2398 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2399 }
2400
2401 static void r8152b_enter_oob(struct r8152 *tp)
2402 {
2403 u32 ocp_data;
2404 int i;
2405
2406 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2407 ocp_data &= ~NOW_IS_OOB;
2408 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2409
2410 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
2411 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
2412 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
2413
2414 rtl_disable(tp);
2415
2416 for (i = 0; i < 1000; i++) {
2417 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2418 if (ocp_data & LINK_LIST_READY)
2419 break;
2420 usleep_range(1000, 2000);
2421 }
2422
2423 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2424 ocp_data |= RE_INIT_LL;
2425 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2426
2427 for (i = 0; i < 1000; i++) {
2428 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2429 if (ocp_data & LINK_LIST_READY)
2430 break;
2431 usleep_range(1000, 2000);
2432 }
2433
2434 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2435
2436 rtl_rx_vlan_en(tp, true);
2437
2438 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2439 ocp_data |= ALDPS_PROXY_MODE;
2440 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2441
2442 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2443 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2444 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2445
2446 rxdy_gated_en(tp, false);
2447
2448 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2449 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2450 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2451 }
2452
2453 static void r8153_hw_phy_cfg(struct r8152 *tp)
2454 {
2455 u32 ocp_data;
2456 u16 data;
2457
2458 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
2459 data = r8152_mdio_read(tp, MII_BMCR);
2460 if (data & BMCR_PDOWN) {
2461 data &= ~BMCR_PDOWN;
2462 r8152_mdio_write(tp, MII_BMCR, data);
2463 }
2464
2465 if (tp->version == RTL_VER_03) {
2466 data = ocp_reg_read(tp, OCP_EEE_CFG);
2467 data &= ~CTAP_SHORT_EN;
2468 ocp_reg_write(tp, OCP_EEE_CFG, data);
2469 }
2470
2471 data = ocp_reg_read(tp, OCP_POWER_CFG);
2472 data |= EEE_CLKDIV_EN;
2473 ocp_reg_write(tp, OCP_POWER_CFG, data);
2474
2475 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
2476 data |= EN_10M_BGOFF;
2477 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
2478 data = ocp_reg_read(tp, OCP_POWER_CFG);
2479 data |= EN_10M_PLLOFF;
2480 ocp_reg_write(tp, OCP_POWER_CFG, data);
2481 data = sram_read(tp, SRAM_IMPEDANCE);
2482 data &= ~RX_DRIVING_MASK;
2483 sram_write(tp, SRAM_IMPEDANCE, data);
2484
2485 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
2486 ocp_data |= PFM_PWM_SWITCH;
2487 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
2488
2489 data = sram_read(tp, SRAM_LPF_CFG);
2490 data |= LPF_AUTO_TUNE;
2491 sram_write(tp, SRAM_LPF_CFG, data);
2492
2493 data = sram_read(tp, SRAM_10M_AMP1);
2494 data |= GDAC_IB_UPALL;
2495 sram_write(tp, SRAM_10M_AMP1, data);
2496 data = sram_read(tp, SRAM_10M_AMP2);
2497 data |= AMP_DN;
2498 sram_write(tp, SRAM_10M_AMP2, data);
2499
2500 set_bit(PHY_RESET, &tp->flags);
2501 }
2502
2503 static void r8153_u1u2en(struct r8152 *tp, bool enable)
2504 {
2505 u8 u1u2[8];
2506
2507 if (enable)
2508 memset(u1u2, 0xff, sizeof(u1u2));
2509 else
2510 memset(u1u2, 0x00, sizeof(u1u2));
2511
2512 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
2513 }
2514
2515 static void r8153_u2p3en(struct r8152 *tp, bool enable)
2516 {
2517 u32 ocp_data;
2518
2519 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
2520 if (enable)
2521 ocp_data |= U2P3_ENABLE;
2522 else
2523 ocp_data &= ~U2P3_ENABLE;
2524 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
2525 }
2526
2527 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
2528 {
2529 u32 ocp_data;
2530
2531 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2532 if (enable)
2533 ocp_data |= PWR_EN | PHASE2_EN;
2534 else
2535 ocp_data &= ~(PWR_EN | PHASE2_EN);
2536 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2537
2538 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2539 ocp_data &= ~PCUT_STATUS;
2540 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2541 }
2542
2543 static void r8153_first_init(struct r8152 *tp)
2544 {
2545 u32 ocp_data;
2546 int i;
2547
2548 rxdy_gated_en(tp, true);
2549 r8153_teredo_off(tp);
2550
2551 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2552 ocp_data &= ~RCR_ACPT_ALL;
2553 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2554
2555 r8153_hw_phy_cfg(tp);
2556
2557 rtl8152_nic_reset(tp);
2558
2559 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2560 ocp_data &= ~NOW_IS_OOB;
2561 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2562
2563 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2564 ocp_data &= ~MCU_BORW_EN;
2565 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2566
2567 for (i = 0; i < 1000; i++) {
2568 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2569 if (ocp_data & LINK_LIST_READY)
2570 break;
2571 usleep_range(1000, 2000);
2572 }
2573
2574 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2575 ocp_data |= RE_INIT_LL;
2576 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2577
2578 for (i = 0; i < 1000; i++) {
2579 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2580 if (ocp_data & LINK_LIST_READY)
2581 break;
2582 usleep_range(1000, 2000);
2583 }
2584
2585 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
2586
2587 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
2588 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
2589
2590 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2591 ocp_data |= TCR0_AUTO_FIFO;
2592 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2593
2594 rtl8152_nic_reset(tp);
2595
2596 /* rx share fifo credit full threshold */
2597 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2598 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
2599 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
2600 /* TX share fifo free credit full threshold */
2601 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
2602
2603 /* rx aggregation */
2604 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2605 ocp_data &= ~RX_AGG_DISABLE;
2606 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2607 }
2608
2609 static void r8153_enter_oob(struct r8152 *tp)
2610 {
2611 u32 ocp_data;
2612 int i;
2613
2614 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2615 ocp_data &= ~NOW_IS_OOB;
2616 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2617
2618 rtl_disable(tp);
2619
2620 for (i = 0; i < 1000; i++) {
2621 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2622 if (ocp_data & LINK_LIST_READY)
2623 break;
2624 usleep_range(1000, 2000);
2625 }
2626
2627 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2628 ocp_data |= RE_INIT_LL;
2629 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2630
2631 for (i = 0; i < 1000; i++) {
2632 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2633 if (ocp_data & LINK_LIST_READY)
2634 break;
2635 usleep_range(1000, 2000);
2636 }
2637
2638 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
2639
2640 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2641 ocp_data &= ~TEREDO_WAKE_MASK;
2642 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2643
2644 rtl_rx_vlan_en(tp, true);
2645
2646 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2647 ocp_data |= ALDPS_PROXY_MODE;
2648 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2649
2650 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2651 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2652 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2653
2654 rxdy_gated_en(tp, false);
2655
2656 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2657 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2658 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2659 }
2660
2661 static void r8153_disable_aldps(struct r8152 *tp)
2662 {
2663 u16 data;
2664
2665 data = ocp_reg_read(tp, OCP_POWER_CFG);
2666 data &= ~EN_ALDPS;
2667 ocp_reg_write(tp, OCP_POWER_CFG, data);
2668 msleep(20);
2669 }
2670
2671 static void r8153_enable_aldps(struct r8152 *tp)
2672 {
2673 u16 data;
2674
2675 data = ocp_reg_read(tp, OCP_POWER_CFG);
2676 data |= EN_ALDPS;
2677 ocp_reg_write(tp, OCP_POWER_CFG, data);
2678 }
2679
2680 static void rtl8153_disable(struct r8152 *tp)
2681 {
2682 r8153_disable_aldps(tp);
2683 rtl_disable(tp);
2684 r8153_enable_aldps(tp);
2685 }
2686
2687 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
2688 {
2689 u16 bmcr, anar, gbcr;
2690 int ret = 0;
2691
2692 cancel_delayed_work_sync(&tp->schedule);
2693 anar = r8152_mdio_read(tp, MII_ADVERTISE);
2694 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
2695 ADVERTISE_100HALF | ADVERTISE_100FULL);
2696 if (tp->mii.supports_gmii) {
2697 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
2698 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
2699 } else {
2700 gbcr = 0;
2701 }
2702
2703 if (autoneg == AUTONEG_DISABLE) {
2704 if (speed == SPEED_10) {
2705 bmcr = 0;
2706 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2707 } else if (speed == SPEED_100) {
2708 bmcr = BMCR_SPEED100;
2709 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2710 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2711 bmcr = BMCR_SPEED1000;
2712 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
2713 } else {
2714 ret = -EINVAL;
2715 goto out;
2716 }
2717
2718 if (duplex == DUPLEX_FULL)
2719 bmcr |= BMCR_FULLDPLX;
2720 } else {
2721 if (speed == SPEED_10) {
2722 if (duplex == DUPLEX_FULL)
2723 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2724 else
2725 anar |= ADVERTISE_10HALF;
2726 } else if (speed == SPEED_100) {
2727 if (duplex == DUPLEX_FULL) {
2728 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2729 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2730 } else {
2731 anar |= ADVERTISE_10HALF;
2732 anar |= ADVERTISE_100HALF;
2733 }
2734 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2735 if (duplex == DUPLEX_FULL) {
2736 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2737 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2738 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
2739 } else {
2740 anar |= ADVERTISE_10HALF;
2741 anar |= ADVERTISE_100HALF;
2742 gbcr |= ADVERTISE_1000HALF;
2743 }
2744 } else {
2745 ret = -EINVAL;
2746 goto out;
2747 }
2748
2749 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
2750 }
2751
2752 if (test_bit(PHY_RESET, &tp->flags))
2753 bmcr |= BMCR_RESET;
2754
2755 if (tp->mii.supports_gmii)
2756 r8152_mdio_write(tp, MII_CTRL1000, gbcr);
2757
2758 r8152_mdio_write(tp, MII_ADVERTISE, anar);
2759 r8152_mdio_write(tp, MII_BMCR, bmcr);
2760
2761 if (test_bit(PHY_RESET, &tp->flags)) {
2762 int i;
2763
2764 clear_bit(PHY_RESET, &tp->flags);
2765 for (i = 0; i < 50; i++) {
2766 msleep(20);
2767 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
2768 break;
2769 }
2770 }
2771
2772 out:
2773
2774 return ret;
2775 }
2776
2777 static void rtl8152_up(struct r8152 *tp)
2778 {
2779 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2780 return;
2781
2782 r8152b_disable_aldps(tp);
2783 r8152b_exit_oob(tp);
2784 r8152b_enable_aldps(tp);
2785 }
2786
2787 static void rtl8152_down(struct r8152 *tp)
2788 {
2789 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2790 rtl_drop_queued_tx(tp);
2791 return;
2792 }
2793
2794 r8152_power_cut_en(tp, false);
2795 r8152b_disable_aldps(tp);
2796 r8152b_enter_oob(tp);
2797 r8152b_enable_aldps(tp);
2798 }
2799
2800 static void rtl8153_up(struct r8152 *tp)
2801 {
2802 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2803 return;
2804
2805 r8153_disable_aldps(tp);
2806 r8153_first_init(tp);
2807 r8153_enable_aldps(tp);
2808 }
2809
2810 static void rtl8153_down(struct r8152 *tp)
2811 {
2812 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2813 rtl_drop_queued_tx(tp);
2814 return;
2815 }
2816
2817 r8153_u1u2en(tp, false);
2818 r8153_power_cut_en(tp, false);
2819 r8153_disable_aldps(tp);
2820 r8153_enter_oob(tp);
2821 r8153_enable_aldps(tp);
2822 }
2823
2824 static void set_carrier(struct r8152 *tp)
2825 {
2826 struct net_device *netdev = tp->netdev;
2827 u8 speed;
2828
2829 clear_bit(RTL8152_LINK_CHG, &tp->flags);
2830 speed = rtl8152_get_speed(tp);
2831
2832 if (speed & LINK_STATUS) {
2833 if (!(tp->speed & LINK_STATUS)) {
2834 tp->rtl_ops.enable(tp);
2835 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2836 netif_carrier_on(netdev);
2837 }
2838 } else {
2839 if (tp->speed & LINK_STATUS) {
2840 netif_carrier_off(netdev);
2841 tasklet_disable(&tp->tl);
2842 tp->rtl_ops.disable(tp);
2843 tasklet_enable(&tp->tl);
2844 }
2845 }
2846 tp->speed = speed;
2847 }
2848
2849 static void rtl_work_func_t(struct work_struct *work)
2850 {
2851 struct r8152 *tp = container_of(work, struct r8152, schedule.work);
2852
2853 if (usb_autopm_get_interface(tp->intf) < 0)
2854 return;
2855
2856 if (!test_bit(WORK_ENABLE, &tp->flags))
2857 goto out1;
2858
2859 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2860 goto out1;
2861
2862 if (!mutex_trylock(&tp->control)) {
2863 schedule_delayed_work(&tp->schedule, 0);
2864 goto out1;
2865 }
2866
2867 if (test_bit(RTL8152_LINK_CHG, &tp->flags))
2868 set_carrier(tp);
2869
2870 if (test_bit(RTL8152_SET_RX_MODE, &tp->flags))
2871 _rtl8152_set_rx_mode(tp->netdev);
2872
2873 if (test_bit(SCHEDULE_TASKLET, &tp->flags) &&
2874 (tp->speed & LINK_STATUS)) {
2875 clear_bit(SCHEDULE_TASKLET, &tp->flags);
2876 tasklet_schedule(&tp->tl);
2877 }
2878
2879 if (test_bit(PHY_RESET, &tp->flags))
2880 rtl_phy_reset(tp);
2881
2882 mutex_unlock(&tp->control);
2883
2884 out1:
2885 usb_autopm_put_interface(tp->intf);
2886 }
2887
2888 static int rtl8152_open(struct net_device *netdev)
2889 {
2890 struct r8152 *tp = netdev_priv(netdev);
2891 int res = 0;
2892
2893 res = alloc_all_mem(tp);
2894 if (res)
2895 goto out;
2896
2897 /* set speed to 0 to avoid autoresume try to submit rx */
2898 tp->speed = 0;
2899
2900 res = usb_autopm_get_interface(tp->intf);
2901 if (res < 0) {
2902 free_all_mem(tp);
2903 goto out;
2904 }
2905
2906 mutex_lock(&tp->control);
2907
2908 /* The WORK_ENABLE may be set when autoresume occurs */
2909 if (test_bit(WORK_ENABLE, &tp->flags)) {
2910 clear_bit(WORK_ENABLE, &tp->flags);
2911 usb_kill_urb(tp->intr_urb);
2912 cancel_delayed_work_sync(&tp->schedule);
2913
2914 /* disable the tx/rx, if the workqueue has enabled them. */
2915 if (tp->speed & LINK_STATUS)
2916 tp->rtl_ops.disable(tp);
2917 }
2918
2919 tp->rtl_ops.up(tp);
2920
2921 rtl8152_set_speed(tp, AUTONEG_ENABLE,
2922 tp->mii.supports_gmii ? SPEED_1000 : SPEED_100,
2923 DUPLEX_FULL);
2924 tp->speed = 0;
2925 netif_carrier_off(netdev);
2926 netif_start_queue(netdev);
2927 set_bit(WORK_ENABLE, &tp->flags);
2928
2929 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
2930 if (res) {
2931 if (res == -ENODEV)
2932 netif_device_detach(tp->netdev);
2933 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
2934 res);
2935 free_all_mem(tp);
2936 }
2937
2938 mutex_unlock(&tp->control);
2939
2940 usb_autopm_put_interface(tp->intf);
2941
2942 out:
2943 return res;
2944 }
2945
2946 static int rtl8152_close(struct net_device *netdev)
2947 {
2948 struct r8152 *tp = netdev_priv(netdev);
2949 int res = 0;
2950
2951 clear_bit(WORK_ENABLE, &tp->flags);
2952 usb_kill_urb(tp->intr_urb);
2953 cancel_delayed_work_sync(&tp->schedule);
2954 netif_stop_queue(netdev);
2955
2956 res = usb_autopm_get_interface(tp->intf);
2957 if (res < 0) {
2958 rtl_drop_queued_tx(tp);
2959 } else {
2960 mutex_lock(&tp->control);
2961
2962 /* The autosuspend may have been enabled and wouldn't
2963 * be disable when autoresume occurs, because the
2964 * netif_running() would be false.
2965 */
2966 rtl_runtime_suspend_enable(tp, false);
2967
2968 tasklet_disable(&tp->tl);
2969 tp->rtl_ops.down(tp);
2970 tasklet_enable(&tp->tl);
2971
2972 mutex_unlock(&tp->control);
2973
2974 usb_autopm_put_interface(tp->intf);
2975 }
2976
2977 free_all_mem(tp);
2978
2979 return res;
2980 }
2981
2982 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
2983 {
2984 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
2985 ocp_reg_write(tp, OCP_EEE_DATA, reg);
2986 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
2987 }
2988
2989 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
2990 {
2991 u16 data;
2992
2993 r8152_mmd_indirect(tp, dev, reg);
2994 data = ocp_reg_read(tp, OCP_EEE_DATA);
2995 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
2996
2997 return data;
2998 }
2999
3000 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
3001 {
3002 r8152_mmd_indirect(tp, dev, reg);
3003 ocp_reg_write(tp, OCP_EEE_DATA, data);
3004 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
3005 }
3006
3007 static void r8152_eee_en(struct r8152 *tp, bool enable)
3008 {
3009 u16 config1, config2, config3;
3010 u32 ocp_data;
3011
3012 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3013 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
3014 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
3015 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
3016
3017 if (enable) {
3018 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3019 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
3020 config1 |= sd_rise_time(1);
3021 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
3022 config3 |= fast_snr(42);
3023 } else {
3024 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3025 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
3026 RX_QUIET_EN);
3027 config1 |= sd_rise_time(7);
3028 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
3029 config3 |= fast_snr(511);
3030 }
3031
3032 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
3033 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
3034 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
3035 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
3036 }
3037
3038 static void r8152b_enable_eee(struct r8152 *tp)
3039 {
3040 r8152_eee_en(tp, true);
3041 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX);
3042 }
3043
3044 static void r8153_eee_en(struct r8152 *tp, bool enable)
3045 {
3046 u32 ocp_data;
3047 u16 config;
3048
3049 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3050 config = ocp_reg_read(tp, OCP_EEE_CFG);
3051
3052 if (enable) {
3053 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3054 config |= EEE10_EN;
3055 } else {
3056 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3057 config &= ~EEE10_EN;
3058 }
3059
3060 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
3061 ocp_reg_write(tp, OCP_EEE_CFG, config);
3062 }
3063
3064 static void r8153_enable_eee(struct r8152 *tp)
3065 {
3066 r8153_eee_en(tp, true);
3067 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
3068 }
3069
3070 static void r8152b_enable_fc(struct r8152 *tp)
3071 {
3072 u16 anar;
3073
3074 anar = r8152_mdio_read(tp, MII_ADVERTISE);
3075 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3076 r8152_mdio_write(tp, MII_ADVERTISE, anar);
3077 }
3078
3079 static void rtl_tally_reset(struct r8152 *tp)
3080 {
3081 u32 ocp_data;
3082
3083 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
3084 ocp_data |= TALLY_RESET;
3085 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
3086 }
3087
3088 static void r8152b_init(struct r8152 *tp)
3089 {
3090 u32 ocp_data;
3091
3092 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3093 return;
3094
3095 r8152b_disable_aldps(tp);
3096
3097 if (tp->version == RTL_VER_01) {
3098 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3099 ocp_data &= ~LED_MODE_MASK;
3100 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3101 }
3102
3103 r8152_power_cut_en(tp, false);
3104
3105 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3106 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
3107 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3108 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
3109 ocp_data &= ~MCU_CLK_RATIO_MASK;
3110 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
3111 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
3112 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
3113 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
3114 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
3115
3116 r8152b_enable_eee(tp);
3117 r8152b_enable_aldps(tp);
3118 r8152b_enable_fc(tp);
3119 rtl_tally_reset(tp);
3120
3121 /* enable rx aggregation */
3122 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
3123 ocp_data &= ~RX_AGG_DISABLE;
3124 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
3125 }
3126
3127 static void r8153_init(struct r8152 *tp)
3128 {
3129 u32 ocp_data;
3130 int i;
3131
3132 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3133 return;
3134
3135 r8153_disable_aldps(tp);
3136 r8153_u1u2en(tp, false);
3137
3138 for (i = 0; i < 500; i++) {
3139 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
3140 AUTOLOAD_DONE)
3141 break;
3142 msleep(20);
3143 }
3144
3145 for (i = 0; i < 500; i++) {
3146 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
3147 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
3148 break;
3149 msleep(20);
3150 }
3151
3152 r8153_u2p3en(tp, false);
3153
3154 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
3155 ocp_data &= ~TIMER11_EN;
3156 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
3157
3158 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3159 ocp_data &= ~LED_MODE_MASK;
3160 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3161
3162 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL);
3163 ocp_data &= ~LPM_TIMER_MASK;
3164 if (tp->udev->speed == USB_SPEED_SUPER)
3165 ocp_data |= LPM_TIMER_500US;
3166 else
3167 ocp_data |= LPM_TIMER_500MS;
3168 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
3169
3170 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
3171 ocp_data &= ~SEN_VAL_MASK;
3172 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
3173 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
3174
3175 r8153_power_cut_en(tp, false);
3176 r8153_u1u2en(tp, true);
3177
3178 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO);
3179 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO);
3180 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
3181 PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
3182 U1U2_SPDWN_EN | L1_SPDWN_EN);
3183 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
3184 PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
3185 TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN |
3186 EEE_SPDWN_EN);
3187
3188 r8153_enable_eee(tp);
3189 r8153_enable_aldps(tp);
3190 r8152b_enable_fc(tp);
3191 rtl_tally_reset(tp);
3192 }
3193
3194 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
3195 {
3196 struct r8152 *tp = usb_get_intfdata(intf);
3197 struct net_device *netdev = tp->netdev;
3198 int ret = 0;
3199
3200 mutex_lock(&tp->control);
3201
3202 if (PMSG_IS_AUTO(message)) {
3203 if (netif_running(netdev) && work_busy(&tp->schedule.work)) {
3204 ret = -EBUSY;
3205 goto out1;
3206 }
3207
3208 set_bit(SELECTIVE_SUSPEND, &tp->flags);
3209 } else {
3210 netif_device_detach(netdev);
3211 }
3212
3213 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
3214 clear_bit(WORK_ENABLE, &tp->flags);
3215 usb_kill_urb(tp->intr_urb);
3216 tasklet_disable(&tp->tl);
3217 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3218 rtl_stop_rx(tp);
3219 rtl_runtime_suspend_enable(tp, true);
3220 } else {
3221 cancel_delayed_work_sync(&tp->schedule);
3222 tp->rtl_ops.down(tp);
3223 }
3224 tasklet_enable(&tp->tl);
3225 }
3226 out1:
3227 mutex_unlock(&tp->control);
3228
3229 return ret;
3230 }
3231
3232 static int rtl8152_resume(struct usb_interface *intf)
3233 {
3234 struct r8152 *tp = usb_get_intfdata(intf);
3235
3236 mutex_lock(&tp->control);
3237
3238 if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3239 tp->rtl_ops.init(tp);
3240 netif_device_attach(tp->netdev);
3241 }
3242
3243 if (netif_running(tp->netdev)) {
3244 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3245 rtl_runtime_suspend_enable(tp, false);
3246 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
3247 set_bit(WORK_ENABLE, &tp->flags);
3248 if (tp->speed & LINK_STATUS)
3249 rtl_start_rx(tp);
3250 } else {
3251 tp->rtl_ops.up(tp);
3252 rtl8152_set_speed(tp, AUTONEG_ENABLE,
3253 tp->mii.supports_gmii ?
3254 SPEED_1000 : SPEED_100,
3255 DUPLEX_FULL);
3256 tp->speed = 0;
3257 netif_carrier_off(tp->netdev);
3258 set_bit(WORK_ENABLE, &tp->flags);
3259 }
3260 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
3261 } else if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3262 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
3263 }
3264
3265 mutex_unlock(&tp->control);
3266
3267 return 0;
3268 }
3269
3270 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3271 {
3272 struct r8152 *tp = netdev_priv(dev);
3273
3274 if (usb_autopm_get_interface(tp->intf) < 0)
3275 return;
3276
3277 mutex_lock(&tp->control);
3278
3279 wol->supported = WAKE_ANY;
3280 wol->wolopts = __rtl_get_wol(tp);
3281
3282 mutex_unlock(&tp->control);
3283
3284 usb_autopm_put_interface(tp->intf);
3285 }
3286
3287 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3288 {
3289 struct r8152 *tp = netdev_priv(dev);
3290 int ret;
3291
3292 ret = usb_autopm_get_interface(tp->intf);
3293 if (ret < 0)
3294 goto out_set_wol;
3295
3296 mutex_lock(&tp->control);
3297
3298 __rtl_set_wol(tp, wol->wolopts);
3299 tp->saved_wolopts = wol->wolopts & WAKE_ANY;
3300
3301 mutex_unlock(&tp->control);
3302
3303 usb_autopm_put_interface(tp->intf);
3304
3305 out_set_wol:
3306 return ret;
3307 }
3308
3309 static u32 rtl8152_get_msglevel(struct net_device *dev)
3310 {
3311 struct r8152 *tp = netdev_priv(dev);
3312
3313 return tp->msg_enable;
3314 }
3315
3316 static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
3317 {
3318 struct r8152 *tp = netdev_priv(dev);
3319
3320 tp->msg_enable = value;
3321 }
3322
3323 static void rtl8152_get_drvinfo(struct net_device *netdev,
3324 struct ethtool_drvinfo *info)
3325 {
3326 struct r8152 *tp = netdev_priv(netdev);
3327
3328 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
3329 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
3330 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
3331 }
3332
3333 static
3334 int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
3335 {
3336 struct r8152 *tp = netdev_priv(netdev);
3337 int ret;
3338
3339 if (!tp->mii.mdio_read)
3340 return -EOPNOTSUPP;
3341
3342 ret = usb_autopm_get_interface(tp->intf);
3343 if (ret < 0)
3344 goto out;
3345
3346 mutex_lock(&tp->control);
3347
3348 ret = mii_ethtool_gset(&tp->mii, cmd);
3349
3350 mutex_unlock(&tp->control);
3351
3352 usb_autopm_put_interface(tp->intf);
3353
3354 out:
3355 return ret;
3356 }
3357
3358 static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
3359 {
3360 struct r8152 *tp = netdev_priv(dev);
3361 int ret;
3362
3363 ret = usb_autopm_get_interface(tp->intf);
3364 if (ret < 0)
3365 goto out;
3366
3367 mutex_lock(&tp->control);
3368
3369 ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex);
3370
3371 mutex_unlock(&tp->control);
3372
3373 usb_autopm_put_interface(tp->intf);
3374
3375 out:
3376 return ret;
3377 }
3378
3379 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
3380 "tx_packets",
3381 "rx_packets",
3382 "tx_errors",
3383 "rx_errors",
3384 "rx_missed",
3385 "align_errors",
3386 "tx_single_collisions",
3387 "tx_multi_collisions",
3388 "rx_unicast",
3389 "rx_broadcast",
3390 "rx_multicast",
3391 "tx_aborted",
3392 "tx_underrun",
3393 };
3394
3395 static int rtl8152_get_sset_count(struct net_device *dev, int sset)
3396 {
3397 switch (sset) {
3398 case ETH_SS_STATS:
3399 return ARRAY_SIZE(rtl8152_gstrings);
3400 default:
3401 return -EOPNOTSUPP;
3402 }
3403 }
3404
3405 static void rtl8152_get_ethtool_stats(struct net_device *dev,
3406 struct ethtool_stats *stats, u64 *data)
3407 {
3408 struct r8152 *tp = netdev_priv(dev);
3409 struct tally_counter tally;
3410
3411 if (usb_autopm_get_interface(tp->intf) < 0)
3412 return;
3413
3414 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
3415
3416 usb_autopm_put_interface(tp->intf);
3417
3418 data[0] = le64_to_cpu(tally.tx_packets);
3419 data[1] = le64_to_cpu(tally.rx_packets);
3420 data[2] = le64_to_cpu(tally.tx_errors);
3421 data[3] = le32_to_cpu(tally.rx_errors);
3422 data[4] = le16_to_cpu(tally.rx_missed);
3423 data[5] = le16_to_cpu(tally.align_errors);
3424 data[6] = le32_to_cpu(tally.tx_one_collision);
3425 data[7] = le32_to_cpu(tally.tx_multi_collision);
3426 data[8] = le64_to_cpu(tally.rx_unicast);
3427 data[9] = le64_to_cpu(tally.rx_broadcast);
3428 data[10] = le32_to_cpu(tally.rx_multicast);
3429 data[11] = le16_to_cpu(tally.tx_aborted);
3430 data[12] = le16_to_cpu(tally.tx_underun);
3431 }
3432
3433 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
3434 {
3435 switch (stringset) {
3436 case ETH_SS_STATS:
3437 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
3438 break;
3439 }
3440 }
3441
3442 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
3443 {
3444 u32 ocp_data, lp, adv, supported = 0;
3445 u16 val;
3446
3447 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
3448 supported = mmd_eee_cap_to_ethtool_sup_t(val);
3449
3450 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
3451 adv = mmd_eee_adv_to_ethtool_adv_t(val);
3452
3453 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
3454 lp = mmd_eee_adv_to_ethtool_adv_t(val);
3455
3456 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3457 ocp_data &= EEE_RX_EN | EEE_TX_EN;
3458
3459 eee->eee_enabled = !!ocp_data;
3460 eee->eee_active = !!(supported & adv & lp);
3461 eee->supported = supported;
3462 eee->advertised = adv;
3463 eee->lp_advertised = lp;
3464
3465 return 0;
3466 }
3467
3468 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
3469 {
3470 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
3471
3472 r8152_eee_en(tp, eee->eee_enabled);
3473
3474 if (!eee->eee_enabled)
3475 val = 0;
3476
3477 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
3478
3479 return 0;
3480 }
3481
3482 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
3483 {
3484 u32 ocp_data, lp, adv, supported = 0;
3485 u16 val;
3486
3487 val = ocp_reg_read(tp, OCP_EEE_ABLE);
3488 supported = mmd_eee_cap_to_ethtool_sup_t(val);
3489
3490 val = ocp_reg_read(tp, OCP_EEE_ADV);
3491 adv = mmd_eee_adv_to_ethtool_adv_t(val);
3492
3493 val = ocp_reg_read(tp, OCP_EEE_LPABLE);
3494 lp = mmd_eee_adv_to_ethtool_adv_t(val);
3495
3496 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3497 ocp_data &= EEE_RX_EN | EEE_TX_EN;
3498
3499 eee->eee_enabled = !!ocp_data;
3500 eee->eee_active = !!(supported & adv & lp);
3501 eee->supported = supported;
3502 eee->advertised = adv;
3503 eee->lp_advertised = lp;
3504
3505 return 0;
3506 }
3507
3508 static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
3509 {
3510 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
3511
3512 r8153_eee_en(tp, eee->eee_enabled);
3513
3514 if (!eee->eee_enabled)
3515 val = 0;
3516
3517 ocp_reg_write(tp, OCP_EEE_ADV, val);
3518
3519 return 0;
3520 }
3521
3522 static int
3523 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
3524 {
3525 struct r8152 *tp = netdev_priv(net);
3526 int ret;
3527
3528 ret = usb_autopm_get_interface(tp->intf);
3529 if (ret < 0)
3530 goto out;
3531
3532 mutex_lock(&tp->control);
3533
3534 ret = tp->rtl_ops.eee_get(tp, edata);
3535
3536 mutex_unlock(&tp->control);
3537
3538 usb_autopm_put_interface(tp->intf);
3539
3540 out:
3541 return ret;
3542 }
3543
3544 static int
3545 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
3546 {
3547 struct r8152 *tp = netdev_priv(net);
3548 int ret;
3549
3550 ret = usb_autopm_get_interface(tp->intf);
3551 if (ret < 0)
3552 goto out;
3553
3554 mutex_lock(&tp->control);
3555
3556 ret = tp->rtl_ops.eee_set(tp, edata);
3557 if (!ret)
3558 ret = mii_nway_restart(&tp->mii);
3559
3560 mutex_unlock(&tp->control);
3561
3562 usb_autopm_put_interface(tp->intf);
3563
3564 out:
3565 return ret;
3566 }
3567
3568 static struct ethtool_ops ops = {
3569 .get_drvinfo = rtl8152_get_drvinfo,
3570 .get_settings = rtl8152_get_settings,
3571 .set_settings = rtl8152_set_settings,
3572 .get_link = ethtool_op_get_link,
3573 .get_msglevel = rtl8152_get_msglevel,
3574 .set_msglevel = rtl8152_set_msglevel,
3575 .get_wol = rtl8152_get_wol,
3576 .set_wol = rtl8152_set_wol,
3577 .get_strings = rtl8152_get_strings,
3578 .get_sset_count = rtl8152_get_sset_count,
3579 .get_ethtool_stats = rtl8152_get_ethtool_stats,
3580 .get_eee = rtl_ethtool_get_eee,
3581 .set_eee = rtl_ethtool_set_eee,
3582 };
3583
3584 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
3585 {
3586 struct r8152 *tp = netdev_priv(netdev);
3587 struct mii_ioctl_data *data = if_mii(rq);
3588 int res;
3589
3590 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3591 return -ENODEV;
3592
3593 res = usb_autopm_get_interface(tp->intf);
3594 if (res < 0)
3595 goto out;
3596
3597 switch (cmd) {
3598 case SIOCGMIIPHY:
3599 data->phy_id = R8152_PHY_ID; /* Internal PHY */
3600 break;
3601
3602 case SIOCGMIIREG:
3603 mutex_lock(&tp->control);
3604 data->val_out = r8152_mdio_read(tp, data->reg_num);
3605 mutex_unlock(&tp->control);
3606 break;
3607
3608 case SIOCSMIIREG:
3609 if (!capable(CAP_NET_ADMIN)) {
3610 res = -EPERM;
3611 break;
3612 }
3613 mutex_lock(&tp->control);
3614 r8152_mdio_write(tp, data->reg_num, data->val_in);
3615 mutex_unlock(&tp->control);
3616 break;
3617
3618 default:
3619 res = -EOPNOTSUPP;
3620 }
3621
3622 usb_autopm_put_interface(tp->intf);
3623
3624 out:
3625 return res;
3626 }
3627
3628 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
3629 {
3630 struct r8152 *tp = netdev_priv(dev);
3631
3632 switch (tp->version) {
3633 case RTL_VER_01:
3634 case RTL_VER_02:
3635 return eth_change_mtu(dev, new_mtu);
3636 default:
3637 break;
3638 }
3639
3640 if (new_mtu < 68 || new_mtu > RTL8153_MAX_MTU)
3641 return -EINVAL;
3642
3643 dev->mtu = new_mtu;
3644
3645 return 0;
3646 }
3647
3648 static const struct net_device_ops rtl8152_netdev_ops = {
3649 .ndo_open = rtl8152_open,
3650 .ndo_stop = rtl8152_close,
3651 .ndo_do_ioctl = rtl8152_ioctl,
3652 .ndo_start_xmit = rtl8152_start_xmit,
3653 .ndo_tx_timeout = rtl8152_tx_timeout,
3654 .ndo_set_features = rtl8152_set_features,
3655 .ndo_set_rx_mode = rtl8152_set_rx_mode,
3656 .ndo_set_mac_address = rtl8152_set_mac_address,
3657 .ndo_change_mtu = rtl8152_change_mtu,
3658 .ndo_validate_addr = eth_validate_addr,
3659 };
3660
3661 static void r8152b_get_version(struct r8152 *tp)
3662 {
3663 u32 ocp_data;
3664 u16 version;
3665
3666 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
3667 version = (u16)(ocp_data & VERSION_MASK);
3668
3669 switch (version) {
3670 case 0x4c00:
3671 tp->version = RTL_VER_01;
3672 break;
3673 case 0x4c10:
3674 tp->version = RTL_VER_02;
3675 break;
3676 case 0x5c00:
3677 tp->version = RTL_VER_03;
3678 tp->mii.supports_gmii = 1;
3679 break;
3680 case 0x5c10:
3681 tp->version = RTL_VER_04;
3682 tp->mii.supports_gmii = 1;
3683 break;
3684 case 0x5c20:
3685 tp->version = RTL_VER_05;
3686 tp->mii.supports_gmii = 1;
3687 break;
3688 default:
3689 netif_info(tp, probe, tp->netdev,
3690 "Unknown version 0x%04x\n", version);
3691 break;
3692 }
3693 }
3694
3695 static void rtl8152_unload(struct r8152 *tp)
3696 {
3697 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3698 return;
3699
3700 if (tp->version != RTL_VER_01)
3701 r8152_power_cut_en(tp, true);
3702 }
3703
3704 static void rtl8153_unload(struct r8152 *tp)
3705 {
3706 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3707 return;
3708
3709 r8153_power_cut_en(tp, false);
3710 }
3711
3712 static int rtl_ops_init(struct r8152 *tp, const struct usb_device_id *id)
3713 {
3714 struct rtl_ops *ops = &tp->rtl_ops;
3715 int ret = -ENODEV;
3716
3717 switch (id->idVendor) {
3718 case VENDOR_ID_REALTEK:
3719 switch (id->idProduct) {
3720 case PRODUCT_ID_RTL8152:
3721 ops->init = r8152b_init;
3722 ops->enable = rtl8152_enable;
3723 ops->disable = rtl8152_disable;
3724 ops->up = rtl8152_up;
3725 ops->down = rtl8152_down;
3726 ops->unload = rtl8152_unload;
3727 ops->eee_get = r8152_get_eee;
3728 ops->eee_set = r8152_set_eee;
3729 ret = 0;
3730 break;
3731 case PRODUCT_ID_RTL8153:
3732 ops->init = r8153_init;
3733 ops->enable = rtl8153_enable;
3734 ops->disable = rtl8153_disable;
3735 ops->up = rtl8153_up;
3736 ops->down = rtl8153_down;
3737 ops->unload = rtl8153_unload;
3738 ops->eee_get = r8153_get_eee;
3739 ops->eee_set = r8153_set_eee;
3740 ret = 0;
3741 break;
3742 default:
3743 break;
3744 }
3745 break;
3746
3747 case VENDOR_ID_SAMSUNG:
3748 switch (id->idProduct) {
3749 case PRODUCT_ID_SAMSUNG:
3750 ops->init = r8153_init;
3751 ops->enable = rtl8153_enable;
3752 ops->disable = rtl8153_disable;
3753 ops->up = rtl8153_up;
3754 ops->down = rtl8153_down;
3755 ops->unload = rtl8153_unload;
3756 ops->eee_get = r8153_get_eee;
3757 ops->eee_set = r8153_set_eee;
3758 ret = 0;
3759 break;
3760 default:
3761 break;
3762 }
3763 break;
3764
3765 default:
3766 break;
3767 }
3768
3769 if (ret)
3770 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
3771
3772 return ret;
3773 }
3774
3775 static int rtl8152_probe(struct usb_interface *intf,
3776 const struct usb_device_id *id)
3777 {
3778 struct usb_device *udev = interface_to_usbdev(intf);
3779 struct r8152 *tp;
3780 struct net_device *netdev;
3781 int ret;
3782
3783 if (udev->actconfig->desc.bConfigurationValue != 1) {
3784 usb_driver_set_configuration(udev, 1);
3785 return -ENODEV;
3786 }
3787
3788 usb_reset_device(udev);
3789 netdev = alloc_etherdev(sizeof(struct r8152));
3790 if (!netdev) {
3791 dev_err(&intf->dev, "Out of memory\n");
3792 return -ENOMEM;
3793 }
3794
3795 SET_NETDEV_DEV(netdev, &intf->dev);
3796 tp = netdev_priv(netdev);
3797 tp->msg_enable = 0x7FFF;
3798
3799 tp->udev = udev;
3800 tp->netdev = netdev;
3801 tp->intf = intf;
3802
3803 ret = rtl_ops_init(tp, id);
3804 if (ret)
3805 goto out;
3806
3807 tasklet_init(&tp->tl, bottom_half, (unsigned long)tp);
3808 mutex_init(&tp->control);
3809 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
3810
3811 netdev->netdev_ops = &rtl8152_netdev_ops;
3812 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
3813
3814 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
3815 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
3816 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
3817 NETIF_F_HW_VLAN_CTAG_TX;
3818 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
3819 NETIF_F_TSO | NETIF_F_FRAGLIST |
3820 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
3821 NETIF_F_HW_VLAN_CTAG_RX |
3822 NETIF_F_HW_VLAN_CTAG_TX;
3823 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3824 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
3825 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
3826
3827 netdev->ethtool_ops = &ops;
3828 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
3829
3830 tp->mii.dev = netdev;
3831 tp->mii.mdio_read = read_mii_word;
3832 tp->mii.mdio_write = write_mii_word;
3833 tp->mii.phy_id_mask = 0x3f;
3834 tp->mii.reg_num_mask = 0x1f;
3835 tp->mii.phy_id = R8152_PHY_ID;
3836 tp->mii.supports_gmii = 0;
3837
3838 intf->needs_remote_wakeup = 1;
3839
3840 r8152b_get_version(tp);
3841 tp->rtl_ops.init(tp);
3842 set_ethernet_addr(tp);
3843
3844 usb_set_intfdata(intf, tp);
3845
3846 ret = register_netdev(netdev);
3847 if (ret != 0) {
3848 netif_err(tp, probe, netdev, "couldn't register the device\n");
3849 goto out1;
3850 }
3851
3852 tp->saved_wolopts = __rtl_get_wol(tp);
3853 if (tp->saved_wolopts)
3854 device_set_wakeup_enable(&udev->dev, true);
3855 else
3856 device_set_wakeup_enable(&udev->dev, false);
3857
3858 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
3859
3860 return 0;
3861
3862 out1:
3863 usb_set_intfdata(intf, NULL);
3864 out:
3865 free_netdev(netdev);
3866 return ret;
3867 }
3868
3869 static void rtl8152_disconnect(struct usb_interface *intf)
3870 {
3871 struct r8152 *tp = usb_get_intfdata(intf);
3872
3873 usb_set_intfdata(intf, NULL);
3874 if (tp) {
3875 struct usb_device *udev = tp->udev;
3876
3877 if (udev->state == USB_STATE_NOTATTACHED)
3878 set_bit(RTL8152_UNPLUG, &tp->flags);
3879
3880 tasklet_kill(&tp->tl);
3881 unregister_netdev(tp->netdev);
3882 tp->rtl_ops.unload(tp);
3883 free_netdev(tp->netdev);
3884 }
3885 }
3886
3887 /* table of devices that work with this driver */
3888 static struct usb_device_id rtl8152_table[] = {
3889 {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8152)},
3890 {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8153)},
3891 {USB_DEVICE(VENDOR_ID_SAMSUNG, PRODUCT_ID_SAMSUNG)},
3892 {}
3893 };
3894
3895 MODULE_DEVICE_TABLE(usb, rtl8152_table);
3896
3897 static struct usb_driver rtl8152_driver = {
3898 .name = MODULENAME,
3899 .id_table = rtl8152_table,
3900 .probe = rtl8152_probe,
3901 .disconnect = rtl8152_disconnect,
3902 .suspend = rtl8152_suspend,
3903 .resume = rtl8152_resume,
3904 .reset_resume = rtl8152_resume,
3905 .supports_autosuspend = 1,
3906 .disable_hub_initiated_lpm = 1,
3907 };
3908
3909 module_usb_driver(rtl8152_driver);
3910
3911 MODULE_AUTHOR(DRIVER_AUTHOR);
3912 MODULE_DESCRIPTION(DRIVER_DESC);
3913 MODULE_LICENSE("GPL");
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