r8152: deal with the empty line and space
[deliverable/linux.git] / drivers / net / usb / r8152.c
1 /*
2 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * version 2 as published by the Free Software Foundation.
7 *
8 */
9
10 #include <linux/signal.h>
11 #include <linux/slab.h>
12 #include <linux/module.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/mii.h>
16 #include <linux/ethtool.h>
17 #include <linux/usb.h>
18 #include <linux/crc32.h>
19 #include <linux/if_vlan.h>
20 #include <linux/uaccess.h>
21 #include <linux/list.h>
22 #include <linux/ip.h>
23 #include <linux/ipv6.h>
24
25 /* Version Information */
26 #define DRIVER_VERSION "v1.05.0 (2014/02/18)"
27 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
28 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
29 #define MODULENAME "r8152"
30
31 #define R8152_PHY_ID 32
32
33 #define PLA_IDR 0xc000
34 #define PLA_RCR 0xc010
35 #define PLA_RMS 0xc016
36 #define PLA_RXFIFO_CTRL0 0xc0a0
37 #define PLA_RXFIFO_CTRL1 0xc0a4
38 #define PLA_RXFIFO_CTRL2 0xc0a8
39 #define PLA_FMC 0xc0b4
40 #define PLA_CFG_WOL 0xc0b6
41 #define PLA_TEREDO_CFG 0xc0bc
42 #define PLA_MAR 0xcd00
43 #define PLA_BACKUP 0xd000
44 #define PAL_BDC_CR 0xd1a0
45 #define PLA_TEREDO_TIMER 0xd2cc
46 #define PLA_REALWOW_TIMER 0xd2e8
47 #define PLA_LEDSEL 0xdd90
48 #define PLA_LED_FEATURE 0xdd92
49 #define PLA_PHYAR 0xde00
50 #define PLA_BOOT_CTRL 0xe004
51 #define PLA_GPHY_INTR_IMR 0xe022
52 #define PLA_EEE_CR 0xe040
53 #define PLA_EEEP_CR 0xe080
54 #define PLA_MAC_PWR_CTRL 0xe0c0
55 #define PLA_MAC_PWR_CTRL2 0xe0ca
56 #define PLA_MAC_PWR_CTRL3 0xe0cc
57 #define PLA_MAC_PWR_CTRL4 0xe0ce
58 #define PLA_WDT6_CTRL 0xe428
59 #define PLA_TCR0 0xe610
60 #define PLA_TCR1 0xe612
61 #define PLA_TXFIFO_CTRL 0xe618
62 #define PLA_RSTTELLY 0xe800
63 #define PLA_CR 0xe813
64 #define PLA_CRWECR 0xe81c
65 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
66 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
67 #define PLA_CONFIG5 0xe822
68 #define PLA_PHY_PWR 0xe84c
69 #define PLA_OOB_CTRL 0xe84f
70 #define PLA_CPCR 0xe854
71 #define PLA_MISC_0 0xe858
72 #define PLA_MISC_1 0xe85a
73 #define PLA_OCP_GPHY_BASE 0xe86c
74 #define PLA_TELLYCNT 0xe890
75 #define PLA_SFF_STS_7 0xe8de
76 #define PLA_PHYSTATUS 0xe908
77 #define PLA_BP_BA 0xfc26
78 #define PLA_BP_0 0xfc28
79 #define PLA_BP_1 0xfc2a
80 #define PLA_BP_2 0xfc2c
81 #define PLA_BP_3 0xfc2e
82 #define PLA_BP_4 0xfc30
83 #define PLA_BP_5 0xfc32
84 #define PLA_BP_6 0xfc34
85 #define PLA_BP_7 0xfc36
86 #define PLA_BP_EN 0xfc38
87
88 #define USB_U2P3_CTRL 0xb460
89 #define USB_DEV_STAT 0xb808
90 #define USB_USB_CTRL 0xd406
91 #define USB_PHY_CTRL 0xd408
92 #define USB_TX_AGG 0xd40a
93 #define USB_RX_BUF_TH 0xd40c
94 #define USB_USB_TIMER 0xd428
95 #define USB_RX_EARLY_AGG 0xd42c
96 #define USB_PM_CTRL_STATUS 0xd432
97 #define USB_TX_DMA 0xd434
98 #define USB_TOLERANCE 0xd490
99 #define USB_LPM_CTRL 0xd41a
100 #define USB_UPS_CTRL 0xd800
101 #define USB_MISC_0 0xd81a
102 #define USB_POWER_CUT 0xd80a
103 #define USB_AFE_CTRL2 0xd824
104 #define USB_WDT11_CTRL 0xe43c
105 #define USB_BP_BA 0xfc26
106 #define USB_BP_0 0xfc28
107 #define USB_BP_1 0xfc2a
108 #define USB_BP_2 0xfc2c
109 #define USB_BP_3 0xfc2e
110 #define USB_BP_4 0xfc30
111 #define USB_BP_5 0xfc32
112 #define USB_BP_6 0xfc34
113 #define USB_BP_7 0xfc36
114 #define USB_BP_EN 0xfc38
115
116 /* OCP Registers */
117 #define OCP_ALDPS_CONFIG 0x2010
118 #define OCP_EEE_CONFIG1 0x2080
119 #define OCP_EEE_CONFIG2 0x2092
120 #define OCP_EEE_CONFIG3 0x2094
121 #define OCP_BASE_MII 0xa400
122 #define OCP_EEE_AR 0xa41a
123 #define OCP_EEE_DATA 0xa41c
124 #define OCP_PHY_STATUS 0xa420
125 #define OCP_POWER_CFG 0xa430
126 #define OCP_EEE_CFG 0xa432
127 #define OCP_SRAM_ADDR 0xa436
128 #define OCP_SRAM_DATA 0xa438
129 #define OCP_DOWN_SPEED 0xa442
130 #define OCP_EEE_CFG2 0xa5d0
131 #define OCP_ADC_CFG 0xbc06
132
133 /* SRAM Register */
134 #define SRAM_LPF_CFG 0x8012
135 #define SRAM_10M_AMP1 0x8080
136 #define SRAM_10M_AMP2 0x8082
137 #define SRAM_IMPEDANCE 0x8084
138
139 /* PLA_RCR */
140 #define RCR_AAP 0x00000001
141 #define RCR_APM 0x00000002
142 #define RCR_AM 0x00000004
143 #define RCR_AB 0x00000008
144 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
145
146 /* PLA_RXFIFO_CTRL0 */
147 #define RXFIFO_THR1_NORMAL 0x00080002
148 #define RXFIFO_THR1_OOB 0x01800003
149
150 /* PLA_RXFIFO_CTRL1 */
151 #define RXFIFO_THR2_FULL 0x00000060
152 #define RXFIFO_THR2_HIGH 0x00000038
153 #define RXFIFO_THR2_OOB 0x0000004a
154 #define RXFIFO_THR2_NORMAL 0x00a0
155
156 /* PLA_RXFIFO_CTRL2 */
157 #define RXFIFO_THR3_FULL 0x00000078
158 #define RXFIFO_THR3_HIGH 0x00000048
159 #define RXFIFO_THR3_OOB 0x0000005a
160 #define RXFIFO_THR3_NORMAL 0x0110
161
162 /* PLA_TXFIFO_CTRL */
163 #define TXFIFO_THR_NORMAL 0x00400008
164 #define TXFIFO_THR_NORMAL2 0x01000008
165
166 /* PLA_FMC */
167 #define FMC_FCR_MCU_EN 0x0001
168
169 /* PLA_EEEP_CR */
170 #define EEEP_CR_EEEP_TX 0x0002
171
172 /* PLA_WDT6_CTRL */
173 #define WDT6_SET_MODE 0x0010
174
175 /* PLA_TCR0 */
176 #define TCR0_TX_EMPTY 0x0800
177 #define TCR0_AUTO_FIFO 0x0080
178
179 /* PLA_TCR1 */
180 #define VERSION_MASK 0x7cf0
181
182 /* PLA_CR */
183 #define CR_RST 0x10
184 #define CR_RE 0x08
185 #define CR_TE 0x04
186
187 /* PLA_CRWECR */
188 #define CRWECR_NORAML 0x00
189 #define CRWECR_CONFIG 0xc0
190
191 /* PLA_OOB_CTRL */
192 #define NOW_IS_OOB 0x80
193 #define TXFIFO_EMPTY 0x20
194 #define RXFIFO_EMPTY 0x10
195 #define LINK_LIST_READY 0x02
196 #define DIS_MCU_CLROOB 0x01
197 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
198
199 /* PLA_MISC_1 */
200 #define RXDY_GATED_EN 0x0008
201
202 /* PLA_SFF_STS_7 */
203 #define RE_INIT_LL 0x8000
204 #define MCU_BORW_EN 0x4000
205
206 /* PLA_CPCR */
207 #define CPCR_RX_VLAN 0x0040
208
209 /* PLA_CFG_WOL */
210 #define MAGIC_EN 0x0001
211
212 /* PLA_TEREDO_CFG */
213 #define TEREDO_SEL 0x8000
214 #define TEREDO_WAKE_MASK 0x7f00
215 #define TEREDO_RS_EVENT_MASK 0x00fe
216 #define OOB_TEREDO_EN 0x0001
217
218 /* PAL_BDC_CR */
219 #define ALDPS_PROXY_MODE 0x0001
220
221 /* PLA_CONFIG34 */
222 #define LINK_ON_WAKE_EN 0x0010
223 #define LINK_OFF_WAKE_EN 0x0008
224
225 /* PLA_CONFIG5 */
226 #define BWF_EN 0x0040
227 #define MWF_EN 0x0020
228 #define UWF_EN 0x0010
229 #define LAN_WAKE_EN 0x0002
230
231 /* PLA_LED_FEATURE */
232 #define LED_MODE_MASK 0x0700
233
234 /* PLA_PHY_PWR */
235 #define TX_10M_IDLE_EN 0x0080
236 #define PFM_PWM_SWITCH 0x0040
237
238 /* PLA_MAC_PWR_CTRL */
239 #define D3_CLK_GATED_EN 0x00004000
240 #define MCU_CLK_RATIO 0x07010f07
241 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
242 #define ALDPS_SPDWN_RATIO 0x0f87
243
244 /* PLA_MAC_PWR_CTRL2 */
245 #define EEE_SPDWN_RATIO 0x8007
246
247 /* PLA_MAC_PWR_CTRL3 */
248 #define PKT_AVAIL_SPDWN_EN 0x0100
249 #define SUSPEND_SPDWN_EN 0x0004
250 #define U1U2_SPDWN_EN 0x0002
251 #define L1_SPDWN_EN 0x0001
252
253 /* PLA_MAC_PWR_CTRL4 */
254 #define PWRSAVE_SPDWN_EN 0x1000
255 #define RXDV_SPDWN_EN 0x0800
256 #define TX10MIDLE_EN 0x0100
257 #define TP100_SPDWN_EN 0x0020
258 #define TP500_SPDWN_EN 0x0010
259 #define TP1000_SPDWN_EN 0x0008
260 #define EEE_SPDWN_EN 0x0001
261
262 /* PLA_GPHY_INTR_IMR */
263 #define GPHY_STS_MSK 0x0001
264 #define SPEED_DOWN_MSK 0x0002
265 #define SPDWN_RXDV_MSK 0x0004
266 #define SPDWN_LINKCHG_MSK 0x0008
267
268 /* PLA_PHYAR */
269 #define PHYAR_FLAG 0x80000000
270
271 /* PLA_EEE_CR */
272 #define EEE_RX_EN 0x0001
273 #define EEE_TX_EN 0x0002
274
275 /* PLA_BOOT_CTRL */
276 #define AUTOLOAD_DONE 0x0002
277
278 /* USB_DEV_STAT */
279 #define STAT_SPEED_MASK 0x0006
280 #define STAT_SPEED_HIGH 0x0000
281 #define STAT_SPEED_FULL 0x0001
282
283 /* USB_TX_AGG */
284 #define TX_AGG_MAX_THRESHOLD 0x03
285
286 /* USB_RX_BUF_TH */
287 #define RX_THR_SUPPER 0x0c350180
288 #define RX_THR_HIGH 0x7a120180
289 #define RX_THR_SLOW 0xffff0180
290
291 /* USB_TX_DMA */
292 #define TEST_MODE_DISABLE 0x00000001
293 #define TX_SIZE_ADJUST1 0x00000100
294
295 /* USB_UPS_CTRL */
296 #define POWER_CUT 0x0100
297
298 /* USB_PM_CTRL_STATUS */
299 #define RESUME_INDICATE 0x0001
300
301 /* USB_USB_CTRL */
302 #define RX_AGG_DISABLE 0x0010
303
304 /* USB_U2P3_CTRL */
305 #define U2P3_ENABLE 0x0001
306
307 /* USB_POWER_CUT */
308 #define PWR_EN 0x0001
309 #define PHASE2_EN 0x0008
310
311 /* USB_MISC_0 */
312 #define PCUT_STATUS 0x0001
313
314 /* USB_RX_EARLY_AGG */
315 #define EARLY_AGG_SUPPER 0x0e832981
316 #define EARLY_AGG_HIGH 0x0e837a12
317 #define EARLY_AGG_SLOW 0x0e83ffff
318
319 /* USB_WDT11_CTRL */
320 #define TIMER11_EN 0x0001
321
322 /* USB_LPM_CTRL */
323 #define LPM_TIMER_MASK 0x0c
324 #define LPM_TIMER_500MS 0x04 /* 500 ms */
325 #define LPM_TIMER_500US 0x0c /* 500 us */
326
327 /* USB_AFE_CTRL2 */
328 #define SEN_VAL_MASK 0xf800
329 #define SEN_VAL_NORMAL 0xa000
330 #define SEL_RXIDLE 0x0100
331
332 /* OCP_ALDPS_CONFIG */
333 #define ENPWRSAVE 0x8000
334 #define ENPDNPS 0x0200
335 #define LINKENA 0x0100
336 #define DIS_SDSAVE 0x0010
337
338 /* OCP_PHY_STATUS */
339 #define PHY_STAT_MASK 0x0007
340 #define PHY_STAT_LAN_ON 3
341 #define PHY_STAT_PWRDN 5
342
343 /* OCP_POWER_CFG */
344 #define EEE_CLKDIV_EN 0x8000
345 #define EN_ALDPS 0x0004
346 #define EN_10M_PLLOFF 0x0001
347
348 /* OCP_EEE_CONFIG1 */
349 #define RG_TXLPI_MSK_HFDUP 0x8000
350 #define RG_MATCLR_EN 0x4000
351 #define EEE_10_CAP 0x2000
352 #define EEE_NWAY_EN 0x1000
353 #define TX_QUIET_EN 0x0200
354 #define RX_QUIET_EN 0x0100
355 #define SDRISETIME 0x0010 /* bit 4 ~ 6 */
356 #define RG_RXLPI_MSK_HFDUP 0x0008
357 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
358
359 /* OCP_EEE_CONFIG2 */
360 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
361 #define RG_DACQUIET_EN 0x0400
362 #define RG_LDVQUIET_EN 0x0200
363 #define RG_CKRSEL 0x0020
364 #define RG_EEEPRG_EN 0x0010
365
366 /* OCP_EEE_CONFIG3 */
367 #define FST_SNR_EYE_R 0x1500 /* bit 7 ~ 15 */
368 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
369 #define MSK_PH 0x0006 /* bit 0 ~ 3 */
370
371 /* OCP_EEE_AR */
372 /* bit[15:14] function */
373 #define FUN_ADDR 0x0000
374 #define FUN_DATA 0x4000
375 /* bit[4:0] device addr */
376 #define DEVICE_ADDR 0x0007
377
378 /* OCP_EEE_DATA */
379 #define EEE_ADDR 0x003C
380 #define EEE_DATA 0x0002
381
382 /* OCP_EEE_CFG */
383 #define CTAP_SHORT_EN 0x0040
384 #define EEE10_EN 0x0010
385
386 /* OCP_DOWN_SPEED */
387 #define EN_10M_BGOFF 0x0080
388
389 /* OCP_EEE_CFG2 */
390 #define MY1000_EEE 0x0004
391 #define MY100_EEE 0x0002
392
393 /* OCP_ADC_CFG */
394 #define CKADSEL_L 0x0100
395 #define ADC_EN 0x0080
396 #define EN_EMI_L 0x0040
397
398 /* SRAM_LPF_CFG */
399 #define LPF_AUTO_TUNE 0x8000
400
401 /* SRAM_10M_AMP1 */
402 #define GDAC_IB_UPALL 0x0008
403
404 /* SRAM_10M_AMP2 */
405 #define AMP_DN 0x0200
406
407 /* SRAM_IMPEDANCE */
408 #define RX_DRIVING_MASK 0x6000
409
410 enum rtl_register_content {
411 _1000bps = 0x10,
412 _100bps = 0x08,
413 _10bps = 0x04,
414 LINK_STATUS = 0x02,
415 FULL_DUP = 0x01,
416 };
417
418 #define RTL8152_MAX_TX 10
419 #define RTL8152_MAX_RX 10
420 #define INTBUFSIZE 2
421 #define CRC_SIZE 4
422 #define TX_ALIGN 4
423 #define RX_ALIGN 8
424
425 #define INTR_LINK 0x0004
426
427 #define RTL8152_REQT_READ 0xc0
428 #define RTL8152_REQT_WRITE 0x40
429 #define RTL8152_REQ_GET_REGS 0x05
430 #define RTL8152_REQ_SET_REGS 0x05
431
432 #define BYTE_EN_DWORD 0xff
433 #define BYTE_EN_WORD 0x33
434 #define BYTE_EN_BYTE 0x11
435 #define BYTE_EN_SIX_BYTES 0x3f
436 #define BYTE_EN_START_MASK 0x0f
437 #define BYTE_EN_END_MASK 0xf0
438
439 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
440 #define RTL8152_TX_TIMEOUT (HZ)
441
442 /* rtl8152 flags */
443 enum rtl8152_flags {
444 RTL8152_UNPLUG = 0,
445 RTL8152_SET_RX_MODE,
446 WORK_ENABLE,
447 RTL8152_LINK_CHG,
448 SELECTIVE_SUSPEND,
449 PHY_RESET,
450 };
451
452 /* Define these values to match your device */
453 #define VENDOR_ID_REALTEK 0x0bda
454 #define PRODUCT_ID_RTL8152 0x8152
455 #define PRODUCT_ID_RTL8153 0x8153
456
457 #define VENDOR_ID_SAMSUNG 0x04e8
458 #define PRODUCT_ID_SAMSUNG 0xa101
459
460 #define MCU_TYPE_PLA 0x0100
461 #define MCU_TYPE_USB 0x0000
462
463 #define REALTEK_USB_DEVICE(vend, prod) \
464 USB_DEVICE_INTERFACE_CLASS(vend, prod, USB_CLASS_VENDOR_SPEC)
465
466 struct rx_desc {
467 __le32 opts1;
468 #define RX_LEN_MASK 0x7fff
469 __le32 opts2;
470 __le32 opts3;
471 __le32 opts4;
472 __le32 opts5;
473 __le32 opts6;
474 };
475
476 struct tx_desc {
477 __le32 opts1;
478 #define TX_FS (1 << 31) /* First segment of a packet */
479 #define TX_LS (1 << 30) /* Final segment of a packet */
480 #define TX_LEN_MASK 0x3ffff
481
482 __le32 opts2;
483 #define UDP_CS (1 << 31) /* Calculate UDP/IP checksum */
484 #define TCP_CS (1 << 30) /* Calculate TCP/IP checksum */
485 #define IPV4_CS (1 << 29) /* Calculate IPv4 checksum */
486 #define IPV6_CS (1 << 28) /* Calculate IPv6 checksum */
487 };
488
489 struct r8152;
490
491 struct rx_agg {
492 struct list_head list;
493 struct urb *urb;
494 struct r8152 *context;
495 void *buffer;
496 void *head;
497 };
498
499 struct tx_agg {
500 struct list_head list;
501 struct urb *urb;
502 struct r8152 *context;
503 void *buffer;
504 void *head;
505 u32 skb_num;
506 u32 skb_len;
507 };
508
509 struct r8152 {
510 unsigned long flags;
511 struct usb_device *udev;
512 struct tasklet_struct tl;
513 struct usb_interface *intf;
514 struct net_device *netdev;
515 struct urb *intr_urb;
516 struct tx_agg tx_info[RTL8152_MAX_TX];
517 struct rx_agg rx_info[RTL8152_MAX_RX];
518 struct list_head rx_done, tx_free;
519 struct sk_buff_head tx_queue;
520 spinlock_t rx_lock, tx_lock;
521 struct delayed_work schedule;
522 struct mii_if_info mii;
523
524 struct rtl_ops {
525 void (*init)(struct r8152 *);
526 int (*enable)(struct r8152 *);
527 void (*disable)(struct r8152 *);
528 void (*up)(struct r8152 *);
529 void (*down)(struct r8152 *);
530 void (*unload)(struct r8152 *);
531 } rtl_ops;
532
533 int intr_interval;
534 u32 saved_wolopts;
535 u32 msg_enable;
536 u32 tx_qlen;
537 u16 ocp_base;
538 u8 *intr_buff;
539 u8 version;
540 u8 speed;
541 };
542
543 enum rtl_version {
544 RTL_VER_UNKNOWN = 0,
545 RTL_VER_01,
546 RTL_VER_02,
547 RTL_VER_03,
548 RTL_VER_04,
549 RTL_VER_05,
550 RTL_VER_MAX
551 };
552
553 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
554 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
555 */
556 static const int multicast_filter_limit = 32;
557 static unsigned int rx_buf_sz = 16384;
558
559 static
560 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
561 {
562 int ret;
563 void *tmp;
564
565 tmp = kmalloc(size, GFP_KERNEL);
566 if (!tmp)
567 return -ENOMEM;
568
569 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
570 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
571 value, index, tmp, size, 500);
572
573 memcpy(data, tmp, size);
574 kfree(tmp);
575
576 return ret;
577 }
578
579 static
580 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
581 {
582 int ret;
583 void *tmp;
584
585 tmp = kmalloc(size, GFP_KERNEL);
586 if (!tmp)
587 return -ENOMEM;
588
589 memcpy(tmp, data, size);
590
591 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
592 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
593 value, index, tmp, size, 500);
594
595 kfree(tmp);
596
597 return ret;
598 }
599
600 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
601 void *data, u16 type)
602 {
603 u16 limit = 64;
604 int ret = 0;
605
606 if (test_bit(RTL8152_UNPLUG, &tp->flags))
607 return -ENODEV;
608
609 /* both size and indix must be 4 bytes align */
610 if ((size & 3) || !size || (index & 3) || !data)
611 return -EPERM;
612
613 if ((u32)index + (u32)size > 0xffff)
614 return -EPERM;
615
616 while (size) {
617 if (size > limit) {
618 ret = get_registers(tp, index, type, limit, data);
619 if (ret < 0)
620 break;
621
622 index += limit;
623 data += limit;
624 size -= limit;
625 } else {
626 ret = get_registers(tp, index, type, size, data);
627 if (ret < 0)
628 break;
629
630 index += size;
631 data += size;
632 size = 0;
633 break;
634 }
635 }
636
637 return ret;
638 }
639
640 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
641 u16 size, void *data, u16 type)
642 {
643 int ret;
644 u16 byteen_start, byteen_end, byen;
645 u16 limit = 512;
646
647 if (test_bit(RTL8152_UNPLUG, &tp->flags))
648 return -ENODEV;
649
650 /* both size and indix must be 4 bytes align */
651 if ((size & 3) || !size || (index & 3) || !data)
652 return -EPERM;
653
654 if ((u32)index + (u32)size > 0xffff)
655 return -EPERM;
656
657 byteen_start = byteen & BYTE_EN_START_MASK;
658 byteen_end = byteen & BYTE_EN_END_MASK;
659
660 byen = byteen_start | (byteen_start << 4);
661 ret = set_registers(tp, index, type | byen, 4, data);
662 if (ret < 0)
663 goto error1;
664
665 index += 4;
666 data += 4;
667 size -= 4;
668
669 if (size) {
670 size -= 4;
671
672 while (size) {
673 if (size > limit) {
674 ret = set_registers(tp, index,
675 type | BYTE_EN_DWORD,
676 limit, data);
677 if (ret < 0)
678 goto error1;
679
680 index += limit;
681 data += limit;
682 size -= limit;
683 } else {
684 ret = set_registers(tp, index,
685 type | BYTE_EN_DWORD,
686 size, data);
687 if (ret < 0)
688 goto error1;
689
690 index += size;
691 data += size;
692 size = 0;
693 break;
694 }
695 }
696
697 byen = byteen_end | (byteen_end >> 4);
698 ret = set_registers(tp, index, type | byen, 4, data);
699 if (ret < 0)
700 goto error1;
701 }
702
703 error1:
704 return ret;
705 }
706
707 static inline
708 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
709 {
710 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
711 }
712
713 static inline
714 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
715 {
716 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
717 }
718
719 static inline
720 int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
721 {
722 return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
723 }
724
725 static inline
726 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
727 {
728 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
729 }
730
731 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
732 {
733 __le32 data;
734
735 generic_ocp_read(tp, index, sizeof(data), &data, type);
736
737 return __le32_to_cpu(data);
738 }
739
740 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
741 {
742 __le32 tmp = __cpu_to_le32(data);
743
744 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
745 }
746
747 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
748 {
749 u32 data;
750 __le32 tmp;
751 u8 shift = index & 2;
752
753 index &= ~3;
754
755 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
756
757 data = __le32_to_cpu(tmp);
758 data >>= (shift * 8);
759 data &= 0xffff;
760
761 return (u16)data;
762 }
763
764 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
765 {
766 u32 mask = 0xffff;
767 __le32 tmp;
768 u16 byen = BYTE_EN_WORD;
769 u8 shift = index & 2;
770
771 data &= mask;
772
773 if (index & 2) {
774 byen <<= shift;
775 mask <<= (shift * 8);
776 data <<= (shift * 8);
777 index &= ~3;
778 }
779
780 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
781
782 data |= __le32_to_cpu(tmp) & ~mask;
783 tmp = __cpu_to_le32(data);
784
785 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
786 }
787
788 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
789 {
790 u32 data;
791 __le32 tmp;
792 u8 shift = index & 3;
793
794 index &= ~3;
795
796 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
797
798 data = __le32_to_cpu(tmp);
799 data >>= (shift * 8);
800 data &= 0xff;
801
802 return (u8)data;
803 }
804
805 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
806 {
807 u32 mask = 0xff;
808 __le32 tmp;
809 u16 byen = BYTE_EN_BYTE;
810 u8 shift = index & 3;
811
812 data &= mask;
813
814 if (index & 3) {
815 byen <<= shift;
816 mask <<= (shift * 8);
817 data <<= (shift * 8);
818 index &= ~3;
819 }
820
821 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
822
823 data |= __le32_to_cpu(tmp) & ~mask;
824 tmp = __cpu_to_le32(data);
825
826 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
827 }
828
829 static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
830 {
831 u16 ocp_base, ocp_index;
832
833 ocp_base = addr & 0xf000;
834 if (ocp_base != tp->ocp_base) {
835 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
836 tp->ocp_base = ocp_base;
837 }
838
839 ocp_index = (addr & 0x0fff) | 0xb000;
840 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
841 }
842
843 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
844 {
845 u16 ocp_base, ocp_index;
846
847 ocp_base = addr & 0xf000;
848 if (ocp_base != tp->ocp_base) {
849 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
850 tp->ocp_base = ocp_base;
851 }
852
853 ocp_index = (addr & 0x0fff) | 0xb000;
854 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
855 }
856
857 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
858 {
859 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
860 }
861
862 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
863 {
864 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
865 }
866
867 static void sram_write(struct r8152 *tp, u16 addr, u16 data)
868 {
869 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
870 ocp_reg_write(tp, OCP_SRAM_DATA, data);
871 }
872
873 static u16 sram_read(struct r8152 *tp, u16 addr)
874 {
875 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
876 return ocp_reg_read(tp, OCP_SRAM_DATA);
877 }
878
879 static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
880 {
881 struct r8152 *tp = netdev_priv(netdev);
882 int ret;
883
884 if (phy_id != R8152_PHY_ID)
885 return -EINVAL;
886
887 ret = usb_autopm_get_interface(tp->intf);
888 if (ret < 0)
889 goto out;
890
891 ret = r8152_mdio_read(tp, reg);
892
893 usb_autopm_put_interface(tp->intf);
894
895 out:
896 return ret;
897 }
898
899 static
900 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
901 {
902 struct r8152 *tp = netdev_priv(netdev);
903
904 if (phy_id != R8152_PHY_ID)
905 return;
906
907 if (usb_autopm_get_interface(tp->intf) < 0)
908 return;
909
910 r8152_mdio_write(tp, reg, val);
911
912 usb_autopm_put_interface(tp->intf);
913 }
914
915 static
916 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
917
918 static inline void set_ethernet_addr(struct r8152 *tp)
919 {
920 struct net_device *dev = tp->netdev;
921 int ret;
922 u8 node_id[8] = {0};
923
924 if (tp->version == RTL_VER_01)
925 ret = pla_ocp_read(tp, PLA_IDR, sizeof(node_id), node_id);
926 else
927 ret = pla_ocp_read(tp, PLA_BACKUP, sizeof(node_id), node_id);
928
929 if (ret < 0) {
930 netif_notice(tp, probe, dev, "inet addr fail\n");
931 } else {
932 if (tp->version != RTL_VER_01) {
933 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR,
934 CRWECR_CONFIG);
935 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES,
936 sizeof(node_id), node_id);
937 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR,
938 CRWECR_NORAML);
939 }
940
941 memcpy(dev->dev_addr, node_id, dev->addr_len);
942 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
943 }
944 }
945
946 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
947 {
948 struct r8152 *tp = netdev_priv(netdev);
949 struct sockaddr *addr = p;
950
951 if (!is_valid_ether_addr(addr->sa_data))
952 return -EADDRNOTAVAIL;
953
954 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
955
956 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
957 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
958 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
959
960 return 0;
961 }
962
963 static struct net_device_stats *rtl8152_get_stats(struct net_device *dev)
964 {
965 return &dev->stats;
966 }
967
968 static void read_bulk_callback(struct urb *urb)
969 {
970 struct net_device *netdev;
971 unsigned long flags;
972 int status = urb->status;
973 struct rx_agg *agg;
974 struct r8152 *tp;
975 int result;
976
977 agg = urb->context;
978 if (!agg)
979 return;
980
981 tp = agg->context;
982 if (!tp)
983 return;
984
985 if (test_bit(RTL8152_UNPLUG, &tp->flags))
986 return;
987
988 if (!test_bit(WORK_ENABLE, &tp->flags))
989 return;
990
991 netdev = tp->netdev;
992
993 /* When link down, the driver would cancel all bulks. */
994 /* This avoid the re-submitting bulk */
995 if (!netif_carrier_ok(netdev))
996 return;
997
998 usb_mark_last_busy(tp->udev);
999
1000 switch (status) {
1001 case 0:
1002 if (urb->actual_length < ETH_ZLEN)
1003 break;
1004
1005 spin_lock_irqsave(&tp->rx_lock, flags);
1006 list_add_tail(&agg->list, &tp->rx_done);
1007 spin_unlock_irqrestore(&tp->rx_lock, flags);
1008 tasklet_schedule(&tp->tl);
1009 return;
1010 case -ESHUTDOWN:
1011 set_bit(RTL8152_UNPLUG, &tp->flags);
1012 netif_device_detach(tp->netdev);
1013 return;
1014 case -ENOENT:
1015 return; /* the urb is in unlink state */
1016 case -ETIME:
1017 if (net_ratelimit())
1018 netdev_warn(netdev, "maybe reset is needed?\n");
1019 break;
1020 default:
1021 if (net_ratelimit())
1022 netdev_warn(netdev, "Rx status %d\n", status);
1023 break;
1024 }
1025
1026 result = r8152_submit_rx(tp, agg, GFP_ATOMIC);
1027 if (result == -ENODEV) {
1028 netif_device_detach(tp->netdev);
1029 } else if (result) {
1030 spin_lock_irqsave(&tp->rx_lock, flags);
1031 list_add_tail(&agg->list, &tp->rx_done);
1032 spin_unlock_irqrestore(&tp->rx_lock, flags);
1033 tasklet_schedule(&tp->tl);
1034 }
1035 }
1036
1037 static void write_bulk_callback(struct urb *urb)
1038 {
1039 struct net_device_stats *stats;
1040 unsigned long flags;
1041 struct tx_agg *agg;
1042 struct r8152 *tp;
1043 int status = urb->status;
1044
1045 agg = urb->context;
1046 if (!agg)
1047 return;
1048
1049 tp = agg->context;
1050 if (!tp)
1051 return;
1052
1053 stats = rtl8152_get_stats(tp->netdev);
1054 if (status) {
1055 if (net_ratelimit())
1056 netdev_warn(tp->netdev, "Tx status %d\n", status);
1057 stats->tx_errors += agg->skb_num;
1058 } else {
1059 stats->tx_packets += agg->skb_num;
1060 stats->tx_bytes += agg->skb_len;
1061 }
1062
1063 spin_lock_irqsave(&tp->tx_lock, flags);
1064 list_add_tail(&agg->list, &tp->tx_free);
1065 spin_unlock_irqrestore(&tp->tx_lock, flags);
1066
1067 usb_autopm_put_interface_async(tp->intf);
1068
1069 if (!netif_carrier_ok(tp->netdev))
1070 return;
1071
1072 if (!test_bit(WORK_ENABLE, &tp->flags))
1073 return;
1074
1075 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1076 return;
1077
1078 if (!skb_queue_empty(&tp->tx_queue))
1079 schedule_delayed_work(&tp->schedule, 0);
1080 }
1081
1082 static void intr_callback(struct urb *urb)
1083 {
1084 struct r8152 *tp;
1085 __le16 *d;
1086 int status = urb->status;
1087 int res;
1088
1089 tp = urb->context;
1090 if (!tp)
1091 return;
1092
1093 if (!test_bit(WORK_ENABLE, &tp->flags))
1094 return;
1095
1096 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1097 return;
1098
1099 switch (status) {
1100 case 0: /* success */
1101 break;
1102 case -ECONNRESET: /* unlink */
1103 case -ESHUTDOWN:
1104 netif_device_detach(tp->netdev);
1105 case -ENOENT:
1106 return;
1107 case -EOVERFLOW:
1108 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1109 goto resubmit;
1110 /* -EPIPE: should clear the halt */
1111 default:
1112 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1113 goto resubmit;
1114 }
1115
1116 d = urb->transfer_buffer;
1117 if (INTR_LINK & __le16_to_cpu(d[0])) {
1118 if (!(tp->speed & LINK_STATUS)) {
1119 set_bit(RTL8152_LINK_CHG, &tp->flags);
1120 schedule_delayed_work(&tp->schedule, 0);
1121 }
1122 } else {
1123 if (tp->speed & LINK_STATUS) {
1124 set_bit(RTL8152_LINK_CHG, &tp->flags);
1125 schedule_delayed_work(&tp->schedule, 0);
1126 }
1127 }
1128
1129 resubmit:
1130 res = usb_submit_urb(urb, GFP_ATOMIC);
1131 if (res == -ENODEV)
1132 netif_device_detach(tp->netdev);
1133 else if (res)
1134 netif_err(tp, intr, tp->netdev,
1135 "can't resubmit intr, status %d\n", res);
1136 }
1137
1138 static inline void *rx_agg_align(void *data)
1139 {
1140 return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1141 }
1142
1143 static inline void *tx_agg_align(void *data)
1144 {
1145 return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1146 }
1147
1148 static void free_all_mem(struct r8152 *tp)
1149 {
1150 int i;
1151
1152 for (i = 0; i < RTL8152_MAX_RX; i++) {
1153 usb_free_urb(tp->rx_info[i].urb);
1154 tp->rx_info[i].urb = NULL;
1155
1156 kfree(tp->rx_info[i].buffer);
1157 tp->rx_info[i].buffer = NULL;
1158 tp->rx_info[i].head = NULL;
1159 }
1160
1161 for (i = 0; i < RTL8152_MAX_TX; i++) {
1162 usb_free_urb(tp->tx_info[i].urb);
1163 tp->tx_info[i].urb = NULL;
1164
1165 kfree(tp->tx_info[i].buffer);
1166 tp->tx_info[i].buffer = NULL;
1167 tp->tx_info[i].head = NULL;
1168 }
1169
1170 usb_free_urb(tp->intr_urb);
1171 tp->intr_urb = NULL;
1172
1173 kfree(tp->intr_buff);
1174 tp->intr_buff = NULL;
1175 }
1176
1177 static int alloc_all_mem(struct r8152 *tp)
1178 {
1179 struct net_device *netdev = tp->netdev;
1180 struct usb_interface *intf = tp->intf;
1181 struct usb_host_interface *alt = intf->cur_altsetting;
1182 struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
1183 struct urb *urb;
1184 int node, i;
1185 u8 *buf;
1186
1187 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1188
1189 spin_lock_init(&tp->rx_lock);
1190 spin_lock_init(&tp->tx_lock);
1191 INIT_LIST_HEAD(&tp->rx_done);
1192 INIT_LIST_HEAD(&tp->tx_free);
1193 skb_queue_head_init(&tp->tx_queue);
1194
1195 for (i = 0; i < RTL8152_MAX_RX; i++) {
1196 buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
1197 if (!buf)
1198 goto err1;
1199
1200 if (buf != rx_agg_align(buf)) {
1201 kfree(buf);
1202 buf = kmalloc_node(rx_buf_sz + RX_ALIGN, GFP_KERNEL,
1203 node);
1204 if (!buf)
1205 goto err1;
1206 }
1207
1208 urb = usb_alloc_urb(0, GFP_KERNEL);
1209 if (!urb) {
1210 kfree(buf);
1211 goto err1;
1212 }
1213
1214 INIT_LIST_HEAD(&tp->rx_info[i].list);
1215 tp->rx_info[i].context = tp;
1216 tp->rx_info[i].urb = urb;
1217 tp->rx_info[i].buffer = buf;
1218 tp->rx_info[i].head = rx_agg_align(buf);
1219 }
1220
1221 for (i = 0; i < RTL8152_MAX_TX; i++) {
1222 buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
1223 if (!buf)
1224 goto err1;
1225
1226 if (buf != tx_agg_align(buf)) {
1227 kfree(buf);
1228 buf = kmalloc_node(rx_buf_sz + TX_ALIGN, GFP_KERNEL,
1229 node);
1230 if (!buf)
1231 goto err1;
1232 }
1233
1234 urb = usb_alloc_urb(0, GFP_KERNEL);
1235 if (!urb) {
1236 kfree(buf);
1237 goto err1;
1238 }
1239
1240 INIT_LIST_HEAD(&tp->tx_info[i].list);
1241 tp->tx_info[i].context = tp;
1242 tp->tx_info[i].urb = urb;
1243 tp->tx_info[i].buffer = buf;
1244 tp->tx_info[i].head = tx_agg_align(buf);
1245
1246 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1247 }
1248
1249 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1250 if (!tp->intr_urb)
1251 goto err1;
1252
1253 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1254 if (!tp->intr_buff)
1255 goto err1;
1256
1257 tp->intr_interval = (int)ep_intr->desc.bInterval;
1258 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
1259 tp->intr_buff, INTBUFSIZE, intr_callback,
1260 tp, tp->intr_interval);
1261
1262 return 0;
1263
1264 err1:
1265 free_all_mem(tp);
1266 return -ENOMEM;
1267 }
1268
1269 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1270 {
1271 struct tx_agg *agg = NULL;
1272 unsigned long flags;
1273
1274 spin_lock_irqsave(&tp->tx_lock, flags);
1275 if (!list_empty(&tp->tx_free)) {
1276 struct list_head *cursor;
1277
1278 cursor = tp->tx_free.next;
1279 list_del_init(cursor);
1280 agg = list_entry(cursor, struct tx_agg, list);
1281 }
1282 spin_unlock_irqrestore(&tp->tx_lock, flags);
1283
1284 return agg;
1285 }
1286
1287 static void
1288 r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, struct sk_buff *skb)
1289 {
1290 memset(desc, 0, sizeof(*desc));
1291
1292 desc->opts1 = cpu_to_le32((skb->len & TX_LEN_MASK) | TX_FS | TX_LS);
1293
1294 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1295 __be16 protocol;
1296 u8 ip_protocol;
1297 u32 opts2 = 0;
1298
1299 if (skb->protocol == htons(ETH_P_8021Q))
1300 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
1301 else
1302 protocol = skb->protocol;
1303
1304 switch (protocol) {
1305 case htons(ETH_P_IP):
1306 opts2 |= IPV4_CS;
1307 ip_protocol = ip_hdr(skb)->protocol;
1308 break;
1309
1310 case htons(ETH_P_IPV6):
1311 opts2 |= IPV6_CS;
1312 ip_protocol = ipv6_hdr(skb)->nexthdr;
1313 break;
1314
1315 default:
1316 ip_protocol = IPPROTO_RAW;
1317 break;
1318 }
1319
1320 if (ip_protocol == IPPROTO_TCP) {
1321 opts2 |= TCP_CS;
1322 opts2 |= (skb_transport_offset(skb) & 0x7fff) << 17;
1323 } else if (ip_protocol == IPPROTO_UDP) {
1324 opts2 |= UDP_CS;
1325 } else {
1326 WARN_ON_ONCE(1);
1327 }
1328
1329 desc->opts2 = cpu_to_le32(opts2);
1330 }
1331 }
1332
1333 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
1334 {
1335 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1336 unsigned long flags;
1337 int remain, ret;
1338 u8 *tx_data;
1339
1340 __skb_queue_head_init(&skb_head);
1341 spin_lock_irqsave(&tx_queue->lock, flags);
1342 skb_queue_splice_init(tx_queue, &skb_head);
1343 spin_unlock_irqrestore(&tx_queue->lock, flags);
1344
1345 tx_data = agg->head;
1346 agg->skb_num = agg->skb_len = 0;
1347 remain = rx_buf_sz;
1348
1349 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
1350 struct tx_desc *tx_desc;
1351 struct sk_buff *skb;
1352 unsigned int len;
1353
1354 skb = __skb_dequeue(&skb_head);
1355 if (!skb)
1356 break;
1357
1358 remain -= sizeof(*tx_desc);
1359 len = skb->len;
1360 if (remain < len) {
1361 __skb_queue_head(&skb_head, skb);
1362 break;
1363 }
1364
1365 tx_data = tx_agg_align(tx_data);
1366 tx_desc = (struct tx_desc *)tx_data;
1367 tx_data += sizeof(*tx_desc);
1368
1369 r8152_tx_csum(tp, tx_desc, skb);
1370 memcpy(tx_data, skb->data, len);
1371 agg->skb_num++;
1372 agg->skb_len += len;
1373 dev_kfree_skb_any(skb);
1374
1375 tx_data += len;
1376 remain = rx_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
1377 }
1378
1379 if (!skb_queue_empty(&skb_head)) {
1380 spin_lock_irqsave(&tx_queue->lock, flags);
1381 skb_queue_splice(&skb_head, tx_queue);
1382 spin_unlock_irqrestore(&tx_queue->lock, flags);
1383 }
1384
1385 netif_tx_lock_bh(tp->netdev);
1386
1387 if (netif_queue_stopped(tp->netdev) &&
1388 skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
1389 netif_wake_queue(tp->netdev);
1390
1391 netif_tx_unlock_bh(tp->netdev);
1392
1393 ret = usb_autopm_get_interface(tp->intf);
1394 if (ret < 0)
1395 goto out_tx_fill;
1396
1397 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1398 agg->head, (int)(tx_data - (u8 *)agg->head),
1399 (usb_complete_t)write_bulk_callback, agg);
1400
1401 ret = usb_submit_urb(agg->urb, GFP_KERNEL);
1402 if (ret < 0)
1403 usb_autopm_put_interface(tp->intf);
1404
1405 out_tx_fill:
1406 return ret;
1407 }
1408
1409 static void rx_bottom(struct r8152 *tp)
1410 {
1411 unsigned long flags;
1412 struct list_head *cursor, *next, rx_queue;
1413
1414 if (list_empty(&tp->rx_done))
1415 return;
1416
1417 INIT_LIST_HEAD(&rx_queue);
1418 spin_lock_irqsave(&tp->rx_lock, flags);
1419 list_splice_init(&tp->rx_done, &rx_queue);
1420 spin_unlock_irqrestore(&tp->rx_lock, flags);
1421
1422 list_for_each_safe(cursor, next, &rx_queue) {
1423 struct rx_desc *rx_desc;
1424 struct rx_agg *agg;
1425 int len_used = 0;
1426 struct urb *urb;
1427 u8 *rx_data;
1428 int ret;
1429
1430 list_del_init(cursor);
1431
1432 agg = list_entry(cursor, struct rx_agg, list);
1433 urb = agg->urb;
1434 if (urb->actual_length < ETH_ZLEN)
1435 goto submit;
1436
1437 rx_desc = agg->head;
1438 rx_data = agg->head;
1439 len_used += sizeof(struct rx_desc);
1440
1441 while (urb->actual_length > len_used) {
1442 struct net_device *netdev = tp->netdev;
1443 struct net_device_stats *stats;
1444 unsigned int pkt_len;
1445 struct sk_buff *skb;
1446
1447 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1448 if (pkt_len < ETH_ZLEN)
1449 break;
1450
1451 len_used += pkt_len;
1452 if (urb->actual_length < len_used)
1453 break;
1454
1455 stats = rtl8152_get_stats(netdev);
1456
1457 pkt_len -= CRC_SIZE;
1458 rx_data += sizeof(struct rx_desc);
1459
1460 skb = netdev_alloc_skb_ip_align(netdev, pkt_len);
1461 if (!skb) {
1462 stats->rx_dropped++;
1463 break;
1464 }
1465 memcpy(skb->data, rx_data, pkt_len);
1466 skb_put(skb, pkt_len);
1467 skb->protocol = eth_type_trans(skb, netdev);
1468 netif_receive_skb(skb);
1469 stats->rx_packets++;
1470 stats->rx_bytes += pkt_len;
1471
1472 rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE);
1473 rx_desc = (struct rx_desc *)rx_data;
1474 len_used = (int)(rx_data - (u8 *)agg->head);
1475 len_used += sizeof(struct rx_desc);
1476 }
1477
1478 submit:
1479 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
1480 if (ret && ret != -ENODEV) {
1481 spin_lock_irqsave(&tp->rx_lock, flags);
1482 list_add_tail(&agg->list, &tp->rx_done);
1483 spin_unlock_irqrestore(&tp->rx_lock, flags);
1484 tasklet_schedule(&tp->tl);
1485 }
1486 }
1487 }
1488
1489 static void tx_bottom(struct r8152 *tp)
1490 {
1491 int res;
1492
1493 do {
1494 struct tx_agg *agg;
1495
1496 if (skb_queue_empty(&tp->tx_queue))
1497 break;
1498
1499 agg = r8152_get_tx_agg(tp);
1500 if (!agg)
1501 break;
1502
1503 res = r8152_tx_agg_fill(tp, agg);
1504 if (res) {
1505 struct net_device_stats *stats;
1506 struct net_device *netdev;
1507 unsigned long flags;
1508
1509 netdev = tp->netdev;
1510 stats = rtl8152_get_stats(netdev);
1511
1512 if (res == -ENODEV) {
1513 netif_device_detach(netdev);
1514 } else {
1515 netif_warn(tp, tx_err, netdev,
1516 "failed tx_urb %d\n", res);
1517 stats->tx_dropped += agg->skb_num;
1518
1519 spin_lock_irqsave(&tp->tx_lock, flags);
1520 list_add_tail(&agg->list, &tp->tx_free);
1521 spin_unlock_irqrestore(&tp->tx_lock, flags);
1522 }
1523 }
1524 } while (res == 0);
1525 }
1526
1527 static void bottom_half(unsigned long data)
1528 {
1529 struct r8152 *tp;
1530
1531 tp = (struct r8152 *)data;
1532
1533 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1534 return;
1535
1536 if (!test_bit(WORK_ENABLE, &tp->flags))
1537 return;
1538
1539 /* When link down, the driver would cancel all bulks. */
1540 /* This avoid the re-submitting bulk */
1541 if (!netif_carrier_ok(tp->netdev))
1542 return;
1543
1544 rx_bottom(tp);
1545 }
1546
1547 static
1548 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
1549 {
1550 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
1551 agg->head, rx_buf_sz,
1552 (usb_complete_t)read_bulk_callback, agg);
1553
1554 return usb_submit_urb(agg->urb, mem_flags);
1555 }
1556
1557 static void rtl_drop_queued_tx(struct r8152 *tp)
1558 {
1559 struct net_device_stats *stats = &tp->netdev->stats;
1560 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1561 unsigned long flags;
1562 struct sk_buff *skb;
1563
1564 if (skb_queue_empty(tx_queue))
1565 return;
1566
1567 __skb_queue_head_init(&skb_head);
1568 spin_lock_irqsave(&tx_queue->lock, flags);
1569 skb_queue_splice_init(tx_queue, &skb_head);
1570 spin_unlock_irqrestore(&tx_queue->lock, flags);
1571
1572 while ((skb = __skb_dequeue(&skb_head))) {
1573 dev_kfree_skb(skb);
1574 stats->tx_dropped++;
1575 }
1576 }
1577
1578 static void rtl8152_tx_timeout(struct net_device *netdev)
1579 {
1580 struct r8152 *tp = netdev_priv(netdev);
1581 int i;
1582
1583 netif_warn(tp, tx_err, netdev, "Tx timeout\n");
1584 for (i = 0; i < RTL8152_MAX_TX; i++)
1585 usb_unlink_urb(tp->tx_info[i].urb);
1586 }
1587
1588 static void rtl8152_set_rx_mode(struct net_device *netdev)
1589 {
1590 struct r8152 *tp = netdev_priv(netdev);
1591
1592 if (tp->speed & LINK_STATUS) {
1593 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
1594 schedule_delayed_work(&tp->schedule, 0);
1595 }
1596 }
1597
1598 static void _rtl8152_set_rx_mode(struct net_device *netdev)
1599 {
1600 struct r8152 *tp = netdev_priv(netdev);
1601 u32 mc_filter[2]; /* Multicast hash filter */
1602 __le32 tmp[2];
1603 u32 ocp_data;
1604
1605 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
1606 netif_stop_queue(netdev);
1607 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1608 ocp_data &= ~RCR_ACPT_ALL;
1609 ocp_data |= RCR_AB | RCR_APM;
1610
1611 if (netdev->flags & IFF_PROMISC) {
1612 /* Unconditionally log net taps. */
1613 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
1614 ocp_data |= RCR_AM | RCR_AAP;
1615 mc_filter[1] = mc_filter[0] = 0xffffffff;
1616 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
1617 (netdev->flags & IFF_ALLMULTI)) {
1618 /* Too many to filter perfectly -- accept all multicasts. */
1619 ocp_data |= RCR_AM;
1620 mc_filter[1] = mc_filter[0] = 0xffffffff;
1621 } else {
1622 struct netdev_hw_addr *ha;
1623
1624 mc_filter[1] = mc_filter[0] = 0;
1625 netdev_for_each_mc_addr(ha, netdev) {
1626 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1627 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1628 ocp_data |= RCR_AM;
1629 }
1630 }
1631
1632 tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
1633 tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
1634
1635 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
1636 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1637 netif_wake_queue(netdev);
1638 }
1639
1640 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
1641 struct net_device *netdev)
1642 {
1643 struct r8152 *tp = netdev_priv(netdev);
1644
1645 skb_tx_timestamp(skb);
1646
1647 skb_queue_tail(&tp->tx_queue, skb);
1648
1649 if (list_empty(&tp->tx_free) &&
1650 skb_queue_len(&tp->tx_queue) > tp->tx_qlen)
1651 netif_stop_queue(netdev);
1652
1653 if (!list_empty(&tp->tx_free))
1654 schedule_delayed_work(&tp->schedule, 0);
1655
1656 return NETDEV_TX_OK;
1657 }
1658
1659 static void r8152b_reset_packet_filter(struct r8152 *tp)
1660 {
1661 u32 ocp_data;
1662
1663 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
1664 ocp_data &= ~FMC_FCR_MCU_EN;
1665 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
1666 ocp_data |= FMC_FCR_MCU_EN;
1667 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
1668 }
1669
1670 static void rtl8152_nic_reset(struct r8152 *tp)
1671 {
1672 int i;
1673
1674 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
1675
1676 for (i = 0; i < 1000; i++) {
1677 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
1678 break;
1679 udelay(100);
1680 }
1681 }
1682
1683 static void set_tx_qlen(struct r8152 *tp)
1684 {
1685 struct net_device *netdev = tp->netdev;
1686
1687 tp->tx_qlen = rx_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN +
1688 sizeof(struct tx_desc));
1689 }
1690
1691 static inline u8 rtl8152_get_speed(struct r8152 *tp)
1692 {
1693 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
1694 }
1695
1696 static void rtl_set_eee_plus(struct r8152 *tp)
1697 {
1698 u32 ocp_data;
1699 u8 speed;
1700
1701 speed = rtl8152_get_speed(tp);
1702 if (speed & _10bps) {
1703 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
1704 ocp_data |= EEEP_CR_EEEP_TX;
1705 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
1706 } else {
1707 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
1708 ocp_data &= ~EEEP_CR_EEEP_TX;
1709 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
1710 }
1711 }
1712
1713 static void rxdy_gated_en(struct r8152 *tp, bool enable)
1714 {
1715 u32 ocp_data;
1716
1717 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
1718 if (enable)
1719 ocp_data |= RXDY_GATED_EN;
1720 else
1721 ocp_data &= ~RXDY_GATED_EN;
1722 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
1723 }
1724
1725 static int rtl_enable(struct r8152 *tp)
1726 {
1727 u32 ocp_data;
1728 int i, ret;
1729
1730 r8152b_reset_packet_filter(tp);
1731
1732 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
1733 ocp_data |= CR_RE | CR_TE;
1734 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
1735
1736 rxdy_gated_en(tp, false);
1737
1738 INIT_LIST_HEAD(&tp->rx_done);
1739 ret = 0;
1740 for (i = 0; i < RTL8152_MAX_RX; i++) {
1741 INIT_LIST_HEAD(&tp->rx_info[i].list);
1742 ret |= r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
1743 }
1744
1745 return ret;
1746 }
1747
1748 static int rtl8152_enable(struct r8152 *tp)
1749 {
1750 set_tx_qlen(tp);
1751 rtl_set_eee_plus(tp);
1752
1753 return rtl_enable(tp);
1754 }
1755
1756 static void r8153_set_rx_agg(struct r8152 *tp)
1757 {
1758 u8 speed;
1759
1760 speed = rtl8152_get_speed(tp);
1761 if (speed & _1000bps) {
1762 if (tp->udev->speed == USB_SPEED_SUPER) {
1763 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH,
1764 RX_THR_SUPPER);
1765 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
1766 EARLY_AGG_SUPPER);
1767 } else {
1768 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH,
1769 RX_THR_HIGH);
1770 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
1771 EARLY_AGG_HIGH);
1772 }
1773 } else {
1774 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_SLOW);
1775 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
1776 EARLY_AGG_SLOW);
1777 }
1778 }
1779
1780 static int rtl8153_enable(struct r8152 *tp)
1781 {
1782 set_tx_qlen(tp);
1783 rtl_set_eee_plus(tp);
1784 r8153_set_rx_agg(tp);
1785
1786 return rtl_enable(tp);
1787 }
1788
1789 static void rtl8152_disable(struct r8152 *tp)
1790 {
1791 u32 ocp_data;
1792 int i;
1793
1794 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1795 ocp_data &= ~RCR_ACPT_ALL;
1796 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1797
1798 rtl_drop_queued_tx(tp);
1799
1800 for (i = 0; i < RTL8152_MAX_TX; i++)
1801 usb_kill_urb(tp->tx_info[i].urb);
1802
1803 rxdy_gated_en(tp, true);
1804
1805 for (i = 0; i < 1000; i++) {
1806 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1807 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
1808 break;
1809 mdelay(1);
1810 }
1811
1812 for (i = 0; i < 1000; i++) {
1813 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
1814 break;
1815 mdelay(1);
1816 }
1817
1818 for (i = 0; i < RTL8152_MAX_RX; i++)
1819 usb_kill_urb(tp->rx_info[i].urb);
1820
1821 rtl8152_nic_reset(tp);
1822 }
1823
1824 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
1825 {
1826 u32 ocp_data;
1827
1828 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
1829 if (enable)
1830 ocp_data |= POWER_CUT;
1831 else
1832 ocp_data &= ~POWER_CUT;
1833 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
1834
1835 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
1836 ocp_data &= ~RESUME_INDICATE;
1837 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
1838 }
1839
1840 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1841
1842 static u32 __rtl_get_wol(struct r8152 *tp)
1843 {
1844 u32 ocp_data;
1845 u32 wolopts = 0;
1846
1847 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5);
1848 if (!(ocp_data & LAN_WAKE_EN))
1849 return 0;
1850
1851 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
1852 if (ocp_data & LINK_ON_WAKE_EN)
1853 wolopts |= WAKE_PHY;
1854
1855 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
1856 if (ocp_data & UWF_EN)
1857 wolopts |= WAKE_UCAST;
1858 if (ocp_data & BWF_EN)
1859 wolopts |= WAKE_BCAST;
1860 if (ocp_data & MWF_EN)
1861 wolopts |= WAKE_MCAST;
1862
1863 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
1864 if (ocp_data & MAGIC_EN)
1865 wolopts |= WAKE_MAGIC;
1866
1867 return wolopts;
1868 }
1869
1870 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
1871 {
1872 u32 ocp_data;
1873
1874 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1875
1876 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
1877 ocp_data &= ~LINK_ON_WAKE_EN;
1878 if (wolopts & WAKE_PHY)
1879 ocp_data |= LINK_ON_WAKE_EN;
1880 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
1881
1882 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
1883 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN | LAN_WAKE_EN);
1884 if (wolopts & WAKE_UCAST)
1885 ocp_data |= UWF_EN;
1886 if (wolopts & WAKE_BCAST)
1887 ocp_data |= BWF_EN;
1888 if (wolopts & WAKE_MCAST)
1889 ocp_data |= MWF_EN;
1890 if (wolopts & WAKE_ANY)
1891 ocp_data |= LAN_WAKE_EN;
1892 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
1893
1894 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1895
1896 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
1897 ocp_data &= ~MAGIC_EN;
1898 if (wolopts & WAKE_MAGIC)
1899 ocp_data |= MAGIC_EN;
1900 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
1901
1902 if (wolopts & WAKE_ANY)
1903 device_set_wakeup_enable(&tp->udev->dev, true);
1904 else
1905 device_set_wakeup_enable(&tp->udev->dev, false);
1906 }
1907
1908 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
1909 {
1910 if (enable) {
1911 u32 ocp_data;
1912
1913 __rtl_set_wol(tp, WAKE_ANY);
1914
1915 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1916
1917 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
1918 ocp_data |= LINK_OFF_WAKE_EN;
1919 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
1920
1921 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1922 } else {
1923 __rtl_set_wol(tp, tp->saved_wolopts);
1924 }
1925 }
1926
1927 static void rtl_phy_reset(struct r8152 *tp)
1928 {
1929 u16 data;
1930 int i;
1931
1932 clear_bit(PHY_RESET, &tp->flags);
1933
1934 data = r8152_mdio_read(tp, MII_BMCR);
1935
1936 /* don't reset again before the previous one complete */
1937 if (data & BMCR_RESET)
1938 return;
1939
1940 data |= BMCR_RESET;
1941 r8152_mdio_write(tp, MII_BMCR, data);
1942
1943 for (i = 0; i < 50; i++) {
1944 msleep(20);
1945 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
1946 break;
1947 }
1948 }
1949
1950 static void rtl_clear_bp(struct r8152 *tp)
1951 {
1952 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_0, 0);
1953 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_2, 0);
1954 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_4, 0);
1955 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_6, 0);
1956 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_0, 0);
1957 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_2, 0);
1958 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_4, 0);
1959 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_6, 0);
1960 mdelay(3);
1961 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_BA, 0);
1962 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_BA, 0);
1963 }
1964
1965 static void r8153_clear_bp(struct r8152 *tp)
1966 {
1967 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_BP_EN, 0);
1968 ocp_write_byte(tp, MCU_TYPE_USB, USB_BP_EN, 0);
1969 rtl_clear_bp(tp);
1970 }
1971
1972 static void r8153_teredo_off(struct r8152 *tp)
1973 {
1974 u32 ocp_data;
1975
1976 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
1977 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN);
1978 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
1979
1980 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
1981 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
1982 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
1983 }
1984
1985 static void r8152b_disable_aldps(struct r8152 *tp)
1986 {
1987 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
1988 msleep(20);
1989 }
1990
1991 static inline void r8152b_enable_aldps(struct r8152 *tp)
1992 {
1993 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
1994 LINKENA | DIS_SDSAVE);
1995 }
1996
1997 static void r8152b_hw_phy_cfg(struct r8152 *tp)
1998 {
1999 u16 data;
2000
2001 data = r8152_mdio_read(tp, MII_BMCR);
2002 if (data & BMCR_PDOWN) {
2003 data &= ~BMCR_PDOWN;
2004 r8152_mdio_write(tp, MII_BMCR, data);
2005 }
2006
2007 r8152b_disable_aldps(tp);
2008
2009 rtl_clear_bp(tp);
2010
2011 r8152b_enable_aldps(tp);
2012 set_bit(PHY_RESET, &tp->flags);
2013 }
2014
2015 static void r8152b_exit_oob(struct r8152 *tp)
2016 {
2017 u32 ocp_data;
2018 int i;
2019
2020 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2021 ocp_data &= ~RCR_ACPT_ALL;
2022 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2023
2024 rxdy_gated_en(tp, true);
2025 r8153_teredo_off(tp);
2026 r8152b_hw_phy_cfg(tp);
2027
2028 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2029 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
2030
2031 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2032 ocp_data &= ~NOW_IS_OOB;
2033 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2034
2035 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2036 ocp_data &= ~MCU_BORW_EN;
2037 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2038
2039 for (i = 0; i < 1000; i++) {
2040 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2041 if (ocp_data & LINK_LIST_READY)
2042 break;
2043 mdelay(1);
2044 }
2045
2046 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2047 ocp_data |= RE_INIT_LL;
2048 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2049
2050 for (i = 0; i < 1000; i++) {
2051 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2052 if (ocp_data & LINK_LIST_READY)
2053 break;
2054 mdelay(1);
2055 }
2056
2057 rtl8152_nic_reset(tp);
2058
2059 /* rx share fifo credit full threshold */
2060 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2061
2062 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_DEV_STAT);
2063 ocp_data &= STAT_SPEED_MASK;
2064 if (ocp_data == STAT_SPEED_FULL) {
2065 /* rx share fifo credit near full threshold */
2066 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2067 RXFIFO_THR2_FULL);
2068 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2069 RXFIFO_THR3_FULL);
2070 } else {
2071 /* rx share fifo credit near full threshold */
2072 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2073 RXFIFO_THR2_HIGH);
2074 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2075 RXFIFO_THR3_HIGH);
2076 }
2077
2078 /* TX share fifo free credit full threshold */
2079 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
2080
2081 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
2082 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
2083 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
2084 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
2085
2086 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2087 ocp_data &= ~CPCR_RX_VLAN;
2088 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2089
2090 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2091
2092 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2093 ocp_data |= TCR0_AUTO_FIFO;
2094 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2095 }
2096
2097 static void r8152b_enter_oob(struct r8152 *tp)
2098 {
2099 u32 ocp_data;
2100 int i;
2101
2102 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2103 ocp_data &= ~NOW_IS_OOB;
2104 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2105
2106 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
2107 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
2108 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
2109
2110 rtl8152_disable(tp);
2111
2112 for (i = 0; i < 1000; i++) {
2113 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2114 if (ocp_data & LINK_LIST_READY)
2115 break;
2116 mdelay(1);
2117 }
2118
2119 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2120 ocp_data |= RE_INIT_LL;
2121 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2122
2123 for (i = 0; i < 1000; i++) {
2124 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2125 if (ocp_data & LINK_LIST_READY)
2126 break;
2127 mdelay(1);
2128 }
2129
2130 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2131
2132 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2133 ocp_data |= CPCR_RX_VLAN;
2134 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2135
2136 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2137 ocp_data |= ALDPS_PROXY_MODE;
2138 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2139
2140 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2141 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2142 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2143
2144 rxdy_gated_en(tp, false);
2145
2146 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2147 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2148 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2149 }
2150
2151 static void r8153_hw_phy_cfg(struct r8152 *tp)
2152 {
2153 u32 ocp_data;
2154 u16 data;
2155
2156 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
2157 data = r8152_mdio_read(tp, MII_BMCR);
2158 if (data & BMCR_PDOWN) {
2159 data &= ~BMCR_PDOWN;
2160 r8152_mdio_write(tp, MII_BMCR, data);
2161 }
2162
2163 r8153_clear_bp(tp);
2164
2165 if (tp->version == RTL_VER_03) {
2166 data = ocp_reg_read(tp, OCP_EEE_CFG);
2167 data &= ~CTAP_SHORT_EN;
2168 ocp_reg_write(tp, OCP_EEE_CFG, data);
2169 }
2170
2171 data = ocp_reg_read(tp, OCP_POWER_CFG);
2172 data |= EEE_CLKDIV_EN;
2173 ocp_reg_write(tp, OCP_POWER_CFG, data);
2174
2175 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
2176 data |= EN_10M_BGOFF;
2177 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
2178 data = ocp_reg_read(tp, OCP_POWER_CFG);
2179 data |= EN_10M_PLLOFF;
2180 ocp_reg_write(tp, OCP_POWER_CFG, data);
2181 data = sram_read(tp, SRAM_IMPEDANCE);
2182 data &= ~RX_DRIVING_MASK;
2183 sram_write(tp, SRAM_IMPEDANCE, data);
2184
2185 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
2186 ocp_data |= PFM_PWM_SWITCH;
2187 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
2188
2189 data = sram_read(tp, SRAM_LPF_CFG);
2190 data |= LPF_AUTO_TUNE;
2191 sram_write(tp, SRAM_LPF_CFG, data);
2192
2193 data = sram_read(tp, SRAM_10M_AMP1);
2194 data |= GDAC_IB_UPALL;
2195 sram_write(tp, SRAM_10M_AMP1, data);
2196 data = sram_read(tp, SRAM_10M_AMP2);
2197 data |= AMP_DN;
2198 sram_write(tp, SRAM_10M_AMP2, data);
2199
2200 set_bit(PHY_RESET, &tp->flags);
2201 }
2202
2203 static void r8153_u1u2en(struct r8152 *tp, bool enable)
2204 {
2205 u8 u1u2[8];
2206
2207 if (enable)
2208 memset(u1u2, 0xff, sizeof(u1u2));
2209 else
2210 memset(u1u2, 0x00, sizeof(u1u2));
2211
2212 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
2213 }
2214
2215 static void r8153_u2p3en(struct r8152 *tp, bool enable)
2216 {
2217 u32 ocp_data;
2218
2219 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
2220 if (enable)
2221 ocp_data |= U2P3_ENABLE;
2222 else
2223 ocp_data &= ~U2P3_ENABLE;
2224 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
2225 }
2226
2227 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
2228 {
2229 u32 ocp_data;
2230
2231 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2232 if (enable)
2233 ocp_data |= PWR_EN | PHASE2_EN;
2234 else
2235 ocp_data &= ~(PWR_EN | PHASE2_EN);
2236 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2237
2238 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2239 ocp_data &= ~PCUT_STATUS;
2240 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2241 }
2242
2243 static void r8153_first_init(struct r8152 *tp)
2244 {
2245 u32 ocp_data;
2246 int i;
2247
2248 rxdy_gated_en(tp, true);
2249 r8153_teredo_off(tp);
2250
2251 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2252 ocp_data &= ~RCR_ACPT_ALL;
2253 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2254
2255 r8153_hw_phy_cfg(tp);
2256
2257 rtl8152_nic_reset(tp);
2258
2259 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2260 ocp_data &= ~NOW_IS_OOB;
2261 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2262
2263 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2264 ocp_data &= ~MCU_BORW_EN;
2265 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2266
2267 for (i = 0; i < 1000; i++) {
2268 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2269 if (ocp_data & LINK_LIST_READY)
2270 break;
2271 mdelay(1);
2272 }
2273
2274 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2275 ocp_data |= RE_INIT_LL;
2276 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2277
2278 for (i = 0; i < 1000; i++) {
2279 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2280 if (ocp_data & LINK_LIST_READY)
2281 break;
2282 mdelay(1);
2283 }
2284
2285 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2286 ocp_data &= ~CPCR_RX_VLAN;
2287 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2288
2289 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2290
2291 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2292 ocp_data |= TCR0_AUTO_FIFO;
2293 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2294
2295 rtl8152_nic_reset(tp);
2296
2297 /* rx share fifo credit full threshold */
2298 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2299 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
2300 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
2301 /* TX share fifo free credit full threshold */
2302 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
2303
2304 /* rx aggregation */
2305 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2306 ocp_data &= ~RX_AGG_DISABLE;
2307 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2308 }
2309
2310 static void r8153_enter_oob(struct r8152 *tp)
2311 {
2312 u32 ocp_data;
2313 int i;
2314
2315 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2316 ocp_data &= ~NOW_IS_OOB;
2317 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2318
2319 rtl8152_disable(tp);
2320
2321 for (i = 0; i < 1000; i++) {
2322 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2323 if (ocp_data & LINK_LIST_READY)
2324 break;
2325 mdelay(1);
2326 }
2327
2328 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2329 ocp_data |= RE_INIT_LL;
2330 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2331
2332 for (i = 0; i < 1000; i++) {
2333 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2334 if (ocp_data & LINK_LIST_READY)
2335 break;
2336 mdelay(1);
2337 }
2338
2339 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2340
2341 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2342 ocp_data &= ~TEREDO_WAKE_MASK;
2343 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2344
2345 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2346 ocp_data |= CPCR_RX_VLAN;
2347 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2348
2349 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2350 ocp_data |= ALDPS_PROXY_MODE;
2351 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2352
2353 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2354 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2355 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2356
2357 rxdy_gated_en(tp, false);
2358
2359 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2360 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2361 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2362 }
2363
2364 static void r8153_disable_aldps(struct r8152 *tp)
2365 {
2366 u16 data;
2367
2368 data = ocp_reg_read(tp, OCP_POWER_CFG);
2369 data &= ~EN_ALDPS;
2370 ocp_reg_write(tp, OCP_POWER_CFG, data);
2371 msleep(20);
2372 }
2373
2374 static void r8153_enable_aldps(struct r8152 *tp)
2375 {
2376 u16 data;
2377
2378 data = ocp_reg_read(tp, OCP_POWER_CFG);
2379 data |= EN_ALDPS;
2380 ocp_reg_write(tp, OCP_POWER_CFG, data);
2381 }
2382
2383 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
2384 {
2385 u16 bmcr, anar, gbcr;
2386 int ret = 0;
2387
2388 cancel_delayed_work_sync(&tp->schedule);
2389 anar = r8152_mdio_read(tp, MII_ADVERTISE);
2390 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
2391 ADVERTISE_100HALF | ADVERTISE_100FULL);
2392 if (tp->mii.supports_gmii) {
2393 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
2394 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
2395 } else {
2396 gbcr = 0;
2397 }
2398
2399 if (autoneg == AUTONEG_DISABLE) {
2400 if (speed == SPEED_10) {
2401 bmcr = 0;
2402 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2403 } else if (speed == SPEED_100) {
2404 bmcr = BMCR_SPEED100;
2405 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2406 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2407 bmcr = BMCR_SPEED1000;
2408 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
2409 } else {
2410 ret = -EINVAL;
2411 goto out;
2412 }
2413
2414 if (duplex == DUPLEX_FULL)
2415 bmcr |= BMCR_FULLDPLX;
2416 } else {
2417 if (speed == SPEED_10) {
2418 if (duplex == DUPLEX_FULL)
2419 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2420 else
2421 anar |= ADVERTISE_10HALF;
2422 } else if (speed == SPEED_100) {
2423 if (duplex == DUPLEX_FULL) {
2424 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2425 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2426 } else {
2427 anar |= ADVERTISE_10HALF;
2428 anar |= ADVERTISE_100HALF;
2429 }
2430 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2431 if (duplex == DUPLEX_FULL) {
2432 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2433 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2434 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
2435 } else {
2436 anar |= ADVERTISE_10HALF;
2437 anar |= ADVERTISE_100HALF;
2438 gbcr |= ADVERTISE_1000HALF;
2439 }
2440 } else {
2441 ret = -EINVAL;
2442 goto out;
2443 }
2444
2445 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
2446 }
2447
2448 if (test_bit(PHY_RESET, &tp->flags))
2449 bmcr |= BMCR_RESET;
2450
2451 if (tp->mii.supports_gmii)
2452 r8152_mdio_write(tp, MII_CTRL1000, gbcr);
2453
2454 r8152_mdio_write(tp, MII_ADVERTISE, anar);
2455 r8152_mdio_write(tp, MII_BMCR, bmcr);
2456
2457 if (test_bit(PHY_RESET, &tp->flags)) {
2458 int i;
2459
2460 clear_bit(PHY_RESET, &tp->flags);
2461 for (i = 0; i < 50; i++) {
2462 msleep(20);
2463 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
2464 break;
2465 }
2466 }
2467
2468 out:
2469
2470 return ret;
2471 }
2472
2473 static void rtl8152_down(struct r8152 *tp)
2474 {
2475 r8152_power_cut_en(tp, false);
2476 r8152b_disable_aldps(tp);
2477 r8152b_enter_oob(tp);
2478 r8152b_enable_aldps(tp);
2479 }
2480
2481 static void rtl8153_down(struct r8152 *tp)
2482 {
2483 r8153_u1u2en(tp, false);
2484 r8153_power_cut_en(tp, false);
2485 r8153_disable_aldps(tp);
2486 r8153_enter_oob(tp);
2487 r8153_enable_aldps(tp);
2488 }
2489
2490 static void set_carrier(struct r8152 *tp)
2491 {
2492 struct net_device *netdev = tp->netdev;
2493 u8 speed;
2494
2495 clear_bit(RTL8152_LINK_CHG, &tp->flags);
2496 speed = rtl8152_get_speed(tp);
2497
2498 if (speed & LINK_STATUS) {
2499 if (!(tp->speed & LINK_STATUS)) {
2500 tp->rtl_ops.enable(tp);
2501 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2502 netif_carrier_on(netdev);
2503 }
2504 } else {
2505 if (tp->speed & LINK_STATUS) {
2506 netif_carrier_off(netdev);
2507 tasklet_disable(&tp->tl);
2508 tp->rtl_ops.disable(tp);
2509 tasklet_enable(&tp->tl);
2510 }
2511 }
2512 tp->speed = speed;
2513 }
2514
2515 static void rtl_work_func_t(struct work_struct *work)
2516 {
2517 struct r8152 *tp = container_of(work, struct r8152, schedule.work);
2518
2519 if (usb_autopm_get_interface(tp->intf) < 0)
2520 return;
2521
2522 if (!test_bit(WORK_ENABLE, &tp->flags))
2523 goto out1;
2524
2525 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2526 goto out1;
2527
2528 if (test_bit(RTL8152_LINK_CHG, &tp->flags))
2529 set_carrier(tp);
2530
2531 if (test_bit(RTL8152_SET_RX_MODE, &tp->flags))
2532 _rtl8152_set_rx_mode(tp->netdev);
2533
2534 if (tp->speed & LINK_STATUS)
2535 tx_bottom(tp);
2536
2537 if (test_bit(PHY_RESET, &tp->flags))
2538 rtl_phy_reset(tp);
2539
2540 out1:
2541 usb_autopm_put_interface(tp->intf);
2542 }
2543
2544 static int rtl8152_open(struct net_device *netdev)
2545 {
2546 struct r8152 *tp = netdev_priv(netdev);
2547 int res = 0;
2548
2549 res = alloc_all_mem(tp);
2550 if (res)
2551 goto out;
2552
2553 res = usb_autopm_get_interface(tp->intf);
2554 if (res < 0) {
2555 free_all_mem(tp);
2556 goto out;
2557 }
2558
2559 /* The WORK_ENABLE may be set when autoresume occurs */
2560 if (test_bit(WORK_ENABLE, &tp->flags)) {
2561 clear_bit(WORK_ENABLE, &tp->flags);
2562 usb_kill_urb(tp->intr_urb);
2563 cancel_delayed_work_sync(&tp->schedule);
2564 if (tp->speed & LINK_STATUS)
2565 tp->rtl_ops.disable(tp);
2566 }
2567
2568 tp->rtl_ops.up(tp);
2569
2570 rtl8152_set_speed(tp, AUTONEG_ENABLE,
2571 tp->mii.supports_gmii ? SPEED_1000 : SPEED_100,
2572 DUPLEX_FULL);
2573 tp->speed = 0;
2574 netif_carrier_off(netdev);
2575 netif_start_queue(netdev);
2576 set_bit(WORK_ENABLE, &tp->flags);
2577
2578 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
2579 if (res) {
2580 if (res == -ENODEV)
2581 netif_device_detach(tp->netdev);
2582 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
2583 res);
2584 free_all_mem(tp);
2585 }
2586
2587 usb_autopm_put_interface(tp->intf);
2588
2589 out:
2590 return res;
2591 }
2592
2593 static int rtl8152_close(struct net_device *netdev)
2594 {
2595 struct r8152 *tp = netdev_priv(netdev);
2596 int res = 0;
2597
2598 clear_bit(WORK_ENABLE, &tp->flags);
2599 usb_kill_urb(tp->intr_urb);
2600 cancel_delayed_work_sync(&tp->schedule);
2601 netif_stop_queue(netdev);
2602
2603 res = usb_autopm_get_interface(tp->intf);
2604 if (res < 0) {
2605 rtl_drop_queued_tx(tp);
2606 } else {
2607 /*
2608 * The autosuspend may have been enabled and wouldn't
2609 * be disable when autoresume occurs, because the
2610 * netif_running() would be false.
2611 */
2612 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2613 rtl_runtime_suspend_enable(tp, false);
2614 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
2615 }
2616
2617 tasklet_disable(&tp->tl);
2618 tp->rtl_ops.down(tp);
2619 tasklet_enable(&tp->tl);
2620 usb_autopm_put_interface(tp->intf);
2621 }
2622
2623 free_all_mem(tp);
2624
2625 return res;
2626 }
2627
2628 static void r8152b_enable_eee(struct r8152 *tp)
2629 {
2630 u32 ocp_data;
2631
2632 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
2633 ocp_data |= EEE_RX_EN | EEE_TX_EN;
2634 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
2635 ocp_reg_write(tp, OCP_EEE_CONFIG1, RG_TXLPI_MSK_HFDUP | RG_MATCLR_EN |
2636 EEE_10_CAP | EEE_NWAY_EN |
2637 TX_QUIET_EN | RX_QUIET_EN |
2638 SDRISETIME | RG_RXLPI_MSK_HFDUP |
2639 SDFALLTIME);
2640 ocp_reg_write(tp, OCP_EEE_CONFIG2, RG_LPIHYS_NUM | RG_DACQUIET_EN |
2641 RG_LDVQUIET_EN | RG_CKRSEL |
2642 RG_EEEPRG_EN);
2643 ocp_reg_write(tp, OCP_EEE_CONFIG3, FST_SNR_EYE_R | RG_LFS_SEL | MSK_PH);
2644 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | DEVICE_ADDR);
2645 ocp_reg_write(tp, OCP_EEE_DATA, EEE_ADDR);
2646 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | DEVICE_ADDR);
2647 ocp_reg_write(tp, OCP_EEE_DATA, EEE_DATA);
2648 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
2649 }
2650
2651 static void r8153_enable_eee(struct r8152 *tp)
2652 {
2653 u32 ocp_data;
2654 u16 data;
2655
2656 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
2657 ocp_data |= EEE_RX_EN | EEE_TX_EN;
2658 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
2659 data = ocp_reg_read(tp, OCP_EEE_CFG);
2660 data |= EEE10_EN;
2661 ocp_reg_write(tp, OCP_EEE_CFG, data);
2662 data = ocp_reg_read(tp, OCP_EEE_CFG2);
2663 data |= MY1000_EEE | MY100_EEE;
2664 ocp_reg_write(tp, OCP_EEE_CFG2, data);
2665 }
2666
2667 static void r8152b_enable_fc(struct r8152 *tp)
2668 {
2669 u16 anar;
2670
2671 anar = r8152_mdio_read(tp, MII_ADVERTISE);
2672 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
2673 r8152_mdio_write(tp, MII_ADVERTISE, anar);
2674 }
2675
2676 static void r8152b_init(struct r8152 *tp)
2677 {
2678 u32 ocp_data;
2679
2680 if (tp->version == RTL_VER_01) {
2681 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
2682 ocp_data &= ~LED_MODE_MASK;
2683 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
2684 }
2685
2686 r8152_power_cut_en(tp, false);
2687
2688 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
2689 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
2690 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
2691 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
2692 ocp_data &= ~MCU_CLK_RATIO_MASK;
2693 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
2694 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
2695 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
2696 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
2697 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
2698
2699 r8152b_enable_eee(tp);
2700 r8152b_enable_aldps(tp);
2701 r8152b_enable_fc(tp);
2702
2703 /* enable rx aggregation */
2704 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2705 ocp_data &= ~RX_AGG_DISABLE;
2706 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2707 }
2708
2709 static void r8153_init(struct r8152 *tp)
2710 {
2711 u32 ocp_data;
2712 int i;
2713
2714 r8153_u1u2en(tp, false);
2715
2716 for (i = 0; i < 500; i++) {
2717 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
2718 AUTOLOAD_DONE)
2719 break;
2720 msleep(20);
2721 }
2722
2723 for (i = 0; i < 500; i++) {
2724 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
2725 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
2726 break;
2727 msleep(20);
2728 }
2729
2730 r8153_u2p3en(tp, false);
2731
2732 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
2733 ocp_data &= ~TIMER11_EN;
2734 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
2735
2736 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
2737 ocp_data &= ~LED_MODE_MASK;
2738 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
2739
2740 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL);
2741 ocp_data &= ~LPM_TIMER_MASK;
2742 if (tp->udev->speed == USB_SPEED_SUPER)
2743 ocp_data |= LPM_TIMER_500US;
2744 else
2745 ocp_data |= LPM_TIMER_500MS;
2746 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
2747
2748 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
2749 ocp_data &= ~SEN_VAL_MASK;
2750 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
2751 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
2752
2753 r8153_power_cut_en(tp, false);
2754 r8153_u1u2en(tp, true);
2755
2756 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO);
2757 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO);
2758 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
2759 PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
2760 U1U2_SPDWN_EN | L1_SPDWN_EN);
2761 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
2762 PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
2763 TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN |
2764 EEE_SPDWN_EN);
2765
2766 r8153_enable_eee(tp);
2767 r8153_enable_aldps(tp);
2768 r8152b_enable_fc(tp);
2769 }
2770
2771 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
2772 {
2773 struct r8152 *tp = usb_get_intfdata(intf);
2774
2775 if (PMSG_IS_AUTO(message))
2776 set_bit(SELECTIVE_SUSPEND, &tp->flags);
2777 else
2778 netif_device_detach(tp->netdev);
2779
2780 if (netif_running(tp->netdev)) {
2781 clear_bit(WORK_ENABLE, &tp->flags);
2782 usb_kill_urb(tp->intr_urb);
2783 cancel_delayed_work_sync(&tp->schedule);
2784 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2785 rtl_runtime_suspend_enable(tp, true);
2786 } else {
2787 tasklet_disable(&tp->tl);
2788 tp->rtl_ops.down(tp);
2789 tasklet_enable(&tp->tl);
2790 }
2791 }
2792
2793 return 0;
2794 }
2795
2796 static int rtl8152_resume(struct usb_interface *intf)
2797 {
2798 struct r8152 *tp = usb_get_intfdata(intf);
2799
2800 if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2801 tp->rtl_ops.init(tp);
2802 netif_device_attach(tp->netdev);
2803 }
2804
2805 if (netif_running(tp->netdev)) {
2806 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2807 rtl_runtime_suspend_enable(tp, false);
2808 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
2809 if (tp->speed & LINK_STATUS)
2810 tp->rtl_ops.disable(tp);
2811 } else {
2812 tp->rtl_ops.up(tp);
2813 rtl8152_set_speed(tp, AUTONEG_ENABLE,
2814 tp->mii.supports_gmii ? SPEED_1000 : SPEED_100,
2815 DUPLEX_FULL);
2816 }
2817 tp->speed = 0;
2818 netif_carrier_off(tp->netdev);
2819 set_bit(WORK_ENABLE, &tp->flags);
2820 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
2821 }
2822
2823 return 0;
2824 }
2825
2826 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2827 {
2828 struct r8152 *tp = netdev_priv(dev);
2829
2830 if (usb_autopm_get_interface(tp->intf) < 0)
2831 return;
2832
2833 wol->supported = WAKE_ANY;
2834 wol->wolopts = __rtl_get_wol(tp);
2835
2836 usb_autopm_put_interface(tp->intf);
2837 }
2838
2839 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2840 {
2841 struct r8152 *tp = netdev_priv(dev);
2842 int ret;
2843
2844 ret = usb_autopm_get_interface(tp->intf);
2845 if (ret < 0)
2846 goto out_set_wol;
2847
2848 __rtl_set_wol(tp, wol->wolopts);
2849 tp->saved_wolopts = wol->wolopts & WAKE_ANY;
2850
2851 usb_autopm_put_interface(tp->intf);
2852
2853 out_set_wol:
2854 return ret;
2855 }
2856
2857 static u32 rtl8152_get_msglevel(struct net_device *dev)
2858 {
2859 struct r8152 *tp = netdev_priv(dev);
2860
2861 return tp->msg_enable;
2862 }
2863
2864 static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
2865 {
2866 struct r8152 *tp = netdev_priv(dev);
2867
2868 tp->msg_enable = value;
2869 }
2870
2871 static void rtl8152_get_drvinfo(struct net_device *netdev,
2872 struct ethtool_drvinfo *info)
2873 {
2874 struct r8152 *tp = netdev_priv(netdev);
2875
2876 strncpy(info->driver, MODULENAME, ETHTOOL_BUSINFO_LEN);
2877 strncpy(info->version, DRIVER_VERSION, ETHTOOL_BUSINFO_LEN);
2878 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
2879 }
2880
2881 static
2882 int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
2883 {
2884 struct r8152 *tp = netdev_priv(netdev);
2885
2886 if (!tp->mii.mdio_read)
2887 return -EOPNOTSUPP;
2888
2889 return mii_ethtool_gset(&tp->mii, cmd);
2890 }
2891
2892 static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2893 {
2894 struct r8152 *tp = netdev_priv(dev);
2895 int ret;
2896
2897 ret = usb_autopm_get_interface(tp->intf);
2898 if (ret < 0)
2899 goto out;
2900
2901 ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex);
2902
2903 usb_autopm_put_interface(tp->intf);
2904
2905 out:
2906 return ret;
2907 }
2908
2909 static struct ethtool_ops ops = {
2910 .get_drvinfo = rtl8152_get_drvinfo,
2911 .get_settings = rtl8152_get_settings,
2912 .set_settings = rtl8152_set_settings,
2913 .get_link = ethtool_op_get_link,
2914 .get_msglevel = rtl8152_get_msglevel,
2915 .set_msglevel = rtl8152_set_msglevel,
2916 .get_wol = rtl8152_get_wol,
2917 .set_wol = rtl8152_set_wol,
2918 };
2919
2920 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2921 {
2922 struct r8152 *tp = netdev_priv(netdev);
2923 struct mii_ioctl_data *data = if_mii(rq);
2924 int res;
2925
2926 res = usb_autopm_get_interface(tp->intf);
2927 if (res < 0)
2928 goto out;
2929
2930 switch (cmd) {
2931 case SIOCGMIIPHY:
2932 data->phy_id = R8152_PHY_ID; /* Internal PHY */
2933 break;
2934
2935 case SIOCGMIIREG:
2936 data->val_out = r8152_mdio_read(tp, data->reg_num);
2937 break;
2938
2939 case SIOCSMIIREG:
2940 if (!capable(CAP_NET_ADMIN)) {
2941 res = -EPERM;
2942 break;
2943 }
2944 r8152_mdio_write(tp, data->reg_num, data->val_in);
2945 break;
2946
2947 default:
2948 res = -EOPNOTSUPP;
2949 }
2950
2951 usb_autopm_put_interface(tp->intf);
2952
2953 out:
2954 return res;
2955 }
2956
2957 static const struct net_device_ops rtl8152_netdev_ops = {
2958 .ndo_open = rtl8152_open,
2959 .ndo_stop = rtl8152_close,
2960 .ndo_do_ioctl = rtl8152_ioctl,
2961 .ndo_start_xmit = rtl8152_start_xmit,
2962 .ndo_tx_timeout = rtl8152_tx_timeout,
2963 .ndo_set_rx_mode = rtl8152_set_rx_mode,
2964 .ndo_set_mac_address = rtl8152_set_mac_address,
2965
2966 .ndo_change_mtu = eth_change_mtu,
2967 .ndo_validate_addr = eth_validate_addr,
2968 };
2969
2970 static void r8152b_get_version(struct r8152 *tp)
2971 {
2972 u32 ocp_data;
2973 u16 version;
2974
2975 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
2976 version = (u16)(ocp_data & VERSION_MASK);
2977
2978 switch (version) {
2979 case 0x4c00:
2980 tp->version = RTL_VER_01;
2981 break;
2982 case 0x4c10:
2983 tp->version = RTL_VER_02;
2984 break;
2985 case 0x5c00:
2986 tp->version = RTL_VER_03;
2987 tp->mii.supports_gmii = 1;
2988 break;
2989 case 0x5c10:
2990 tp->version = RTL_VER_04;
2991 tp->mii.supports_gmii = 1;
2992 break;
2993 case 0x5c20:
2994 tp->version = RTL_VER_05;
2995 tp->mii.supports_gmii = 1;
2996 break;
2997 default:
2998 netif_info(tp, probe, tp->netdev,
2999 "Unknown version 0x%04x\n", version);
3000 break;
3001 }
3002 }
3003
3004 static void rtl8152_unload(struct r8152 *tp)
3005 {
3006 if (tp->version != RTL_VER_01)
3007 r8152_power_cut_en(tp, true);
3008 }
3009
3010 static void rtl8153_unload(struct r8152 *tp)
3011 {
3012 r8153_power_cut_en(tp, true);
3013 }
3014
3015 static int rtl_ops_init(struct r8152 *tp, const struct usb_device_id *id)
3016 {
3017 struct rtl_ops *ops = &tp->rtl_ops;
3018 int ret = -ENODEV;
3019
3020 switch (id->idVendor) {
3021 case VENDOR_ID_REALTEK:
3022 switch (id->idProduct) {
3023 case PRODUCT_ID_RTL8152:
3024 ops->init = r8152b_init;
3025 ops->enable = rtl8152_enable;
3026 ops->disable = rtl8152_disable;
3027 ops->up = r8152b_exit_oob;
3028 ops->down = rtl8152_down;
3029 ops->unload = rtl8152_unload;
3030 ret = 0;
3031 break;
3032 case PRODUCT_ID_RTL8153:
3033 ops->init = r8153_init;
3034 ops->enable = rtl8153_enable;
3035 ops->disable = rtl8152_disable;
3036 ops->up = r8153_first_init;
3037 ops->down = rtl8153_down;
3038 ops->unload = rtl8153_unload;
3039 ret = 0;
3040 break;
3041 default:
3042 break;
3043 }
3044 break;
3045
3046 case VENDOR_ID_SAMSUNG:
3047 switch (id->idProduct) {
3048 case PRODUCT_ID_SAMSUNG:
3049 ops->init = r8153_init;
3050 ops->enable = rtl8153_enable;
3051 ops->disable = rtl8152_disable;
3052 ops->up = r8153_first_init;
3053 ops->down = rtl8153_down;
3054 ops->unload = rtl8153_unload;
3055 ret = 0;
3056 break;
3057 default:
3058 break;
3059 }
3060 break;
3061
3062 default:
3063 break;
3064 }
3065
3066 if (ret)
3067 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
3068
3069 return ret;
3070 }
3071
3072 static int rtl8152_probe(struct usb_interface *intf,
3073 const struct usb_device_id *id)
3074 {
3075 struct usb_device *udev = interface_to_usbdev(intf);
3076 struct r8152 *tp;
3077 struct net_device *netdev;
3078 int ret;
3079
3080 netdev = alloc_etherdev(sizeof(struct r8152));
3081 if (!netdev) {
3082 dev_err(&intf->dev, "Out of memory\n");
3083 return -ENOMEM;
3084 }
3085
3086 SET_NETDEV_DEV(netdev, &intf->dev);
3087 tp = netdev_priv(netdev);
3088 tp->msg_enable = 0x7FFF;
3089
3090 tp->udev = udev;
3091 tp->netdev = netdev;
3092 tp->intf = intf;
3093
3094 ret = rtl_ops_init(tp, id);
3095 if (ret)
3096 goto out;
3097
3098 tasklet_init(&tp->tl, bottom_half, (unsigned long)tp);
3099 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
3100
3101 netdev->netdev_ops = &rtl8152_netdev_ops;
3102 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
3103
3104 netdev->features |= NETIF_F_IP_CSUM;
3105 netdev->hw_features = NETIF_F_IP_CSUM;
3106
3107 SET_ETHTOOL_OPS(netdev, &ops);
3108
3109 tp->mii.dev = netdev;
3110 tp->mii.mdio_read = read_mii_word;
3111 tp->mii.mdio_write = write_mii_word;
3112 tp->mii.phy_id_mask = 0x3f;
3113 tp->mii.reg_num_mask = 0x1f;
3114 tp->mii.phy_id = R8152_PHY_ID;
3115 tp->mii.supports_gmii = 0;
3116
3117 intf->needs_remote_wakeup = 1;
3118
3119 r8152b_get_version(tp);
3120 tp->rtl_ops.init(tp);
3121 set_ethernet_addr(tp);
3122
3123 usb_set_intfdata(intf, tp);
3124
3125 ret = register_netdev(netdev);
3126 if (ret != 0) {
3127 netif_err(tp, probe, netdev, "couldn't register the device\n");
3128 goto out1;
3129 }
3130
3131 tp->saved_wolopts = __rtl_get_wol(tp);
3132 if (tp->saved_wolopts)
3133 device_set_wakeup_enable(&udev->dev, true);
3134 else
3135 device_set_wakeup_enable(&udev->dev, false);
3136
3137 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
3138
3139 return 0;
3140
3141 out1:
3142 usb_set_intfdata(intf, NULL);
3143 out:
3144 free_netdev(netdev);
3145 return ret;
3146 }
3147
3148 static void rtl8152_disconnect(struct usb_interface *intf)
3149 {
3150 struct r8152 *tp = usb_get_intfdata(intf);
3151
3152 usb_set_intfdata(intf, NULL);
3153 if (tp) {
3154 set_bit(RTL8152_UNPLUG, &tp->flags);
3155 tasklet_kill(&tp->tl);
3156 unregister_netdev(tp->netdev);
3157 tp->rtl_ops.unload(tp);
3158 free_netdev(tp->netdev);
3159 }
3160 }
3161
3162 /* table of devices that work with this driver */
3163 static struct usb_device_id rtl8152_table[] = {
3164 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8152)},
3165 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8153)},
3166 {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, PRODUCT_ID_SAMSUNG)},
3167 {}
3168 };
3169
3170 MODULE_DEVICE_TABLE(usb, rtl8152_table);
3171
3172 static struct usb_driver rtl8152_driver = {
3173 .name = MODULENAME,
3174 .id_table = rtl8152_table,
3175 .probe = rtl8152_probe,
3176 .disconnect = rtl8152_disconnect,
3177 .suspend = rtl8152_suspend,
3178 .resume = rtl8152_resume,
3179 .reset_resume = rtl8152_resume,
3180 .supports_autosuspend = 1,
3181 .disable_hub_initiated_lpm = 1,
3182 };
3183
3184 module_usb_driver(rtl8152_driver);
3185
3186 MODULE_AUTHOR(DRIVER_AUTHOR);
3187 MODULE_DESCRIPTION(DRIVER_DESC);
3188 MODULE_LICENSE("GPL");
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