Merge tag 'nfc-next-4.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sameo...
[deliverable/linux.git] / drivers / net / usb / r8152.c
1 /*
2 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * version 2 as published by the Free Software Foundation.
7 *
8 */
9
10 #include <linux/signal.h>
11 #include <linux/slab.h>
12 #include <linux/module.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/mii.h>
16 #include <linux/ethtool.h>
17 #include <linux/usb.h>
18 #include <linux/crc32.h>
19 #include <linux/if_vlan.h>
20 #include <linux/uaccess.h>
21 #include <linux/list.h>
22 #include <linux/ip.h>
23 #include <linux/ipv6.h>
24 #include <net/ip6_checksum.h>
25 #include <uapi/linux/mdio.h>
26 #include <linux/mdio.h>
27 #include <linux/usb/cdc.h>
28 #include <linux/suspend.h>
29
30 /* Information for net-next */
31 #define NETNEXT_VERSION "08"
32
33 /* Information for net */
34 #define NET_VERSION "5"
35
36 #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION
37 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
38 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
39 #define MODULENAME "r8152"
40
41 #define R8152_PHY_ID 32
42
43 #define PLA_IDR 0xc000
44 #define PLA_RCR 0xc010
45 #define PLA_RMS 0xc016
46 #define PLA_RXFIFO_CTRL0 0xc0a0
47 #define PLA_RXFIFO_CTRL1 0xc0a4
48 #define PLA_RXFIFO_CTRL2 0xc0a8
49 #define PLA_DMY_REG0 0xc0b0
50 #define PLA_FMC 0xc0b4
51 #define PLA_CFG_WOL 0xc0b6
52 #define PLA_TEREDO_CFG 0xc0bc
53 #define PLA_MAR 0xcd00
54 #define PLA_BACKUP 0xd000
55 #define PAL_BDC_CR 0xd1a0
56 #define PLA_TEREDO_TIMER 0xd2cc
57 #define PLA_REALWOW_TIMER 0xd2e8
58 #define PLA_LEDSEL 0xdd90
59 #define PLA_LED_FEATURE 0xdd92
60 #define PLA_PHYAR 0xde00
61 #define PLA_BOOT_CTRL 0xe004
62 #define PLA_GPHY_INTR_IMR 0xe022
63 #define PLA_EEE_CR 0xe040
64 #define PLA_EEEP_CR 0xe080
65 #define PLA_MAC_PWR_CTRL 0xe0c0
66 #define PLA_MAC_PWR_CTRL2 0xe0ca
67 #define PLA_MAC_PWR_CTRL3 0xe0cc
68 #define PLA_MAC_PWR_CTRL4 0xe0ce
69 #define PLA_WDT6_CTRL 0xe428
70 #define PLA_TCR0 0xe610
71 #define PLA_TCR1 0xe612
72 #define PLA_MTPS 0xe615
73 #define PLA_TXFIFO_CTRL 0xe618
74 #define PLA_RSTTALLY 0xe800
75 #define PLA_CR 0xe813
76 #define PLA_CRWECR 0xe81c
77 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
78 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
79 #define PLA_CONFIG5 0xe822
80 #define PLA_PHY_PWR 0xe84c
81 #define PLA_OOB_CTRL 0xe84f
82 #define PLA_CPCR 0xe854
83 #define PLA_MISC_0 0xe858
84 #define PLA_MISC_1 0xe85a
85 #define PLA_OCP_GPHY_BASE 0xe86c
86 #define PLA_TALLYCNT 0xe890
87 #define PLA_SFF_STS_7 0xe8de
88 #define PLA_PHYSTATUS 0xe908
89 #define PLA_BP_BA 0xfc26
90 #define PLA_BP_0 0xfc28
91 #define PLA_BP_1 0xfc2a
92 #define PLA_BP_2 0xfc2c
93 #define PLA_BP_3 0xfc2e
94 #define PLA_BP_4 0xfc30
95 #define PLA_BP_5 0xfc32
96 #define PLA_BP_6 0xfc34
97 #define PLA_BP_7 0xfc36
98 #define PLA_BP_EN 0xfc38
99
100 #define USB_USB2PHY 0xb41e
101 #define USB_SSPHYLINK2 0xb428
102 #define USB_U2P3_CTRL 0xb460
103 #define USB_CSR_DUMMY1 0xb464
104 #define USB_CSR_DUMMY2 0xb466
105 #define USB_DEV_STAT 0xb808
106 #define USB_CONNECT_TIMER 0xcbf8
107 #define USB_BURST_SIZE 0xcfc0
108 #define USB_USB_CTRL 0xd406
109 #define USB_PHY_CTRL 0xd408
110 #define USB_TX_AGG 0xd40a
111 #define USB_RX_BUF_TH 0xd40c
112 #define USB_USB_TIMER 0xd428
113 #define USB_RX_EARLY_TIMEOUT 0xd42c
114 #define USB_RX_EARLY_SIZE 0xd42e
115 #define USB_PM_CTRL_STATUS 0xd432
116 #define USB_TX_DMA 0xd434
117 #define USB_TOLERANCE 0xd490
118 #define USB_LPM_CTRL 0xd41a
119 #define USB_BMU_RESET 0xd4b0
120 #define USB_UPS_CTRL 0xd800
121 #define USB_MISC_0 0xd81a
122 #define USB_POWER_CUT 0xd80a
123 #define USB_AFE_CTRL2 0xd824
124 #define USB_WDT11_CTRL 0xe43c
125 #define USB_BP_BA 0xfc26
126 #define USB_BP_0 0xfc28
127 #define USB_BP_1 0xfc2a
128 #define USB_BP_2 0xfc2c
129 #define USB_BP_3 0xfc2e
130 #define USB_BP_4 0xfc30
131 #define USB_BP_5 0xfc32
132 #define USB_BP_6 0xfc34
133 #define USB_BP_7 0xfc36
134 #define USB_BP_EN 0xfc38
135
136 /* OCP Registers */
137 #define OCP_ALDPS_CONFIG 0x2010
138 #define OCP_EEE_CONFIG1 0x2080
139 #define OCP_EEE_CONFIG2 0x2092
140 #define OCP_EEE_CONFIG3 0x2094
141 #define OCP_BASE_MII 0xa400
142 #define OCP_EEE_AR 0xa41a
143 #define OCP_EEE_DATA 0xa41c
144 #define OCP_PHY_STATUS 0xa420
145 #define OCP_POWER_CFG 0xa430
146 #define OCP_EEE_CFG 0xa432
147 #define OCP_SRAM_ADDR 0xa436
148 #define OCP_SRAM_DATA 0xa438
149 #define OCP_DOWN_SPEED 0xa442
150 #define OCP_EEE_ABLE 0xa5c4
151 #define OCP_EEE_ADV 0xa5d0
152 #define OCP_EEE_LPABLE 0xa5d2
153 #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
154 #define OCP_ADC_CFG 0xbc06
155
156 /* SRAM Register */
157 #define SRAM_LPF_CFG 0x8012
158 #define SRAM_10M_AMP1 0x8080
159 #define SRAM_10M_AMP2 0x8082
160 #define SRAM_IMPEDANCE 0x8084
161
162 /* PLA_RCR */
163 #define RCR_AAP 0x00000001
164 #define RCR_APM 0x00000002
165 #define RCR_AM 0x00000004
166 #define RCR_AB 0x00000008
167 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
168
169 /* PLA_RXFIFO_CTRL0 */
170 #define RXFIFO_THR1_NORMAL 0x00080002
171 #define RXFIFO_THR1_OOB 0x01800003
172
173 /* PLA_RXFIFO_CTRL1 */
174 #define RXFIFO_THR2_FULL 0x00000060
175 #define RXFIFO_THR2_HIGH 0x00000038
176 #define RXFIFO_THR2_OOB 0x0000004a
177 #define RXFIFO_THR2_NORMAL 0x00a0
178
179 /* PLA_RXFIFO_CTRL2 */
180 #define RXFIFO_THR3_FULL 0x00000078
181 #define RXFIFO_THR3_HIGH 0x00000048
182 #define RXFIFO_THR3_OOB 0x0000005a
183 #define RXFIFO_THR3_NORMAL 0x0110
184
185 /* PLA_TXFIFO_CTRL */
186 #define TXFIFO_THR_NORMAL 0x00400008
187 #define TXFIFO_THR_NORMAL2 0x01000008
188
189 /* PLA_DMY_REG0 */
190 #define ECM_ALDPS 0x0002
191
192 /* PLA_FMC */
193 #define FMC_FCR_MCU_EN 0x0001
194
195 /* PLA_EEEP_CR */
196 #define EEEP_CR_EEEP_TX 0x0002
197
198 /* PLA_WDT6_CTRL */
199 #define WDT6_SET_MODE 0x0010
200
201 /* PLA_TCR0 */
202 #define TCR0_TX_EMPTY 0x0800
203 #define TCR0_AUTO_FIFO 0x0080
204
205 /* PLA_TCR1 */
206 #define VERSION_MASK 0x7cf0
207
208 /* PLA_MTPS */
209 #define MTPS_JUMBO (12 * 1024 / 64)
210 #define MTPS_DEFAULT (6 * 1024 / 64)
211
212 /* PLA_RSTTALLY */
213 #define TALLY_RESET 0x0001
214
215 /* PLA_CR */
216 #define CR_RST 0x10
217 #define CR_RE 0x08
218 #define CR_TE 0x04
219
220 /* PLA_CRWECR */
221 #define CRWECR_NORAML 0x00
222 #define CRWECR_CONFIG 0xc0
223
224 /* PLA_OOB_CTRL */
225 #define NOW_IS_OOB 0x80
226 #define TXFIFO_EMPTY 0x20
227 #define RXFIFO_EMPTY 0x10
228 #define LINK_LIST_READY 0x02
229 #define DIS_MCU_CLROOB 0x01
230 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
231
232 /* PLA_MISC_1 */
233 #define RXDY_GATED_EN 0x0008
234
235 /* PLA_SFF_STS_7 */
236 #define RE_INIT_LL 0x8000
237 #define MCU_BORW_EN 0x4000
238
239 /* PLA_CPCR */
240 #define CPCR_RX_VLAN 0x0040
241
242 /* PLA_CFG_WOL */
243 #define MAGIC_EN 0x0001
244
245 /* PLA_TEREDO_CFG */
246 #define TEREDO_SEL 0x8000
247 #define TEREDO_WAKE_MASK 0x7f00
248 #define TEREDO_RS_EVENT_MASK 0x00fe
249 #define OOB_TEREDO_EN 0x0001
250
251 /* PAL_BDC_CR */
252 #define ALDPS_PROXY_MODE 0x0001
253
254 /* PLA_CONFIG34 */
255 #define LINK_ON_WAKE_EN 0x0010
256 #define LINK_OFF_WAKE_EN 0x0008
257
258 /* PLA_CONFIG5 */
259 #define BWF_EN 0x0040
260 #define MWF_EN 0x0020
261 #define UWF_EN 0x0010
262 #define LAN_WAKE_EN 0x0002
263
264 /* PLA_LED_FEATURE */
265 #define LED_MODE_MASK 0x0700
266
267 /* PLA_PHY_PWR */
268 #define TX_10M_IDLE_EN 0x0080
269 #define PFM_PWM_SWITCH 0x0040
270
271 /* PLA_MAC_PWR_CTRL */
272 #define D3_CLK_GATED_EN 0x00004000
273 #define MCU_CLK_RATIO 0x07010f07
274 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
275 #define ALDPS_SPDWN_RATIO 0x0f87
276
277 /* PLA_MAC_PWR_CTRL2 */
278 #define EEE_SPDWN_RATIO 0x8007
279
280 /* PLA_MAC_PWR_CTRL3 */
281 #define PKT_AVAIL_SPDWN_EN 0x0100
282 #define SUSPEND_SPDWN_EN 0x0004
283 #define U1U2_SPDWN_EN 0x0002
284 #define L1_SPDWN_EN 0x0001
285
286 /* PLA_MAC_PWR_CTRL4 */
287 #define PWRSAVE_SPDWN_EN 0x1000
288 #define RXDV_SPDWN_EN 0x0800
289 #define TX10MIDLE_EN 0x0100
290 #define TP100_SPDWN_EN 0x0020
291 #define TP500_SPDWN_EN 0x0010
292 #define TP1000_SPDWN_EN 0x0008
293 #define EEE_SPDWN_EN 0x0001
294
295 /* PLA_GPHY_INTR_IMR */
296 #define GPHY_STS_MSK 0x0001
297 #define SPEED_DOWN_MSK 0x0002
298 #define SPDWN_RXDV_MSK 0x0004
299 #define SPDWN_LINKCHG_MSK 0x0008
300
301 /* PLA_PHYAR */
302 #define PHYAR_FLAG 0x80000000
303
304 /* PLA_EEE_CR */
305 #define EEE_RX_EN 0x0001
306 #define EEE_TX_EN 0x0002
307
308 /* PLA_BOOT_CTRL */
309 #define AUTOLOAD_DONE 0x0002
310
311 /* USB_USB2PHY */
312 #define USB2PHY_SUSPEND 0x0001
313 #define USB2PHY_L1 0x0002
314
315 /* USB_SSPHYLINK2 */
316 #define pwd_dn_scale_mask 0x3ffe
317 #define pwd_dn_scale(x) ((x) << 1)
318
319 /* USB_CSR_DUMMY1 */
320 #define DYNAMIC_BURST 0x0001
321
322 /* USB_CSR_DUMMY2 */
323 #define EP4_FULL_FC 0x0001
324
325 /* USB_DEV_STAT */
326 #define STAT_SPEED_MASK 0x0006
327 #define STAT_SPEED_HIGH 0x0000
328 #define STAT_SPEED_FULL 0x0002
329
330 /* USB_TX_AGG */
331 #define TX_AGG_MAX_THRESHOLD 0x03
332
333 /* USB_RX_BUF_TH */
334 #define RX_THR_SUPPER 0x0c350180
335 #define RX_THR_HIGH 0x7a120180
336 #define RX_THR_SLOW 0xffff0180
337
338 /* USB_TX_DMA */
339 #define TEST_MODE_DISABLE 0x00000001
340 #define TX_SIZE_ADJUST1 0x00000100
341
342 /* USB_BMU_RESET */
343 #define BMU_RESET_EP_IN 0x01
344 #define BMU_RESET_EP_OUT 0x02
345
346 /* USB_UPS_CTRL */
347 #define POWER_CUT 0x0100
348
349 /* USB_PM_CTRL_STATUS */
350 #define RESUME_INDICATE 0x0001
351
352 /* USB_USB_CTRL */
353 #define RX_AGG_DISABLE 0x0010
354 #define RX_ZERO_EN 0x0080
355
356 /* USB_U2P3_CTRL */
357 #define U2P3_ENABLE 0x0001
358
359 /* USB_POWER_CUT */
360 #define PWR_EN 0x0001
361 #define PHASE2_EN 0x0008
362
363 /* USB_MISC_0 */
364 #define PCUT_STATUS 0x0001
365
366 /* USB_RX_EARLY_TIMEOUT */
367 #define COALESCE_SUPER 85000U
368 #define COALESCE_HIGH 250000U
369 #define COALESCE_SLOW 524280U
370
371 /* USB_WDT11_CTRL */
372 #define TIMER11_EN 0x0001
373
374 /* USB_LPM_CTRL */
375 /* bit 4 ~ 5: fifo empty boundary */
376 #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
377 /* bit 2 ~ 3: LMP timer */
378 #define LPM_TIMER_MASK 0x0c
379 #define LPM_TIMER_500MS 0x04 /* 500 ms */
380 #define LPM_TIMER_500US 0x0c /* 500 us */
381 #define ROK_EXIT_LPM 0x02
382
383 /* USB_AFE_CTRL2 */
384 #define SEN_VAL_MASK 0xf800
385 #define SEN_VAL_NORMAL 0xa000
386 #define SEL_RXIDLE 0x0100
387
388 /* OCP_ALDPS_CONFIG */
389 #define ENPWRSAVE 0x8000
390 #define ENPDNPS 0x0200
391 #define LINKENA 0x0100
392 #define DIS_SDSAVE 0x0010
393
394 /* OCP_PHY_STATUS */
395 #define PHY_STAT_MASK 0x0007
396 #define PHY_STAT_LAN_ON 3
397 #define PHY_STAT_PWRDN 5
398
399 /* OCP_POWER_CFG */
400 #define EEE_CLKDIV_EN 0x8000
401 #define EN_ALDPS 0x0004
402 #define EN_10M_PLLOFF 0x0001
403
404 /* OCP_EEE_CONFIG1 */
405 #define RG_TXLPI_MSK_HFDUP 0x8000
406 #define RG_MATCLR_EN 0x4000
407 #define EEE_10_CAP 0x2000
408 #define EEE_NWAY_EN 0x1000
409 #define TX_QUIET_EN 0x0200
410 #define RX_QUIET_EN 0x0100
411 #define sd_rise_time_mask 0x0070
412 #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
413 #define RG_RXLPI_MSK_HFDUP 0x0008
414 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
415
416 /* OCP_EEE_CONFIG2 */
417 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
418 #define RG_DACQUIET_EN 0x0400
419 #define RG_LDVQUIET_EN 0x0200
420 #define RG_CKRSEL 0x0020
421 #define RG_EEEPRG_EN 0x0010
422
423 /* OCP_EEE_CONFIG3 */
424 #define fast_snr_mask 0xff80
425 #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
426 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
427 #define MSK_PH 0x0006 /* bit 0 ~ 3 */
428
429 /* OCP_EEE_AR */
430 /* bit[15:14] function */
431 #define FUN_ADDR 0x0000
432 #define FUN_DATA 0x4000
433 /* bit[4:0] device addr */
434
435 /* OCP_EEE_CFG */
436 #define CTAP_SHORT_EN 0x0040
437 #define EEE10_EN 0x0010
438
439 /* OCP_DOWN_SPEED */
440 #define EN_10M_BGOFF 0x0080
441
442 /* OCP_PHY_STATE */
443 #define TXDIS_STATE 0x01
444 #define ABD_STATE 0x02
445
446 /* OCP_ADC_CFG */
447 #define CKADSEL_L 0x0100
448 #define ADC_EN 0x0080
449 #define EN_EMI_L 0x0040
450
451 /* SRAM_LPF_CFG */
452 #define LPF_AUTO_TUNE 0x8000
453
454 /* SRAM_10M_AMP1 */
455 #define GDAC_IB_UPALL 0x0008
456
457 /* SRAM_10M_AMP2 */
458 #define AMP_DN 0x0200
459
460 /* SRAM_IMPEDANCE */
461 #define RX_DRIVING_MASK 0x6000
462
463 enum rtl_register_content {
464 _1000bps = 0x10,
465 _100bps = 0x08,
466 _10bps = 0x04,
467 LINK_STATUS = 0x02,
468 FULL_DUP = 0x01,
469 };
470
471 #define RTL8152_MAX_TX 4
472 #define RTL8152_MAX_RX 10
473 #define INTBUFSIZE 2
474 #define CRC_SIZE 4
475 #define TX_ALIGN 4
476 #define RX_ALIGN 8
477
478 #define INTR_LINK 0x0004
479
480 #define RTL8152_REQT_READ 0xc0
481 #define RTL8152_REQT_WRITE 0x40
482 #define RTL8152_REQ_GET_REGS 0x05
483 #define RTL8152_REQ_SET_REGS 0x05
484
485 #define BYTE_EN_DWORD 0xff
486 #define BYTE_EN_WORD 0x33
487 #define BYTE_EN_BYTE 0x11
488 #define BYTE_EN_SIX_BYTES 0x3f
489 #define BYTE_EN_START_MASK 0x0f
490 #define BYTE_EN_END_MASK 0xf0
491
492 #define RTL8153_MAX_PACKET 9216 /* 9K */
493 #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN)
494 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
495 #define RTL8153_RMS RTL8153_MAX_PACKET
496 #define RTL8152_TX_TIMEOUT (5 * HZ)
497 #define RTL8152_NAPI_WEIGHT 64
498
499 /* rtl8152 flags */
500 enum rtl8152_flags {
501 RTL8152_UNPLUG = 0,
502 RTL8152_SET_RX_MODE,
503 WORK_ENABLE,
504 RTL8152_LINK_CHG,
505 SELECTIVE_SUSPEND,
506 PHY_RESET,
507 SCHEDULE_NAPI,
508 };
509
510 /* Define these values to match your device */
511 #define VENDOR_ID_REALTEK 0x0bda
512 #define VENDOR_ID_SAMSUNG 0x04e8
513 #define VENDOR_ID_LENOVO 0x17ef
514 #define VENDOR_ID_NVIDIA 0x0955
515
516 #define MCU_TYPE_PLA 0x0100
517 #define MCU_TYPE_USB 0x0000
518
519 struct tally_counter {
520 __le64 tx_packets;
521 __le64 rx_packets;
522 __le64 tx_errors;
523 __le32 rx_errors;
524 __le16 rx_missed;
525 __le16 align_errors;
526 __le32 tx_one_collision;
527 __le32 tx_multi_collision;
528 __le64 rx_unicast;
529 __le64 rx_broadcast;
530 __le32 rx_multicast;
531 __le16 tx_aborted;
532 __le16 tx_underrun;
533 };
534
535 struct rx_desc {
536 __le32 opts1;
537 #define RX_LEN_MASK 0x7fff
538
539 __le32 opts2;
540 #define RD_UDP_CS BIT(23)
541 #define RD_TCP_CS BIT(22)
542 #define RD_IPV6_CS BIT(20)
543 #define RD_IPV4_CS BIT(19)
544
545 __le32 opts3;
546 #define IPF BIT(23) /* IP checksum fail */
547 #define UDPF BIT(22) /* UDP checksum fail */
548 #define TCPF BIT(21) /* TCP checksum fail */
549 #define RX_VLAN_TAG BIT(16)
550
551 __le32 opts4;
552 __le32 opts5;
553 __le32 opts6;
554 };
555
556 struct tx_desc {
557 __le32 opts1;
558 #define TX_FS BIT(31) /* First segment of a packet */
559 #define TX_LS BIT(30) /* Final segment of a packet */
560 #define GTSENDV4 BIT(28)
561 #define GTSENDV6 BIT(27)
562 #define GTTCPHO_SHIFT 18
563 #define GTTCPHO_MAX 0x7fU
564 #define TX_LEN_MAX 0x3ffffU
565
566 __le32 opts2;
567 #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
568 #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
569 #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
570 #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
571 #define MSS_SHIFT 17
572 #define MSS_MAX 0x7ffU
573 #define TCPHO_SHIFT 17
574 #define TCPHO_MAX 0x7ffU
575 #define TX_VLAN_TAG BIT(16)
576 };
577
578 struct r8152;
579
580 struct rx_agg {
581 struct list_head list;
582 struct urb *urb;
583 struct r8152 *context;
584 void *buffer;
585 void *head;
586 };
587
588 struct tx_agg {
589 struct list_head list;
590 struct urb *urb;
591 struct r8152 *context;
592 void *buffer;
593 void *head;
594 u32 skb_num;
595 u32 skb_len;
596 };
597
598 struct r8152 {
599 unsigned long flags;
600 struct usb_device *udev;
601 struct napi_struct napi;
602 struct usb_interface *intf;
603 struct net_device *netdev;
604 struct urb *intr_urb;
605 struct tx_agg tx_info[RTL8152_MAX_TX];
606 struct rx_agg rx_info[RTL8152_MAX_RX];
607 struct list_head rx_done, tx_free;
608 struct sk_buff_head tx_queue, rx_queue;
609 spinlock_t rx_lock, tx_lock;
610 struct delayed_work schedule, hw_phy_work;
611 struct mii_if_info mii;
612 struct mutex control; /* use for hw setting */
613 #ifdef CONFIG_PM_SLEEP
614 struct notifier_block pm_notifier;
615 #endif
616
617 struct rtl_ops {
618 void (*init)(struct r8152 *);
619 int (*enable)(struct r8152 *);
620 void (*disable)(struct r8152 *);
621 void (*up)(struct r8152 *);
622 void (*down)(struct r8152 *);
623 void (*unload)(struct r8152 *);
624 int (*eee_get)(struct r8152 *, struct ethtool_eee *);
625 int (*eee_set)(struct r8152 *, struct ethtool_eee *);
626 bool (*in_nway)(struct r8152 *);
627 void (*hw_phy_cfg)(struct r8152 *);
628 void (*autosuspend_en)(struct r8152 *tp, bool enable);
629 } rtl_ops;
630
631 int intr_interval;
632 u32 saved_wolopts;
633 u32 msg_enable;
634 u32 tx_qlen;
635 u32 coalesce;
636 u16 ocp_base;
637 u16 speed;
638 u8 *intr_buff;
639 u8 version;
640 u8 duplex;
641 u8 autoneg;
642 };
643
644 enum rtl_version {
645 RTL_VER_UNKNOWN = 0,
646 RTL_VER_01,
647 RTL_VER_02,
648 RTL_VER_03,
649 RTL_VER_04,
650 RTL_VER_05,
651 RTL_VER_06,
652 RTL_VER_MAX
653 };
654
655 enum tx_csum_stat {
656 TX_CSUM_SUCCESS = 0,
657 TX_CSUM_TSO,
658 TX_CSUM_NONE
659 };
660
661 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
662 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
663 */
664 static const int multicast_filter_limit = 32;
665 static unsigned int agg_buf_sz = 16384;
666
667 #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \
668 VLAN_ETH_HLEN - VLAN_HLEN)
669
670 static
671 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
672 {
673 int ret;
674 void *tmp;
675
676 tmp = kmalloc(size, GFP_KERNEL);
677 if (!tmp)
678 return -ENOMEM;
679
680 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
681 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
682 value, index, tmp, size, 500);
683
684 memcpy(data, tmp, size);
685 kfree(tmp);
686
687 return ret;
688 }
689
690 static
691 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
692 {
693 int ret;
694 void *tmp;
695
696 tmp = kmemdup(data, size, GFP_KERNEL);
697 if (!tmp)
698 return -ENOMEM;
699
700 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
701 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
702 value, index, tmp, size, 500);
703
704 kfree(tmp);
705
706 return ret;
707 }
708
709 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
710 void *data, u16 type)
711 {
712 u16 limit = 64;
713 int ret = 0;
714
715 if (test_bit(RTL8152_UNPLUG, &tp->flags))
716 return -ENODEV;
717
718 /* both size and indix must be 4 bytes align */
719 if ((size & 3) || !size || (index & 3) || !data)
720 return -EPERM;
721
722 if ((u32)index + (u32)size > 0xffff)
723 return -EPERM;
724
725 while (size) {
726 if (size > limit) {
727 ret = get_registers(tp, index, type, limit, data);
728 if (ret < 0)
729 break;
730
731 index += limit;
732 data += limit;
733 size -= limit;
734 } else {
735 ret = get_registers(tp, index, type, size, data);
736 if (ret < 0)
737 break;
738
739 index += size;
740 data += size;
741 size = 0;
742 break;
743 }
744 }
745
746 if (ret == -ENODEV)
747 set_bit(RTL8152_UNPLUG, &tp->flags);
748
749 return ret;
750 }
751
752 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
753 u16 size, void *data, u16 type)
754 {
755 int ret;
756 u16 byteen_start, byteen_end, byen;
757 u16 limit = 512;
758
759 if (test_bit(RTL8152_UNPLUG, &tp->flags))
760 return -ENODEV;
761
762 /* both size and indix must be 4 bytes align */
763 if ((size & 3) || !size || (index & 3) || !data)
764 return -EPERM;
765
766 if ((u32)index + (u32)size > 0xffff)
767 return -EPERM;
768
769 byteen_start = byteen & BYTE_EN_START_MASK;
770 byteen_end = byteen & BYTE_EN_END_MASK;
771
772 byen = byteen_start | (byteen_start << 4);
773 ret = set_registers(tp, index, type | byen, 4, data);
774 if (ret < 0)
775 goto error1;
776
777 index += 4;
778 data += 4;
779 size -= 4;
780
781 if (size) {
782 size -= 4;
783
784 while (size) {
785 if (size > limit) {
786 ret = set_registers(tp, index,
787 type | BYTE_EN_DWORD,
788 limit, data);
789 if (ret < 0)
790 goto error1;
791
792 index += limit;
793 data += limit;
794 size -= limit;
795 } else {
796 ret = set_registers(tp, index,
797 type | BYTE_EN_DWORD,
798 size, data);
799 if (ret < 0)
800 goto error1;
801
802 index += size;
803 data += size;
804 size = 0;
805 break;
806 }
807 }
808
809 byen = byteen_end | (byteen_end >> 4);
810 ret = set_registers(tp, index, type | byen, 4, data);
811 if (ret < 0)
812 goto error1;
813 }
814
815 error1:
816 if (ret == -ENODEV)
817 set_bit(RTL8152_UNPLUG, &tp->flags);
818
819 return ret;
820 }
821
822 static inline
823 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
824 {
825 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
826 }
827
828 static inline
829 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
830 {
831 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
832 }
833
834 static inline
835 int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
836 {
837 return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
838 }
839
840 static inline
841 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
842 {
843 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
844 }
845
846 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
847 {
848 __le32 data;
849
850 generic_ocp_read(tp, index, sizeof(data), &data, type);
851
852 return __le32_to_cpu(data);
853 }
854
855 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
856 {
857 __le32 tmp = __cpu_to_le32(data);
858
859 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
860 }
861
862 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
863 {
864 u32 data;
865 __le32 tmp;
866 u8 shift = index & 2;
867
868 index &= ~3;
869
870 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
871
872 data = __le32_to_cpu(tmp);
873 data >>= (shift * 8);
874 data &= 0xffff;
875
876 return (u16)data;
877 }
878
879 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
880 {
881 u32 mask = 0xffff;
882 __le32 tmp;
883 u16 byen = BYTE_EN_WORD;
884 u8 shift = index & 2;
885
886 data &= mask;
887
888 if (index & 2) {
889 byen <<= shift;
890 mask <<= (shift * 8);
891 data <<= (shift * 8);
892 index &= ~3;
893 }
894
895 tmp = __cpu_to_le32(data);
896
897 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
898 }
899
900 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
901 {
902 u32 data;
903 __le32 tmp;
904 u8 shift = index & 3;
905
906 index &= ~3;
907
908 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
909
910 data = __le32_to_cpu(tmp);
911 data >>= (shift * 8);
912 data &= 0xff;
913
914 return (u8)data;
915 }
916
917 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
918 {
919 u32 mask = 0xff;
920 __le32 tmp;
921 u16 byen = BYTE_EN_BYTE;
922 u8 shift = index & 3;
923
924 data &= mask;
925
926 if (index & 3) {
927 byen <<= shift;
928 mask <<= (shift * 8);
929 data <<= (shift * 8);
930 index &= ~3;
931 }
932
933 tmp = __cpu_to_le32(data);
934
935 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
936 }
937
938 static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
939 {
940 u16 ocp_base, ocp_index;
941
942 ocp_base = addr & 0xf000;
943 if (ocp_base != tp->ocp_base) {
944 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
945 tp->ocp_base = ocp_base;
946 }
947
948 ocp_index = (addr & 0x0fff) | 0xb000;
949 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
950 }
951
952 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
953 {
954 u16 ocp_base, ocp_index;
955
956 ocp_base = addr & 0xf000;
957 if (ocp_base != tp->ocp_base) {
958 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
959 tp->ocp_base = ocp_base;
960 }
961
962 ocp_index = (addr & 0x0fff) | 0xb000;
963 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
964 }
965
966 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
967 {
968 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
969 }
970
971 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
972 {
973 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
974 }
975
976 static void sram_write(struct r8152 *tp, u16 addr, u16 data)
977 {
978 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
979 ocp_reg_write(tp, OCP_SRAM_DATA, data);
980 }
981
982 static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
983 {
984 struct r8152 *tp = netdev_priv(netdev);
985 int ret;
986
987 if (test_bit(RTL8152_UNPLUG, &tp->flags))
988 return -ENODEV;
989
990 if (phy_id != R8152_PHY_ID)
991 return -EINVAL;
992
993 ret = r8152_mdio_read(tp, reg);
994
995 return ret;
996 }
997
998 static
999 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
1000 {
1001 struct r8152 *tp = netdev_priv(netdev);
1002
1003 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1004 return;
1005
1006 if (phy_id != R8152_PHY_ID)
1007 return;
1008
1009 r8152_mdio_write(tp, reg, val);
1010 }
1011
1012 static int
1013 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
1014
1015 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
1016 {
1017 struct r8152 *tp = netdev_priv(netdev);
1018 struct sockaddr *addr = p;
1019 int ret = -EADDRNOTAVAIL;
1020
1021 if (!is_valid_ether_addr(addr->sa_data))
1022 goto out1;
1023
1024 ret = usb_autopm_get_interface(tp->intf);
1025 if (ret < 0)
1026 goto out1;
1027
1028 mutex_lock(&tp->control);
1029
1030 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1031
1032 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1033 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
1034 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1035
1036 mutex_unlock(&tp->control);
1037
1038 usb_autopm_put_interface(tp->intf);
1039 out1:
1040 return ret;
1041 }
1042
1043 static int set_ethernet_addr(struct r8152 *tp)
1044 {
1045 struct net_device *dev = tp->netdev;
1046 struct sockaddr sa;
1047 int ret;
1048
1049 if (tp->version == RTL_VER_01)
1050 ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data);
1051 else
1052 ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data);
1053
1054 if (ret < 0) {
1055 netif_err(tp, probe, dev, "Get ether addr fail\n");
1056 } else if (!is_valid_ether_addr(sa.sa_data)) {
1057 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1058 sa.sa_data);
1059 eth_hw_addr_random(dev);
1060 ether_addr_copy(sa.sa_data, dev->dev_addr);
1061 ret = rtl8152_set_mac_address(dev, &sa);
1062 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1063 sa.sa_data);
1064 } else {
1065 if (tp->version == RTL_VER_01)
1066 ether_addr_copy(dev->dev_addr, sa.sa_data);
1067 else
1068 ret = rtl8152_set_mac_address(dev, &sa);
1069 }
1070
1071 return ret;
1072 }
1073
1074 static void read_bulk_callback(struct urb *urb)
1075 {
1076 struct net_device *netdev;
1077 int status = urb->status;
1078 struct rx_agg *agg;
1079 struct r8152 *tp;
1080
1081 agg = urb->context;
1082 if (!agg)
1083 return;
1084
1085 tp = agg->context;
1086 if (!tp)
1087 return;
1088
1089 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1090 return;
1091
1092 if (!test_bit(WORK_ENABLE, &tp->flags))
1093 return;
1094
1095 netdev = tp->netdev;
1096
1097 /* When link down, the driver would cancel all bulks. */
1098 /* This avoid the re-submitting bulk */
1099 if (!netif_carrier_ok(netdev))
1100 return;
1101
1102 usb_mark_last_busy(tp->udev);
1103
1104 switch (status) {
1105 case 0:
1106 if (urb->actual_length < ETH_ZLEN)
1107 break;
1108
1109 spin_lock(&tp->rx_lock);
1110 list_add_tail(&agg->list, &tp->rx_done);
1111 spin_unlock(&tp->rx_lock);
1112 napi_schedule(&tp->napi);
1113 return;
1114 case -ESHUTDOWN:
1115 set_bit(RTL8152_UNPLUG, &tp->flags);
1116 netif_device_detach(tp->netdev);
1117 return;
1118 case -ENOENT:
1119 return; /* the urb is in unlink state */
1120 case -ETIME:
1121 if (net_ratelimit())
1122 netdev_warn(netdev, "maybe reset is needed?\n");
1123 break;
1124 default:
1125 if (net_ratelimit())
1126 netdev_warn(netdev, "Rx status %d\n", status);
1127 break;
1128 }
1129
1130 r8152_submit_rx(tp, agg, GFP_ATOMIC);
1131 }
1132
1133 static void write_bulk_callback(struct urb *urb)
1134 {
1135 struct net_device_stats *stats;
1136 struct net_device *netdev;
1137 struct tx_agg *agg;
1138 struct r8152 *tp;
1139 int status = urb->status;
1140
1141 agg = urb->context;
1142 if (!agg)
1143 return;
1144
1145 tp = agg->context;
1146 if (!tp)
1147 return;
1148
1149 netdev = tp->netdev;
1150 stats = &netdev->stats;
1151 if (status) {
1152 if (net_ratelimit())
1153 netdev_warn(netdev, "Tx status %d\n", status);
1154 stats->tx_errors += agg->skb_num;
1155 } else {
1156 stats->tx_packets += agg->skb_num;
1157 stats->tx_bytes += agg->skb_len;
1158 }
1159
1160 spin_lock(&tp->tx_lock);
1161 list_add_tail(&agg->list, &tp->tx_free);
1162 spin_unlock(&tp->tx_lock);
1163
1164 usb_autopm_put_interface_async(tp->intf);
1165
1166 if (!netif_carrier_ok(netdev))
1167 return;
1168
1169 if (!test_bit(WORK_ENABLE, &tp->flags))
1170 return;
1171
1172 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1173 return;
1174
1175 if (!skb_queue_empty(&tp->tx_queue))
1176 napi_schedule(&tp->napi);
1177 }
1178
1179 static void intr_callback(struct urb *urb)
1180 {
1181 struct r8152 *tp;
1182 __le16 *d;
1183 int status = urb->status;
1184 int res;
1185
1186 tp = urb->context;
1187 if (!tp)
1188 return;
1189
1190 if (!test_bit(WORK_ENABLE, &tp->flags))
1191 return;
1192
1193 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1194 return;
1195
1196 switch (status) {
1197 case 0: /* success */
1198 break;
1199 case -ECONNRESET: /* unlink */
1200 case -ESHUTDOWN:
1201 netif_device_detach(tp->netdev);
1202 case -ENOENT:
1203 case -EPROTO:
1204 netif_info(tp, intr, tp->netdev,
1205 "Stop submitting intr, status %d\n", status);
1206 return;
1207 case -EOVERFLOW:
1208 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1209 goto resubmit;
1210 /* -EPIPE: should clear the halt */
1211 default:
1212 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1213 goto resubmit;
1214 }
1215
1216 d = urb->transfer_buffer;
1217 if (INTR_LINK & __le16_to_cpu(d[0])) {
1218 if (!netif_carrier_ok(tp->netdev)) {
1219 set_bit(RTL8152_LINK_CHG, &tp->flags);
1220 schedule_delayed_work(&tp->schedule, 0);
1221 }
1222 } else {
1223 if (netif_carrier_ok(tp->netdev)) {
1224 set_bit(RTL8152_LINK_CHG, &tp->flags);
1225 schedule_delayed_work(&tp->schedule, 0);
1226 }
1227 }
1228
1229 resubmit:
1230 res = usb_submit_urb(urb, GFP_ATOMIC);
1231 if (res == -ENODEV) {
1232 set_bit(RTL8152_UNPLUG, &tp->flags);
1233 netif_device_detach(tp->netdev);
1234 } else if (res) {
1235 netif_err(tp, intr, tp->netdev,
1236 "can't resubmit intr, status %d\n", res);
1237 }
1238 }
1239
1240 static inline void *rx_agg_align(void *data)
1241 {
1242 return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1243 }
1244
1245 static inline void *tx_agg_align(void *data)
1246 {
1247 return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1248 }
1249
1250 static void free_all_mem(struct r8152 *tp)
1251 {
1252 int i;
1253
1254 for (i = 0; i < RTL8152_MAX_RX; i++) {
1255 usb_free_urb(tp->rx_info[i].urb);
1256 tp->rx_info[i].urb = NULL;
1257
1258 kfree(tp->rx_info[i].buffer);
1259 tp->rx_info[i].buffer = NULL;
1260 tp->rx_info[i].head = NULL;
1261 }
1262
1263 for (i = 0; i < RTL8152_MAX_TX; i++) {
1264 usb_free_urb(tp->tx_info[i].urb);
1265 tp->tx_info[i].urb = NULL;
1266
1267 kfree(tp->tx_info[i].buffer);
1268 tp->tx_info[i].buffer = NULL;
1269 tp->tx_info[i].head = NULL;
1270 }
1271
1272 usb_free_urb(tp->intr_urb);
1273 tp->intr_urb = NULL;
1274
1275 kfree(tp->intr_buff);
1276 tp->intr_buff = NULL;
1277 }
1278
1279 static int alloc_all_mem(struct r8152 *tp)
1280 {
1281 struct net_device *netdev = tp->netdev;
1282 struct usb_interface *intf = tp->intf;
1283 struct usb_host_interface *alt = intf->cur_altsetting;
1284 struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
1285 struct urb *urb;
1286 int node, i;
1287 u8 *buf;
1288
1289 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1290
1291 spin_lock_init(&tp->rx_lock);
1292 spin_lock_init(&tp->tx_lock);
1293 INIT_LIST_HEAD(&tp->tx_free);
1294 skb_queue_head_init(&tp->tx_queue);
1295 skb_queue_head_init(&tp->rx_queue);
1296
1297 for (i = 0; i < RTL8152_MAX_RX; i++) {
1298 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1299 if (!buf)
1300 goto err1;
1301
1302 if (buf != rx_agg_align(buf)) {
1303 kfree(buf);
1304 buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL,
1305 node);
1306 if (!buf)
1307 goto err1;
1308 }
1309
1310 urb = usb_alloc_urb(0, GFP_KERNEL);
1311 if (!urb) {
1312 kfree(buf);
1313 goto err1;
1314 }
1315
1316 INIT_LIST_HEAD(&tp->rx_info[i].list);
1317 tp->rx_info[i].context = tp;
1318 tp->rx_info[i].urb = urb;
1319 tp->rx_info[i].buffer = buf;
1320 tp->rx_info[i].head = rx_agg_align(buf);
1321 }
1322
1323 for (i = 0; i < RTL8152_MAX_TX; i++) {
1324 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1325 if (!buf)
1326 goto err1;
1327
1328 if (buf != tx_agg_align(buf)) {
1329 kfree(buf);
1330 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
1331 node);
1332 if (!buf)
1333 goto err1;
1334 }
1335
1336 urb = usb_alloc_urb(0, GFP_KERNEL);
1337 if (!urb) {
1338 kfree(buf);
1339 goto err1;
1340 }
1341
1342 INIT_LIST_HEAD(&tp->tx_info[i].list);
1343 tp->tx_info[i].context = tp;
1344 tp->tx_info[i].urb = urb;
1345 tp->tx_info[i].buffer = buf;
1346 tp->tx_info[i].head = tx_agg_align(buf);
1347
1348 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1349 }
1350
1351 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1352 if (!tp->intr_urb)
1353 goto err1;
1354
1355 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1356 if (!tp->intr_buff)
1357 goto err1;
1358
1359 tp->intr_interval = (int)ep_intr->desc.bInterval;
1360 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
1361 tp->intr_buff, INTBUFSIZE, intr_callback,
1362 tp, tp->intr_interval);
1363
1364 return 0;
1365
1366 err1:
1367 free_all_mem(tp);
1368 return -ENOMEM;
1369 }
1370
1371 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1372 {
1373 struct tx_agg *agg = NULL;
1374 unsigned long flags;
1375
1376 if (list_empty(&tp->tx_free))
1377 return NULL;
1378
1379 spin_lock_irqsave(&tp->tx_lock, flags);
1380 if (!list_empty(&tp->tx_free)) {
1381 struct list_head *cursor;
1382
1383 cursor = tp->tx_free.next;
1384 list_del_init(cursor);
1385 agg = list_entry(cursor, struct tx_agg, list);
1386 }
1387 spin_unlock_irqrestore(&tp->tx_lock, flags);
1388
1389 return agg;
1390 }
1391
1392 /* r8152_csum_workaround()
1393 * The hw limites the value the transport offset. When the offset is out of the
1394 * range, calculate the checksum by sw.
1395 */
1396 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1397 struct sk_buff_head *list)
1398 {
1399 if (skb_shinfo(skb)->gso_size) {
1400 netdev_features_t features = tp->netdev->features;
1401 struct sk_buff_head seg_list;
1402 struct sk_buff *segs, *nskb;
1403
1404 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
1405 segs = skb_gso_segment(skb, features);
1406 if (IS_ERR(segs) || !segs)
1407 goto drop;
1408
1409 __skb_queue_head_init(&seg_list);
1410
1411 do {
1412 nskb = segs;
1413 segs = segs->next;
1414 nskb->next = NULL;
1415 __skb_queue_tail(&seg_list, nskb);
1416 } while (segs);
1417
1418 skb_queue_splice(&seg_list, list);
1419 dev_kfree_skb(skb);
1420 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1421 if (skb_checksum_help(skb) < 0)
1422 goto drop;
1423
1424 __skb_queue_head(list, skb);
1425 } else {
1426 struct net_device_stats *stats;
1427
1428 drop:
1429 stats = &tp->netdev->stats;
1430 stats->tx_dropped++;
1431 dev_kfree_skb(skb);
1432 }
1433 }
1434
1435 /* msdn_giant_send_check()
1436 * According to the document of microsoft, the TCP Pseudo Header excludes the
1437 * packet length for IPv6 TCP large packets.
1438 */
1439 static int msdn_giant_send_check(struct sk_buff *skb)
1440 {
1441 const struct ipv6hdr *ipv6h;
1442 struct tcphdr *th;
1443 int ret;
1444
1445 ret = skb_cow_head(skb, 0);
1446 if (ret)
1447 return ret;
1448
1449 ipv6h = ipv6_hdr(skb);
1450 th = tcp_hdr(skb);
1451
1452 th->check = 0;
1453 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
1454
1455 return ret;
1456 }
1457
1458 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
1459 {
1460 if (skb_vlan_tag_present(skb)) {
1461 u32 opts2;
1462
1463 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
1464 desc->opts2 |= cpu_to_le32(opts2);
1465 }
1466 }
1467
1468 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
1469 {
1470 u32 opts2 = le32_to_cpu(desc->opts2);
1471
1472 if (opts2 & RX_VLAN_TAG)
1473 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1474 swab16(opts2 & 0xffff));
1475 }
1476
1477 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1478 struct sk_buff *skb, u32 len, u32 transport_offset)
1479 {
1480 u32 mss = skb_shinfo(skb)->gso_size;
1481 u32 opts1, opts2 = 0;
1482 int ret = TX_CSUM_SUCCESS;
1483
1484 WARN_ON_ONCE(len > TX_LEN_MAX);
1485
1486 opts1 = len | TX_FS | TX_LS;
1487
1488 if (mss) {
1489 if (transport_offset > GTTCPHO_MAX) {
1490 netif_warn(tp, tx_err, tp->netdev,
1491 "Invalid transport offset 0x%x for TSO\n",
1492 transport_offset);
1493 ret = TX_CSUM_TSO;
1494 goto unavailable;
1495 }
1496
1497 switch (vlan_get_protocol(skb)) {
1498 case htons(ETH_P_IP):
1499 opts1 |= GTSENDV4;
1500 break;
1501
1502 case htons(ETH_P_IPV6):
1503 if (msdn_giant_send_check(skb)) {
1504 ret = TX_CSUM_TSO;
1505 goto unavailable;
1506 }
1507 opts1 |= GTSENDV6;
1508 break;
1509
1510 default:
1511 WARN_ON_ONCE(1);
1512 break;
1513 }
1514
1515 opts1 |= transport_offset << GTTCPHO_SHIFT;
1516 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
1517 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1518 u8 ip_protocol;
1519
1520 if (transport_offset > TCPHO_MAX) {
1521 netif_warn(tp, tx_err, tp->netdev,
1522 "Invalid transport offset 0x%x\n",
1523 transport_offset);
1524 ret = TX_CSUM_NONE;
1525 goto unavailable;
1526 }
1527
1528 switch (vlan_get_protocol(skb)) {
1529 case htons(ETH_P_IP):
1530 opts2 |= IPV4_CS;
1531 ip_protocol = ip_hdr(skb)->protocol;
1532 break;
1533
1534 case htons(ETH_P_IPV6):
1535 opts2 |= IPV6_CS;
1536 ip_protocol = ipv6_hdr(skb)->nexthdr;
1537 break;
1538
1539 default:
1540 ip_protocol = IPPROTO_RAW;
1541 break;
1542 }
1543
1544 if (ip_protocol == IPPROTO_TCP)
1545 opts2 |= TCP_CS;
1546 else if (ip_protocol == IPPROTO_UDP)
1547 opts2 |= UDP_CS;
1548 else
1549 WARN_ON_ONCE(1);
1550
1551 opts2 |= transport_offset << TCPHO_SHIFT;
1552 }
1553
1554 desc->opts2 = cpu_to_le32(opts2);
1555 desc->opts1 = cpu_to_le32(opts1);
1556
1557 unavailable:
1558 return ret;
1559 }
1560
1561 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
1562 {
1563 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1564 int remain, ret;
1565 u8 *tx_data;
1566
1567 __skb_queue_head_init(&skb_head);
1568 spin_lock(&tx_queue->lock);
1569 skb_queue_splice_init(tx_queue, &skb_head);
1570 spin_unlock(&tx_queue->lock);
1571
1572 tx_data = agg->head;
1573 agg->skb_num = 0;
1574 agg->skb_len = 0;
1575 remain = agg_buf_sz;
1576
1577 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
1578 struct tx_desc *tx_desc;
1579 struct sk_buff *skb;
1580 unsigned int len;
1581 u32 offset;
1582
1583 skb = __skb_dequeue(&skb_head);
1584 if (!skb)
1585 break;
1586
1587 len = skb->len + sizeof(*tx_desc);
1588
1589 if (len > remain) {
1590 __skb_queue_head(&skb_head, skb);
1591 break;
1592 }
1593
1594 tx_data = tx_agg_align(tx_data);
1595 tx_desc = (struct tx_desc *)tx_data;
1596
1597 offset = (u32)skb_transport_offset(skb);
1598
1599 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
1600 r8152_csum_workaround(tp, skb, &skb_head);
1601 continue;
1602 }
1603
1604 rtl_tx_vlan_tag(tx_desc, skb);
1605
1606 tx_data += sizeof(*tx_desc);
1607
1608 len = skb->len;
1609 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
1610 struct net_device_stats *stats = &tp->netdev->stats;
1611
1612 stats->tx_dropped++;
1613 dev_kfree_skb_any(skb);
1614 tx_data -= sizeof(*tx_desc);
1615 continue;
1616 }
1617
1618 tx_data += len;
1619 agg->skb_len += len;
1620 agg->skb_num++;
1621
1622 dev_kfree_skb_any(skb);
1623
1624 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
1625 }
1626
1627 if (!skb_queue_empty(&skb_head)) {
1628 spin_lock(&tx_queue->lock);
1629 skb_queue_splice(&skb_head, tx_queue);
1630 spin_unlock(&tx_queue->lock);
1631 }
1632
1633 netif_tx_lock(tp->netdev);
1634
1635 if (netif_queue_stopped(tp->netdev) &&
1636 skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
1637 netif_wake_queue(tp->netdev);
1638
1639 netif_tx_unlock(tp->netdev);
1640
1641 ret = usb_autopm_get_interface_async(tp->intf);
1642 if (ret < 0)
1643 goto out_tx_fill;
1644
1645 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1646 agg->head, (int)(tx_data - (u8 *)agg->head),
1647 (usb_complete_t)write_bulk_callback, agg);
1648
1649 ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
1650 if (ret < 0)
1651 usb_autopm_put_interface_async(tp->intf);
1652
1653 out_tx_fill:
1654 return ret;
1655 }
1656
1657 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
1658 {
1659 u8 checksum = CHECKSUM_NONE;
1660 u32 opts2, opts3;
1661
1662 if (tp->version == RTL_VER_01)
1663 goto return_result;
1664
1665 opts2 = le32_to_cpu(rx_desc->opts2);
1666 opts3 = le32_to_cpu(rx_desc->opts3);
1667
1668 if (opts2 & RD_IPV4_CS) {
1669 if (opts3 & IPF)
1670 checksum = CHECKSUM_NONE;
1671 else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF))
1672 checksum = CHECKSUM_NONE;
1673 else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF))
1674 checksum = CHECKSUM_NONE;
1675 else
1676 checksum = CHECKSUM_UNNECESSARY;
1677 } else if (RD_IPV6_CS) {
1678 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
1679 checksum = CHECKSUM_UNNECESSARY;
1680 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
1681 checksum = CHECKSUM_UNNECESSARY;
1682 }
1683
1684 return_result:
1685 return checksum;
1686 }
1687
1688 static int rx_bottom(struct r8152 *tp, int budget)
1689 {
1690 unsigned long flags;
1691 struct list_head *cursor, *next, rx_queue;
1692 int ret = 0, work_done = 0;
1693
1694 if (!skb_queue_empty(&tp->rx_queue)) {
1695 while (work_done < budget) {
1696 struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
1697 struct net_device *netdev = tp->netdev;
1698 struct net_device_stats *stats = &netdev->stats;
1699 unsigned int pkt_len;
1700
1701 if (!skb)
1702 break;
1703
1704 pkt_len = skb->len;
1705 napi_gro_receive(&tp->napi, skb);
1706 work_done++;
1707 stats->rx_packets++;
1708 stats->rx_bytes += pkt_len;
1709 }
1710 }
1711
1712 if (list_empty(&tp->rx_done))
1713 goto out1;
1714
1715 INIT_LIST_HEAD(&rx_queue);
1716 spin_lock_irqsave(&tp->rx_lock, flags);
1717 list_splice_init(&tp->rx_done, &rx_queue);
1718 spin_unlock_irqrestore(&tp->rx_lock, flags);
1719
1720 list_for_each_safe(cursor, next, &rx_queue) {
1721 struct rx_desc *rx_desc;
1722 struct rx_agg *agg;
1723 int len_used = 0;
1724 struct urb *urb;
1725 u8 *rx_data;
1726
1727 list_del_init(cursor);
1728
1729 agg = list_entry(cursor, struct rx_agg, list);
1730 urb = agg->urb;
1731 if (urb->actual_length < ETH_ZLEN)
1732 goto submit;
1733
1734 rx_desc = agg->head;
1735 rx_data = agg->head;
1736 len_used += sizeof(struct rx_desc);
1737
1738 while (urb->actual_length > len_used) {
1739 struct net_device *netdev = tp->netdev;
1740 struct net_device_stats *stats = &netdev->stats;
1741 unsigned int pkt_len;
1742 struct sk_buff *skb;
1743
1744 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1745 if (pkt_len < ETH_ZLEN)
1746 break;
1747
1748 len_used += pkt_len;
1749 if (urb->actual_length < len_used)
1750 break;
1751
1752 pkt_len -= CRC_SIZE;
1753 rx_data += sizeof(struct rx_desc);
1754
1755 skb = napi_alloc_skb(&tp->napi, pkt_len);
1756 if (!skb) {
1757 stats->rx_dropped++;
1758 goto find_next_rx;
1759 }
1760
1761 skb->ip_summed = r8152_rx_csum(tp, rx_desc);
1762 memcpy(skb->data, rx_data, pkt_len);
1763 skb_put(skb, pkt_len);
1764 skb->protocol = eth_type_trans(skb, netdev);
1765 rtl_rx_vlan_tag(rx_desc, skb);
1766 if (work_done < budget) {
1767 napi_gro_receive(&tp->napi, skb);
1768 work_done++;
1769 stats->rx_packets++;
1770 stats->rx_bytes += pkt_len;
1771 } else {
1772 __skb_queue_tail(&tp->rx_queue, skb);
1773 }
1774
1775 find_next_rx:
1776 rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE);
1777 rx_desc = (struct rx_desc *)rx_data;
1778 len_used = (int)(rx_data - (u8 *)agg->head);
1779 len_used += sizeof(struct rx_desc);
1780 }
1781
1782 submit:
1783 if (!ret) {
1784 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
1785 } else {
1786 urb->actual_length = 0;
1787 list_add_tail(&agg->list, next);
1788 }
1789 }
1790
1791 if (!list_empty(&rx_queue)) {
1792 spin_lock_irqsave(&tp->rx_lock, flags);
1793 list_splice_tail(&rx_queue, &tp->rx_done);
1794 spin_unlock_irqrestore(&tp->rx_lock, flags);
1795 }
1796
1797 out1:
1798 return work_done;
1799 }
1800
1801 static void tx_bottom(struct r8152 *tp)
1802 {
1803 int res;
1804
1805 do {
1806 struct tx_agg *agg;
1807
1808 if (skb_queue_empty(&tp->tx_queue))
1809 break;
1810
1811 agg = r8152_get_tx_agg(tp);
1812 if (!agg)
1813 break;
1814
1815 res = r8152_tx_agg_fill(tp, agg);
1816 if (res) {
1817 struct net_device *netdev = tp->netdev;
1818
1819 if (res == -ENODEV) {
1820 set_bit(RTL8152_UNPLUG, &tp->flags);
1821 netif_device_detach(netdev);
1822 } else {
1823 struct net_device_stats *stats = &netdev->stats;
1824 unsigned long flags;
1825
1826 netif_warn(tp, tx_err, netdev,
1827 "failed tx_urb %d\n", res);
1828 stats->tx_dropped += agg->skb_num;
1829
1830 spin_lock_irqsave(&tp->tx_lock, flags);
1831 list_add_tail(&agg->list, &tp->tx_free);
1832 spin_unlock_irqrestore(&tp->tx_lock, flags);
1833 }
1834 }
1835 } while (res == 0);
1836 }
1837
1838 static void bottom_half(struct r8152 *tp)
1839 {
1840 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1841 return;
1842
1843 if (!test_bit(WORK_ENABLE, &tp->flags))
1844 return;
1845
1846 /* When link down, the driver would cancel all bulks. */
1847 /* This avoid the re-submitting bulk */
1848 if (!netif_carrier_ok(tp->netdev))
1849 return;
1850
1851 clear_bit(SCHEDULE_NAPI, &tp->flags);
1852
1853 tx_bottom(tp);
1854 }
1855
1856 static int r8152_poll(struct napi_struct *napi, int budget)
1857 {
1858 struct r8152 *tp = container_of(napi, struct r8152, napi);
1859 int work_done;
1860
1861 work_done = rx_bottom(tp, budget);
1862 bottom_half(tp);
1863
1864 if (work_done < budget) {
1865 napi_complete(napi);
1866 if (!list_empty(&tp->rx_done))
1867 napi_schedule(napi);
1868 }
1869
1870 return work_done;
1871 }
1872
1873 static
1874 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
1875 {
1876 int ret;
1877
1878 /* The rx would be stopped, so skip submitting */
1879 if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
1880 !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
1881 return 0;
1882
1883 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
1884 agg->head, agg_buf_sz,
1885 (usb_complete_t)read_bulk_callback, agg);
1886
1887 ret = usb_submit_urb(agg->urb, mem_flags);
1888 if (ret == -ENODEV) {
1889 set_bit(RTL8152_UNPLUG, &tp->flags);
1890 netif_device_detach(tp->netdev);
1891 } else if (ret) {
1892 struct urb *urb = agg->urb;
1893 unsigned long flags;
1894
1895 urb->actual_length = 0;
1896 spin_lock_irqsave(&tp->rx_lock, flags);
1897 list_add_tail(&agg->list, &tp->rx_done);
1898 spin_unlock_irqrestore(&tp->rx_lock, flags);
1899
1900 netif_err(tp, rx_err, tp->netdev,
1901 "Couldn't submit rx[%p], ret = %d\n", agg, ret);
1902
1903 napi_schedule(&tp->napi);
1904 }
1905
1906 return ret;
1907 }
1908
1909 static void rtl_drop_queued_tx(struct r8152 *tp)
1910 {
1911 struct net_device_stats *stats = &tp->netdev->stats;
1912 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1913 struct sk_buff *skb;
1914
1915 if (skb_queue_empty(tx_queue))
1916 return;
1917
1918 __skb_queue_head_init(&skb_head);
1919 spin_lock_bh(&tx_queue->lock);
1920 skb_queue_splice_init(tx_queue, &skb_head);
1921 spin_unlock_bh(&tx_queue->lock);
1922
1923 while ((skb = __skb_dequeue(&skb_head))) {
1924 dev_kfree_skb(skb);
1925 stats->tx_dropped++;
1926 }
1927 }
1928
1929 static void rtl8152_tx_timeout(struct net_device *netdev)
1930 {
1931 struct r8152 *tp = netdev_priv(netdev);
1932
1933 netif_warn(tp, tx_err, netdev, "Tx timeout\n");
1934
1935 usb_queue_reset_device(tp->intf);
1936 }
1937
1938 static void rtl8152_set_rx_mode(struct net_device *netdev)
1939 {
1940 struct r8152 *tp = netdev_priv(netdev);
1941
1942 if (netif_carrier_ok(netdev)) {
1943 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
1944 schedule_delayed_work(&tp->schedule, 0);
1945 }
1946 }
1947
1948 static void _rtl8152_set_rx_mode(struct net_device *netdev)
1949 {
1950 struct r8152 *tp = netdev_priv(netdev);
1951 u32 mc_filter[2]; /* Multicast hash filter */
1952 __le32 tmp[2];
1953 u32 ocp_data;
1954
1955 netif_stop_queue(netdev);
1956 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1957 ocp_data &= ~RCR_ACPT_ALL;
1958 ocp_data |= RCR_AB | RCR_APM;
1959
1960 if (netdev->flags & IFF_PROMISC) {
1961 /* Unconditionally log net taps. */
1962 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
1963 ocp_data |= RCR_AM | RCR_AAP;
1964 mc_filter[1] = 0xffffffff;
1965 mc_filter[0] = 0xffffffff;
1966 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
1967 (netdev->flags & IFF_ALLMULTI)) {
1968 /* Too many to filter perfectly -- accept all multicasts. */
1969 ocp_data |= RCR_AM;
1970 mc_filter[1] = 0xffffffff;
1971 mc_filter[0] = 0xffffffff;
1972 } else {
1973 struct netdev_hw_addr *ha;
1974
1975 mc_filter[1] = 0;
1976 mc_filter[0] = 0;
1977 netdev_for_each_mc_addr(ha, netdev) {
1978 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1979
1980 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1981 ocp_data |= RCR_AM;
1982 }
1983 }
1984
1985 tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
1986 tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
1987
1988 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
1989 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1990 netif_wake_queue(netdev);
1991 }
1992
1993 static netdev_features_t
1994 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
1995 netdev_features_t features)
1996 {
1997 u32 mss = skb_shinfo(skb)->gso_size;
1998 int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
1999 int offset = skb_transport_offset(skb);
2000
2001 if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
2002 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2003 else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
2004 features &= ~NETIF_F_GSO_MASK;
2005
2006 return features;
2007 }
2008
2009 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
2010 struct net_device *netdev)
2011 {
2012 struct r8152 *tp = netdev_priv(netdev);
2013
2014 skb_tx_timestamp(skb);
2015
2016 skb_queue_tail(&tp->tx_queue, skb);
2017
2018 if (!list_empty(&tp->tx_free)) {
2019 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2020 set_bit(SCHEDULE_NAPI, &tp->flags);
2021 schedule_delayed_work(&tp->schedule, 0);
2022 } else {
2023 usb_mark_last_busy(tp->udev);
2024 napi_schedule(&tp->napi);
2025 }
2026 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
2027 netif_stop_queue(netdev);
2028 }
2029
2030 return NETDEV_TX_OK;
2031 }
2032
2033 static void r8152b_reset_packet_filter(struct r8152 *tp)
2034 {
2035 u32 ocp_data;
2036
2037 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
2038 ocp_data &= ~FMC_FCR_MCU_EN;
2039 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2040 ocp_data |= FMC_FCR_MCU_EN;
2041 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2042 }
2043
2044 static void rtl8152_nic_reset(struct r8152 *tp)
2045 {
2046 int i;
2047
2048 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
2049
2050 for (i = 0; i < 1000; i++) {
2051 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
2052 break;
2053 usleep_range(100, 400);
2054 }
2055 }
2056
2057 static void set_tx_qlen(struct r8152 *tp)
2058 {
2059 struct net_device *netdev = tp->netdev;
2060
2061 tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN +
2062 sizeof(struct tx_desc));
2063 }
2064
2065 static inline u8 rtl8152_get_speed(struct r8152 *tp)
2066 {
2067 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
2068 }
2069
2070 static void rtl_set_eee_plus(struct r8152 *tp)
2071 {
2072 u32 ocp_data;
2073 u8 speed;
2074
2075 speed = rtl8152_get_speed(tp);
2076 if (speed & _10bps) {
2077 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2078 ocp_data |= EEEP_CR_EEEP_TX;
2079 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2080 } else {
2081 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2082 ocp_data &= ~EEEP_CR_EEEP_TX;
2083 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2084 }
2085 }
2086
2087 static void rxdy_gated_en(struct r8152 *tp, bool enable)
2088 {
2089 u32 ocp_data;
2090
2091 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
2092 if (enable)
2093 ocp_data |= RXDY_GATED_EN;
2094 else
2095 ocp_data &= ~RXDY_GATED_EN;
2096 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
2097 }
2098
2099 static int rtl_start_rx(struct r8152 *tp)
2100 {
2101 int i, ret = 0;
2102
2103 INIT_LIST_HEAD(&tp->rx_done);
2104 for (i = 0; i < RTL8152_MAX_RX; i++) {
2105 INIT_LIST_HEAD(&tp->rx_info[i].list);
2106 ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
2107 if (ret)
2108 break;
2109 }
2110
2111 if (ret && ++i < RTL8152_MAX_RX) {
2112 struct list_head rx_queue;
2113 unsigned long flags;
2114
2115 INIT_LIST_HEAD(&rx_queue);
2116
2117 do {
2118 struct rx_agg *agg = &tp->rx_info[i++];
2119 struct urb *urb = agg->urb;
2120
2121 urb->actual_length = 0;
2122 list_add_tail(&agg->list, &rx_queue);
2123 } while (i < RTL8152_MAX_RX);
2124
2125 spin_lock_irqsave(&tp->rx_lock, flags);
2126 list_splice_tail(&rx_queue, &tp->rx_done);
2127 spin_unlock_irqrestore(&tp->rx_lock, flags);
2128 }
2129
2130 return ret;
2131 }
2132
2133 static int rtl_stop_rx(struct r8152 *tp)
2134 {
2135 int i;
2136
2137 for (i = 0; i < RTL8152_MAX_RX; i++)
2138 usb_kill_urb(tp->rx_info[i].urb);
2139
2140 while (!skb_queue_empty(&tp->rx_queue))
2141 dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
2142
2143 return 0;
2144 }
2145
2146 static int rtl_enable(struct r8152 *tp)
2147 {
2148 u32 ocp_data;
2149
2150 r8152b_reset_packet_filter(tp);
2151
2152 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2153 ocp_data |= CR_RE | CR_TE;
2154 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2155
2156 rxdy_gated_en(tp, false);
2157
2158 return 0;
2159 }
2160
2161 static int rtl8152_enable(struct r8152 *tp)
2162 {
2163 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2164 return -ENODEV;
2165
2166 set_tx_qlen(tp);
2167 rtl_set_eee_plus(tp);
2168
2169 return rtl_enable(tp);
2170 }
2171
2172 static void r8153_set_rx_early_timeout(struct r8152 *tp)
2173 {
2174 u32 ocp_data = tp->coalesce / 8;
2175
2176 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, ocp_data);
2177 }
2178
2179 static void r8153_set_rx_early_size(struct r8152 *tp)
2180 {
2181 u32 mtu = tp->netdev->mtu;
2182 u32 ocp_data = (agg_buf_sz - mtu - VLAN_ETH_HLEN - VLAN_HLEN) / 8;
2183
2184 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, ocp_data);
2185 }
2186
2187 static int rtl8153_enable(struct r8152 *tp)
2188 {
2189 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2190 return -ENODEV;
2191
2192 usb_disable_lpm(tp->udev);
2193 set_tx_qlen(tp);
2194 rtl_set_eee_plus(tp);
2195 r8153_set_rx_early_timeout(tp);
2196 r8153_set_rx_early_size(tp);
2197
2198 return rtl_enable(tp);
2199 }
2200
2201 static void rtl_disable(struct r8152 *tp)
2202 {
2203 u32 ocp_data;
2204 int i;
2205
2206 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2207 rtl_drop_queued_tx(tp);
2208 return;
2209 }
2210
2211 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2212 ocp_data &= ~RCR_ACPT_ALL;
2213 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2214
2215 rtl_drop_queued_tx(tp);
2216
2217 for (i = 0; i < RTL8152_MAX_TX; i++)
2218 usb_kill_urb(tp->tx_info[i].urb);
2219
2220 rxdy_gated_en(tp, true);
2221
2222 for (i = 0; i < 1000; i++) {
2223 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2224 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2225 break;
2226 usleep_range(1000, 2000);
2227 }
2228
2229 for (i = 0; i < 1000; i++) {
2230 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2231 break;
2232 usleep_range(1000, 2000);
2233 }
2234
2235 rtl_stop_rx(tp);
2236
2237 rtl8152_nic_reset(tp);
2238 }
2239
2240 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2241 {
2242 u32 ocp_data;
2243
2244 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2245 if (enable)
2246 ocp_data |= POWER_CUT;
2247 else
2248 ocp_data &= ~POWER_CUT;
2249 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2250
2251 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2252 ocp_data &= ~RESUME_INDICATE;
2253 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2254 }
2255
2256 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
2257 {
2258 u32 ocp_data;
2259
2260 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2261 if (enable)
2262 ocp_data |= CPCR_RX_VLAN;
2263 else
2264 ocp_data &= ~CPCR_RX_VLAN;
2265 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2266 }
2267
2268 static int rtl8152_set_features(struct net_device *dev,
2269 netdev_features_t features)
2270 {
2271 netdev_features_t changed = features ^ dev->features;
2272 struct r8152 *tp = netdev_priv(dev);
2273 int ret;
2274
2275 ret = usb_autopm_get_interface(tp->intf);
2276 if (ret < 0)
2277 goto out;
2278
2279 mutex_lock(&tp->control);
2280
2281 if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
2282 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2283 rtl_rx_vlan_en(tp, true);
2284 else
2285 rtl_rx_vlan_en(tp, false);
2286 }
2287
2288 mutex_unlock(&tp->control);
2289
2290 usb_autopm_put_interface(tp->intf);
2291
2292 out:
2293 return ret;
2294 }
2295
2296 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2297
2298 static u32 __rtl_get_wol(struct r8152 *tp)
2299 {
2300 u32 ocp_data;
2301 u32 wolopts = 0;
2302
2303 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2304 if (!(ocp_data & LAN_WAKE_EN))
2305 return 0;
2306
2307 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2308 if (ocp_data & LINK_ON_WAKE_EN)
2309 wolopts |= WAKE_PHY;
2310
2311 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2312 if (ocp_data & UWF_EN)
2313 wolopts |= WAKE_UCAST;
2314 if (ocp_data & BWF_EN)
2315 wolopts |= WAKE_BCAST;
2316 if (ocp_data & MWF_EN)
2317 wolopts |= WAKE_MCAST;
2318
2319 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2320 if (ocp_data & MAGIC_EN)
2321 wolopts |= WAKE_MAGIC;
2322
2323 return wolopts;
2324 }
2325
2326 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
2327 {
2328 u32 ocp_data;
2329
2330 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2331
2332 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2333 ocp_data &= ~LINK_ON_WAKE_EN;
2334 if (wolopts & WAKE_PHY)
2335 ocp_data |= LINK_ON_WAKE_EN;
2336 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2337
2338 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2339 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN | LAN_WAKE_EN);
2340 if (wolopts & WAKE_UCAST)
2341 ocp_data |= UWF_EN;
2342 if (wolopts & WAKE_BCAST)
2343 ocp_data |= BWF_EN;
2344 if (wolopts & WAKE_MCAST)
2345 ocp_data |= MWF_EN;
2346 if (wolopts & WAKE_ANY)
2347 ocp_data |= LAN_WAKE_EN;
2348 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
2349
2350 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2351
2352 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2353 ocp_data &= ~MAGIC_EN;
2354 if (wolopts & WAKE_MAGIC)
2355 ocp_data |= MAGIC_EN;
2356 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
2357
2358 if (wolopts & WAKE_ANY)
2359 device_set_wakeup_enable(&tp->udev->dev, true);
2360 else
2361 device_set_wakeup_enable(&tp->udev->dev, false);
2362 }
2363
2364 static void r8153_u1u2en(struct r8152 *tp, bool enable)
2365 {
2366 u8 u1u2[8];
2367
2368 if (enable)
2369 memset(u1u2, 0xff, sizeof(u1u2));
2370 else
2371 memset(u1u2, 0x00, sizeof(u1u2));
2372
2373 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
2374 }
2375
2376 static void r8153_u2p3en(struct r8152 *tp, bool enable)
2377 {
2378 u32 ocp_data;
2379
2380 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
2381 if (enable && tp->version != RTL_VER_03 && tp->version != RTL_VER_04)
2382 ocp_data |= U2P3_ENABLE;
2383 else
2384 ocp_data &= ~U2P3_ENABLE;
2385 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
2386 }
2387
2388 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
2389 {
2390 u32 ocp_data;
2391
2392 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2393 if (enable)
2394 ocp_data |= PWR_EN | PHASE2_EN;
2395 else
2396 ocp_data &= ~(PWR_EN | PHASE2_EN);
2397 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2398
2399 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2400 ocp_data &= ~PCUT_STATUS;
2401 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2402 }
2403
2404 static bool rtl_can_wakeup(struct r8152 *tp)
2405 {
2406 struct usb_device *udev = tp->udev;
2407
2408 return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
2409 }
2410
2411 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
2412 {
2413 if (enable) {
2414 u32 ocp_data;
2415
2416 __rtl_set_wol(tp, WAKE_ANY);
2417
2418 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2419
2420 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2421 ocp_data |= LINK_OFF_WAKE_EN;
2422 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2423
2424 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2425 } else {
2426 u32 ocp_data;
2427
2428 __rtl_set_wol(tp, tp->saved_wolopts);
2429
2430 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2431
2432 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2433 ocp_data &= ~LINK_OFF_WAKE_EN;
2434 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2435
2436 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2437 }
2438 }
2439
2440 static void rtl8153_runtime_enable(struct r8152 *tp, bool enable)
2441 {
2442 rtl_runtime_suspend_enable(tp, enable);
2443
2444 if (enable) {
2445 r8153_u1u2en(tp, false);
2446 r8153_u2p3en(tp, false);
2447 } else {
2448 r8153_u2p3en(tp, true);
2449 r8153_u1u2en(tp, true);
2450 }
2451 }
2452
2453 static void r8153_teredo_off(struct r8152 *tp)
2454 {
2455 u32 ocp_data;
2456
2457 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2458 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN);
2459 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2460
2461 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
2462 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
2463 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
2464 }
2465
2466 static void rtl_reset_bmu(struct r8152 *tp)
2467 {
2468 u32 ocp_data;
2469
2470 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
2471 ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
2472 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2473 ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
2474 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2475 }
2476
2477 static void r8152_aldps_en(struct r8152 *tp, bool enable)
2478 {
2479 if (enable) {
2480 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
2481 LINKENA | DIS_SDSAVE);
2482 } else {
2483 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |
2484 DIS_SDSAVE);
2485 msleep(20);
2486 }
2487 }
2488
2489 static void rtl8152_disable(struct r8152 *tp)
2490 {
2491 r8152_aldps_en(tp, false);
2492 rtl_disable(tp);
2493 r8152_aldps_en(tp, true);
2494 }
2495
2496 static void r8152b_hw_phy_cfg(struct r8152 *tp)
2497 {
2498 u16 data;
2499
2500 data = r8152_mdio_read(tp, MII_BMCR);
2501 if (data & BMCR_PDOWN) {
2502 data &= ~BMCR_PDOWN;
2503 r8152_mdio_write(tp, MII_BMCR, data);
2504 }
2505
2506 set_bit(PHY_RESET, &tp->flags);
2507 }
2508
2509 static void r8152b_exit_oob(struct r8152 *tp)
2510 {
2511 u32 ocp_data;
2512 int i;
2513
2514 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2515 ocp_data &= ~RCR_ACPT_ALL;
2516 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2517
2518 rxdy_gated_en(tp, true);
2519 r8153_teredo_off(tp);
2520 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2521 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
2522
2523 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2524 ocp_data &= ~NOW_IS_OOB;
2525 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2526
2527 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2528 ocp_data &= ~MCU_BORW_EN;
2529 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2530
2531 for (i = 0; i < 1000; i++) {
2532 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2533 if (ocp_data & LINK_LIST_READY)
2534 break;
2535 usleep_range(1000, 2000);
2536 }
2537
2538 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2539 ocp_data |= RE_INIT_LL;
2540 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2541
2542 for (i = 0; i < 1000; i++) {
2543 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2544 if (ocp_data & LINK_LIST_READY)
2545 break;
2546 usleep_range(1000, 2000);
2547 }
2548
2549 rtl8152_nic_reset(tp);
2550
2551 /* rx share fifo credit full threshold */
2552 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2553
2554 if (tp->udev->speed == USB_SPEED_FULL ||
2555 tp->udev->speed == USB_SPEED_LOW) {
2556 /* rx share fifo credit near full threshold */
2557 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2558 RXFIFO_THR2_FULL);
2559 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2560 RXFIFO_THR3_FULL);
2561 } else {
2562 /* rx share fifo credit near full threshold */
2563 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2564 RXFIFO_THR2_HIGH);
2565 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2566 RXFIFO_THR3_HIGH);
2567 }
2568
2569 /* TX share fifo free credit full threshold */
2570 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
2571
2572 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
2573 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
2574 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
2575 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
2576
2577 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
2578
2579 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2580
2581 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2582 ocp_data |= TCR0_AUTO_FIFO;
2583 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2584 }
2585
2586 static void r8152b_enter_oob(struct r8152 *tp)
2587 {
2588 u32 ocp_data;
2589 int i;
2590
2591 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2592 ocp_data &= ~NOW_IS_OOB;
2593 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2594
2595 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
2596 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
2597 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
2598
2599 rtl_disable(tp);
2600
2601 for (i = 0; i < 1000; i++) {
2602 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2603 if (ocp_data & LINK_LIST_READY)
2604 break;
2605 usleep_range(1000, 2000);
2606 }
2607
2608 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2609 ocp_data |= RE_INIT_LL;
2610 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2611
2612 for (i = 0; i < 1000; i++) {
2613 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2614 if (ocp_data & LINK_LIST_READY)
2615 break;
2616 usleep_range(1000, 2000);
2617 }
2618
2619 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2620
2621 rtl_rx_vlan_en(tp, true);
2622
2623 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2624 ocp_data |= ALDPS_PROXY_MODE;
2625 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2626
2627 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2628 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2629 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2630
2631 rxdy_gated_en(tp, false);
2632
2633 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2634 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2635 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2636 }
2637
2638 static void r8153_hw_phy_cfg(struct r8152 *tp)
2639 {
2640 u32 ocp_data;
2641 u16 data;
2642
2643 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
2644 tp->version == RTL_VER_05)
2645 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
2646
2647 data = r8152_mdio_read(tp, MII_BMCR);
2648 if (data & BMCR_PDOWN) {
2649 data &= ~BMCR_PDOWN;
2650 r8152_mdio_write(tp, MII_BMCR, data);
2651 }
2652
2653 if (tp->version == RTL_VER_03) {
2654 data = ocp_reg_read(tp, OCP_EEE_CFG);
2655 data &= ~CTAP_SHORT_EN;
2656 ocp_reg_write(tp, OCP_EEE_CFG, data);
2657 }
2658
2659 data = ocp_reg_read(tp, OCP_POWER_CFG);
2660 data |= EEE_CLKDIV_EN;
2661 ocp_reg_write(tp, OCP_POWER_CFG, data);
2662
2663 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
2664 data |= EN_10M_BGOFF;
2665 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
2666 data = ocp_reg_read(tp, OCP_POWER_CFG);
2667 data |= EN_10M_PLLOFF;
2668 ocp_reg_write(tp, OCP_POWER_CFG, data);
2669 sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
2670
2671 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
2672 ocp_data |= PFM_PWM_SWITCH;
2673 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
2674
2675 /* Enable LPF corner auto tune */
2676 sram_write(tp, SRAM_LPF_CFG, 0xf70f);
2677
2678 /* Adjust 10M Amplitude */
2679 sram_write(tp, SRAM_10M_AMP1, 0x00af);
2680 sram_write(tp, SRAM_10M_AMP2, 0x0208);
2681
2682 set_bit(PHY_RESET, &tp->flags);
2683 }
2684
2685 static void r8153_first_init(struct r8152 *tp)
2686 {
2687 u32 ocp_data;
2688 int i;
2689
2690 rxdy_gated_en(tp, true);
2691 r8153_teredo_off(tp);
2692
2693 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2694 ocp_data &= ~RCR_ACPT_ALL;
2695 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2696
2697 rtl8152_nic_reset(tp);
2698 rtl_reset_bmu(tp);
2699
2700 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2701 ocp_data &= ~NOW_IS_OOB;
2702 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2703
2704 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2705 ocp_data &= ~MCU_BORW_EN;
2706 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2707
2708 for (i = 0; i < 1000; i++) {
2709 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2710 if (ocp_data & LINK_LIST_READY)
2711 break;
2712 usleep_range(1000, 2000);
2713 }
2714
2715 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2716 ocp_data |= RE_INIT_LL;
2717 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2718
2719 for (i = 0; i < 1000; i++) {
2720 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2721 if (ocp_data & LINK_LIST_READY)
2722 break;
2723 usleep_range(1000, 2000);
2724 }
2725
2726 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
2727
2728 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
2729 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
2730
2731 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2732 ocp_data |= TCR0_AUTO_FIFO;
2733 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2734
2735 rtl8152_nic_reset(tp);
2736
2737 /* rx share fifo credit full threshold */
2738 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2739 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
2740 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
2741 /* TX share fifo free credit full threshold */
2742 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
2743
2744 /* rx aggregation */
2745 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2746 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
2747 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2748 }
2749
2750 static void r8153_enter_oob(struct r8152 *tp)
2751 {
2752 u32 ocp_data;
2753 int i;
2754
2755 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2756 ocp_data &= ~NOW_IS_OOB;
2757 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2758
2759 rtl_disable(tp);
2760 rtl_reset_bmu(tp);
2761
2762 for (i = 0; i < 1000; i++) {
2763 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2764 if (ocp_data & LINK_LIST_READY)
2765 break;
2766 usleep_range(1000, 2000);
2767 }
2768
2769 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2770 ocp_data |= RE_INIT_LL;
2771 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2772
2773 for (i = 0; i < 1000; i++) {
2774 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2775 if (ocp_data & LINK_LIST_READY)
2776 break;
2777 usleep_range(1000, 2000);
2778 }
2779
2780 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
2781
2782 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2783 ocp_data &= ~TEREDO_WAKE_MASK;
2784 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2785
2786 rtl_rx_vlan_en(tp, true);
2787
2788 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2789 ocp_data |= ALDPS_PROXY_MODE;
2790 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2791
2792 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2793 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2794 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2795
2796 rxdy_gated_en(tp, false);
2797
2798 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2799 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2800 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2801 }
2802
2803 static void r8153_aldps_en(struct r8152 *tp, bool enable)
2804 {
2805 u16 data;
2806
2807 data = ocp_reg_read(tp, OCP_POWER_CFG);
2808 if (enable) {
2809 data |= EN_ALDPS;
2810 ocp_reg_write(tp, OCP_POWER_CFG, data);
2811 } else {
2812 data &= ~EN_ALDPS;
2813 ocp_reg_write(tp, OCP_POWER_CFG, data);
2814 msleep(20);
2815 }
2816 }
2817
2818 static void rtl8153_disable(struct r8152 *tp)
2819 {
2820 r8153_aldps_en(tp, false);
2821 rtl_disable(tp);
2822 rtl_reset_bmu(tp);
2823 r8153_aldps_en(tp, true);
2824 usb_enable_lpm(tp->udev);
2825 }
2826
2827 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
2828 {
2829 u16 bmcr, anar, gbcr;
2830 int ret = 0;
2831
2832 anar = r8152_mdio_read(tp, MII_ADVERTISE);
2833 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
2834 ADVERTISE_100HALF | ADVERTISE_100FULL);
2835 if (tp->mii.supports_gmii) {
2836 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
2837 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
2838 } else {
2839 gbcr = 0;
2840 }
2841
2842 if (autoneg == AUTONEG_DISABLE) {
2843 if (speed == SPEED_10) {
2844 bmcr = 0;
2845 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2846 } else if (speed == SPEED_100) {
2847 bmcr = BMCR_SPEED100;
2848 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2849 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2850 bmcr = BMCR_SPEED1000;
2851 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
2852 } else {
2853 ret = -EINVAL;
2854 goto out;
2855 }
2856
2857 if (duplex == DUPLEX_FULL)
2858 bmcr |= BMCR_FULLDPLX;
2859 } else {
2860 if (speed == SPEED_10) {
2861 if (duplex == DUPLEX_FULL)
2862 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2863 else
2864 anar |= ADVERTISE_10HALF;
2865 } else if (speed == SPEED_100) {
2866 if (duplex == DUPLEX_FULL) {
2867 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2868 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2869 } else {
2870 anar |= ADVERTISE_10HALF;
2871 anar |= ADVERTISE_100HALF;
2872 }
2873 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2874 if (duplex == DUPLEX_FULL) {
2875 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2876 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2877 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
2878 } else {
2879 anar |= ADVERTISE_10HALF;
2880 anar |= ADVERTISE_100HALF;
2881 gbcr |= ADVERTISE_1000HALF;
2882 }
2883 } else {
2884 ret = -EINVAL;
2885 goto out;
2886 }
2887
2888 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
2889 }
2890
2891 if (test_and_clear_bit(PHY_RESET, &tp->flags))
2892 bmcr |= BMCR_RESET;
2893
2894 if (tp->mii.supports_gmii)
2895 r8152_mdio_write(tp, MII_CTRL1000, gbcr);
2896
2897 r8152_mdio_write(tp, MII_ADVERTISE, anar);
2898 r8152_mdio_write(tp, MII_BMCR, bmcr);
2899
2900 if (bmcr & BMCR_RESET) {
2901 int i;
2902
2903 for (i = 0; i < 50; i++) {
2904 msleep(20);
2905 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
2906 break;
2907 }
2908 }
2909
2910 out:
2911 return ret;
2912 }
2913
2914 static void rtl8152_up(struct r8152 *tp)
2915 {
2916 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2917 return;
2918
2919 r8152_aldps_en(tp, false);
2920 r8152b_exit_oob(tp);
2921 r8152_aldps_en(tp, true);
2922 }
2923
2924 static void rtl8152_down(struct r8152 *tp)
2925 {
2926 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2927 rtl_drop_queued_tx(tp);
2928 return;
2929 }
2930
2931 r8152_power_cut_en(tp, false);
2932 r8152_aldps_en(tp, false);
2933 r8152b_enter_oob(tp);
2934 r8152_aldps_en(tp, true);
2935 }
2936
2937 static void rtl8153_up(struct r8152 *tp)
2938 {
2939 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2940 return;
2941
2942 r8153_u1u2en(tp, false);
2943 r8153_aldps_en(tp, false);
2944 r8153_first_init(tp);
2945 r8153_aldps_en(tp, true);
2946 r8153_u2p3en(tp, true);
2947 r8153_u1u2en(tp, true);
2948 usb_enable_lpm(tp->udev);
2949 }
2950
2951 static void rtl8153_down(struct r8152 *tp)
2952 {
2953 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2954 rtl_drop_queued_tx(tp);
2955 return;
2956 }
2957
2958 r8153_u1u2en(tp, false);
2959 r8153_u2p3en(tp, false);
2960 r8153_power_cut_en(tp, false);
2961 r8153_aldps_en(tp, false);
2962 r8153_enter_oob(tp);
2963 r8153_aldps_en(tp, true);
2964 }
2965
2966 static bool rtl8152_in_nway(struct r8152 *tp)
2967 {
2968 u16 nway_state;
2969
2970 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
2971 tp->ocp_base = 0x2000;
2972 ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */
2973 nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a);
2974
2975 /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
2976 if (nway_state & 0xc000)
2977 return false;
2978 else
2979 return true;
2980 }
2981
2982 static bool rtl8153_in_nway(struct r8152 *tp)
2983 {
2984 u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
2985
2986 if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
2987 return false;
2988 else
2989 return true;
2990 }
2991
2992 static void set_carrier(struct r8152 *tp)
2993 {
2994 struct net_device *netdev = tp->netdev;
2995 u8 speed;
2996
2997 speed = rtl8152_get_speed(tp);
2998
2999 if (speed & LINK_STATUS) {
3000 if (!netif_carrier_ok(netdev)) {
3001 tp->rtl_ops.enable(tp);
3002 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
3003 napi_disable(&tp->napi);
3004 netif_carrier_on(netdev);
3005 rtl_start_rx(tp);
3006 napi_enable(&tp->napi);
3007 }
3008 } else {
3009 if (netif_carrier_ok(netdev)) {
3010 netif_carrier_off(netdev);
3011 napi_disable(&tp->napi);
3012 tp->rtl_ops.disable(tp);
3013 napi_enable(&tp->napi);
3014 }
3015 }
3016 }
3017
3018 static void rtl_work_func_t(struct work_struct *work)
3019 {
3020 struct r8152 *tp = container_of(work, struct r8152, schedule.work);
3021
3022 /* If the device is unplugged or !netif_running(), the workqueue
3023 * doesn't need to wake the device, and could return directly.
3024 */
3025 if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
3026 return;
3027
3028 if (usb_autopm_get_interface(tp->intf) < 0)
3029 return;
3030
3031 if (!test_bit(WORK_ENABLE, &tp->flags))
3032 goto out1;
3033
3034 if (!mutex_trylock(&tp->control)) {
3035 schedule_delayed_work(&tp->schedule, 0);
3036 goto out1;
3037 }
3038
3039 if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags))
3040 set_carrier(tp);
3041
3042 if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags))
3043 _rtl8152_set_rx_mode(tp->netdev);
3044
3045 /* don't schedule napi before linking */
3046 if (test_and_clear_bit(SCHEDULE_NAPI, &tp->flags) &&
3047 netif_carrier_ok(tp->netdev))
3048 napi_schedule(&tp->napi);
3049
3050 mutex_unlock(&tp->control);
3051
3052 out1:
3053 usb_autopm_put_interface(tp->intf);
3054 }
3055
3056 static void rtl_hw_phy_work_func_t(struct work_struct *work)
3057 {
3058 struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work);
3059
3060 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3061 return;
3062
3063 if (usb_autopm_get_interface(tp->intf) < 0)
3064 return;
3065
3066 mutex_lock(&tp->control);
3067
3068 tp->rtl_ops.hw_phy_cfg(tp);
3069
3070 rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex);
3071
3072 mutex_unlock(&tp->control);
3073
3074 usb_autopm_put_interface(tp->intf);
3075 }
3076
3077 #ifdef CONFIG_PM_SLEEP
3078 static int rtl_notifier(struct notifier_block *nb, unsigned long action,
3079 void *data)
3080 {
3081 struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);
3082
3083 switch (action) {
3084 case PM_HIBERNATION_PREPARE:
3085 case PM_SUSPEND_PREPARE:
3086 usb_autopm_get_interface(tp->intf);
3087 break;
3088
3089 case PM_POST_HIBERNATION:
3090 case PM_POST_SUSPEND:
3091 usb_autopm_put_interface(tp->intf);
3092 break;
3093
3094 case PM_POST_RESTORE:
3095 case PM_RESTORE_PREPARE:
3096 default:
3097 break;
3098 }
3099
3100 return NOTIFY_DONE;
3101 }
3102 #endif
3103
3104 static int rtl8152_open(struct net_device *netdev)
3105 {
3106 struct r8152 *tp = netdev_priv(netdev);
3107 int res = 0;
3108
3109 res = alloc_all_mem(tp);
3110 if (res)
3111 goto out;
3112
3113 res = usb_autopm_get_interface(tp->intf);
3114 if (res < 0) {
3115 free_all_mem(tp);
3116 goto out;
3117 }
3118
3119 mutex_lock(&tp->control);
3120
3121 tp->rtl_ops.up(tp);
3122
3123 netif_carrier_off(netdev);
3124 netif_start_queue(netdev);
3125 set_bit(WORK_ENABLE, &tp->flags);
3126
3127 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
3128 if (res) {
3129 if (res == -ENODEV)
3130 netif_device_detach(tp->netdev);
3131 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
3132 res);
3133 free_all_mem(tp);
3134 } else {
3135 napi_enable(&tp->napi);
3136 }
3137
3138 mutex_unlock(&tp->control);
3139
3140 usb_autopm_put_interface(tp->intf);
3141 #ifdef CONFIG_PM_SLEEP
3142 tp->pm_notifier.notifier_call = rtl_notifier;
3143 register_pm_notifier(&tp->pm_notifier);
3144 #endif
3145
3146 out:
3147 return res;
3148 }
3149
3150 static int rtl8152_close(struct net_device *netdev)
3151 {
3152 struct r8152 *tp = netdev_priv(netdev);
3153 int res = 0;
3154
3155 #ifdef CONFIG_PM_SLEEP
3156 unregister_pm_notifier(&tp->pm_notifier);
3157 #endif
3158 napi_disable(&tp->napi);
3159 clear_bit(WORK_ENABLE, &tp->flags);
3160 usb_kill_urb(tp->intr_urb);
3161 cancel_delayed_work_sync(&tp->schedule);
3162 netif_stop_queue(netdev);
3163
3164 res = usb_autopm_get_interface(tp->intf);
3165 if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
3166 rtl_drop_queued_tx(tp);
3167 rtl_stop_rx(tp);
3168 } else {
3169 mutex_lock(&tp->control);
3170
3171 tp->rtl_ops.down(tp);
3172
3173 mutex_unlock(&tp->control);
3174
3175 usb_autopm_put_interface(tp->intf);
3176 }
3177
3178 free_all_mem(tp);
3179
3180 return res;
3181 }
3182
3183 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
3184 {
3185 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
3186 ocp_reg_write(tp, OCP_EEE_DATA, reg);
3187 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
3188 }
3189
3190 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
3191 {
3192 u16 data;
3193
3194 r8152_mmd_indirect(tp, dev, reg);
3195 data = ocp_reg_read(tp, OCP_EEE_DATA);
3196 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
3197
3198 return data;
3199 }
3200
3201 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
3202 {
3203 r8152_mmd_indirect(tp, dev, reg);
3204 ocp_reg_write(tp, OCP_EEE_DATA, data);
3205 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
3206 }
3207
3208 static void r8152_eee_en(struct r8152 *tp, bool enable)
3209 {
3210 u16 config1, config2, config3;
3211 u32 ocp_data;
3212
3213 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3214 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
3215 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
3216 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
3217
3218 if (enable) {
3219 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3220 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
3221 config1 |= sd_rise_time(1);
3222 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
3223 config3 |= fast_snr(42);
3224 } else {
3225 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3226 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
3227 RX_QUIET_EN);
3228 config1 |= sd_rise_time(7);
3229 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
3230 config3 |= fast_snr(511);
3231 }
3232
3233 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
3234 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
3235 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
3236 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
3237 }
3238
3239 static void r8152b_enable_eee(struct r8152 *tp)
3240 {
3241 r8152_eee_en(tp, true);
3242 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX);
3243 }
3244
3245 static void r8153_eee_en(struct r8152 *tp, bool enable)
3246 {
3247 u32 ocp_data;
3248 u16 config;
3249
3250 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3251 config = ocp_reg_read(tp, OCP_EEE_CFG);
3252
3253 if (enable) {
3254 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3255 config |= EEE10_EN;
3256 } else {
3257 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3258 config &= ~EEE10_EN;
3259 }
3260
3261 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
3262 ocp_reg_write(tp, OCP_EEE_CFG, config);
3263 }
3264
3265 static void r8153_enable_eee(struct r8152 *tp)
3266 {
3267 r8153_eee_en(tp, true);
3268 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
3269 }
3270
3271 static void r8152b_enable_fc(struct r8152 *tp)
3272 {
3273 u16 anar;
3274
3275 anar = r8152_mdio_read(tp, MII_ADVERTISE);
3276 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3277 r8152_mdio_write(tp, MII_ADVERTISE, anar);
3278 }
3279
3280 static void rtl_tally_reset(struct r8152 *tp)
3281 {
3282 u32 ocp_data;
3283
3284 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
3285 ocp_data |= TALLY_RESET;
3286 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
3287 }
3288
3289 static void r8152b_init(struct r8152 *tp)
3290 {
3291 u32 ocp_data;
3292
3293 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3294 return;
3295
3296 r8152_aldps_en(tp, false);
3297
3298 if (tp->version == RTL_VER_01) {
3299 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3300 ocp_data &= ~LED_MODE_MASK;
3301 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3302 }
3303
3304 r8152_power_cut_en(tp, false);
3305
3306 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3307 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
3308 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3309 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
3310 ocp_data &= ~MCU_CLK_RATIO_MASK;
3311 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
3312 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
3313 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
3314 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
3315 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
3316
3317 r8152b_enable_eee(tp);
3318 r8152_aldps_en(tp, true);
3319 r8152b_enable_fc(tp);
3320 rtl_tally_reset(tp);
3321
3322 /* enable rx aggregation */
3323 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
3324 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
3325 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
3326 }
3327
3328 static void r8153_init(struct r8152 *tp)
3329 {
3330 u32 ocp_data;
3331 int i;
3332
3333 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3334 return;
3335
3336 r8153_aldps_en(tp, false);
3337 r8153_u1u2en(tp, false);
3338
3339 for (i = 0; i < 500; i++) {
3340 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
3341 AUTOLOAD_DONE)
3342 break;
3343 msleep(20);
3344 }
3345
3346 for (i = 0; i < 500; i++) {
3347 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
3348 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
3349 break;
3350 msleep(20);
3351 }
3352
3353 usb_disable_lpm(tp->udev);
3354 r8153_u2p3en(tp, false);
3355
3356 if (tp->version == RTL_VER_04) {
3357 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
3358 ocp_data &= ~pwd_dn_scale_mask;
3359 ocp_data |= pwd_dn_scale(96);
3360 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
3361
3362 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
3363 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
3364 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
3365 } else if (tp->version == RTL_VER_05) {
3366 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
3367 ocp_data &= ~ECM_ALDPS;
3368 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
3369
3370 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
3371 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
3372 ocp_data &= ~DYNAMIC_BURST;
3373 else
3374 ocp_data |= DYNAMIC_BURST;
3375 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
3376 } else if (tp->version == RTL_VER_06) {
3377 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
3378 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
3379 ocp_data &= ~DYNAMIC_BURST;
3380 else
3381 ocp_data |= DYNAMIC_BURST;
3382 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
3383 }
3384
3385 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
3386 ocp_data |= EP4_FULL_FC;
3387 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
3388
3389 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
3390 ocp_data &= ~TIMER11_EN;
3391 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
3392
3393 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3394 ocp_data &= ~LED_MODE_MASK;
3395 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3396
3397 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
3398 if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER)
3399 ocp_data |= LPM_TIMER_500MS;
3400 else
3401 ocp_data |= LPM_TIMER_500US;
3402 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
3403
3404 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
3405 ocp_data &= ~SEN_VAL_MASK;
3406 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
3407 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
3408
3409 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
3410
3411 r8153_power_cut_en(tp, false);
3412 r8153_u1u2en(tp, true);
3413
3414 /* MAC clock speed down */
3415 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0);
3416 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0);
3417 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0);
3418 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0);
3419
3420 r8153_enable_eee(tp);
3421 r8153_aldps_en(tp, true);
3422 r8152b_enable_fc(tp);
3423 rtl_tally_reset(tp);
3424 r8153_u2p3en(tp, true);
3425 }
3426
3427 static int rtl8152_pre_reset(struct usb_interface *intf)
3428 {
3429 struct r8152 *tp = usb_get_intfdata(intf);
3430 struct net_device *netdev;
3431
3432 if (!tp)
3433 return 0;
3434
3435 netdev = tp->netdev;
3436 if (!netif_running(netdev))
3437 return 0;
3438
3439 napi_disable(&tp->napi);
3440 clear_bit(WORK_ENABLE, &tp->flags);
3441 usb_kill_urb(tp->intr_urb);
3442 cancel_delayed_work_sync(&tp->schedule);
3443 if (netif_carrier_ok(netdev)) {
3444 netif_stop_queue(netdev);
3445 mutex_lock(&tp->control);
3446 tp->rtl_ops.disable(tp);
3447 mutex_unlock(&tp->control);
3448 }
3449
3450 return 0;
3451 }
3452
3453 static int rtl8152_post_reset(struct usb_interface *intf)
3454 {
3455 struct r8152 *tp = usb_get_intfdata(intf);
3456 struct net_device *netdev;
3457
3458 if (!tp)
3459 return 0;
3460
3461 netdev = tp->netdev;
3462 if (!netif_running(netdev))
3463 return 0;
3464
3465 set_bit(WORK_ENABLE, &tp->flags);
3466 if (netif_carrier_ok(netdev)) {
3467 mutex_lock(&tp->control);
3468 tp->rtl_ops.enable(tp);
3469 rtl8152_set_rx_mode(netdev);
3470 mutex_unlock(&tp->control);
3471 netif_wake_queue(netdev);
3472 }
3473
3474 napi_enable(&tp->napi);
3475
3476 return 0;
3477 }
3478
3479 static bool delay_autosuspend(struct r8152 *tp)
3480 {
3481 bool sw_linking = !!netif_carrier_ok(tp->netdev);
3482 bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
3483
3484 /* This means a linking change occurs and the driver doesn't detect it,
3485 * yet. If the driver has disabled tx/rx and hw is linking on, the
3486 * device wouldn't wake up by receiving any packet.
3487 */
3488 if (work_busy(&tp->schedule.work) || sw_linking != hw_linking)
3489 return true;
3490
3491 /* If the linking down is occurred by nway, the device may miss the
3492 * linking change event. And it wouldn't wake when linking on.
3493 */
3494 if (!sw_linking && tp->rtl_ops.in_nway(tp))
3495 return true;
3496 else
3497 return false;
3498 }
3499
3500 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
3501 {
3502 struct r8152 *tp = usb_get_intfdata(intf);
3503 struct net_device *netdev = tp->netdev;
3504 int ret = 0;
3505
3506 mutex_lock(&tp->control);
3507
3508 if (PMSG_IS_AUTO(message)) {
3509 if (netif_running(netdev) && delay_autosuspend(tp)) {
3510 ret = -EBUSY;
3511 goto out1;
3512 }
3513
3514 set_bit(SELECTIVE_SUSPEND, &tp->flags);
3515 } else {
3516 netif_device_detach(netdev);
3517 }
3518
3519 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
3520 clear_bit(WORK_ENABLE, &tp->flags);
3521 usb_kill_urb(tp->intr_urb);
3522 napi_disable(&tp->napi);
3523 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3524 rtl_stop_rx(tp);
3525 tp->rtl_ops.autosuspend_en(tp, true);
3526 } else {
3527 cancel_delayed_work_sync(&tp->schedule);
3528 tp->rtl_ops.down(tp);
3529 }
3530 napi_enable(&tp->napi);
3531 }
3532 out1:
3533 mutex_unlock(&tp->control);
3534
3535 return ret;
3536 }
3537
3538 static int rtl8152_resume(struct usb_interface *intf)
3539 {
3540 struct r8152 *tp = usb_get_intfdata(intf);
3541
3542 mutex_lock(&tp->control);
3543
3544 if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3545 tp->rtl_ops.init(tp);
3546 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
3547 netif_device_attach(tp->netdev);
3548 }
3549
3550 if (netif_running(tp->netdev) && tp->netdev->flags & IFF_UP) {
3551 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3552 tp->rtl_ops.autosuspend_en(tp, false);
3553 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
3554 napi_disable(&tp->napi);
3555 set_bit(WORK_ENABLE, &tp->flags);
3556 if (netif_carrier_ok(tp->netdev))
3557 rtl_start_rx(tp);
3558 napi_enable(&tp->napi);
3559 } else {
3560 tp->rtl_ops.up(tp);
3561 netif_carrier_off(tp->netdev);
3562 set_bit(WORK_ENABLE, &tp->flags);
3563 }
3564 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
3565 } else if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3566 if (tp->netdev->flags & IFF_UP)
3567 tp->rtl_ops.autosuspend_en(tp, false);
3568 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
3569 }
3570
3571 mutex_unlock(&tp->control);
3572
3573 return 0;
3574 }
3575
3576 static int rtl8152_reset_resume(struct usb_interface *intf)
3577 {
3578 struct r8152 *tp = usb_get_intfdata(intf);
3579
3580 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
3581 return rtl8152_resume(intf);
3582 }
3583
3584 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3585 {
3586 struct r8152 *tp = netdev_priv(dev);
3587
3588 if (usb_autopm_get_interface(tp->intf) < 0)
3589 return;
3590
3591 if (!rtl_can_wakeup(tp)) {
3592 wol->supported = 0;
3593 wol->wolopts = 0;
3594 } else {
3595 mutex_lock(&tp->control);
3596 wol->supported = WAKE_ANY;
3597 wol->wolopts = __rtl_get_wol(tp);
3598 mutex_unlock(&tp->control);
3599 }
3600
3601 usb_autopm_put_interface(tp->intf);
3602 }
3603
3604 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3605 {
3606 struct r8152 *tp = netdev_priv(dev);
3607 int ret;
3608
3609 if (!rtl_can_wakeup(tp))
3610 return -EOPNOTSUPP;
3611
3612 ret = usb_autopm_get_interface(tp->intf);
3613 if (ret < 0)
3614 goto out_set_wol;
3615
3616 mutex_lock(&tp->control);
3617
3618 __rtl_set_wol(tp, wol->wolopts);
3619 tp->saved_wolopts = wol->wolopts & WAKE_ANY;
3620
3621 mutex_unlock(&tp->control);
3622
3623 usb_autopm_put_interface(tp->intf);
3624
3625 out_set_wol:
3626 return ret;
3627 }
3628
3629 static u32 rtl8152_get_msglevel(struct net_device *dev)
3630 {
3631 struct r8152 *tp = netdev_priv(dev);
3632
3633 return tp->msg_enable;
3634 }
3635
3636 static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
3637 {
3638 struct r8152 *tp = netdev_priv(dev);
3639
3640 tp->msg_enable = value;
3641 }
3642
3643 static void rtl8152_get_drvinfo(struct net_device *netdev,
3644 struct ethtool_drvinfo *info)
3645 {
3646 struct r8152 *tp = netdev_priv(netdev);
3647
3648 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
3649 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
3650 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
3651 }
3652
3653 static
3654 int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
3655 {
3656 struct r8152 *tp = netdev_priv(netdev);
3657 int ret;
3658
3659 if (!tp->mii.mdio_read)
3660 return -EOPNOTSUPP;
3661
3662 ret = usb_autopm_get_interface(tp->intf);
3663 if (ret < 0)
3664 goto out;
3665
3666 mutex_lock(&tp->control);
3667
3668 ret = mii_ethtool_gset(&tp->mii, cmd);
3669
3670 mutex_unlock(&tp->control);
3671
3672 usb_autopm_put_interface(tp->intf);
3673
3674 out:
3675 return ret;
3676 }
3677
3678 static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
3679 {
3680 struct r8152 *tp = netdev_priv(dev);
3681 int ret;
3682
3683 ret = usb_autopm_get_interface(tp->intf);
3684 if (ret < 0)
3685 goto out;
3686
3687 mutex_lock(&tp->control);
3688
3689 ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex);
3690 if (!ret) {
3691 tp->autoneg = cmd->autoneg;
3692 tp->speed = cmd->speed;
3693 tp->duplex = cmd->duplex;
3694 }
3695
3696 mutex_unlock(&tp->control);
3697
3698 usb_autopm_put_interface(tp->intf);
3699
3700 out:
3701 return ret;
3702 }
3703
3704 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
3705 "tx_packets",
3706 "rx_packets",
3707 "tx_errors",
3708 "rx_errors",
3709 "rx_missed",
3710 "align_errors",
3711 "tx_single_collisions",
3712 "tx_multi_collisions",
3713 "rx_unicast",
3714 "rx_broadcast",
3715 "rx_multicast",
3716 "tx_aborted",
3717 "tx_underrun",
3718 };
3719
3720 static int rtl8152_get_sset_count(struct net_device *dev, int sset)
3721 {
3722 switch (sset) {
3723 case ETH_SS_STATS:
3724 return ARRAY_SIZE(rtl8152_gstrings);
3725 default:
3726 return -EOPNOTSUPP;
3727 }
3728 }
3729
3730 static void rtl8152_get_ethtool_stats(struct net_device *dev,
3731 struct ethtool_stats *stats, u64 *data)
3732 {
3733 struct r8152 *tp = netdev_priv(dev);
3734 struct tally_counter tally;
3735
3736 if (usb_autopm_get_interface(tp->intf) < 0)
3737 return;
3738
3739 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
3740
3741 usb_autopm_put_interface(tp->intf);
3742
3743 data[0] = le64_to_cpu(tally.tx_packets);
3744 data[1] = le64_to_cpu(tally.rx_packets);
3745 data[2] = le64_to_cpu(tally.tx_errors);
3746 data[3] = le32_to_cpu(tally.rx_errors);
3747 data[4] = le16_to_cpu(tally.rx_missed);
3748 data[5] = le16_to_cpu(tally.align_errors);
3749 data[6] = le32_to_cpu(tally.tx_one_collision);
3750 data[7] = le32_to_cpu(tally.tx_multi_collision);
3751 data[8] = le64_to_cpu(tally.rx_unicast);
3752 data[9] = le64_to_cpu(tally.rx_broadcast);
3753 data[10] = le32_to_cpu(tally.rx_multicast);
3754 data[11] = le16_to_cpu(tally.tx_aborted);
3755 data[12] = le16_to_cpu(tally.tx_underrun);
3756 }
3757
3758 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
3759 {
3760 switch (stringset) {
3761 case ETH_SS_STATS:
3762 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
3763 break;
3764 }
3765 }
3766
3767 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
3768 {
3769 u32 ocp_data, lp, adv, supported = 0;
3770 u16 val;
3771
3772 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
3773 supported = mmd_eee_cap_to_ethtool_sup_t(val);
3774
3775 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
3776 adv = mmd_eee_adv_to_ethtool_adv_t(val);
3777
3778 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
3779 lp = mmd_eee_adv_to_ethtool_adv_t(val);
3780
3781 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3782 ocp_data &= EEE_RX_EN | EEE_TX_EN;
3783
3784 eee->eee_enabled = !!ocp_data;
3785 eee->eee_active = !!(supported & adv & lp);
3786 eee->supported = supported;
3787 eee->advertised = adv;
3788 eee->lp_advertised = lp;
3789
3790 return 0;
3791 }
3792
3793 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
3794 {
3795 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
3796
3797 r8152_eee_en(tp, eee->eee_enabled);
3798
3799 if (!eee->eee_enabled)
3800 val = 0;
3801
3802 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
3803
3804 return 0;
3805 }
3806
3807 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
3808 {
3809 u32 ocp_data, lp, adv, supported = 0;
3810 u16 val;
3811
3812 val = ocp_reg_read(tp, OCP_EEE_ABLE);
3813 supported = mmd_eee_cap_to_ethtool_sup_t(val);
3814
3815 val = ocp_reg_read(tp, OCP_EEE_ADV);
3816 adv = mmd_eee_adv_to_ethtool_adv_t(val);
3817
3818 val = ocp_reg_read(tp, OCP_EEE_LPABLE);
3819 lp = mmd_eee_adv_to_ethtool_adv_t(val);
3820
3821 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3822 ocp_data &= EEE_RX_EN | EEE_TX_EN;
3823
3824 eee->eee_enabled = !!ocp_data;
3825 eee->eee_active = !!(supported & adv & lp);
3826 eee->supported = supported;
3827 eee->advertised = adv;
3828 eee->lp_advertised = lp;
3829
3830 return 0;
3831 }
3832
3833 static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
3834 {
3835 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
3836
3837 r8153_eee_en(tp, eee->eee_enabled);
3838
3839 if (!eee->eee_enabled)
3840 val = 0;
3841
3842 ocp_reg_write(tp, OCP_EEE_ADV, val);
3843
3844 return 0;
3845 }
3846
3847 static int
3848 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
3849 {
3850 struct r8152 *tp = netdev_priv(net);
3851 int ret;
3852
3853 ret = usb_autopm_get_interface(tp->intf);
3854 if (ret < 0)
3855 goto out;
3856
3857 mutex_lock(&tp->control);
3858
3859 ret = tp->rtl_ops.eee_get(tp, edata);
3860
3861 mutex_unlock(&tp->control);
3862
3863 usb_autopm_put_interface(tp->intf);
3864
3865 out:
3866 return ret;
3867 }
3868
3869 static int
3870 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
3871 {
3872 struct r8152 *tp = netdev_priv(net);
3873 int ret;
3874
3875 ret = usb_autopm_get_interface(tp->intf);
3876 if (ret < 0)
3877 goto out;
3878
3879 mutex_lock(&tp->control);
3880
3881 ret = tp->rtl_ops.eee_set(tp, edata);
3882 if (!ret)
3883 ret = mii_nway_restart(&tp->mii);
3884
3885 mutex_unlock(&tp->control);
3886
3887 usb_autopm_put_interface(tp->intf);
3888
3889 out:
3890 return ret;
3891 }
3892
3893 static int rtl8152_nway_reset(struct net_device *dev)
3894 {
3895 struct r8152 *tp = netdev_priv(dev);
3896 int ret;
3897
3898 ret = usb_autopm_get_interface(tp->intf);
3899 if (ret < 0)
3900 goto out;
3901
3902 mutex_lock(&tp->control);
3903
3904 ret = mii_nway_restart(&tp->mii);
3905
3906 mutex_unlock(&tp->control);
3907
3908 usb_autopm_put_interface(tp->intf);
3909
3910 out:
3911 return ret;
3912 }
3913
3914 static int rtl8152_get_coalesce(struct net_device *netdev,
3915 struct ethtool_coalesce *coalesce)
3916 {
3917 struct r8152 *tp = netdev_priv(netdev);
3918
3919 switch (tp->version) {
3920 case RTL_VER_01:
3921 case RTL_VER_02:
3922 return -EOPNOTSUPP;
3923 default:
3924 break;
3925 }
3926
3927 coalesce->rx_coalesce_usecs = tp->coalesce;
3928
3929 return 0;
3930 }
3931
3932 static int rtl8152_set_coalesce(struct net_device *netdev,
3933 struct ethtool_coalesce *coalesce)
3934 {
3935 struct r8152 *tp = netdev_priv(netdev);
3936 int ret;
3937
3938 switch (tp->version) {
3939 case RTL_VER_01:
3940 case RTL_VER_02:
3941 return -EOPNOTSUPP;
3942 default:
3943 break;
3944 }
3945
3946 if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
3947 return -EINVAL;
3948
3949 ret = usb_autopm_get_interface(tp->intf);
3950 if (ret < 0)
3951 return ret;
3952
3953 mutex_lock(&tp->control);
3954
3955 if (tp->coalesce != coalesce->rx_coalesce_usecs) {
3956 tp->coalesce = coalesce->rx_coalesce_usecs;
3957
3958 if (netif_running(tp->netdev) && netif_carrier_ok(netdev))
3959 r8153_set_rx_early_timeout(tp);
3960 }
3961
3962 mutex_unlock(&tp->control);
3963
3964 usb_autopm_put_interface(tp->intf);
3965
3966 return ret;
3967 }
3968
3969 static struct ethtool_ops ops = {
3970 .get_drvinfo = rtl8152_get_drvinfo,
3971 .get_settings = rtl8152_get_settings,
3972 .set_settings = rtl8152_set_settings,
3973 .get_link = ethtool_op_get_link,
3974 .nway_reset = rtl8152_nway_reset,
3975 .get_msglevel = rtl8152_get_msglevel,
3976 .set_msglevel = rtl8152_set_msglevel,
3977 .get_wol = rtl8152_get_wol,
3978 .set_wol = rtl8152_set_wol,
3979 .get_strings = rtl8152_get_strings,
3980 .get_sset_count = rtl8152_get_sset_count,
3981 .get_ethtool_stats = rtl8152_get_ethtool_stats,
3982 .get_coalesce = rtl8152_get_coalesce,
3983 .set_coalesce = rtl8152_set_coalesce,
3984 .get_eee = rtl_ethtool_get_eee,
3985 .set_eee = rtl_ethtool_set_eee,
3986 };
3987
3988 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
3989 {
3990 struct r8152 *tp = netdev_priv(netdev);
3991 struct mii_ioctl_data *data = if_mii(rq);
3992 int res;
3993
3994 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3995 return -ENODEV;
3996
3997 res = usb_autopm_get_interface(tp->intf);
3998 if (res < 0)
3999 goto out;
4000
4001 switch (cmd) {
4002 case SIOCGMIIPHY:
4003 data->phy_id = R8152_PHY_ID; /* Internal PHY */
4004 break;
4005
4006 case SIOCGMIIREG:
4007 mutex_lock(&tp->control);
4008 data->val_out = r8152_mdio_read(tp, data->reg_num);
4009 mutex_unlock(&tp->control);
4010 break;
4011
4012 case SIOCSMIIREG:
4013 if (!capable(CAP_NET_ADMIN)) {
4014 res = -EPERM;
4015 break;
4016 }
4017 mutex_lock(&tp->control);
4018 r8152_mdio_write(tp, data->reg_num, data->val_in);
4019 mutex_unlock(&tp->control);
4020 break;
4021
4022 default:
4023 res = -EOPNOTSUPP;
4024 }
4025
4026 usb_autopm_put_interface(tp->intf);
4027
4028 out:
4029 return res;
4030 }
4031
4032 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
4033 {
4034 struct r8152 *tp = netdev_priv(dev);
4035 int ret;
4036
4037 switch (tp->version) {
4038 case RTL_VER_01:
4039 case RTL_VER_02:
4040 return eth_change_mtu(dev, new_mtu);
4041 default:
4042 break;
4043 }
4044
4045 if (new_mtu < 68 || new_mtu > RTL8153_MAX_MTU)
4046 return -EINVAL;
4047
4048 ret = usb_autopm_get_interface(tp->intf);
4049 if (ret < 0)
4050 return ret;
4051
4052 mutex_lock(&tp->control);
4053
4054 dev->mtu = new_mtu;
4055
4056 if (netif_running(dev) && netif_carrier_ok(dev))
4057 r8153_set_rx_early_size(tp);
4058
4059 mutex_unlock(&tp->control);
4060
4061 usb_autopm_put_interface(tp->intf);
4062
4063 return ret;
4064 }
4065
4066 static const struct net_device_ops rtl8152_netdev_ops = {
4067 .ndo_open = rtl8152_open,
4068 .ndo_stop = rtl8152_close,
4069 .ndo_do_ioctl = rtl8152_ioctl,
4070 .ndo_start_xmit = rtl8152_start_xmit,
4071 .ndo_tx_timeout = rtl8152_tx_timeout,
4072 .ndo_set_features = rtl8152_set_features,
4073 .ndo_set_rx_mode = rtl8152_set_rx_mode,
4074 .ndo_set_mac_address = rtl8152_set_mac_address,
4075 .ndo_change_mtu = rtl8152_change_mtu,
4076 .ndo_validate_addr = eth_validate_addr,
4077 .ndo_features_check = rtl8152_features_check,
4078 };
4079
4080 static void r8152b_get_version(struct r8152 *tp)
4081 {
4082 u32 ocp_data;
4083 u16 version;
4084
4085 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
4086 version = (u16)(ocp_data & VERSION_MASK);
4087
4088 switch (version) {
4089 case 0x4c00:
4090 tp->version = RTL_VER_01;
4091 break;
4092 case 0x4c10:
4093 tp->version = RTL_VER_02;
4094 break;
4095 case 0x5c00:
4096 tp->version = RTL_VER_03;
4097 tp->mii.supports_gmii = 1;
4098 break;
4099 case 0x5c10:
4100 tp->version = RTL_VER_04;
4101 tp->mii.supports_gmii = 1;
4102 break;
4103 case 0x5c20:
4104 tp->version = RTL_VER_05;
4105 tp->mii.supports_gmii = 1;
4106 break;
4107 case 0x5c30:
4108 tp->version = RTL_VER_06;
4109 tp->mii.supports_gmii = 1;
4110 break;
4111 default:
4112 netif_info(tp, probe, tp->netdev,
4113 "Unknown version 0x%04x\n", version);
4114 break;
4115 }
4116 }
4117
4118 static void rtl8152_unload(struct r8152 *tp)
4119 {
4120 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4121 return;
4122
4123 if (tp->version != RTL_VER_01)
4124 r8152_power_cut_en(tp, true);
4125 }
4126
4127 static void rtl8153_unload(struct r8152 *tp)
4128 {
4129 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4130 return;
4131
4132 r8153_power_cut_en(tp, false);
4133 }
4134
4135 static int rtl_ops_init(struct r8152 *tp)
4136 {
4137 struct rtl_ops *ops = &tp->rtl_ops;
4138 int ret = 0;
4139
4140 switch (tp->version) {
4141 case RTL_VER_01:
4142 case RTL_VER_02:
4143 ops->init = r8152b_init;
4144 ops->enable = rtl8152_enable;
4145 ops->disable = rtl8152_disable;
4146 ops->up = rtl8152_up;
4147 ops->down = rtl8152_down;
4148 ops->unload = rtl8152_unload;
4149 ops->eee_get = r8152_get_eee;
4150 ops->eee_set = r8152_set_eee;
4151 ops->in_nway = rtl8152_in_nway;
4152 ops->hw_phy_cfg = r8152b_hw_phy_cfg;
4153 ops->autosuspend_en = rtl_runtime_suspend_enable;
4154 break;
4155
4156 case RTL_VER_03:
4157 case RTL_VER_04:
4158 case RTL_VER_05:
4159 case RTL_VER_06:
4160 ops->init = r8153_init;
4161 ops->enable = rtl8153_enable;
4162 ops->disable = rtl8153_disable;
4163 ops->up = rtl8153_up;
4164 ops->down = rtl8153_down;
4165 ops->unload = rtl8153_unload;
4166 ops->eee_get = r8153_get_eee;
4167 ops->eee_set = r8153_set_eee;
4168 ops->in_nway = rtl8153_in_nway;
4169 ops->hw_phy_cfg = r8153_hw_phy_cfg;
4170 ops->autosuspend_en = rtl8153_runtime_enable;
4171 break;
4172
4173 default:
4174 ret = -ENODEV;
4175 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
4176 break;
4177 }
4178
4179 return ret;
4180 }
4181
4182 static int rtl8152_probe(struct usb_interface *intf,
4183 const struct usb_device_id *id)
4184 {
4185 struct usb_device *udev = interface_to_usbdev(intf);
4186 struct r8152 *tp;
4187 struct net_device *netdev;
4188 int ret;
4189
4190 if (udev->actconfig->desc.bConfigurationValue != 1) {
4191 usb_driver_set_configuration(udev, 1);
4192 return -ENODEV;
4193 }
4194
4195 usb_reset_device(udev);
4196 netdev = alloc_etherdev(sizeof(struct r8152));
4197 if (!netdev) {
4198 dev_err(&intf->dev, "Out of memory\n");
4199 return -ENOMEM;
4200 }
4201
4202 SET_NETDEV_DEV(netdev, &intf->dev);
4203 tp = netdev_priv(netdev);
4204 tp->msg_enable = 0x7FFF;
4205
4206 tp->udev = udev;
4207 tp->netdev = netdev;
4208 tp->intf = intf;
4209
4210 r8152b_get_version(tp);
4211 ret = rtl_ops_init(tp);
4212 if (ret)
4213 goto out;
4214
4215 mutex_init(&tp->control);
4216 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
4217 INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t);
4218
4219 netdev->netdev_ops = &rtl8152_netdev_ops;
4220 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
4221
4222 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
4223 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
4224 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
4225 NETIF_F_HW_VLAN_CTAG_TX;
4226 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
4227 NETIF_F_TSO | NETIF_F_FRAGLIST |
4228 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
4229 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
4230 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
4231 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
4232 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
4233
4234 netdev->ethtool_ops = &ops;
4235 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
4236
4237 tp->mii.dev = netdev;
4238 tp->mii.mdio_read = read_mii_word;
4239 tp->mii.mdio_write = write_mii_word;
4240 tp->mii.phy_id_mask = 0x3f;
4241 tp->mii.reg_num_mask = 0x1f;
4242 tp->mii.phy_id = R8152_PHY_ID;
4243
4244 switch (udev->speed) {
4245 case USB_SPEED_SUPER:
4246 case USB_SPEED_SUPER_PLUS:
4247 tp->coalesce = COALESCE_SUPER;
4248 break;
4249 case USB_SPEED_HIGH:
4250 tp->coalesce = COALESCE_HIGH;
4251 break;
4252 default:
4253 tp->coalesce = COALESCE_SLOW;
4254 break;
4255 }
4256
4257 tp->autoneg = AUTONEG_ENABLE;
4258 tp->speed = tp->mii.supports_gmii ? SPEED_1000 : SPEED_100;
4259 tp->duplex = DUPLEX_FULL;
4260
4261 intf->needs_remote_wakeup = 1;
4262
4263 tp->rtl_ops.init(tp);
4264 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
4265 set_ethernet_addr(tp);
4266
4267 usb_set_intfdata(intf, tp);
4268 netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
4269
4270 ret = register_netdev(netdev);
4271 if (ret != 0) {
4272 netif_err(tp, probe, netdev, "couldn't register the device\n");
4273 goto out1;
4274 }
4275
4276 if (!rtl_can_wakeup(tp))
4277 __rtl_set_wol(tp, 0);
4278
4279 tp->saved_wolopts = __rtl_get_wol(tp);
4280 if (tp->saved_wolopts)
4281 device_set_wakeup_enable(&udev->dev, true);
4282 else
4283 device_set_wakeup_enable(&udev->dev, false);
4284
4285 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
4286
4287 return 0;
4288
4289 out1:
4290 netif_napi_del(&tp->napi);
4291 usb_set_intfdata(intf, NULL);
4292 out:
4293 free_netdev(netdev);
4294 return ret;
4295 }
4296
4297 static void rtl8152_disconnect(struct usb_interface *intf)
4298 {
4299 struct r8152 *tp = usb_get_intfdata(intf);
4300
4301 usb_set_intfdata(intf, NULL);
4302 if (tp) {
4303 struct usb_device *udev = tp->udev;
4304
4305 if (udev->state == USB_STATE_NOTATTACHED)
4306 set_bit(RTL8152_UNPLUG, &tp->flags);
4307
4308 netif_napi_del(&tp->napi);
4309 unregister_netdev(tp->netdev);
4310 cancel_delayed_work_sync(&tp->hw_phy_work);
4311 tp->rtl_ops.unload(tp);
4312 free_netdev(tp->netdev);
4313 }
4314 }
4315
4316 #define REALTEK_USB_DEVICE(vend, prod) \
4317 .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
4318 USB_DEVICE_ID_MATCH_INT_CLASS, \
4319 .idVendor = (vend), \
4320 .idProduct = (prod), \
4321 .bInterfaceClass = USB_CLASS_VENDOR_SPEC \
4322 }, \
4323 { \
4324 .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
4325 USB_DEVICE_ID_MATCH_DEVICE, \
4326 .idVendor = (vend), \
4327 .idProduct = (prod), \
4328 .bInterfaceClass = USB_CLASS_COMM, \
4329 .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
4330 .bInterfaceProtocol = USB_CDC_PROTO_NONE
4331
4332 /* table of devices that work with this driver */
4333 static struct usb_device_id rtl8152_table[] = {
4334 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
4335 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
4336 {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
4337 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)},
4338 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)},
4339 {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)},
4340 {}
4341 };
4342
4343 MODULE_DEVICE_TABLE(usb, rtl8152_table);
4344
4345 static struct usb_driver rtl8152_driver = {
4346 .name = MODULENAME,
4347 .id_table = rtl8152_table,
4348 .probe = rtl8152_probe,
4349 .disconnect = rtl8152_disconnect,
4350 .suspend = rtl8152_suspend,
4351 .resume = rtl8152_resume,
4352 .reset_resume = rtl8152_reset_resume,
4353 .pre_reset = rtl8152_pre_reset,
4354 .post_reset = rtl8152_post_reset,
4355 .supports_autosuspend = 1,
4356 .disable_hub_initiated_lpm = 1,
4357 };
4358
4359 module_usb_driver(rtl8152_driver);
4360
4361 MODULE_AUTHOR(DRIVER_AUTHOR);
4362 MODULE_DESCRIPTION(DRIVER_DESC);
4363 MODULE_LICENSE("GPL");
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