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[deliverable/linux.git] / drivers / net / vmxnet3 / vmxnet3_drv.c
1 /*
2 * Linux driver for VMware's vmxnet3 ethernet NIC.
3 *
4 * Copyright (C) 2008-2009, VMware, Inc. All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; version 2 of the License and no later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
13 * NON INFRINGEMENT. See the GNU General Public License for more
14 * details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * The full GNU General Public License is included in this distribution in
21 * the file called "COPYING".
22 *
23 * Maintained by: Shreyas Bhatewara <pv-drivers@vmware.com>
24 *
25 */
26
27 #include <linux/module.h>
28 #include <net/ip6_checksum.h>
29
30 #include "vmxnet3_int.h"
31
32 char vmxnet3_driver_name[] = "vmxnet3";
33 #define VMXNET3_DRIVER_DESC "VMware vmxnet3 virtual NIC driver"
34
35 /*
36 * PCI Device ID Table
37 * Last entry must be all 0s
38 */
39 static DEFINE_PCI_DEVICE_TABLE(vmxnet3_pciid_table) = {
40 {PCI_VDEVICE(VMWARE, PCI_DEVICE_ID_VMWARE_VMXNET3)},
41 {0}
42 };
43
44 MODULE_DEVICE_TABLE(pci, vmxnet3_pciid_table);
45
46 static atomic_t devices_found;
47
48 #define VMXNET3_MAX_DEVICES 10
49 static int enable_mq = 1;
50 static int irq_share_mode;
51
52 static void
53 vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac);
54
55 /*
56 * Enable/Disable the given intr
57 */
58 static void
59 vmxnet3_enable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx)
60 {
61 VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 0);
62 }
63
64
65 static void
66 vmxnet3_disable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx)
67 {
68 VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 1);
69 }
70
71
72 /*
73 * Enable/Disable all intrs used by the device
74 */
75 static void
76 vmxnet3_enable_all_intrs(struct vmxnet3_adapter *adapter)
77 {
78 int i;
79
80 for (i = 0; i < adapter->intr.num_intrs; i++)
81 vmxnet3_enable_intr(adapter, i);
82 adapter->shared->devRead.intrConf.intrCtrl &=
83 cpu_to_le32(~VMXNET3_IC_DISABLE_ALL);
84 }
85
86
87 static void
88 vmxnet3_disable_all_intrs(struct vmxnet3_adapter *adapter)
89 {
90 int i;
91
92 adapter->shared->devRead.intrConf.intrCtrl |=
93 cpu_to_le32(VMXNET3_IC_DISABLE_ALL);
94 for (i = 0; i < adapter->intr.num_intrs; i++)
95 vmxnet3_disable_intr(adapter, i);
96 }
97
98
99 static void
100 vmxnet3_ack_events(struct vmxnet3_adapter *adapter, u32 events)
101 {
102 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_ECR, events);
103 }
104
105
106 static bool
107 vmxnet3_tq_stopped(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
108 {
109 return tq->stopped;
110 }
111
112
113 static void
114 vmxnet3_tq_start(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
115 {
116 tq->stopped = false;
117 netif_start_subqueue(adapter->netdev, tq - adapter->tx_queue);
118 }
119
120
121 static void
122 vmxnet3_tq_wake(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
123 {
124 tq->stopped = false;
125 netif_wake_subqueue(adapter->netdev, (tq - adapter->tx_queue));
126 }
127
128
129 static void
130 vmxnet3_tq_stop(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
131 {
132 tq->stopped = true;
133 tq->num_stop++;
134 netif_stop_subqueue(adapter->netdev, (tq - adapter->tx_queue));
135 }
136
137
138 /*
139 * Check the link state. This may start or stop the tx queue.
140 */
141 static void
142 vmxnet3_check_link(struct vmxnet3_adapter *adapter, bool affectTxQueue)
143 {
144 u32 ret;
145 int i;
146 unsigned long flags;
147
148 spin_lock_irqsave(&adapter->cmd_lock, flags);
149 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK);
150 ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
151 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
152
153 adapter->link_speed = ret >> 16;
154 if (ret & 1) { /* Link is up. */
155 netdev_info(adapter->netdev, "NIC Link is Up %d Mbps\n",
156 adapter->link_speed);
157 if (!netif_carrier_ok(adapter->netdev))
158 netif_carrier_on(adapter->netdev);
159
160 if (affectTxQueue) {
161 for (i = 0; i < adapter->num_tx_queues; i++)
162 vmxnet3_tq_start(&adapter->tx_queue[i],
163 adapter);
164 }
165 } else {
166 netdev_info(adapter->netdev, "NIC Link is Down\n");
167 if (netif_carrier_ok(adapter->netdev))
168 netif_carrier_off(adapter->netdev);
169
170 if (affectTxQueue) {
171 for (i = 0; i < adapter->num_tx_queues; i++)
172 vmxnet3_tq_stop(&adapter->tx_queue[i], adapter);
173 }
174 }
175 }
176
177 static void
178 vmxnet3_process_events(struct vmxnet3_adapter *adapter)
179 {
180 int i;
181 unsigned long flags;
182 u32 events = le32_to_cpu(adapter->shared->ecr);
183 if (!events)
184 return;
185
186 vmxnet3_ack_events(adapter, events);
187
188 /* Check if link state has changed */
189 if (events & VMXNET3_ECR_LINK)
190 vmxnet3_check_link(adapter, true);
191
192 /* Check if there is an error on xmit/recv queues */
193 if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) {
194 spin_lock_irqsave(&adapter->cmd_lock, flags);
195 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
196 VMXNET3_CMD_GET_QUEUE_STATUS);
197 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
198
199 for (i = 0; i < adapter->num_tx_queues; i++)
200 if (adapter->tqd_start[i].status.stopped)
201 dev_err(&adapter->netdev->dev,
202 "%s: tq[%d] error 0x%x\n",
203 adapter->netdev->name, i, le32_to_cpu(
204 adapter->tqd_start[i].status.error));
205 for (i = 0; i < adapter->num_rx_queues; i++)
206 if (adapter->rqd_start[i].status.stopped)
207 dev_err(&adapter->netdev->dev,
208 "%s: rq[%d] error 0x%x\n",
209 adapter->netdev->name, i,
210 adapter->rqd_start[i].status.error);
211
212 schedule_work(&adapter->work);
213 }
214 }
215
216 #ifdef __BIG_ENDIAN_BITFIELD
217 /*
218 * The device expects the bitfields in shared structures to be written in
219 * little endian. When CPU is big endian, the following routines are used to
220 * correctly read and write into ABI.
221 * The general technique used here is : double word bitfields are defined in
222 * opposite order for big endian architecture. Then before reading them in
223 * driver the complete double word is translated using le32_to_cpu. Similarly
224 * After the driver writes into bitfields, cpu_to_le32 is used to translate the
225 * double words into required format.
226 * In order to avoid touching bits in shared structure more than once, temporary
227 * descriptors are used. These are passed as srcDesc to following functions.
228 */
229 static void vmxnet3_RxDescToCPU(const struct Vmxnet3_RxDesc *srcDesc,
230 struct Vmxnet3_RxDesc *dstDesc)
231 {
232 u32 *src = (u32 *)srcDesc + 2;
233 u32 *dst = (u32 *)dstDesc + 2;
234 dstDesc->addr = le64_to_cpu(srcDesc->addr);
235 *dst = le32_to_cpu(*src);
236 dstDesc->ext1 = le32_to_cpu(srcDesc->ext1);
237 }
238
239 static void vmxnet3_TxDescToLe(const struct Vmxnet3_TxDesc *srcDesc,
240 struct Vmxnet3_TxDesc *dstDesc)
241 {
242 int i;
243 u32 *src = (u32 *)(srcDesc + 1);
244 u32 *dst = (u32 *)(dstDesc + 1);
245
246 /* Working backwards so that the gen bit is set at the end. */
247 for (i = 2; i > 0; i--) {
248 src--;
249 dst--;
250 *dst = cpu_to_le32(*src);
251 }
252 }
253
254
255 static void vmxnet3_RxCompToCPU(const struct Vmxnet3_RxCompDesc *srcDesc,
256 struct Vmxnet3_RxCompDesc *dstDesc)
257 {
258 int i = 0;
259 u32 *src = (u32 *)srcDesc;
260 u32 *dst = (u32 *)dstDesc;
261 for (i = 0; i < sizeof(struct Vmxnet3_RxCompDesc) / sizeof(u32); i++) {
262 *dst = le32_to_cpu(*src);
263 src++;
264 dst++;
265 }
266 }
267
268
269 /* Used to read bitfield values from double words. */
270 static u32 get_bitfield32(const __le32 *bitfield, u32 pos, u32 size)
271 {
272 u32 temp = le32_to_cpu(*bitfield);
273 u32 mask = ((1 << size) - 1) << pos;
274 temp &= mask;
275 temp >>= pos;
276 return temp;
277 }
278
279
280
281 #endif /* __BIG_ENDIAN_BITFIELD */
282
283 #ifdef __BIG_ENDIAN_BITFIELD
284
285 # define VMXNET3_TXDESC_GET_GEN(txdesc) get_bitfield32(((const __le32 *) \
286 txdesc) + VMXNET3_TXD_GEN_DWORD_SHIFT, \
287 VMXNET3_TXD_GEN_SHIFT, VMXNET3_TXD_GEN_SIZE)
288 # define VMXNET3_TXDESC_GET_EOP(txdesc) get_bitfield32(((const __le32 *) \
289 txdesc) + VMXNET3_TXD_EOP_DWORD_SHIFT, \
290 VMXNET3_TXD_EOP_SHIFT, VMXNET3_TXD_EOP_SIZE)
291 # define VMXNET3_TCD_GET_GEN(tcd) get_bitfield32(((const __le32 *)tcd) + \
292 VMXNET3_TCD_GEN_DWORD_SHIFT, VMXNET3_TCD_GEN_SHIFT, \
293 VMXNET3_TCD_GEN_SIZE)
294 # define VMXNET3_TCD_GET_TXIDX(tcd) get_bitfield32((const __le32 *)tcd, \
295 VMXNET3_TCD_TXIDX_SHIFT, VMXNET3_TCD_TXIDX_SIZE)
296 # define vmxnet3_getRxComp(dstrcd, rcd, tmp) do { \
297 (dstrcd) = (tmp); \
298 vmxnet3_RxCompToCPU((rcd), (tmp)); \
299 } while (0)
300 # define vmxnet3_getRxDesc(dstrxd, rxd, tmp) do { \
301 (dstrxd) = (tmp); \
302 vmxnet3_RxDescToCPU((rxd), (tmp)); \
303 } while (0)
304
305 #else
306
307 # define VMXNET3_TXDESC_GET_GEN(txdesc) ((txdesc)->gen)
308 # define VMXNET3_TXDESC_GET_EOP(txdesc) ((txdesc)->eop)
309 # define VMXNET3_TCD_GET_GEN(tcd) ((tcd)->gen)
310 # define VMXNET3_TCD_GET_TXIDX(tcd) ((tcd)->txdIdx)
311 # define vmxnet3_getRxComp(dstrcd, rcd, tmp) (dstrcd) = (rcd)
312 # define vmxnet3_getRxDesc(dstrxd, rxd, tmp) (dstrxd) = (rxd)
313
314 #endif /* __BIG_ENDIAN_BITFIELD */
315
316
317 static void
318 vmxnet3_unmap_tx_buf(struct vmxnet3_tx_buf_info *tbi,
319 struct pci_dev *pdev)
320 {
321 if (tbi->map_type == VMXNET3_MAP_SINGLE)
322 pci_unmap_single(pdev, tbi->dma_addr, tbi->len,
323 PCI_DMA_TODEVICE);
324 else if (tbi->map_type == VMXNET3_MAP_PAGE)
325 pci_unmap_page(pdev, tbi->dma_addr, tbi->len,
326 PCI_DMA_TODEVICE);
327 else
328 BUG_ON(tbi->map_type != VMXNET3_MAP_NONE);
329
330 tbi->map_type = VMXNET3_MAP_NONE; /* to help debugging */
331 }
332
333
334 static int
335 vmxnet3_unmap_pkt(u32 eop_idx, struct vmxnet3_tx_queue *tq,
336 struct pci_dev *pdev, struct vmxnet3_adapter *adapter)
337 {
338 struct sk_buff *skb;
339 int entries = 0;
340
341 /* no out of order completion */
342 BUG_ON(tq->buf_info[eop_idx].sop_idx != tq->tx_ring.next2comp);
343 BUG_ON(VMXNET3_TXDESC_GET_EOP(&(tq->tx_ring.base[eop_idx].txd)) != 1);
344
345 skb = tq->buf_info[eop_idx].skb;
346 BUG_ON(skb == NULL);
347 tq->buf_info[eop_idx].skb = NULL;
348
349 VMXNET3_INC_RING_IDX_ONLY(eop_idx, tq->tx_ring.size);
350
351 while (tq->tx_ring.next2comp != eop_idx) {
352 vmxnet3_unmap_tx_buf(tq->buf_info + tq->tx_ring.next2comp,
353 pdev);
354
355 /* update next2comp w/o tx_lock. Since we are marking more,
356 * instead of less, tx ring entries avail, the worst case is
357 * that the tx routine incorrectly re-queues a pkt due to
358 * insufficient tx ring entries.
359 */
360 vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring);
361 entries++;
362 }
363
364 dev_kfree_skb_any(skb);
365 return entries;
366 }
367
368
369 static int
370 vmxnet3_tq_tx_complete(struct vmxnet3_tx_queue *tq,
371 struct vmxnet3_adapter *adapter)
372 {
373 int completed = 0;
374 union Vmxnet3_GenericDesc *gdesc;
375
376 gdesc = tq->comp_ring.base + tq->comp_ring.next2proc;
377 while (VMXNET3_TCD_GET_GEN(&gdesc->tcd) == tq->comp_ring.gen) {
378 completed += vmxnet3_unmap_pkt(VMXNET3_TCD_GET_TXIDX(
379 &gdesc->tcd), tq, adapter->pdev,
380 adapter);
381
382 vmxnet3_comp_ring_adv_next2proc(&tq->comp_ring);
383 gdesc = tq->comp_ring.base + tq->comp_ring.next2proc;
384 }
385
386 if (completed) {
387 spin_lock(&tq->tx_lock);
388 if (unlikely(vmxnet3_tq_stopped(tq, adapter) &&
389 vmxnet3_cmd_ring_desc_avail(&tq->tx_ring) >
390 VMXNET3_WAKE_QUEUE_THRESHOLD(tq) &&
391 netif_carrier_ok(adapter->netdev))) {
392 vmxnet3_tq_wake(tq, adapter);
393 }
394 spin_unlock(&tq->tx_lock);
395 }
396 return completed;
397 }
398
399
400 static void
401 vmxnet3_tq_cleanup(struct vmxnet3_tx_queue *tq,
402 struct vmxnet3_adapter *adapter)
403 {
404 int i;
405
406 while (tq->tx_ring.next2comp != tq->tx_ring.next2fill) {
407 struct vmxnet3_tx_buf_info *tbi;
408
409 tbi = tq->buf_info + tq->tx_ring.next2comp;
410
411 vmxnet3_unmap_tx_buf(tbi, adapter->pdev);
412 if (tbi->skb) {
413 dev_kfree_skb_any(tbi->skb);
414 tbi->skb = NULL;
415 }
416 vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring);
417 }
418
419 /* sanity check, verify all buffers are indeed unmapped and freed */
420 for (i = 0; i < tq->tx_ring.size; i++) {
421 BUG_ON(tq->buf_info[i].skb != NULL ||
422 tq->buf_info[i].map_type != VMXNET3_MAP_NONE);
423 }
424
425 tq->tx_ring.gen = VMXNET3_INIT_GEN;
426 tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0;
427
428 tq->comp_ring.gen = VMXNET3_INIT_GEN;
429 tq->comp_ring.next2proc = 0;
430 }
431
432
433 static void
434 vmxnet3_tq_destroy(struct vmxnet3_tx_queue *tq,
435 struct vmxnet3_adapter *adapter)
436 {
437 if (tq->tx_ring.base) {
438 pci_free_consistent(adapter->pdev, tq->tx_ring.size *
439 sizeof(struct Vmxnet3_TxDesc),
440 tq->tx_ring.base, tq->tx_ring.basePA);
441 tq->tx_ring.base = NULL;
442 }
443 if (tq->data_ring.base) {
444 pci_free_consistent(adapter->pdev, tq->data_ring.size *
445 sizeof(struct Vmxnet3_TxDataDesc),
446 tq->data_ring.base, tq->data_ring.basePA);
447 tq->data_ring.base = NULL;
448 }
449 if (tq->comp_ring.base) {
450 pci_free_consistent(adapter->pdev, tq->comp_ring.size *
451 sizeof(struct Vmxnet3_TxCompDesc),
452 tq->comp_ring.base, tq->comp_ring.basePA);
453 tq->comp_ring.base = NULL;
454 }
455 kfree(tq->buf_info);
456 tq->buf_info = NULL;
457 }
458
459
460 /* Destroy all tx queues */
461 void
462 vmxnet3_tq_destroy_all(struct vmxnet3_adapter *adapter)
463 {
464 int i;
465
466 for (i = 0; i < adapter->num_tx_queues; i++)
467 vmxnet3_tq_destroy(&adapter->tx_queue[i], adapter);
468 }
469
470
471 static void
472 vmxnet3_tq_init(struct vmxnet3_tx_queue *tq,
473 struct vmxnet3_adapter *adapter)
474 {
475 int i;
476
477 /* reset the tx ring contents to 0 and reset the tx ring states */
478 memset(tq->tx_ring.base, 0, tq->tx_ring.size *
479 sizeof(struct Vmxnet3_TxDesc));
480 tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0;
481 tq->tx_ring.gen = VMXNET3_INIT_GEN;
482
483 memset(tq->data_ring.base, 0, tq->data_ring.size *
484 sizeof(struct Vmxnet3_TxDataDesc));
485
486 /* reset the tx comp ring contents to 0 and reset comp ring states */
487 memset(tq->comp_ring.base, 0, tq->comp_ring.size *
488 sizeof(struct Vmxnet3_TxCompDesc));
489 tq->comp_ring.next2proc = 0;
490 tq->comp_ring.gen = VMXNET3_INIT_GEN;
491
492 /* reset the bookkeeping data */
493 memset(tq->buf_info, 0, sizeof(tq->buf_info[0]) * tq->tx_ring.size);
494 for (i = 0; i < tq->tx_ring.size; i++)
495 tq->buf_info[i].map_type = VMXNET3_MAP_NONE;
496
497 /* stats are not reset */
498 }
499
500
501 static int
502 vmxnet3_tq_create(struct vmxnet3_tx_queue *tq,
503 struct vmxnet3_adapter *adapter)
504 {
505 BUG_ON(tq->tx_ring.base || tq->data_ring.base ||
506 tq->comp_ring.base || tq->buf_info);
507
508 tq->tx_ring.base = pci_alloc_consistent(adapter->pdev, tq->tx_ring.size
509 * sizeof(struct Vmxnet3_TxDesc),
510 &tq->tx_ring.basePA);
511 if (!tq->tx_ring.base) {
512 netdev_err(adapter->netdev, "failed to allocate tx ring\n");
513 goto err;
514 }
515
516 tq->data_ring.base = pci_alloc_consistent(adapter->pdev,
517 tq->data_ring.size *
518 sizeof(struct Vmxnet3_TxDataDesc),
519 &tq->data_ring.basePA);
520 if (!tq->data_ring.base) {
521 netdev_err(adapter->netdev, "failed to allocate data ring\n");
522 goto err;
523 }
524
525 tq->comp_ring.base = pci_alloc_consistent(adapter->pdev,
526 tq->comp_ring.size *
527 sizeof(struct Vmxnet3_TxCompDesc),
528 &tq->comp_ring.basePA);
529 if (!tq->comp_ring.base) {
530 netdev_err(adapter->netdev, "failed to allocate tx comp ring\n");
531 goto err;
532 }
533
534 tq->buf_info = kcalloc(tq->tx_ring.size, sizeof(tq->buf_info[0]),
535 GFP_KERNEL);
536 if (!tq->buf_info)
537 goto err;
538
539 return 0;
540
541 err:
542 vmxnet3_tq_destroy(tq, adapter);
543 return -ENOMEM;
544 }
545
546 static void
547 vmxnet3_tq_cleanup_all(struct vmxnet3_adapter *adapter)
548 {
549 int i;
550
551 for (i = 0; i < adapter->num_tx_queues; i++)
552 vmxnet3_tq_cleanup(&adapter->tx_queue[i], adapter);
553 }
554
555 /*
556 * starting from ring->next2fill, allocate rx buffers for the given ring
557 * of the rx queue and update the rx desc. stop after @num_to_alloc buffers
558 * are allocated or allocation fails
559 */
560
561 static int
562 vmxnet3_rq_alloc_rx_buf(struct vmxnet3_rx_queue *rq, u32 ring_idx,
563 int num_to_alloc, struct vmxnet3_adapter *adapter)
564 {
565 int num_allocated = 0;
566 struct vmxnet3_rx_buf_info *rbi_base = rq->buf_info[ring_idx];
567 struct vmxnet3_cmd_ring *ring = &rq->rx_ring[ring_idx];
568 u32 val;
569
570 while (num_allocated <= num_to_alloc) {
571 struct vmxnet3_rx_buf_info *rbi;
572 union Vmxnet3_GenericDesc *gd;
573
574 rbi = rbi_base + ring->next2fill;
575 gd = ring->base + ring->next2fill;
576
577 if (rbi->buf_type == VMXNET3_RX_BUF_SKB) {
578 if (rbi->skb == NULL) {
579 rbi->skb = __netdev_alloc_skb_ip_align(adapter->netdev,
580 rbi->len,
581 GFP_KERNEL);
582 if (unlikely(rbi->skb == NULL)) {
583 rq->stats.rx_buf_alloc_failure++;
584 break;
585 }
586
587 rbi->dma_addr = pci_map_single(adapter->pdev,
588 rbi->skb->data, rbi->len,
589 PCI_DMA_FROMDEVICE);
590 } else {
591 /* rx buffer skipped by the device */
592 }
593 val = VMXNET3_RXD_BTYPE_HEAD << VMXNET3_RXD_BTYPE_SHIFT;
594 } else {
595 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_PAGE ||
596 rbi->len != PAGE_SIZE);
597
598 if (rbi->page == NULL) {
599 rbi->page = alloc_page(GFP_ATOMIC);
600 if (unlikely(rbi->page == NULL)) {
601 rq->stats.rx_buf_alloc_failure++;
602 break;
603 }
604 rbi->dma_addr = pci_map_page(adapter->pdev,
605 rbi->page, 0, PAGE_SIZE,
606 PCI_DMA_FROMDEVICE);
607 } else {
608 /* rx buffers skipped by the device */
609 }
610 val = VMXNET3_RXD_BTYPE_BODY << VMXNET3_RXD_BTYPE_SHIFT;
611 }
612
613 BUG_ON(rbi->dma_addr == 0);
614 gd->rxd.addr = cpu_to_le64(rbi->dma_addr);
615 gd->dword[2] = cpu_to_le32((!ring->gen << VMXNET3_RXD_GEN_SHIFT)
616 | val | rbi->len);
617
618 /* Fill the last buffer but dont mark it ready, or else the
619 * device will think that the queue is full */
620 if (num_allocated == num_to_alloc)
621 break;
622
623 gd->dword[2] |= cpu_to_le32(ring->gen << VMXNET3_RXD_GEN_SHIFT);
624 num_allocated++;
625 vmxnet3_cmd_ring_adv_next2fill(ring);
626 }
627
628 netdev_dbg(adapter->netdev,
629 "alloc_rx_buf: %d allocated, next2fill %u, next2comp %u\n",
630 num_allocated, ring->next2fill, ring->next2comp);
631
632 /* so that the device can distinguish a full ring and an empty ring */
633 BUG_ON(num_allocated != 0 && ring->next2fill == ring->next2comp);
634
635 return num_allocated;
636 }
637
638
639 static void
640 vmxnet3_append_frag(struct sk_buff *skb, struct Vmxnet3_RxCompDesc *rcd,
641 struct vmxnet3_rx_buf_info *rbi)
642 {
643 struct skb_frag_struct *frag = skb_shinfo(skb)->frags +
644 skb_shinfo(skb)->nr_frags;
645
646 BUG_ON(skb_shinfo(skb)->nr_frags >= MAX_SKB_FRAGS);
647
648 __skb_frag_set_page(frag, rbi->page);
649 frag->page_offset = 0;
650 skb_frag_size_set(frag, rcd->len);
651 skb->data_len += rcd->len;
652 skb->truesize += PAGE_SIZE;
653 skb_shinfo(skb)->nr_frags++;
654 }
655
656
657 static void
658 vmxnet3_map_pkt(struct sk_buff *skb, struct vmxnet3_tx_ctx *ctx,
659 struct vmxnet3_tx_queue *tq, struct pci_dev *pdev,
660 struct vmxnet3_adapter *adapter)
661 {
662 u32 dw2, len;
663 unsigned long buf_offset;
664 int i;
665 union Vmxnet3_GenericDesc *gdesc;
666 struct vmxnet3_tx_buf_info *tbi = NULL;
667
668 BUG_ON(ctx->copy_size > skb_headlen(skb));
669
670 /* use the previous gen bit for the SOP desc */
671 dw2 = (tq->tx_ring.gen ^ 0x1) << VMXNET3_TXD_GEN_SHIFT;
672
673 ctx->sop_txd = tq->tx_ring.base + tq->tx_ring.next2fill;
674 gdesc = ctx->sop_txd; /* both loops below can be skipped */
675
676 /* no need to map the buffer if headers are copied */
677 if (ctx->copy_size) {
678 ctx->sop_txd->txd.addr = cpu_to_le64(tq->data_ring.basePA +
679 tq->tx_ring.next2fill *
680 sizeof(struct Vmxnet3_TxDataDesc));
681 ctx->sop_txd->dword[2] = cpu_to_le32(dw2 | ctx->copy_size);
682 ctx->sop_txd->dword[3] = 0;
683
684 tbi = tq->buf_info + tq->tx_ring.next2fill;
685 tbi->map_type = VMXNET3_MAP_NONE;
686
687 netdev_dbg(adapter->netdev,
688 "txd[%u]: 0x%Lx 0x%x 0x%x\n",
689 tq->tx_ring.next2fill,
690 le64_to_cpu(ctx->sop_txd->txd.addr),
691 ctx->sop_txd->dword[2], ctx->sop_txd->dword[3]);
692 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
693
694 /* use the right gen for non-SOP desc */
695 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
696 }
697
698 /* linear part can use multiple tx desc if it's big */
699 len = skb_headlen(skb) - ctx->copy_size;
700 buf_offset = ctx->copy_size;
701 while (len) {
702 u32 buf_size;
703
704 if (len < VMXNET3_MAX_TX_BUF_SIZE) {
705 buf_size = len;
706 dw2 |= len;
707 } else {
708 buf_size = VMXNET3_MAX_TX_BUF_SIZE;
709 /* spec says that for TxDesc.len, 0 == 2^14 */
710 }
711
712 tbi = tq->buf_info + tq->tx_ring.next2fill;
713 tbi->map_type = VMXNET3_MAP_SINGLE;
714 tbi->dma_addr = pci_map_single(adapter->pdev,
715 skb->data + buf_offset, buf_size,
716 PCI_DMA_TODEVICE);
717
718 tbi->len = buf_size;
719
720 gdesc = tq->tx_ring.base + tq->tx_ring.next2fill;
721 BUG_ON(gdesc->txd.gen == tq->tx_ring.gen);
722
723 gdesc->txd.addr = cpu_to_le64(tbi->dma_addr);
724 gdesc->dword[2] = cpu_to_le32(dw2);
725 gdesc->dword[3] = 0;
726
727 netdev_dbg(adapter->netdev,
728 "txd[%u]: 0x%Lx 0x%x 0x%x\n",
729 tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr),
730 le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]);
731 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
732 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
733
734 len -= buf_size;
735 buf_offset += buf_size;
736 }
737
738 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
739 const struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
740 u32 buf_size;
741
742 buf_offset = 0;
743 len = skb_frag_size(frag);
744 while (len) {
745 tbi = tq->buf_info + tq->tx_ring.next2fill;
746 if (len < VMXNET3_MAX_TX_BUF_SIZE) {
747 buf_size = len;
748 dw2 |= len;
749 } else {
750 buf_size = VMXNET3_MAX_TX_BUF_SIZE;
751 /* spec says that for TxDesc.len, 0 == 2^14 */
752 }
753 tbi->map_type = VMXNET3_MAP_PAGE;
754 tbi->dma_addr = skb_frag_dma_map(&adapter->pdev->dev, frag,
755 buf_offset, buf_size,
756 DMA_TO_DEVICE);
757
758 tbi->len = buf_size;
759
760 gdesc = tq->tx_ring.base + tq->tx_ring.next2fill;
761 BUG_ON(gdesc->txd.gen == tq->tx_ring.gen);
762
763 gdesc->txd.addr = cpu_to_le64(tbi->dma_addr);
764 gdesc->dword[2] = cpu_to_le32(dw2);
765 gdesc->dword[3] = 0;
766
767 netdev_dbg(adapter->netdev,
768 "txd[%u]: 0x%llu %u %u\n",
769 tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr),
770 le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]);
771 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
772 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
773
774 len -= buf_size;
775 buf_offset += buf_size;
776 }
777 }
778
779 ctx->eop_txd = gdesc;
780
781 /* set the last buf_info for the pkt */
782 tbi->skb = skb;
783 tbi->sop_idx = ctx->sop_txd - tq->tx_ring.base;
784 }
785
786
787 /* Init all tx queues */
788 static void
789 vmxnet3_tq_init_all(struct vmxnet3_adapter *adapter)
790 {
791 int i;
792
793 for (i = 0; i < adapter->num_tx_queues; i++)
794 vmxnet3_tq_init(&adapter->tx_queue[i], adapter);
795 }
796
797
798 /*
799 * parse and copy relevant protocol headers:
800 * For a tso pkt, relevant headers are L2/3/4 including options
801 * For a pkt requesting csum offloading, they are L2/3 and may include L4
802 * if it's a TCP/UDP pkt
803 *
804 * Returns:
805 * -1: error happens during parsing
806 * 0: protocol headers parsed, but too big to be copied
807 * 1: protocol headers parsed and copied
808 *
809 * Other effects:
810 * 1. related *ctx fields are updated.
811 * 2. ctx->copy_size is # of bytes copied
812 * 3. the portion copied is guaranteed to be in the linear part
813 *
814 */
815 static int
816 vmxnet3_parse_and_copy_hdr(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
817 struct vmxnet3_tx_ctx *ctx,
818 struct vmxnet3_adapter *adapter)
819 {
820 struct Vmxnet3_TxDataDesc *tdd;
821
822 if (ctx->mss) { /* TSO */
823 ctx->eth_ip_hdr_size = skb_transport_offset(skb);
824 ctx->l4_hdr_size = tcp_hdrlen(skb);
825 ctx->copy_size = ctx->eth_ip_hdr_size + ctx->l4_hdr_size;
826 } else {
827 if (skb->ip_summed == CHECKSUM_PARTIAL) {
828 ctx->eth_ip_hdr_size = skb_checksum_start_offset(skb);
829
830 if (ctx->ipv4) {
831 const struct iphdr *iph = ip_hdr(skb);
832
833 if (iph->protocol == IPPROTO_TCP)
834 ctx->l4_hdr_size = tcp_hdrlen(skb);
835 else if (iph->protocol == IPPROTO_UDP)
836 ctx->l4_hdr_size = sizeof(struct udphdr);
837 else
838 ctx->l4_hdr_size = 0;
839 } else {
840 /* for simplicity, don't copy L4 headers */
841 ctx->l4_hdr_size = 0;
842 }
843 ctx->copy_size = min(ctx->eth_ip_hdr_size +
844 ctx->l4_hdr_size, skb->len);
845 } else {
846 ctx->eth_ip_hdr_size = 0;
847 ctx->l4_hdr_size = 0;
848 /* copy as much as allowed */
849 ctx->copy_size = min((unsigned int)VMXNET3_HDR_COPY_SIZE
850 , skb_headlen(skb));
851 }
852
853 /* make sure headers are accessible directly */
854 if (unlikely(!pskb_may_pull(skb, ctx->copy_size)))
855 goto err;
856 }
857
858 if (unlikely(ctx->copy_size > VMXNET3_HDR_COPY_SIZE)) {
859 tq->stats.oversized_hdr++;
860 ctx->copy_size = 0;
861 return 0;
862 }
863
864 tdd = tq->data_ring.base + tq->tx_ring.next2fill;
865
866 memcpy(tdd->data, skb->data, ctx->copy_size);
867 netdev_dbg(adapter->netdev,
868 "copy %u bytes to dataRing[%u]\n",
869 ctx->copy_size, tq->tx_ring.next2fill);
870 return 1;
871
872 err:
873 return -1;
874 }
875
876
877 static void
878 vmxnet3_prepare_tso(struct sk_buff *skb,
879 struct vmxnet3_tx_ctx *ctx)
880 {
881 struct tcphdr *tcph = tcp_hdr(skb);
882
883 if (ctx->ipv4) {
884 struct iphdr *iph = ip_hdr(skb);
885
886 iph->check = 0;
887 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0,
888 IPPROTO_TCP, 0);
889 } else {
890 struct ipv6hdr *iph = ipv6_hdr(skb);
891
892 tcph->check = ~csum_ipv6_magic(&iph->saddr, &iph->daddr, 0,
893 IPPROTO_TCP, 0);
894 }
895 }
896
897 static int txd_estimate(const struct sk_buff *skb)
898 {
899 int count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + 1;
900 int i;
901
902 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
903 const struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
904
905 count += VMXNET3_TXD_NEEDED(skb_frag_size(frag));
906 }
907 return count;
908 }
909
910 /*
911 * Transmits a pkt thru a given tq
912 * Returns:
913 * NETDEV_TX_OK: descriptors are setup successfully
914 * NETDEV_TX_OK: error occurred, the pkt is dropped
915 * NETDEV_TX_BUSY: tx ring is full, queue is stopped
916 *
917 * Side-effects:
918 * 1. tx ring may be changed
919 * 2. tq stats may be updated accordingly
920 * 3. shared->txNumDeferred may be updated
921 */
922
923 static int
924 vmxnet3_tq_xmit(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
925 struct vmxnet3_adapter *adapter, struct net_device *netdev)
926 {
927 int ret;
928 u32 count;
929 unsigned long flags;
930 struct vmxnet3_tx_ctx ctx;
931 union Vmxnet3_GenericDesc *gdesc;
932 #ifdef __BIG_ENDIAN_BITFIELD
933 /* Use temporary descriptor to avoid touching bits multiple times */
934 union Vmxnet3_GenericDesc tempTxDesc;
935 #endif
936
937 count = txd_estimate(skb);
938
939 ctx.ipv4 = (vlan_get_protocol(skb) == cpu_to_be16(ETH_P_IP));
940
941 ctx.mss = skb_shinfo(skb)->gso_size;
942 if (ctx.mss) {
943 if (skb_header_cloned(skb)) {
944 if (unlikely(pskb_expand_head(skb, 0, 0,
945 GFP_ATOMIC) != 0)) {
946 tq->stats.drop_tso++;
947 goto drop_pkt;
948 }
949 tq->stats.copy_skb_header++;
950 }
951 vmxnet3_prepare_tso(skb, &ctx);
952 } else {
953 if (unlikely(count > VMXNET3_MAX_TXD_PER_PKT)) {
954
955 /* non-tso pkts must not use more than
956 * VMXNET3_MAX_TXD_PER_PKT entries
957 */
958 if (skb_linearize(skb) != 0) {
959 tq->stats.drop_too_many_frags++;
960 goto drop_pkt;
961 }
962 tq->stats.linearized++;
963
964 /* recalculate the # of descriptors to use */
965 count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + 1;
966 }
967 }
968
969 spin_lock_irqsave(&tq->tx_lock, flags);
970
971 if (count > vmxnet3_cmd_ring_desc_avail(&tq->tx_ring)) {
972 tq->stats.tx_ring_full++;
973 netdev_dbg(adapter->netdev,
974 "tx queue stopped on %s, next2comp %u"
975 " next2fill %u\n", adapter->netdev->name,
976 tq->tx_ring.next2comp, tq->tx_ring.next2fill);
977
978 vmxnet3_tq_stop(tq, adapter);
979 spin_unlock_irqrestore(&tq->tx_lock, flags);
980 return NETDEV_TX_BUSY;
981 }
982
983
984 ret = vmxnet3_parse_and_copy_hdr(skb, tq, &ctx, adapter);
985 if (ret >= 0) {
986 BUG_ON(ret <= 0 && ctx.copy_size != 0);
987 /* hdrs parsed, check against other limits */
988 if (ctx.mss) {
989 if (unlikely(ctx.eth_ip_hdr_size + ctx.l4_hdr_size >
990 VMXNET3_MAX_TX_BUF_SIZE)) {
991 goto hdr_too_big;
992 }
993 } else {
994 if (skb->ip_summed == CHECKSUM_PARTIAL) {
995 if (unlikely(ctx.eth_ip_hdr_size +
996 skb->csum_offset >
997 VMXNET3_MAX_CSUM_OFFSET)) {
998 goto hdr_too_big;
999 }
1000 }
1001 }
1002 } else {
1003 tq->stats.drop_hdr_inspect_err++;
1004 goto unlock_drop_pkt;
1005 }
1006
1007 /* fill tx descs related to addr & len */
1008 vmxnet3_map_pkt(skb, &ctx, tq, adapter->pdev, adapter);
1009
1010 /* setup the EOP desc */
1011 ctx.eop_txd->dword[3] = cpu_to_le32(VMXNET3_TXD_CQ | VMXNET3_TXD_EOP);
1012
1013 /* setup the SOP desc */
1014 #ifdef __BIG_ENDIAN_BITFIELD
1015 gdesc = &tempTxDesc;
1016 gdesc->dword[2] = ctx.sop_txd->dword[2];
1017 gdesc->dword[3] = ctx.sop_txd->dword[3];
1018 #else
1019 gdesc = ctx.sop_txd;
1020 #endif
1021 if (ctx.mss) {
1022 gdesc->txd.hlen = ctx.eth_ip_hdr_size + ctx.l4_hdr_size;
1023 gdesc->txd.om = VMXNET3_OM_TSO;
1024 gdesc->txd.msscof = ctx.mss;
1025 le32_add_cpu(&tq->shared->txNumDeferred, (skb->len -
1026 gdesc->txd.hlen + ctx.mss - 1) / ctx.mss);
1027 } else {
1028 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1029 gdesc->txd.hlen = ctx.eth_ip_hdr_size;
1030 gdesc->txd.om = VMXNET3_OM_CSUM;
1031 gdesc->txd.msscof = ctx.eth_ip_hdr_size +
1032 skb->csum_offset;
1033 } else {
1034 gdesc->txd.om = 0;
1035 gdesc->txd.msscof = 0;
1036 }
1037 le32_add_cpu(&tq->shared->txNumDeferred, 1);
1038 }
1039
1040 if (vlan_tx_tag_present(skb)) {
1041 gdesc->txd.ti = 1;
1042 gdesc->txd.tci = vlan_tx_tag_get(skb);
1043 }
1044
1045 /* finally flips the GEN bit of the SOP desc. */
1046 gdesc->dword[2] = cpu_to_le32(le32_to_cpu(gdesc->dword[2]) ^
1047 VMXNET3_TXD_GEN);
1048 #ifdef __BIG_ENDIAN_BITFIELD
1049 /* Finished updating in bitfields of Tx Desc, so write them in original
1050 * place.
1051 */
1052 vmxnet3_TxDescToLe((struct Vmxnet3_TxDesc *)gdesc,
1053 (struct Vmxnet3_TxDesc *)ctx.sop_txd);
1054 gdesc = ctx.sop_txd;
1055 #endif
1056 netdev_dbg(adapter->netdev,
1057 "txd[%u]: SOP 0x%Lx 0x%x 0x%x\n",
1058 (u32)(ctx.sop_txd -
1059 tq->tx_ring.base), le64_to_cpu(gdesc->txd.addr),
1060 le32_to_cpu(gdesc->dword[2]), le32_to_cpu(gdesc->dword[3]));
1061
1062 spin_unlock_irqrestore(&tq->tx_lock, flags);
1063
1064 if (le32_to_cpu(tq->shared->txNumDeferred) >=
1065 le32_to_cpu(tq->shared->txThreshold)) {
1066 tq->shared->txNumDeferred = 0;
1067 VMXNET3_WRITE_BAR0_REG(adapter,
1068 VMXNET3_REG_TXPROD + tq->qid * 8,
1069 tq->tx_ring.next2fill);
1070 }
1071
1072 return NETDEV_TX_OK;
1073
1074 hdr_too_big:
1075 tq->stats.drop_oversized_hdr++;
1076 unlock_drop_pkt:
1077 spin_unlock_irqrestore(&tq->tx_lock, flags);
1078 drop_pkt:
1079 tq->stats.drop_total++;
1080 dev_kfree_skb(skb);
1081 return NETDEV_TX_OK;
1082 }
1083
1084
1085 static netdev_tx_t
1086 vmxnet3_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1087 {
1088 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
1089
1090 BUG_ON(skb->queue_mapping > adapter->num_tx_queues);
1091 return vmxnet3_tq_xmit(skb,
1092 &adapter->tx_queue[skb->queue_mapping],
1093 adapter, netdev);
1094 }
1095
1096
1097 static void
1098 vmxnet3_rx_csum(struct vmxnet3_adapter *adapter,
1099 struct sk_buff *skb,
1100 union Vmxnet3_GenericDesc *gdesc)
1101 {
1102 if (!gdesc->rcd.cnc && adapter->netdev->features & NETIF_F_RXCSUM) {
1103 /* typical case: TCP/UDP over IP and both csums are correct */
1104 if ((le32_to_cpu(gdesc->dword[3]) & VMXNET3_RCD_CSUM_OK) ==
1105 VMXNET3_RCD_CSUM_OK) {
1106 skb->ip_summed = CHECKSUM_UNNECESSARY;
1107 BUG_ON(!(gdesc->rcd.tcp || gdesc->rcd.udp));
1108 BUG_ON(!(gdesc->rcd.v4 || gdesc->rcd.v6));
1109 BUG_ON(gdesc->rcd.frg);
1110 } else {
1111 if (gdesc->rcd.csum) {
1112 skb->csum = htons(gdesc->rcd.csum);
1113 skb->ip_summed = CHECKSUM_PARTIAL;
1114 } else {
1115 skb_checksum_none_assert(skb);
1116 }
1117 }
1118 } else {
1119 skb_checksum_none_assert(skb);
1120 }
1121 }
1122
1123
1124 static void
1125 vmxnet3_rx_error(struct vmxnet3_rx_queue *rq, struct Vmxnet3_RxCompDesc *rcd,
1126 struct vmxnet3_rx_ctx *ctx, struct vmxnet3_adapter *adapter)
1127 {
1128 rq->stats.drop_err++;
1129 if (!rcd->fcs)
1130 rq->stats.drop_fcs++;
1131
1132 rq->stats.drop_total++;
1133
1134 /*
1135 * We do not unmap and chain the rx buffer to the skb.
1136 * We basically pretend this buffer is not used and will be recycled
1137 * by vmxnet3_rq_alloc_rx_buf()
1138 */
1139
1140 /*
1141 * ctx->skb may be NULL if this is the first and the only one
1142 * desc for the pkt
1143 */
1144 if (ctx->skb)
1145 dev_kfree_skb_irq(ctx->skb);
1146
1147 ctx->skb = NULL;
1148 }
1149
1150
1151 static int
1152 vmxnet3_rq_rx_complete(struct vmxnet3_rx_queue *rq,
1153 struct vmxnet3_adapter *adapter, int quota)
1154 {
1155 static const u32 rxprod_reg[2] = {
1156 VMXNET3_REG_RXPROD, VMXNET3_REG_RXPROD2
1157 };
1158 u32 num_rxd = 0;
1159 bool skip_page_frags = false;
1160 struct Vmxnet3_RxCompDesc *rcd;
1161 struct vmxnet3_rx_ctx *ctx = &rq->rx_ctx;
1162 #ifdef __BIG_ENDIAN_BITFIELD
1163 struct Vmxnet3_RxDesc rxCmdDesc;
1164 struct Vmxnet3_RxCompDesc rxComp;
1165 #endif
1166 vmxnet3_getRxComp(rcd, &rq->comp_ring.base[rq->comp_ring.next2proc].rcd,
1167 &rxComp);
1168 while (rcd->gen == rq->comp_ring.gen) {
1169 struct vmxnet3_rx_buf_info *rbi;
1170 struct sk_buff *skb, *new_skb = NULL;
1171 struct page *new_page = NULL;
1172 int num_to_alloc;
1173 struct Vmxnet3_RxDesc *rxd;
1174 u32 idx, ring_idx;
1175 struct vmxnet3_cmd_ring *ring = NULL;
1176 if (num_rxd >= quota) {
1177 /* we may stop even before we see the EOP desc of
1178 * the current pkt
1179 */
1180 break;
1181 }
1182 num_rxd++;
1183 BUG_ON(rcd->rqID != rq->qid && rcd->rqID != rq->qid2);
1184 idx = rcd->rxdIdx;
1185 ring_idx = rcd->rqID < adapter->num_rx_queues ? 0 : 1;
1186 ring = rq->rx_ring + ring_idx;
1187 vmxnet3_getRxDesc(rxd, &rq->rx_ring[ring_idx].base[idx].rxd,
1188 &rxCmdDesc);
1189 rbi = rq->buf_info[ring_idx] + idx;
1190
1191 BUG_ON(rxd->addr != rbi->dma_addr ||
1192 rxd->len != rbi->len);
1193
1194 if (unlikely(rcd->eop && rcd->err)) {
1195 vmxnet3_rx_error(rq, rcd, ctx, adapter);
1196 goto rcd_done;
1197 }
1198
1199 if (rcd->sop) { /* first buf of the pkt */
1200 BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_HEAD ||
1201 rcd->rqID != rq->qid);
1202
1203 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_SKB);
1204 BUG_ON(ctx->skb != NULL || rbi->skb == NULL);
1205
1206 if (unlikely(rcd->len == 0)) {
1207 /* Pretend the rx buffer is skipped. */
1208 BUG_ON(!(rcd->sop && rcd->eop));
1209 netdev_dbg(adapter->netdev,
1210 "rxRing[%u][%u] 0 length\n",
1211 ring_idx, idx);
1212 goto rcd_done;
1213 }
1214
1215 skip_page_frags = false;
1216 ctx->skb = rbi->skb;
1217 new_skb = netdev_alloc_skb_ip_align(adapter->netdev,
1218 rbi->len);
1219 if (new_skb == NULL) {
1220 /* Skb allocation failed, do not handover this
1221 * skb to stack. Reuse it. Drop the existing pkt
1222 */
1223 rq->stats.rx_buf_alloc_failure++;
1224 ctx->skb = NULL;
1225 rq->stats.drop_total++;
1226 skip_page_frags = true;
1227 goto rcd_done;
1228 }
1229
1230 pci_unmap_single(adapter->pdev, rbi->dma_addr, rbi->len,
1231 PCI_DMA_FROMDEVICE);
1232
1233 skb_put(ctx->skb, rcd->len);
1234
1235 /* Immediate refill */
1236 rbi->skb = new_skb;
1237 rbi->dma_addr = pci_map_single(adapter->pdev,
1238 rbi->skb->data, rbi->len,
1239 PCI_DMA_FROMDEVICE);
1240 rxd->addr = cpu_to_le64(rbi->dma_addr);
1241 rxd->len = rbi->len;
1242
1243 } else {
1244 BUG_ON(ctx->skb == NULL && !skip_page_frags);
1245
1246 /* non SOP buffer must be type 1 in most cases */
1247 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_PAGE);
1248 BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_BODY);
1249
1250 /* If an sop buffer was dropped, skip all
1251 * following non-sop fragments. They will be reused.
1252 */
1253 if (skip_page_frags)
1254 goto rcd_done;
1255
1256 new_page = alloc_page(GFP_ATOMIC);
1257 if (unlikely(new_page == NULL)) {
1258 /* Replacement page frag could not be allocated.
1259 * Reuse this page. Drop the pkt and free the
1260 * skb which contained this page as a frag. Skip
1261 * processing all the following non-sop frags.
1262 */
1263 rq->stats.rx_buf_alloc_failure++;
1264 dev_kfree_skb(ctx->skb);
1265 ctx->skb = NULL;
1266 skip_page_frags = true;
1267 goto rcd_done;
1268 }
1269
1270 if (rcd->len) {
1271 pci_unmap_page(adapter->pdev,
1272 rbi->dma_addr, rbi->len,
1273 PCI_DMA_FROMDEVICE);
1274
1275 vmxnet3_append_frag(ctx->skb, rcd, rbi);
1276 }
1277
1278 /* Immediate refill */
1279 rbi->page = new_page;
1280 rbi->dma_addr = pci_map_page(adapter->pdev, rbi->page,
1281 0, PAGE_SIZE,
1282 PCI_DMA_FROMDEVICE);
1283 rxd->addr = cpu_to_le64(rbi->dma_addr);
1284 rxd->len = rbi->len;
1285 }
1286
1287
1288 skb = ctx->skb;
1289 if (rcd->eop) {
1290 skb->len += skb->data_len;
1291
1292 vmxnet3_rx_csum(adapter, skb,
1293 (union Vmxnet3_GenericDesc *)rcd);
1294 skb->protocol = eth_type_trans(skb, adapter->netdev);
1295
1296 if (unlikely(rcd->ts))
1297 __vlan_hwaccel_put_tag(skb, rcd->tci);
1298
1299 if (adapter->netdev->features & NETIF_F_LRO)
1300 netif_receive_skb(skb);
1301 else
1302 napi_gro_receive(&rq->napi, skb);
1303
1304 ctx->skb = NULL;
1305 }
1306
1307 rcd_done:
1308 /* device may have skipped some rx descs */
1309 ring->next2comp = idx;
1310 num_to_alloc = vmxnet3_cmd_ring_desc_avail(ring);
1311 ring = rq->rx_ring + ring_idx;
1312 while (num_to_alloc) {
1313 vmxnet3_getRxDesc(rxd, &ring->base[ring->next2fill].rxd,
1314 &rxCmdDesc);
1315 BUG_ON(!rxd->addr);
1316
1317 /* Recv desc is ready to be used by the device */
1318 rxd->gen = ring->gen;
1319 vmxnet3_cmd_ring_adv_next2fill(ring);
1320 num_to_alloc--;
1321 }
1322
1323 /* if needed, update the register */
1324 if (unlikely(rq->shared->updateRxProd)) {
1325 VMXNET3_WRITE_BAR0_REG(adapter,
1326 rxprod_reg[ring_idx] + rq->qid * 8,
1327 ring->next2fill);
1328 }
1329
1330 vmxnet3_comp_ring_adv_next2proc(&rq->comp_ring);
1331 vmxnet3_getRxComp(rcd,
1332 &rq->comp_ring.base[rq->comp_ring.next2proc].rcd, &rxComp);
1333 }
1334
1335 return num_rxd;
1336 }
1337
1338
1339 static void
1340 vmxnet3_rq_cleanup(struct vmxnet3_rx_queue *rq,
1341 struct vmxnet3_adapter *adapter)
1342 {
1343 u32 i, ring_idx;
1344 struct Vmxnet3_RxDesc *rxd;
1345
1346 for (ring_idx = 0; ring_idx < 2; ring_idx++) {
1347 for (i = 0; i < rq->rx_ring[ring_idx].size; i++) {
1348 #ifdef __BIG_ENDIAN_BITFIELD
1349 struct Vmxnet3_RxDesc rxDesc;
1350 #endif
1351 vmxnet3_getRxDesc(rxd,
1352 &rq->rx_ring[ring_idx].base[i].rxd, &rxDesc);
1353
1354 if (rxd->btype == VMXNET3_RXD_BTYPE_HEAD &&
1355 rq->buf_info[ring_idx][i].skb) {
1356 pci_unmap_single(adapter->pdev, rxd->addr,
1357 rxd->len, PCI_DMA_FROMDEVICE);
1358 dev_kfree_skb(rq->buf_info[ring_idx][i].skb);
1359 rq->buf_info[ring_idx][i].skb = NULL;
1360 } else if (rxd->btype == VMXNET3_RXD_BTYPE_BODY &&
1361 rq->buf_info[ring_idx][i].page) {
1362 pci_unmap_page(adapter->pdev, rxd->addr,
1363 rxd->len, PCI_DMA_FROMDEVICE);
1364 put_page(rq->buf_info[ring_idx][i].page);
1365 rq->buf_info[ring_idx][i].page = NULL;
1366 }
1367 }
1368
1369 rq->rx_ring[ring_idx].gen = VMXNET3_INIT_GEN;
1370 rq->rx_ring[ring_idx].next2fill =
1371 rq->rx_ring[ring_idx].next2comp = 0;
1372 }
1373
1374 rq->comp_ring.gen = VMXNET3_INIT_GEN;
1375 rq->comp_ring.next2proc = 0;
1376 }
1377
1378
1379 static void
1380 vmxnet3_rq_cleanup_all(struct vmxnet3_adapter *adapter)
1381 {
1382 int i;
1383
1384 for (i = 0; i < adapter->num_rx_queues; i++)
1385 vmxnet3_rq_cleanup(&adapter->rx_queue[i], adapter);
1386 }
1387
1388
1389 void vmxnet3_rq_destroy(struct vmxnet3_rx_queue *rq,
1390 struct vmxnet3_adapter *adapter)
1391 {
1392 int i;
1393 int j;
1394
1395 /* all rx buffers must have already been freed */
1396 for (i = 0; i < 2; i++) {
1397 if (rq->buf_info[i]) {
1398 for (j = 0; j < rq->rx_ring[i].size; j++)
1399 BUG_ON(rq->buf_info[i][j].page != NULL);
1400 }
1401 }
1402
1403
1404 kfree(rq->buf_info[0]);
1405
1406 for (i = 0; i < 2; i++) {
1407 if (rq->rx_ring[i].base) {
1408 pci_free_consistent(adapter->pdev, rq->rx_ring[i].size
1409 * sizeof(struct Vmxnet3_RxDesc),
1410 rq->rx_ring[i].base,
1411 rq->rx_ring[i].basePA);
1412 rq->rx_ring[i].base = NULL;
1413 }
1414 rq->buf_info[i] = NULL;
1415 }
1416
1417 if (rq->comp_ring.base) {
1418 pci_free_consistent(adapter->pdev, rq->comp_ring.size *
1419 sizeof(struct Vmxnet3_RxCompDesc),
1420 rq->comp_ring.base, rq->comp_ring.basePA);
1421 rq->comp_ring.base = NULL;
1422 }
1423 }
1424
1425
1426 static int
1427 vmxnet3_rq_init(struct vmxnet3_rx_queue *rq,
1428 struct vmxnet3_adapter *adapter)
1429 {
1430 int i;
1431
1432 /* initialize buf_info */
1433 for (i = 0; i < rq->rx_ring[0].size; i++) {
1434
1435 /* 1st buf for a pkt is skbuff */
1436 if (i % adapter->rx_buf_per_pkt == 0) {
1437 rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_SKB;
1438 rq->buf_info[0][i].len = adapter->skb_buf_size;
1439 } else { /* subsequent bufs for a pkt is frag */
1440 rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_PAGE;
1441 rq->buf_info[0][i].len = PAGE_SIZE;
1442 }
1443 }
1444 for (i = 0; i < rq->rx_ring[1].size; i++) {
1445 rq->buf_info[1][i].buf_type = VMXNET3_RX_BUF_PAGE;
1446 rq->buf_info[1][i].len = PAGE_SIZE;
1447 }
1448
1449 /* reset internal state and allocate buffers for both rings */
1450 for (i = 0; i < 2; i++) {
1451 rq->rx_ring[i].next2fill = rq->rx_ring[i].next2comp = 0;
1452
1453 memset(rq->rx_ring[i].base, 0, rq->rx_ring[i].size *
1454 sizeof(struct Vmxnet3_RxDesc));
1455 rq->rx_ring[i].gen = VMXNET3_INIT_GEN;
1456 }
1457 if (vmxnet3_rq_alloc_rx_buf(rq, 0, rq->rx_ring[0].size - 1,
1458 adapter) == 0) {
1459 /* at least has 1 rx buffer for the 1st ring */
1460 return -ENOMEM;
1461 }
1462 vmxnet3_rq_alloc_rx_buf(rq, 1, rq->rx_ring[1].size - 1, adapter);
1463
1464 /* reset the comp ring */
1465 rq->comp_ring.next2proc = 0;
1466 memset(rq->comp_ring.base, 0, rq->comp_ring.size *
1467 sizeof(struct Vmxnet3_RxCompDesc));
1468 rq->comp_ring.gen = VMXNET3_INIT_GEN;
1469
1470 /* reset rxctx */
1471 rq->rx_ctx.skb = NULL;
1472
1473 /* stats are not reset */
1474 return 0;
1475 }
1476
1477
1478 static int
1479 vmxnet3_rq_init_all(struct vmxnet3_adapter *adapter)
1480 {
1481 int i, err = 0;
1482
1483 for (i = 0; i < adapter->num_rx_queues; i++) {
1484 err = vmxnet3_rq_init(&adapter->rx_queue[i], adapter);
1485 if (unlikely(err)) {
1486 dev_err(&adapter->netdev->dev, "%s: failed to "
1487 "initialize rx queue%i\n",
1488 adapter->netdev->name, i);
1489 break;
1490 }
1491 }
1492 return err;
1493
1494 }
1495
1496
1497 static int
1498 vmxnet3_rq_create(struct vmxnet3_rx_queue *rq, struct vmxnet3_adapter *adapter)
1499 {
1500 int i;
1501 size_t sz;
1502 struct vmxnet3_rx_buf_info *bi;
1503
1504 for (i = 0; i < 2; i++) {
1505
1506 sz = rq->rx_ring[i].size * sizeof(struct Vmxnet3_RxDesc);
1507 rq->rx_ring[i].base = pci_alloc_consistent(adapter->pdev, sz,
1508 &rq->rx_ring[i].basePA);
1509 if (!rq->rx_ring[i].base) {
1510 netdev_err(adapter->netdev,
1511 "failed to allocate rx ring %d\n", i);
1512 goto err;
1513 }
1514 }
1515
1516 sz = rq->comp_ring.size * sizeof(struct Vmxnet3_RxCompDesc);
1517 rq->comp_ring.base = pci_alloc_consistent(adapter->pdev, sz,
1518 &rq->comp_ring.basePA);
1519 if (!rq->comp_ring.base) {
1520 netdev_err(adapter->netdev, "failed to allocate rx comp ring\n");
1521 goto err;
1522 }
1523
1524 sz = sizeof(struct vmxnet3_rx_buf_info) * (rq->rx_ring[0].size +
1525 rq->rx_ring[1].size);
1526 bi = kzalloc(sz, GFP_KERNEL);
1527 if (!bi)
1528 goto err;
1529
1530 rq->buf_info[0] = bi;
1531 rq->buf_info[1] = bi + rq->rx_ring[0].size;
1532
1533 return 0;
1534
1535 err:
1536 vmxnet3_rq_destroy(rq, adapter);
1537 return -ENOMEM;
1538 }
1539
1540
1541 static int
1542 vmxnet3_rq_create_all(struct vmxnet3_adapter *adapter)
1543 {
1544 int i, err = 0;
1545
1546 for (i = 0; i < adapter->num_rx_queues; i++) {
1547 err = vmxnet3_rq_create(&adapter->rx_queue[i], adapter);
1548 if (unlikely(err)) {
1549 dev_err(&adapter->netdev->dev,
1550 "%s: failed to create rx queue%i\n",
1551 adapter->netdev->name, i);
1552 goto err_out;
1553 }
1554 }
1555 return err;
1556 err_out:
1557 vmxnet3_rq_destroy_all(adapter);
1558 return err;
1559
1560 }
1561
1562 /* Multiple queue aware polling function for tx and rx */
1563
1564 static int
1565 vmxnet3_do_poll(struct vmxnet3_adapter *adapter, int budget)
1566 {
1567 int rcd_done = 0, i;
1568 if (unlikely(adapter->shared->ecr))
1569 vmxnet3_process_events(adapter);
1570 for (i = 0; i < adapter->num_tx_queues; i++)
1571 vmxnet3_tq_tx_complete(&adapter->tx_queue[i], adapter);
1572
1573 for (i = 0; i < adapter->num_rx_queues; i++)
1574 rcd_done += vmxnet3_rq_rx_complete(&adapter->rx_queue[i],
1575 adapter, budget);
1576 return rcd_done;
1577 }
1578
1579
1580 static int
1581 vmxnet3_poll(struct napi_struct *napi, int budget)
1582 {
1583 struct vmxnet3_rx_queue *rx_queue = container_of(napi,
1584 struct vmxnet3_rx_queue, napi);
1585 int rxd_done;
1586
1587 rxd_done = vmxnet3_do_poll(rx_queue->adapter, budget);
1588
1589 if (rxd_done < budget) {
1590 napi_complete(napi);
1591 vmxnet3_enable_all_intrs(rx_queue->adapter);
1592 }
1593 return rxd_done;
1594 }
1595
1596 /*
1597 * NAPI polling function for MSI-X mode with multiple Rx queues
1598 * Returns the # of the NAPI credit consumed (# of rx descriptors processed)
1599 */
1600
1601 static int
1602 vmxnet3_poll_rx_only(struct napi_struct *napi, int budget)
1603 {
1604 struct vmxnet3_rx_queue *rq = container_of(napi,
1605 struct vmxnet3_rx_queue, napi);
1606 struct vmxnet3_adapter *adapter = rq->adapter;
1607 int rxd_done;
1608
1609 /* When sharing interrupt with corresponding tx queue, process
1610 * tx completions in that queue as well
1611 */
1612 if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE) {
1613 struct vmxnet3_tx_queue *tq =
1614 &adapter->tx_queue[rq - adapter->rx_queue];
1615 vmxnet3_tq_tx_complete(tq, adapter);
1616 }
1617
1618 rxd_done = vmxnet3_rq_rx_complete(rq, adapter, budget);
1619
1620 if (rxd_done < budget) {
1621 napi_complete(napi);
1622 vmxnet3_enable_intr(adapter, rq->comp_ring.intr_idx);
1623 }
1624 return rxd_done;
1625 }
1626
1627
1628 #ifdef CONFIG_PCI_MSI
1629
1630 /*
1631 * Handle completion interrupts on tx queues
1632 * Returns whether or not the intr is handled
1633 */
1634
1635 static irqreturn_t
1636 vmxnet3_msix_tx(int irq, void *data)
1637 {
1638 struct vmxnet3_tx_queue *tq = data;
1639 struct vmxnet3_adapter *adapter = tq->adapter;
1640
1641 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
1642 vmxnet3_disable_intr(adapter, tq->comp_ring.intr_idx);
1643
1644 /* Handle the case where only one irq is allocate for all tx queues */
1645 if (adapter->share_intr == VMXNET3_INTR_TXSHARE) {
1646 int i;
1647 for (i = 0; i < adapter->num_tx_queues; i++) {
1648 struct vmxnet3_tx_queue *txq = &adapter->tx_queue[i];
1649 vmxnet3_tq_tx_complete(txq, adapter);
1650 }
1651 } else {
1652 vmxnet3_tq_tx_complete(tq, adapter);
1653 }
1654 vmxnet3_enable_intr(adapter, tq->comp_ring.intr_idx);
1655
1656 return IRQ_HANDLED;
1657 }
1658
1659
1660 /*
1661 * Handle completion interrupts on rx queues. Returns whether or not the
1662 * intr is handled
1663 */
1664
1665 static irqreturn_t
1666 vmxnet3_msix_rx(int irq, void *data)
1667 {
1668 struct vmxnet3_rx_queue *rq = data;
1669 struct vmxnet3_adapter *adapter = rq->adapter;
1670
1671 /* disable intr if needed */
1672 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
1673 vmxnet3_disable_intr(adapter, rq->comp_ring.intr_idx);
1674 napi_schedule(&rq->napi);
1675
1676 return IRQ_HANDLED;
1677 }
1678
1679 /*
1680 *----------------------------------------------------------------------------
1681 *
1682 * vmxnet3_msix_event --
1683 *
1684 * vmxnet3 msix event intr handler
1685 *
1686 * Result:
1687 * whether or not the intr is handled
1688 *
1689 *----------------------------------------------------------------------------
1690 */
1691
1692 static irqreturn_t
1693 vmxnet3_msix_event(int irq, void *data)
1694 {
1695 struct net_device *dev = data;
1696 struct vmxnet3_adapter *adapter = netdev_priv(dev);
1697
1698 /* disable intr if needed */
1699 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
1700 vmxnet3_disable_intr(adapter, adapter->intr.event_intr_idx);
1701
1702 if (adapter->shared->ecr)
1703 vmxnet3_process_events(adapter);
1704
1705 vmxnet3_enable_intr(adapter, adapter->intr.event_intr_idx);
1706
1707 return IRQ_HANDLED;
1708 }
1709
1710 #endif /* CONFIG_PCI_MSI */
1711
1712
1713 /* Interrupt handler for vmxnet3 */
1714 static irqreturn_t
1715 vmxnet3_intr(int irq, void *dev_id)
1716 {
1717 struct net_device *dev = dev_id;
1718 struct vmxnet3_adapter *adapter = netdev_priv(dev);
1719
1720 if (adapter->intr.type == VMXNET3_IT_INTX) {
1721 u32 icr = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_ICR);
1722 if (unlikely(icr == 0))
1723 /* not ours */
1724 return IRQ_NONE;
1725 }
1726
1727
1728 /* disable intr if needed */
1729 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
1730 vmxnet3_disable_all_intrs(adapter);
1731
1732 napi_schedule(&adapter->rx_queue[0].napi);
1733
1734 return IRQ_HANDLED;
1735 }
1736
1737 #ifdef CONFIG_NET_POLL_CONTROLLER
1738
1739 /* netpoll callback. */
1740 static void
1741 vmxnet3_netpoll(struct net_device *netdev)
1742 {
1743 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
1744
1745 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
1746 vmxnet3_disable_all_intrs(adapter);
1747
1748 vmxnet3_do_poll(adapter, adapter->rx_queue[0].rx_ring[0].size);
1749 vmxnet3_enable_all_intrs(adapter);
1750
1751 }
1752 #endif /* CONFIG_NET_POLL_CONTROLLER */
1753
1754 static int
1755 vmxnet3_request_irqs(struct vmxnet3_adapter *adapter)
1756 {
1757 struct vmxnet3_intr *intr = &adapter->intr;
1758 int err = 0, i;
1759 int vector = 0;
1760
1761 #ifdef CONFIG_PCI_MSI
1762 if (adapter->intr.type == VMXNET3_IT_MSIX) {
1763 for (i = 0; i < adapter->num_tx_queues; i++) {
1764 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) {
1765 sprintf(adapter->tx_queue[i].name, "%s-tx-%d",
1766 adapter->netdev->name, vector);
1767 err = request_irq(
1768 intr->msix_entries[vector].vector,
1769 vmxnet3_msix_tx, 0,
1770 adapter->tx_queue[i].name,
1771 &adapter->tx_queue[i]);
1772 } else {
1773 sprintf(adapter->tx_queue[i].name, "%s-rxtx-%d",
1774 adapter->netdev->name, vector);
1775 }
1776 if (err) {
1777 dev_err(&adapter->netdev->dev,
1778 "Failed to request irq for MSIX, %s, "
1779 "error %d\n",
1780 adapter->tx_queue[i].name, err);
1781 return err;
1782 }
1783
1784 /* Handle the case where only 1 MSIx was allocated for
1785 * all tx queues */
1786 if (adapter->share_intr == VMXNET3_INTR_TXSHARE) {
1787 for (; i < adapter->num_tx_queues; i++)
1788 adapter->tx_queue[i].comp_ring.intr_idx
1789 = vector;
1790 vector++;
1791 break;
1792 } else {
1793 adapter->tx_queue[i].comp_ring.intr_idx
1794 = vector++;
1795 }
1796 }
1797 if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE)
1798 vector = 0;
1799
1800 for (i = 0; i < adapter->num_rx_queues; i++) {
1801 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE)
1802 sprintf(adapter->rx_queue[i].name, "%s-rx-%d",
1803 adapter->netdev->name, vector);
1804 else
1805 sprintf(adapter->rx_queue[i].name, "%s-rxtx-%d",
1806 adapter->netdev->name, vector);
1807 err = request_irq(intr->msix_entries[vector].vector,
1808 vmxnet3_msix_rx, 0,
1809 adapter->rx_queue[i].name,
1810 &(adapter->rx_queue[i]));
1811 if (err) {
1812 netdev_err(adapter->netdev,
1813 "Failed to request irq for MSIX, "
1814 "%s, error %d\n",
1815 adapter->rx_queue[i].name, err);
1816 return err;
1817 }
1818
1819 adapter->rx_queue[i].comp_ring.intr_idx = vector++;
1820 }
1821
1822 sprintf(intr->event_msi_vector_name, "%s-event-%d",
1823 adapter->netdev->name, vector);
1824 err = request_irq(intr->msix_entries[vector].vector,
1825 vmxnet3_msix_event, 0,
1826 intr->event_msi_vector_name, adapter->netdev);
1827 intr->event_intr_idx = vector;
1828
1829 } else if (intr->type == VMXNET3_IT_MSI) {
1830 adapter->num_rx_queues = 1;
1831 err = request_irq(adapter->pdev->irq, vmxnet3_intr, 0,
1832 adapter->netdev->name, adapter->netdev);
1833 } else {
1834 #endif
1835 adapter->num_rx_queues = 1;
1836 err = request_irq(adapter->pdev->irq, vmxnet3_intr,
1837 IRQF_SHARED, adapter->netdev->name,
1838 adapter->netdev);
1839 #ifdef CONFIG_PCI_MSI
1840 }
1841 #endif
1842 intr->num_intrs = vector + 1;
1843 if (err) {
1844 netdev_err(adapter->netdev,
1845 "Failed to request irq (intr type:%d), error %d\n",
1846 intr->type, err);
1847 } else {
1848 /* Number of rx queues will not change after this */
1849 for (i = 0; i < adapter->num_rx_queues; i++) {
1850 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
1851 rq->qid = i;
1852 rq->qid2 = i + adapter->num_rx_queues;
1853 }
1854
1855
1856
1857 /* init our intr settings */
1858 for (i = 0; i < intr->num_intrs; i++)
1859 intr->mod_levels[i] = UPT1_IML_ADAPTIVE;
1860 if (adapter->intr.type != VMXNET3_IT_MSIX) {
1861 adapter->intr.event_intr_idx = 0;
1862 for (i = 0; i < adapter->num_tx_queues; i++)
1863 adapter->tx_queue[i].comp_ring.intr_idx = 0;
1864 adapter->rx_queue[0].comp_ring.intr_idx = 0;
1865 }
1866
1867 netdev_info(adapter->netdev,
1868 "intr type %u, mode %u, %u vectors allocated\n",
1869 intr->type, intr->mask_mode, intr->num_intrs);
1870 }
1871
1872 return err;
1873 }
1874
1875
1876 static void
1877 vmxnet3_free_irqs(struct vmxnet3_adapter *adapter)
1878 {
1879 struct vmxnet3_intr *intr = &adapter->intr;
1880 BUG_ON(intr->type == VMXNET3_IT_AUTO || intr->num_intrs <= 0);
1881
1882 switch (intr->type) {
1883 #ifdef CONFIG_PCI_MSI
1884 case VMXNET3_IT_MSIX:
1885 {
1886 int i, vector = 0;
1887
1888 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) {
1889 for (i = 0; i < adapter->num_tx_queues; i++) {
1890 free_irq(intr->msix_entries[vector++].vector,
1891 &(adapter->tx_queue[i]));
1892 if (adapter->share_intr == VMXNET3_INTR_TXSHARE)
1893 break;
1894 }
1895 }
1896
1897 for (i = 0; i < adapter->num_rx_queues; i++) {
1898 free_irq(intr->msix_entries[vector++].vector,
1899 &(adapter->rx_queue[i]));
1900 }
1901
1902 free_irq(intr->msix_entries[vector].vector,
1903 adapter->netdev);
1904 BUG_ON(vector >= intr->num_intrs);
1905 break;
1906 }
1907 #endif
1908 case VMXNET3_IT_MSI:
1909 free_irq(adapter->pdev->irq, adapter->netdev);
1910 break;
1911 case VMXNET3_IT_INTX:
1912 free_irq(adapter->pdev->irq, adapter->netdev);
1913 break;
1914 default:
1915 BUG();
1916 }
1917 }
1918
1919
1920 static void
1921 vmxnet3_restore_vlan(struct vmxnet3_adapter *adapter)
1922 {
1923 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
1924 u16 vid;
1925
1926 /* allow untagged pkts */
1927 VMXNET3_SET_VFTABLE_ENTRY(vfTable, 0);
1928
1929 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
1930 VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid);
1931 }
1932
1933
1934 static int
1935 vmxnet3_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
1936 {
1937 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
1938
1939 if (!(netdev->flags & IFF_PROMISC)) {
1940 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
1941 unsigned long flags;
1942
1943 VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid);
1944 spin_lock_irqsave(&adapter->cmd_lock, flags);
1945 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
1946 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
1947 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
1948 }
1949
1950 set_bit(vid, adapter->active_vlans);
1951
1952 return 0;
1953 }
1954
1955
1956 static int
1957 vmxnet3_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
1958 {
1959 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
1960
1961 if (!(netdev->flags & IFF_PROMISC)) {
1962 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
1963 unsigned long flags;
1964
1965 VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid);
1966 spin_lock_irqsave(&adapter->cmd_lock, flags);
1967 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
1968 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
1969 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
1970 }
1971
1972 clear_bit(vid, adapter->active_vlans);
1973
1974 return 0;
1975 }
1976
1977
1978 static u8 *
1979 vmxnet3_copy_mc(struct net_device *netdev)
1980 {
1981 u8 *buf = NULL;
1982 u32 sz = netdev_mc_count(netdev) * ETH_ALEN;
1983
1984 /* struct Vmxnet3_RxFilterConf.mfTableLen is u16. */
1985 if (sz <= 0xffff) {
1986 /* We may be called with BH disabled */
1987 buf = kmalloc(sz, GFP_ATOMIC);
1988 if (buf) {
1989 struct netdev_hw_addr *ha;
1990 int i = 0;
1991
1992 netdev_for_each_mc_addr(ha, netdev)
1993 memcpy(buf + i++ * ETH_ALEN, ha->addr,
1994 ETH_ALEN);
1995 }
1996 }
1997 return buf;
1998 }
1999
2000
2001 static void
2002 vmxnet3_set_mc(struct net_device *netdev)
2003 {
2004 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2005 unsigned long flags;
2006 struct Vmxnet3_RxFilterConf *rxConf =
2007 &adapter->shared->devRead.rxFilterConf;
2008 u8 *new_table = NULL;
2009 u32 new_mode = VMXNET3_RXM_UCAST;
2010
2011 if (netdev->flags & IFF_PROMISC) {
2012 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
2013 memset(vfTable, 0, VMXNET3_VFT_SIZE * sizeof(*vfTable));
2014
2015 new_mode |= VMXNET3_RXM_PROMISC;
2016 } else {
2017 vmxnet3_restore_vlan(adapter);
2018 }
2019
2020 if (netdev->flags & IFF_BROADCAST)
2021 new_mode |= VMXNET3_RXM_BCAST;
2022
2023 if (netdev->flags & IFF_ALLMULTI)
2024 new_mode |= VMXNET3_RXM_ALL_MULTI;
2025 else
2026 if (!netdev_mc_empty(netdev)) {
2027 new_table = vmxnet3_copy_mc(netdev);
2028 if (new_table) {
2029 new_mode |= VMXNET3_RXM_MCAST;
2030 rxConf->mfTableLen = cpu_to_le16(
2031 netdev_mc_count(netdev) * ETH_ALEN);
2032 rxConf->mfTablePA = cpu_to_le64(virt_to_phys(
2033 new_table));
2034 } else {
2035 netdev_info(netdev, "failed to copy mcast list"
2036 ", setting ALL_MULTI\n");
2037 new_mode |= VMXNET3_RXM_ALL_MULTI;
2038 }
2039 }
2040
2041
2042 if (!(new_mode & VMXNET3_RXM_MCAST)) {
2043 rxConf->mfTableLen = 0;
2044 rxConf->mfTablePA = 0;
2045 }
2046
2047 spin_lock_irqsave(&adapter->cmd_lock, flags);
2048 if (new_mode != rxConf->rxMode) {
2049 rxConf->rxMode = cpu_to_le32(new_mode);
2050 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2051 VMXNET3_CMD_UPDATE_RX_MODE);
2052 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2053 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
2054 }
2055
2056 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2057 VMXNET3_CMD_UPDATE_MAC_FILTERS);
2058 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2059
2060 kfree(new_table);
2061 }
2062
2063 void
2064 vmxnet3_rq_destroy_all(struct vmxnet3_adapter *adapter)
2065 {
2066 int i;
2067
2068 for (i = 0; i < adapter->num_rx_queues; i++)
2069 vmxnet3_rq_destroy(&adapter->rx_queue[i], adapter);
2070 }
2071
2072
2073 /*
2074 * Set up driver_shared based on settings in adapter.
2075 */
2076
2077 static void
2078 vmxnet3_setup_driver_shared(struct vmxnet3_adapter *adapter)
2079 {
2080 struct Vmxnet3_DriverShared *shared = adapter->shared;
2081 struct Vmxnet3_DSDevRead *devRead = &shared->devRead;
2082 struct Vmxnet3_TxQueueConf *tqc;
2083 struct Vmxnet3_RxQueueConf *rqc;
2084 int i;
2085
2086 memset(shared, 0, sizeof(*shared));
2087
2088 /* driver settings */
2089 shared->magic = cpu_to_le32(VMXNET3_REV1_MAGIC);
2090 devRead->misc.driverInfo.version = cpu_to_le32(
2091 VMXNET3_DRIVER_VERSION_NUM);
2092 devRead->misc.driverInfo.gos.gosBits = (sizeof(void *) == 4 ?
2093 VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64);
2094 devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX;
2095 *((u32 *)&devRead->misc.driverInfo.gos) = cpu_to_le32(
2096 *((u32 *)&devRead->misc.driverInfo.gos));
2097 devRead->misc.driverInfo.vmxnet3RevSpt = cpu_to_le32(1);
2098 devRead->misc.driverInfo.uptVerSpt = cpu_to_le32(1);
2099
2100 devRead->misc.ddPA = cpu_to_le64(virt_to_phys(adapter));
2101 devRead->misc.ddLen = cpu_to_le32(sizeof(struct vmxnet3_adapter));
2102
2103 /* set up feature flags */
2104 if (adapter->netdev->features & NETIF_F_RXCSUM)
2105 devRead->misc.uptFeatures |= UPT1_F_RXCSUM;
2106
2107 if (adapter->netdev->features & NETIF_F_LRO) {
2108 devRead->misc.uptFeatures |= UPT1_F_LRO;
2109 devRead->misc.maxNumRxSG = cpu_to_le16(1 + MAX_SKB_FRAGS);
2110 }
2111 if (adapter->netdev->features & NETIF_F_HW_VLAN_RX)
2112 devRead->misc.uptFeatures |= UPT1_F_RXVLAN;
2113
2114 devRead->misc.mtu = cpu_to_le32(adapter->netdev->mtu);
2115 devRead->misc.queueDescPA = cpu_to_le64(adapter->queue_desc_pa);
2116 devRead->misc.queueDescLen = cpu_to_le32(
2117 adapter->num_tx_queues * sizeof(struct Vmxnet3_TxQueueDesc) +
2118 adapter->num_rx_queues * sizeof(struct Vmxnet3_RxQueueDesc));
2119
2120 /* tx queue settings */
2121 devRead->misc.numTxQueues = adapter->num_tx_queues;
2122 for (i = 0; i < adapter->num_tx_queues; i++) {
2123 struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i];
2124 BUG_ON(adapter->tx_queue[i].tx_ring.base == NULL);
2125 tqc = &adapter->tqd_start[i].conf;
2126 tqc->txRingBasePA = cpu_to_le64(tq->tx_ring.basePA);
2127 tqc->dataRingBasePA = cpu_to_le64(tq->data_ring.basePA);
2128 tqc->compRingBasePA = cpu_to_le64(tq->comp_ring.basePA);
2129 tqc->ddPA = cpu_to_le64(virt_to_phys(tq->buf_info));
2130 tqc->txRingSize = cpu_to_le32(tq->tx_ring.size);
2131 tqc->dataRingSize = cpu_to_le32(tq->data_ring.size);
2132 tqc->compRingSize = cpu_to_le32(tq->comp_ring.size);
2133 tqc->ddLen = cpu_to_le32(
2134 sizeof(struct vmxnet3_tx_buf_info) *
2135 tqc->txRingSize);
2136 tqc->intrIdx = tq->comp_ring.intr_idx;
2137 }
2138
2139 /* rx queue settings */
2140 devRead->misc.numRxQueues = adapter->num_rx_queues;
2141 for (i = 0; i < adapter->num_rx_queues; i++) {
2142 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
2143 rqc = &adapter->rqd_start[i].conf;
2144 rqc->rxRingBasePA[0] = cpu_to_le64(rq->rx_ring[0].basePA);
2145 rqc->rxRingBasePA[1] = cpu_to_le64(rq->rx_ring[1].basePA);
2146 rqc->compRingBasePA = cpu_to_le64(rq->comp_ring.basePA);
2147 rqc->ddPA = cpu_to_le64(virt_to_phys(
2148 rq->buf_info));
2149 rqc->rxRingSize[0] = cpu_to_le32(rq->rx_ring[0].size);
2150 rqc->rxRingSize[1] = cpu_to_le32(rq->rx_ring[1].size);
2151 rqc->compRingSize = cpu_to_le32(rq->comp_ring.size);
2152 rqc->ddLen = cpu_to_le32(
2153 sizeof(struct vmxnet3_rx_buf_info) *
2154 (rqc->rxRingSize[0] +
2155 rqc->rxRingSize[1]));
2156 rqc->intrIdx = rq->comp_ring.intr_idx;
2157 }
2158
2159 #ifdef VMXNET3_RSS
2160 memset(adapter->rss_conf, 0, sizeof(*adapter->rss_conf));
2161
2162 if (adapter->rss) {
2163 struct UPT1_RSSConf *rssConf = adapter->rss_conf;
2164 devRead->misc.uptFeatures |= UPT1_F_RSS;
2165 devRead->misc.numRxQueues = adapter->num_rx_queues;
2166 rssConf->hashType = UPT1_RSS_HASH_TYPE_TCP_IPV4 |
2167 UPT1_RSS_HASH_TYPE_IPV4 |
2168 UPT1_RSS_HASH_TYPE_TCP_IPV6 |
2169 UPT1_RSS_HASH_TYPE_IPV6;
2170 rssConf->hashFunc = UPT1_RSS_HASH_FUNC_TOEPLITZ;
2171 rssConf->hashKeySize = UPT1_RSS_MAX_KEY_SIZE;
2172 rssConf->indTableSize = VMXNET3_RSS_IND_TABLE_SIZE;
2173 get_random_bytes(&rssConf->hashKey[0], rssConf->hashKeySize);
2174 for (i = 0; i < rssConf->indTableSize; i++)
2175 rssConf->indTable[i] = ethtool_rxfh_indir_default(
2176 i, adapter->num_rx_queues);
2177
2178 devRead->rssConfDesc.confVer = 1;
2179 devRead->rssConfDesc.confLen = sizeof(*rssConf);
2180 devRead->rssConfDesc.confPA = virt_to_phys(rssConf);
2181 }
2182
2183 #endif /* VMXNET3_RSS */
2184
2185 /* intr settings */
2186 devRead->intrConf.autoMask = adapter->intr.mask_mode ==
2187 VMXNET3_IMM_AUTO;
2188 devRead->intrConf.numIntrs = adapter->intr.num_intrs;
2189 for (i = 0; i < adapter->intr.num_intrs; i++)
2190 devRead->intrConf.modLevels[i] = adapter->intr.mod_levels[i];
2191
2192 devRead->intrConf.eventIntrIdx = adapter->intr.event_intr_idx;
2193 devRead->intrConf.intrCtrl |= cpu_to_le32(VMXNET3_IC_DISABLE_ALL);
2194
2195 /* rx filter settings */
2196 devRead->rxFilterConf.rxMode = 0;
2197 vmxnet3_restore_vlan(adapter);
2198 vmxnet3_write_mac_addr(adapter, adapter->netdev->dev_addr);
2199
2200 /* the rest are already zeroed */
2201 }
2202
2203
2204 int
2205 vmxnet3_activate_dev(struct vmxnet3_adapter *adapter)
2206 {
2207 int err, i;
2208 u32 ret;
2209 unsigned long flags;
2210
2211 netdev_dbg(adapter->netdev, "%s: skb_buf_size %d, rx_buf_per_pkt %d,"
2212 " ring sizes %u %u %u\n", adapter->netdev->name,
2213 adapter->skb_buf_size, adapter->rx_buf_per_pkt,
2214 adapter->tx_queue[0].tx_ring.size,
2215 adapter->rx_queue[0].rx_ring[0].size,
2216 adapter->rx_queue[0].rx_ring[1].size);
2217
2218 vmxnet3_tq_init_all(adapter);
2219 err = vmxnet3_rq_init_all(adapter);
2220 if (err) {
2221 netdev_err(adapter->netdev,
2222 "Failed to init rx queue error %d\n", err);
2223 goto rq_err;
2224 }
2225
2226 err = vmxnet3_request_irqs(adapter);
2227 if (err) {
2228 netdev_err(adapter->netdev,
2229 "Failed to setup irq for error %d\n", err);
2230 goto irq_err;
2231 }
2232
2233 vmxnet3_setup_driver_shared(adapter);
2234
2235 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, VMXNET3_GET_ADDR_LO(
2236 adapter->shared_pa));
2237 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, VMXNET3_GET_ADDR_HI(
2238 adapter->shared_pa));
2239 spin_lock_irqsave(&adapter->cmd_lock, flags);
2240 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2241 VMXNET3_CMD_ACTIVATE_DEV);
2242 ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
2243 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2244
2245 if (ret != 0) {
2246 netdev_err(adapter->netdev,
2247 "Failed to activate dev: error %u\n", ret);
2248 err = -EINVAL;
2249 goto activate_err;
2250 }
2251
2252 for (i = 0; i < adapter->num_rx_queues; i++) {
2253 VMXNET3_WRITE_BAR0_REG(adapter,
2254 VMXNET3_REG_RXPROD + i * VMXNET3_REG_ALIGN,
2255 adapter->rx_queue[i].rx_ring[0].next2fill);
2256 VMXNET3_WRITE_BAR0_REG(adapter, (VMXNET3_REG_RXPROD2 +
2257 (i * VMXNET3_REG_ALIGN)),
2258 adapter->rx_queue[i].rx_ring[1].next2fill);
2259 }
2260
2261 /* Apply the rx filter settins last. */
2262 vmxnet3_set_mc(adapter->netdev);
2263
2264 /*
2265 * Check link state when first activating device. It will start the
2266 * tx queue if the link is up.
2267 */
2268 vmxnet3_check_link(adapter, true);
2269 for (i = 0; i < adapter->num_rx_queues; i++)
2270 napi_enable(&adapter->rx_queue[i].napi);
2271 vmxnet3_enable_all_intrs(adapter);
2272 clear_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state);
2273 return 0;
2274
2275 activate_err:
2276 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, 0);
2277 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, 0);
2278 vmxnet3_free_irqs(adapter);
2279 irq_err:
2280 rq_err:
2281 /* free up buffers we allocated */
2282 vmxnet3_rq_cleanup_all(adapter);
2283 return err;
2284 }
2285
2286
2287 void
2288 vmxnet3_reset_dev(struct vmxnet3_adapter *adapter)
2289 {
2290 unsigned long flags;
2291 spin_lock_irqsave(&adapter->cmd_lock, flags);
2292 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV);
2293 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2294 }
2295
2296
2297 int
2298 vmxnet3_quiesce_dev(struct vmxnet3_adapter *adapter)
2299 {
2300 int i;
2301 unsigned long flags;
2302 if (test_and_set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state))
2303 return 0;
2304
2305
2306 spin_lock_irqsave(&adapter->cmd_lock, flags);
2307 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2308 VMXNET3_CMD_QUIESCE_DEV);
2309 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2310 vmxnet3_disable_all_intrs(adapter);
2311
2312 for (i = 0; i < adapter->num_rx_queues; i++)
2313 napi_disable(&adapter->rx_queue[i].napi);
2314 netif_tx_disable(adapter->netdev);
2315 adapter->link_speed = 0;
2316 netif_carrier_off(adapter->netdev);
2317
2318 vmxnet3_tq_cleanup_all(adapter);
2319 vmxnet3_rq_cleanup_all(adapter);
2320 vmxnet3_free_irqs(adapter);
2321 return 0;
2322 }
2323
2324
2325 static void
2326 vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac)
2327 {
2328 u32 tmp;
2329
2330 tmp = *(u32 *)mac;
2331 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACL, tmp);
2332
2333 tmp = (mac[5] << 8) | mac[4];
2334 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACH, tmp);
2335 }
2336
2337
2338 static int
2339 vmxnet3_set_mac_addr(struct net_device *netdev, void *p)
2340 {
2341 struct sockaddr *addr = p;
2342 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2343
2344 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2345 vmxnet3_write_mac_addr(adapter, addr->sa_data);
2346
2347 return 0;
2348 }
2349
2350
2351 /* ==================== initialization and cleanup routines ============ */
2352
2353 static int
2354 vmxnet3_alloc_pci_resources(struct vmxnet3_adapter *adapter, bool *dma64)
2355 {
2356 int err;
2357 unsigned long mmio_start, mmio_len;
2358 struct pci_dev *pdev = adapter->pdev;
2359
2360 err = pci_enable_device(pdev);
2361 if (err) {
2362 dev_err(&pdev->dev, "Failed to enable adapter: error %d\n", err);
2363 return err;
2364 }
2365
2366 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) == 0) {
2367 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) {
2368 dev_err(&pdev->dev,
2369 "pci_set_consistent_dma_mask failed\n");
2370 err = -EIO;
2371 goto err_set_mask;
2372 }
2373 *dma64 = true;
2374 } else {
2375 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) {
2376 dev_err(&pdev->dev,
2377 "pci_set_dma_mask failed\n");
2378 err = -EIO;
2379 goto err_set_mask;
2380 }
2381 *dma64 = false;
2382 }
2383
2384 err = pci_request_selected_regions(pdev, (1 << 2) - 1,
2385 vmxnet3_driver_name);
2386 if (err) {
2387 dev_err(&pdev->dev,
2388 "Failed to request region for adapter: error %d\n", err);
2389 goto err_set_mask;
2390 }
2391
2392 pci_set_master(pdev);
2393
2394 mmio_start = pci_resource_start(pdev, 0);
2395 mmio_len = pci_resource_len(pdev, 0);
2396 adapter->hw_addr0 = ioremap(mmio_start, mmio_len);
2397 if (!adapter->hw_addr0) {
2398 dev_err(&pdev->dev, "Failed to map bar0\n");
2399 err = -EIO;
2400 goto err_ioremap;
2401 }
2402
2403 mmio_start = pci_resource_start(pdev, 1);
2404 mmio_len = pci_resource_len(pdev, 1);
2405 adapter->hw_addr1 = ioremap(mmio_start, mmio_len);
2406 if (!adapter->hw_addr1) {
2407 dev_err(&pdev->dev, "Failed to map bar1\n");
2408 err = -EIO;
2409 goto err_bar1;
2410 }
2411 return 0;
2412
2413 err_bar1:
2414 iounmap(adapter->hw_addr0);
2415 err_ioremap:
2416 pci_release_selected_regions(pdev, (1 << 2) - 1);
2417 err_set_mask:
2418 pci_disable_device(pdev);
2419 return err;
2420 }
2421
2422
2423 static void
2424 vmxnet3_free_pci_resources(struct vmxnet3_adapter *adapter)
2425 {
2426 BUG_ON(!adapter->pdev);
2427
2428 iounmap(adapter->hw_addr0);
2429 iounmap(adapter->hw_addr1);
2430 pci_release_selected_regions(adapter->pdev, (1 << 2) - 1);
2431 pci_disable_device(adapter->pdev);
2432 }
2433
2434
2435 static void
2436 vmxnet3_adjust_rx_ring_size(struct vmxnet3_adapter *adapter)
2437 {
2438 size_t sz, i, ring0_size, ring1_size, comp_size;
2439 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[0];
2440
2441
2442 if (adapter->netdev->mtu <= VMXNET3_MAX_SKB_BUF_SIZE -
2443 VMXNET3_MAX_ETH_HDR_SIZE) {
2444 adapter->skb_buf_size = adapter->netdev->mtu +
2445 VMXNET3_MAX_ETH_HDR_SIZE;
2446 if (adapter->skb_buf_size < VMXNET3_MIN_T0_BUF_SIZE)
2447 adapter->skb_buf_size = VMXNET3_MIN_T0_BUF_SIZE;
2448
2449 adapter->rx_buf_per_pkt = 1;
2450 } else {
2451 adapter->skb_buf_size = VMXNET3_MAX_SKB_BUF_SIZE;
2452 sz = adapter->netdev->mtu - VMXNET3_MAX_SKB_BUF_SIZE +
2453 VMXNET3_MAX_ETH_HDR_SIZE;
2454 adapter->rx_buf_per_pkt = 1 + (sz + PAGE_SIZE - 1) / PAGE_SIZE;
2455 }
2456
2457 /*
2458 * for simplicity, force the ring0 size to be a multiple of
2459 * rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN
2460 */
2461 sz = adapter->rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN;
2462 ring0_size = adapter->rx_queue[0].rx_ring[0].size;
2463 ring0_size = (ring0_size + sz - 1) / sz * sz;
2464 ring0_size = min_t(u32, ring0_size, VMXNET3_RX_RING_MAX_SIZE /
2465 sz * sz);
2466 ring1_size = adapter->rx_queue[0].rx_ring[1].size;
2467 comp_size = ring0_size + ring1_size;
2468
2469 for (i = 0; i < adapter->num_rx_queues; i++) {
2470 rq = &adapter->rx_queue[i];
2471 rq->rx_ring[0].size = ring0_size;
2472 rq->rx_ring[1].size = ring1_size;
2473 rq->comp_ring.size = comp_size;
2474 }
2475 }
2476
2477
2478 int
2479 vmxnet3_create_queues(struct vmxnet3_adapter *adapter, u32 tx_ring_size,
2480 u32 rx_ring_size, u32 rx_ring2_size)
2481 {
2482 int err = 0, i;
2483
2484 for (i = 0; i < adapter->num_tx_queues; i++) {
2485 struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i];
2486 tq->tx_ring.size = tx_ring_size;
2487 tq->data_ring.size = tx_ring_size;
2488 tq->comp_ring.size = tx_ring_size;
2489 tq->shared = &adapter->tqd_start[i].ctrl;
2490 tq->stopped = true;
2491 tq->adapter = adapter;
2492 tq->qid = i;
2493 err = vmxnet3_tq_create(tq, adapter);
2494 /*
2495 * Too late to change num_tx_queues. We cannot do away with
2496 * lesser number of queues than what we asked for
2497 */
2498 if (err)
2499 goto queue_err;
2500 }
2501
2502 adapter->rx_queue[0].rx_ring[0].size = rx_ring_size;
2503 adapter->rx_queue[0].rx_ring[1].size = rx_ring2_size;
2504 vmxnet3_adjust_rx_ring_size(adapter);
2505 for (i = 0; i < adapter->num_rx_queues; i++) {
2506 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
2507 /* qid and qid2 for rx queues will be assigned later when num
2508 * of rx queues is finalized after allocating intrs */
2509 rq->shared = &adapter->rqd_start[i].ctrl;
2510 rq->adapter = adapter;
2511 err = vmxnet3_rq_create(rq, adapter);
2512 if (err) {
2513 if (i == 0) {
2514 netdev_err(adapter->netdev,
2515 "Could not allocate any rx queues. "
2516 "Aborting.\n");
2517 goto queue_err;
2518 } else {
2519 netdev_info(adapter->netdev,
2520 "Number of rx queues changed "
2521 "to : %d.\n", i);
2522 adapter->num_rx_queues = i;
2523 err = 0;
2524 break;
2525 }
2526 }
2527 }
2528 return err;
2529 queue_err:
2530 vmxnet3_tq_destroy_all(adapter);
2531 return err;
2532 }
2533
2534 static int
2535 vmxnet3_open(struct net_device *netdev)
2536 {
2537 struct vmxnet3_adapter *adapter;
2538 int err, i;
2539
2540 adapter = netdev_priv(netdev);
2541
2542 for (i = 0; i < adapter->num_tx_queues; i++)
2543 spin_lock_init(&adapter->tx_queue[i].tx_lock);
2544
2545 err = vmxnet3_create_queues(adapter, VMXNET3_DEF_TX_RING_SIZE,
2546 VMXNET3_DEF_RX_RING_SIZE,
2547 VMXNET3_DEF_RX_RING_SIZE);
2548 if (err)
2549 goto queue_err;
2550
2551 err = vmxnet3_activate_dev(adapter);
2552 if (err)
2553 goto activate_err;
2554
2555 return 0;
2556
2557 activate_err:
2558 vmxnet3_rq_destroy_all(adapter);
2559 vmxnet3_tq_destroy_all(adapter);
2560 queue_err:
2561 return err;
2562 }
2563
2564
2565 static int
2566 vmxnet3_close(struct net_device *netdev)
2567 {
2568 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2569
2570 /*
2571 * Reset_work may be in the middle of resetting the device, wait for its
2572 * completion.
2573 */
2574 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
2575 msleep(1);
2576
2577 vmxnet3_quiesce_dev(adapter);
2578
2579 vmxnet3_rq_destroy_all(adapter);
2580 vmxnet3_tq_destroy_all(adapter);
2581
2582 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
2583
2584
2585 return 0;
2586 }
2587
2588
2589 void
2590 vmxnet3_force_close(struct vmxnet3_adapter *adapter)
2591 {
2592 int i;
2593
2594 /*
2595 * we must clear VMXNET3_STATE_BIT_RESETTING, otherwise
2596 * vmxnet3_close() will deadlock.
2597 */
2598 BUG_ON(test_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state));
2599
2600 /* we need to enable NAPI, otherwise dev_close will deadlock */
2601 for (i = 0; i < adapter->num_rx_queues; i++)
2602 napi_enable(&adapter->rx_queue[i].napi);
2603 dev_close(adapter->netdev);
2604 }
2605
2606
2607 static int
2608 vmxnet3_change_mtu(struct net_device *netdev, int new_mtu)
2609 {
2610 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2611 int err = 0;
2612
2613 if (new_mtu < VMXNET3_MIN_MTU || new_mtu > VMXNET3_MAX_MTU)
2614 return -EINVAL;
2615
2616 netdev->mtu = new_mtu;
2617
2618 /*
2619 * Reset_work may be in the middle of resetting the device, wait for its
2620 * completion.
2621 */
2622 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
2623 msleep(1);
2624
2625 if (netif_running(netdev)) {
2626 vmxnet3_quiesce_dev(adapter);
2627 vmxnet3_reset_dev(adapter);
2628
2629 /* we need to re-create the rx queue based on the new mtu */
2630 vmxnet3_rq_destroy_all(adapter);
2631 vmxnet3_adjust_rx_ring_size(adapter);
2632 err = vmxnet3_rq_create_all(adapter);
2633 if (err) {
2634 netdev_err(netdev,
2635 "failed to re-create rx queues, "
2636 " error %d. Closing it.\n", err);
2637 goto out;
2638 }
2639
2640 err = vmxnet3_activate_dev(adapter);
2641 if (err) {
2642 netdev_err(netdev,
2643 "failed to re-activate, error %d. "
2644 "Closing it\n", err);
2645 goto out;
2646 }
2647 }
2648
2649 out:
2650 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
2651 if (err)
2652 vmxnet3_force_close(adapter);
2653
2654 return err;
2655 }
2656
2657
2658 static void
2659 vmxnet3_declare_features(struct vmxnet3_adapter *adapter, bool dma64)
2660 {
2661 struct net_device *netdev = adapter->netdev;
2662
2663 netdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM |
2664 NETIF_F_HW_CSUM | NETIF_F_HW_VLAN_TX |
2665 NETIF_F_HW_VLAN_RX | NETIF_F_TSO | NETIF_F_TSO6 |
2666 NETIF_F_LRO;
2667 if (dma64)
2668 netdev->hw_features |= NETIF_F_HIGHDMA;
2669 netdev->vlan_features = netdev->hw_features &
2670 ~(NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX);
2671 netdev->features = netdev->hw_features | NETIF_F_HW_VLAN_FILTER;
2672 }
2673
2674
2675 static void
2676 vmxnet3_read_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac)
2677 {
2678 u32 tmp;
2679
2680 tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACL);
2681 *(u32 *)mac = tmp;
2682
2683 tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACH);
2684 mac[4] = tmp & 0xff;
2685 mac[5] = (tmp >> 8) & 0xff;
2686 }
2687
2688 #ifdef CONFIG_PCI_MSI
2689
2690 /*
2691 * Enable MSIx vectors.
2692 * Returns :
2693 * 0 on successful enabling of required vectors,
2694 * VMXNET3_LINUX_MIN_MSIX_VECT when only minimum number of vectors required
2695 * could be enabled.
2696 * number of vectors which can be enabled otherwise (this number is smaller
2697 * than VMXNET3_LINUX_MIN_MSIX_VECT)
2698 */
2699
2700 static int
2701 vmxnet3_acquire_msix_vectors(struct vmxnet3_adapter *adapter,
2702 int vectors)
2703 {
2704 int err = 0, vector_threshold;
2705 vector_threshold = VMXNET3_LINUX_MIN_MSIX_VECT;
2706
2707 while (vectors >= vector_threshold) {
2708 err = pci_enable_msix(adapter->pdev, adapter->intr.msix_entries,
2709 vectors);
2710 if (!err) {
2711 adapter->intr.num_intrs = vectors;
2712 return 0;
2713 } else if (err < 0) {
2714 dev_err(&adapter->netdev->dev,
2715 "Failed to enable MSI-X, error: %d\n", err);
2716 vectors = 0;
2717 } else if (err < vector_threshold) {
2718 break;
2719 } else {
2720 /* If fails to enable required number of MSI-x vectors
2721 * try enabling minimum number of vectors required.
2722 */
2723 dev_err(&adapter->netdev->dev,
2724 "Failed to enable %d MSI-X, trying %d instead\n",
2725 vectors, vector_threshold);
2726 vectors = vector_threshold;
2727 }
2728 }
2729
2730 dev_info(&adapter->pdev->dev,
2731 "Number of MSI-X interrupts which can be allocated "
2732 "is lower than min threshold required.\n");
2733 return err;
2734 }
2735
2736
2737 #endif /* CONFIG_PCI_MSI */
2738
2739 static void
2740 vmxnet3_alloc_intr_resources(struct vmxnet3_adapter *adapter)
2741 {
2742 u32 cfg;
2743 unsigned long flags;
2744
2745 /* intr settings */
2746 spin_lock_irqsave(&adapter->cmd_lock, flags);
2747 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2748 VMXNET3_CMD_GET_CONF_INTR);
2749 cfg = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
2750 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2751 adapter->intr.type = cfg & 0x3;
2752 adapter->intr.mask_mode = (cfg >> 2) & 0x3;
2753
2754 if (adapter->intr.type == VMXNET3_IT_AUTO) {
2755 adapter->intr.type = VMXNET3_IT_MSIX;
2756 }
2757
2758 #ifdef CONFIG_PCI_MSI
2759 if (adapter->intr.type == VMXNET3_IT_MSIX) {
2760 int vector, err = 0;
2761
2762 adapter->intr.num_intrs = (adapter->share_intr ==
2763 VMXNET3_INTR_TXSHARE) ? 1 :
2764 adapter->num_tx_queues;
2765 adapter->intr.num_intrs += (adapter->share_intr ==
2766 VMXNET3_INTR_BUDDYSHARE) ? 0 :
2767 adapter->num_rx_queues;
2768 adapter->intr.num_intrs += 1; /* for link event */
2769
2770 adapter->intr.num_intrs = (adapter->intr.num_intrs >
2771 VMXNET3_LINUX_MIN_MSIX_VECT
2772 ? adapter->intr.num_intrs :
2773 VMXNET3_LINUX_MIN_MSIX_VECT);
2774
2775 for (vector = 0; vector < adapter->intr.num_intrs; vector++)
2776 adapter->intr.msix_entries[vector].entry = vector;
2777
2778 err = vmxnet3_acquire_msix_vectors(adapter,
2779 adapter->intr.num_intrs);
2780 /* If we cannot allocate one MSIx vector per queue
2781 * then limit the number of rx queues to 1
2782 */
2783 if (err == VMXNET3_LINUX_MIN_MSIX_VECT) {
2784 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE
2785 || adapter->num_rx_queues != 1) {
2786 adapter->share_intr = VMXNET3_INTR_TXSHARE;
2787 netdev_err(adapter->netdev,
2788 "Number of rx queues : 1\n");
2789 adapter->num_rx_queues = 1;
2790 adapter->intr.num_intrs =
2791 VMXNET3_LINUX_MIN_MSIX_VECT;
2792 }
2793 return;
2794 }
2795 if (!err)
2796 return;
2797
2798 /* If we cannot allocate MSIx vectors use only one rx queue */
2799 dev_info(&adapter->pdev->dev,
2800 "Failed to enable MSI-X, error %d. "
2801 "Limiting #rx queues to 1, try MSI.\n", err);
2802
2803 adapter->intr.type = VMXNET3_IT_MSI;
2804 }
2805
2806 if (adapter->intr.type == VMXNET3_IT_MSI) {
2807 int err;
2808 err = pci_enable_msi(adapter->pdev);
2809 if (!err) {
2810 adapter->num_rx_queues = 1;
2811 adapter->intr.num_intrs = 1;
2812 return;
2813 }
2814 }
2815 #endif /* CONFIG_PCI_MSI */
2816
2817 adapter->num_rx_queues = 1;
2818 dev_info(&adapter->netdev->dev,
2819 "Using INTx interrupt, #Rx queues: 1.\n");
2820 adapter->intr.type = VMXNET3_IT_INTX;
2821
2822 /* INT-X related setting */
2823 adapter->intr.num_intrs = 1;
2824 }
2825
2826
2827 static void
2828 vmxnet3_free_intr_resources(struct vmxnet3_adapter *adapter)
2829 {
2830 if (adapter->intr.type == VMXNET3_IT_MSIX)
2831 pci_disable_msix(adapter->pdev);
2832 else if (adapter->intr.type == VMXNET3_IT_MSI)
2833 pci_disable_msi(adapter->pdev);
2834 else
2835 BUG_ON(adapter->intr.type != VMXNET3_IT_INTX);
2836 }
2837
2838
2839 static void
2840 vmxnet3_tx_timeout(struct net_device *netdev)
2841 {
2842 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2843 adapter->tx_timeout_count++;
2844
2845 netdev_err(adapter->netdev, "tx hang\n");
2846 schedule_work(&adapter->work);
2847 netif_wake_queue(adapter->netdev);
2848 }
2849
2850
2851 static void
2852 vmxnet3_reset_work(struct work_struct *data)
2853 {
2854 struct vmxnet3_adapter *adapter;
2855
2856 adapter = container_of(data, struct vmxnet3_adapter, work);
2857
2858 /* if another thread is resetting the device, no need to proceed */
2859 if (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
2860 return;
2861
2862 /* if the device is closed, we must leave it alone */
2863 rtnl_lock();
2864 if (netif_running(adapter->netdev)) {
2865 netdev_notice(adapter->netdev, "resetting\n");
2866 vmxnet3_quiesce_dev(adapter);
2867 vmxnet3_reset_dev(adapter);
2868 vmxnet3_activate_dev(adapter);
2869 } else {
2870 netdev_info(adapter->netdev, "already closed\n");
2871 }
2872 rtnl_unlock();
2873
2874 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
2875 }
2876
2877
2878 static int
2879 vmxnet3_probe_device(struct pci_dev *pdev,
2880 const struct pci_device_id *id)
2881 {
2882 static const struct net_device_ops vmxnet3_netdev_ops = {
2883 .ndo_open = vmxnet3_open,
2884 .ndo_stop = vmxnet3_close,
2885 .ndo_start_xmit = vmxnet3_xmit_frame,
2886 .ndo_set_mac_address = vmxnet3_set_mac_addr,
2887 .ndo_change_mtu = vmxnet3_change_mtu,
2888 .ndo_set_features = vmxnet3_set_features,
2889 .ndo_get_stats64 = vmxnet3_get_stats64,
2890 .ndo_tx_timeout = vmxnet3_tx_timeout,
2891 .ndo_set_rx_mode = vmxnet3_set_mc,
2892 .ndo_vlan_rx_add_vid = vmxnet3_vlan_rx_add_vid,
2893 .ndo_vlan_rx_kill_vid = vmxnet3_vlan_rx_kill_vid,
2894 #ifdef CONFIG_NET_POLL_CONTROLLER
2895 .ndo_poll_controller = vmxnet3_netpoll,
2896 #endif
2897 };
2898 int err;
2899 bool dma64 = false; /* stupid gcc */
2900 u32 ver;
2901 struct net_device *netdev;
2902 struct vmxnet3_adapter *adapter;
2903 u8 mac[ETH_ALEN];
2904 int size;
2905 int num_tx_queues;
2906 int num_rx_queues;
2907
2908 if (!pci_msi_enabled())
2909 enable_mq = 0;
2910
2911 #ifdef VMXNET3_RSS
2912 if (enable_mq)
2913 num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES,
2914 (int)num_online_cpus());
2915 else
2916 #endif
2917 num_rx_queues = 1;
2918 num_rx_queues = rounddown_pow_of_two(num_rx_queues);
2919
2920 if (enable_mq)
2921 num_tx_queues = min(VMXNET3_DEVICE_MAX_TX_QUEUES,
2922 (int)num_online_cpus());
2923 else
2924 num_tx_queues = 1;
2925
2926 num_tx_queues = rounddown_pow_of_two(num_tx_queues);
2927 netdev = alloc_etherdev_mq(sizeof(struct vmxnet3_adapter),
2928 max(num_tx_queues, num_rx_queues));
2929 dev_info(&pdev->dev,
2930 "# of Tx queues : %d, # of Rx queues : %d\n",
2931 num_tx_queues, num_rx_queues);
2932
2933 if (!netdev)
2934 return -ENOMEM;
2935
2936 pci_set_drvdata(pdev, netdev);
2937 adapter = netdev_priv(netdev);
2938 adapter->netdev = netdev;
2939 adapter->pdev = pdev;
2940
2941 spin_lock_init(&adapter->cmd_lock);
2942 adapter->shared = pci_alloc_consistent(adapter->pdev,
2943 sizeof(struct Vmxnet3_DriverShared),
2944 &adapter->shared_pa);
2945 if (!adapter->shared) {
2946 dev_err(&pdev->dev, "Failed to allocate memory\n");
2947 err = -ENOMEM;
2948 goto err_alloc_shared;
2949 }
2950
2951 adapter->num_rx_queues = num_rx_queues;
2952 adapter->num_tx_queues = num_tx_queues;
2953
2954 size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues;
2955 size += sizeof(struct Vmxnet3_RxQueueDesc) * adapter->num_rx_queues;
2956 adapter->tqd_start = pci_alloc_consistent(adapter->pdev, size,
2957 &adapter->queue_desc_pa);
2958
2959 if (!adapter->tqd_start) {
2960 dev_err(&pdev->dev, "Failed to allocate memory\n");
2961 err = -ENOMEM;
2962 goto err_alloc_queue_desc;
2963 }
2964 adapter->rqd_start = (struct Vmxnet3_RxQueueDesc *)(adapter->tqd_start +
2965 adapter->num_tx_queues);
2966
2967 adapter->pm_conf = kmalloc(sizeof(struct Vmxnet3_PMConf), GFP_KERNEL);
2968 if (adapter->pm_conf == NULL) {
2969 err = -ENOMEM;
2970 goto err_alloc_pm;
2971 }
2972
2973 #ifdef VMXNET3_RSS
2974
2975 adapter->rss_conf = kmalloc(sizeof(struct UPT1_RSSConf), GFP_KERNEL);
2976 if (adapter->rss_conf == NULL) {
2977 err = -ENOMEM;
2978 goto err_alloc_rss;
2979 }
2980 #endif /* VMXNET3_RSS */
2981
2982 err = vmxnet3_alloc_pci_resources(adapter, &dma64);
2983 if (err < 0)
2984 goto err_alloc_pci;
2985
2986 ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_VRRS);
2987 if (ver & 1) {
2988 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_VRRS, 1);
2989 } else {
2990 dev_err(&pdev->dev,
2991 "Incompatible h/w version (0x%x) for adapter\n", ver);
2992 err = -EBUSY;
2993 goto err_ver;
2994 }
2995
2996 ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_UVRS);
2997 if (ver & 1) {
2998 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_UVRS, 1);
2999 } else {
3000 dev_err(&pdev->dev,
3001 "Incompatible upt version (0x%x) for adapter\n", ver);
3002 err = -EBUSY;
3003 goto err_ver;
3004 }
3005
3006 SET_NETDEV_DEV(netdev, &pdev->dev);
3007 vmxnet3_declare_features(adapter, dma64);
3008
3009 adapter->dev_number = atomic_read(&devices_found);
3010
3011 adapter->share_intr = irq_share_mode;
3012 if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE &&
3013 adapter->num_tx_queues != adapter->num_rx_queues)
3014 adapter->share_intr = VMXNET3_INTR_DONTSHARE;
3015
3016 vmxnet3_alloc_intr_resources(adapter);
3017
3018 #ifdef VMXNET3_RSS
3019 if (adapter->num_rx_queues > 1 &&
3020 adapter->intr.type == VMXNET3_IT_MSIX) {
3021 adapter->rss = true;
3022 dev_dbg(&pdev->dev, "RSS is enabled.\n");
3023 } else {
3024 adapter->rss = false;
3025 }
3026 #endif
3027
3028 vmxnet3_read_mac_addr(adapter, mac);
3029 memcpy(netdev->dev_addr, mac, netdev->addr_len);
3030
3031 netdev->netdev_ops = &vmxnet3_netdev_ops;
3032 vmxnet3_set_ethtool_ops(netdev);
3033 netdev->watchdog_timeo = 5 * HZ;
3034
3035 INIT_WORK(&adapter->work, vmxnet3_reset_work);
3036 set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state);
3037
3038 if (adapter->intr.type == VMXNET3_IT_MSIX) {
3039 int i;
3040 for (i = 0; i < adapter->num_rx_queues; i++) {
3041 netif_napi_add(adapter->netdev,
3042 &adapter->rx_queue[i].napi,
3043 vmxnet3_poll_rx_only, 64);
3044 }
3045 } else {
3046 netif_napi_add(adapter->netdev, &adapter->rx_queue[0].napi,
3047 vmxnet3_poll, 64);
3048 }
3049
3050 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
3051 netif_set_real_num_rx_queues(adapter->netdev, adapter->num_rx_queues);
3052
3053 err = register_netdev(netdev);
3054
3055 if (err) {
3056 dev_err(&pdev->dev, "Failed to register adapter\n");
3057 goto err_register;
3058 }
3059
3060 vmxnet3_check_link(adapter, false);
3061 atomic_inc(&devices_found);
3062 return 0;
3063
3064 err_register:
3065 vmxnet3_free_intr_resources(adapter);
3066 err_ver:
3067 vmxnet3_free_pci_resources(adapter);
3068 err_alloc_pci:
3069 #ifdef VMXNET3_RSS
3070 kfree(adapter->rss_conf);
3071 err_alloc_rss:
3072 #endif
3073 kfree(adapter->pm_conf);
3074 err_alloc_pm:
3075 pci_free_consistent(adapter->pdev, size, adapter->tqd_start,
3076 adapter->queue_desc_pa);
3077 err_alloc_queue_desc:
3078 pci_free_consistent(adapter->pdev, sizeof(struct Vmxnet3_DriverShared),
3079 adapter->shared, adapter->shared_pa);
3080 err_alloc_shared:
3081 pci_set_drvdata(pdev, NULL);
3082 free_netdev(netdev);
3083 return err;
3084 }
3085
3086
3087 static void
3088 vmxnet3_remove_device(struct pci_dev *pdev)
3089 {
3090 struct net_device *netdev = pci_get_drvdata(pdev);
3091 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3092 int size = 0;
3093 int num_rx_queues;
3094
3095 #ifdef VMXNET3_RSS
3096 if (enable_mq)
3097 num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES,
3098 (int)num_online_cpus());
3099 else
3100 #endif
3101 num_rx_queues = 1;
3102 num_rx_queues = rounddown_pow_of_two(num_rx_queues);
3103
3104 cancel_work_sync(&adapter->work);
3105
3106 unregister_netdev(netdev);
3107
3108 vmxnet3_free_intr_resources(adapter);
3109 vmxnet3_free_pci_resources(adapter);
3110 #ifdef VMXNET3_RSS
3111 kfree(adapter->rss_conf);
3112 #endif
3113 kfree(adapter->pm_conf);
3114
3115 size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues;
3116 size += sizeof(struct Vmxnet3_RxQueueDesc) * num_rx_queues;
3117 pci_free_consistent(adapter->pdev, size, adapter->tqd_start,
3118 adapter->queue_desc_pa);
3119 pci_free_consistent(adapter->pdev, sizeof(struct Vmxnet3_DriverShared),
3120 adapter->shared, adapter->shared_pa);
3121 free_netdev(netdev);
3122 }
3123
3124
3125 #ifdef CONFIG_PM
3126
3127 static int
3128 vmxnet3_suspend(struct device *device)
3129 {
3130 struct pci_dev *pdev = to_pci_dev(device);
3131 struct net_device *netdev = pci_get_drvdata(pdev);
3132 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3133 struct Vmxnet3_PMConf *pmConf;
3134 struct ethhdr *ehdr;
3135 struct arphdr *ahdr;
3136 u8 *arpreq;
3137 struct in_device *in_dev;
3138 struct in_ifaddr *ifa;
3139 unsigned long flags;
3140 int i = 0;
3141
3142 if (!netif_running(netdev))
3143 return 0;
3144
3145 for (i = 0; i < adapter->num_rx_queues; i++)
3146 napi_disable(&adapter->rx_queue[i].napi);
3147
3148 vmxnet3_disable_all_intrs(adapter);
3149 vmxnet3_free_irqs(adapter);
3150 vmxnet3_free_intr_resources(adapter);
3151
3152 netif_device_detach(netdev);
3153 netif_tx_stop_all_queues(netdev);
3154
3155 /* Create wake-up filters. */
3156 pmConf = adapter->pm_conf;
3157 memset(pmConf, 0, sizeof(*pmConf));
3158
3159 if (adapter->wol & WAKE_UCAST) {
3160 pmConf->filters[i].patternSize = ETH_ALEN;
3161 pmConf->filters[i].maskSize = 1;
3162 memcpy(pmConf->filters[i].pattern, netdev->dev_addr, ETH_ALEN);
3163 pmConf->filters[i].mask[0] = 0x3F; /* LSB ETH_ALEN bits */
3164
3165 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER;
3166 i++;
3167 }
3168
3169 if (adapter->wol & WAKE_ARP) {
3170 in_dev = in_dev_get(netdev);
3171 if (!in_dev)
3172 goto skip_arp;
3173
3174 ifa = (struct in_ifaddr *)in_dev->ifa_list;
3175 if (!ifa)
3176 goto skip_arp;
3177
3178 pmConf->filters[i].patternSize = ETH_HLEN + /* Ethernet header*/
3179 sizeof(struct arphdr) + /* ARP header */
3180 2 * ETH_ALEN + /* 2 Ethernet addresses*/
3181 2 * sizeof(u32); /*2 IPv4 addresses */
3182 pmConf->filters[i].maskSize =
3183 (pmConf->filters[i].patternSize - 1) / 8 + 1;
3184
3185 /* ETH_P_ARP in Ethernet header. */
3186 ehdr = (struct ethhdr *)pmConf->filters[i].pattern;
3187 ehdr->h_proto = htons(ETH_P_ARP);
3188
3189 /* ARPOP_REQUEST in ARP header. */
3190 ahdr = (struct arphdr *)&pmConf->filters[i].pattern[ETH_HLEN];
3191 ahdr->ar_op = htons(ARPOP_REQUEST);
3192 arpreq = (u8 *)(ahdr + 1);
3193
3194 /* The Unicast IPv4 address in 'tip' field. */
3195 arpreq += 2 * ETH_ALEN + sizeof(u32);
3196 *(u32 *)arpreq = ifa->ifa_address;
3197
3198 /* The mask for the relevant bits. */
3199 pmConf->filters[i].mask[0] = 0x00;
3200 pmConf->filters[i].mask[1] = 0x30; /* ETH_P_ARP */
3201 pmConf->filters[i].mask[2] = 0x30; /* ARPOP_REQUEST */
3202 pmConf->filters[i].mask[3] = 0x00;
3203 pmConf->filters[i].mask[4] = 0xC0; /* IPv4 TIP */
3204 pmConf->filters[i].mask[5] = 0x03; /* IPv4 TIP */
3205 in_dev_put(in_dev);
3206
3207 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER;
3208 i++;
3209 }
3210
3211 skip_arp:
3212 if (adapter->wol & WAKE_MAGIC)
3213 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_MAGIC;
3214
3215 pmConf->numFilters = i;
3216
3217 adapter->shared->devRead.pmConfDesc.confVer = cpu_to_le32(1);
3218 adapter->shared->devRead.pmConfDesc.confLen = cpu_to_le32(sizeof(
3219 *pmConf));
3220 adapter->shared->devRead.pmConfDesc.confPA = cpu_to_le64(virt_to_phys(
3221 pmConf));
3222
3223 spin_lock_irqsave(&adapter->cmd_lock, flags);
3224 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3225 VMXNET3_CMD_UPDATE_PMCFG);
3226 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
3227
3228 pci_save_state(pdev);
3229 pci_enable_wake(pdev, pci_choose_state(pdev, PMSG_SUSPEND),
3230 adapter->wol);
3231 pci_disable_device(pdev);
3232 pci_set_power_state(pdev, pci_choose_state(pdev, PMSG_SUSPEND));
3233
3234 return 0;
3235 }
3236
3237
3238 static int
3239 vmxnet3_resume(struct device *device)
3240 {
3241 int err, i = 0;
3242 unsigned long flags;
3243 struct pci_dev *pdev = to_pci_dev(device);
3244 struct net_device *netdev = pci_get_drvdata(pdev);
3245 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3246 struct Vmxnet3_PMConf *pmConf;
3247
3248 if (!netif_running(netdev))
3249 return 0;
3250
3251 /* Destroy wake-up filters. */
3252 pmConf = adapter->pm_conf;
3253 memset(pmConf, 0, sizeof(*pmConf));
3254
3255 adapter->shared->devRead.pmConfDesc.confVer = cpu_to_le32(1);
3256 adapter->shared->devRead.pmConfDesc.confLen = cpu_to_le32(sizeof(
3257 *pmConf));
3258 adapter->shared->devRead.pmConfDesc.confPA = cpu_to_le64(virt_to_phys(
3259 pmConf));
3260
3261 netif_device_attach(netdev);
3262 pci_set_power_state(pdev, PCI_D0);
3263 pci_restore_state(pdev);
3264 err = pci_enable_device_mem(pdev);
3265 if (err != 0)
3266 return err;
3267
3268 pci_enable_wake(pdev, PCI_D0, 0);
3269
3270 spin_lock_irqsave(&adapter->cmd_lock, flags);
3271 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3272 VMXNET3_CMD_UPDATE_PMCFG);
3273 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
3274 vmxnet3_alloc_intr_resources(adapter);
3275 vmxnet3_request_irqs(adapter);
3276 for (i = 0; i < adapter->num_rx_queues; i++)
3277 napi_enable(&adapter->rx_queue[i].napi);
3278 vmxnet3_enable_all_intrs(adapter);
3279
3280 return 0;
3281 }
3282
3283 static const struct dev_pm_ops vmxnet3_pm_ops = {
3284 .suspend = vmxnet3_suspend,
3285 .resume = vmxnet3_resume,
3286 };
3287 #endif
3288
3289 static struct pci_driver vmxnet3_driver = {
3290 .name = vmxnet3_driver_name,
3291 .id_table = vmxnet3_pciid_table,
3292 .probe = vmxnet3_probe_device,
3293 .remove = vmxnet3_remove_device,
3294 #ifdef CONFIG_PM
3295 .driver.pm = &vmxnet3_pm_ops,
3296 #endif
3297 };
3298
3299
3300 static int __init
3301 vmxnet3_init_module(void)
3302 {
3303 pr_info("%s - version %s\n", VMXNET3_DRIVER_DESC,
3304 VMXNET3_DRIVER_VERSION_REPORT);
3305 return pci_register_driver(&vmxnet3_driver);
3306 }
3307
3308 module_init(vmxnet3_init_module);
3309
3310
3311 static void
3312 vmxnet3_exit_module(void)
3313 {
3314 pci_unregister_driver(&vmxnet3_driver);
3315 }
3316
3317 module_exit(vmxnet3_exit_module);
3318
3319 MODULE_AUTHOR("VMware, Inc.");
3320 MODULE_DESCRIPTION(VMXNET3_DRIVER_DESC);
3321 MODULE_LICENSE("GPL v2");
3322 MODULE_VERSION(VMXNET3_DRIVER_VERSION_STRING);
Linux kernel - Deliverables
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