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hwmon: (max6650) Add support for alarms
[deliverable/linux.git] / drivers / net / wan / pc300_drv.c
1 #define USE_PCI_CLOCK
2 static char rcsid[] =
3 "Revision: 3.4.5 Date: 2002/03/07 ";
4
5 /*
6 * pc300.c Cyclades-PC300(tm) Driver.
7 *
8 * Author: Ivan Passos <ivan@cyclades.com>
9 * Maintainer: PC300 Maintainer <pc300@cyclades.com>
10 *
11 * Copyright: (c) 1999-2003 Cyclades Corp.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
17 *
18 * Using tabstop = 4.
19 *
20 * $Log: pc300_drv.c,v $
21 * Revision 3.23 2002/03/20 13:58:40 henrique
22 * Fixed ortographic mistakes
23 *
24 * Revision 3.22 2002/03/13 16:56:56 henrique
25 * Take out the debug messages
26 *
27 * Revision 3.21 2002/03/07 14:17:09 henrique
28 * License data fixed
29 *
30 * Revision 3.20 2002/01/17 17:58:52 ivan
31 * Support for PC300-TE/M (PMC).
32 *
33 * Revision 3.19 2002/01/03 17:08:47 daniela
34 * Enables DMA reception when the SCA-II disables it improperly.
35 *
36 * Revision 3.18 2001/12/03 18:47:50 daniela
37 * Esthetic changes.
38 *
39 * Revision 3.17 2001/10/19 16:50:13 henrique
40 * Patch to kernel 2.4.12 and new generic hdlc.
41 *
42 * Revision 3.16 2001/10/16 15:12:31 regina
43 * clear statistics
44 *
45 * Revision 3.11 to 3.15 2001/10/11 20:26:04 daniela
46 * More DMA fixes for noisy lines.
47 * Return the size of bad frames in dma_get_rx_frame_size, so that the Rx buffer
48 * descriptors can be cleaned by dma_buf_read (called in cpc_net_rx).
49 * Renamed dma_start routine to rx_dma_start. Improved Rx statistics.
50 * Fixed BOF interrupt treatment. Created dma_start routine.
51 * Changed min and max to cpc_min and cpc_max.
52 *
53 * Revision 3.10 2001/08/06 12:01:51 regina
54 * Fixed problem in DSR_DE bit.
55 *
56 * Revision 3.9 2001/07/18 19:27:26 daniela
57 * Added some history comments.
58 *
59 * Revision 3.8 2001/07/12 13:11:19 regina
60 * bug fix - DCD-OFF in pc300 tty driver
61 *
62 * Revision 3.3 to 3.7 2001/07/06 15:00:20 daniela
63 * Removing kernel 2.4.3 and previous support.
64 * DMA transmission bug fix.
65 * MTU check in cpc_net_rx fixed.
66 * Boot messages reviewed.
67 * New configuration parameters (line code, CRC calculation and clock).
68 *
69 * Revision 3.2 2001/06/22 13:13:02 regina
70 * MLPPP implementation. Changed the header of message trace to include
71 * the device name. New format : "hdlcX[R/T]: ".
72 * Default configuration changed.
73 *
74 * Revision 3.1 2001/06/15 regina
75 * in cpc_queue_xmit, netif_stop_queue is called if don't have free descriptor
76 * upping major version number
77 *
78 * Revision 1.1.1.1 2001/06/13 20:25:04 daniela
79 * PC300 initial CVS version (3.4.0-pre1)
80 *
81 * Revision 3.0.1.2 2001/06/08 daniela
82 * Did some changes in the DMA programming implementation to avoid the
83 * occurrence of a SCA-II bug when CDA is accessed during a DMA transfer.
84 *
85 * Revision 3.0.1.1 2001/05/02 daniela
86 * Added kernel 2.4.3 support.
87 *
88 * Revision 3.0.1.0 2001/03/13 daniela, henrique
89 * Added Frame Relay Support.
90 * Driver now uses HDLC generic driver to provide protocol support.
91 *
92 * Revision 3.0.0.8 2001/03/02 daniela
93 * Fixed ram size detection.
94 * Changed SIOCGPC300CONF ioctl, to give hw information to pc300util.
95 *
96 * Revision 3.0.0.7 2001/02/23 daniela
97 * netif_stop_queue called before the SCA-II transmition commands in
98 * cpc_queue_xmit, and with interrupts disabled to avoid race conditions with
99 * transmition interrupts.
100 * Fixed falc_check_status for Unframed E1.
101 *
102 * Revision 3.0.0.6 2000/12/13 daniela
103 * Implemented pc300util support: trace, statistics, status and loopback
104 * tests for the PC300 TE boards.
105 *
106 * Revision 3.0.0.5 2000/12/12 ivan
107 * Added support for Unframed E1.
108 * Implemented monitor mode.
109 * Fixed DCD sensitivity on the second channel.
110 * Driver now complies with new PCI kernel architecture.
111 *
112 * Revision 3.0.0.4 2000/09/28 ivan
113 * Implemented DCD sensitivity.
114 * Moved hardware-specific open to the end of cpc_open, to avoid race
115 * conditions with early reception interrupts.
116 * Included code for [request|release]_mem_region().
117 * Changed location of pc300.h .
118 * Minor code revision (contrib. of Jeff Garzik).
119 *
120 * Revision 3.0.0.3 2000/07/03 ivan
121 * Previous bugfix for the framing errors with external clock made X21
122 * boards stop working. This version fixes it.
123 *
124 * Revision 3.0.0.2 2000/06/23 ivan
125 * Revisited cpc_queue_xmit to prevent race conditions on Tx DMA buffer
126 * handling when Tx timeouts occur.
127 * Revisited Rx statistics.
128 * Fixed a bug in the SCA-II programming that would cause framing errors
129 * when external clock was configured.
130 *
131 * Revision 3.0.0.1 2000/05/26 ivan
132 * Added logic in the SCA interrupt handler so that no board can monopolize
133 * the driver.
134 * Request PLX I/O region, although driver doesn't use it, to avoid
135 * problems with other drivers accessing it.
136 *
137 * Revision 3.0.0.0 2000/05/15 ivan
138 * Did some changes in the DMA programming implementation to avoid the
139 * occurrence of a SCA-II bug in the second channel.
140 * Implemented workaround for PLX9050 bug that would cause a system lockup
141 * in certain systems, depending on the MMIO addresses allocated to the
142 * board.
143 * Fixed the FALC chip programming to avoid synchronization problems in the
144 * second channel (TE only).
145 * Implemented a cleaner and faster Tx DMA descriptor cleanup procedure in
146 * cpc_queue_xmit().
147 * Changed the built-in driver implementation so that the driver can use the
148 * general 'hdlcN' naming convention instead of proprietary device names.
149 * Driver load messages are now device-centric, instead of board-centric.
150 * Dynamic allocation of net_device structures.
151 * Code is now compliant with the new module interface (module_[init|exit]).
152 * Make use of the PCI helper functions to access PCI resources.
153 *
154 * Revision 2.0.0.0 2000/04/15 ivan
155 * Added support for the PC300/TE boards (T1/FT1/E1/FE1).
156 *
157 * Revision 1.1.0.0 2000/02/28 ivan
158 * Major changes in the driver architecture.
159 * Softnet compliancy implemented.
160 * Driver now reports physical instead of virtual memory addresses.
161 * Added cpc_change_mtu function.
162 *
163 * Revision 1.0.0.0 1999/12/16 ivan
164 * First official release.
165 * Support for 1- and 2-channel boards (which use distinct PCI Device ID's).
166 * Support for monolythic installation (i.e., drv built into the kernel).
167 * X.25 additional checking when lapb_[dis]connect_request returns an error.
168 * SCA programming now covers X.21 as well.
169 *
170 * Revision 0.3.1.0 1999/11/18 ivan
171 * Made X.25 support configuration-dependent (as it depends on external
172 * modules to work).
173 * Changed X.25-specific function names to comply with adopted convention.
174 * Fixed typos in X.25 functions that would cause compile errors (Daniela).
175 * Fixed bug in ch_config that would disable interrupts on a previously
176 * enabled channel if the other channel on the same board was enabled later.
177 *
178 * Revision 0.3.0.0 1999/11/16 daniela
179 * X.25 support.
180 *
181 * Revision 0.2.3.0 1999/11/15 ivan
182 * Function cpc_ch_status now provides more detailed information.
183 * Added support for X.21 clock configuration.
184 * Changed TNR1 setting in order to prevent Tx FIFO overaccesses by the SCA.
185 * Now using PCI clock instead of internal oscillator clock for the SCA.
186 *
187 * Revision 0.2.2.0 1999/11/10 ivan
188 * Changed the *_dma_buf_check functions so that they would print only
189 * the useful info instead of the whole buffer descriptor bank.
190 * Fixed bug in cpc_queue_xmit that would eventually crash the system
191 * in case of a packet drop.
192 * Implemented TX underrun handling.
193 * Improved SCA fine tuning to boost up its performance.
194 *
195 * Revision 0.2.1.0 1999/11/03 ivan
196 * Added functions *dma_buf_pt_init to allow independent initialization
197 * of the next-descr. and DMA buffer pointers on the DMA descriptors.
198 * Kernel buffer release and tbusy clearing is now done in the interrupt
199 * handler.
200 * Fixed bug in cpc_open that would cause an interface reopen to fail.
201 * Added a protocol-specific code section in cpc_net_rx.
202 * Removed printk level defs (they might be added back after the beta phase).
203 *
204 * Revision 0.2.0.0 1999/10/28 ivan
205 * Revisited the code so that new protocols can be easily added / supported.
206 *
207 * Revision 0.1.0.1 1999/10/20 ivan
208 * Mostly "esthetic" changes.
209 *
210 * Revision 0.1.0.0 1999/10/11 ivan
211 * Initial version.
212 *
213 */
214
215 #include <linux/module.h>
216 #include <linux/kernel.h>
217 #include <linux/mm.h>
218 #include <linux/ioport.h>
219 #include <linux/pci.h>
220 #include <linux/errno.h>
221 #include <linux/string.h>
222 #include <linux/init.h>
223 #include <linux/delay.h>
224 #include <linux/net.h>
225 #include <linux/skbuff.h>
226 #include <linux/if_arp.h>
227 #include <linux/netdevice.h>
228 #include <linux/spinlock.h>
229 #include <linux/if.h>
230 #include <net/arp.h>
231
232 #include <asm/io.h>
233 #include <asm/uaccess.h>
234
235 #include "pc300.h"
236
237 #define CPC_LOCK(card,flags) \
238 do { \
239 spin_lock_irqsave(&card->card_lock, flags); \
240 } while (0)
241
242 #define CPC_UNLOCK(card,flags) \
243 do { \
244 spin_unlock_irqrestore(&card->card_lock, flags); \
245 } while (0)
246
247 #undef PC300_DEBUG_PCI
248 #undef PC300_DEBUG_INTR
249 #undef PC300_DEBUG_TX
250 #undef PC300_DEBUG_RX
251 #undef PC300_DEBUG_OTHER
252
253 static struct pci_device_id cpc_pci_dev_id[] __devinitdata = {
254 /* PC300/RSV or PC300/X21, 2 chan */
255 {0x120e, 0x300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x300},
256 /* PC300/RSV or PC300/X21, 1 chan */
257 {0x120e, 0x301, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x301},
258 /* PC300/TE, 2 chan */
259 {0x120e, 0x310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x310},
260 /* PC300/TE, 1 chan */
261 {0x120e, 0x311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x311},
262 /* PC300/TE-M, 2 chan */
263 {0x120e, 0x320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x320},
264 /* PC300/TE-M, 1 chan */
265 {0x120e, 0x321, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x321},
266 /* End of table */
267 {0,},
268 };
269 MODULE_DEVICE_TABLE(pci, cpc_pci_dev_id);
270
271 #ifndef cpc_min
272 #define cpc_min(a,b) (((a)<(b))?(a):(b))
273 #endif
274 #ifndef cpc_max
275 #define cpc_max(a,b) (((a)>(b))?(a):(b))
276 #endif
277
278 /* prototypes */
279 static void tx_dma_buf_pt_init(pc300_t *, int);
280 static void tx_dma_buf_init(pc300_t *, int);
281 static void rx_dma_buf_pt_init(pc300_t *, int);
282 static void rx_dma_buf_init(pc300_t *, int);
283 static void tx_dma_buf_check(pc300_t *, int);
284 static void rx_dma_buf_check(pc300_t *, int);
285 static irqreturn_t cpc_intr(int, void *);
286 static int clock_rate_calc(u32, u32, int *);
287 static u32 detect_ram(pc300_t *);
288 static void plx_init(pc300_t *);
289 static void cpc_trace(struct net_device *, struct sk_buff *, char);
290 static int cpc_attach(struct net_device *, unsigned short, unsigned short);
291 static int cpc_close(struct net_device *dev);
292
293 #ifdef CONFIG_PC300_MLPPP
294 void cpc_tty_init(pc300dev_t * dev);
295 void cpc_tty_unregister_service(pc300dev_t * pc300dev);
296 void cpc_tty_receive(pc300dev_t * pc300dev);
297 void cpc_tty_trigger_poll(pc300dev_t * pc300dev);
298 void cpc_tty_reset_var(void);
299 #endif
300
301 /************************/
302 /*** DMA Routines ***/
303 /************************/
304 static void tx_dma_buf_pt_init(pc300_t * card, int ch)
305 {
306 int i;
307 int ch_factor = ch * N_DMA_TX_BUF;
308 volatile pcsca_bd_t __iomem *ptdescr = (card->hw.rambase
309 + DMA_TX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
310
311 for (i = 0; i < N_DMA_TX_BUF; i++, ptdescr++) {
312 cpc_writel(&ptdescr->next, (u32)(DMA_TX_BD_BASE +
313 (ch_factor + ((i + 1) & (N_DMA_TX_BUF - 1))) * sizeof(pcsca_bd_t)));
314 cpc_writel(&ptdescr->ptbuf,
315 (u32)(DMA_TX_BASE + (ch_factor + i) * BD_DEF_LEN));
316 }
317 }
318
319 static void tx_dma_buf_init(pc300_t * card, int ch)
320 {
321 int i;
322 int ch_factor = ch * N_DMA_TX_BUF;
323 volatile pcsca_bd_t __iomem *ptdescr = (card->hw.rambase
324 + DMA_TX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
325
326 for (i = 0; i < N_DMA_TX_BUF; i++, ptdescr++) {
327 memset_io(ptdescr, 0, sizeof(pcsca_bd_t));
328 cpc_writew(&ptdescr->len, 0);
329 cpc_writeb(&ptdescr->status, DST_OSB);
330 }
331 tx_dma_buf_pt_init(card, ch);
332 }
333
334 static void rx_dma_buf_pt_init(pc300_t * card, int ch)
335 {
336 int i;
337 int ch_factor = ch * N_DMA_RX_BUF;
338 volatile pcsca_bd_t __iomem *ptdescr = (card->hw.rambase
339 + DMA_RX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
340
341 for (i = 0; i < N_DMA_RX_BUF; i++, ptdescr++) {
342 cpc_writel(&ptdescr->next, (u32)(DMA_RX_BD_BASE +
343 (ch_factor + ((i + 1) & (N_DMA_RX_BUF - 1))) * sizeof(pcsca_bd_t)));
344 cpc_writel(&ptdescr->ptbuf,
345 (u32)(DMA_RX_BASE + (ch_factor + i) * BD_DEF_LEN));
346 }
347 }
348
349 static void rx_dma_buf_init(pc300_t * card, int ch)
350 {
351 int i;
352 int ch_factor = ch * N_DMA_RX_BUF;
353 volatile pcsca_bd_t __iomem *ptdescr = (card->hw.rambase
354 + DMA_RX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
355
356 for (i = 0; i < N_DMA_RX_BUF; i++, ptdescr++) {
357 memset_io(ptdescr, 0, sizeof(pcsca_bd_t));
358 cpc_writew(&ptdescr->len, 0);
359 cpc_writeb(&ptdescr->status, 0);
360 }
361 rx_dma_buf_pt_init(card, ch);
362 }
363
364 static void tx_dma_buf_check(pc300_t * card, int ch)
365 {
366 volatile pcsca_bd_t __iomem *ptdescr;
367 int i;
368 u16 first_bd = card->chan[ch].tx_first_bd;
369 u16 next_bd = card->chan[ch].tx_next_bd;
370
371 printk("#CH%d: f_bd = %d(0x%08zx), n_bd = %d(0x%08zx)\n", ch,
372 first_bd, TX_BD_ADDR(ch, first_bd),
373 next_bd, TX_BD_ADDR(ch, next_bd));
374 for (i = first_bd,
375 ptdescr = (card->hw.rambase + TX_BD_ADDR(ch, first_bd));
376 i != ((next_bd + 1) & (N_DMA_TX_BUF - 1));
377 i = (i + 1) & (N_DMA_TX_BUF - 1),
378 ptdescr = (card->hw.rambase + TX_BD_ADDR(ch, i))) {
379 printk("\n CH%d TX%d: next=0x%x, ptbuf=0x%x, ST=0x%x, len=%d",
380 ch, i, cpc_readl(&ptdescr->next),
381 cpc_readl(&ptdescr->ptbuf),
382 cpc_readb(&ptdescr->status), cpc_readw(&ptdescr->len));
383 }
384 printk("\n");
385 }
386
387 #ifdef PC300_DEBUG_OTHER
388 /* Show all TX buffer descriptors */
389 static void tx1_dma_buf_check(pc300_t * card, int ch)
390 {
391 volatile pcsca_bd_t __iomem *ptdescr;
392 int i;
393 u16 first_bd = card->chan[ch].tx_first_bd;
394 u16 next_bd = card->chan[ch].tx_next_bd;
395 u32 scabase = card->hw.scabase;
396
397 printk ("\nnfree_tx_bd = %d \n", card->chan[ch].nfree_tx_bd);
398 printk("#CH%d: f_bd = %d(0x%08x), n_bd = %d(0x%08x)\n", ch,
399 first_bd, TX_BD_ADDR(ch, first_bd),
400 next_bd, TX_BD_ADDR(ch, next_bd));
401 printk("TX_CDA=0x%08x, TX_EDA=0x%08x\n",
402 cpc_readl(scabase + DTX_REG(CDAL, ch)),
403 cpc_readl(scabase + DTX_REG(EDAL, ch)));
404 for (i = 0; i < N_DMA_TX_BUF; i++) {
405 ptdescr = (card->hw.rambase + TX_BD_ADDR(ch, i));
406 printk("\n CH%d TX%d: next=0x%x, ptbuf=0x%x, ST=0x%x, len=%d",
407 ch, i, cpc_readl(&ptdescr->next),
408 cpc_readl(&ptdescr->ptbuf),
409 cpc_readb(&ptdescr->status), cpc_readw(&ptdescr->len));
410 }
411 printk("\n");
412 }
413 #endif
414
415 static void rx_dma_buf_check(pc300_t * card, int ch)
416 {
417 volatile pcsca_bd_t __iomem *ptdescr;
418 int i;
419 u16 first_bd = card->chan[ch].rx_first_bd;
420 u16 last_bd = card->chan[ch].rx_last_bd;
421 int ch_factor;
422
423 ch_factor = ch * N_DMA_RX_BUF;
424 printk("#CH%d: f_bd = %d, l_bd = %d\n", ch, first_bd, last_bd);
425 for (i = 0, ptdescr = (card->hw.rambase +
426 DMA_RX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
427 i < N_DMA_RX_BUF; i++, ptdescr++) {
428 if (cpc_readb(&ptdescr->status) & DST_OSB)
429 printk ("\n CH%d RX%d: next=0x%x, ptbuf=0x%x, ST=0x%x, len=%d",
430 ch, i, cpc_readl(&ptdescr->next),
431 cpc_readl(&ptdescr->ptbuf),
432 cpc_readb(&ptdescr->status),
433 cpc_readw(&ptdescr->len));
434 }
435 printk("\n");
436 }
437
438 static int dma_get_rx_frame_size(pc300_t * card, int ch)
439 {
440 volatile pcsca_bd_t __iomem *ptdescr;
441 u16 first_bd = card->chan[ch].rx_first_bd;
442 int rcvd = 0;
443 volatile u8 status;
444
445 ptdescr = (card->hw.rambase + RX_BD_ADDR(ch, first_bd));
446 while ((status = cpc_readb(&ptdescr->status)) & DST_OSB) {
447 rcvd += cpc_readw(&ptdescr->len);
448 first_bd = (first_bd + 1) & (N_DMA_RX_BUF - 1);
449 if ((status & DST_EOM) || (first_bd == card->chan[ch].rx_last_bd)) {
450 /* Return the size of a good frame or incomplete bad frame
451 * (dma_buf_read will clean the buffer descriptors in this case). */
452 return (rcvd);
453 }
454 ptdescr = (card->hw.rambase + cpc_readl(&ptdescr->next));
455 }
456 return (-1);
457 }
458
459 /*
460 * dma_buf_write: writes a frame to the Tx DMA buffers
461 * NOTE: this function writes one frame at a time.
462 */
463 static int dma_buf_write(pc300_t *card, int ch, u8 *ptdata, int len)
464 {
465 int i, nchar;
466 volatile pcsca_bd_t __iomem *ptdescr;
467 int tosend = len;
468 u8 nbuf = ((len - 1) / BD_DEF_LEN) + 1;
469
470 if (nbuf >= card->chan[ch].nfree_tx_bd) {
471 return -ENOMEM;
472 }
473
474 for (i = 0; i < nbuf; i++) {
475 ptdescr = (card->hw.rambase +
476 TX_BD_ADDR(ch, card->chan[ch].tx_next_bd));
477 nchar = cpc_min(BD_DEF_LEN, tosend);
478 if (cpc_readb(&ptdescr->status) & DST_OSB) {
479 memcpy_toio((card->hw.rambase + cpc_readl(&ptdescr->ptbuf)),
480 &ptdata[len - tosend], nchar);
481 cpc_writew(&ptdescr->len, nchar);
482 card->chan[ch].nfree_tx_bd--;
483 if ((i + 1) == nbuf) {
484 /* This must be the last BD to be used */
485 cpc_writeb(&ptdescr->status, DST_EOM);
486 } else {
487 cpc_writeb(&ptdescr->status, 0);
488 }
489 } else {
490 return -ENOMEM;
491 }
492 tosend -= nchar;
493 card->chan[ch].tx_next_bd =
494 (card->chan[ch].tx_next_bd + 1) & (N_DMA_TX_BUF - 1);
495 }
496 /* If it gets to here, it means we have sent the whole frame */
497 return 0;
498 }
499
500 /*
501 * dma_buf_read: reads a frame from the Rx DMA buffers
502 * NOTE: this function reads one frame at a time.
503 */
504 static int dma_buf_read(pc300_t * card, int ch, struct sk_buff *skb)
505 {
506 int nchar;
507 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
508 volatile pcsca_bd_t __iomem *ptdescr;
509 int rcvd = 0;
510 volatile u8 status;
511
512 ptdescr = (card->hw.rambase +
513 RX_BD_ADDR(ch, chan->rx_first_bd));
514 while ((status = cpc_readb(&ptdescr->status)) & DST_OSB) {
515 nchar = cpc_readw(&ptdescr->len);
516 if ((status & (DST_OVR | DST_CRC | DST_RBIT | DST_SHRT | DST_ABT))
517 || (nchar > BD_DEF_LEN)) {
518
519 if (nchar > BD_DEF_LEN)
520 status |= DST_RBIT;
521 rcvd = -status;
522 /* Discard remaining descriptors used by the bad frame */
523 while (chan->rx_first_bd != chan->rx_last_bd) {
524 cpc_writeb(&ptdescr->status, 0);
525 chan->rx_first_bd = (chan->rx_first_bd+1) & (N_DMA_RX_BUF-1);
526 if (status & DST_EOM)
527 break;
528 ptdescr = (card->hw.rambase +
529 cpc_readl(&ptdescr->next));
530 status = cpc_readb(&ptdescr->status);
531 }
532 break;
533 }
534 if (nchar != 0) {
535 if (skb) {
536 memcpy_fromio(skb_put(skb, nchar),
537 (card->hw.rambase+cpc_readl(&ptdescr->ptbuf)),nchar);
538 }
539 rcvd += nchar;
540 }
541 cpc_writeb(&ptdescr->status, 0);
542 cpc_writeb(&ptdescr->len, 0);
543 chan->rx_first_bd = (chan->rx_first_bd + 1) & (N_DMA_RX_BUF - 1);
544
545 if (status & DST_EOM)
546 break;
547
548 ptdescr = (card->hw.rambase + cpc_readl(&ptdescr->next));
549 }
550
551 if (rcvd != 0) {
552 /* Update pointer */
553 chan->rx_last_bd = (chan->rx_first_bd - 1) & (N_DMA_RX_BUF - 1);
554 /* Update EDA */
555 cpc_writel(card->hw.scabase + DRX_REG(EDAL, ch),
556 RX_BD_ADDR(ch, chan->rx_last_bd));
557 }
558 return (rcvd);
559 }
560
561 static void tx_dma_stop(pc300_t * card, int ch)
562 {
563 void __iomem *scabase = card->hw.scabase;
564 u8 drr_ena_bit = 1 << (5 + 2 * ch);
565 u8 drr_rst_bit = 1 << (1 + 2 * ch);
566
567 /* Disable DMA */
568 cpc_writeb(scabase + DRR, drr_ena_bit);
569 cpc_writeb(scabase + DRR, drr_rst_bit & ~drr_ena_bit);
570 }
571
572 static void rx_dma_stop(pc300_t * card, int ch)
573 {
574 void __iomem *scabase = card->hw.scabase;
575 u8 drr_ena_bit = 1 << (4 + 2 * ch);
576 u8 drr_rst_bit = 1 << (2 * ch);
577
578 /* Disable DMA */
579 cpc_writeb(scabase + DRR, drr_ena_bit);
580 cpc_writeb(scabase + DRR, drr_rst_bit & ~drr_ena_bit);
581 }
582
583 static void rx_dma_start(pc300_t * card, int ch)
584 {
585 void __iomem *scabase = card->hw.scabase;
586 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
587
588 /* Start DMA */
589 cpc_writel(scabase + DRX_REG(CDAL, ch),
590 RX_BD_ADDR(ch, chan->rx_first_bd));
591 if (cpc_readl(scabase + DRX_REG(CDAL,ch)) !=
592 RX_BD_ADDR(ch, chan->rx_first_bd)) {
593 cpc_writel(scabase + DRX_REG(CDAL, ch),
594 RX_BD_ADDR(ch, chan->rx_first_bd));
595 }
596 cpc_writel(scabase + DRX_REG(EDAL, ch),
597 RX_BD_ADDR(ch, chan->rx_last_bd));
598 cpc_writew(scabase + DRX_REG(BFLL, ch), BD_DEF_LEN);
599 cpc_writeb(scabase + DSR_RX(ch), DSR_DE);
600 if (!(cpc_readb(scabase + DSR_RX(ch)) & DSR_DE)) {
601 cpc_writeb(scabase + DSR_RX(ch), DSR_DE);
602 }
603 }
604
605 /*************************/
606 /*** FALC Routines ***/
607 /*************************/
608 static void falc_issue_cmd(pc300_t *card, int ch, u8 cmd)
609 {
610 void __iomem *falcbase = card->hw.falcbase;
611 unsigned long i = 0;
612
613 while (cpc_readb(falcbase + F_REG(SIS, ch)) & SIS_CEC) {
614 if (i++ >= PC300_FALC_MAXLOOP) {
615 printk("%s: FALC command locked(cmd=0x%x).\n",
616 card->chan[ch].d.name, cmd);
617 break;
618 }
619 }
620 cpc_writeb(falcbase + F_REG(CMDR, ch), cmd);
621 }
622
623 static void falc_intr_enable(pc300_t * card, int ch)
624 {
625 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
626 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
627 falc_t *pfalc = (falc_t *) & chan->falc;
628 void __iomem *falcbase = card->hw.falcbase;
629
630 /* Interrupt pins are open-drain */
631 cpc_writeb(falcbase + F_REG(IPC, ch),
632 cpc_readb(falcbase + F_REG(IPC, ch)) & ~IPC_IC0);
633 /* Conters updated each second */
634 cpc_writeb(falcbase + F_REG(FMR1, ch),
635 cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_ECM);
636 /* Enable SEC and ES interrupts */
637 cpc_writeb(falcbase + F_REG(IMR3, ch),
638 cpc_readb(falcbase + F_REG(IMR3, ch)) & ~(IMR3_SEC | IMR3_ES));
639 if (conf->fr_mode == PC300_FR_UNFRAMED) {
640 cpc_writeb(falcbase + F_REG(IMR4, ch),
641 cpc_readb(falcbase + F_REG(IMR4, ch)) & ~(IMR4_LOS));
642 } else {
643 cpc_writeb(falcbase + F_REG(IMR4, ch),
644 cpc_readb(falcbase + F_REG(IMR4, ch)) &
645 ~(IMR4_LFA | IMR4_AIS | IMR4_LOS | IMR4_SLIP));
646 }
647 if (conf->media == IF_IFACE_T1) {
648 cpc_writeb(falcbase + F_REG(IMR3, ch),
649 cpc_readb(falcbase + F_REG(IMR3, ch)) & ~IMR3_LLBSC);
650 } else {
651 cpc_writeb(falcbase + F_REG(IPC, ch),
652 cpc_readb(falcbase + F_REG(IPC, ch)) | IPC_SCI);
653 if (conf->fr_mode == PC300_FR_UNFRAMED) {
654 cpc_writeb(falcbase + F_REG(IMR2, ch),
655 cpc_readb(falcbase + F_REG(IMR2, ch)) & ~(IMR2_LOS));
656 } else {
657 cpc_writeb(falcbase + F_REG(IMR2, ch),
658 cpc_readb(falcbase + F_REG(IMR2, ch)) &
659 ~(IMR2_FAR | IMR2_LFA | IMR2_AIS | IMR2_LOS));
660 if (pfalc->multiframe_mode) {
661 cpc_writeb(falcbase + F_REG(IMR2, ch),
662 cpc_readb(falcbase + F_REG(IMR2, ch)) &
663 ~(IMR2_T400MS | IMR2_MFAR));
664 } else {
665 cpc_writeb(falcbase + F_REG(IMR2, ch),
666 cpc_readb(falcbase + F_REG(IMR2, ch)) |
667 IMR2_T400MS | IMR2_MFAR);
668 }
669 }
670 }
671 }
672
673 static void falc_open_timeslot(pc300_t * card, int ch, int timeslot)
674 {
675 void __iomem *falcbase = card->hw.falcbase;
676 u8 tshf = card->chan[ch].falc.offset;
677
678 cpc_writeb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch),
679 cpc_readb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch)) &
680 ~(0x80 >> ((timeslot - tshf) & 0x07)));
681 cpc_writeb(falcbase + F_REG((TTR1 + timeslot / 8), ch),
682 cpc_readb(falcbase + F_REG((TTR1 + timeslot / 8), ch)) |
683 (0x80 >> (timeslot & 0x07)));
684 cpc_writeb(falcbase + F_REG((RTR1 + timeslot / 8), ch),
685 cpc_readb(falcbase + F_REG((RTR1 + timeslot / 8), ch)) |
686 (0x80 >> (timeslot & 0x07)));
687 }
688
689 static void falc_close_timeslot(pc300_t * card, int ch, int timeslot)
690 {
691 void __iomem *falcbase = card->hw.falcbase;
692 u8 tshf = card->chan[ch].falc.offset;
693
694 cpc_writeb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch),
695 cpc_readb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch)) |
696 (0x80 >> ((timeslot - tshf) & 0x07)));
697 cpc_writeb(falcbase + F_REG((TTR1 + timeslot / 8), ch),
698 cpc_readb(falcbase + F_REG((TTR1 + timeslot / 8), ch)) &
699 ~(0x80 >> (timeslot & 0x07)));
700 cpc_writeb(falcbase + F_REG((RTR1 + timeslot / 8), ch),
701 cpc_readb(falcbase + F_REG((RTR1 + timeslot / 8), ch)) &
702 ~(0x80 >> (timeslot & 0x07)));
703 }
704
705 static void falc_close_all_timeslots(pc300_t * card, int ch)
706 {
707 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
708 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
709 void __iomem *falcbase = card->hw.falcbase;
710
711 cpc_writeb(falcbase + F_REG(ICB1, ch), 0xff);
712 cpc_writeb(falcbase + F_REG(TTR1, ch), 0);
713 cpc_writeb(falcbase + F_REG(RTR1, ch), 0);
714 cpc_writeb(falcbase + F_REG(ICB2, ch), 0xff);
715 cpc_writeb(falcbase + F_REG(TTR2, ch), 0);
716 cpc_writeb(falcbase + F_REG(RTR2, ch), 0);
717 cpc_writeb(falcbase + F_REG(ICB3, ch), 0xff);
718 cpc_writeb(falcbase + F_REG(TTR3, ch), 0);
719 cpc_writeb(falcbase + F_REG(RTR3, ch), 0);
720 if (conf->media == IF_IFACE_E1) {
721 cpc_writeb(falcbase + F_REG(ICB4, ch), 0xff);
722 cpc_writeb(falcbase + F_REG(TTR4, ch), 0);
723 cpc_writeb(falcbase + F_REG(RTR4, ch), 0);
724 }
725 }
726
727 static void falc_open_all_timeslots(pc300_t * card, int ch)
728 {
729 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
730 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
731 void __iomem *falcbase = card->hw.falcbase;
732
733 cpc_writeb(falcbase + F_REG(ICB1, ch), 0);
734 if (conf->fr_mode == PC300_FR_UNFRAMED) {
735 cpc_writeb(falcbase + F_REG(TTR1, ch), 0xff);
736 cpc_writeb(falcbase + F_REG(RTR1, ch), 0xff);
737 } else {
738 /* Timeslot 0 is never enabled */
739 cpc_writeb(falcbase + F_REG(TTR1, ch), 0x7f);
740 cpc_writeb(falcbase + F_REG(RTR1, ch), 0x7f);
741 }
742 cpc_writeb(falcbase + F_REG(ICB2, ch), 0);
743 cpc_writeb(falcbase + F_REG(TTR2, ch), 0xff);
744 cpc_writeb(falcbase + F_REG(RTR2, ch), 0xff);
745 cpc_writeb(falcbase + F_REG(ICB3, ch), 0);
746 cpc_writeb(falcbase + F_REG(TTR3, ch), 0xff);
747 cpc_writeb(falcbase + F_REG(RTR3, ch), 0xff);
748 if (conf->media == IF_IFACE_E1) {
749 cpc_writeb(falcbase + F_REG(ICB4, ch), 0);
750 cpc_writeb(falcbase + F_REG(TTR4, ch), 0xff);
751 cpc_writeb(falcbase + F_REG(RTR4, ch), 0xff);
752 } else {
753 cpc_writeb(falcbase + F_REG(ICB4, ch), 0xff);
754 cpc_writeb(falcbase + F_REG(TTR4, ch), 0x80);
755 cpc_writeb(falcbase + F_REG(RTR4, ch), 0x80);
756 }
757 }
758
759 static void falc_init_timeslot(pc300_t * card, int ch)
760 {
761 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
762 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
763 falc_t *pfalc = (falc_t *) & chan->falc;
764 int tslot;
765
766 for (tslot = 0; tslot < pfalc->num_channels; tslot++) {
767 if (conf->tslot_bitmap & (1 << tslot)) {
768 // Channel enabled
769 falc_open_timeslot(card, ch, tslot + 1);
770 } else {
771 // Channel disabled
772 falc_close_timeslot(card, ch, tslot + 1);
773 }
774 }
775 }
776
777 static void falc_enable_comm(pc300_t * card, int ch)
778 {
779 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
780 falc_t *pfalc = (falc_t *) & chan->falc;
781
782 if (pfalc->full_bandwidth) {
783 falc_open_all_timeslots(card, ch);
784 } else {
785 falc_init_timeslot(card, ch);
786 }
787 // CTS/DCD ON
788 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
789 cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) &
790 ~((CPLD_REG1_FALC_DCD | CPLD_REG1_FALC_CTS) << (2 * ch)));
791 }
792
793 static void falc_disable_comm(pc300_t * card, int ch)
794 {
795 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
796 falc_t *pfalc = (falc_t *) & chan->falc;
797
798 if (pfalc->loop_active != 2) {
799 falc_close_all_timeslots(card, ch);
800 }
801 // CTS/DCD OFF
802 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
803 cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) |
804 ((CPLD_REG1_FALC_DCD | CPLD_REG1_FALC_CTS) << (2 * ch)));
805 }
806
807 static void falc_init_t1(pc300_t * card, int ch)
808 {
809 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
810 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
811 falc_t *pfalc = (falc_t *) & chan->falc;
812 void __iomem *falcbase = card->hw.falcbase;
813 u8 dja = (ch ? (LIM2_DJA2 | LIM2_DJA1) : 0);
814
815 /* Switch to T1 mode (PCM 24) */
816 cpc_writeb(falcbase + F_REG(FMR1, ch), FMR1_PMOD);
817
818 /* Wait 20 us for setup */
819 udelay(20);
820
821 /* Transmit Buffer Size (1 frame) */
822 cpc_writeb(falcbase + F_REG(SIC1, ch), SIC1_XBS0);
823
824 /* Clock mode */
825 if (conf->phys_settings.clock_type == CLOCK_INT) { /* Master mode */
826 cpc_writeb(falcbase + F_REG(LIM0, ch),
827 cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_MAS);
828 } else { /* Slave mode */
829 cpc_writeb(falcbase + F_REG(LIM0, ch),
830 cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_MAS);
831 cpc_writeb(falcbase + F_REG(LOOP, ch),
832 cpc_readb(falcbase + F_REG(LOOP, ch)) & ~LOOP_RTM);
833 }
834
835 cpc_writeb(falcbase + F_REG(IPC, ch), IPC_SCI);
836 cpc_writeb(falcbase + F_REG(FMR0, ch),
837 cpc_readb(falcbase + F_REG(FMR0, ch)) &
838 ~(FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1));
839
840 switch (conf->lcode) {
841 case PC300_LC_AMI:
842 cpc_writeb(falcbase + F_REG(FMR0, ch),
843 cpc_readb(falcbase + F_REG(FMR0, ch)) |
844 FMR0_XC1 | FMR0_RC1);
845 /* Clear Channel register to ON for all channels */
846 cpc_writeb(falcbase + F_REG(CCB1, ch), 0xff);
847 cpc_writeb(falcbase + F_REG(CCB2, ch), 0xff);
848 cpc_writeb(falcbase + F_REG(CCB3, ch), 0xff);
849 break;
850
851 case PC300_LC_B8ZS:
852 cpc_writeb(falcbase + F_REG(FMR0, ch),
853 cpc_readb(falcbase + F_REG(FMR0, ch)) |
854 FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1);
855 break;
856
857 case PC300_LC_NRZ:
858 cpc_writeb(falcbase + F_REG(FMR0, ch),
859 cpc_readb(falcbase + F_REG(FMR0, ch)) | 0x00);
860 break;
861 }
862
863 cpc_writeb(falcbase + F_REG(LIM0, ch),
864 cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_ELOS);
865 cpc_writeb(falcbase + F_REG(LIM0, ch),
866 cpc_readb(falcbase + F_REG(LIM0, ch)) & ~(LIM0_SCL1 | LIM0_SCL0));
867 /* Set interface mode to 2 MBPS */
868 cpc_writeb(falcbase + F_REG(FMR1, ch),
869 cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_IMOD);
870
871 switch (conf->fr_mode) {
872 case PC300_FR_ESF:
873 pfalc->multiframe_mode = 0;
874 cpc_writeb(falcbase + F_REG(FMR4, ch),
875 cpc_readb(falcbase + F_REG(FMR4, ch)) | FMR4_FM1);
876 cpc_writeb(falcbase + F_REG(FMR1, ch),
877 cpc_readb(falcbase + F_REG(FMR1, ch)) |
878 FMR1_CRC | FMR1_EDL);
879 cpc_writeb(falcbase + F_REG(XDL1, ch), 0);
880 cpc_writeb(falcbase + F_REG(XDL2, ch), 0);
881 cpc_writeb(falcbase + F_REG(XDL3, ch), 0);
882 cpc_writeb(falcbase + F_REG(FMR0, ch),
883 cpc_readb(falcbase + F_REG(FMR0, ch)) & ~FMR0_SRAF);
884 cpc_writeb(falcbase + F_REG(FMR2, ch),
885 cpc_readb(falcbase + F_REG(FMR2,ch)) | FMR2_MCSP | FMR2_SSP);
886 break;
887
888 case PC300_FR_D4:
889 pfalc->multiframe_mode = 1;
890 cpc_writeb(falcbase + F_REG(FMR4, ch),
891 cpc_readb(falcbase + F_REG(FMR4, ch)) &
892 ~(FMR4_FM1 | FMR4_FM0));
893 cpc_writeb(falcbase + F_REG(FMR0, ch),
894 cpc_readb(falcbase + F_REG(FMR0, ch)) | FMR0_SRAF);
895 cpc_writeb(falcbase + F_REG(FMR2, ch),
896 cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_SSP);
897 break;
898 }
899
900 /* Enable Automatic Resynchronization */
901 cpc_writeb(falcbase + F_REG(FMR4, ch),
902 cpc_readb(falcbase + F_REG(FMR4, ch)) | FMR4_AUTO);
903
904 /* Transmit Automatic Remote Alarm */
905 cpc_writeb(falcbase + F_REG(FMR2, ch),
906 cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_AXRA);
907
908 /* Channel translation mode 1 : one to one */
909 cpc_writeb(falcbase + F_REG(FMR1, ch),
910 cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_CTM);
911
912 /* No signaling */
913 cpc_writeb(falcbase + F_REG(FMR1, ch),
914 cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_SIGM);
915 cpc_writeb(falcbase + F_REG(FMR5, ch),
916 cpc_readb(falcbase + F_REG(FMR5, ch)) &
917 ~(FMR5_EIBR | FMR5_SRS));
918 cpc_writeb(falcbase + F_REG(CCR1, ch), 0);
919
920 cpc_writeb(falcbase + F_REG(LIM1, ch),
921 cpc_readb(falcbase + F_REG(LIM1, ch)) | LIM1_RIL0 | LIM1_RIL1);
922
923 switch (conf->lbo) {
924 /* Provides proper Line Build Out */
925 case PC300_LBO_0_DB:
926 cpc_writeb(falcbase + F_REG(LIM2, ch), (LIM2_LOS1 | dja));
927 cpc_writeb(falcbase + F_REG(XPM0, ch), 0x5a);
928 cpc_writeb(falcbase + F_REG(XPM1, ch), 0x8f);
929 cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20);
930 break;
931 case PC300_LBO_7_5_DB:
932 cpc_writeb(falcbase + F_REG(LIM2, ch), (0x40 | LIM2_LOS1 | dja));
933 cpc_writeb(falcbase + F_REG(XPM0, ch), 0x11);
934 cpc_writeb(falcbase + F_REG(XPM1, ch), 0x02);
935 cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20);
936 break;
937 case PC300_LBO_15_DB:
938 cpc_writeb(falcbase + F_REG(LIM2, ch), (0x80 | LIM2_LOS1 | dja));
939 cpc_writeb(falcbase + F_REG(XPM0, ch), 0x8e);
940 cpc_writeb(falcbase + F_REG(XPM1, ch), 0x01);
941 cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20);
942 break;
943 case PC300_LBO_22_5_DB:
944 cpc_writeb(falcbase + F_REG(LIM2, ch), (0xc0 | LIM2_LOS1 | dja));
945 cpc_writeb(falcbase + F_REG(XPM0, ch), 0x09);
946 cpc_writeb(falcbase + F_REG(XPM1, ch), 0x01);
947 cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20);
948 break;
949 }
950
951 /* Transmit Clock-Slot Offset */
952 cpc_writeb(falcbase + F_REG(XC0, ch),
953 cpc_readb(falcbase + F_REG(XC0, ch)) | 0x01);
954 /* Transmit Time-slot Offset */
955 cpc_writeb(falcbase + F_REG(XC1, ch), 0x3e);
956 /* Receive Clock-Slot offset */
957 cpc_writeb(falcbase + F_REG(RC0, ch), 0x05);
958 /* Receive Time-slot offset */
959 cpc_writeb(falcbase + F_REG(RC1, ch), 0x00);
960
961 /* LOS Detection after 176 consecutive 0s */
962 cpc_writeb(falcbase + F_REG(PCDR, ch), 0x0a);
963 /* LOS Recovery after 22 ones in the time window of PCD */
964 cpc_writeb(falcbase + F_REG(PCRR, ch), 0x15);
965
966 cpc_writeb(falcbase + F_REG(IDLE, ch), 0x7f);
967
968 if (conf->fr_mode == PC300_FR_ESF_JAPAN) {
969 cpc_writeb(falcbase + F_REG(RC1, ch),
970 cpc_readb(falcbase + F_REG(RC1, ch)) | 0x80);
971 }
972
973 falc_close_all_timeslots(card, ch);
974 }
975
976 static void falc_init_e1(pc300_t * card, int ch)
977 {
978 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
979 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
980 falc_t *pfalc = (falc_t *) & chan->falc;
981 void __iomem *falcbase = card->hw.falcbase;
982 u8 dja = (ch ? (LIM2_DJA2 | LIM2_DJA1) : 0);
983
984 /* Switch to E1 mode (PCM 30) */
985 cpc_writeb(falcbase + F_REG(FMR1, ch),
986 cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_PMOD);
987
988 /* Clock mode */
989 if (conf->phys_settings.clock_type == CLOCK_INT) { /* Master mode */
990 cpc_writeb(falcbase + F_REG(LIM0, ch),
991 cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_MAS);
992 } else { /* Slave mode */
993 cpc_writeb(falcbase + F_REG(LIM0, ch),
994 cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_MAS);
995 }
996 cpc_writeb(falcbase + F_REG(LOOP, ch),
997 cpc_readb(falcbase + F_REG(LOOP, ch)) & ~LOOP_SFM);
998
999 cpc_writeb(falcbase + F_REG(IPC, ch), IPC_SCI);
1000 cpc_writeb(falcbase + F_REG(FMR0, ch),
1001 cpc_readb(falcbase + F_REG(FMR0, ch)) &
1002 ~(FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1));
1003
1004 switch (conf->lcode) {
1005 case PC300_LC_AMI:
1006 cpc_writeb(falcbase + F_REG(FMR0, ch),
1007 cpc_readb(falcbase + F_REG(FMR0, ch)) |
1008 FMR0_XC1 | FMR0_RC1);
1009 break;
1010
1011 case PC300_LC_HDB3:
1012 cpc_writeb(falcbase + F_REG(FMR0, ch),
1013 cpc_readb(falcbase + F_REG(FMR0, ch)) |
1014 FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1);
1015 break;
1016
1017 case PC300_LC_NRZ:
1018 break;
1019 }
1020
1021 cpc_writeb(falcbase + F_REG(LIM0, ch),
1022 cpc_readb(falcbase + F_REG(LIM0, ch)) & ~(LIM0_SCL1 | LIM0_SCL0));
1023 /* Set interface mode to 2 MBPS */
1024 cpc_writeb(falcbase + F_REG(FMR1, ch),
1025 cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_IMOD);
1026
1027 cpc_writeb(falcbase + F_REG(XPM0, ch), 0x18);
1028 cpc_writeb(falcbase + F_REG(XPM1, ch), 0x03);
1029 cpc_writeb(falcbase + F_REG(XPM2, ch), 0x00);
1030
1031 switch (conf->fr_mode) {
1032 case PC300_FR_MF_CRC4:
1033 pfalc->multiframe_mode = 1;
1034 cpc_writeb(falcbase + F_REG(FMR1, ch),
1035 cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_XFS);
1036 cpc_writeb(falcbase + F_REG(FMR2, ch),
1037 cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_RFS1);
1038 cpc_writeb(falcbase + F_REG(FMR2, ch),
1039 cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_RFS0);
1040 cpc_writeb(falcbase + F_REG(FMR3, ch),
1041 cpc_readb(falcbase + F_REG(FMR3, ch)) & ~FMR3_EXTIW);
1042
1043 /* MultiFrame Resynchronization */
1044 cpc_writeb(falcbase + F_REG(FMR1, ch),
1045 cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_MFCS);
1046
1047 /* Automatic Loss of Multiframe > 914 CRC errors */
1048 cpc_writeb(falcbase + F_REG(FMR2, ch),
1049 cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_ALMF);
1050
1051 /* S1 and SI1/SI2 spare Bits set to 1 */
1052 cpc_writeb(falcbase + F_REG(XSP, ch),
1053 cpc_readb(falcbase + F_REG(XSP, ch)) & ~XSP_AXS);
1054 cpc_writeb(falcbase + F_REG(XSP, ch),
1055 cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_EBP);
1056 cpc_writeb(falcbase + F_REG(XSP, ch),
1057 cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_XS13 | XSP_XS15);
1058
1059 /* Automatic Force Resynchronization */
1060 cpc_writeb(falcbase + F_REG(FMR1, ch),
1061 cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_AFR);
1062
1063 /* Transmit Automatic Remote Alarm */
1064 cpc_writeb(falcbase + F_REG(FMR2, ch),
1065 cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_AXRA);
1066
1067 /* Transmit Spare Bits for National Use (Y, Sn, Sa) */
1068 cpc_writeb(falcbase + F_REG(XSW, ch),
1069 cpc_readb(falcbase + F_REG(XSW, ch)) |
1070 XSW_XY0 | XSW_XY1 | XSW_XY2 | XSW_XY3 | XSW_XY4);
1071 break;
1072
1073 case PC300_FR_MF_NON_CRC4:
1074 case PC300_FR_D4:
1075 pfalc->multiframe_mode = 0;
1076 cpc_writeb(falcbase + F_REG(FMR1, ch),
1077 cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_XFS);
1078 cpc_writeb(falcbase + F_REG(FMR2, ch),
1079 cpc_readb(falcbase + F_REG(FMR2, ch)) &
1080 ~(FMR2_RFS1 | FMR2_RFS0));
1081 cpc_writeb(falcbase + F_REG(XSW, ch),
1082 cpc_readb(falcbase + F_REG(XSW, ch)) | XSW_XSIS);
1083 cpc_writeb(falcbase + F_REG(XSP, ch),
1084 cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_XSIF);
1085
1086 /* Automatic Force Resynchronization */
1087 cpc_writeb(falcbase + F_REG(FMR1, ch),
1088 cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_AFR);
1089
1090 /* Transmit Automatic Remote Alarm */
1091 cpc_writeb(falcbase + F_REG(FMR2, ch),
1092 cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_AXRA);
1093
1094 /* Transmit Spare Bits for National Use (Y, Sn, Sa) */
1095 cpc_writeb(falcbase + F_REG(XSW, ch),
1096 cpc_readb(falcbase + F_REG(XSW, ch)) |
1097 XSW_XY0 | XSW_XY1 | XSW_XY2 | XSW_XY3 | XSW_XY4);
1098 break;
1099
1100 case PC300_FR_UNFRAMED:
1101 pfalc->multiframe_mode = 0;
1102 cpc_writeb(falcbase + F_REG(FMR1, ch),
1103 cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_XFS);
1104 cpc_writeb(falcbase + F_REG(FMR2, ch),
1105 cpc_readb(falcbase + F_REG(FMR2, ch)) &
1106 ~(FMR2_RFS1 | FMR2_RFS0));
1107 cpc_writeb(falcbase + F_REG(XSP, ch),
1108 cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_TT0);
1109 cpc_writeb(falcbase + F_REG(XSW, ch),
1110 cpc_readb(falcbase + F_REG(XSW, ch)) &
1111 ~(XSW_XTM|XSW_XY0|XSW_XY1|XSW_XY2|XSW_XY3|XSW_XY4));
1112 cpc_writeb(falcbase + F_REG(TSWM, ch), 0xff);
1113 cpc_writeb(falcbase + F_REG(FMR2, ch),
1114 cpc_readb(falcbase + F_REG(FMR2, ch)) |
1115 (FMR2_RTM | FMR2_DAIS));
1116 cpc_writeb(falcbase + F_REG(FMR2, ch),
1117 cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_AXRA);
1118 cpc_writeb(falcbase + F_REG(FMR1, ch),
1119 cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_AFR);
1120 pfalc->sync = 1;
1121 cpc_writeb(falcbase + card->hw.cpld_reg2,
1122 cpc_readb(falcbase + card->hw.cpld_reg2) |
1123 (CPLD_REG2_FALC_LED2 << (2 * ch)));
1124 break;
1125 }
1126
1127 /* No signaling */
1128 cpc_writeb(falcbase + F_REG(XSP, ch),
1129 cpc_readb(falcbase + F_REG(XSP, ch)) & ~XSP_CASEN);
1130 cpc_writeb(falcbase + F_REG(CCR1, ch), 0);
1131
1132 cpc_writeb(falcbase + F_REG(LIM1, ch),
1133 cpc_readb(falcbase + F_REG(LIM1, ch)) | LIM1_RIL0 | LIM1_RIL1);
1134 cpc_writeb(falcbase + F_REG(LIM2, ch), (LIM2_LOS1 | dja));
1135
1136 /* Transmit Clock-Slot Offset */
1137 cpc_writeb(falcbase + F_REG(XC0, ch),
1138 cpc_readb(falcbase + F_REG(XC0, ch)) | 0x01);
1139 /* Transmit Time-slot Offset */
1140 cpc_writeb(falcbase + F_REG(XC1, ch), 0x3e);
1141 /* Receive Clock-Slot offset */
1142 cpc_writeb(falcbase + F_REG(RC0, ch), 0x05);
1143 /* Receive Time-slot offset */
1144 cpc_writeb(falcbase + F_REG(RC1, ch), 0x00);
1145
1146 /* LOS Detection after 176 consecutive 0s */
1147 cpc_writeb(falcbase + F_REG(PCDR, ch), 0x0a);
1148 /* LOS Recovery after 22 ones in the time window of PCD */
1149 cpc_writeb(falcbase + F_REG(PCRR, ch), 0x15);
1150
1151 cpc_writeb(falcbase + F_REG(IDLE, ch), 0x7f);
1152
1153 falc_close_all_timeslots(card, ch);
1154 }
1155
1156 static void falc_init_hdlc(pc300_t * card, int ch)
1157 {
1158 void __iomem *falcbase = card->hw.falcbase;
1159 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1160 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1161
1162 /* Enable transparent data transfer */
1163 if (conf->fr_mode == PC300_FR_UNFRAMED) {
1164 cpc_writeb(falcbase + F_REG(MODE, ch), 0);
1165 } else {
1166 cpc_writeb(falcbase + F_REG(MODE, ch),
1167 cpc_readb(falcbase + F_REG(MODE, ch)) |
1168 (MODE_HRAC | MODE_MDS2));
1169 cpc_writeb(falcbase + F_REG(RAH2, ch), 0xff);
1170 cpc_writeb(falcbase + F_REG(RAH1, ch), 0xff);
1171 cpc_writeb(falcbase + F_REG(RAL2, ch), 0xff);
1172 cpc_writeb(falcbase + F_REG(RAL1, ch), 0xff);
1173 }
1174
1175 /* Tx/Rx reset */
1176 falc_issue_cmd(card, ch, CMDR_RRES | CMDR_XRES | CMDR_SRES);
1177
1178 /* Enable interrupt sources */
1179 falc_intr_enable(card, ch);
1180 }
1181
1182 static void te_config(pc300_t * card, int ch)
1183 {
1184 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1185 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1186 falc_t *pfalc = (falc_t *) & chan->falc;
1187 void __iomem *falcbase = card->hw.falcbase;
1188 u8 dummy;
1189 unsigned long flags;
1190
1191 memset(pfalc, 0, sizeof(falc_t));
1192 switch (conf->media) {
1193 case IF_IFACE_T1:
1194 pfalc->num_channels = NUM_OF_T1_CHANNELS;
1195 pfalc->offset = 1;
1196 break;
1197 case IF_IFACE_E1:
1198 pfalc->num_channels = NUM_OF_E1_CHANNELS;
1199 pfalc->offset = 0;
1200 break;
1201 }
1202 if (conf->tslot_bitmap == 0xffffffffUL)
1203 pfalc->full_bandwidth = 1;
1204 else
1205 pfalc->full_bandwidth = 0;
1206
1207 CPC_LOCK(card, flags);
1208 /* Reset the FALC chip */
1209 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
1210 cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) |
1211 (CPLD_REG1_FALC_RESET << (2 * ch)));
1212 udelay(10000);
1213 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
1214 cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) &
1215 ~(CPLD_REG1_FALC_RESET << (2 * ch)));
1216
1217 if (conf->media == IF_IFACE_T1) {
1218 falc_init_t1(card, ch);
1219 } else {
1220 falc_init_e1(card, ch);
1221 }
1222 falc_init_hdlc(card, ch);
1223 if (conf->rx_sens == PC300_RX_SENS_SH) {
1224 cpc_writeb(falcbase + F_REG(LIM0, ch),
1225 cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_EQON);
1226 } else {
1227 cpc_writeb(falcbase + F_REG(LIM0, ch),
1228 cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_EQON);
1229 }
1230 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
1231 cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) |
1232 ((CPLD_REG2_FALC_TX_CLK | CPLD_REG2_FALC_RX_CLK) << (2 * ch)));
1233
1234 /* Clear all interrupt registers */
1235 dummy = cpc_readb(falcbase + F_REG(FISR0, ch)) +
1236 cpc_readb(falcbase + F_REG(FISR1, ch)) +
1237 cpc_readb(falcbase + F_REG(FISR2, ch)) +
1238 cpc_readb(falcbase + F_REG(FISR3, ch));
1239 CPC_UNLOCK(card, flags);
1240 }
1241
1242 static void falc_check_status(pc300_t * card, int ch, unsigned char frs0)
1243 {
1244 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1245 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1246 falc_t *pfalc = (falc_t *) & chan->falc;
1247 void __iomem *falcbase = card->hw.falcbase;
1248
1249 /* Verify LOS */
1250 if (frs0 & FRS0_LOS) {
1251 if (!pfalc->red_alarm) {
1252 pfalc->red_alarm = 1;
1253 pfalc->los++;
1254 if (!pfalc->blue_alarm) {
1255 // EVENT_FALC_ABNORMAL
1256 if (conf->media == IF_IFACE_T1) {
1257 /* Disable this interrupt as it may otherwise interfere
1258 * with other working boards. */
1259 cpc_writeb(falcbase + F_REG(IMR0, ch),
1260 cpc_readb(falcbase + F_REG(IMR0, ch))
1261 | IMR0_PDEN);
1262 }
1263 falc_disable_comm(card, ch);
1264 // EVENT_FALC_ABNORMAL
1265 }
1266 }
1267 } else {
1268 if (pfalc->red_alarm) {
1269 pfalc->red_alarm = 0;
1270 pfalc->losr++;
1271 }
1272 }
1273
1274 if (conf->fr_mode != PC300_FR_UNFRAMED) {
1275 /* Verify AIS alarm */
1276 if (frs0 & FRS0_AIS) {
1277 if (!pfalc->blue_alarm) {
1278 pfalc->blue_alarm = 1;
1279 pfalc->ais++;
1280 // EVENT_AIS
1281 if (conf->media == IF_IFACE_T1) {
1282 /* Disable this interrupt as it may otherwise interfere with other working boards. */
1283 cpc_writeb(falcbase + F_REG(IMR0, ch),
1284 cpc_readb(falcbase + F_REG(IMR0, ch)) | IMR0_PDEN);
1285 }
1286 falc_disable_comm(card, ch);
1287 // EVENT_AIS
1288 }
1289 } else {
1290 pfalc->blue_alarm = 0;
1291 }
1292
1293 /* Verify LFA */
1294 if (frs0 & FRS0_LFA) {
1295 if (!pfalc->loss_fa) {
1296 pfalc->loss_fa = 1;
1297 pfalc->lfa++;
1298 if (!pfalc->blue_alarm && !pfalc->red_alarm) {
1299 // EVENT_FALC_ABNORMAL
1300 if (conf->media == IF_IFACE_T1) {
1301 /* Disable this interrupt as it may otherwise
1302 * interfere with other working boards. */
1303 cpc_writeb(falcbase + F_REG(IMR0, ch),
1304 cpc_readb(falcbase + F_REG(IMR0, ch))
1305 | IMR0_PDEN);
1306 }
1307 falc_disable_comm(card, ch);
1308 // EVENT_FALC_ABNORMAL
1309 }
1310 }
1311 } else {
1312 if (pfalc->loss_fa) {
1313 pfalc->loss_fa = 0;
1314 pfalc->farec++;
1315 }
1316 }
1317
1318 /* Verify LMFA */
1319 if (pfalc->multiframe_mode && (frs0 & FRS0_LMFA)) {
1320 /* D4 or CRC4 frame mode */
1321 if (!pfalc->loss_mfa) {
1322 pfalc->loss_mfa = 1;
1323 pfalc->lmfa++;
1324 if (!pfalc->blue_alarm && !pfalc->red_alarm &&
1325 !pfalc->loss_fa) {
1326 // EVENT_FALC_ABNORMAL
1327 if (conf->media == IF_IFACE_T1) {
1328 /* Disable this interrupt as it may otherwise
1329 * interfere with other working boards. */
1330 cpc_writeb(falcbase + F_REG(IMR0, ch),
1331 cpc_readb(falcbase + F_REG(IMR0, ch))
1332 | IMR0_PDEN);
1333 }
1334 falc_disable_comm(card, ch);
1335 // EVENT_FALC_ABNORMAL
1336 }
1337 }
1338 } else {
1339 pfalc->loss_mfa = 0;
1340 }
1341
1342 /* Verify Remote Alarm */
1343 if (frs0 & FRS0_RRA) {
1344 if (!pfalc->yellow_alarm) {
1345 pfalc->yellow_alarm = 1;
1346 pfalc->rai++;
1347 if (pfalc->sync) {
1348 // EVENT_RAI
1349 falc_disable_comm(card, ch);
1350 // EVENT_RAI
1351 }
1352 }
1353 } else {
1354 pfalc->yellow_alarm = 0;
1355 }
1356 } /* if !PC300_UNFRAMED */
1357
1358 if (pfalc->red_alarm || pfalc->loss_fa ||
1359 pfalc->loss_mfa || pfalc->blue_alarm) {
1360 if (pfalc->sync) {
1361 pfalc->sync = 0;
1362 chan->d.line_off++;
1363 cpc_writeb(falcbase + card->hw.cpld_reg2,
1364 cpc_readb(falcbase + card->hw.cpld_reg2) &
1365 ~(CPLD_REG2_FALC_LED2 << (2 * ch)));
1366 }
1367 } else {
1368 if (!pfalc->sync) {
1369 pfalc->sync = 1;
1370 chan->d.line_on++;
1371 cpc_writeb(falcbase + card->hw.cpld_reg2,
1372 cpc_readb(falcbase + card->hw.cpld_reg2) |
1373 (CPLD_REG2_FALC_LED2 << (2 * ch)));
1374 }
1375 }
1376
1377 if (pfalc->sync && !pfalc->yellow_alarm) {
1378 if (!pfalc->active) {
1379 // EVENT_FALC_NORMAL
1380 if (pfalc->loop_active) {
1381 return;
1382 }
1383 if (conf->media == IF_IFACE_T1) {
1384 cpc_writeb(falcbase + F_REG(IMR0, ch),
1385 cpc_readb(falcbase + F_REG(IMR0, ch)) & ~IMR0_PDEN);
1386 }
1387 falc_enable_comm(card, ch);
1388 // EVENT_FALC_NORMAL
1389 pfalc->active = 1;
1390 }
1391 } else {
1392 if (pfalc->active) {
1393 pfalc->active = 0;
1394 }
1395 }
1396 }
1397
1398 static void falc_update_stats(pc300_t * card, int ch)
1399 {
1400 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1401 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1402 falc_t *pfalc = (falc_t *) & chan->falc;
1403 void __iomem *falcbase = card->hw.falcbase;
1404 u16 counter;
1405
1406 counter = cpc_readb(falcbase + F_REG(FECL, ch));
1407 counter |= cpc_readb(falcbase + F_REG(FECH, ch)) << 8;
1408 pfalc->fec += counter;
1409
1410 counter = cpc_readb(falcbase + F_REG(CVCL, ch));
1411 counter |= cpc_readb(falcbase + F_REG(CVCH, ch)) << 8;
1412 pfalc->cvc += counter;
1413
1414 counter = cpc_readb(falcbase + F_REG(CECL, ch));
1415 counter |= cpc_readb(falcbase + F_REG(CECH, ch)) << 8;
1416 pfalc->cec += counter;
1417
1418 counter = cpc_readb(falcbase + F_REG(EBCL, ch));
1419 counter |= cpc_readb(falcbase + F_REG(EBCH, ch)) << 8;
1420 pfalc->ebc += counter;
1421
1422 if (cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_EPRM) {
1423 mdelay(10);
1424 counter = cpc_readb(falcbase + F_REG(BECL, ch));
1425 counter |= cpc_readb(falcbase + F_REG(BECH, ch)) << 8;
1426 pfalc->bec += counter;
1427
1428 if (((conf->media == IF_IFACE_T1) &&
1429 (cpc_readb(falcbase + F_REG(FRS1, ch)) & FRS1_LLBAD) &&
1430 (!(cpc_readb(falcbase + F_REG(FRS1, ch)) & FRS1_PDEN)))
1431 ||
1432 ((conf->media == IF_IFACE_E1) &&
1433 (cpc_readb(falcbase + F_REG(RSP, ch)) & RSP_LLBAD))) {
1434 pfalc->prbs = 2;
1435 } else {
1436 pfalc->prbs = 1;
1437 }
1438 }
1439 }
1440
1441 /*----------------------------------------------------------------------------
1442 * falc_remote_loop
1443 *----------------------------------------------------------------------------
1444 * Description: In the remote loopback mode the clock and data recovered
1445 * from the line inputs RL1/2 or RDIP/RDIN are routed back
1446 * to the line outputs XL1/2 or XDOP/XDON via the analog
1447 * transmitter. As in normal mode they are processsed by
1448 * the synchronizer and then sent to the system interface.
1449 *----------------------------------------------------------------------------
1450 */
1451 static void falc_remote_loop(pc300_t * card, int ch, int loop_on)
1452 {
1453 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1454 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1455 falc_t *pfalc = (falc_t *) & chan->falc;
1456 void __iomem *falcbase = card->hw.falcbase;
1457
1458 if (loop_on) {
1459 // EVENT_FALC_ABNORMAL
1460 if (conf->media == IF_IFACE_T1) {
1461 /* Disable this interrupt as it may otherwise interfere with
1462 * other working boards. */
1463 cpc_writeb(falcbase + F_REG(IMR0, ch),
1464 cpc_readb(falcbase + F_REG(IMR0, ch)) | IMR0_PDEN);
1465 }
1466 falc_disable_comm(card, ch);
1467 // EVENT_FALC_ABNORMAL
1468 cpc_writeb(falcbase + F_REG(LIM1, ch),
1469 cpc_readb(falcbase + F_REG(LIM1, ch)) | LIM1_RL);
1470 pfalc->loop_active = 1;
1471 } else {
1472 cpc_writeb(falcbase + F_REG(LIM1, ch),
1473 cpc_readb(falcbase + F_REG(LIM1, ch)) & ~LIM1_RL);
1474 pfalc->sync = 0;
1475 cpc_writeb(falcbase + card->hw.cpld_reg2,
1476 cpc_readb(falcbase + card->hw.cpld_reg2) &
1477 ~(CPLD_REG2_FALC_LED2 << (2 * ch)));
1478 pfalc->active = 0;
1479 falc_issue_cmd(card, ch, CMDR_XRES);
1480 pfalc->loop_active = 0;
1481 }
1482 }
1483
1484 /*----------------------------------------------------------------------------
1485 * falc_local_loop
1486 *----------------------------------------------------------------------------
1487 * Description: The local loopback mode disconnects the receive lines
1488 * RL1/RL2 resp. RDIP/RDIN from the receiver. Instead of the
1489 * signals coming from the line the data provided by system
1490 * interface are routed through the analog receiver back to
1491 * the system interface. The unipolar bit stream will be
1492 * undisturbed transmitted on the line. Receiver and transmitter
1493 * coding must be identical.
1494 *----------------------------------------------------------------------------
1495 */
1496 static void falc_local_loop(pc300_t * card, int ch, int loop_on)
1497 {
1498 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1499 falc_t *pfalc = (falc_t *) & chan->falc;
1500 void __iomem *falcbase = card->hw.falcbase;
1501
1502 if (loop_on) {
1503 cpc_writeb(falcbase + F_REG(LIM0, ch),
1504 cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_LL);
1505 pfalc->loop_active = 1;
1506 } else {
1507 cpc_writeb(falcbase + F_REG(LIM0, ch),
1508 cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_LL);
1509 pfalc->loop_active = 0;
1510 }
1511 }
1512
1513 /*----------------------------------------------------------------------------
1514 * falc_payload_loop
1515 *----------------------------------------------------------------------------
1516 * Description: This routine allows to enable/disable payload loopback.
1517 * When the payload loop is activated, the received 192 bits
1518 * of payload data will be looped back to the transmit
1519 * direction. The framing bits, CRC6 and DL bits are not
1520 * looped. They are originated by the FALC-LH transmitter.
1521 *----------------------------------------------------------------------------
1522 */
1523 static void falc_payload_loop(pc300_t * card, int ch, int loop_on)
1524 {
1525 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1526 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1527 falc_t *pfalc = (falc_t *) & chan->falc;
1528 void __iomem *falcbase = card->hw.falcbase;
1529
1530 if (loop_on) {
1531 // EVENT_FALC_ABNORMAL
1532 if (conf->media == IF_IFACE_T1) {
1533 /* Disable this interrupt as it may otherwise interfere with
1534 * other working boards. */
1535 cpc_writeb(falcbase + F_REG(IMR0, ch),
1536 cpc_readb(falcbase + F_REG(IMR0, ch)) | IMR0_PDEN);
1537 }
1538 falc_disable_comm(card, ch);
1539 // EVENT_FALC_ABNORMAL
1540 cpc_writeb(falcbase + F_REG(FMR2, ch),
1541 cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_PLB);
1542 if (conf->media == IF_IFACE_T1) {
1543 cpc_writeb(falcbase + F_REG(FMR4, ch),
1544 cpc_readb(falcbase + F_REG(FMR4, ch)) | FMR4_TM);
1545 } else {
1546 cpc_writeb(falcbase + F_REG(FMR5, ch),
1547 cpc_readb(falcbase + F_REG(FMR5, ch)) | XSP_TT0);
1548 }
1549 falc_open_all_timeslots(card, ch);
1550 pfalc->loop_active = 2;
1551 } else {
1552 cpc_writeb(falcbase + F_REG(FMR2, ch),
1553 cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_PLB);
1554 if (conf->media == IF_IFACE_T1) {
1555 cpc_writeb(falcbase + F_REG(FMR4, ch),
1556 cpc_readb(falcbase + F_REG(FMR4, ch)) & ~FMR4_TM);
1557 } else {
1558 cpc_writeb(falcbase + F_REG(FMR5, ch),
1559 cpc_readb(falcbase + F_REG(FMR5, ch)) & ~XSP_TT0);
1560 }
1561 pfalc->sync = 0;
1562 cpc_writeb(falcbase + card->hw.cpld_reg2,
1563 cpc_readb(falcbase + card->hw.cpld_reg2) &
1564 ~(CPLD_REG2_FALC_LED2 << (2 * ch)));
1565 pfalc->active = 0;
1566 falc_issue_cmd(card, ch, CMDR_XRES);
1567 pfalc->loop_active = 0;
1568 }
1569 }
1570
1571 /*----------------------------------------------------------------------------
1572 * turn_off_xlu
1573 *----------------------------------------------------------------------------
1574 * Description: Turns XLU bit off in the proper register
1575 *----------------------------------------------------------------------------
1576 */
1577 static void turn_off_xlu(pc300_t * card, int ch)
1578 {
1579 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1580 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1581 void __iomem *falcbase = card->hw.falcbase;
1582
1583 if (conf->media == IF_IFACE_T1) {
1584 cpc_writeb(falcbase + F_REG(FMR5, ch),
1585 cpc_readb(falcbase + F_REG(FMR5, ch)) & ~FMR5_XLU);
1586 } else {
1587 cpc_writeb(falcbase + F_REG(FMR3, ch),
1588 cpc_readb(falcbase + F_REG(FMR3, ch)) & ~FMR3_XLU);
1589 }
1590 }
1591
1592 /*----------------------------------------------------------------------------
1593 * turn_off_xld
1594 *----------------------------------------------------------------------------
1595 * Description: Turns XLD bit off in the proper register
1596 *----------------------------------------------------------------------------
1597 */
1598 static void turn_off_xld(pc300_t * card, int ch)
1599 {
1600 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1601 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1602 void __iomem *falcbase = card->hw.falcbase;
1603
1604 if (conf->media == IF_IFACE_T1) {
1605 cpc_writeb(falcbase + F_REG(FMR5, ch),
1606 cpc_readb(falcbase + F_REG(FMR5, ch)) & ~FMR5_XLD);
1607 } else {
1608 cpc_writeb(falcbase + F_REG(FMR3, ch),
1609 cpc_readb(falcbase + F_REG(FMR3, ch)) & ~FMR3_XLD);
1610 }
1611 }
1612
1613 /*----------------------------------------------------------------------------
1614 * falc_generate_loop_up_code
1615 *----------------------------------------------------------------------------
1616 * Description: This routine writes the proper FALC chip register in order
1617 * to generate a LOOP activation code over a T1/E1 line.
1618 *----------------------------------------------------------------------------
1619 */
1620 static void falc_generate_loop_up_code(pc300_t * card, int ch)
1621 {
1622 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1623 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1624 falc_t *pfalc = (falc_t *) & chan->falc;
1625 void __iomem *falcbase = card->hw.falcbase;
1626
1627 if (conf->media == IF_IFACE_T1) {
1628 cpc_writeb(falcbase + F_REG(FMR5, ch),
1629 cpc_readb(falcbase + F_REG(FMR5, ch)) | FMR5_XLU);
1630 } else {
1631 cpc_writeb(falcbase + F_REG(FMR3, ch),
1632 cpc_readb(falcbase + F_REG(FMR3, ch)) | FMR3_XLU);
1633 }
1634 // EVENT_FALC_ABNORMAL
1635 if (conf->media == IF_IFACE_T1) {
1636 /* Disable this interrupt as it may otherwise interfere with
1637 * other working boards. */
1638 cpc_writeb(falcbase + F_REG(IMR0, ch),
1639 cpc_readb(falcbase + F_REG(IMR0, ch)) | IMR0_PDEN);
1640 }
1641 falc_disable_comm(card, ch);
1642 // EVENT_FALC_ABNORMAL
1643 pfalc->loop_gen = 1;
1644 }
1645
1646 /*----------------------------------------------------------------------------
1647 * falc_generate_loop_down_code
1648 *----------------------------------------------------------------------------
1649 * Description: This routine writes the proper FALC chip register in order
1650 * to generate a LOOP deactivation code over a T1/E1 line.
1651 *----------------------------------------------------------------------------
1652 */
1653 static void falc_generate_loop_down_code(pc300_t * card, int ch)
1654 {
1655 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1656 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1657 falc_t *pfalc = (falc_t *) & chan->falc;
1658 void __iomem *falcbase = card->hw.falcbase;
1659
1660 if (conf->media == IF_IFACE_T1) {
1661 cpc_writeb(falcbase + F_REG(FMR5, ch),
1662 cpc_readb(falcbase + F_REG(FMR5, ch)) | FMR5_XLD);
1663 } else {
1664 cpc_writeb(falcbase + F_REG(FMR3, ch),
1665 cpc_readb(falcbase + F_REG(FMR3, ch)) | FMR3_XLD);
1666 }
1667 pfalc->sync = 0;
1668 cpc_writeb(falcbase + card->hw.cpld_reg2,
1669 cpc_readb(falcbase + card->hw.cpld_reg2) &
1670 ~(CPLD_REG2_FALC_LED2 << (2 * ch)));
1671 pfalc->active = 0;
1672 //? falc_issue_cmd(card, ch, CMDR_XRES);
1673 pfalc->loop_gen = 0;
1674 }
1675
1676 /*----------------------------------------------------------------------------
1677 * falc_pattern_test
1678 *----------------------------------------------------------------------------
1679 * Description: This routine generates a pattern code and checks
1680 * it on the reception side.
1681 *----------------------------------------------------------------------------
1682 */
1683 static void falc_pattern_test(pc300_t * card, int ch, unsigned int activate)
1684 {
1685 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1686 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1687 falc_t *pfalc = (falc_t *) & chan->falc;
1688 void __iomem *falcbase = card->hw.falcbase;
1689
1690 if (activate) {
1691 pfalc->prbs = 1;
1692 pfalc->bec = 0;
1693 if (conf->media == IF_IFACE_T1) {
1694 /* Disable local loop activation/deactivation detect */
1695 cpc_writeb(falcbase + F_REG(IMR3, ch),
1696 cpc_readb(falcbase + F_REG(IMR3, ch)) | IMR3_LLBSC);
1697 } else {
1698 /* Disable local loop activation/deactivation detect */
1699 cpc_writeb(falcbase + F_REG(IMR1, ch),
1700 cpc_readb(falcbase + F_REG(IMR1, ch)) | IMR1_LLBSC);
1701 }
1702 /* Activates generation and monitoring of PRBS
1703 * (Pseudo Random Bit Sequence) */
1704 cpc_writeb(falcbase + F_REG(LCR1, ch),
1705 cpc_readb(falcbase + F_REG(LCR1, ch)) | LCR1_EPRM | LCR1_XPRBS);
1706 } else {
1707 pfalc->prbs = 0;
1708 /* Deactivates generation and monitoring of PRBS
1709 * (Pseudo Random Bit Sequence) */
1710 cpc_writeb(falcbase + F_REG(LCR1, ch),
1711 cpc_readb(falcbase+F_REG(LCR1,ch)) & ~(LCR1_EPRM | LCR1_XPRBS));
1712 if (conf->media == IF_IFACE_T1) {
1713 /* Enable local loop activation/deactivation detect */
1714 cpc_writeb(falcbase + F_REG(IMR3, ch),
1715 cpc_readb(falcbase + F_REG(IMR3, ch)) & ~IMR3_LLBSC);
1716 } else {
1717 /* Enable local loop activation/deactivation detect */
1718 cpc_writeb(falcbase + F_REG(IMR1, ch),
1719 cpc_readb(falcbase + F_REG(IMR1, ch)) & ~IMR1_LLBSC);
1720 }
1721 }
1722 }
1723
1724 /*----------------------------------------------------------------------------
1725 * falc_pattern_test_error
1726 *----------------------------------------------------------------------------
1727 * Description: This routine returns the bit error counter value
1728 *----------------------------------------------------------------------------
1729 */
1730 static u16 falc_pattern_test_error(pc300_t * card, int ch)
1731 {
1732 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1733 falc_t *pfalc = (falc_t *) & chan->falc;
1734
1735 return (pfalc->bec);
1736 }
1737
1738 /**********************************/
1739 /*** Net Interface Routines ***/
1740 /**********************************/
1741
1742 static void
1743 cpc_trace(struct net_device *dev, struct sk_buff *skb_main, char rx_tx)
1744 {
1745 struct sk_buff *skb;
1746
1747 if ((skb = dev_alloc_skb(10 + skb_main->len)) == NULL) {
1748 printk("%s: out of memory\n", dev->name);
1749 return;
1750 }
1751 skb_put(skb, 10 + skb_main->len);
1752
1753 skb->dev = dev;
1754 skb->protocol = htons(ETH_P_CUST);
1755 skb_reset_mac_header(skb);
1756 skb->pkt_type = PACKET_HOST;
1757 skb->len = 10 + skb_main->len;
1758
1759 skb_copy_to_linear_data(skb, dev->name, 5);
1760 skb->data[5] = '[';
1761 skb->data[6] = rx_tx;
1762 skb->data[7] = ']';
1763 skb->data[8] = ':';
1764 skb->data[9] = ' ';
1765 skb_copy_from_linear_data(skb_main, &skb->data[10], skb_main->len);
1766
1767 netif_rx(skb);
1768 }
1769
1770 static void cpc_tx_timeout(struct net_device *dev)
1771 {
1772 pc300dev_t *d = (pc300dev_t *) dev_to_hdlc(dev)->priv;
1773 pc300ch_t *chan = (pc300ch_t *) d->chan;
1774 pc300_t *card = (pc300_t *) chan->card;
1775 int ch = chan->channel;
1776 unsigned long flags;
1777 u8 ilar;
1778
1779 dev->stats.tx_errors++;
1780 dev->stats.tx_aborted_errors++;
1781 CPC_LOCK(card, flags);
1782 if ((ilar = cpc_readb(card->hw.scabase + ILAR)) != 0) {
1783 printk("%s: ILAR=0x%x\n", dev->name, ilar);
1784 cpc_writeb(card->hw.scabase + ILAR, ilar);
1785 cpc_writeb(card->hw.scabase + DMER, 0x80);
1786 }
1787 if (card->hw.type == PC300_TE) {
1788 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
1789 cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) &
1790 ~(CPLD_REG2_FALC_LED1 << (2 * ch)));
1791 }
1792 dev->trans_start = jiffies;
1793 CPC_UNLOCK(card, flags);
1794 netif_wake_queue(dev);
1795 }
1796
1797 static int cpc_queue_xmit(struct sk_buff *skb, struct net_device *dev)
1798 {
1799 pc300dev_t *d = (pc300dev_t *) dev_to_hdlc(dev)->priv;
1800 pc300ch_t *chan = (pc300ch_t *) d->chan;
1801 pc300_t *card = (pc300_t *) chan->card;
1802 int ch = chan->channel;
1803 unsigned long flags;
1804 #ifdef PC300_DEBUG_TX
1805 int i;
1806 #endif
1807
1808 if (!netif_carrier_ok(dev)) {
1809 /* DCD must be OFF: drop packet */
1810 dev_kfree_skb(skb);
1811 dev->stats.tx_errors++;
1812 dev->stats.tx_carrier_errors++;
1813 return 0;
1814 } else if (cpc_readb(card->hw.scabase + M_REG(ST3, ch)) & ST3_DCD) {
1815 printk("%s: DCD is OFF. Going administrative down.\n", dev->name);
1816 dev->stats.tx_errors++;
1817 dev->stats.tx_carrier_errors++;
1818 dev_kfree_skb(skb);
1819 netif_carrier_off(dev);
1820 CPC_LOCK(card, flags);
1821 cpc_writeb(card->hw.scabase + M_REG(CMD, ch), CMD_TX_BUF_CLR);
1822 if (card->hw.type == PC300_TE) {
1823 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
1824 cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) &
1825 ~(CPLD_REG2_FALC_LED1 << (2 * ch)));
1826 }
1827 CPC_UNLOCK(card, flags);
1828 netif_wake_queue(dev);
1829 return 0;
1830 }
1831
1832 /* Write buffer to DMA buffers */
1833 if (dma_buf_write(card, ch, (u8 *)skb->data, skb->len) != 0) {
1834 // printk("%s: write error. Dropping TX packet.\n", dev->name);
1835 netif_stop_queue(dev);
1836 dev_kfree_skb(skb);
1837 dev->stats.tx_errors++;
1838 dev->stats.tx_dropped++;
1839 return 0;
1840 }
1841 #ifdef PC300_DEBUG_TX
1842 printk("%s T:", dev->name);
1843 for (i = 0; i < skb->len; i++)
1844 printk(" %02x", *(skb->data + i));
1845 printk("\n");
1846 #endif
1847
1848 if (d->trace_on) {
1849 cpc_trace(dev, skb, 'T');
1850 }
1851 dev->trans_start = jiffies;
1852
1853 /* Start transmission */
1854 CPC_LOCK(card, flags);
1855 /* verify if it has more than one free descriptor */
1856 if (card->chan[ch].nfree_tx_bd <= 1) {
1857 /* don't have so stop the queue */
1858 netif_stop_queue(dev);
1859 }
1860 cpc_writel(card->hw.scabase + DTX_REG(EDAL, ch),
1861 TX_BD_ADDR(ch, chan->tx_next_bd));
1862 cpc_writeb(card->hw.scabase + M_REG(CMD, ch), CMD_TX_ENA);
1863 cpc_writeb(card->hw.scabase + DSR_TX(ch), DSR_DE);
1864 if (card->hw.type == PC300_TE) {
1865 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
1866 cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) |
1867 (CPLD_REG2_FALC_LED1 << (2 * ch)));
1868 }
1869 CPC_UNLOCK(card, flags);
1870 dev_kfree_skb(skb);
1871
1872 return 0;
1873 }
1874
1875 static void cpc_net_rx(struct net_device *dev)
1876 {
1877 pc300dev_t *d = (pc300dev_t *) dev_to_hdlc(dev)->priv;
1878 pc300ch_t *chan = (pc300ch_t *) d->chan;
1879 pc300_t *card = (pc300_t *) chan->card;
1880 int ch = chan->channel;
1881 #ifdef PC300_DEBUG_RX
1882 int i;
1883 #endif
1884 int rxb;
1885 struct sk_buff *skb;
1886
1887 while (1) {
1888 if ((rxb = dma_get_rx_frame_size(card, ch)) == -1)
1889 return;
1890
1891 if (!netif_carrier_ok(dev)) {
1892 /* DCD must be OFF: drop packet */
1893 printk("%s : DCD is OFF - drop %d rx bytes\n", dev->name, rxb);
1894 skb = NULL;
1895 } else {
1896 if (rxb > (dev->mtu + 40)) { /* add headers */
1897 printk("%s : MTU exceeded %d\n", dev->name, rxb);
1898 skb = NULL;
1899 } else {
1900 skb = dev_alloc_skb(rxb);
1901 if (skb == NULL) {
1902 printk("%s: Memory squeeze!!\n", dev->name);
1903 return;
1904 }
1905 skb->dev = dev;
1906 }
1907 }
1908
1909 if (((rxb = dma_buf_read(card, ch, skb)) <= 0) || (skb == NULL)) {
1910 #ifdef PC300_DEBUG_RX
1911 printk("%s: rxb = %x\n", dev->name, rxb);
1912 #endif
1913 if ((skb == NULL) && (rxb > 0)) {
1914 /* rxb > dev->mtu */
1915 dev->stats.rx_errors++;
1916 dev->stats.rx_length_errors++;
1917 continue;
1918 }
1919
1920 if (rxb < 0) { /* Invalid frame */
1921 rxb = -rxb;
1922 if (rxb & DST_OVR) {
1923 dev->stats.rx_errors++;
1924 dev->stats.rx_fifo_errors++;
1925 }
1926 if (rxb & DST_CRC) {
1927 dev->stats.rx_errors++;
1928 dev->stats.rx_crc_errors++;
1929 }
1930 if (rxb & (DST_RBIT | DST_SHRT | DST_ABT)) {
1931 dev->stats.rx_errors++;
1932 dev->stats.rx_frame_errors++;
1933 }
1934 }
1935 if (skb) {
1936 dev_kfree_skb_irq(skb);
1937 }
1938 continue;
1939 }
1940
1941 dev->stats.rx_bytes += rxb;
1942
1943 #ifdef PC300_DEBUG_RX
1944 printk("%s R:", dev->name);
1945 for (i = 0; i < skb->len; i++)
1946 printk(" %02x", *(skb->data + i));
1947 printk("\n");
1948 #endif
1949 if (d->trace_on) {
1950 cpc_trace(dev, skb, 'R');
1951 }
1952 dev->stats.rx_packets++;
1953 skb->protocol = hdlc_type_trans(skb, dev);
1954 netif_rx(skb);
1955 }
1956 }
1957
1958 /************************************/
1959 /*** PC300 Interrupt Routines ***/
1960 /************************************/
1961 static void sca_tx_intr(pc300dev_t *dev)
1962 {
1963 pc300ch_t *chan = (pc300ch_t *)dev->chan;
1964 pc300_t *card = (pc300_t *)chan->card;
1965 int ch = chan->channel;
1966 volatile pcsca_bd_t __iomem * ptdescr;
1967
1968 /* Clean up descriptors from previous transmission */
1969 ptdescr = (card->hw.rambase +
1970 TX_BD_ADDR(ch,chan->tx_first_bd));
1971 while ((cpc_readl(card->hw.scabase + DTX_REG(CDAL,ch)) !=
1972 TX_BD_ADDR(ch,chan->tx_first_bd)) &&
1973 (cpc_readb(&ptdescr->status) & DST_OSB)) {
1974 dev->dev->stats.tx_packets++;
1975 dev->dev->stats.tx_bytes += cpc_readw(&ptdescr->len);
1976 cpc_writeb(&ptdescr->status, DST_OSB);
1977 cpc_writew(&ptdescr->len, 0);
1978 chan->nfree_tx_bd++;
1979 chan->tx_first_bd = (chan->tx_first_bd + 1) & (N_DMA_TX_BUF - 1);
1980 ptdescr = (card->hw.rambase + TX_BD_ADDR(ch,chan->tx_first_bd));
1981 }
1982
1983 #ifdef CONFIG_PC300_MLPPP
1984 if (chan->conf.proto == PC300_PROTO_MLPPP) {
1985 cpc_tty_trigger_poll(dev);
1986 } else {
1987 #endif
1988 /* Tell the upper layer we are ready to transmit more packets */
1989 netif_wake_queue(dev->dev);
1990 #ifdef CONFIG_PC300_MLPPP
1991 }
1992 #endif
1993 }
1994
1995 static void sca_intr(pc300_t * card)
1996 {
1997 void __iomem *scabase = card->hw.scabase;
1998 volatile u32 status;
1999 int ch;
2000 int intr_count = 0;
2001 unsigned char dsr_rx;
2002
2003 while ((status = cpc_readl(scabase + ISR0)) != 0) {
2004 for (ch = 0; ch < card->hw.nchan; ch++) {
2005 pc300ch_t *chan = &card->chan[ch];
2006 pc300dev_t *d = &chan->d;
2007 struct net_device *dev = d->dev;
2008
2009 spin_lock(&card->card_lock);
2010
2011 /**** Reception ****/
2012 if (status & IR0_DRX((IR0_DMIA | IR0_DMIB), ch)) {
2013 u8 drx_stat = cpc_readb(scabase + DSR_RX(ch));
2014
2015 /* Clear RX interrupts */
2016 cpc_writeb(scabase + DSR_RX(ch), drx_stat | DSR_DWE);
2017
2018 #ifdef PC300_DEBUG_INTR
2019 printk ("sca_intr: RX intr chan[%d] (st=0x%08lx, dsr=0x%02x)\n",
2020 ch, status, drx_stat);
2021 #endif
2022 if (status & IR0_DRX(IR0_DMIA, ch)) {
2023 if (drx_stat & DSR_BOF) {
2024 #ifdef CONFIG_PC300_MLPPP
2025 if (chan->conf.proto == PC300_PROTO_MLPPP) {
2026 /* verify if driver is TTY */
2027 if ((cpc_readb(scabase + DSR_RX(ch)) & DSR_DE)) {
2028 rx_dma_stop(card, ch);
2029 }
2030 cpc_tty_receive(d);
2031 rx_dma_start(card, ch);
2032 } else
2033 #endif
2034 {
2035 if ((cpc_readb(scabase + DSR_RX(ch)) & DSR_DE)) {
2036 rx_dma_stop(card, ch);
2037 }
2038 cpc_net_rx(dev);
2039 /* Discard invalid frames */
2040 dev->stats.rx_errors++;
2041 dev->stats.rx_over_errors++;
2042 chan->rx_first_bd = 0;
2043 chan->rx_last_bd = N_DMA_RX_BUF - 1;
2044 rx_dma_start(card, ch);
2045 }
2046 }
2047 }
2048 if (status & IR0_DRX(IR0_DMIB, ch)) {
2049 if (drx_stat & DSR_EOM) {
2050 if (card->hw.type == PC300_TE) {
2051 cpc_writeb(card->hw.falcbase +
2052 card->hw.cpld_reg2,
2053 cpc_readb (card->hw.falcbase +
2054 card->hw.cpld_reg2) |
2055 (CPLD_REG2_FALC_LED1 << (2 * ch)));
2056 }
2057 #ifdef CONFIG_PC300_MLPPP
2058 if (chan->conf.proto == PC300_PROTO_MLPPP) {
2059 /* verify if driver is TTY */
2060 cpc_tty_receive(d);
2061 } else {
2062 cpc_net_rx(dev);
2063 }
2064 #else
2065 cpc_net_rx(dev);
2066 #endif
2067 if (card->hw.type == PC300_TE) {
2068 cpc_writeb(card->hw.falcbase +
2069 card->hw.cpld_reg2,
2070 cpc_readb (card->hw.falcbase +
2071 card->hw.cpld_reg2) &
2072 ~ (CPLD_REG2_FALC_LED1 << (2 * ch)));
2073 }
2074 }
2075 }
2076 if (!(dsr_rx = cpc_readb(scabase + DSR_RX(ch)) & DSR_DE)) {
2077 #ifdef PC300_DEBUG_INTR
2078 printk("%s: RX intr chan[%d] (st=0x%08lx, dsr=0x%02x, dsr2=0x%02x)\n",
2079 dev->name, ch, status, drx_stat, dsr_rx);
2080 #endif
2081 cpc_writeb(scabase + DSR_RX(ch), (dsr_rx | DSR_DE) & 0xfe);
2082 }
2083 }
2084
2085 /**** Transmission ****/
2086 if (status & IR0_DTX((IR0_EFT | IR0_DMIA | IR0_DMIB), ch)) {
2087 u8 dtx_stat = cpc_readb(scabase + DSR_TX(ch));
2088
2089 /* Clear TX interrupts */
2090 cpc_writeb(scabase + DSR_TX(ch), dtx_stat | DSR_DWE);
2091
2092 #ifdef PC300_DEBUG_INTR
2093 printk ("sca_intr: TX intr chan[%d] (st=0x%08lx, dsr=0x%02x)\n",
2094 ch, status, dtx_stat);
2095 #endif
2096 if (status & IR0_DTX(IR0_EFT, ch)) {
2097 if (dtx_stat & DSR_UDRF) {
2098 if (cpc_readb (scabase + M_REG(TBN, ch)) != 0) {
2099 cpc_writeb(scabase + M_REG(CMD,ch), CMD_TX_BUF_CLR);
2100 }
2101 if (card->hw.type == PC300_TE) {
2102 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
2103 cpc_readb (card->hw.falcbase +
2104 card->hw.cpld_reg2) &
2105 ~ (CPLD_REG2_FALC_LED1 << (2 * ch)));
2106 }
2107 dev->stats.tx_errors++;
2108 dev->stats.tx_fifo_errors++;
2109 sca_tx_intr(d);
2110 }
2111 }
2112 if (status & IR0_DTX(IR0_DMIA, ch)) {
2113 if (dtx_stat & DSR_BOF) {
2114 }
2115 }
2116 if (status & IR0_DTX(IR0_DMIB, ch)) {
2117 if (dtx_stat & DSR_EOM) {
2118 if (card->hw.type == PC300_TE) {
2119 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
2120 cpc_readb (card->hw.falcbase +
2121 card->hw.cpld_reg2) &
2122 ~ (CPLD_REG2_FALC_LED1 << (2 * ch)));
2123 }
2124 sca_tx_intr(d);
2125 }
2126 }
2127 }
2128
2129 /**** MSCI ****/
2130 if (status & IR0_M(IR0_RXINTA, ch)) {
2131 u8 st1 = cpc_readb(scabase + M_REG(ST1, ch));
2132
2133 /* Clear MSCI interrupts */
2134 cpc_writeb(scabase + M_REG(ST1, ch), st1);
2135
2136 #ifdef PC300_DEBUG_INTR
2137 printk("sca_intr: MSCI intr chan[%d] (st=0x%08lx, st1=0x%02x)\n",
2138 ch, status, st1);
2139 #endif
2140 if (st1 & ST1_CDCD) { /* DCD changed */
2141 if (cpc_readb(scabase + M_REG(ST3, ch)) & ST3_DCD) {
2142 printk ("%s: DCD is OFF. Going administrative down.\n",
2143 dev->name);
2144 #ifdef CONFIG_PC300_MLPPP
2145 if (chan->conf.proto != PC300_PROTO_MLPPP) {
2146 netif_carrier_off(dev);
2147 }
2148 #else
2149 netif_carrier_off(dev);
2150
2151 #endif
2152 card->chan[ch].d.line_off++;
2153 } else { /* DCD = 1 */
2154 printk ("%s: DCD is ON. Going administrative up.\n",
2155 dev->name);
2156 #ifdef CONFIG_PC300_MLPPP
2157 if (chan->conf.proto != PC300_PROTO_MLPPP)
2158 /* verify if driver is not TTY */
2159 #endif
2160 netif_carrier_on(dev);
2161 card->chan[ch].d.line_on++;
2162 }
2163 }
2164 }
2165 spin_unlock(&card->card_lock);
2166 }
2167 if (++intr_count == 10)
2168 /* Too much work at this board. Force exit */
2169 break;
2170 }
2171 }
2172
2173 static void falc_t1_loop_detection(pc300_t *card, int ch, u8 frs1)
2174 {
2175 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
2176 falc_t *pfalc = (falc_t *) & chan->falc;
2177 void __iomem *falcbase = card->hw.falcbase;
2178
2179 if (((cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_XPRBS) == 0) &&
2180 !pfalc->loop_gen) {
2181 if (frs1 & FRS1_LLBDD) {
2182 // A Line Loop Back Deactivation signal detected
2183 if (pfalc->loop_active) {
2184 falc_remote_loop(card, ch, 0);
2185 }
2186 } else {
2187 if ((frs1 & FRS1_LLBAD) &&
2188 ((cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_EPRM) == 0)) {
2189 // A Line Loop Back Activation signal detected
2190 if (!pfalc->loop_active) {
2191 falc_remote_loop(card, ch, 1);
2192 }
2193 }
2194 }
2195 }
2196 }
2197
2198 static void falc_e1_loop_detection(pc300_t *card, int ch, u8 rsp)
2199 {
2200 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
2201 falc_t *pfalc = (falc_t *) & chan->falc;
2202 void __iomem *falcbase = card->hw.falcbase;
2203
2204 if (((cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_XPRBS) == 0) &&
2205 !pfalc->loop_gen) {
2206 if (rsp & RSP_LLBDD) {
2207 // A Line Loop Back Deactivation signal detected
2208 if (pfalc->loop_active) {
2209 falc_remote_loop(card, ch, 0);
2210 }
2211 } else {
2212 if ((rsp & RSP_LLBAD) &&
2213 ((cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_EPRM) == 0)) {
2214 // A Line Loop Back Activation signal detected
2215 if (!pfalc->loop_active) {
2216 falc_remote_loop(card, ch, 1);
2217 }
2218 }
2219 }
2220 }
2221 }
2222
2223 static void falc_t1_intr(pc300_t * card, int ch)
2224 {
2225 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
2226 falc_t *pfalc = (falc_t *) & chan->falc;
2227 void __iomem *falcbase = card->hw.falcbase;
2228 u8 isr0, isr3, gis;
2229 u8 dummy;
2230
2231 while ((gis = cpc_readb(falcbase + F_REG(GIS, ch))) != 0) {
2232 if (gis & GIS_ISR0) {
2233 isr0 = cpc_readb(falcbase + F_REG(FISR0, ch));
2234 if (isr0 & FISR0_PDEN) {
2235 /* Read the bit to clear the situation */
2236 if (cpc_readb(falcbase + F_REG(FRS1, ch)) &
2237 FRS1_PDEN) {
2238 pfalc->pden++;
2239 }
2240 }
2241 }
2242
2243 if (gis & GIS_ISR1) {
2244 dummy = cpc_readb(falcbase + F_REG(FISR1, ch));
2245 }
2246
2247 if (gis & GIS_ISR2) {
2248 dummy = cpc_readb(falcbase + F_REG(FISR2, ch));
2249 }
2250
2251 if (gis & GIS_ISR3) {
2252 isr3 = cpc_readb(falcbase + F_REG(FISR3, ch));
2253 if (isr3 & FISR3_SEC) {
2254 pfalc->sec++;
2255 falc_update_stats(card, ch);
2256 falc_check_status(card, ch,
2257 cpc_readb(falcbase + F_REG(FRS0, ch)));
2258 }
2259 if (isr3 & FISR3_ES) {
2260 pfalc->es++;
2261 }
2262 if (isr3 & FISR3_LLBSC) {
2263 falc_t1_loop_detection(card, ch,
2264 cpc_readb(falcbase + F_REG(FRS1, ch)));
2265 }
2266 }
2267 }
2268 }
2269
2270 static void falc_e1_intr(pc300_t * card, int ch)
2271 {
2272 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
2273 falc_t *pfalc = (falc_t *) & chan->falc;
2274 void __iomem *falcbase = card->hw.falcbase;
2275 u8 isr1, isr2, isr3, gis, rsp;
2276 u8 dummy;
2277
2278 while ((gis = cpc_readb(falcbase + F_REG(GIS, ch))) != 0) {
2279 rsp = cpc_readb(falcbase + F_REG(RSP, ch));
2280
2281 if (gis & GIS_ISR0) {
2282 dummy = cpc_readb(falcbase + F_REG(FISR0, ch));
2283 }
2284 if (gis & GIS_ISR1) {
2285 isr1 = cpc_readb(falcbase + F_REG(FISR1, ch));
2286 if (isr1 & FISR1_XMB) {
2287 if ((pfalc->xmb_cause & 2)
2288 && pfalc->multiframe_mode) {
2289 if (cpc_readb (falcbase + F_REG(FRS0, ch)) &
2290 (FRS0_LOS | FRS0_AIS | FRS0_LFA)) {
2291 cpc_writeb(falcbase + F_REG(XSP, ch),
2292 cpc_readb(falcbase + F_REG(XSP, ch))
2293 & ~XSP_AXS);
2294 } else {
2295 cpc_writeb(falcbase + F_REG(XSP, ch),
2296 cpc_readb(falcbase + F_REG(XSP, ch))
2297 | XSP_AXS);
2298 }
2299 }
2300 pfalc->xmb_cause = 0;
2301 cpc_writeb(falcbase + F_REG(IMR1, ch),
2302 cpc_readb(falcbase + F_REG(IMR1, ch)) | IMR1_XMB);
2303 }
2304 if (isr1 & FISR1_LLBSC) {
2305 falc_e1_loop_detection(card, ch, rsp);
2306 }
2307 }
2308 if (gis & GIS_ISR2) {
2309 isr2 = cpc_readb(falcbase + F_REG(FISR2, ch));
2310 if (isr2 & FISR2_T400MS) {
2311 cpc_writeb(falcbase + F_REG(XSW, ch),
2312 cpc_readb(falcbase + F_REG(XSW, ch)) | XSW_XRA);
2313 }
2314 if (isr2 & FISR2_MFAR) {
2315 cpc_writeb(falcbase + F_REG(XSW, ch),
2316 cpc_readb(falcbase + F_REG(XSW, ch)) & ~XSW_XRA);
2317 }
2318 if (isr2 & (FISR2_FAR | FISR2_LFA | FISR2_AIS | FISR2_LOS)) {
2319 pfalc->xmb_cause |= 2;
2320 cpc_writeb(falcbase + F_REG(IMR1, ch),
2321 cpc_readb(falcbase + F_REG(IMR1, ch)) & ~IMR1_XMB);
2322 }
2323 }
2324 if (gis & GIS_ISR3) {
2325 isr3 = cpc_readb(falcbase + F_REG(FISR3, ch));
2326 if (isr3 & FISR3_SEC) {
2327 pfalc->sec++;
2328 falc_update_stats(card, ch);
2329 falc_check_status(card, ch,
2330 cpc_readb(falcbase + F_REG(FRS0, ch)));
2331 }
2332 if (isr3 & FISR3_ES) {
2333 pfalc->es++;
2334 }
2335 }
2336 }
2337 }
2338
2339 static void falc_intr(pc300_t * card)
2340 {
2341 int ch;
2342
2343 for (ch = 0; ch < card->hw.nchan; ch++) {
2344 pc300ch_t *chan = &card->chan[ch];
2345 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
2346
2347 if (conf->media == IF_IFACE_T1) {
2348 falc_t1_intr(card, ch);
2349 } else {
2350 falc_e1_intr(card, ch);
2351 }
2352 }
2353 }
2354
2355 static irqreturn_t cpc_intr(int irq, void *dev_id)
2356 {
2357 pc300_t *card = dev_id;
2358 volatile u8 plx_status;
2359
2360 if (!card) {
2361 #ifdef PC300_DEBUG_INTR
2362 printk("cpc_intr: spurious intr %d\n", irq);
2363 #endif
2364 return IRQ_NONE; /* spurious intr */
2365 }
2366
2367 if (!card->hw.rambase) {
2368 #ifdef PC300_DEBUG_INTR
2369 printk("cpc_intr: spurious intr2 %d\n", irq);
2370 #endif
2371 return IRQ_NONE; /* spurious intr */
2372 }
2373
2374 switch (card->hw.type) {
2375 case PC300_RSV:
2376 case PC300_X21:
2377 sca_intr(card);
2378 break;
2379
2380 case PC300_TE:
2381 while ( (plx_status = (cpc_readb(card->hw.plxbase + card->hw.intctl_reg) &
2382 (PLX_9050_LINT1_STATUS | PLX_9050_LINT2_STATUS))) != 0) {
2383 if (plx_status & PLX_9050_LINT1_STATUS) { /* SCA Interrupt */
2384 sca_intr(card);
2385 }
2386 if (plx_status & PLX_9050_LINT2_STATUS) { /* FALC Interrupt */
2387 falc_intr(card);
2388 }
2389 }
2390 break;
2391 }
2392 return IRQ_HANDLED;
2393 }
2394
2395 static void cpc_sca_status(pc300_t * card, int ch)
2396 {
2397 u8 ilar;
2398 void __iomem *scabase = card->hw.scabase;
2399 unsigned long flags;
2400
2401 tx_dma_buf_check(card, ch);
2402 rx_dma_buf_check(card, ch);
2403 ilar = cpc_readb(scabase + ILAR);
2404 printk ("ILAR=0x%02x, WCRL=0x%02x, PCR=0x%02x, BTCR=0x%02x, BOLR=0x%02x\n",
2405 ilar, cpc_readb(scabase + WCRL), cpc_readb(scabase + PCR),
2406 cpc_readb(scabase + BTCR), cpc_readb(scabase + BOLR));
2407 printk("TX_CDA=0x%08x, TX_EDA=0x%08x\n",
2408 cpc_readl(scabase + DTX_REG(CDAL, ch)),
2409 cpc_readl(scabase + DTX_REG(EDAL, ch)));
2410 printk("RX_CDA=0x%08x, RX_EDA=0x%08x, BFL=0x%04x\n",
2411 cpc_readl(scabase + DRX_REG(CDAL, ch)),
2412 cpc_readl(scabase + DRX_REG(EDAL, ch)),
2413 cpc_readw(scabase + DRX_REG(BFLL, ch)));
2414 printk("DMER=0x%02x, DSR_TX=0x%02x, DSR_RX=0x%02x\n",
2415 cpc_readb(scabase + DMER), cpc_readb(scabase + DSR_TX(ch)),
2416 cpc_readb(scabase + DSR_RX(ch)));
2417 printk("DMR_TX=0x%02x, DMR_RX=0x%02x, DIR_TX=0x%02x, DIR_RX=0x%02x\n",
2418 cpc_readb(scabase + DMR_TX(ch)), cpc_readb(scabase + DMR_RX(ch)),
2419 cpc_readb(scabase + DIR_TX(ch)),
2420 cpc_readb(scabase + DIR_RX(ch)));
2421 printk("DCR_TX=0x%02x, DCR_RX=0x%02x, FCT_TX=0x%02x, FCT_RX=0x%02x\n",
2422 cpc_readb(scabase + DCR_TX(ch)), cpc_readb(scabase + DCR_RX(ch)),
2423 cpc_readb(scabase + FCT_TX(ch)),
2424 cpc_readb(scabase + FCT_RX(ch)));
2425 printk("MD0=0x%02x, MD1=0x%02x, MD2=0x%02x, MD3=0x%02x, IDL=0x%02x\n",
2426 cpc_readb(scabase + M_REG(MD0, ch)),
2427 cpc_readb(scabase + M_REG(MD1, ch)),
2428 cpc_readb(scabase + M_REG(MD2, ch)),
2429 cpc_readb(scabase + M_REG(MD3, ch)),
2430 cpc_readb(scabase + M_REG(IDL, ch)));
2431 printk("CMD=0x%02x, SA0=0x%02x, SA1=0x%02x, TFN=0x%02x, CTL=0x%02x\n",
2432 cpc_readb(scabase + M_REG(CMD, ch)),
2433 cpc_readb(scabase + M_REG(SA0, ch)),
2434 cpc_readb(scabase + M_REG(SA1, ch)),
2435 cpc_readb(scabase + M_REG(TFN, ch)),
2436 cpc_readb(scabase + M_REG(CTL, ch)));
2437 printk("ST0=0x%02x, ST1=0x%02x, ST2=0x%02x, ST3=0x%02x, ST4=0x%02x\n",
2438 cpc_readb(scabase + M_REG(ST0, ch)),
2439 cpc_readb(scabase + M_REG(ST1, ch)),
2440 cpc_readb(scabase + M_REG(ST2, ch)),
2441 cpc_readb(scabase + M_REG(ST3, ch)),
2442 cpc_readb(scabase + M_REG(ST4, ch)));
2443 printk ("CST0=0x%02x, CST1=0x%02x, CST2=0x%02x, CST3=0x%02x, FST=0x%02x\n",
2444 cpc_readb(scabase + M_REG(CST0, ch)),
2445 cpc_readb(scabase + M_REG(CST1, ch)),
2446 cpc_readb(scabase + M_REG(CST2, ch)),
2447 cpc_readb(scabase + M_REG(CST3, ch)),
2448 cpc_readb(scabase + M_REG(FST, ch)));
2449 printk("TRC0=0x%02x, TRC1=0x%02x, RRC=0x%02x, TBN=0x%02x, RBN=0x%02x\n",
2450 cpc_readb(scabase + M_REG(TRC0, ch)),
2451 cpc_readb(scabase + M_REG(TRC1, ch)),
2452 cpc_readb(scabase + M_REG(RRC, ch)),
2453 cpc_readb(scabase + M_REG(TBN, ch)),
2454 cpc_readb(scabase + M_REG(RBN, ch)));
2455 printk("TFS=0x%02x, TNR0=0x%02x, TNR1=0x%02x, RNR=0x%02x\n",
2456 cpc_readb(scabase + M_REG(TFS, ch)),
2457 cpc_readb(scabase + M_REG(TNR0, ch)),
2458 cpc_readb(scabase + M_REG(TNR1, ch)),
2459 cpc_readb(scabase + M_REG(RNR, ch)));
2460 printk("TCR=0x%02x, RCR=0x%02x, TNR1=0x%02x, RNR=0x%02x\n",
2461 cpc_readb(scabase + M_REG(TCR, ch)),
2462 cpc_readb(scabase + M_REG(RCR, ch)),
2463 cpc_readb(scabase + M_REG(TNR1, ch)),
2464 cpc_readb(scabase + M_REG(RNR, ch)));
2465 printk("TXS=0x%02x, RXS=0x%02x, EXS=0x%02x, TMCT=0x%02x, TMCR=0x%02x\n",
2466 cpc_readb(scabase + M_REG(TXS, ch)),
2467 cpc_readb(scabase + M_REG(RXS, ch)),
2468 cpc_readb(scabase + M_REG(EXS, ch)),
2469 cpc_readb(scabase + M_REG(TMCT, ch)),
2470 cpc_readb(scabase + M_REG(TMCR, ch)));
2471 printk("IE0=0x%02x, IE1=0x%02x, IE2=0x%02x, IE4=0x%02x, FIE=0x%02x\n",
2472 cpc_readb(scabase + M_REG(IE0, ch)),
2473 cpc_readb(scabase + M_REG(IE1, ch)),
2474 cpc_readb(scabase + M_REG(IE2, ch)),
2475 cpc_readb(scabase + M_REG(IE4, ch)),
2476 cpc_readb(scabase + M_REG(FIE, ch)));
2477 printk("IER0=0x%08x\n", cpc_readl(scabase + IER0));
2478
2479 if (ilar != 0) {
2480 CPC_LOCK(card, flags);
2481 cpc_writeb(scabase + ILAR, ilar);
2482 cpc_writeb(scabase + DMER, 0x80);
2483 CPC_UNLOCK(card, flags);
2484 }
2485 }
2486
2487 static void cpc_falc_status(pc300_t * card, int ch)
2488 {
2489 pc300ch_t *chan = &card->chan[ch];
2490 falc_t *pfalc = (falc_t *) & chan->falc;
2491 unsigned long flags;
2492
2493 CPC_LOCK(card, flags);
2494 printk("CH%d: %s %s %d channels\n",
2495 ch, (pfalc->sync ? "SYNC" : ""), (pfalc->active ? "ACTIVE" : ""),
2496 pfalc->num_channels);
2497
2498 printk(" pden=%d, los=%d, losr=%d, lfa=%d, farec=%d\n",
2499 pfalc->pden, pfalc->los, pfalc->losr, pfalc->lfa, pfalc->farec);
2500 printk(" lmfa=%d, ais=%d, sec=%d, es=%d, rai=%d\n",
2501 pfalc->lmfa, pfalc->ais, pfalc->sec, pfalc->es, pfalc->rai);
2502 printk(" bec=%d, fec=%d, cvc=%d, cec=%d, ebc=%d\n",
2503 pfalc->bec, pfalc->fec, pfalc->cvc, pfalc->cec, pfalc->ebc);
2504
2505 printk("\n");
2506 printk(" STATUS: %s %s %s %s %s %s\n",
2507 (pfalc->red_alarm ? "RED" : ""),
2508 (pfalc->blue_alarm ? "BLU" : ""),
2509 (pfalc->yellow_alarm ? "YEL" : ""),
2510 (pfalc->loss_fa ? "LFA" : ""),
2511 (pfalc->loss_mfa ? "LMF" : ""), (pfalc->prbs ? "PRB" : ""));
2512 CPC_UNLOCK(card, flags);
2513 }
2514
2515 static int cpc_change_mtu(struct net_device *dev, int new_mtu)
2516 {
2517 if ((new_mtu < 128) || (new_mtu > PC300_DEF_MTU))
2518 return -EINVAL;
2519 dev->mtu = new_mtu;
2520 return 0;
2521 }
2522
2523 static int cpc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2524 {
2525 pc300dev_t *d = (pc300dev_t *) dev_to_hdlc(dev)->priv;
2526 pc300ch_t *chan = (pc300ch_t *) d->chan;
2527 pc300_t *card = (pc300_t *) chan->card;
2528 pc300conf_t conf_aux;
2529 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
2530 int ch = chan->channel;
2531 void __user *arg = ifr->ifr_data;
2532 struct if_settings *settings = &ifr->ifr_settings;
2533 void __iomem *scabase = card->hw.scabase;
2534
2535 if (!capable(CAP_NET_ADMIN))
2536 return -EPERM;
2537
2538 switch (cmd) {
2539 case SIOCGPC300CONF:
2540 #ifdef CONFIG_PC300_MLPPP
2541 if (conf->proto != PC300_PROTO_MLPPP) {
2542 conf->proto = /* FIXME hdlc->proto.id */ 0;
2543 }
2544 #else
2545 conf->proto = /* FIXME hdlc->proto.id */ 0;
2546 #endif
2547 memcpy(&conf_aux.conf, conf, sizeof(pc300chconf_t));
2548 memcpy(&conf_aux.hw, &card->hw, sizeof(pc300hw_t));
2549 if (!arg ||
2550 copy_to_user(arg, &conf_aux, sizeof(pc300conf_t)))
2551 return -EINVAL;
2552 return 0;
2553 case SIOCSPC300CONF:
2554 if (!capable(CAP_NET_ADMIN))
2555 return -EPERM;
2556 if (!arg ||
2557 copy_from_user(&conf_aux.conf, arg, sizeof(pc300chconf_t)))
2558 return -EINVAL;
2559 if (card->hw.cpld_id < 0x02 &&
2560 conf_aux.conf.fr_mode == PC300_FR_UNFRAMED) {
2561 /* CPLD_ID < 0x02 doesn't support Unframed E1 */
2562 return -EINVAL;
2563 }
2564 #ifdef CONFIG_PC300_MLPPP
2565 if (conf_aux.conf.proto == PC300_PROTO_MLPPP) {
2566 if (conf->proto != PC300_PROTO_MLPPP) {
2567 memcpy(conf, &conf_aux.conf, sizeof(pc300chconf_t));
2568 cpc_tty_init(d); /* init TTY driver */
2569 }
2570 } else {
2571 if (conf_aux.conf.proto == 0xffff) {
2572 if (conf->proto == PC300_PROTO_MLPPP){
2573 /* ifdown interface */
2574 cpc_close(dev);
2575 }
2576 } else {
2577 memcpy(conf, &conf_aux.conf, sizeof(pc300chconf_t));
2578 /* FIXME hdlc->proto.id = conf->proto; */
2579 }
2580 }
2581 #else
2582 memcpy(conf, &conf_aux.conf, sizeof(pc300chconf_t));
2583 /* FIXME hdlc->proto.id = conf->proto; */
2584 #endif
2585 return 0;
2586 case SIOCGPC300STATUS:
2587 cpc_sca_status(card, ch);
2588 return 0;
2589 case SIOCGPC300FALCSTATUS:
2590 cpc_falc_status(card, ch);
2591 return 0;
2592
2593 case SIOCGPC300UTILSTATS:
2594 {
2595 if (!arg) { /* clear statistics */
2596 memset(&dev->stats, 0, sizeof(dev->stats));
2597 if (card->hw.type == PC300_TE) {
2598 memset(&chan->falc, 0, sizeof(falc_t));
2599 }
2600 } else {
2601 pc300stats_t pc300stats;
2602
2603 memset(&pc300stats, 0, sizeof(pc300stats_t));
2604 pc300stats.hw_type = card->hw.type;
2605 pc300stats.line_on = card->chan[ch].d.line_on;
2606 pc300stats.line_off = card->chan[ch].d.line_off;
2607 memcpy(&pc300stats.gen_stats, &dev->stats,
2608 sizeof(dev->stats));
2609 if (card->hw.type == PC300_TE)
2610 memcpy(&pc300stats.te_stats,&chan->falc,sizeof(falc_t));
2611 if (copy_to_user(arg, &pc300stats, sizeof(pc300stats_t)))
2612 return -EFAULT;
2613 }
2614 return 0;
2615 }
2616
2617 case SIOCGPC300UTILSTATUS:
2618 {
2619 struct pc300status pc300status;
2620
2621 pc300status.hw_type = card->hw.type;
2622 if (card->hw.type == PC300_TE) {
2623 pc300status.te_status.sync = chan->falc.sync;
2624 pc300status.te_status.red_alarm = chan->falc.red_alarm;
2625 pc300status.te_status.blue_alarm = chan->falc.blue_alarm;
2626 pc300status.te_status.loss_fa = chan->falc.loss_fa;
2627 pc300status.te_status.yellow_alarm =chan->falc.yellow_alarm;
2628 pc300status.te_status.loss_mfa = chan->falc.loss_mfa;
2629 pc300status.te_status.prbs = chan->falc.prbs;
2630 } else {
2631 pc300status.gen_status.dcd =
2632 !(cpc_readb (scabase + M_REG(ST3, ch)) & ST3_DCD);
2633 pc300status.gen_status.cts =
2634 !(cpc_readb (scabase + M_REG(ST3, ch)) & ST3_CTS);
2635 pc300status.gen_status.rts =
2636 !(cpc_readb (scabase + M_REG(CTL, ch)) & CTL_RTS);
2637 pc300status.gen_status.dtr =
2638 !(cpc_readb (scabase + M_REG(CTL, ch)) & CTL_DTR);
2639 /* There is no DSR in HD64572 */
2640 }
2641 if (!arg
2642 || copy_to_user(arg, &pc300status, sizeof(pc300status_t)))
2643 return -EINVAL;
2644 return 0;
2645 }
2646
2647 case SIOCSPC300TRACE:
2648 /* Sets/resets a trace_flag for the respective device */
2649 if (!arg || copy_from_user(&d->trace_on, arg,sizeof(unsigned char)))
2650 return -EINVAL;
2651 return 0;
2652
2653 case SIOCSPC300LOOPBACK:
2654 {
2655 struct pc300loopback pc300loop;
2656
2657 /* TE boards only */
2658 if (card->hw.type != PC300_TE)
2659 return -EINVAL;
2660
2661 if (!arg ||
2662 copy_from_user(&pc300loop, arg, sizeof(pc300loopback_t)))
2663 return -EINVAL;
2664 switch (pc300loop.loop_type) {
2665 case PC300LOCLOOP: /* Turn the local loop on/off */
2666 falc_local_loop(card, ch, pc300loop.loop_on);
2667 return 0;
2668
2669 case PC300REMLOOP: /* Turn the remote loop on/off */
2670 falc_remote_loop(card, ch, pc300loop.loop_on);
2671 return 0;
2672
2673 case PC300PAYLOADLOOP: /* Turn the payload loop on/off */
2674 falc_payload_loop(card, ch, pc300loop.loop_on);
2675 return 0;
2676
2677 case PC300GENLOOPUP: /* Generate loop UP */
2678 if (pc300loop.loop_on) {
2679 falc_generate_loop_up_code (card, ch);
2680 } else {
2681 turn_off_xlu(card, ch);
2682 }
2683 return 0;
2684
2685 case PC300GENLOOPDOWN: /* Generate loop DOWN */
2686 if (pc300loop.loop_on) {
2687 falc_generate_loop_down_code (card, ch);
2688 } else {
2689 turn_off_xld(card, ch);
2690 }
2691 return 0;
2692
2693 default:
2694 return -EINVAL;
2695 }
2696 }
2697
2698 case SIOCSPC300PATTERNTEST:
2699 /* Turn the pattern test on/off and show the errors counter */
2700 {
2701 struct pc300patterntst pc300patrntst;
2702
2703 /* TE boards only */
2704 if (card->hw.type != PC300_TE)
2705 return -EINVAL;
2706
2707 if (card->hw.cpld_id < 0x02) {
2708 /* CPLD_ID < 0x02 doesn't support pattern test */
2709 return -EINVAL;
2710 }
2711
2712 if (!arg ||
2713 copy_from_user(&pc300patrntst,arg,sizeof(pc300patterntst_t)))
2714 return -EINVAL;
2715 if (pc300patrntst.patrntst_on == 2) {
2716 if (chan->falc.prbs == 0) {
2717 falc_pattern_test(card, ch, 1);
2718 }
2719 pc300patrntst.num_errors =
2720 falc_pattern_test_error(card, ch);
2721 if (copy_to_user(arg, &pc300patrntst,
2722 sizeof(pc300patterntst_t)))
2723 return -EINVAL;
2724 } else {
2725 falc_pattern_test(card, ch, pc300patrntst.patrntst_on);
2726 }
2727 return 0;
2728 }
2729
2730 case SIOCWANDEV:
2731 switch (ifr->ifr_settings.type) {
2732 case IF_GET_IFACE:
2733 {
2734 const size_t size = sizeof(sync_serial_settings);
2735 ifr->ifr_settings.type = conf->media;
2736 if (ifr->ifr_settings.size < size) {
2737 /* data size wanted */
2738 ifr->ifr_settings.size = size;
2739 return -ENOBUFS;
2740 }
2741
2742 if (copy_to_user(settings->ifs_ifsu.sync,
2743 &conf->phys_settings, size)) {
2744 return -EFAULT;
2745 }
2746 return 0;
2747 }
2748
2749 case IF_IFACE_V35:
2750 case IF_IFACE_V24:
2751 case IF_IFACE_X21:
2752 {
2753 const size_t size = sizeof(sync_serial_settings);
2754
2755 if (!capable(CAP_NET_ADMIN)) {
2756 return -EPERM;
2757 }
2758 /* incorrect data len? */
2759 if (ifr->ifr_settings.size != size) {
2760 return -ENOBUFS;
2761 }
2762
2763 if (copy_from_user(&conf->phys_settings,
2764 settings->ifs_ifsu.sync, size)) {
2765 return -EFAULT;
2766 }
2767
2768 if (conf->phys_settings.loopback) {
2769 cpc_writeb(card->hw.scabase + M_REG(MD2, ch),
2770 cpc_readb(card->hw.scabase + M_REG(MD2, ch)) |
2771 MD2_LOOP_MIR);
2772 }
2773 conf->media = ifr->ifr_settings.type;
2774 return 0;
2775 }
2776
2777 case IF_IFACE_T1:
2778 case IF_IFACE_E1:
2779 {
2780 const size_t te_size = sizeof(te1_settings);
2781 const size_t size = sizeof(sync_serial_settings);
2782
2783 if (!capable(CAP_NET_ADMIN)) {
2784 return -EPERM;
2785 }
2786
2787 /* incorrect data len? */
2788 if (ifr->ifr_settings.size != te_size) {
2789 return -ENOBUFS;
2790 }
2791
2792 if (copy_from_user(&conf->phys_settings,
2793 settings->ifs_ifsu.te1, size)) {
2794 return -EFAULT;
2795 }/* Ignoring HDLC slot_map for a while */
2796
2797 if (conf->phys_settings.loopback) {
2798 cpc_writeb(card->hw.scabase + M_REG(MD2, ch),
2799 cpc_readb(card->hw.scabase + M_REG(MD2, ch)) |
2800 MD2_LOOP_MIR);
2801 }
2802 conf->media = ifr->ifr_settings.type;
2803 return 0;
2804 }
2805 default:
2806 return hdlc_ioctl(dev, ifr, cmd);
2807 }
2808
2809 default:
2810 return hdlc_ioctl(dev, ifr, cmd);
2811 }
2812 }
2813
2814 static int clock_rate_calc(u32 rate, u32 clock, int *br_io)
2815 {
2816 int br, tc;
2817 int br_pwr, error;
2818
2819 *br_io = 0;
2820
2821 if (rate == 0)
2822 return (0);
2823
2824 for (br = 0, br_pwr = 1; br <= 9; br++, br_pwr <<= 1) {
2825 if ((tc = clock / br_pwr / rate) <= 0xff) {
2826 *br_io = br;
2827 break;
2828 }
2829 }
2830
2831 if (tc <= 0xff) {
2832 error = ((rate - (clock / br_pwr / rate)) / rate) * 1000;
2833 /* Errors bigger than +/- 1% won't be tolerated */
2834 if (error < -10 || error > 10)
2835 return (-1);
2836 else
2837 return (tc);
2838 } else {
2839 return (-1);
2840 }
2841 }
2842
2843 static int ch_config(pc300dev_t * d)
2844 {
2845 pc300ch_t *chan = (pc300ch_t *) d->chan;
2846 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
2847 pc300_t *card = (pc300_t *) chan->card;
2848 void __iomem *scabase = card->hw.scabase;
2849 void __iomem *plxbase = card->hw.plxbase;
2850 int ch = chan->channel;
2851 u32 clkrate = chan->conf.phys_settings.clock_rate;
2852 u32 clktype = chan->conf.phys_settings.clock_type;
2853 u16 encoding = chan->conf.proto_settings.encoding;
2854 u16 parity = chan->conf.proto_settings.parity;
2855 u8 md0, md2;
2856
2857 /* Reset the channel */
2858 cpc_writeb(scabase + M_REG(CMD, ch), CMD_CH_RST);
2859
2860 /* Configure the SCA registers */
2861 switch (parity) {
2862 case PARITY_NONE:
2863 md0 = MD0_BIT_SYNC;
2864 break;
2865 case PARITY_CRC16_PR0:
2866 md0 = MD0_CRC16_0|MD0_CRCC0|MD0_BIT_SYNC;
2867 break;
2868 case PARITY_CRC16_PR1:
2869 md0 = MD0_CRC16_1|MD0_CRCC0|MD0_BIT_SYNC;
2870 break;
2871 case PARITY_CRC32_PR1_CCITT:
2872 md0 = MD0_CRC32|MD0_CRCC0|MD0_BIT_SYNC;
2873 break;
2874 case PARITY_CRC16_PR1_CCITT:
2875 default:
2876 md0 = MD0_CRC_CCITT|MD0_CRCC0|MD0_BIT_SYNC;
2877 break;
2878 }
2879 switch (encoding) {
2880 case ENCODING_NRZI:
2881 md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_NRZI;
2882 break;
2883 case ENCODING_FM_MARK: /* FM1 */
2884 md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_FM|MD2_FM1;
2885 break;
2886 case ENCODING_FM_SPACE: /* FM0 */
2887 md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_FM|MD2_FM0;
2888 break;
2889 case ENCODING_MANCHESTER: /* It's not working... */
2890 md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_FM|MD2_MANCH;
2891 break;
2892 case ENCODING_NRZ:
2893 default:
2894 md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_NRZ;
2895 break;
2896 }
2897 cpc_writeb(scabase + M_REG(MD0, ch), md0);
2898 cpc_writeb(scabase + M_REG(MD1, ch), 0);
2899 cpc_writeb(scabase + M_REG(MD2, ch), md2);
2900 cpc_writeb(scabase + M_REG(IDL, ch), 0x7e);
2901 cpc_writeb(scabase + M_REG(CTL, ch), CTL_URSKP | CTL_IDLC);
2902
2903 /* Configure HW media */
2904 switch (card->hw.type) {
2905 case PC300_RSV:
2906 if (conf->media == IF_IFACE_V35) {
2907 cpc_writel((plxbase + card->hw.gpioc_reg),
2908 cpc_readl(plxbase + card->hw.gpioc_reg) | PC300_CHMEDIA_MASK(ch));
2909 } else {
2910 cpc_writel((plxbase + card->hw.gpioc_reg),
2911 cpc_readl(plxbase + card->hw.gpioc_reg) & ~PC300_CHMEDIA_MASK(ch));
2912 }
2913 break;
2914
2915 case PC300_X21:
2916 break;
2917
2918 case PC300_TE:
2919 te_config(card, ch);
2920 break;
2921 }
2922
2923 switch (card->hw.type) {
2924 case PC300_RSV:
2925 case PC300_X21:
2926 if (clktype == CLOCK_INT || clktype == CLOCK_TXINT) {
2927 int tmc, br;
2928
2929 /* Calculate the clkrate parameters */
2930 tmc = clock_rate_calc(clkrate, card->hw.clock, &br);
2931 if (tmc < 0)
2932 return -EIO;
2933 cpc_writeb(scabase + M_REG(TMCT, ch), tmc);
2934 cpc_writeb(scabase + M_REG(TXS, ch),
2935 (TXS_DTRXC | TXS_IBRG | br));
2936 if (clktype == CLOCK_INT) {
2937 cpc_writeb(scabase + M_REG(TMCR, ch), tmc);
2938 cpc_writeb(scabase + M_REG(RXS, ch),
2939 (RXS_IBRG | br));
2940 } else {
2941 cpc_writeb(scabase + M_REG(TMCR, ch), 1);
2942 cpc_writeb(scabase + M_REG(RXS, ch), 0);
2943 }
2944 if (card->hw.type == PC300_X21) {
2945 cpc_writeb(scabase + M_REG(GPO, ch), 1);
2946 cpc_writeb(scabase + M_REG(EXS, ch), EXS_TES1 | EXS_RES1);
2947 } else {
2948 cpc_writeb(scabase + M_REG(EXS, ch), EXS_TES1);
2949 }
2950 } else {
2951 cpc_writeb(scabase + M_REG(TMCT, ch), 1);
2952 if (clktype == CLOCK_EXT) {
2953 cpc_writeb(scabase + M_REG(TXS, ch),
2954 TXS_DTRXC);
2955 } else {
2956 cpc_writeb(scabase + M_REG(TXS, ch),
2957 TXS_DTRXC|TXS_RCLK);
2958 }
2959 cpc_writeb(scabase + M_REG(TMCR, ch), 1);
2960 cpc_writeb(scabase + M_REG(RXS, ch), 0);
2961 if (card->hw.type == PC300_X21) {
2962 cpc_writeb(scabase + M_REG(GPO, ch), 0);
2963 cpc_writeb(scabase + M_REG(EXS, ch), EXS_TES1 | EXS_RES1);
2964 } else {
2965 cpc_writeb(scabase + M_REG(EXS, ch), EXS_TES1);
2966 }
2967 }
2968 break;
2969
2970 case PC300_TE:
2971 /* SCA always receives clock from the FALC chip */
2972 cpc_writeb(scabase + M_REG(TMCT, ch), 1);
2973 cpc_writeb(scabase + M_REG(TXS, ch), 0);
2974 cpc_writeb(scabase + M_REG(TMCR, ch), 1);
2975 cpc_writeb(scabase + M_REG(RXS, ch), 0);
2976 cpc_writeb(scabase + M_REG(EXS, ch), 0);
2977 break;
2978 }
2979
2980 /* Enable Interrupts */
2981 cpc_writel(scabase + IER0,
2982 cpc_readl(scabase + IER0) |
2983 IR0_M(IR0_RXINTA, ch) |
2984 IR0_DRX(IR0_EFT | IR0_DMIA | IR0_DMIB, ch) |
2985 IR0_DTX(IR0_EFT | IR0_DMIA | IR0_DMIB, ch));
2986 cpc_writeb(scabase + M_REG(IE0, ch),
2987 cpc_readl(scabase + M_REG(IE0, ch)) | IE0_RXINTA);
2988 cpc_writeb(scabase + M_REG(IE1, ch),
2989 cpc_readl(scabase + M_REG(IE1, ch)) | IE1_CDCD);
2990
2991 return 0;
2992 }
2993
2994 static int rx_config(pc300dev_t * d)
2995 {
2996 pc300ch_t *chan = (pc300ch_t *) d->chan;
2997 pc300_t *card = (pc300_t *) chan->card;
2998 void __iomem *scabase = card->hw.scabase;
2999 int ch = chan->channel;
3000
3001 cpc_writeb(scabase + DSR_RX(ch), 0);
3002
3003 /* General RX settings */
3004 cpc_writeb(scabase + M_REG(RRC, ch), 0);
3005 cpc_writeb(scabase + M_REG(RNR, ch), 16);
3006
3007 /* Enable reception */
3008 cpc_writeb(scabase + M_REG(CMD, ch), CMD_RX_CRC_INIT);
3009 cpc_writeb(scabase + M_REG(CMD, ch), CMD_RX_ENA);
3010
3011 /* Initialize DMA stuff */
3012 chan->rx_first_bd = 0;
3013 chan->rx_last_bd = N_DMA_RX_BUF - 1;
3014 rx_dma_buf_init(card, ch);
3015 cpc_writeb(scabase + DCR_RX(ch), DCR_FCT_CLR);
3016 cpc_writeb(scabase + DMR_RX(ch), (DMR_TMOD | DMR_NF));
3017 cpc_writeb(scabase + DIR_RX(ch), (DIR_EOM | DIR_BOF));
3018
3019 /* Start DMA */
3020 rx_dma_start(card, ch);
3021
3022 return 0;
3023 }
3024
3025 static int tx_config(pc300dev_t * d)
3026 {
3027 pc300ch_t *chan = (pc300ch_t *) d->chan;
3028 pc300_t *card = (pc300_t *) chan->card;
3029 void __iomem *scabase = card->hw.scabase;
3030 int ch = chan->channel;
3031
3032 cpc_writeb(scabase + DSR_TX(ch), 0);
3033
3034 /* General TX settings */
3035 cpc_writeb(scabase + M_REG(TRC0, ch), 0);
3036 cpc_writeb(scabase + M_REG(TFS, ch), 32);
3037 cpc_writeb(scabase + M_REG(TNR0, ch), 20);
3038 cpc_writeb(scabase + M_REG(TNR1, ch), 48);
3039 cpc_writeb(scabase + M_REG(TCR, ch), 8);
3040
3041 /* Enable transmission */
3042 cpc_writeb(scabase + M_REG(CMD, ch), CMD_TX_CRC_INIT);
3043
3044 /* Initialize DMA stuff */
3045 chan->tx_first_bd = 0;
3046 chan->tx_next_bd = 0;
3047 tx_dma_buf_init(card, ch);
3048 cpc_writeb(scabase + DCR_TX(ch), DCR_FCT_CLR);
3049 cpc_writeb(scabase + DMR_TX(ch), (DMR_TMOD | DMR_NF));
3050 cpc_writeb(scabase + DIR_TX(ch), (DIR_EOM | DIR_BOF | DIR_UDRF));
3051 cpc_writel(scabase + DTX_REG(CDAL, ch), TX_BD_ADDR(ch, chan->tx_first_bd));
3052 cpc_writel(scabase + DTX_REG(EDAL, ch), TX_BD_ADDR(ch, chan->tx_next_bd));
3053
3054 return 0;
3055 }
3056
3057 static int cpc_attach(struct net_device *dev, unsigned short encoding,
3058 unsigned short parity)
3059 {
3060 pc300dev_t *d = (pc300dev_t *)dev_to_hdlc(dev)->priv;
3061 pc300ch_t *chan = (pc300ch_t *)d->chan;
3062 pc300_t *card = (pc300_t *)chan->card;
3063 pc300chconf_t *conf = (pc300chconf_t *)&chan->conf;
3064
3065 if (card->hw.type == PC300_TE) {
3066 if (encoding != ENCODING_NRZ && encoding != ENCODING_NRZI) {
3067 return -EINVAL;
3068 }
3069 } else {
3070 if (encoding != ENCODING_NRZ && encoding != ENCODING_NRZI &&
3071 encoding != ENCODING_FM_MARK && encoding != ENCODING_FM_SPACE) {
3072 /* Driver doesn't support ENCODING_MANCHESTER yet */
3073 return -EINVAL;
3074 }
3075 }
3076
3077 if (parity != PARITY_NONE && parity != PARITY_CRC16_PR0 &&
3078 parity != PARITY_CRC16_PR1 && parity != PARITY_CRC32_PR1_CCITT &&
3079 parity != PARITY_CRC16_PR1_CCITT) {
3080 return -EINVAL;
3081 }
3082
3083 conf->proto_settings.encoding = encoding;
3084 conf->proto_settings.parity = parity;
3085 return 0;
3086 }
3087
3088 static int cpc_opench(pc300dev_t * d)
3089 {
3090 pc300ch_t *chan = (pc300ch_t *) d->chan;
3091 pc300_t *card = (pc300_t *) chan->card;
3092 int ch = chan->channel, rc;
3093 void __iomem *scabase = card->hw.scabase;
3094
3095 rc = ch_config(d);
3096 if (rc)
3097 return rc;
3098
3099 rx_config(d);
3100
3101 tx_config(d);
3102
3103 /* Assert RTS and DTR */
3104 cpc_writeb(scabase + M_REG(CTL, ch),
3105 cpc_readb(scabase + M_REG(CTL, ch)) & ~(CTL_RTS | CTL_DTR));
3106
3107 return 0;
3108 }
3109
3110 static void cpc_closech(pc300dev_t * d)
3111 {
3112 pc300ch_t *chan = (pc300ch_t *) d->chan;
3113 pc300_t *card = (pc300_t *) chan->card;
3114 falc_t *pfalc = (falc_t *) & chan->falc;
3115 int ch = chan->channel;
3116
3117 cpc_writeb(card->hw.scabase + M_REG(CMD, ch), CMD_CH_RST);
3118 rx_dma_stop(card, ch);
3119 tx_dma_stop(card, ch);
3120
3121 if (card->hw.type == PC300_TE) {
3122 memset(pfalc, 0, sizeof(falc_t));
3123 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
3124 cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) &
3125 ~((CPLD_REG2_FALC_TX_CLK | CPLD_REG2_FALC_RX_CLK |
3126 CPLD_REG2_FALC_LED2) << (2 * ch)));
3127 /* Reset the FALC chip */
3128 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
3129 cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) |
3130 (CPLD_REG1_FALC_RESET << (2 * ch)));
3131 udelay(10000);
3132 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
3133 cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) &
3134 ~(CPLD_REG1_FALC_RESET << (2 * ch)));
3135 }
3136 }
3137
3138 int cpc_open(struct net_device *dev)
3139 {
3140 pc300dev_t *d = (pc300dev_t *) dev_to_hdlc(dev)->priv;
3141 struct ifreq ifr;
3142 int result;
3143
3144 #ifdef PC300_DEBUG_OTHER
3145 printk("pc300: cpc_open");
3146 #endif
3147
3148 result = hdlc_open(dev);
3149
3150 if (result)
3151 return result;
3152
3153 sprintf(ifr.ifr_name, "%s", dev->name);
3154 result = cpc_opench(d);
3155 if (result)
3156 goto err_out;
3157
3158 netif_start_queue(dev);
3159 return 0;
3160
3161 err_out:
3162 hdlc_close(dev);
3163 return result;
3164 }
3165
3166 static int cpc_close(struct net_device *dev)
3167 {
3168 pc300dev_t *d = (pc300dev_t *) dev_to_hdlc(dev)->priv;
3169 pc300ch_t *chan = (pc300ch_t *) d->chan;
3170 pc300_t *card = (pc300_t *) chan->card;
3171 unsigned long flags;
3172
3173 #ifdef PC300_DEBUG_OTHER
3174 printk("pc300: cpc_close");
3175 #endif
3176
3177 netif_stop_queue(dev);
3178
3179 CPC_LOCK(card, flags);
3180 cpc_closech(d);
3181 CPC_UNLOCK(card, flags);
3182
3183 hdlc_close(dev);
3184
3185 #ifdef CONFIG_PC300_MLPPP
3186 if (chan->conf.proto == PC300_PROTO_MLPPP) {
3187 cpc_tty_unregister_service(d);
3188 chan->conf.proto = 0xffff;
3189 }
3190 #endif
3191
3192 return 0;
3193 }
3194
3195 static u32 detect_ram(pc300_t * card)
3196 {
3197 u32 i;
3198 u8 data;
3199 void __iomem *rambase = card->hw.rambase;
3200
3201 card->hw.ramsize = PC300_RAMSIZE;
3202 /* Let's find out how much RAM is present on this board */
3203 for (i = 0; i < card->hw.ramsize; i++) {
3204 data = (u8)(i & 0xff);
3205 cpc_writeb(rambase + i, data);
3206 if (cpc_readb(rambase + i) != data) {
3207 break;
3208 }
3209 }
3210 return (i);
3211 }
3212
3213 static void plx_init(pc300_t * card)
3214 {
3215 struct RUNTIME_9050 __iomem *plx_ctl = card->hw.plxbase;
3216
3217 /* Reset PLX */
3218 cpc_writel(&plx_ctl->init_ctrl,
3219 cpc_readl(&plx_ctl->init_ctrl) | 0x40000000);
3220 udelay(10000L);
3221 cpc_writel(&plx_ctl->init_ctrl,
3222 cpc_readl(&plx_ctl->init_ctrl) & ~0x40000000);
3223
3224 /* Reload Config. Registers from EEPROM */
3225 cpc_writel(&plx_ctl->init_ctrl,
3226 cpc_readl(&plx_ctl->init_ctrl) | 0x20000000);
3227 udelay(10000L);
3228 cpc_writel(&plx_ctl->init_ctrl,
3229 cpc_readl(&plx_ctl->init_ctrl) & ~0x20000000);
3230
3231 }
3232
3233 static inline void show_version(void)
3234 {
3235 char *rcsvers, *rcsdate, *tmp;
3236
3237 rcsvers = strchr(rcsid, ' ');
3238 rcsvers++;
3239 tmp = strchr(rcsvers, ' ');
3240 *tmp++ = '\0';
3241 rcsdate = strchr(tmp, ' ');
3242 rcsdate++;
3243 tmp = strrchr(rcsdate, ' ');
3244 *tmp = '\0';
3245 printk(KERN_INFO "Cyclades-PC300 driver %s %s (built %s %s)\n",
3246 rcsvers, rcsdate, __DATE__, __TIME__);
3247 } /* show_version */
3248
3249 static void cpc_init_card(pc300_t * card)
3250 {
3251 int i, devcount = 0;
3252 static int board_nbr = 1;
3253
3254 /* Enable interrupts on the PCI bridge */
3255 plx_init(card);
3256 cpc_writew(card->hw.plxbase + card->hw.intctl_reg,
3257 cpc_readw(card->hw.plxbase + card->hw.intctl_reg) | 0x0040);
3258
3259 #ifdef USE_PCI_CLOCK
3260 /* Set board clock to PCI clock */
3261 cpc_writel(card->hw.plxbase + card->hw.gpioc_reg,
3262 cpc_readl(card->hw.plxbase + card->hw.gpioc_reg) | 0x00000004UL);
3263 card->hw.clock = PC300_PCI_CLOCK;
3264 #else
3265 /* Set board clock to internal oscillator clock */
3266 cpc_writel(card->hw.plxbase + card->hw.gpioc_reg,
3267 cpc_readl(card->hw.plxbase + card->hw.gpioc_reg) & ~0x00000004UL);
3268 card->hw.clock = PC300_OSC_CLOCK;
3269 #endif
3270
3271 /* Detect actual on-board RAM size */
3272 card->hw.ramsize = detect_ram(card);
3273
3274 /* Set Global SCA-II registers */
3275 cpc_writeb(card->hw.scabase + PCR, PCR_PR2);
3276 cpc_writeb(card->hw.scabase + BTCR, 0x10);
3277 cpc_writeb(card->hw.scabase + WCRL, 0);
3278 cpc_writeb(card->hw.scabase + DMER, 0x80);
3279
3280 if (card->hw.type == PC300_TE) {
3281 u8 reg1;
3282
3283 /* Check CPLD version */
3284 reg1 = cpc_readb(card->hw.falcbase + CPLD_REG1);
3285 cpc_writeb(card->hw.falcbase + CPLD_REG1, (reg1 + 0x5a));
3286 if (cpc_readb(card->hw.falcbase + CPLD_REG1) == reg1) {
3287 /* New CPLD */
3288 card->hw.cpld_id = cpc_readb(card->hw.falcbase + CPLD_ID_REG);
3289 card->hw.cpld_reg1 = CPLD_V2_REG1;
3290 card->hw.cpld_reg2 = CPLD_V2_REG2;
3291 } else {
3292 /* old CPLD */
3293 card->hw.cpld_id = 0;
3294 card->hw.cpld_reg1 = CPLD_REG1;
3295 card->hw.cpld_reg2 = CPLD_REG2;
3296 cpc_writeb(card->hw.falcbase + CPLD_REG1, reg1);
3297 }
3298
3299 /* Enable the board's global clock */
3300 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
3301 cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) |
3302 CPLD_REG1_GLOBAL_CLK);
3303
3304 }
3305
3306 for (i = 0; i < card->hw.nchan; i++) {
3307 pc300ch_t *chan = &card->chan[i];
3308 pc300dev_t *d = &chan->d;
3309 hdlc_device *hdlc;
3310 struct net_device *dev;
3311
3312 chan->card = card;
3313 chan->channel = i;
3314 chan->conf.phys_settings.clock_rate = 0;
3315 chan->conf.phys_settings.clock_type = CLOCK_EXT;
3316 chan->conf.proto_settings.encoding = ENCODING_NRZ;
3317 chan->conf.proto_settings.parity = PARITY_CRC16_PR1_CCITT;
3318 switch (card->hw.type) {
3319 case PC300_TE:
3320 chan->conf.media = IF_IFACE_T1;
3321 chan->conf.lcode = PC300_LC_B8ZS;
3322 chan->conf.fr_mode = PC300_FR_ESF;
3323 chan->conf.lbo = PC300_LBO_0_DB;
3324 chan->conf.rx_sens = PC300_RX_SENS_SH;
3325 chan->conf.tslot_bitmap = 0xffffffffUL;
3326 break;
3327
3328 case PC300_X21:
3329 chan->conf.media = IF_IFACE_X21;
3330 break;
3331
3332 case PC300_RSV:
3333 default:
3334 chan->conf.media = IF_IFACE_V35;
3335 break;
3336 }
3337 chan->conf.proto = IF_PROTO_PPP;
3338 chan->tx_first_bd = 0;
3339 chan->tx_next_bd = 0;
3340 chan->rx_first_bd = 0;
3341 chan->rx_last_bd = N_DMA_RX_BUF - 1;
3342 chan->nfree_tx_bd = N_DMA_TX_BUF;
3343
3344 d->chan = chan;
3345 d->trace_on = 0;
3346 d->line_on = 0;
3347 d->line_off = 0;
3348
3349 dev = alloc_hdlcdev(d);
3350 if (dev == NULL)
3351 continue;
3352
3353 hdlc = dev_to_hdlc(dev);
3354 hdlc->xmit = cpc_queue_xmit;
3355 hdlc->attach = cpc_attach;
3356 d->dev = dev;
3357 dev->mem_start = card->hw.ramphys;
3358 dev->mem_end = card->hw.ramphys + card->hw.ramsize - 1;
3359 dev->irq = card->hw.irq;
3360 dev->init = NULL;
3361 dev->tx_queue_len = PC300_TX_QUEUE_LEN;
3362 dev->mtu = PC300_DEF_MTU;
3363
3364 dev->open = cpc_open;
3365 dev->stop = cpc_close;
3366 dev->tx_timeout = cpc_tx_timeout;
3367 dev->watchdog_timeo = PC300_TX_TIMEOUT;
3368 dev->set_multicast_list = NULL;
3369 dev->set_mac_address = NULL;
3370 dev->change_mtu = cpc_change_mtu;
3371 dev->do_ioctl = cpc_ioctl;
3372
3373 if (register_hdlc_device(dev) == 0) {
3374 printk("%s: Cyclades-PC300/", dev->name);
3375 switch (card->hw.type) {
3376 case PC300_TE:
3377 if (card->hw.bus == PC300_PMC) {
3378 printk("TE-M");
3379 } else {
3380 printk("TE ");
3381 }
3382 break;
3383
3384 case PC300_X21:
3385 printk("X21 ");
3386 break;
3387
3388 case PC300_RSV:
3389 default:
3390 printk("RSV ");
3391 break;
3392 }
3393 printk (" #%d, %dKB of RAM at 0x%08x, IRQ%d, channel %d.\n",
3394 board_nbr, card->hw.ramsize / 1024,
3395 card->hw.ramphys, card->hw.irq, i + 1);
3396 devcount++;
3397 } else {
3398 printk ("Dev%d on card(0x%08x): unable to allocate i/f name.\n",
3399 i + 1, card->hw.ramphys);
3400 free_netdev(dev);
3401 continue;
3402 }
3403 }
3404 spin_lock_init(&card->card_lock);
3405
3406 board_nbr++;
3407 }
3408
3409 static int __devinit
3410 cpc_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3411 {
3412 static int first_time = 1;
3413 int err, eeprom_outdated = 0;
3414 u16 device_id;
3415 pc300_t *card;
3416
3417 if (first_time) {
3418 first_time = 0;
3419 show_version();
3420 #ifdef CONFIG_PC300_MLPPP
3421 cpc_tty_reset_var();
3422 #endif
3423 }
3424
3425 if ((err = pci_enable_device(pdev)) < 0)
3426 return err;
3427
3428 card = kzalloc(sizeof(pc300_t), GFP_KERNEL);
3429 if (card == NULL) {
3430 printk("PC300 found at RAM 0x%016llx, "
3431 "but could not allocate card structure.\n",
3432 (unsigned long long)pci_resource_start(pdev, 3));
3433 err = -ENOMEM;
3434 goto err_disable_dev;
3435 }
3436
3437 err = -ENODEV;
3438
3439 /* read PCI configuration area */
3440 device_id = ent->device;
3441 card->hw.irq = pdev->irq;
3442 card->hw.iophys = pci_resource_start(pdev, 1);
3443 card->hw.iosize = pci_resource_len(pdev, 1);
3444 card->hw.scaphys = pci_resource_start(pdev, 2);
3445 card->hw.scasize = pci_resource_len(pdev, 2);
3446 card->hw.ramphys = pci_resource_start(pdev, 3);
3447 card->hw.alloc_ramsize = pci_resource_len(pdev, 3);
3448 card->hw.falcphys = pci_resource_start(pdev, 4);
3449 card->hw.falcsize = pci_resource_len(pdev, 4);
3450 card->hw.plxphys = pci_resource_start(pdev, 5);
3451 card->hw.plxsize = pci_resource_len(pdev, 5);
3452
3453 switch (device_id) {
3454 case PCI_DEVICE_ID_PC300_RX_1:
3455 case PCI_DEVICE_ID_PC300_TE_1:
3456 case PCI_DEVICE_ID_PC300_TE_M_1:
3457 card->hw.nchan = 1;
3458 break;
3459
3460 case PCI_DEVICE_ID_PC300_RX_2:
3461 case PCI_DEVICE_ID_PC300_TE_2:
3462 case PCI_DEVICE_ID_PC300_TE_M_2:
3463 default:
3464 card->hw.nchan = PC300_MAXCHAN;
3465 break;
3466 }
3467 #ifdef PC300_DEBUG_PCI
3468 printk("cpc (bus=0x0%x,pci_id=0x%x,", pdev->bus->number, pdev->devfn);
3469 printk("rev_id=%d) IRQ%d\n", pdev->revision, card->hw.irq);
3470 printk("cpc:found ramaddr=0x%08lx plxaddr=0x%08lx "
3471 "ctladdr=0x%08lx falcaddr=0x%08lx\n",
3472 card->hw.ramphys, card->hw.plxphys, card->hw.scaphys,
3473 card->hw.falcphys);
3474 #endif
3475 /* Although we don't use this I/O region, we should
3476 * request it from the kernel anyway, to avoid problems
3477 * with other drivers accessing it. */
3478 if (!request_region(card->hw.iophys, card->hw.iosize, "PLX Registers")) {
3479 /* In case we can't allocate it, warn user */
3480 printk("WARNING: couldn't allocate I/O region for PC300 board "
3481 "at 0x%08x!\n", card->hw.ramphys);
3482 }
3483
3484 if (card->hw.plxphys) {
3485 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, card->hw.plxphys);
3486 } else {
3487 eeprom_outdated = 1;
3488 card->hw.plxphys = pci_resource_start(pdev, 0);
3489 card->hw.plxsize = pci_resource_len(pdev, 0);
3490 }
3491
3492 if (!request_mem_region(card->hw.plxphys, card->hw.plxsize,
3493 "PLX Registers")) {
3494 printk("PC300 found at RAM 0x%08x, "
3495 "but could not allocate PLX mem region.\n",
3496 card->hw.ramphys);
3497 goto err_release_io;
3498 }
3499 if (!request_mem_region(card->hw.ramphys, card->hw.alloc_ramsize,
3500 "On-board RAM")) {
3501 printk("PC300 found at RAM 0x%08x, "
3502 "but could not allocate RAM mem region.\n",
3503 card->hw.ramphys);
3504 goto err_release_plx;
3505 }
3506 if (!request_mem_region(card->hw.scaphys, card->hw.scasize,
3507 "SCA-II Registers")) {
3508 printk("PC300 found at RAM 0x%08x, "
3509 "but could not allocate SCA mem region.\n",
3510 card->hw.ramphys);
3511 goto err_release_ram;
3512 }
3513
3514 card->hw.plxbase = ioremap(card->hw.plxphys, card->hw.plxsize);
3515 card->hw.rambase = ioremap(card->hw.ramphys, card->hw.alloc_ramsize);
3516 card->hw.scabase = ioremap(card->hw.scaphys, card->hw.scasize);
3517 switch (device_id) {
3518 case PCI_DEVICE_ID_PC300_TE_1:
3519 case PCI_DEVICE_ID_PC300_TE_2:
3520 case PCI_DEVICE_ID_PC300_TE_M_1:
3521 case PCI_DEVICE_ID_PC300_TE_M_2:
3522 request_mem_region(card->hw.falcphys, card->hw.falcsize,
3523 "FALC Registers");
3524 card->hw.falcbase = ioremap(card->hw.falcphys, card->hw.falcsize);
3525 break;
3526
3527 case PCI_DEVICE_ID_PC300_RX_1:
3528 case PCI_DEVICE_ID_PC300_RX_2:
3529 default:
3530 card->hw.falcbase = NULL;
3531 break;
3532 }
3533
3534 #ifdef PC300_DEBUG_PCI
3535 printk("cpc: relocate ramaddr=0x%08lx plxaddr=0x%08lx "
3536 "ctladdr=0x%08lx falcaddr=0x%08lx\n",
3537 card->hw.rambase, card->hw.plxbase, card->hw.scabase,
3538 card->hw.falcbase);
3539 #endif
3540
3541 /* Set PCI drv pointer to the card structure */
3542 pci_set_drvdata(pdev, card);
3543
3544 /* Set board type */
3545 switch (device_id) {
3546 case PCI_DEVICE_ID_PC300_TE_1:
3547 case PCI_DEVICE_ID_PC300_TE_2:
3548 case PCI_DEVICE_ID_PC300_TE_M_1:
3549 case PCI_DEVICE_ID_PC300_TE_M_2:
3550 card->hw.type = PC300_TE;
3551
3552 if ((device_id == PCI_DEVICE_ID_PC300_TE_M_1) ||
3553 (device_id == PCI_DEVICE_ID_PC300_TE_M_2)) {
3554 card->hw.bus = PC300_PMC;
3555 /* Set PLX register offsets */
3556 card->hw.gpioc_reg = 0x54;
3557 card->hw.intctl_reg = 0x4c;
3558 } else {
3559 card->hw.bus = PC300_PCI;
3560 /* Set PLX register offsets */
3561 card->hw.gpioc_reg = 0x50;
3562 card->hw.intctl_reg = 0x4c;
3563 }
3564 break;
3565
3566 case PCI_DEVICE_ID_PC300_RX_1:
3567 case PCI_DEVICE_ID_PC300_RX_2:
3568 default:
3569 card->hw.bus = PC300_PCI;
3570 /* Set PLX register offsets */
3571 card->hw.gpioc_reg = 0x50;
3572 card->hw.intctl_reg = 0x4c;
3573
3574 if ((cpc_readl(card->hw.plxbase + card->hw.gpioc_reg) & PC300_CTYPE_MASK)) {
3575 card->hw.type = PC300_X21;
3576 } else {
3577 card->hw.type = PC300_RSV;
3578 }
3579 break;
3580 }
3581
3582 /* Allocate IRQ */
3583 if (request_irq(card->hw.irq, cpc_intr, IRQF_SHARED, "Cyclades-PC300", card)) {
3584 printk ("PC300 found at RAM 0x%08x, but could not allocate IRQ%d.\n",
3585 card->hw.ramphys, card->hw.irq);
3586 goto err_io_unmap;
3587 }
3588
3589 cpc_init_card(card);
3590
3591 if (eeprom_outdated)
3592 printk("WARNING: PC300 with outdated EEPROM.\n");
3593 return 0;
3594
3595 err_io_unmap:
3596 iounmap(card->hw.plxbase);
3597 iounmap(card->hw.scabase);
3598 iounmap(card->hw.rambase);
3599 if (card->hw.type == PC300_TE) {
3600 iounmap(card->hw.falcbase);
3601 release_mem_region(card->hw.falcphys, card->hw.falcsize);
3602 }
3603 release_mem_region(card->hw.scaphys, card->hw.scasize);
3604 err_release_ram:
3605 release_mem_region(card->hw.ramphys, card->hw.alloc_ramsize);
3606 err_release_plx:
3607 release_mem_region(card->hw.plxphys, card->hw.plxsize);
3608 err_release_io:
3609 release_region(card->hw.iophys, card->hw.iosize);
3610 kfree(card);
3611 err_disable_dev:
3612 pci_disable_device(pdev);
3613 return err;
3614 }
3615
3616 static void __devexit cpc_remove_one(struct pci_dev *pdev)
3617 {
3618 pc300_t *card = pci_get_drvdata(pdev);
3619
3620 if (card->hw.rambase) {
3621 int i;
3622
3623 /* Disable interrupts on the PCI bridge */
3624 cpc_writew(card->hw.plxbase + card->hw.intctl_reg,
3625 cpc_readw(card->hw.plxbase + card->hw.intctl_reg) & ~(0x0040));
3626
3627 for (i = 0; i < card->hw.nchan; i++) {
3628 unregister_hdlc_device(card->chan[i].d.dev);
3629 }
3630 iounmap(card->hw.plxbase);
3631 iounmap(card->hw.scabase);
3632 iounmap(card->hw.rambase);
3633 release_mem_region(card->hw.plxphys, card->hw.plxsize);
3634 release_mem_region(card->hw.ramphys, card->hw.alloc_ramsize);
3635 release_mem_region(card->hw.scaphys, card->hw.scasize);
3636 release_region(card->hw.iophys, card->hw.iosize);
3637 if (card->hw.type == PC300_TE) {
3638 iounmap(card->hw.falcbase);
3639 release_mem_region(card->hw.falcphys, card->hw.falcsize);
3640 }
3641 for (i = 0; i < card->hw.nchan; i++)
3642 if (card->chan[i].d.dev)
3643 free_netdev(card->chan[i].d.dev);
3644 if (card->hw.irq)
3645 free_irq(card->hw.irq, card);
3646 kfree(card);
3647 pci_disable_device(pdev);
3648 }
3649 }
3650
3651 static struct pci_driver cpc_driver = {
3652 .name = "pc300",
3653 .id_table = cpc_pci_dev_id,
3654 .probe = cpc_init_one,
3655 .remove = __devexit_p(cpc_remove_one),
3656 };
3657
3658 static int __init cpc_init(void)
3659 {
3660 return pci_register_driver(&cpc_driver);
3661 }
3662
3663 static void __exit cpc_cleanup_module(void)
3664 {
3665 pci_unregister_driver(&cpc_driver);
3666 }
3667
3668 module_init(cpc_init);
3669 module_exit(cpc_cleanup_module);
3670
3671 MODULE_DESCRIPTION("Cyclades-PC300 cards driver");
3672 MODULE_AUTHOR( "Author: Ivan Passos <ivan@cyclades.com>\r\n"
3673 "Maintainer: PC300 Maintainer <pc300@cyclades.com");
3674 MODULE_LICENSE("GPL");
3675
Linux kernel - Deliverables
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