drivers/net/wireless/ath/ath10k/core.h

   1 /*
   2  * Copyright (c) 2005-2011 Atheros Communications Inc.
   3  * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
   4  *
   5  * Permission to use, copy, modify, and/or distribute this software for any
   6  * purpose with or without fee is hereby granted, provided that the above
   7  * copyright notice and this permission notice appear in all copies.
   8  *
   9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16  */
  17
  18 #ifndef _CORE_H_
  19 #define _CORE_H_
  20
  21 #include <linux/completion.h>
  22 #include <linux/if_ether.h>
  23 #include <linux/types.h>
  24 #include <linux/pci.h>
  25 #include <linux/uuid.h>
  26 #include <linux/time.h>
  27
  28 #include "htt.h"
  29 #include "htc.h"
  30 #include "hw.h"
  31 #include "targaddrs.h"
  32 #include "wmi.h"
  33 #include "../ath.h"
  34 #include "../regd.h"
  35 #include "../dfs_pattern_detector.h"
  36 #include "spectral.h"
  37 #include "thermal.h"
  38 #include "wow.h"
  39 #include "swap.h"
  40
  41 #define MS(_v, _f) (((_v) & _f##_MASK) >> _f##_LSB)
  42 #define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK)
  43 #define WO(_f)      ((_f##_OFFSET) >> 2)
  44
  45 #define ATH10K_SCAN_ID 0
  46 #define WMI_READY_TIMEOUT (5 * HZ)
  47 #define ATH10K_FLUSH_TIMEOUT_HZ (5*HZ)
  48 #define ATH10K_CONNECTION_LOSS_HZ (3*HZ)
  49 #define ATH10K_NUM_CHANS 39
  50
  51 /* Antenna noise floor */
  52 #define ATH10K_DEFAULT_NOISE_FLOOR -95
  53
  54 #define ATH10K_MAX_NUM_MGMT_PENDING 128
  55
  56 /* number of failed packets (20 packets with 16 sw reties each) */
  57 #define ATH10K_KICKOUT_THRESHOLD (20 * 16)
  58
  59 /*
  60  * Use insanely high numbers to make sure that the firmware implementation
  61  * won't start, we have the same functionality already in hostapd. Unit
  62  * is seconds.
  63  */
  64 #define ATH10K_KEEPALIVE_MIN_IDLE 3747
  65 #define ATH10K_KEEPALIVE_MAX_IDLE 3895
  66 #define ATH10K_KEEPALIVE_MAX_UNRESPONSIVE 3900
  67
  68 struct ath10k;
  69
  70 enum ath10k_bus {
  71         ATH10K_BUS_PCI,
  72 };
  73
  74 static inline const char *ath10k_bus_str(enum ath10k_bus bus)
  75 {
  76         switch (bus) {
  77         case ATH10K_BUS_PCI:
  78                 return "pci";
  79         }
  80
  81         return "unknown";
  82 }
  83
  84 struct ath10k_skb_cb {
  85         dma_addr_t paddr;
  86         u8 eid;
  87         u8 vdev_id;
  88         enum ath10k_hw_txrx_mode txmode;
  89         bool is_protected;
  90
  91         struct {
  92                 u8 tid;
  93                 u16 freq;
  94                 bool is_offchan;
  95                 bool nohwcrypt;
  96                 struct ath10k_htt_txbuf *txbuf;
  97                 u32 txbuf_paddr;
  98         } __packed htt;
  99
 100         struct {
 101                 bool dtim_zero;
 102                 bool deliver_cab;
 103         } bcn;
 104 } __packed;
 105
 106 struct ath10k_skb_rxcb {
 107         dma_addr_t paddr;
 108         struct hlist_node hlist;
 109 };
 110
 111 static inline struct ath10k_skb_cb *ATH10K_SKB_CB(struct sk_buff *skb)
 112 {
 113         BUILD_BUG_ON(sizeof(struct ath10k_skb_cb) >
 114                      IEEE80211_TX_INFO_DRIVER_DATA_SIZE);
 115         return (struct ath10k_skb_cb *)&IEEE80211_SKB_CB(skb)->driver_data;
 116 }
 117
 118 static inline struct ath10k_skb_rxcb *ATH10K_SKB_RXCB(struct sk_buff *skb)
 119 {
 120         BUILD_BUG_ON(sizeof(struct ath10k_skb_rxcb) > sizeof(skb->cb));
 121         return (struct ath10k_skb_rxcb *)skb->cb;
 122 }
 123
 124 #define ATH10K_RXCB_SKB(rxcb) \
 125                 container_of((void *)rxcb, struct sk_buff, cb)
 126
 127 static inline u32 host_interest_item_address(u32 item_offset)
 128 {
 129         return QCA988X_HOST_INTEREST_ADDRESS + item_offset;
 130 }
 131
 132 struct ath10k_bmi {
 133         bool done_sent;
 134 };
 135
 136 struct ath10k_mem_chunk {
 137         void *vaddr;
 138         dma_addr_t paddr;
 139         u32 len;
 140         u32 req_id;
 141 };
 142
 143 struct ath10k_wmi {
 144         enum ath10k_fw_wmi_op_version op_version;
 145         enum ath10k_htc_ep_id eid;
 146         struct completion service_ready;
 147         struct completion unified_ready;
 148         wait_queue_head_t tx_credits_wq;
 149         DECLARE_BITMAP(svc_map, WMI_SERVICE_MAX);
 150         struct wmi_cmd_map *cmd;
 151         struct wmi_vdev_param_map *vdev_param;
 152         struct wmi_pdev_param_map *pdev_param;
 153         const struct wmi_ops *ops;
 154         const struct wmi_peer_flags_map *peer_flags;
 155
 156         u32 num_mem_chunks;
 157         u32 rx_decap_mode;
 158         struct ath10k_mem_chunk mem_chunks[WMI_MAX_MEM_REQS];
 159 };
 160
 161 struct ath10k_fw_stats_peer {
 162         struct list_head list;
 163
 164         u8 peer_macaddr[ETH_ALEN];
 165         u32 peer_rssi;
 166         u32 peer_tx_rate;
 167         u32 peer_rx_rate; /* 10x only */
 168 };
 169
 170 struct ath10k_fw_stats_vdev {
 171         struct list_head list;
 172
 173         u32 vdev_id;
 174         u32 beacon_snr;
 175         u32 data_snr;
 176         u32 num_tx_frames[4];
 177         u32 num_rx_frames;
 178         u32 num_tx_frames_retries[4];
 179         u32 num_tx_frames_failures[4];
 180         u32 num_rts_fail;
 181         u32 num_rts_success;
 182         u32 num_rx_err;
 183         u32 num_rx_discard;
 184         u32 num_tx_not_acked;
 185         u32 tx_rate_history[10];
 186         u32 beacon_rssi_history[10];
 187 };
 188
 189 struct ath10k_fw_stats_pdev {
 190         struct list_head list;
 191
 192         /* PDEV stats */
 193         s32 ch_noise_floor;
 194         u32 tx_frame_count;
 195         u32 rx_frame_count;
 196         u32 rx_clear_count;
 197         u32 cycle_count;
 198         u32 phy_err_count;
 199         u32 chan_tx_power;
 200         u32 ack_rx_bad;
 201         u32 rts_bad;
 202         u32 rts_good;
 203         u32 fcs_bad;
 204         u32 no_beacons;
 205         u32 mib_int_count;
 206
 207         /* PDEV TX stats */
 208         s32 comp_queued;
 209         s32 comp_delivered;
 210         s32 msdu_enqued;
 211         s32 mpdu_enqued;
 212         s32 wmm_drop;
 213         s32 local_enqued;
 214         s32 local_freed;
 215         s32 hw_queued;
 216         s32 hw_reaped;
 217         s32 underrun;
 218         u32 hw_paused;
 219         s32 tx_abort;
 220         s32 mpdus_requed;
 221         u32 tx_ko;
 222         u32 data_rc;
 223         u32 self_triggers;
 224         u32 sw_retry_failure;
 225         u32 illgl_rate_phy_err;
 226         u32 pdev_cont_xretry;
 227         u32 pdev_tx_timeout;
 228         u32 pdev_resets;
 229         u32 phy_underrun;
 230         u32 txop_ovf;
 231         u32 seq_posted;
 232         u32 seq_failed_queueing;
 233         u32 seq_completed;
 234         u32 seq_restarted;
 235         u32 mu_seq_posted;
 236         u32 mpdus_sw_flush;
 237         u32 mpdus_hw_filter;
 238         u32 mpdus_truncated;
 239         u32 mpdus_ack_failed;
 240         u32 mpdus_expired;
 241
 242         /* PDEV RX stats */
 243         s32 mid_ppdu_route_change;
 244         s32 status_rcvd;
 245         s32 r0_frags;
 246         s32 r1_frags;
 247         s32 r2_frags;
 248         s32 r3_frags;
 249         s32 htt_msdus;
 250         s32 htt_mpdus;
 251         s32 loc_msdus;
 252         s32 loc_mpdus;
 253         s32 oversize_amsdu;
 254         s32 phy_errs;
 255         s32 phy_err_drop;
 256         s32 mpdu_errs;
 257         s32 rx_ovfl_errs;
 258 };
 259
 260 struct ath10k_fw_stats {
 261         struct list_head pdevs;
 262         struct list_head vdevs;
 263         struct list_head peers;
 264 };
 265
 266 #define ATH10K_TPC_TABLE_TYPE_FLAG      1
 267 #define ATH10K_TPC_PREAM_TABLE_END      0xFFFF
 268
 269 struct ath10k_tpc_table {
 270         u32 pream_idx[WMI_TPC_RATE_MAX];
 271         u8 rate_code[WMI_TPC_RATE_MAX];
 272         char tpc_value[WMI_TPC_RATE_MAX][WMI_TPC_TX_N_CHAIN * WMI_TPC_BUF_SIZE];
 273 };
 274
 275 struct ath10k_tpc_stats {
 276         u32 reg_domain;
 277         u32 chan_freq;
 278         u32 phy_mode;
 279         u32 twice_antenna_reduction;
 280         u32 twice_max_rd_power;
 281         s32 twice_antenna_gain;
 282         u32 power_limit;
 283         u32 num_tx_chain;
 284         u32 ctl;
 285         u32 rate_max;
 286         u8 flag[WMI_TPC_FLAG];
 287         struct ath10k_tpc_table tpc_table[WMI_TPC_FLAG];
 288 };
 289
 290 struct ath10k_dfs_stats {
 291         u32 phy_errors;
 292         u32 pulses_total;
 293         u32 pulses_detected;
 294         u32 pulses_discarded;
 295         u32 radar_detected;
 296 };
 297
 298 #define ATH10K_MAX_NUM_PEER_IDS (1 << 11) /* htt rx_desc limit */
 299
 300 struct ath10k_peer {
 301         struct list_head list;
 302         int vdev_id;
 303         u8 addr[ETH_ALEN];
 304         DECLARE_BITMAP(peer_ids, ATH10K_MAX_NUM_PEER_IDS);
 305
 306         /* protected by ar->data_lock */
 307         struct ieee80211_key_conf *keys[WMI_MAX_KEY_INDEX + 1];
 308 };
 309
 310 struct ath10k_sta {
 311         struct ath10k_vif *arvif;
 312
 313         /* the following are protected by ar->data_lock */
 314         u32 changed; /* IEEE80211_RC_* */
 315         u32 bw;
 316         u32 nss;
 317         u32 smps;
 318
 319         struct work_struct update_wk;
 320
 321 #ifdef CONFIG_MAC80211_DEBUGFS
 322         /* protected by conf_mutex */
 323         bool aggr_mode;
 324 #endif
 325 };
 326
 327 #define ATH10K_VDEV_SETUP_TIMEOUT_HZ (5*HZ)
 328
 329 enum ath10k_beacon_state {
 330         ATH10K_BEACON_SCHEDULED = 0,
 331         ATH10K_BEACON_SENDING,
 332         ATH10K_BEACON_SENT,
 333 };
 334
 335 struct ath10k_vif {
 336         struct list_head list;
 337
 338         u32 vdev_id;
 339         enum wmi_vdev_type vdev_type;
 340         enum wmi_vdev_subtype vdev_subtype;
 341         u32 beacon_interval;
 342         u32 dtim_period;
 343         struct sk_buff *beacon;
 344         /* protected by data_lock */
 345         enum ath10k_beacon_state beacon_state;
 346         void *beacon_buf;
 347         dma_addr_t beacon_paddr;
 348         unsigned long tx_paused; /* arbitrary values defined by target */
 349
 350         struct ath10k *ar;
 351         struct ieee80211_vif *vif;
 352
 353         bool is_started;
 354         bool is_up;
 355         bool spectral_enabled;
 356         bool ps;
 357         u32 aid;
 358         u8 bssid[ETH_ALEN];
 359
 360         struct ieee80211_key_conf *wep_keys[WMI_MAX_KEY_INDEX + 1];
 361         s8 def_wep_key_idx;
 362
 363         u16 tx_seq_no;
 364
 365         union {
 366                 struct {
 367                         u32 uapsd;
 368                 } sta;
 369                 struct {
 370                         /* 512 stations */
 371                         u8 tim_bitmap[64];
 372                         u8 tim_len;
 373                         u32 ssid_len;
 374                         u8 ssid[IEEE80211_MAX_SSID_LEN];
 375                         bool hidden_ssid;
 376                         /* P2P_IE with NoA attribute for P2P_GO case */
 377                         u32 noa_len;
 378                         u8 *noa_data;
 379                 } ap;
 380         } u;
 381
 382         bool use_cts_prot;
 383         bool nohwcrypt;
 384         int num_legacy_stations;
 385         int txpower;
 386         struct wmi_wmm_params_all_arg wmm_params;
 387         struct work_struct ap_csa_work;
 388         struct delayed_work connection_loss_work;
 389         struct cfg80211_bitrate_mask bitrate_mask;
 390 };
 391
 392 struct ath10k_vif_iter {
 393         u32 vdev_id;
 394         struct ath10k_vif *arvif;
 395 };
 396
 397 /* used for crash-dump storage, protected by data-lock */
 398 struct ath10k_fw_crash_data {
 399         bool crashed_since_read;
 400
 401         uuid_le uuid;
 402         struct timespec timestamp;
 403         __le32 registers[REG_DUMP_COUNT_QCA988X];
 404 };
 405
 406 struct ath10k_debug {
 407         struct dentry *debugfs_phy;
 408
 409         struct ath10k_fw_stats fw_stats;
 410         struct completion fw_stats_complete;
 411         bool fw_stats_done;
 412
 413         unsigned long htt_stats_mask;
 414         struct delayed_work htt_stats_dwork;
 415         struct ath10k_dfs_stats dfs_stats;
 416         struct ath_dfs_pool_stats dfs_pool_stats;
 417
 418         /* used for tpc-dump storage, protected by data-lock */
 419         struct ath10k_tpc_stats *tpc_stats;
 420
 421         struct completion tpc_complete;
 422
 423         /* protected by conf_mutex */
 424         u32 fw_dbglog_mask;
 425         u32 fw_dbglog_level;
 426         u32 pktlog_filter;
 427         u32 reg_addr;
 428         u32 nf_cal_period;
 429
 430         struct ath10k_fw_crash_data *fw_crash_data;
 431 };
 432
 433 enum ath10k_state {
 434         ATH10K_STATE_OFF = 0,
 435         ATH10K_STATE_ON,
 436
 437         /* When doing firmware recovery the device is first powered down.
 438          * mac80211 is supposed to call in to start() hook later on. It is
 439          * however possible that driver unloading and firmware crash overlap.
 440          * mac80211 can wait on conf_mutex in stop() while the device is
 441          * stopped in ath10k_core_restart() work holding conf_mutex. The state
 442          * RESTARTED means that the device is up and mac80211 has started hw
 443          * reconfiguration. Once mac80211 is done with the reconfiguration we
 444          * set the state to STATE_ON in reconfig_complete(). */
 445         ATH10K_STATE_RESTARTING,
 446         ATH10K_STATE_RESTARTED,
 447
 448         /* The device has crashed while restarting hw. This state is like ON
 449          * but commands are blocked in HTC and -ECOMM response is given. This
 450          * prevents completion timeouts and makes the driver more responsive to
 451          * userspace commands. This is also prevents recursive recovery. */
 452         ATH10K_STATE_WEDGED,
 453
 454         /* factory tests */
 455         ATH10K_STATE_UTF,
 456 };
 457
 458 enum ath10k_firmware_mode {
 459         /* the default mode, standard 802.11 functionality */
 460         ATH10K_FIRMWARE_MODE_NORMAL,
 461
 462         /* factory tests etc */
 463         ATH10K_FIRMWARE_MODE_UTF,
 464 };
 465
 466 enum ath10k_fw_features {
 467         /* wmi_mgmt_rx_hdr contains extra RSSI information */
 468         ATH10K_FW_FEATURE_EXT_WMI_MGMT_RX = 0,
 469
 470         /* Firmware from 10X branch. Deprecated, don't use in new code. */
 471         ATH10K_FW_FEATURE_WMI_10X = 1,
 472
 473         /* firmware support tx frame management over WMI, otherwise it's HTT */
 474         ATH10K_FW_FEATURE_HAS_WMI_MGMT_TX = 2,
 475
 476         /* Firmware does not support P2P */
 477         ATH10K_FW_FEATURE_NO_P2P = 3,
 478
 479         /* Firmware 10.2 feature bit. The ATH10K_FW_FEATURE_WMI_10X feature
 480          * bit is required to be set as well. Deprecated, don't use in new
 481          * code.
 482          */
 483         ATH10K_FW_FEATURE_WMI_10_2 = 4,
 484
 485         /* Some firmware revisions lack proper multi-interface client powersave
 486          * implementation. Enabling PS could result in connection drops,
 487          * traffic stalls, etc.
 488          */
 489         ATH10K_FW_FEATURE_MULTI_VIF_PS_SUPPORT = 5,
 490
 491         /* Some firmware revisions have an incomplete WoWLAN implementation
 492          * despite WMI service bit being advertised. This feature flag is used
 493          * to distinguish whether WoWLAN is really supported or not.
 494          */
 495         ATH10K_FW_FEATURE_WOWLAN_SUPPORT = 6,
 496
 497         /* Don't trust error code from otp.bin */
 498         ATH10K_FW_FEATURE_IGNORE_OTP_RESULT = 7,
 499
 500         /* Some firmware revisions pad 4th hw address to 4 byte boundary making
 501          * it 8 bytes long in Native Wifi Rx decap.
 502          */
 503         ATH10K_FW_FEATURE_NO_NWIFI_DECAP_4ADDR_PADDING = 8,
 504
 505         /* Firmware supports bypassing PLL setting on init. */
 506         ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT = 9,
 507
 508         /* Raw mode support. If supported, FW supports receiving and trasmitting
 509          * frames in raw mode.
 510          */
 511         ATH10K_FW_FEATURE_RAW_MODE_SUPPORT = 10,
 512
 513         /* Firmware Supports Adaptive CCA*/
 514         ATH10K_FW_FEATURE_SUPPORTS_ADAPTIVE_CCA = 11,
 515
 516         /* Firmware supports management frame protection */
 517         ATH10K_FW_FEATURE_MFP_SUPPORT = 12,
 518
 519         /* keep last */
 520         ATH10K_FW_FEATURE_COUNT,
 521 };
 522
 523 enum ath10k_dev_flags {
 524         /* Indicates that ath10k device is during CAC phase of DFS */
 525         ATH10K_CAC_RUNNING,
 526         ATH10K_FLAG_CORE_REGISTERED,
 527
 528         /* Device has crashed and needs to restart. This indicates any pending
 529          * waiters should immediately cancel instead of waiting for a time out.
 530          */
 531         ATH10K_FLAG_CRASH_FLUSH,
 532
 533         /* Use Raw mode instead of native WiFi Tx/Rx encap mode.
 534          * Raw mode supports both hardware and software crypto. Native WiFi only
 535          * supports hardware crypto.
 536          */
 537         ATH10K_FLAG_RAW_MODE,
 538
 539         /* Disable HW crypto engine */
 540         ATH10K_FLAG_HW_CRYPTO_DISABLED,
 541
 542         /* Bluetooth coexistance enabled */
 543         ATH10K_FLAG_BTCOEX,
 544 };
 545
 546 enum ath10k_cal_mode {
 547         ATH10K_CAL_MODE_FILE,
 548         ATH10K_CAL_MODE_OTP,
 549         ATH10K_CAL_MODE_DT,
 550 };
 551
 552 enum ath10k_crypt_mode {
 553         /* Only use hardware crypto engine */
 554         ATH10K_CRYPT_MODE_HW,
 555         /* Only use software crypto engine */
 556         ATH10K_CRYPT_MODE_SW,
 557 };
 558
 559 static inline const char *ath10k_cal_mode_str(enum ath10k_cal_mode mode)
 560 {
 561         switch (mode) {
 562         case ATH10K_CAL_MODE_FILE:
 563                 return "file";
 564         case ATH10K_CAL_MODE_OTP:
 565                 return "otp";
 566         case ATH10K_CAL_MODE_DT:
 567                 return "dt";
 568         }
 569
 570         return "unknown";
 571 }
 572
 573 enum ath10k_scan_state {
 574         ATH10K_SCAN_IDLE,
 575         ATH10K_SCAN_STARTING,
 576         ATH10K_SCAN_RUNNING,
 577         ATH10K_SCAN_ABORTING,
 578 };
 579
 580 static inline const char *ath10k_scan_state_str(enum ath10k_scan_state state)
 581 {
 582         switch (state) {
 583         case ATH10K_SCAN_IDLE:
 584                 return "idle";
 585         case ATH10K_SCAN_STARTING:
 586                 return "starting";
 587         case ATH10K_SCAN_RUNNING:
 588                 return "running";
 589         case ATH10K_SCAN_ABORTING:
 590                 return "aborting";
 591         }
 592
 593         return "unknown";
 594 }
 595
 596 enum ath10k_tx_pause_reason {
 597         ATH10K_TX_PAUSE_Q_FULL,
 598         ATH10K_TX_PAUSE_MAX,
 599 };
 600
 601 struct ath10k {
 602         struct ath_common ath_common;
 603         struct ieee80211_hw *hw;
 604         struct device *dev;
 605         u8 mac_addr[ETH_ALEN];
 606
 607         enum ath10k_hw_rev hw_rev;
 608         u16 dev_id;
 609         u32 chip_id;
 610         u32 target_version;
 611         u8 fw_version_major;
 612         u32 fw_version_minor;
 613         u16 fw_version_release;
 614         u16 fw_version_build;
 615         u32 fw_stats_req_mask;
 616         u32 phy_capability;
 617         u32 hw_min_tx_power;
 618         u32 hw_max_tx_power;
 619         u32 ht_cap_info;
 620         u32 vht_cap_info;
 621         u32 num_rf_chains;
 622         u32 max_spatial_stream;
 623         /* protected by conf_mutex */
 624         bool ani_enabled;
 625
 626         DECLARE_BITMAP(fw_features, ATH10K_FW_FEATURE_COUNT);
 627
 628         bool p2p;
 629
 630         struct {
 631                 enum ath10k_bus bus;
 632                 const struct ath10k_hif_ops *ops;
 633         } hif;
 634
 635         struct completion target_suspend;
 636
 637         const struct ath10k_hw_regs *regs;
 638         const struct ath10k_hw_values *hw_values;
 639         struct ath10k_bmi bmi;
 640         struct ath10k_wmi wmi;
 641         struct ath10k_htc htc;
 642         struct ath10k_htt htt;
 643
 644         struct ath10k_hw_params {
 645                 u32 id;
 646                 const char *name;
 647                 u32 patch_load_addr;
 648                 int uart_pin;
 649                 u32 otp_exe_param;
 650
 651                 /* This is true if given HW chip has a quirky Cycle Counter
 652                  * wraparound which resets to 0x7fffffff instead of 0. All
 653                  * other CC related counters (e.g. Rx Clear Count) are divided
 654                  * by 2 so they never wraparound themselves.
 655                  */
 656                 bool has_shifted_cc_wraparound;
 657
 658                 /* Some of chip expects fragment descriptor to be continuous
 659                  * memory for any TX operation. Set continuous_frag_desc flag
 660                  * for the hardware which have such requirement.
 661                  */
 662                 bool continuous_frag_desc;
 663
 664                 u32 channel_counters_freq_hz;
 665
 666                 /* Mgmt tx descriptors threshold for limiting probe response
 667                  * frames.
 668                  */
 669                 u32 max_probe_resp_desc_thres;
 670
 671                 /* The padding bytes's location is different on various chips */
 672                 enum ath10k_hw_4addr_pad hw_4addr_pad;
 673
 674                 struct ath10k_hw_params_fw {
 675                         const char *dir;
 676                         const char *fw;
 677                         const char *otp;
 678                         const char *board;
 679                         size_t board_size;
 680                         size_t board_ext_size;
 681                 } fw;
 682         } hw_params;
 683
 684         const struct firmware *board;
 685         const void *board_data;
 686         size_t board_len;
 687
 688         const struct firmware *otp;
 689         const void *otp_data;
 690         size_t otp_len;
 691
 692         const struct firmware *firmware;
 693         const void *firmware_data;
 694         size_t firmware_len;
 695
 696         const struct firmware *cal_file;
 697
 698         struct {
 699                 const void *firmware_codeswap_data;
 700                 size_t firmware_codeswap_len;
 701                 struct ath10k_swap_code_seg_info *firmware_swap_code_seg_info;
 702         } swap;
 703
 704         struct {
 705                 u32 vendor;
 706                 u32 device;
 707                 u32 subsystem_vendor;
 708                 u32 subsystem_device;
 709
 710                 bool bmi_ids_valid;
 711                 u8 bmi_board_id;
 712                 u8 bmi_chip_id;
 713         } id;
 714
 715         int fw_api;
 716         int bd_api;
 717         enum ath10k_cal_mode cal_mode;
 718
 719         struct {
 720                 struct completion started;
 721                 struct completion completed;
 722                 struct completion on_channel;
 723                 struct delayed_work timeout;
 724                 enum ath10k_scan_state state;
 725                 bool is_roc;
 726                 int vdev_id;
 727                 int roc_freq;
 728                 bool roc_notify;
 729         } scan;
 730
 731         struct {
 732                 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
 733         } mac;
 734
 735         /* should never be NULL; needed for regular htt rx */
 736         struct ieee80211_channel *rx_channel;
 737
 738         /* valid during scan; needed for mgmt rx during scan */
 739         struct ieee80211_channel *scan_channel;
 740
 741         /* current operating channel definition */
 742         struct cfg80211_chan_def chandef;
 743
 744         unsigned long long free_vdev_map;
 745         struct ath10k_vif *monitor_arvif;
 746         bool monitor;
 747         int monitor_vdev_id;
 748         bool monitor_started;
 749         unsigned int filter_flags;
 750         unsigned long dev_flags;
 751         u32 dfs_block_radar_events;
 752
 753         /* protected by conf_mutex */
 754         bool radar_enabled;
 755         int num_started_vdevs;
 756
 757         /* Protected by conf-mutex */
 758         u8 cfg_tx_chainmask;
 759         u8 cfg_rx_chainmask;
 760
 761         struct completion install_key_done;
 762
 763         struct completion vdev_setup_done;
 764
 765         struct workqueue_struct *workqueue;
 766         /* Auxiliary workqueue */
 767         struct workqueue_struct *workqueue_aux;
 768
 769         /* prevents concurrent FW reconfiguration */
 770         struct mutex conf_mutex;
 771
 772         /* protects shared structure data */
 773         spinlock_t data_lock;
 774
 775         struct list_head arvifs;
 776         struct list_head peers;
 777         wait_queue_head_t peer_mapping_wq;
 778
 779         /* protected by conf_mutex */
 780         int num_peers;
 781         int num_stations;
 782
 783         int max_num_peers;
 784         int max_num_stations;
 785         int max_num_vdevs;
 786         int max_num_tdls_vdevs;
 787         int num_active_peers;
 788         int num_tids;
 789
 790         struct work_struct svc_rdy_work;
 791         struct sk_buff *svc_rdy_skb;
 792
 793         struct work_struct offchan_tx_work;
 794         struct sk_buff_head offchan_tx_queue;
 795         struct completion offchan_tx_completed;
 796         struct sk_buff *offchan_tx_skb;
 797
 798         struct work_struct wmi_mgmt_tx_work;
 799         struct sk_buff_head wmi_mgmt_tx_queue;
 800
 801         enum ath10k_state state;
 802
 803         struct work_struct register_work;
 804         struct work_struct restart_work;
 805
 806         /* cycle count is reported twice for each visited channel during scan.
 807          * access protected by data_lock */
 808         u32 survey_last_rx_clear_count;
 809         u32 survey_last_cycle_count;
 810         struct survey_info survey[ATH10K_NUM_CHANS];
 811
 812         /* Channel info events are expected to come in pairs without and with
 813          * COMPLETE flag set respectively for each channel visit during scan.
 814          *
 815          * However there are deviations from this rule. This flag is used to
 816          * avoid reporting garbage data.
 817          */
 818         bool ch_info_can_report_survey;
 819
 820         struct dfs_pattern_detector *dfs_detector;
 821
 822         unsigned long tx_paused; /* see ATH10K_TX_PAUSE_ */
 823
 824 #ifdef CONFIG_ATH10K_DEBUGFS
 825         struct ath10k_debug debug;
 826 #endif
 827
 828         struct {
 829                 /* relay(fs) channel for spectral scan */
 830                 struct rchan *rfs_chan_spec_scan;
 831
 832                 /* spectral_mode and spec_config are protected by conf_mutex */
 833                 enum ath10k_spectral_mode mode;
 834                 struct ath10k_spec_scan config;
 835         } spectral;
 836
 837         struct {
 838                 /* protected by conf_mutex */
 839                 const struct firmware *utf;
 840                 char utf_version[32];
 841                 const void *utf_firmware_data;
 842                 size_t utf_firmware_len;
 843                 DECLARE_BITMAP(orig_fw_features, ATH10K_FW_FEATURE_COUNT);
 844                 enum ath10k_fw_wmi_op_version orig_wmi_op_version;
 845                 enum ath10k_fw_wmi_op_version op_version;
 846                 /* protected by data_lock */
 847                 bool utf_monitor;
 848         } testmode;
 849
 850         struct {
 851                 /* protected by data_lock */
 852                 u32 fw_crash_counter;
 853                 u32 fw_warm_reset_counter;
 854                 u32 fw_cold_reset_counter;
 855         } stats;
 856
 857         struct ath10k_thermal thermal;
 858         struct ath10k_wow wow;
 859
 860         /* must be last */
 861         u8 drv_priv[0] __aligned(sizeof(void *));
 862 };
 863
 864 struct ath10k *ath10k_core_create(size_t priv_size, struct device *dev,
 865                                   enum ath10k_bus bus,
 866                                   enum ath10k_hw_rev hw_rev,
 867                                   const struct ath10k_hif_ops *hif_ops);
 868 void ath10k_core_destroy(struct ath10k *ar);
 869 void ath10k_core_get_fw_features_str(struct ath10k *ar,
 870                                      char *buf,
 871                                      size_t max_len);
 872
 873 int ath10k_core_start(struct ath10k *ar, enum ath10k_firmware_mode mode);
 874 int ath10k_wait_for_suspend(struct ath10k *ar, u32 suspend_opt);
 875 void ath10k_core_stop(struct ath10k *ar);
 876 int ath10k_core_register(struct ath10k *ar, u32 chip_id);
 877 void ath10k_core_unregister(struct ath10k *ar);
 878
 879 #endif /* _CORE_H_ */