drivers/net/wireless/ath/ath10k/htt_tx.c

   1 /*
   2  * Copyright (c) 2005-2011 Atheros Communications Inc.
   3  * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
   4  *
   5  * Permission to use, copy, modify, and/or distribute this software for any
   6  * purpose with or without fee is hereby granted, provided that the above
   7  * copyright notice and this permission notice appear in all copies.
   8  *
   9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16  */
  17
  18 #include <linux/etherdevice.h>
  19 #include "htt.h"
  20 #include "mac.h"
  21 #include "hif.h"
  22 #include "txrx.h"
  23 #include "debug.h"
  24
  25 void __ath10k_htt_tx_dec_pending(struct ath10k_htt *htt, bool limit_mgmt_desc)
  26 {
  27         if (limit_mgmt_desc)
  28                 htt->num_pending_mgmt_tx--;
  29
  30         htt->num_pending_tx--;
  31         if (htt->num_pending_tx == htt->max_num_pending_tx - 1)
  32                 ath10k_mac_tx_unlock(htt->ar, ATH10K_TX_PAUSE_Q_FULL);
  33 }
  34
  35 static void ath10k_htt_tx_dec_pending(struct ath10k_htt *htt,
  36                                       bool limit_mgmt_desc)
  37 {
  38         spin_lock_bh(&htt->tx_lock);
  39         __ath10k_htt_tx_dec_pending(htt, limit_mgmt_desc);
  40         spin_unlock_bh(&htt->tx_lock);
  41 }
  42
  43 static int ath10k_htt_tx_inc_pending(struct ath10k_htt *htt,
  44                                      bool limit_mgmt_desc, bool is_probe_resp)
  45 {
  46         struct ath10k *ar = htt->ar;
  47         int ret = 0;
  48
  49         spin_lock_bh(&htt->tx_lock);
  50
  51         if (htt->num_pending_tx >= htt->max_num_pending_tx) {
  52                 ret = -EBUSY;
  53                 goto exit;
  54         }
  55
  56         if (limit_mgmt_desc) {
  57                 if (is_probe_resp && (htt->num_pending_mgmt_tx >
  58                     ar->hw_params.max_probe_resp_desc_thres)) {
  59                         ret = -EBUSY;
  60                         goto exit;
  61                 }
  62                 htt->num_pending_mgmt_tx++;
  63         }
  64
  65         htt->num_pending_tx++;
  66         if (htt->num_pending_tx == htt->max_num_pending_tx)
  67                 ath10k_mac_tx_lock(htt->ar, ATH10K_TX_PAUSE_Q_FULL);
  68
  69 exit:
  70         spin_unlock_bh(&htt->tx_lock);
  71         return ret;
  72 }
  73
  74 int ath10k_htt_tx_alloc_msdu_id(struct ath10k_htt *htt, struct sk_buff *skb)
  75 {
  76         struct ath10k *ar = htt->ar;
  77         int ret;
  78
  79         lockdep_assert_held(&htt->tx_lock);
  80
  81         ret = idr_alloc(&htt->pending_tx, skb, 0,
  82                         htt->max_num_pending_tx, GFP_ATOMIC);
  83
  84         ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx alloc msdu_id %d\n", ret);
  85
  86         return ret;
  87 }
  88
  89 void ath10k_htt_tx_free_msdu_id(struct ath10k_htt *htt, u16 msdu_id)
  90 {
  91         struct ath10k *ar = htt->ar;
  92
  93         lockdep_assert_held(&htt->tx_lock);
  94
  95         ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx free msdu_id %hu\n", msdu_id);
  96
  97         idr_remove(&htt->pending_tx, msdu_id);
  98 }
  99
 100 int ath10k_htt_tx_alloc(struct ath10k_htt *htt)
 101 {
 102         struct ath10k *ar = htt->ar;
 103         int ret, size;
 104
 105         ath10k_dbg(ar, ATH10K_DBG_BOOT, "htt tx max num pending tx %d\n",
 106                    htt->max_num_pending_tx);
 107
 108         spin_lock_init(&htt->tx_lock);
 109         idr_init(&htt->pending_tx);
 110
 111         htt->tx_pool = dma_pool_create("ath10k htt tx pool", htt->ar->dev,
 112                                        sizeof(struct ath10k_htt_txbuf), 4, 0);
 113         if (!htt->tx_pool) {
 114                 ret = -ENOMEM;
 115                 goto free_idr_pending_tx;
 116         }
 117
 118         if (!ar->hw_params.continuous_frag_desc)
 119                 goto skip_frag_desc_alloc;
 120
 121         size = htt->max_num_pending_tx * sizeof(struct htt_msdu_ext_desc);
 122         htt->frag_desc.vaddr = dma_alloc_coherent(ar->dev, size,
 123                                                   &htt->frag_desc.paddr,
 124                                                   GFP_DMA);
 125         if (!htt->frag_desc.vaddr) {
 126                 ath10k_warn(ar, "failed to alloc fragment desc memory\n");
 127                 ret = -ENOMEM;
 128                 goto free_tx_pool;
 129         }
 130
 131 skip_frag_desc_alloc:
 132         return 0;
 133
 134 free_tx_pool:
 135         dma_pool_destroy(htt->tx_pool);
 136 free_idr_pending_tx:
 137         idr_destroy(&htt->pending_tx);
 138         return ret;
 139 }
 140
 141 static int ath10k_htt_tx_clean_up_pending(int msdu_id, void *skb, void *ctx)
 142 {
 143         struct ath10k *ar = ctx;
 144         struct ath10k_htt *htt = &ar->htt;
 145         struct htt_tx_done tx_done = {0};
 146
 147         ath10k_dbg(ar, ATH10K_DBG_HTT, "force cleanup msdu_id %hu\n", msdu_id);
 148
 149         tx_done.discard = 1;
 150         tx_done.msdu_id = msdu_id;
 151
 152         ath10k_txrx_tx_unref(htt, &tx_done);
 153
 154         return 0;
 155 }
 156
 157 void ath10k_htt_tx_free(struct ath10k_htt *htt)
 158 {
 159         int size;
 160
 161         idr_for_each(&htt->pending_tx, ath10k_htt_tx_clean_up_pending, htt->ar);
 162         idr_destroy(&htt->pending_tx);
 163         dma_pool_destroy(htt->tx_pool);
 164
 165         if (htt->frag_desc.vaddr) {
 166                 size = htt->max_num_pending_tx *
 167                                   sizeof(struct htt_msdu_ext_desc);
 168                 dma_free_coherent(htt->ar->dev, size, htt->frag_desc.vaddr,
 169                                   htt->frag_desc.paddr);
 170         }
 171 }
 172
 173 void ath10k_htt_htc_tx_complete(struct ath10k *ar, struct sk_buff *skb)
 174 {
 175         dev_kfree_skb_any(skb);
 176 }
 177
 178 int ath10k_htt_h2t_ver_req_msg(struct ath10k_htt *htt)
 179 {
 180         struct ath10k *ar = htt->ar;
 181         struct sk_buff *skb;
 182         struct htt_cmd *cmd;
 183         int len = 0;
 184         int ret;
 185
 186         len += sizeof(cmd->hdr);
 187         len += sizeof(cmd->ver_req);
 188
 189         skb = ath10k_htc_alloc_skb(ar, len);
 190         if (!skb)
 191                 return -ENOMEM;
 192
 193         skb_put(skb, len);
 194         cmd = (struct htt_cmd *)skb->data;
 195         cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_VERSION_REQ;
 196
 197         ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);
 198         if (ret) {
 199                 dev_kfree_skb_any(skb);
 200                 return ret;
 201         }
 202
 203         return 0;
 204 }
 205
 206 int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u8 mask, u64 cookie)
 207 {
 208         struct ath10k *ar = htt->ar;
 209         struct htt_stats_req *req;
 210         struct sk_buff *skb;
 211         struct htt_cmd *cmd;
 212         int len = 0, ret;
 213
 214         len += sizeof(cmd->hdr);
 215         len += sizeof(cmd->stats_req);
 216
 217         skb = ath10k_htc_alloc_skb(ar, len);
 218         if (!skb)
 219                 return -ENOMEM;
 220
 221         skb_put(skb, len);
 222         cmd = (struct htt_cmd *)skb->data;
 223         cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_STATS_REQ;
 224
 225         req = &cmd->stats_req;
 226
 227         memset(req, 0, sizeof(*req));
 228
 229         /* currently we support only max 8 bit masks so no need to worry
 230          * about endian support */
 231         req->upload_types[0] = mask;
 232         req->reset_types[0] = mask;
 233         req->stat_type = HTT_STATS_REQ_CFG_STAT_TYPE_INVALID;
 234         req->cookie_lsb = cpu_to_le32(cookie & 0xffffffff);
 235         req->cookie_msb = cpu_to_le32((cookie & 0xffffffff00000000ULL) >> 32);
 236
 237         ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);
 238         if (ret) {
 239                 ath10k_warn(ar, "failed to send htt type stats request: %d",
 240                             ret);
 241                 dev_kfree_skb_any(skb);
 242                 return ret;
 243         }
 244
 245         return 0;
 246 }
 247
 248 int ath10k_htt_send_frag_desc_bank_cfg(struct ath10k_htt *htt)
 249 {
 250         struct ath10k *ar = htt->ar;
 251         struct sk_buff *skb;
 252         struct htt_cmd *cmd;
 253         int ret, size;
 254
 255         if (!ar->hw_params.continuous_frag_desc)
 256                 return 0;
 257
 258         if (!htt->frag_desc.paddr) {
 259                 ath10k_warn(ar, "invalid frag desc memory\n");
 260                 return -EINVAL;
 261         }
 262
 263         size = sizeof(cmd->hdr) + sizeof(cmd->frag_desc_bank_cfg);
 264         skb = ath10k_htc_alloc_skb(ar, size);
 265         if (!skb)
 266                 return -ENOMEM;
 267
 268         skb_put(skb, size);
 269         cmd = (struct htt_cmd *)skb->data;
 270         cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG;
 271         cmd->frag_desc_bank_cfg.info = 0;
 272         cmd->frag_desc_bank_cfg.num_banks = 1;
 273         cmd->frag_desc_bank_cfg.desc_size = sizeof(struct htt_msdu_ext_desc);
 274         cmd->frag_desc_bank_cfg.bank_base_addrs[0] =
 275                                 __cpu_to_le32(htt->frag_desc.paddr);
 276         cmd->frag_desc_bank_cfg.bank_id[0].bank_min_id = 0;
 277         cmd->frag_desc_bank_cfg.bank_id[0].bank_max_id =
 278                                 __cpu_to_le16(htt->max_num_pending_tx - 1);
 279
 280         ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);
 281         if (ret) {
 282                 ath10k_warn(ar, "failed to send frag desc bank cfg request: %d\n",
 283                             ret);
 284                 dev_kfree_skb_any(skb);
 285                 return ret;
 286         }
 287
 288         return 0;
 289 }
 290
 291 int ath10k_htt_send_rx_ring_cfg_ll(struct ath10k_htt *htt)
 292 {
 293         struct ath10k *ar = htt->ar;
 294         struct sk_buff *skb;
 295         struct htt_cmd *cmd;
 296         struct htt_rx_ring_setup_ring *ring;
 297         const int num_rx_ring = 1;
 298         u16 flags;
 299         u32 fw_idx;
 300         int len;
 301         int ret;
 302
 303         /*
 304          * the HW expects the buffer to be an integral number of 4-byte
 305          * "words"
 306          */
 307         BUILD_BUG_ON(!IS_ALIGNED(HTT_RX_BUF_SIZE, 4));
 308         BUILD_BUG_ON((HTT_RX_BUF_SIZE & HTT_MAX_CACHE_LINE_SIZE_MASK) != 0);
 309
 310         len = sizeof(cmd->hdr) + sizeof(cmd->rx_setup.hdr)
 311             + (sizeof(*ring) * num_rx_ring);
 312         skb = ath10k_htc_alloc_skb(ar, len);
 313         if (!skb)
 314                 return -ENOMEM;
 315
 316         skb_put(skb, len);
 317
 318         cmd = (struct htt_cmd *)skb->data;
 319         ring = &cmd->rx_setup.rings[0];
 320
 321         cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_RX_RING_CFG;
 322         cmd->rx_setup.hdr.num_rings = 1;
 323
 324         /* FIXME: do we need all of this? */
 325         flags = 0;
 326         flags |= HTT_RX_RING_FLAGS_MAC80211_HDR;
 327         flags |= HTT_RX_RING_FLAGS_MSDU_PAYLOAD;
 328         flags |= HTT_RX_RING_FLAGS_PPDU_START;
 329         flags |= HTT_RX_RING_FLAGS_PPDU_END;
 330         flags |= HTT_RX_RING_FLAGS_MPDU_START;
 331         flags |= HTT_RX_RING_FLAGS_MPDU_END;
 332         flags |= HTT_RX_RING_FLAGS_MSDU_START;
 333         flags |= HTT_RX_RING_FLAGS_MSDU_END;
 334         flags |= HTT_RX_RING_FLAGS_RX_ATTENTION;
 335         flags |= HTT_RX_RING_FLAGS_FRAG_INFO;
 336         flags |= HTT_RX_RING_FLAGS_UNICAST_RX;
 337         flags |= HTT_RX_RING_FLAGS_MULTICAST_RX;
 338         flags |= HTT_RX_RING_FLAGS_CTRL_RX;
 339         flags |= HTT_RX_RING_FLAGS_MGMT_RX;
 340         flags |= HTT_RX_RING_FLAGS_NULL_RX;
 341         flags |= HTT_RX_RING_FLAGS_PHY_DATA_RX;
 342
 343         fw_idx = __le32_to_cpu(*htt->rx_ring.alloc_idx.vaddr);
 344
 345         ring->fw_idx_shadow_reg_paddr =
 346                 __cpu_to_le32(htt->rx_ring.alloc_idx.paddr);
 347         ring->rx_ring_base_paddr = __cpu_to_le32(htt->rx_ring.base_paddr);
 348         ring->rx_ring_len = __cpu_to_le16(htt->rx_ring.size);
 349         ring->rx_ring_bufsize = __cpu_to_le16(HTT_RX_BUF_SIZE);
 350         ring->flags = __cpu_to_le16(flags);
 351         ring->fw_idx_init_val = __cpu_to_le16(fw_idx);
 352
 353 #define desc_offset(x) (offsetof(struct htt_rx_desc, x) / 4)
 354
 355         ring->mac80211_hdr_offset = __cpu_to_le16(desc_offset(rx_hdr_status));
 356         ring->msdu_payload_offset = __cpu_to_le16(desc_offset(msdu_payload));
 357         ring->ppdu_start_offset = __cpu_to_le16(desc_offset(ppdu_start));
 358         ring->ppdu_end_offset = __cpu_to_le16(desc_offset(ppdu_end));
 359         ring->mpdu_start_offset = __cpu_to_le16(desc_offset(mpdu_start));
 360         ring->mpdu_end_offset = __cpu_to_le16(desc_offset(mpdu_end));
 361         ring->msdu_start_offset = __cpu_to_le16(desc_offset(msdu_start));
 362         ring->msdu_end_offset = __cpu_to_le16(desc_offset(msdu_end));
 363         ring->rx_attention_offset = __cpu_to_le16(desc_offset(attention));
 364         ring->frag_info_offset = __cpu_to_le16(desc_offset(frag_info));
 365
 366 #undef desc_offset
 367
 368         ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);
 369         if (ret) {
 370                 dev_kfree_skb_any(skb);
 371                 return ret;
 372         }
 373
 374         return 0;
 375 }
 376
 377 int ath10k_htt_h2t_aggr_cfg_msg(struct ath10k_htt *htt,
 378                                 u8 max_subfrms_ampdu,
 379                                 u8 max_subfrms_amsdu)
 380 {
 381         struct ath10k *ar = htt->ar;
 382         struct htt_aggr_conf *aggr_conf;
 383         struct sk_buff *skb;
 384         struct htt_cmd *cmd;
 385         int len;
 386         int ret;
 387
 388         /* Firmware defaults are: amsdu = 3 and ampdu = 64 */
 389
 390         if (max_subfrms_ampdu == 0 || max_subfrms_ampdu > 64)
 391                 return -EINVAL;
 392
 393         if (max_subfrms_amsdu == 0 || max_subfrms_amsdu > 31)
 394                 return -EINVAL;
 395
 396         len = sizeof(cmd->hdr);
 397         len += sizeof(cmd->aggr_conf);
 398
 399         skb = ath10k_htc_alloc_skb(ar, len);
 400         if (!skb)
 401                 return -ENOMEM;
 402
 403         skb_put(skb, len);
 404         cmd = (struct htt_cmd *)skb->data;
 405         cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_AGGR_CFG;
 406
 407         aggr_conf = &cmd->aggr_conf;
 408         aggr_conf->max_num_ampdu_subframes = max_subfrms_ampdu;
 409         aggr_conf->max_num_amsdu_subframes = max_subfrms_amsdu;
 410
 411         ath10k_dbg(ar, ATH10K_DBG_HTT, "htt h2t aggr cfg msg amsdu %d ampdu %d",
 412                    aggr_conf->max_num_amsdu_subframes,
 413                    aggr_conf->max_num_ampdu_subframes);
 414
 415         ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);
 416         if (ret) {
 417                 dev_kfree_skb_any(skb);
 418                 return ret;
 419         }
 420
 421         return 0;
 422 }
 423
 424 int ath10k_htt_mgmt_tx(struct ath10k_htt *htt, struct sk_buff *msdu)
 425 {
 426         struct ath10k *ar = htt->ar;
 427         struct device *dev = ar->dev;
 428         struct sk_buff *txdesc = NULL;
 429         struct htt_cmd *cmd;
 430         struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu);
 431         u8 vdev_id = skb_cb->vdev_id;
 432         int len = 0;
 433         int msdu_id = -1;
 434         int res;
 435         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data;
 436         bool limit_mgmt_desc = false;
 437         bool is_probe_resp = false;
 438
 439         if (ar->hw_params.max_probe_resp_desc_thres) {
 440                 limit_mgmt_desc = true;
 441
 442                 if (ieee80211_is_probe_resp(hdr->frame_control))
 443                         is_probe_resp = true;
 444         }
 445
 446         res = ath10k_htt_tx_inc_pending(htt, limit_mgmt_desc, is_probe_resp);
 447
 448         if (res)
 449                 goto err;
 450
 451         len += sizeof(cmd->hdr);
 452         len += sizeof(cmd->mgmt_tx);
 453
 454         spin_lock_bh(&htt->tx_lock);
 455         res = ath10k_htt_tx_alloc_msdu_id(htt, msdu);
 456         spin_unlock_bh(&htt->tx_lock);
 457         if (res < 0)
 458                 goto err_tx_dec;
 459
 460         msdu_id = res;
 461
 462         txdesc = ath10k_htc_alloc_skb(ar, len);
 463         if (!txdesc) {
 464                 res = -ENOMEM;
 465                 goto err_free_msdu_id;
 466         }
 467
 468         skb_cb->paddr = dma_map_single(dev, msdu->data, msdu->len,
 469                                        DMA_TO_DEVICE);
 470         res = dma_mapping_error(dev, skb_cb->paddr);
 471         if (res) {
 472                 res = -EIO;
 473                 goto err_free_txdesc;
 474         }
 475
 476         skb_put(txdesc, len);
 477         cmd = (struct htt_cmd *)txdesc->data;
 478         memset(cmd, 0, len);
 479
 480         cmd->hdr.msg_type         = HTT_H2T_MSG_TYPE_MGMT_TX;
 481         cmd->mgmt_tx.msdu_paddr = __cpu_to_le32(ATH10K_SKB_CB(msdu)->paddr);
 482         cmd->mgmt_tx.len        = __cpu_to_le32(msdu->len);
 483         cmd->mgmt_tx.desc_id    = __cpu_to_le32(msdu_id);
 484         cmd->mgmt_tx.vdev_id    = __cpu_to_le32(vdev_id);
 485         memcpy(cmd->mgmt_tx.hdr, msdu->data,
 486                min_t(int, msdu->len, HTT_MGMT_FRM_HDR_DOWNLOAD_LEN));
 487
 488         skb_cb->htt.txbuf = NULL;
 489
 490         res = ath10k_htc_send(&htt->ar->htc, htt->eid, txdesc);
 491         if (res)
 492                 goto err_unmap_msdu;
 493
 494         return 0;
 495
 496 err_unmap_msdu:
 497         dma_unmap_single(dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
 498 err_free_txdesc:
 499         dev_kfree_skb_any(txdesc);
 500 err_free_msdu_id:
 501         spin_lock_bh(&htt->tx_lock);
 502         ath10k_htt_tx_free_msdu_id(htt, msdu_id);
 503         spin_unlock_bh(&htt->tx_lock);
 504 err_tx_dec:
 505         ath10k_htt_tx_dec_pending(htt, limit_mgmt_desc);
 506 err:
 507         return res;
 508 }
 509
 510 int ath10k_htt_tx(struct ath10k_htt *htt, struct sk_buff *msdu)
 511 {
 512         struct ath10k *ar = htt->ar;
 513         struct device *dev = ar->dev;
 514         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data;
 515         struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu);
 516         struct ath10k_hif_sg_item sg_items[2];
 517         struct htt_data_tx_desc_frag *frags;
 518         u8 vdev_id = skb_cb->vdev_id;
 519         u8 tid = skb_cb->htt.tid;
 520         int prefetch_len;
 521         int res;
 522         u8 flags0 = 0;
 523         u16 msdu_id, flags1 = 0;
 524         dma_addr_t paddr = 0;
 525         u32 frags_paddr = 0;
 526         struct htt_msdu_ext_desc *ext_desc = NULL;
 527         bool limit_mgmt_desc = false;
 528         bool is_probe_resp = false;
 529
 530         if (unlikely(ieee80211_is_mgmt(hdr->frame_control)) &&
 531             ar->hw_params.max_probe_resp_desc_thres) {
 532                 limit_mgmt_desc = true;
 533
 534                 if (ieee80211_is_probe_resp(hdr->frame_control))
 535                         is_probe_resp = true;
 536         }
 537
 538         res = ath10k_htt_tx_inc_pending(htt, limit_mgmt_desc, is_probe_resp);
 539         if (res)
 540                 goto err;
 541
 542         spin_lock_bh(&htt->tx_lock);
 543         res = ath10k_htt_tx_alloc_msdu_id(htt, msdu);
 544         spin_unlock_bh(&htt->tx_lock);
 545         if (res < 0)
 546                 goto err_tx_dec;
 547
 548         msdu_id = res;
 549
 550         prefetch_len = min(htt->prefetch_len, msdu->len);
 551         prefetch_len = roundup(prefetch_len, 4);
 552
 553         skb_cb->htt.txbuf = dma_pool_alloc(htt->tx_pool, GFP_ATOMIC,
 554                                            &paddr);
 555         if (!skb_cb->htt.txbuf) {
 556                 res = -ENOMEM;
 557                 goto err_free_msdu_id;
 558         }
 559         skb_cb->htt.txbuf_paddr = paddr;
 560
 561         if ((ieee80211_is_action(hdr->frame_control) ||
 562              ieee80211_is_deauth(hdr->frame_control) ||
 563              ieee80211_is_disassoc(hdr->frame_control)) &&
 564              ieee80211_has_protected(hdr->frame_control)) {
 565                 skb_put(msdu, IEEE80211_CCMP_MIC_LEN);
 566         } else if (!skb_cb->htt.nohwcrypt &&
 567                    skb_cb->txmode == ATH10K_HW_TXRX_RAW &&
 568                    ieee80211_has_protected(hdr->frame_control)) {
 569                 skb_put(msdu, IEEE80211_CCMP_MIC_LEN);
 570         }
 571
 572         skb_cb->paddr = dma_map_single(dev, msdu->data, msdu->len,
 573                                        DMA_TO_DEVICE);
 574         res = dma_mapping_error(dev, skb_cb->paddr);
 575         if (res) {
 576                 res = -EIO;
 577                 goto err_free_txbuf;
 578         }
 579
 580         switch (skb_cb->txmode) {
 581         case ATH10K_HW_TXRX_RAW:
 582         case ATH10K_HW_TXRX_NATIVE_WIFI:
 583                 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT;
 584                 /* pass through */
 585         case ATH10K_HW_TXRX_ETHERNET:
 586                 if (ar->hw_params.continuous_frag_desc) {
 587                         memset(&htt->frag_desc.vaddr[msdu_id], 0,
 588                                sizeof(struct htt_msdu_ext_desc));
 589                         frags = (struct htt_data_tx_desc_frag *)
 590                                 &htt->frag_desc.vaddr[msdu_id].frags;
 591                         ext_desc = &htt->frag_desc.vaddr[msdu_id];
 592                         frags[0].tword_addr.paddr_lo =
 593                                 __cpu_to_le32(skb_cb->paddr);
 594                         frags[0].tword_addr.paddr_hi = 0;
 595                         frags[0].tword_addr.len_16 = __cpu_to_le16(msdu->len);
 596
 597                         frags_paddr =  htt->frag_desc.paddr +
 598                                 (sizeof(struct htt_msdu_ext_desc) * msdu_id);
 599                 } else {
 600                         frags = skb_cb->htt.txbuf->frags;
 601                         frags[0].dword_addr.paddr =
 602                                 __cpu_to_le32(skb_cb->paddr);
 603                         frags[0].dword_addr.len = __cpu_to_le32(msdu->len);
 604                         frags[1].dword_addr.paddr = 0;
 605                         frags[1].dword_addr.len = 0;
 606
 607                         frags_paddr = skb_cb->htt.txbuf_paddr;
 608                 }
 609                 flags0 |= SM(skb_cb->txmode, HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE);
 610                 break;
 611         case ATH10K_HW_TXRX_MGMT:
 612                 flags0 |= SM(ATH10K_HW_TXRX_MGMT,
 613                              HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE);
 614                 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT;
 615
 616                 frags_paddr = skb_cb->paddr;
 617                 break;
 618         }
 619
 620         /* Normally all commands go through HTC which manages tx credits for
 621          * each endpoint and notifies when tx is completed.
 622          *
 623          * HTT endpoint is creditless so there's no need to care about HTC
 624          * flags. In that case it is trivial to fill the HTC header here.
 625          *
 626          * MSDU transmission is considered completed upon HTT event. This
 627          * implies no relevant resources can be freed until after the event is
 628          * received. That's why HTC tx completion handler itself is ignored by
 629          * setting NULL to transfer_context for all sg items.
 630          *
 631          * There is simply no point in pushing HTT TX_FRM through HTC tx path
 632          * as it's a waste of resources. By bypassing HTC it is possible to
 633          * avoid extra memory allocations, compress data structures and thus
 634          * improve performance. */
 635
 636         skb_cb->htt.txbuf->htc_hdr.eid = htt->eid;
 637         skb_cb->htt.txbuf->htc_hdr.len = __cpu_to_le16(
 638                         sizeof(skb_cb->htt.txbuf->cmd_hdr) +
 639                         sizeof(skb_cb->htt.txbuf->cmd_tx) +
 640                         prefetch_len);
 641         skb_cb->htt.txbuf->htc_hdr.flags = 0;
 642
 643         if (skb_cb->htt.nohwcrypt)
 644                 flags0 |= HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT;
 645
 646         if (!skb_cb->is_protected)
 647                 flags0 |= HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT;
 648
 649         flags1 |= SM((u16)vdev_id, HTT_DATA_TX_DESC_FLAGS1_VDEV_ID);
 650         flags1 |= SM((u16)tid, HTT_DATA_TX_DESC_FLAGS1_EXT_TID);
 651         if (msdu->ip_summed == CHECKSUM_PARTIAL &&
 652             !test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) {
 653                 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD;
 654                 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD;
 655                 if (ar->hw_params.continuous_frag_desc)
 656                         ext_desc->flags |= HTT_MSDU_CHECKSUM_ENABLE;
 657         }
 658
 659         /* Prevent firmware from sending up tx inspection requests. There's
 660          * nothing ath10k can do with frames requested for inspection so force
 661          * it to simply rely a regular tx completion with discard status.
 662          */
 663         flags1 |= HTT_DATA_TX_DESC_FLAGS1_POSTPONED;
 664
 665         skb_cb->htt.txbuf->cmd_hdr.msg_type = HTT_H2T_MSG_TYPE_TX_FRM;
 666         skb_cb->htt.txbuf->cmd_tx.flags0 = flags0;
 667         skb_cb->htt.txbuf->cmd_tx.flags1 = __cpu_to_le16(flags1);
 668         skb_cb->htt.txbuf->cmd_tx.len = __cpu_to_le16(msdu->len);
 669         skb_cb->htt.txbuf->cmd_tx.id = __cpu_to_le16(msdu_id);
 670         skb_cb->htt.txbuf->cmd_tx.frags_paddr = __cpu_to_le32(frags_paddr);
 671         skb_cb->htt.txbuf->cmd_tx.peerid = __cpu_to_le16(HTT_INVALID_PEERID);
 672         skb_cb->htt.txbuf->cmd_tx.freq = __cpu_to_le16(skb_cb->htt.freq);
 673
 674         trace_ath10k_htt_tx(ar, msdu_id, msdu->len, vdev_id, tid);
 675         ath10k_dbg(ar, ATH10K_DBG_HTT,
 676                    "htt tx flags0 %hhu flags1 %hu len %d id %hu frags_paddr %08x, msdu_paddr %08x vdev %hhu tid %hhu freq %hu\n",
 677                    flags0, flags1, msdu->len, msdu_id, frags_paddr,
 678                    (u32)skb_cb->paddr, vdev_id, tid, skb_cb->htt.freq);
 679         ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt tx msdu: ",
 680                         msdu->data, msdu->len);
 681         trace_ath10k_tx_hdr(ar, msdu->data, msdu->len);
 682         trace_ath10k_tx_payload(ar, msdu->data, msdu->len);
 683
 684         sg_items[0].transfer_id = 0;
 685         sg_items[0].transfer_context = NULL;
 686         sg_items[0].vaddr = &skb_cb->htt.txbuf->htc_hdr;
 687         sg_items[0].paddr = skb_cb->htt.txbuf_paddr +
 688                             sizeof(skb_cb->htt.txbuf->frags);
 689         sg_items[0].len = sizeof(skb_cb->htt.txbuf->htc_hdr) +
 690                           sizeof(skb_cb->htt.txbuf->cmd_hdr) +
 691                           sizeof(skb_cb->htt.txbuf->cmd_tx);
 692
 693         sg_items[1].transfer_id = 0;
 694         sg_items[1].transfer_context = NULL;
 695         sg_items[1].vaddr = msdu->data;
 696         sg_items[1].paddr = skb_cb->paddr;
 697         sg_items[1].len = prefetch_len;
 698
 699         res = ath10k_hif_tx_sg(htt->ar,
 700                                htt->ar->htc.endpoint[htt->eid].ul_pipe_id,
 701                                sg_items, ARRAY_SIZE(sg_items));
 702         if (res)
 703                 goto err_unmap_msdu;
 704
 705         return 0;
 706
 707 err_unmap_msdu:
 708         dma_unmap_single(dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
 709 err_free_txbuf:
 710         dma_pool_free(htt->tx_pool,
 711                       skb_cb->htt.txbuf,
 712                       skb_cb->htt.txbuf_paddr);
 713 err_free_msdu_id:
 714         spin_lock_bh(&htt->tx_lock);
 715         ath10k_htt_tx_free_msdu_id(htt, msdu_id);
 716         spin_unlock_bh(&htt->tx_lock);
 717 err_tx_dec:
 718         ath10k_htt_tx_dec_pending(htt, limit_mgmt_desc);
 719 err:
 720         return res;
 721 }