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02dc4083882d1e5ea7c0c5b1fdaa720140e91a66
[deliverable/linux.git] / drivers / net / wireless / ath / ath10k / pci.c
1 /*
2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18 #include <linux/pci.h>
19 #include <linux/module.h>
20 #include <linux/interrupt.h>
21 #include <linux/spinlock.h>
22 #include <linux/bitops.h>
23
24 #include "core.h"
25 #include "debug.h"
26
27 #include "targaddrs.h"
28 #include "bmi.h"
29
30 #include "hif.h"
31 #include "htc.h"
32
33 #include "ce.h"
34 #include "pci.h"
35
36 enum ath10k_pci_irq_mode {
37 ATH10K_PCI_IRQ_AUTO = 0,
38 ATH10K_PCI_IRQ_LEGACY = 1,
39 ATH10K_PCI_IRQ_MSI = 2,
40 };
41
42 enum ath10k_pci_reset_mode {
43 ATH10K_PCI_RESET_AUTO = 0,
44 ATH10K_PCI_RESET_WARM_ONLY = 1,
45 };
46
47 static unsigned int ath10k_pci_target_ps;
48 static unsigned int ath10k_pci_irq_mode = ATH10K_PCI_IRQ_AUTO;
49 static unsigned int ath10k_pci_reset_mode = ATH10K_PCI_RESET_AUTO;
50
51 module_param_named(target_ps, ath10k_pci_target_ps, uint, 0644);
52 MODULE_PARM_DESC(target_ps, "Enable ath10k Target (SoC) PS option");
53
54 module_param_named(irq_mode, ath10k_pci_irq_mode, uint, 0644);
55 MODULE_PARM_DESC(irq_mode, "0: auto, 1: legacy, 2: msi (default: 0)");
56
57 module_param_named(reset_mode, ath10k_pci_reset_mode, uint, 0644);
58 MODULE_PARM_DESC(reset_mode, "0: auto, 1: warm only (default: 0)");
59
60 /* how long wait to wait for target to initialise, in ms */
61 #define ATH10K_PCI_TARGET_WAIT 3000
62
63 #define QCA988X_2_0_DEVICE_ID (0x003c)
64
65 static DEFINE_PCI_DEVICE_TABLE(ath10k_pci_id_table) = {
66 { PCI_VDEVICE(ATHEROS, QCA988X_2_0_DEVICE_ID) }, /* PCI-E QCA988X V2 */
67 {0}
68 };
69
70 static int ath10k_pci_diag_read_access(struct ath10k *ar, u32 address,
71 u32 *data);
72
73 static int ath10k_pci_post_rx(struct ath10k *ar);
74 static int ath10k_pci_post_rx_pipe(struct ath10k_pci_pipe *pipe_info,
75 int num);
76 static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe *pipe_info);
77 static int ath10k_pci_cold_reset(struct ath10k *ar);
78 static int ath10k_pci_warm_reset(struct ath10k *ar);
79 static int ath10k_pci_wait_for_target_init(struct ath10k *ar);
80 static int ath10k_pci_init_irq(struct ath10k *ar);
81 static int ath10k_pci_deinit_irq(struct ath10k *ar);
82 static int ath10k_pci_request_irq(struct ath10k *ar);
83 static void ath10k_pci_free_irq(struct ath10k *ar);
84 static int ath10k_pci_bmi_wait(struct ath10k_ce_pipe *tx_pipe,
85 struct ath10k_ce_pipe *rx_pipe,
86 struct bmi_xfer *xfer);
87
88 static const struct ce_attr host_ce_config_wlan[] = {
89 /* CE0: host->target HTC control and raw streams */
90 {
91 .flags = CE_ATTR_FLAGS,
92 .src_nentries = 16,
93 .src_sz_max = 256,
94 .dest_nentries = 0,
95 },
96
97 /* CE1: target->host HTT + HTC control */
98 {
99 .flags = CE_ATTR_FLAGS,
100 .src_nentries = 0,
101 .src_sz_max = 512,
102 .dest_nentries = 512,
103 },
104
105 /* CE2: target->host WMI */
106 {
107 .flags = CE_ATTR_FLAGS,
108 .src_nentries = 0,
109 .src_sz_max = 2048,
110 .dest_nentries = 32,
111 },
112
113 /* CE3: host->target WMI */
114 {
115 .flags = CE_ATTR_FLAGS,
116 .src_nentries = 32,
117 .src_sz_max = 2048,
118 .dest_nentries = 0,
119 },
120
121 /* CE4: host->target HTT */
122 {
123 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
124 .src_nentries = CE_HTT_H2T_MSG_SRC_NENTRIES,
125 .src_sz_max = 256,
126 .dest_nentries = 0,
127 },
128
129 /* CE5: unused */
130 {
131 .flags = CE_ATTR_FLAGS,
132 .src_nentries = 0,
133 .src_sz_max = 0,
134 .dest_nentries = 0,
135 },
136
137 /* CE6: target autonomous hif_memcpy */
138 {
139 .flags = CE_ATTR_FLAGS,
140 .src_nentries = 0,
141 .src_sz_max = 0,
142 .dest_nentries = 0,
143 },
144
145 /* CE7: ce_diag, the Diagnostic Window */
146 {
147 .flags = CE_ATTR_FLAGS,
148 .src_nentries = 2,
149 .src_sz_max = DIAG_TRANSFER_LIMIT,
150 .dest_nentries = 2,
151 },
152 };
153
154 /* Target firmware's Copy Engine configuration. */
155 static const struct ce_pipe_config target_ce_config_wlan[] = {
156 /* CE0: host->target HTC control and raw streams */
157 {
158 .pipenum = 0,
159 .pipedir = PIPEDIR_OUT,
160 .nentries = 32,
161 .nbytes_max = 256,
162 .flags = CE_ATTR_FLAGS,
163 .reserved = 0,
164 },
165
166 /* CE1: target->host HTT + HTC control */
167 {
168 .pipenum = 1,
169 .pipedir = PIPEDIR_IN,
170 .nentries = 32,
171 .nbytes_max = 512,
172 .flags = CE_ATTR_FLAGS,
173 .reserved = 0,
174 },
175
176 /* CE2: target->host WMI */
177 {
178 .pipenum = 2,
179 .pipedir = PIPEDIR_IN,
180 .nentries = 32,
181 .nbytes_max = 2048,
182 .flags = CE_ATTR_FLAGS,
183 .reserved = 0,
184 },
185
186 /* CE3: host->target WMI */
187 {
188 .pipenum = 3,
189 .pipedir = PIPEDIR_OUT,
190 .nentries = 32,
191 .nbytes_max = 2048,
192 .flags = CE_ATTR_FLAGS,
193 .reserved = 0,
194 },
195
196 /* CE4: host->target HTT */
197 {
198 .pipenum = 4,
199 .pipedir = PIPEDIR_OUT,
200 .nentries = 256,
201 .nbytes_max = 256,
202 .flags = CE_ATTR_FLAGS,
203 .reserved = 0,
204 },
205
206 /* NB: 50% of src nentries, since tx has 2 frags */
207
208 /* CE5: unused */
209 {
210 .pipenum = 5,
211 .pipedir = PIPEDIR_OUT,
212 .nentries = 32,
213 .nbytes_max = 2048,
214 .flags = CE_ATTR_FLAGS,
215 .reserved = 0,
216 },
217
218 /* CE6: Reserved for target autonomous hif_memcpy */
219 {
220 .pipenum = 6,
221 .pipedir = PIPEDIR_INOUT,
222 .nentries = 32,
223 .nbytes_max = 4096,
224 .flags = CE_ATTR_FLAGS,
225 .reserved = 0,
226 },
227
228 /* CE7 used only by Host */
229 };
230
231 static bool ath10k_pci_irq_pending(struct ath10k *ar)
232 {
233 u32 cause;
234
235 /* Check if the shared legacy irq is for us */
236 cause = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
237 PCIE_INTR_CAUSE_ADDRESS);
238 if (cause & (PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL))
239 return true;
240
241 return false;
242 }
243
244 static void ath10k_pci_disable_and_clear_legacy_irq(struct ath10k *ar)
245 {
246 /* IMPORTANT: INTR_CLR register has to be set after
247 * INTR_ENABLE is set to 0, otherwise interrupt can not be
248 * really cleared. */
249 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
250 0);
251 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_CLR_ADDRESS,
252 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
253
254 /* IMPORTANT: this extra read transaction is required to
255 * flush the posted write buffer. */
256 (void) ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
257 PCIE_INTR_ENABLE_ADDRESS);
258 }
259
260 static void ath10k_pci_enable_legacy_irq(struct ath10k *ar)
261 {
262 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
263 PCIE_INTR_ENABLE_ADDRESS,
264 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
265
266 /* IMPORTANT: this extra read transaction is required to
267 * flush the posted write buffer. */
268 (void) ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
269 PCIE_INTR_ENABLE_ADDRESS);
270 }
271
272 static irqreturn_t ath10k_pci_early_irq_handler(int irq, void *arg)
273 {
274 struct ath10k *ar = arg;
275 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
276
277 if (ar_pci->num_msi_intrs == 0) {
278 if (!ath10k_pci_irq_pending(ar))
279 return IRQ_NONE;
280
281 ath10k_pci_disable_and_clear_legacy_irq(ar);
282 }
283
284 tasklet_schedule(&ar_pci->early_irq_tasklet);
285
286 return IRQ_HANDLED;
287 }
288
289 static int ath10k_pci_request_early_irq(struct ath10k *ar)
290 {
291 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
292 int ret;
293
294 /* Regardless whether MSI-X/MSI/legacy irqs have been set up the first
295 * interrupt from irq vector is triggered in all cases for FW
296 * indication/errors */
297 ret = request_irq(ar_pci->pdev->irq, ath10k_pci_early_irq_handler,
298 IRQF_SHARED, "ath10k_pci (early)", ar);
299 if (ret) {
300 ath10k_warn("failed to request early irq: %d\n", ret);
301 return ret;
302 }
303
304 return 0;
305 }
306
307 static void ath10k_pci_free_early_irq(struct ath10k *ar)
308 {
309 free_irq(ath10k_pci_priv(ar)->pdev->irq, ar);
310 }
311
312 /*
313 * Diagnostic read/write access is provided for startup/config/debug usage.
314 * Caller must guarantee proper alignment, when applicable, and single user
315 * at any moment.
316 */
317 static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, void *data,
318 int nbytes)
319 {
320 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
321 int ret = 0;
322 u32 buf;
323 unsigned int completed_nbytes, orig_nbytes, remaining_bytes;
324 unsigned int id;
325 unsigned int flags;
326 struct ath10k_ce_pipe *ce_diag;
327 /* Host buffer address in CE space */
328 u32 ce_data;
329 dma_addr_t ce_data_base = 0;
330 void *data_buf = NULL;
331 int i;
332
333 /*
334 * This code cannot handle reads to non-memory space. Redirect to the
335 * register read fn but preserve the multi word read capability of
336 * this fn
337 */
338 if (address < DRAM_BASE_ADDRESS) {
339 if (!IS_ALIGNED(address, 4) ||
340 !IS_ALIGNED((unsigned long)data, 4))
341 return -EIO;
342
343 while ((nbytes >= 4) && ((ret = ath10k_pci_diag_read_access(
344 ar, address, (u32 *)data)) == 0)) {
345 nbytes -= sizeof(u32);
346 address += sizeof(u32);
347 data += sizeof(u32);
348 }
349 return ret;
350 }
351
352 ce_diag = ar_pci->ce_diag;
353
354 /*
355 * Allocate a temporary bounce buffer to hold caller's data
356 * to be DMA'ed from Target. This guarantees
357 * 1) 4-byte alignment
358 * 2) Buffer in DMA-able space
359 */
360 orig_nbytes = nbytes;
361 data_buf = (unsigned char *)dma_alloc_coherent(ar->dev,
362 orig_nbytes,
363 &ce_data_base,
364 GFP_ATOMIC);
365
366 if (!data_buf) {
367 ret = -ENOMEM;
368 goto done;
369 }
370 memset(data_buf, 0, orig_nbytes);
371
372 remaining_bytes = orig_nbytes;
373 ce_data = ce_data_base;
374 while (remaining_bytes) {
375 nbytes = min_t(unsigned int, remaining_bytes,
376 DIAG_TRANSFER_LIMIT);
377
378 ret = ath10k_ce_recv_buf_enqueue(ce_diag, NULL, ce_data);
379 if (ret != 0)
380 goto done;
381
382 /* Request CE to send from Target(!) address to Host buffer */
383 /*
384 * The address supplied by the caller is in the
385 * Target CPU virtual address space.
386 *
387 * In order to use this address with the diagnostic CE,
388 * convert it from Target CPU virtual address space
389 * to CE address space
390 */
391 ath10k_pci_wake(ar);
392 address = TARG_CPU_SPACE_TO_CE_SPACE(ar, ar_pci->mem,
393 address);
394 ath10k_pci_sleep(ar);
395
396 ret = ath10k_ce_send(ce_diag, NULL, (u32)address, nbytes, 0,
397 0);
398 if (ret)
399 goto done;
400
401 i = 0;
402 while (ath10k_ce_completed_send_next(ce_diag, NULL, &buf,
403 &completed_nbytes,
404 &id) != 0) {
405 mdelay(1);
406 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
407 ret = -EBUSY;
408 goto done;
409 }
410 }
411
412 if (nbytes != completed_nbytes) {
413 ret = -EIO;
414 goto done;
415 }
416
417 if (buf != (u32) address) {
418 ret = -EIO;
419 goto done;
420 }
421
422 i = 0;
423 while (ath10k_ce_completed_recv_next(ce_diag, NULL, &buf,
424 &completed_nbytes,
425 &id, &flags) != 0) {
426 mdelay(1);
427
428 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
429 ret = -EBUSY;
430 goto done;
431 }
432 }
433
434 if (nbytes != completed_nbytes) {
435 ret = -EIO;
436 goto done;
437 }
438
439 if (buf != ce_data) {
440 ret = -EIO;
441 goto done;
442 }
443
444 remaining_bytes -= nbytes;
445 address += nbytes;
446 ce_data += nbytes;
447 }
448
449 done:
450 if (ret == 0) {
451 /* Copy data from allocated DMA buf to caller's buf */
452 WARN_ON_ONCE(orig_nbytes & 3);
453 for (i = 0; i < orig_nbytes / sizeof(__le32); i++) {
454 ((u32 *)data)[i] =
455 __le32_to_cpu(((__le32 *)data_buf)[i]);
456 }
457 } else
458 ath10k_warn("failed to read diag value at 0x%x: %d\n",
459 address, ret);
460
461 if (data_buf)
462 dma_free_coherent(ar->dev, orig_nbytes, data_buf,
463 ce_data_base);
464
465 return ret;
466 }
467
468 /* Read 4-byte aligned data from Target memory or register */
469 static int ath10k_pci_diag_read_access(struct ath10k *ar, u32 address,
470 u32 *data)
471 {
472 /* Assume range doesn't cross this boundary */
473 if (address >= DRAM_BASE_ADDRESS)
474 return ath10k_pci_diag_read_mem(ar, address, data, sizeof(u32));
475
476 ath10k_pci_wake(ar);
477 *data = ath10k_pci_read32(ar, address);
478 ath10k_pci_sleep(ar);
479 return 0;
480 }
481
482 static int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address,
483 const void *data, int nbytes)
484 {
485 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
486 int ret = 0;
487 u32 buf;
488 unsigned int completed_nbytes, orig_nbytes, remaining_bytes;
489 unsigned int id;
490 unsigned int flags;
491 struct ath10k_ce_pipe *ce_diag;
492 void *data_buf = NULL;
493 u32 ce_data; /* Host buffer address in CE space */
494 dma_addr_t ce_data_base = 0;
495 int i;
496
497 ce_diag = ar_pci->ce_diag;
498
499 /*
500 * Allocate a temporary bounce buffer to hold caller's data
501 * to be DMA'ed to Target. This guarantees
502 * 1) 4-byte alignment
503 * 2) Buffer in DMA-able space
504 */
505 orig_nbytes = nbytes;
506 data_buf = (unsigned char *)dma_alloc_coherent(ar->dev,
507 orig_nbytes,
508 &ce_data_base,
509 GFP_ATOMIC);
510 if (!data_buf) {
511 ret = -ENOMEM;
512 goto done;
513 }
514
515 /* Copy caller's data to allocated DMA buf */
516 WARN_ON_ONCE(orig_nbytes & 3);
517 for (i = 0; i < orig_nbytes / sizeof(__le32); i++)
518 ((__le32 *)data_buf)[i] = __cpu_to_le32(((u32 *)data)[i]);
519
520 /*
521 * The address supplied by the caller is in the
522 * Target CPU virtual address space.
523 *
524 * In order to use this address with the diagnostic CE,
525 * convert it from
526 * Target CPU virtual address space
527 * to
528 * CE address space
529 */
530 ath10k_pci_wake(ar);
531 address = TARG_CPU_SPACE_TO_CE_SPACE(ar, ar_pci->mem, address);
532 ath10k_pci_sleep(ar);
533
534 remaining_bytes = orig_nbytes;
535 ce_data = ce_data_base;
536 while (remaining_bytes) {
537 /* FIXME: check cast */
538 nbytes = min_t(int, remaining_bytes, DIAG_TRANSFER_LIMIT);
539
540 /* Set up to receive directly into Target(!) address */
541 ret = ath10k_ce_recv_buf_enqueue(ce_diag, NULL, address);
542 if (ret != 0)
543 goto done;
544
545 /*
546 * Request CE to send caller-supplied data that
547 * was copied to bounce buffer to Target(!) address.
548 */
549 ret = ath10k_ce_send(ce_diag, NULL, (u32) ce_data,
550 nbytes, 0, 0);
551 if (ret != 0)
552 goto done;
553
554 i = 0;
555 while (ath10k_ce_completed_send_next(ce_diag, NULL, &buf,
556 &completed_nbytes,
557 &id) != 0) {
558 mdelay(1);
559
560 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
561 ret = -EBUSY;
562 goto done;
563 }
564 }
565
566 if (nbytes != completed_nbytes) {
567 ret = -EIO;
568 goto done;
569 }
570
571 if (buf != ce_data) {
572 ret = -EIO;
573 goto done;
574 }
575
576 i = 0;
577 while (ath10k_ce_completed_recv_next(ce_diag, NULL, &buf,
578 &completed_nbytes,
579 &id, &flags) != 0) {
580 mdelay(1);
581
582 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
583 ret = -EBUSY;
584 goto done;
585 }
586 }
587
588 if (nbytes != completed_nbytes) {
589 ret = -EIO;
590 goto done;
591 }
592
593 if (buf != address) {
594 ret = -EIO;
595 goto done;
596 }
597
598 remaining_bytes -= nbytes;
599 address += nbytes;
600 ce_data += nbytes;
601 }
602
603 done:
604 if (data_buf) {
605 dma_free_coherent(ar->dev, orig_nbytes, data_buf,
606 ce_data_base);
607 }
608
609 if (ret != 0)
610 ath10k_warn("failed to write diag value at 0x%x: %d\n",
611 address, ret);
612
613 return ret;
614 }
615
616 /* Write 4B data to Target memory or register */
617 static int ath10k_pci_diag_write_access(struct ath10k *ar, u32 address,
618 u32 data)
619 {
620 /* Assume range doesn't cross this boundary */
621 if (address >= DRAM_BASE_ADDRESS)
622 return ath10k_pci_diag_write_mem(ar, address, &data,
623 sizeof(u32));
624
625 ath10k_pci_wake(ar);
626 ath10k_pci_write32(ar, address, data);
627 ath10k_pci_sleep(ar);
628 return 0;
629 }
630
631 static bool ath10k_pci_target_is_awake(struct ath10k *ar)
632 {
633 void __iomem *mem = ath10k_pci_priv(ar)->mem;
634 u32 val;
635 val = ioread32(mem + PCIE_LOCAL_BASE_ADDRESS +
636 RTC_STATE_ADDRESS);
637 return (RTC_STATE_V_GET(val) == RTC_STATE_V_ON);
638 }
639
640 int ath10k_do_pci_wake(struct ath10k *ar)
641 {
642 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
643 void __iomem *pci_addr = ar_pci->mem;
644 int tot_delay = 0;
645 int curr_delay = 5;
646
647 if (atomic_read(&ar_pci->keep_awake_count) == 0) {
648 /* Force AWAKE */
649 iowrite32(PCIE_SOC_WAKE_V_MASK,
650 pci_addr + PCIE_LOCAL_BASE_ADDRESS +
651 PCIE_SOC_WAKE_ADDRESS);
652 }
653 atomic_inc(&ar_pci->keep_awake_count);
654
655 if (ar_pci->verified_awake)
656 return 0;
657
658 for (;;) {
659 if (ath10k_pci_target_is_awake(ar)) {
660 ar_pci->verified_awake = true;
661 return 0;
662 }
663
664 if (tot_delay > PCIE_WAKE_TIMEOUT) {
665 ath10k_warn("target took longer %d us to wake up (awake count %d)\n",
666 PCIE_WAKE_TIMEOUT,
667 atomic_read(&ar_pci->keep_awake_count));
668 return -ETIMEDOUT;
669 }
670
671 udelay(curr_delay);
672 tot_delay += curr_delay;
673
674 if (curr_delay < 50)
675 curr_delay += 5;
676 }
677 }
678
679 void ath10k_do_pci_sleep(struct ath10k *ar)
680 {
681 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
682 void __iomem *pci_addr = ar_pci->mem;
683
684 if (atomic_dec_and_test(&ar_pci->keep_awake_count)) {
685 /* Allow sleep */
686 ar_pci->verified_awake = false;
687 iowrite32(PCIE_SOC_WAKE_RESET,
688 pci_addr + PCIE_LOCAL_BASE_ADDRESS +
689 PCIE_SOC_WAKE_ADDRESS);
690 }
691 }
692
693 /* Called by lower (CE) layer when a send to Target completes. */
694 static void ath10k_pci_ce_send_done(struct ath10k_ce_pipe *ce_state)
695 {
696 struct ath10k *ar = ce_state->ar;
697 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
698 struct ath10k_hif_cb *cb = &ar_pci->msg_callbacks_current;
699 void *transfer_context;
700 u32 ce_data;
701 unsigned int nbytes;
702 unsigned int transfer_id;
703
704 while (ath10k_ce_completed_send_next(ce_state, &transfer_context,
705 &ce_data, &nbytes,
706 &transfer_id) == 0) {
707 /* no need to call tx completion for NULL pointers */
708 if (transfer_context == NULL)
709 continue;
710
711 cb->tx_completion(ar, transfer_context, transfer_id);
712 }
713 }
714
715 /* Called by lower (CE) layer when data is received from the Target. */
716 static void ath10k_pci_ce_recv_data(struct ath10k_ce_pipe *ce_state)
717 {
718 struct ath10k *ar = ce_state->ar;
719 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
720 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id];
721 struct ath10k_hif_cb *cb = &ar_pci->msg_callbacks_current;
722 struct sk_buff *skb;
723 void *transfer_context;
724 u32 ce_data;
725 unsigned int nbytes, max_nbytes;
726 unsigned int transfer_id;
727 unsigned int flags;
728 int err;
729
730 while (ath10k_ce_completed_recv_next(ce_state, &transfer_context,
731 &ce_data, &nbytes, &transfer_id,
732 &flags) == 0) {
733 err = ath10k_pci_post_rx_pipe(pipe_info, 1);
734 if (unlikely(err)) {
735 /* FIXME: retry */
736 ath10k_warn("failed to replenish CE rx ring %d: %d\n",
737 pipe_info->pipe_num, err);
738 }
739
740 skb = transfer_context;
741 max_nbytes = skb->len + skb_tailroom(skb);
742 dma_unmap_single(ar->dev, ATH10K_SKB_CB(skb)->paddr,
743 max_nbytes, DMA_FROM_DEVICE);
744
745 if (unlikely(max_nbytes < nbytes)) {
746 ath10k_warn("rxed more than expected (nbytes %d, max %d)",
747 nbytes, max_nbytes);
748 dev_kfree_skb_any(skb);
749 continue;
750 }
751
752 skb_put(skb, nbytes);
753 cb->rx_completion(ar, skb, pipe_info->pipe_num);
754 }
755 }
756
757 static int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id,
758 struct ath10k_hif_sg_item *items, int n_items)
759 {
760 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
761 struct ath10k_pci_pipe *pci_pipe = &ar_pci->pipe_info[pipe_id];
762 struct ath10k_ce_pipe *ce_pipe = pci_pipe->ce_hdl;
763 struct ath10k_ce_ring *src_ring = ce_pipe->src_ring;
764 unsigned int nentries_mask = src_ring->nentries_mask;
765 unsigned int sw_index = src_ring->sw_index;
766 unsigned int write_index = src_ring->write_index;
767 int err, i;
768
769 spin_lock_bh(&ar_pci->ce_lock);
770
771 if (unlikely(CE_RING_DELTA(nentries_mask,
772 write_index, sw_index - 1) < n_items)) {
773 err = -ENOBUFS;
774 goto unlock;
775 }
776
777 for (i = 0; i < n_items - 1; i++) {
778 ath10k_dbg(ATH10K_DBG_PCI,
779 "pci tx item %d paddr 0x%08x len %d n_items %d\n",
780 i, items[i].paddr, items[i].len, n_items);
781 ath10k_dbg_dump(ATH10K_DBG_PCI_DUMP, NULL, "item data: ",
782 items[i].vaddr, items[i].len);
783
784 err = ath10k_ce_send_nolock(ce_pipe,
785 items[i].transfer_context,
786 items[i].paddr,
787 items[i].len,
788 items[i].transfer_id,
789 CE_SEND_FLAG_GATHER);
790 if (err)
791 goto unlock;
792 }
793
794 /* `i` is equal to `n_items -1` after for() */
795
796 ath10k_dbg(ATH10K_DBG_PCI,
797 "pci tx item %d paddr 0x%08x len %d n_items %d\n",
798 i, items[i].paddr, items[i].len, n_items);
799 ath10k_dbg_dump(ATH10K_DBG_PCI_DUMP, NULL, "item data: ",
800 items[i].vaddr, items[i].len);
801
802 err = ath10k_ce_send_nolock(ce_pipe,
803 items[i].transfer_context,
804 items[i].paddr,
805 items[i].len,
806 items[i].transfer_id,
807 0);
808 if (err)
809 goto unlock;
810
811 err = 0;
812 unlock:
813 spin_unlock_bh(&ar_pci->ce_lock);
814 return err;
815 }
816
817 static u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe)
818 {
819 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
820
821 ath10k_dbg(ATH10K_DBG_PCI, "pci hif get free queue number\n");
822
823 return ath10k_ce_num_free_src_entries(ar_pci->pipe_info[pipe].ce_hdl);
824 }
825
826 static void ath10k_pci_hif_dump_area(struct ath10k *ar)
827 {
828 u32 reg_dump_area = 0;
829 u32 reg_dump_values[REG_DUMP_COUNT_QCA988X] = {};
830 u32 host_addr;
831 int ret;
832 u32 i;
833
834 ath10k_err("firmware crashed!\n");
835 ath10k_err("hardware name %s version 0x%x\n",
836 ar->hw_params.name, ar->target_version);
837 ath10k_err("firmware version: %s\n", ar->hw->wiphy->fw_version);
838
839 host_addr = host_interest_item_address(HI_ITEM(hi_failure_state));
840 ret = ath10k_pci_diag_read_mem(ar, host_addr,
841 &reg_dump_area, sizeof(u32));
842 if (ret) {
843 ath10k_err("failed to read FW dump area address: %d\n", ret);
844 return;
845 }
846
847 ath10k_err("target register Dump Location: 0x%08X\n", reg_dump_area);
848
849 ret = ath10k_pci_diag_read_mem(ar, reg_dump_area,
850 &reg_dump_values[0],
851 REG_DUMP_COUNT_QCA988X * sizeof(u32));
852 if (ret != 0) {
853 ath10k_err("failed to read FW dump area: %d\n", ret);
854 return;
855 }
856
857 BUILD_BUG_ON(REG_DUMP_COUNT_QCA988X % 4);
858
859 ath10k_err("target Register Dump\n");
860 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i += 4)
861 ath10k_err("[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X\n",
862 i,
863 reg_dump_values[i],
864 reg_dump_values[i + 1],
865 reg_dump_values[i + 2],
866 reg_dump_values[i + 3]);
867
868 queue_work(ar->workqueue, &ar->restart_work);
869 }
870
871 static void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe,
872 int force)
873 {
874 ath10k_dbg(ATH10K_DBG_PCI, "pci hif send complete check\n");
875
876 if (!force) {
877 int resources;
878 /*
879 * Decide whether to actually poll for completions, or just
880 * wait for a later chance.
881 * If there seem to be plenty of resources left, then just wait
882 * since checking involves reading a CE register, which is a
883 * relatively expensive operation.
884 */
885 resources = ath10k_pci_hif_get_free_queue_number(ar, pipe);
886
887 /*
888 * If at least 50% of the total resources are still available,
889 * don't bother checking again yet.
890 */
891 if (resources > (host_ce_config_wlan[pipe].src_nentries >> 1))
892 return;
893 }
894 ath10k_ce_per_engine_service(ar, pipe);
895 }
896
897 static void ath10k_pci_hif_set_callbacks(struct ath10k *ar,
898 struct ath10k_hif_cb *callbacks)
899 {
900 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
901
902 ath10k_dbg(ATH10K_DBG_PCI, "pci hif set callbacks\n");
903
904 memcpy(&ar_pci->msg_callbacks_current, callbacks,
905 sizeof(ar_pci->msg_callbacks_current));
906 }
907
908 static int ath10k_pci_setup_ce_irq(struct ath10k *ar)
909 {
910 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
911 const struct ce_attr *attr;
912 struct ath10k_pci_pipe *pipe_info;
913 int pipe_num, disable_interrupts;
914
915 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
916 pipe_info = &ar_pci->pipe_info[pipe_num];
917
918 /* Handle Diagnostic CE specially */
919 if (pipe_info->ce_hdl == ar_pci->ce_diag)
920 continue;
921
922 attr = &host_ce_config_wlan[pipe_num];
923
924 if (attr->src_nentries) {
925 disable_interrupts = attr->flags & CE_ATTR_DIS_INTR;
926 ath10k_ce_send_cb_register(pipe_info->ce_hdl,
927 ath10k_pci_ce_send_done,
928 disable_interrupts);
929 }
930
931 if (attr->dest_nentries)
932 ath10k_ce_recv_cb_register(pipe_info->ce_hdl,
933 ath10k_pci_ce_recv_data);
934 }
935
936 return 0;
937 }
938
939 static void ath10k_pci_kill_tasklet(struct ath10k *ar)
940 {
941 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
942 int i;
943
944 tasklet_kill(&ar_pci->intr_tq);
945 tasklet_kill(&ar_pci->msi_fw_err);
946 tasklet_kill(&ar_pci->early_irq_tasklet);
947
948 for (i = 0; i < CE_COUNT; i++)
949 tasklet_kill(&ar_pci->pipe_info[i].intr);
950 }
951
952 /* TODO - temporary mapping while we have too few CE's */
953 static int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar,
954 u16 service_id, u8 *ul_pipe,
955 u8 *dl_pipe, int *ul_is_polled,
956 int *dl_is_polled)
957 {
958 int ret = 0;
959
960 ath10k_dbg(ATH10K_DBG_PCI, "pci hif map service\n");
961
962 /* polling for received messages not supported */
963 *dl_is_polled = 0;
964
965 switch (service_id) {
966 case ATH10K_HTC_SVC_ID_HTT_DATA_MSG:
967 /*
968 * Host->target HTT gets its own pipe, so it can be polled
969 * while other pipes are interrupt driven.
970 */
971 *ul_pipe = 4;
972 /*
973 * Use the same target->host pipe for HTC ctrl, HTC raw
974 * streams, and HTT.
975 */
976 *dl_pipe = 1;
977 break;
978
979 case ATH10K_HTC_SVC_ID_RSVD_CTRL:
980 case ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS:
981 /*
982 * Note: HTC_RAW_STREAMS_SVC is currently unused, and
983 * HTC_CTRL_RSVD_SVC could share the same pipe as the
984 * WMI services. So, if another CE is needed, change
985 * this to *ul_pipe = 3, which frees up CE 0.
986 */
987 /* *ul_pipe = 3; */
988 *ul_pipe = 0;
989 *dl_pipe = 1;
990 break;
991
992 case ATH10K_HTC_SVC_ID_WMI_DATA_BK:
993 case ATH10K_HTC_SVC_ID_WMI_DATA_BE:
994 case ATH10K_HTC_SVC_ID_WMI_DATA_VI:
995 case ATH10K_HTC_SVC_ID_WMI_DATA_VO:
996
997 case ATH10K_HTC_SVC_ID_WMI_CONTROL:
998 *ul_pipe = 3;
999 *dl_pipe = 2;
1000 break;
1001
1002 /* pipe 5 unused */
1003 /* pipe 6 reserved */
1004 /* pipe 7 reserved */
1005
1006 default:
1007 ret = -1;
1008 break;
1009 }
1010 *ul_is_polled =
1011 (host_ce_config_wlan[*ul_pipe].flags & CE_ATTR_DIS_INTR) != 0;
1012
1013 return ret;
1014 }
1015
1016 static void ath10k_pci_hif_get_default_pipe(struct ath10k *ar,
1017 u8 *ul_pipe, u8 *dl_pipe)
1018 {
1019 int ul_is_polled, dl_is_polled;
1020
1021 ath10k_dbg(ATH10K_DBG_PCI, "pci hif get default pipe\n");
1022
1023 (void)ath10k_pci_hif_map_service_to_pipe(ar,
1024 ATH10K_HTC_SVC_ID_RSVD_CTRL,
1025 ul_pipe,
1026 dl_pipe,
1027 &ul_is_polled,
1028 &dl_is_polled);
1029 }
1030
1031 static int ath10k_pci_post_rx_pipe(struct ath10k_pci_pipe *pipe_info,
1032 int num)
1033 {
1034 struct ath10k *ar = pipe_info->hif_ce_state;
1035 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1036 struct ath10k_ce_pipe *ce_state = pipe_info->ce_hdl;
1037 struct sk_buff *skb;
1038 dma_addr_t ce_data;
1039 int i, ret = 0;
1040
1041 if (pipe_info->buf_sz == 0)
1042 return 0;
1043
1044 for (i = 0; i < num; i++) {
1045 skb = dev_alloc_skb(pipe_info->buf_sz);
1046 if (!skb) {
1047 ath10k_warn("failed to allocate skbuff for pipe %d\n",
1048 num);
1049 ret = -ENOMEM;
1050 goto err;
1051 }
1052
1053 WARN_ONCE((unsigned long)skb->data & 3, "unaligned skb");
1054
1055 ce_data = dma_map_single(ar->dev, skb->data,
1056 skb->len + skb_tailroom(skb),
1057 DMA_FROM_DEVICE);
1058
1059 if (unlikely(dma_mapping_error(ar->dev, ce_data))) {
1060 ath10k_warn("failed to DMA map sk_buff\n");
1061 dev_kfree_skb_any(skb);
1062 ret = -EIO;
1063 goto err;
1064 }
1065
1066 ATH10K_SKB_CB(skb)->paddr = ce_data;
1067
1068 pci_dma_sync_single_for_device(ar_pci->pdev, ce_data,
1069 pipe_info->buf_sz,
1070 PCI_DMA_FROMDEVICE);
1071
1072 ret = ath10k_ce_recv_buf_enqueue(ce_state, (void *)skb,
1073 ce_data);
1074 if (ret) {
1075 ath10k_warn("failed to enqueue to pipe %d: %d\n",
1076 num, ret);
1077 goto err;
1078 }
1079 }
1080
1081 return ret;
1082
1083 err:
1084 ath10k_pci_rx_pipe_cleanup(pipe_info);
1085 return ret;
1086 }
1087
1088 static int ath10k_pci_post_rx(struct ath10k *ar)
1089 {
1090 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1091 struct ath10k_pci_pipe *pipe_info;
1092 const struct ce_attr *attr;
1093 int pipe_num, ret = 0;
1094
1095 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
1096 pipe_info = &ar_pci->pipe_info[pipe_num];
1097 attr = &host_ce_config_wlan[pipe_num];
1098
1099 if (attr->dest_nentries == 0)
1100 continue;
1101
1102 ret = ath10k_pci_post_rx_pipe(pipe_info,
1103 attr->dest_nentries - 1);
1104 if (ret) {
1105 ath10k_warn("failed to post RX buffer for pipe %d: %d\n",
1106 pipe_num, ret);
1107
1108 for (; pipe_num >= 0; pipe_num--) {
1109 pipe_info = &ar_pci->pipe_info[pipe_num];
1110 ath10k_pci_rx_pipe_cleanup(pipe_info);
1111 }
1112 return ret;
1113 }
1114 }
1115
1116 return 0;
1117 }
1118
1119 static int ath10k_pci_hif_start(struct ath10k *ar)
1120 {
1121 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1122 int ret, ret_early;
1123
1124 ath10k_dbg(ATH10K_DBG_BOOT, "boot hif start\n");
1125
1126 ath10k_pci_free_early_irq(ar);
1127 ath10k_pci_kill_tasklet(ar);
1128
1129 ret = ath10k_pci_request_irq(ar);
1130 if (ret) {
1131 ath10k_warn("failed to post RX buffers for all pipes: %d\n",
1132 ret);
1133 goto err_early_irq;
1134 }
1135
1136 ret = ath10k_pci_setup_ce_irq(ar);
1137 if (ret) {
1138 ath10k_warn("failed to setup CE interrupts: %d\n", ret);
1139 goto err_stop;
1140 }
1141
1142 /* Post buffers once to start things off. */
1143 ret = ath10k_pci_post_rx(ar);
1144 if (ret) {
1145 ath10k_warn("failed to post RX buffers for all pipes: %d\n",
1146 ret);
1147 goto err_stop;
1148 }
1149
1150 ar_pci->started = 1;
1151 return 0;
1152
1153 err_stop:
1154 ath10k_ce_disable_interrupts(ar);
1155 ath10k_pci_free_irq(ar);
1156 ath10k_pci_kill_tasklet(ar);
1157 err_early_irq:
1158 /* Though there should be no interrupts (device was reset)
1159 * power_down() expects the early IRQ to be installed as per the
1160 * driver lifecycle. */
1161 ret_early = ath10k_pci_request_early_irq(ar);
1162 if (ret_early)
1163 ath10k_warn("failed to re-enable early irq: %d\n", ret_early);
1164
1165 return ret;
1166 }
1167
1168 static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe *pipe_info)
1169 {
1170 struct ath10k *ar;
1171 struct ath10k_pci *ar_pci;
1172 struct ath10k_ce_pipe *ce_hdl;
1173 u32 buf_sz;
1174 struct sk_buff *netbuf;
1175 u32 ce_data;
1176
1177 buf_sz = pipe_info->buf_sz;
1178
1179 /* Unused Copy Engine */
1180 if (buf_sz == 0)
1181 return;
1182
1183 ar = pipe_info->hif_ce_state;
1184 ar_pci = ath10k_pci_priv(ar);
1185
1186 if (!ar_pci->started)
1187 return;
1188
1189 ce_hdl = pipe_info->ce_hdl;
1190
1191 while (ath10k_ce_revoke_recv_next(ce_hdl, (void **)&netbuf,
1192 &ce_data) == 0) {
1193 dma_unmap_single(ar->dev, ATH10K_SKB_CB(netbuf)->paddr,
1194 netbuf->len + skb_tailroom(netbuf),
1195 DMA_FROM_DEVICE);
1196 dev_kfree_skb_any(netbuf);
1197 }
1198 }
1199
1200 static void ath10k_pci_tx_pipe_cleanup(struct ath10k_pci_pipe *pipe_info)
1201 {
1202 struct ath10k *ar;
1203 struct ath10k_pci *ar_pci;
1204 struct ath10k_ce_pipe *ce_hdl;
1205 struct sk_buff *netbuf;
1206 u32 ce_data;
1207 unsigned int nbytes;
1208 unsigned int id;
1209 u32 buf_sz;
1210
1211 buf_sz = pipe_info->buf_sz;
1212
1213 /* Unused Copy Engine */
1214 if (buf_sz == 0)
1215 return;
1216
1217 ar = pipe_info->hif_ce_state;
1218 ar_pci = ath10k_pci_priv(ar);
1219
1220 if (!ar_pci->started)
1221 return;
1222
1223 ce_hdl = pipe_info->ce_hdl;
1224
1225 while (ath10k_ce_cancel_send_next(ce_hdl, (void **)&netbuf,
1226 &ce_data, &nbytes, &id) == 0) {
1227 /* no need to call tx completion for NULL pointers */
1228 if (!netbuf)
1229 continue;
1230
1231 ar_pci->msg_callbacks_current.tx_completion(ar,
1232 netbuf,
1233 id);
1234 }
1235 }
1236
1237 /*
1238 * Cleanup residual buffers for device shutdown:
1239 * buffers that were enqueued for receive
1240 * buffers that were to be sent
1241 * Note: Buffers that had completed but which were
1242 * not yet processed are on a completion queue. They
1243 * are handled when the completion thread shuts down.
1244 */
1245 static void ath10k_pci_buffer_cleanup(struct ath10k *ar)
1246 {
1247 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1248 int pipe_num;
1249
1250 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
1251 struct ath10k_pci_pipe *pipe_info;
1252
1253 pipe_info = &ar_pci->pipe_info[pipe_num];
1254 ath10k_pci_rx_pipe_cleanup(pipe_info);
1255 ath10k_pci_tx_pipe_cleanup(pipe_info);
1256 }
1257 }
1258
1259 static void ath10k_pci_ce_deinit(struct ath10k *ar)
1260 {
1261 int i;
1262
1263 for (i = 0; i < CE_COUNT; i++)
1264 ath10k_ce_deinit_pipe(ar, i);
1265 }
1266
1267 static void ath10k_pci_hif_stop(struct ath10k *ar)
1268 {
1269 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1270 int ret;
1271
1272 ath10k_dbg(ATH10K_DBG_BOOT, "boot hif stop\n");
1273
1274 ret = ath10k_ce_disable_interrupts(ar);
1275 if (ret)
1276 ath10k_warn("failed to disable CE interrupts: %d\n", ret);
1277
1278 ath10k_pci_free_irq(ar);
1279 ath10k_pci_kill_tasklet(ar);
1280
1281 ret = ath10k_pci_request_early_irq(ar);
1282 if (ret)
1283 ath10k_warn("failed to re-enable early irq: %d\n", ret);
1284
1285 /* At this point, asynchronous threads are stopped, the target should
1286 * not DMA nor interrupt. We process the leftovers and then free
1287 * everything else up. */
1288
1289 ath10k_pci_buffer_cleanup(ar);
1290
1291 /* Make the sure the device won't access any structures on the host by
1292 * resetting it. The device was fed with PCI CE ringbuffer
1293 * configuration during init. If ringbuffers are freed and the device
1294 * were to access them this could lead to memory corruption on the
1295 * host. */
1296 ath10k_pci_warm_reset(ar);
1297
1298 ar_pci->started = 0;
1299 }
1300
1301 static int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar,
1302 void *req, u32 req_len,
1303 void *resp, u32 *resp_len)
1304 {
1305 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1306 struct ath10k_pci_pipe *pci_tx = &ar_pci->pipe_info[BMI_CE_NUM_TO_TARG];
1307 struct ath10k_pci_pipe *pci_rx = &ar_pci->pipe_info[BMI_CE_NUM_TO_HOST];
1308 struct ath10k_ce_pipe *ce_tx = pci_tx->ce_hdl;
1309 struct ath10k_ce_pipe *ce_rx = pci_rx->ce_hdl;
1310 dma_addr_t req_paddr = 0;
1311 dma_addr_t resp_paddr = 0;
1312 struct bmi_xfer xfer = {};
1313 void *treq, *tresp = NULL;
1314 int ret = 0;
1315
1316 might_sleep();
1317
1318 if (resp && !resp_len)
1319 return -EINVAL;
1320
1321 if (resp && resp_len && *resp_len == 0)
1322 return -EINVAL;
1323
1324 treq = kmemdup(req, req_len, GFP_KERNEL);
1325 if (!treq)
1326 return -ENOMEM;
1327
1328 req_paddr = dma_map_single(ar->dev, treq, req_len, DMA_TO_DEVICE);
1329 ret = dma_mapping_error(ar->dev, req_paddr);
1330 if (ret)
1331 goto err_dma;
1332
1333 if (resp && resp_len) {
1334 tresp = kzalloc(*resp_len, GFP_KERNEL);
1335 if (!tresp) {
1336 ret = -ENOMEM;
1337 goto err_req;
1338 }
1339
1340 resp_paddr = dma_map_single(ar->dev, tresp, *resp_len,
1341 DMA_FROM_DEVICE);
1342 ret = dma_mapping_error(ar->dev, resp_paddr);
1343 if (ret)
1344 goto err_req;
1345
1346 xfer.wait_for_resp = true;
1347 xfer.resp_len = 0;
1348
1349 ath10k_ce_recv_buf_enqueue(ce_rx, &xfer, resp_paddr);
1350 }
1351
1352 init_completion(&xfer.done);
1353
1354 ret = ath10k_ce_send(ce_tx, &xfer, req_paddr, req_len, -1, 0);
1355 if (ret)
1356 goto err_resp;
1357
1358 ret = ath10k_pci_bmi_wait(ce_tx, ce_rx, &xfer);
1359 if (ret) {
1360 u32 unused_buffer;
1361 unsigned int unused_nbytes;
1362 unsigned int unused_id;
1363
1364 ath10k_ce_cancel_send_next(ce_tx, NULL, &unused_buffer,
1365 &unused_nbytes, &unused_id);
1366 } else {
1367 /* non-zero means we did not time out */
1368 ret = 0;
1369 }
1370
1371 err_resp:
1372 if (resp) {
1373 u32 unused_buffer;
1374
1375 ath10k_ce_revoke_recv_next(ce_rx, NULL, &unused_buffer);
1376 dma_unmap_single(ar->dev, resp_paddr,
1377 *resp_len, DMA_FROM_DEVICE);
1378 }
1379 err_req:
1380 dma_unmap_single(ar->dev, req_paddr, req_len, DMA_TO_DEVICE);
1381
1382 if (ret == 0 && resp_len) {
1383 *resp_len = min(*resp_len, xfer.resp_len);
1384 memcpy(resp, tresp, xfer.resp_len);
1385 }
1386 err_dma:
1387 kfree(treq);
1388 kfree(tresp);
1389
1390 return ret;
1391 }
1392
1393 static void ath10k_pci_bmi_send_done(struct ath10k_ce_pipe *ce_state)
1394 {
1395 struct bmi_xfer *xfer;
1396 u32 ce_data;
1397 unsigned int nbytes;
1398 unsigned int transfer_id;
1399
1400 if (ath10k_ce_completed_send_next(ce_state, (void **)&xfer, &ce_data,
1401 &nbytes, &transfer_id))
1402 return;
1403
1404 if (xfer->wait_for_resp)
1405 return;
1406
1407 complete(&xfer->done);
1408 }
1409
1410 static void ath10k_pci_bmi_recv_data(struct ath10k_ce_pipe *ce_state)
1411 {
1412 struct bmi_xfer *xfer;
1413 u32 ce_data;
1414 unsigned int nbytes;
1415 unsigned int transfer_id;
1416 unsigned int flags;
1417
1418 if (ath10k_ce_completed_recv_next(ce_state, (void **)&xfer, &ce_data,
1419 &nbytes, &transfer_id, &flags))
1420 return;
1421
1422 if (!xfer->wait_for_resp) {
1423 ath10k_warn("unexpected: BMI data received; ignoring\n");
1424 return;
1425 }
1426
1427 xfer->resp_len = nbytes;
1428 complete(&xfer->done);
1429 }
1430
1431 static int ath10k_pci_bmi_wait(struct ath10k_ce_pipe *tx_pipe,
1432 struct ath10k_ce_pipe *rx_pipe,
1433 struct bmi_xfer *xfer)
1434 {
1435 unsigned long timeout = jiffies + BMI_COMMUNICATION_TIMEOUT_HZ;
1436
1437 while (time_before_eq(jiffies, timeout)) {
1438 ath10k_pci_bmi_send_done(tx_pipe);
1439 ath10k_pci_bmi_recv_data(rx_pipe);
1440
1441 if (completion_done(&xfer->done))
1442 return 0;
1443
1444 schedule();
1445 }
1446
1447 return -ETIMEDOUT;
1448 }
1449
1450 /*
1451 * Map from service/endpoint to Copy Engine.
1452 * This table is derived from the CE_PCI TABLE, above.
1453 * It is passed to the Target at startup for use by firmware.
1454 */
1455 static const struct service_to_pipe target_service_to_ce_map_wlan[] = {
1456 {
1457 ATH10K_HTC_SVC_ID_WMI_DATA_VO,
1458 PIPEDIR_OUT, /* out = UL = host -> target */
1459 3,
1460 },
1461 {
1462 ATH10K_HTC_SVC_ID_WMI_DATA_VO,
1463 PIPEDIR_IN, /* in = DL = target -> host */
1464 2,
1465 },
1466 {
1467 ATH10K_HTC_SVC_ID_WMI_DATA_BK,
1468 PIPEDIR_OUT, /* out = UL = host -> target */
1469 3,
1470 },
1471 {
1472 ATH10K_HTC_SVC_ID_WMI_DATA_BK,
1473 PIPEDIR_IN, /* in = DL = target -> host */
1474 2,
1475 },
1476 {
1477 ATH10K_HTC_SVC_ID_WMI_DATA_BE,
1478 PIPEDIR_OUT, /* out = UL = host -> target */
1479 3,
1480 },
1481 {
1482 ATH10K_HTC_SVC_ID_WMI_DATA_BE,
1483 PIPEDIR_IN, /* in = DL = target -> host */
1484 2,
1485 },
1486 {
1487 ATH10K_HTC_SVC_ID_WMI_DATA_VI,
1488 PIPEDIR_OUT, /* out = UL = host -> target */
1489 3,
1490 },
1491 {
1492 ATH10K_HTC_SVC_ID_WMI_DATA_VI,
1493 PIPEDIR_IN, /* in = DL = target -> host */
1494 2,
1495 },
1496 {
1497 ATH10K_HTC_SVC_ID_WMI_CONTROL,
1498 PIPEDIR_OUT, /* out = UL = host -> target */
1499 3,
1500 },
1501 {
1502 ATH10K_HTC_SVC_ID_WMI_CONTROL,
1503 PIPEDIR_IN, /* in = DL = target -> host */
1504 2,
1505 },
1506 {
1507 ATH10K_HTC_SVC_ID_RSVD_CTRL,
1508 PIPEDIR_OUT, /* out = UL = host -> target */
1509 0, /* could be moved to 3 (share with WMI) */
1510 },
1511 {
1512 ATH10K_HTC_SVC_ID_RSVD_CTRL,
1513 PIPEDIR_IN, /* in = DL = target -> host */
1514 1,
1515 },
1516 {
1517 ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS, /* not currently used */
1518 PIPEDIR_OUT, /* out = UL = host -> target */
1519 0,
1520 },
1521 {
1522 ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS, /* not currently used */
1523 PIPEDIR_IN, /* in = DL = target -> host */
1524 1,
1525 },
1526 {
1527 ATH10K_HTC_SVC_ID_HTT_DATA_MSG,
1528 PIPEDIR_OUT, /* out = UL = host -> target */
1529 4,
1530 },
1531 {
1532 ATH10K_HTC_SVC_ID_HTT_DATA_MSG,
1533 PIPEDIR_IN, /* in = DL = target -> host */
1534 1,
1535 },
1536
1537 /* (Additions here) */
1538
1539 { /* Must be last */
1540 0,
1541 0,
1542 0,
1543 },
1544 };
1545
1546 /*
1547 * Send an interrupt to the device to wake up the Target CPU
1548 * so it has an opportunity to notice any changed state.
1549 */
1550 static int ath10k_pci_wake_target_cpu(struct ath10k *ar)
1551 {
1552 int ret;
1553 u32 core_ctrl;
1554
1555 ret = ath10k_pci_diag_read_access(ar, SOC_CORE_BASE_ADDRESS |
1556 CORE_CTRL_ADDRESS,
1557 &core_ctrl);
1558 if (ret) {
1559 ath10k_warn("failed to read core_ctrl: %d\n", ret);
1560 return ret;
1561 }
1562
1563 /* A_INUM_FIRMWARE interrupt to Target CPU */
1564 core_ctrl |= CORE_CTRL_CPU_INTR_MASK;
1565
1566 ret = ath10k_pci_diag_write_access(ar, SOC_CORE_BASE_ADDRESS |
1567 CORE_CTRL_ADDRESS,
1568 core_ctrl);
1569 if (ret) {
1570 ath10k_warn("failed to set target CPU interrupt mask: %d\n",
1571 ret);
1572 return ret;
1573 }
1574
1575 return 0;
1576 }
1577
1578 static int ath10k_pci_init_config(struct ath10k *ar)
1579 {
1580 u32 interconnect_targ_addr;
1581 u32 pcie_state_targ_addr = 0;
1582 u32 pipe_cfg_targ_addr = 0;
1583 u32 svc_to_pipe_map = 0;
1584 u32 pcie_config_flags = 0;
1585 u32 ealloc_value;
1586 u32 ealloc_targ_addr;
1587 u32 flag2_value;
1588 u32 flag2_targ_addr;
1589 int ret = 0;
1590
1591 /* Download to Target the CE Config and the service-to-CE map */
1592 interconnect_targ_addr =
1593 host_interest_item_address(HI_ITEM(hi_interconnect_state));
1594
1595 /* Supply Target-side CE configuration */
1596 ret = ath10k_pci_diag_read_access(ar, interconnect_targ_addr,
1597 &pcie_state_targ_addr);
1598 if (ret != 0) {
1599 ath10k_err("Failed to get pcie state addr: %d\n", ret);
1600 return ret;
1601 }
1602
1603 if (pcie_state_targ_addr == 0) {
1604 ret = -EIO;
1605 ath10k_err("Invalid pcie state addr\n");
1606 return ret;
1607 }
1608
1609 ret = ath10k_pci_diag_read_access(ar, pcie_state_targ_addr +
1610 offsetof(struct pcie_state,
1611 pipe_cfg_addr),
1612 &pipe_cfg_targ_addr);
1613 if (ret != 0) {
1614 ath10k_err("Failed to get pipe cfg addr: %d\n", ret);
1615 return ret;
1616 }
1617
1618 if (pipe_cfg_targ_addr == 0) {
1619 ret = -EIO;
1620 ath10k_err("Invalid pipe cfg addr\n");
1621 return ret;
1622 }
1623
1624 ret = ath10k_pci_diag_write_mem(ar, pipe_cfg_targ_addr,
1625 target_ce_config_wlan,
1626 sizeof(target_ce_config_wlan));
1627
1628 if (ret != 0) {
1629 ath10k_err("Failed to write pipe cfg: %d\n", ret);
1630 return ret;
1631 }
1632
1633 ret = ath10k_pci_diag_read_access(ar, pcie_state_targ_addr +
1634 offsetof(struct pcie_state,
1635 svc_to_pipe_map),
1636 &svc_to_pipe_map);
1637 if (ret != 0) {
1638 ath10k_err("Failed to get svc/pipe map: %d\n", ret);
1639 return ret;
1640 }
1641
1642 if (svc_to_pipe_map == 0) {
1643 ret = -EIO;
1644 ath10k_err("Invalid svc_to_pipe map\n");
1645 return ret;
1646 }
1647
1648 ret = ath10k_pci_diag_write_mem(ar, svc_to_pipe_map,
1649 target_service_to_ce_map_wlan,
1650 sizeof(target_service_to_ce_map_wlan));
1651 if (ret != 0) {
1652 ath10k_err("Failed to write svc/pipe map: %d\n", ret);
1653 return ret;
1654 }
1655
1656 ret = ath10k_pci_diag_read_access(ar, pcie_state_targ_addr +
1657 offsetof(struct pcie_state,
1658 config_flags),
1659 &pcie_config_flags);
1660 if (ret != 0) {
1661 ath10k_err("Failed to get pcie config_flags: %d\n", ret);
1662 return ret;
1663 }
1664
1665 pcie_config_flags &= ~PCIE_CONFIG_FLAG_ENABLE_L1;
1666
1667 ret = ath10k_pci_diag_write_mem(ar, pcie_state_targ_addr +
1668 offsetof(struct pcie_state, config_flags),
1669 &pcie_config_flags,
1670 sizeof(pcie_config_flags));
1671 if (ret != 0) {
1672 ath10k_err("Failed to write pcie config_flags: %d\n", ret);
1673 return ret;
1674 }
1675
1676 /* configure early allocation */
1677 ealloc_targ_addr = host_interest_item_address(HI_ITEM(hi_early_alloc));
1678
1679 ret = ath10k_pci_diag_read_access(ar, ealloc_targ_addr, &ealloc_value);
1680 if (ret != 0) {
1681 ath10k_err("Faile to get early alloc val: %d\n", ret);
1682 return ret;
1683 }
1684
1685 /* first bank is switched to IRAM */
1686 ealloc_value |= ((HI_EARLY_ALLOC_MAGIC << HI_EARLY_ALLOC_MAGIC_SHIFT) &
1687 HI_EARLY_ALLOC_MAGIC_MASK);
1688 ealloc_value |= ((1 << HI_EARLY_ALLOC_IRAM_BANKS_SHIFT) &
1689 HI_EARLY_ALLOC_IRAM_BANKS_MASK);
1690
1691 ret = ath10k_pci_diag_write_access(ar, ealloc_targ_addr, ealloc_value);
1692 if (ret != 0) {
1693 ath10k_err("Failed to set early alloc val: %d\n", ret);
1694 return ret;
1695 }
1696
1697 /* Tell Target to proceed with initialization */
1698 flag2_targ_addr = host_interest_item_address(HI_ITEM(hi_option_flag2));
1699
1700 ret = ath10k_pci_diag_read_access(ar, flag2_targ_addr, &flag2_value);
1701 if (ret != 0) {
1702 ath10k_err("Failed to get option val: %d\n", ret);
1703 return ret;
1704 }
1705
1706 flag2_value |= HI_OPTION_EARLY_CFG_DONE;
1707
1708 ret = ath10k_pci_diag_write_access(ar, flag2_targ_addr, flag2_value);
1709 if (ret != 0) {
1710 ath10k_err("Failed to set option val: %d\n", ret);
1711 return ret;
1712 }
1713
1714 return 0;
1715 }
1716
1717 static int ath10k_pci_alloc_ce(struct ath10k *ar)
1718 {
1719 int i, ret;
1720
1721 for (i = 0; i < CE_COUNT; i++) {
1722 ret = ath10k_ce_alloc_pipe(ar, i, &host_ce_config_wlan[i]);
1723 if (ret) {
1724 ath10k_err("failed to allocate copy engine pipe %d: %d\n",
1725 i, ret);
1726 return ret;
1727 }
1728 }
1729
1730 return 0;
1731 }
1732
1733 static void ath10k_pci_free_ce(struct ath10k *ar)
1734 {
1735 int i;
1736
1737 for (i = 0; i < CE_COUNT; i++)
1738 ath10k_ce_free_pipe(ar, i);
1739 }
1740
1741 static int ath10k_pci_ce_init(struct ath10k *ar)
1742 {
1743 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1744 struct ath10k_pci_pipe *pipe_info;
1745 const struct ce_attr *attr;
1746 int pipe_num, ret;
1747
1748 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
1749 pipe_info = &ar_pci->pipe_info[pipe_num];
1750 pipe_info->ce_hdl = &ar_pci->ce_states[pipe_num];
1751 pipe_info->pipe_num = pipe_num;
1752 pipe_info->hif_ce_state = ar;
1753 attr = &host_ce_config_wlan[pipe_num];
1754
1755 ret = ath10k_ce_init_pipe(ar, pipe_num, attr);
1756 if (ret) {
1757 ath10k_err("failed to initialize copy engine pipe %d: %d\n",
1758 pipe_num, ret);
1759 return ret;
1760 }
1761
1762 if (pipe_num == CE_COUNT - 1) {
1763 /*
1764 * Reserve the ultimate CE for
1765 * diagnostic Window support
1766 */
1767 ar_pci->ce_diag = pipe_info->ce_hdl;
1768 continue;
1769 }
1770
1771 pipe_info->buf_sz = (size_t) (attr->src_sz_max);
1772 }
1773
1774 return 0;
1775 }
1776
1777 static void ath10k_pci_fw_interrupt_handler(struct ath10k *ar)
1778 {
1779 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1780 u32 fw_indicator;
1781
1782 ath10k_pci_wake(ar);
1783
1784 fw_indicator = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
1785
1786 if (fw_indicator & FW_IND_EVENT_PENDING) {
1787 /* ACK: clear Target-side pending event */
1788 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS,
1789 fw_indicator & ~FW_IND_EVENT_PENDING);
1790
1791 if (ar_pci->started) {
1792 ath10k_pci_hif_dump_area(ar);
1793 } else {
1794 /*
1795 * Probable Target failure before we're prepared
1796 * to handle it. Generally unexpected.
1797 */
1798 ath10k_warn("early firmware event indicated\n");
1799 }
1800 }
1801
1802 ath10k_pci_sleep(ar);
1803 }
1804
1805 /* this function effectively clears target memory controller assert line */
1806 static void ath10k_pci_warm_reset_si0(struct ath10k *ar)
1807 {
1808 u32 val;
1809
1810 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
1811 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS,
1812 val | SOC_RESET_CONTROL_SI0_RST_MASK);
1813 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
1814
1815 msleep(10);
1816
1817 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
1818 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS,
1819 val & ~SOC_RESET_CONTROL_SI0_RST_MASK);
1820 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
1821
1822 msleep(10);
1823 }
1824
1825 static int ath10k_pci_warm_reset(struct ath10k *ar)
1826 {
1827 int ret = 0;
1828 u32 val;
1829
1830 ath10k_dbg(ATH10K_DBG_BOOT, "boot warm reset\n");
1831
1832 ret = ath10k_do_pci_wake(ar);
1833 if (ret) {
1834 ath10k_err("failed to wake up target: %d\n", ret);
1835 return ret;
1836 }
1837
1838 /* debug */
1839 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1840 PCIE_INTR_CAUSE_ADDRESS);
1841 ath10k_dbg(ATH10K_DBG_BOOT, "boot host cpu intr cause: 0x%08x\n", val);
1842
1843 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1844 CPU_INTR_ADDRESS);
1845 ath10k_dbg(ATH10K_DBG_BOOT, "boot target cpu intr cause: 0x%08x\n",
1846 val);
1847
1848 /* disable pending irqs */
1849 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
1850 PCIE_INTR_ENABLE_ADDRESS, 0);
1851
1852 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
1853 PCIE_INTR_CLR_ADDRESS, ~0);
1854
1855 msleep(100);
1856
1857 /* clear fw indicator */
1858 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, 0);
1859
1860 /* clear target LF timer interrupts */
1861 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
1862 SOC_LF_TIMER_CONTROL0_ADDRESS);
1863 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS +
1864 SOC_LF_TIMER_CONTROL0_ADDRESS,
1865 val & ~SOC_LF_TIMER_CONTROL0_ENABLE_MASK);
1866
1867 /* reset CE */
1868 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
1869 SOC_RESET_CONTROL_ADDRESS);
1870 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
1871 val | SOC_RESET_CONTROL_CE_RST_MASK);
1872 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
1873 SOC_RESET_CONTROL_ADDRESS);
1874 msleep(10);
1875
1876 /* unreset CE */
1877 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
1878 val & ~SOC_RESET_CONTROL_CE_RST_MASK);
1879 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
1880 SOC_RESET_CONTROL_ADDRESS);
1881 msleep(10);
1882
1883 ath10k_pci_warm_reset_si0(ar);
1884
1885 /* debug */
1886 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1887 PCIE_INTR_CAUSE_ADDRESS);
1888 ath10k_dbg(ATH10K_DBG_BOOT, "boot host cpu intr cause: 0x%08x\n", val);
1889
1890 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1891 CPU_INTR_ADDRESS);
1892 ath10k_dbg(ATH10K_DBG_BOOT, "boot target cpu intr cause: 0x%08x\n",
1893 val);
1894
1895 /* CPU warm reset */
1896 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
1897 SOC_RESET_CONTROL_ADDRESS);
1898 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
1899 val | SOC_RESET_CONTROL_CPU_WARM_RST_MASK);
1900
1901 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
1902 SOC_RESET_CONTROL_ADDRESS);
1903 ath10k_dbg(ATH10K_DBG_BOOT, "boot target reset state: 0x%08x\n", val);
1904
1905 msleep(100);
1906
1907 ath10k_dbg(ATH10K_DBG_BOOT, "boot warm reset complete\n");
1908
1909 ath10k_do_pci_sleep(ar);
1910 return ret;
1911 }
1912
1913 static int __ath10k_pci_hif_power_up(struct ath10k *ar, bool cold_reset)
1914 {
1915 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1916 const char *irq_mode;
1917 int ret;
1918
1919 /*
1920 * Bring the target up cleanly.
1921 *
1922 * The target may be in an undefined state with an AUX-powered Target
1923 * and a Host in WoW mode. If the Host crashes, loses power, or is
1924 * restarted (without unloading the driver) then the Target is left
1925 * (aux) powered and running. On a subsequent driver load, the Target
1926 * is in an unexpected state. We try to catch that here in order to
1927 * reset the Target and retry the probe.
1928 */
1929 if (cold_reset)
1930 ret = ath10k_pci_cold_reset(ar);
1931 else
1932 ret = ath10k_pci_warm_reset(ar);
1933
1934 if (ret) {
1935 ath10k_err("failed to reset target: %d\n", ret);
1936 goto err;
1937 }
1938
1939 if (!test_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE, ar_pci->features))
1940 /* Force AWAKE forever */
1941 ath10k_do_pci_wake(ar);
1942
1943 ret = ath10k_pci_ce_init(ar);
1944 if (ret) {
1945 ath10k_err("failed to initialize CE: %d\n", ret);
1946 goto err_ps;
1947 }
1948
1949 ret = ath10k_ce_disable_interrupts(ar);
1950 if (ret) {
1951 ath10k_err("failed to disable CE interrupts: %d\n", ret);
1952 goto err_ce;
1953 }
1954
1955 ret = ath10k_pci_init_irq(ar);
1956 if (ret) {
1957 ath10k_err("failed to init irqs: %d\n", ret);
1958 goto err_ce;
1959 }
1960
1961 ret = ath10k_pci_request_early_irq(ar);
1962 if (ret) {
1963 ath10k_err("failed to request early irq: %d\n", ret);
1964 goto err_deinit_irq;
1965 }
1966
1967 ret = ath10k_pci_wait_for_target_init(ar);
1968 if (ret) {
1969 ath10k_err("failed to wait for target to init: %d\n", ret);
1970 goto err_free_early_irq;
1971 }
1972
1973 ret = ath10k_pci_init_config(ar);
1974 if (ret) {
1975 ath10k_err("failed to setup init config: %d\n", ret);
1976 goto err_free_early_irq;
1977 }
1978
1979 ret = ath10k_pci_wake_target_cpu(ar);
1980 if (ret) {
1981 ath10k_err("could not wake up target CPU: %d\n", ret);
1982 goto err_free_early_irq;
1983 }
1984
1985 if (ar_pci->num_msi_intrs > 1)
1986 irq_mode = "MSI-X";
1987 else if (ar_pci->num_msi_intrs == 1)
1988 irq_mode = "MSI";
1989 else
1990 irq_mode = "legacy";
1991
1992 if (!test_bit(ATH10K_FLAG_FIRST_BOOT_DONE, &ar->dev_flags))
1993 ath10k_info("pci irq %s irq_mode %d reset_mode %d\n",
1994 irq_mode, ath10k_pci_irq_mode,
1995 ath10k_pci_reset_mode);
1996
1997 return 0;
1998
1999 err_free_early_irq:
2000 ath10k_pci_free_early_irq(ar);
2001 err_deinit_irq:
2002 ath10k_pci_deinit_irq(ar);
2003 err_ce:
2004 ath10k_pci_ce_deinit(ar);
2005 ath10k_pci_warm_reset(ar);
2006 err_ps:
2007 if (!test_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE, ar_pci->features))
2008 ath10k_do_pci_sleep(ar);
2009 err:
2010 return ret;
2011 }
2012
2013 static int ath10k_pci_hif_power_up(struct ath10k *ar)
2014 {
2015 int ret;
2016
2017 ath10k_dbg(ATH10K_DBG_BOOT, "boot hif power up\n");
2018
2019 /*
2020 * Hardware CUS232 version 2 has some issues with cold reset and the
2021 * preferred (and safer) way to perform a device reset is through a
2022 * warm reset.
2023 *
2024 * Warm reset doesn't always work though (notably after a firmware
2025 * crash) so fall back to cold reset if necessary.
2026 */
2027 ret = __ath10k_pci_hif_power_up(ar, false);
2028 if (ret) {
2029 ath10k_warn("failed to power up target using warm reset: %d\n",
2030 ret);
2031
2032 if (ath10k_pci_reset_mode == ATH10K_PCI_RESET_WARM_ONLY)
2033 return ret;
2034
2035 ath10k_warn("trying cold reset\n");
2036
2037 ret = __ath10k_pci_hif_power_up(ar, true);
2038 if (ret) {
2039 ath10k_err("failed to power up target using cold reset too (%d)\n",
2040 ret);
2041 return ret;
2042 }
2043 }
2044
2045 return 0;
2046 }
2047
2048 static void ath10k_pci_hif_power_down(struct ath10k *ar)
2049 {
2050 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2051
2052 ath10k_dbg(ATH10K_DBG_BOOT, "boot hif power down\n");
2053
2054 ath10k_pci_free_early_irq(ar);
2055 ath10k_pci_kill_tasklet(ar);
2056 ath10k_pci_deinit_irq(ar);
2057 ath10k_pci_ce_deinit(ar);
2058 ath10k_pci_warm_reset(ar);
2059
2060 if (!test_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE, ar_pci->features))
2061 ath10k_do_pci_sleep(ar);
2062 }
2063
2064 #ifdef CONFIG_PM
2065
2066 #define ATH10K_PCI_PM_CONTROL 0x44
2067
2068 static int ath10k_pci_hif_suspend(struct ath10k *ar)
2069 {
2070 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2071 struct pci_dev *pdev = ar_pci->pdev;
2072 u32 val;
2073
2074 pci_read_config_dword(pdev, ATH10K_PCI_PM_CONTROL, &val);
2075
2076 if ((val & 0x000000ff) != 0x3) {
2077 pci_save_state(pdev);
2078 pci_disable_device(pdev);
2079 pci_write_config_dword(pdev, ATH10K_PCI_PM_CONTROL,
2080 (val & 0xffffff00) | 0x03);
2081 }
2082
2083 return 0;
2084 }
2085
2086 static int ath10k_pci_hif_resume(struct ath10k *ar)
2087 {
2088 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2089 struct pci_dev *pdev = ar_pci->pdev;
2090 u32 val;
2091
2092 pci_read_config_dword(pdev, ATH10K_PCI_PM_CONTROL, &val);
2093
2094 if ((val & 0x000000ff) != 0) {
2095 pci_restore_state(pdev);
2096 pci_write_config_dword(pdev, ATH10K_PCI_PM_CONTROL,
2097 val & 0xffffff00);
2098 /*
2099 * Suspend/Resume resets the PCI configuration space,
2100 * so we have to re-disable the RETRY_TIMEOUT register (0x41)
2101 * to keep PCI Tx retries from interfering with C3 CPU state
2102 */
2103 pci_read_config_dword(pdev, 0x40, &val);
2104
2105 if ((val & 0x0000ff00) != 0)
2106 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2107 }
2108
2109 return 0;
2110 }
2111 #endif
2112
2113 static const struct ath10k_hif_ops ath10k_pci_hif_ops = {
2114 .tx_sg = ath10k_pci_hif_tx_sg,
2115 .exchange_bmi_msg = ath10k_pci_hif_exchange_bmi_msg,
2116 .start = ath10k_pci_hif_start,
2117 .stop = ath10k_pci_hif_stop,
2118 .map_service_to_pipe = ath10k_pci_hif_map_service_to_pipe,
2119 .get_default_pipe = ath10k_pci_hif_get_default_pipe,
2120 .send_complete_check = ath10k_pci_hif_send_complete_check,
2121 .set_callbacks = ath10k_pci_hif_set_callbacks,
2122 .get_free_queue_number = ath10k_pci_hif_get_free_queue_number,
2123 .power_up = ath10k_pci_hif_power_up,
2124 .power_down = ath10k_pci_hif_power_down,
2125 #ifdef CONFIG_PM
2126 .suspend = ath10k_pci_hif_suspend,
2127 .resume = ath10k_pci_hif_resume,
2128 #endif
2129 };
2130
2131 static void ath10k_pci_ce_tasklet(unsigned long ptr)
2132 {
2133 struct ath10k_pci_pipe *pipe = (struct ath10k_pci_pipe *)ptr;
2134 struct ath10k_pci *ar_pci = pipe->ar_pci;
2135
2136 ath10k_ce_per_engine_service(ar_pci->ar, pipe->pipe_num);
2137 }
2138
2139 static void ath10k_msi_err_tasklet(unsigned long data)
2140 {
2141 struct ath10k *ar = (struct ath10k *)data;
2142
2143 ath10k_pci_fw_interrupt_handler(ar);
2144 }
2145
2146 /*
2147 * Handler for a per-engine interrupt on a PARTICULAR CE.
2148 * This is used in cases where each CE has a private MSI interrupt.
2149 */
2150 static irqreturn_t ath10k_pci_per_engine_handler(int irq, void *arg)
2151 {
2152 struct ath10k *ar = arg;
2153 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2154 int ce_id = irq - ar_pci->pdev->irq - MSI_ASSIGN_CE_INITIAL;
2155
2156 if (ce_id < 0 || ce_id >= ARRAY_SIZE(ar_pci->pipe_info)) {
2157 ath10k_warn("unexpected/invalid irq %d ce_id %d\n", irq, ce_id);
2158 return IRQ_HANDLED;
2159 }
2160
2161 /*
2162 * NOTE: We are able to derive ce_id from irq because we
2163 * use a one-to-one mapping for CE's 0..5.
2164 * CE's 6 & 7 do not use interrupts at all.
2165 *
2166 * This mapping must be kept in sync with the mapping
2167 * used by firmware.
2168 */
2169 tasklet_schedule(&ar_pci->pipe_info[ce_id].intr);
2170 return IRQ_HANDLED;
2171 }
2172
2173 static irqreturn_t ath10k_pci_msi_fw_handler(int irq, void *arg)
2174 {
2175 struct ath10k *ar = arg;
2176 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2177
2178 tasklet_schedule(&ar_pci->msi_fw_err);
2179 return IRQ_HANDLED;
2180 }
2181
2182 /*
2183 * Top-level interrupt handler for all PCI interrupts from a Target.
2184 * When a block of MSI interrupts is allocated, this top-level handler
2185 * is not used; instead, we directly call the correct sub-handler.
2186 */
2187 static irqreturn_t ath10k_pci_interrupt_handler(int irq, void *arg)
2188 {
2189 struct ath10k *ar = arg;
2190 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2191
2192 if (ar_pci->num_msi_intrs == 0) {
2193 if (!ath10k_pci_irq_pending(ar))
2194 return IRQ_NONE;
2195
2196 ath10k_pci_disable_and_clear_legacy_irq(ar);
2197 }
2198
2199 tasklet_schedule(&ar_pci->intr_tq);
2200
2201 return IRQ_HANDLED;
2202 }
2203
2204 static void ath10k_pci_early_irq_tasklet(unsigned long data)
2205 {
2206 struct ath10k *ar = (struct ath10k *)data;
2207 u32 fw_ind;
2208 int ret;
2209
2210 ret = ath10k_pci_wake(ar);
2211 if (ret) {
2212 ath10k_warn("failed to wake target in early irq tasklet: %d\n",
2213 ret);
2214 return;
2215 }
2216
2217 fw_ind = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
2218 if (fw_ind & FW_IND_EVENT_PENDING) {
2219 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS,
2220 fw_ind & ~FW_IND_EVENT_PENDING);
2221
2222 /* Some structures are unavailable during early boot or at
2223 * driver teardown so just print that the device has crashed. */
2224 ath10k_warn("device crashed - no diagnostics available\n");
2225 }
2226
2227 ath10k_pci_sleep(ar);
2228 ath10k_pci_enable_legacy_irq(ar);
2229 }
2230
2231 static void ath10k_pci_tasklet(unsigned long data)
2232 {
2233 struct ath10k *ar = (struct ath10k *)data;
2234 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2235
2236 ath10k_pci_fw_interrupt_handler(ar); /* FIXME: Handle FW error */
2237 ath10k_ce_per_engine_service_any(ar);
2238
2239 /* Re-enable legacy irq that was disabled in the irq handler */
2240 if (ar_pci->num_msi_intrs == 0)
2241 ath10k_pci_enable_legacy_irq(ar);
2242 }
2243
2244 static int ath10k_pci_request_irq_msix(struct ath10k *ar)
2245 {
2246 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2247 int ret, i;
2248
2249 ret = request_irq(ar_pci->pdev->irq + MSI_ASSIGN_FW,
2250 ath10k_pci_msi_fw_handler,
2251 IRQF_SHARED, "ath10k_pci", ar);
2252 if (ret) {
2253 ath10k_warn("failed to request MSI-X fw irq %d: %d\n",
2254 ar_pci->pdev->irq + MSI_ASSIGN_FW, ret);
2255 return ret;
2256 }
2257
2258 for (i = MSI_ASSIGN_CE_INITIAL; i <= MSI_ASSIGN_CE_MAX; i++) {
2259 ret = request_irq(ar_pci->pdev->irq + i,
2260 ath10k_pci_per_engine_handler,
2261 IRQF_SHARED, "ath10k_pci", ar);
2262 if (ret) {
2263 ath10k_warn("failed to request MSI-X ce irq %d: %d\n",
2264 ar_pci->pdev->irq + i, ret);
2265
2266 for (i--; i >= MSI_ASSIGN_CE_INITIAL; i--)
2267 free_irq(ar_pci->pdev->irq + i, ar);
2268
2269 free_irq(ar_pci->pdev->irq + MSI_ASSIGN_FW, ar);
2270 return ret;
2271 }
2272 }
2273
2274 return 0;
2275 }
2276
2277 static int ath10k_pci_request_irq_msi(struct ath10k *ar)
2278 {
2279 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2280 int ret;
2281
2282 ret = request_irq(ar_pci->pdev->irq,
2283 ath10k_pci_interrupt_handler,
2284 IRQF_SHARED, "ath10k_pci", ar);
2285 if (ret) {
2286 ath10k_warn("failed to request MSI irq %d: %d\n",
2287 ar_pci->pdev->irq, ret);
2288 return ret;
2289 }
2290
2291 return 0;
2292 }
2293
2294 static int ath10k_pci_request_irq_legacy(struct ath10k *ar)
2295 {
2296 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2297 int ret;
2298
2299 ret = request_irq(ar_pci->pdev->irq,
2300 ath10k_pci_interrupt_handler,
2301 IRQF_SHARED, "ath10k_pci", ar);
2302 if (ret) {
2303 ath10k_warn("failed to request legacy irq %d: %d\n",
2304 ar_pci->pdev->irq, ret);
2305 return ret;
2306 }
2307
2308 return 0;
2309 }
2310
2311 static int ath10k_pci_request_irq(struct ath10k *ar)
2312 {
2313 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2314
2315 switch (ar_pci->num_msi_intrs) {
2316 case 0:
2317 return ath10k_pci_request_irq_legacy(ar);
2318 case 1:
2319 return ath10k_pci_request_irq_msi(ar);
2320 case MSI_NUM_REQUEST:
2321 return ath10k_pci_request_irq_msix(ar);
2322 }
2323
2324 ath10k_warn("unknown irq configuration upon request\n");
2325 return -EINVAL;
2326 }
2327
2328 static void ath10k_pci_free_irq(struct ath10k *ar)
2329 {
2330 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2331 int i;
2332
2333 /* There's at least one interrupt irregardless whether its legacy INTR
2334 * or MSI or MSI-X */
2335 for (i = 0; i < max(1, ar_pci->num_msi_intrs); i++)
2336 free_irq(ar_pci->pdev->irq + i, ar);
2337 }
2338
2339 static void ath10k_pci_init_irq_tasklets(struct ath10k *ar)
2340 {
2341 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2342 int i;
2343
2344 tasklet_init(&ar_pci->intr_tq, ath10k_pci_tasklet, (unsigned long)ar);
2345 tasklet_init(&ar_pci->msi_fw_err, ath10k_msi_err_tasklet,
2346 (unsigned long)ar);
2347 tasklet_init(&ar_pci->early_irq_tasklet, ath10k_pci_early_irq_tasklet,
2348 (unsigned long)ar);
2349
2350 for (i = 0; i < CE_COUNT; i++) {
2351 ar_pci->pipe_info[i].ar_pci = ar_pci;
2352 tasklet_init(&ar_pci->pipe_info[i].intr, ath10k_pci_ce_tasklet,
2353 (unsigned long)&ar_pci->pipe_info[i]);
2354 }
2355 }
2356
2357 static int ath10k_pci_init_irq(struct ath10k *ar)
2358 {
2359 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2360 bool msix_supported = test_bit(ATH10K_PCI_FEATURE_MSI_X,
2361 ar_pci->features);
2362 int ret;
2363
2364 ath10k_pci_init_irq_tasklets(ar);
2365
2366 if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_AUTO &&
2367 !test_bit(ATH10K_FLAG_FIRST_BOOT_DONE, &ar->dev_flags))
2368 ath10k_info("limiting irq mode to: %d\n", ath10k_pci_irq_mode);
2369
2370 /* Try MSI-X */
2371 if (ath10k_pci_irq_mode == ATH10K_PCI_IRQ_AUTO && msix_supported) {
2372 ar_pci->num_msi_intrs = MSI_NUM_REQUEST;
2373 ret = pci_enable_msi_range(ar_pci->pdev, ar_pci->num_msi_intrs,
2374 ar_pci->num_msi_intrs);
2375 if (ret > 0)
2376 return 0;
2377
2378 /* fall-through */
2379 }
2380
2381 /* Try MSI */
2382 if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_LEGACY) {
2383 ar_pci->num_msi_intrs = 1;
2384 ret = pci_enable_msi(ar_pci->pdev);
2385 if (ret == 0)
2386 return 0;
2387
2388 /* fall-through */
2389 }
2390
2391 /* Try legacy irq
2392 *
2393 * A potential race occurs here: The CORE_BASE write
2394 * depends on target correctly decoding AXI address but
2395 * host won't know when target writes BAR to CORE_CTRL.
2396 * This write might get lost if target has NOT written BAR.
2397 * For now, fix the race by repeating the write in below
2398 * synchronization checking. */
2399 ar_pci->num_msi_intrs = 0;
2400
2401 ret = ath10k_pci_wake(ar);
2402 if (ret) {
2403 ath10k_warn("failed to wake target: %d\n", ret);
2404 return ret;
2405 }
2406
2407 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
2408 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
2409 ath10k_pci_sleep(ar);
2410
2411 return 0;
2412 }
2413
2414 static int ath10k_pci_deinit_irq_legacy(struct ath10k *ar)
2415 {
2416 int ret;
2417
2418 ret = ath10k_pci_wake(ar);
2419 if (ret) {
2420 ath10k_warn("failed to wake target: %d\n", ret);
2421 return ret;
2422 }
2423
2424 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
2425 0);
2426 ath10k_pci_sleep(ar);
2427
2428 return 0;
2429 }
2430
2431 static int ath10k_pci_deinit_irq(struct ath10k *ar)
2432 {
2433 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2434
2435 switch (ar_pci->num_msi_intrs) {
2436 case 0:
2437 return ath10k_pci_deinit_irq_legacy(ar);
2438 case 1:
2439 /* fall-through */
2440 case MSI_NUM_REQUEST:
2441 pci_disable_msi(ar_pci->pdev);
2442 return 0;
2443 default:
2444 pci_disable_msi(ar_pci->pdev);
2445 }
2446
2447 ath10k_warn("unknown irq configuration upon deinit\n");
2448 return -EINVAL;
2449 }
2450
2451 static int ath10k_pci_wait_for_target_init(struct ath10k *ar)
2452 {
2453 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2454 unsigned long timeout;
2455 int ret;
2456 u32 val;
2457
2458 ath10k_dbg(ATH10K_DBG_BOOT, "boot waiting target to initialise\n");
2459
2460 ret = ath10k_pci_wake(ar);
2461 if (ret) {
2462 ath10k_err("failed to wake up target for init: %d\n", ret);
2463 return ret;
2464 }
2465
2466 timeout = jiffies + msecs_to_jiffies(ATH10K_PCI_TARGET_WAIT);
2467
2468 do {
2469 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
2470
2471 ath10k_dbg(ATH10K_DBG_BOOT, "boot target indicator %x\n", val);
2472
2473 /* target should never return this */
2474 if (val == 0xffffffff)
2475 continue;
2476
2477 /* the device has crashed so don't bother trying anymore */
2478 if (val & FW_IND_EVENT_PENDING)
2479 break;
2480
2481 if (val & FW_IND_INITIALIZED)
2482 break;
2483
2484 if (ar_pci->num_msi_intrs == 0)
2485 /* Fix potential race by repeating CORE_BASE writes */
2486 ath10k_pci_soc_write32(ar, PCIE_INTR_ENABLE_ADDRESS,
2487 PCIE_INTR_FIRMWARE_MASK |
2488 PCIE_INTR_CE_MASK_ALL);
2489
2490 mdelay(10);
2491 } while (time_before(jiffies, timeout));
2492
2493 if (val == 0xffffffff) {
2494 ath10k_err("failed to read device register, device is gone\n");
2495 ret = -EIO;
2496 goto out;
2497 }
2498
2499 if (val & FW_IND_EVENT_PENDING) {
2500 ath10k_warn("device has crashed during init\n");
2501 ret = -ECOMM;
2502 goto out;
2503 }
2504
2505 if (!(val & FW_IND_INITIALIZED)) {
2506 ath10k_err("failed to receive initialized event from target: %08x\n",
2507 val);
2508 ret = -ETIMEDOUT;
2509 goto out;
2510 }
2511
2512 ath10k_dbg(ATH10K_DBG_BOOT, "boot target initialised\n");
2513
2514 out:
2515 ath10k_pci_sleep(ar);
2516 return ret;
2517 }
2518
2519 static int ath10k_pci_cold_reset(struct ath10k *ar)
2520 {
2521 int i, ret;
2522 u32 val;
2523
2524 ath10k_dbg(ATH10K_DBG_BOOT, "boot cold reset\n");
2525
2526 ret = ath10k_do_pci_wake(ar);
2527 if (ret) {
2528 ath10k_err("failed to wake up target: %d\n",
2529 ret);
2530 return ret;
2531 }
2532
2533 /* Put Target, including PCIe, into RESET. */
2534 val = ath10k_pci_reg_read32(ar, SOC_GLOBAL_RESET_ADDRESS);
2535 val |= 1;
2536 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val);
2537
2538 for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) {
2539 if (ath10k_pci_reg_read32(ar, RTC_STATE_ADDRESS) &
2540 RTC_STATE_COLD_RESET_MASK)
2541 break;
2542 msleep(1);
2543 }
2544
2545 /* Pull Target, including PCIe, out of RESET. */
2546 val &= ~1;
2547 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val);
2548
2549 for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) {
2550 if (!(ath10k_pci_reg_read32(ar, RTC_STATE_ADDRESS) &
2551 RTC_STATE_COLD_RESET_MASK))
2552 break;
2553 msleep(1);
2554 }
2555
2556 ath10k_do_pci_sleep(ar);
2557
2558 ath10k_dbg(ATH10K_DBG_BOOT, "boot cold reset complete\n");
2559
2560 return 0;
2561 }
2562
2563 static void ath10k_pci_dump_features(struct ath10k_pci *ar_pci)
2564 {
2565 int i;
2566
2567 for (i = 0; i < ATH10K_PCI_FEATURE_COUNT; i++) {
2568 if (!test_bit(i, ar_pci->features))
2569 continue;
2570
2571 switch (i) {
2572 case ATH10K_PCI_FEATURE_MSI_X:
2573 ath10k_dbg(ATH10K_DBG_BOOT, "device supports MSI-X\n");
2574 break;
2575 case ATH10K_PCI_FEATURE_SOC_POWER_SAVE:
2576 ath10k_dbg(ATH10K_DBG_BOOT, "QCA98XX SoC power save enabled\n");
2577 break;
2578 }
2579 }
2580 }
2581
2582 static int ath10k_pci_probe(struct pci_dev *pdev,
2583 const struct pci_device_id *pci_dev)
2584 {
2585 void __iomem *mem;
2586 int ret = 0;
2587 struct ath10k *ar;
2588 struct ath10k_pci *ar_pci;
2589 u32 lcr_val, chip_id;
2590
2591 ath10k_dbg(ATH10K_DBG_PCI, "pci probe\n");
2592
2593 ar_pci = kzalloc(sizeof(*ar_pci), GFP_KERNEL);
2594 if (ar_pci == NULL)
2595 return -ENOMEM;
2596
2597 ar_pci->pdev = pdev;
2598 ar_pci->dev = &pdev->dev;
2599
2600 switch (pci_dev->device) {
2601 case QCA988X_2_0_DEVICE_ID:
2602 set_bit(ATH10K_PCI_FEATURE_MSI_X, ar_pci->features);
2603 break;
2604 default:
2605 ret = -ENODEV;
2606 ath10k_err("Unknown device ID: %d\n", pci_dev->device);
2607 goto err_ar_pci;
2608 }
2609
2610 if (ath10k_pci_target_ps)
2611 set_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE, ar_pci->features);
2612
2613 ath10k_pci_dump_features(ar_pci);
2614
2615 ar = ath10k_core_create(ar_pci, ar_pci->dev, &ath10k_pci_hif_ops);
2616 if (!ar) {
2617 ath10k_err("failed to create driver core\n");
2618 ret = -EINVAL;
2619 goto err_ar_pci;
2620 }
2621
2622 ar_pci->ar = ar;
2623 atomic_set(&ar_pci->keep_awake_count, 0);
2624
2625 pci_set_drvdata(pdev, ar);
2626
2627 /*
2628 * Without any knowledge of the Host, the Target may have been reset or
2629 * power cycled and its Config Space may no longer reflect the PCI
2630 * address space that was assigned earlier by the PCI infrastructure.
2631 * Refresh it now.
2632 */
2633 ret = pci_assign_resource(pdev, BAR_NUM);
2634 if (ret) {
2635 ath10k_err("failed to assign PCI space: %d\n", ret);
2636 goto err_ar;
2637 }
2638
2639 ret = pci_enable_device(pdev);
2640 if (ret) {
2641 ath10k_err("failed to enable PCI device: %d\n", ret);
2642 goto err_ar;
2643 }
2644
2645 /* Request MMIO resources */
2646 ret = pci_request_region(pdev, BAR_NUM, "ath");
2647 if (ret) {
2648 ath10k_err("failed to request MMIO region: %d\n", ret);
2649 goto err_device;
2650 }
2651
2652 /*
2653 * Target structures have a limit of 32 bit DMA pointers.
2654 * DMA pointers can be wider than 32 bits by default on some systems.
2655 */
2656 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2657 if (ret) {
2658 ath10k_err("failed to set DMA mask to 32-bit: %d\n", ret);
2659 goto err_region;
2660 }
2661
2662 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
2663 if (ret) {
2664 ath10k_err("failed to set consistent DMA mask to 32-bit\n");
2665 goto err_region;
2666 }
2667
2668 /* Set bus master bit in PCI_COMMAND to enable DMA */
2669 pci_set_master(pdev);
2670
2671 /*
2672 * Temporary FIX: disable ASPM
2673 * Will be removed after the OTP is programmed
2674 */
2675 pci_read_config_dword(pdev, 0x80, &lcr_val);
2676 pci_write_config_dword(pdev, 0x80, (lcr_val & 0xffffff00));
2677
2678 /* Arrange for access to Target SoC registers. */
2679 mem = pci_iomap(pdev, BAR_NUM, 0);
2680 if (!mem) {
2681 ath10k_err("failed to perform IOMAP for BAR%d\n", BAR_NUM);
2682 ret = -EIO;
2683 goto err_master;
2684 }
2685
2686 ar_pci->mem = mem;
2687
2688 spin_lock_init(&ar_pci->ce_lock);
2689
2690 ret = ath10k_do_pci_wake(ar);
2691 if (ret) {
2692 ath10k_err("Failed to get chip id: %d\n", ret);
2693 goto err_iomap;
2694 }
2695
2696 chip_id = ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS);
2697
2698 ath10k_do_pci_sleep(ar);
2699
2700 ret = ath10k_pci_alloc_ce(ar);
2701 if (ret) {
2702 ath10k_err("failed to allocate copy engine pipes: %d\n", ret);
2703 goto err_iomap;
2704 }
2705
2706 ath10k_dbg(ATH10K_DBG_BOOT, "boot pci_mem 0x%p\n", ar_pci->mem);
2707
2708 ret = ath10k_core_register(ar, chip_id);
2709 if (ret) {
2710 ath10k_err("failed to register driver core: %d\n", ret);
2711 goto err_free_ce;
2712 }
2713
2714 return 0;
2715
2716 err_free_ce:
2717 ath10k_pci_free_ce(ar);
2718 err_iomap:
2719 pci_iounmap(pdev, mem);
2720 err_master:
2721 pci_clear_master(pdev);
2722 err_region:
2723 pci_release_region(pdev, BAR_NUM);
2724 err_device:
2725 pci_disable_device(pdev);
2726 err_ar:
2727 ath10k_core_destroy(ar);
2728 err_ar_pci:
2729 /* call HIF PCI free here */
2730 kfree(ar_pci);
2731
2732 return ret;
2733 }
2734
2735 static void ath10k_pci_remove(struct pci_dev *pdev)
2736 {
2737 struct ath10k *ar = pci_get_drvdata(pdev);
2738 struct ath10k_pci *ar_pci;
2739
2740 ath10k_dbg(ATH10K_DBG_PCI, "pci remove\n");
2741
2742 if (!ar)
2743 return;
2744
2745 ar_pci = ath10k_pci_priv(ar);
2746
2747 if (!ar_pci)
2748 return;
2749
2750 tasklet_kill(&ar_pci->msi_fw_err);
2751
2752 ath10k_core_unregister(ar);
2753 ath10k_pci_free_ce(ar);
2754
2755 pci_iounmap(pdev, ar_pci->mem);
2756 pci_release_region(pdev, BAR_NUM);
2757 pci_clear_master(pdev);
2758 pci_disable_device(pdev);
2759
2760 ath10k_core_destroy(ar);
2761 kfree(ar_pci);
2762 }
2763
2764 MODULE_DEVICE_TABLE(pci, ath10k_pci_id_table);
2765
2766 static struct pci_driver ath10k_pci_driver = {
2767 .name = "ath10k_pci",
2768 .id_table = ath10k_pci_id_table,
2769 .probe = ath10k_pci_probe,
2770 .remove = ath10k_pci_remove,
2771 };
2772
2773 static int __init ath10k_pci_init(void)
2774 {
2775 int ret;
2776
2777 ret = pci_register_driver(&ath10k_pci_driver);
2778 if (ret)
2779 ath10k_err("failed to register PCI driver: %d\n", ret);
2780
2781 return ret;
2782 }
2783 module_init(ath10k_pci_init);
2784
2785 static void __exit ath10k_pci_exit(void)
2786 {
2787 pci_unregister_driver(&ath10k_pci_driver);
2788 }
2789
2790 module_exit(ath10k_pci_exit);
2791
2792 MODULE_AUTHOR("Qualcomm Atheros");
2793 MODULE_DESCRIPTION("Driver support for Atheros QCA988X PCIe devices");
2794 MODULE_LICENSE("Dual BSD/GPL");
2795 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_FW_2_FILE);
2796 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_BOARD_DATA_FILE);
Linux kernel - Deliverables
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