2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <linux/pci.h>
19 #include <linux/module.h>
20 #include <linux/interrupt.h>
21 #include <linux/spinlock.h>
22 #include <linux/bitops.h>
27 #include "targaddrs.h"
36 enum ath10k_pci_irq_mode
{
37 ATH10K_PCI_IRQ_AUTO
= 0,
38 ATH10K_PCI_IRQ_LEGACY
= 1,
39 ATH10K_PCI_IRQ_MSI
= 2,
42 enum ath10k_pci_reset_mode
{
43 ATH10K_PCI_RESET_AUTO
= 0,
44 ATH10K_PCI_RESET_WARM_ONLY
= 1,
47 static unsigned int ath10k_pci_irq_mode
= ATH10K_PCI_IRQ_AUTO
;
48 static unsigned int ath10k_pci_reset_mode
= ATH10K_PCI_RESET_AUTO
;
50 module_param_named(irq_mode
, ath10k_pci_irq_mode
, uint
, 0644);
51 MODULE_PARM_DESC(irq_mode
, "0: auto, 1: legacy, 2: msi (default: 0)");
53 module_param_named(reset_mode
, ath10k_pci_reset_mode
, uint
, 0644);
54 MODULE_PARM_DESC(reset_mode
, "0: auto, 1: warm only (default: 0)");
56 /* how long wait to wait for target to initialise, in ms */
57 #define ATH10K_PCI_TARGET_WAIT 3000
58 #define ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS 3
60 #define QCA988X_2_0_DEVICE_ID (0x003c)
61 #define QCA6174_2_1_DEVICE_ID (0x003e)
63 static const struct pci_device_id ath10k_pci_id_table
[] = {
64 { PCI_VDEVICE(ATHEROS
, QCA988X_2_0_DEVICE_ID
) }, /* PCI-E QCA988X V2 */
65 { PCI_VDEVICE(ATHEROS
, QCA6174_2_1_DEVICE_ID
) }, /* PCI-E QCA6174 V2.1 */
69 static const struct ath10k_pci_supp_chip ath10k_pci_supp_chips
[] = {
70 /* QCA988X pre 2.0 chips are not supported because they need some nasty
71 * hacks. ath10k doesn't have them and these devices crash horribly
74 { QCA988X_2_0_DEVICE_ID
, QCA988X_HW_2_0_CHIP_ID_REV
},
75 { QCA6174_2_1_DEVICE_ID
, QCA6174_HW_2_1_CHIP_ID_REV
},
76 { QCA6174_2_1_DEVICE_ID
, QCA6174_HW_2_2_CHIP_ID_REV
},
77 { QCA6174_2_1_DEVICE_ID
, QCA6174_HW_3_0_CHIP_ID_REV
},
78 { QCA6174_2_1_DEVICE_ID
, QCA6174_HW_3_1_CHIP_ID_REV
},
79 { QCA6174_2_1_DEVICE_ID
, QCA6174_HW_3_2_CHIP_ID_REV
},
82 static void ath10k_pci_buffer_cleanup(struct ath10k
*ar
);
83 static int ath10k_pci_cold_reset(struct ath10k
*ar
);
84 static int ath10k_pci_warm_reset(struct ath10k
*ar
);
85 static int ath10k_pci_wait_for_target_init(struct ath10k
*ar
);
86 static int ath10k_pci_init_irq(struct ath10k
*ar
);
87 static int ath10k_pci_deinit_irq(struct ath10k
*ar
);
88 static int ath10k_pci_request_irq(struct ath10k
*ar
);
89 static void ath10k_pci_free_irq(struct ath10k
*ar
);
90 static int ath10k_pci_bmi_wait(struct ath10k_ce_pipe
*tx_pipe
,
91 struct ath10k_ce_pipe
*rx_pipe
,
92 struct bmi_xfer
*xfer
);
94 static const struct ce_attr host_ce_config_wlan
[] = {
95 /* CE0: host->target HTC control and raw streams */
97 .flags
= CE_ATTR_FLAGS
,
103 /* CE1: target->host HTT + HTC control */
105 .flags
= CE_ATTR_FLAGS
,
108 .dest_nentries
= 512,
111 /* CE2: target->host WMI */
113 .flags
= CE_ATTR_FLAGS
,
116 .dest_nentries
= 128,
119 /* CE3: host->target WMI */
121 .flags
= CE_ATTR_FLAGS
,
127 /* CE4: host->target HTT */
129 .flags
= CE_ATTR_FLAGS
| CE_ATTR_DIS_INTR
,
130 .src_nentries
= CE_HTT_H2T_MSG_SRC_NENTRIES
,
137 .flags
= CE_ATTR_FLAGS
,
143 /* CE6: target autonomous hif_memcpy */
145 .flags
= CE_ATTR_FLAGS
,
151 /* CE7: ce_diag, the Diagnostic Window */
153 .flags
= CE_ATTR_FLAGS
,
155 .src_sz_max
= DIAG_TRANSFER_LIMIT
,
160 /* Target firmware's Copy Engine configuration. */
161 static const struct ce_pipe_config target_ce_config_wlan
[] = {
162 /* CE0: host->target HTC control and raw streams */
164 .pipenum
= __cpu_to_le32(0),
165 .pipedir
= __cpu_to_le32(PIPEDIR_OUT
),
166 .nentries
= __cpu_to_le32(32),
167 .nbytes_max
= __cpu_to_le32(256),
168 .flags
= __cpu_to_le32(CE_ATTR_FLAGS
),
169 .reserved
= __cpu_to_le32(0),
172 /* CE1: target->host HTT + HTC control */
174 .pipenum
= __cpu_to_le32(1),
175 .pipedir
= __cpu_to_le32(PIPEDIR_IN
),
176 .nentries
= __cpu_to_le32(32),
177 .nbytes_max
= __cpu_to_le32(2048),
178 .flags
= __cpu_to_le32(CE_ATTR_FLAGS
),
179 .reserved
= __cpu_to_le32(0),
182 /* CE2: target->host WMI */
184 .pipenum
= __cpu_to_le32(2),
185 .pipedir
= __cpu_to_le32(PIPEDIR_IN
),
186 .nentries
= __cpu_to_le32(64),
187 .nbytes_max
= __cpu_to_le32(2048),
188 .flags
= __cpu_to_le32(CE_ATTR_FLAGS
),
189 .reserved
= __cpu_to_le32(0),
192 /* CE3: host->target WMI */
194 .pipenum
= __cpu_to_le32(3),
195 .pipedir
= __cpu_to_le32(PIPEDIR_OUT
),
196 .nentries
= __cpu_to_le32(32),
197 .nbytes_max
= __cpu_to_le32(2048),
198 .flags
= __cpu_to_le32(CE_ATTR_FLAGS
),
199 .reserved
= __cpu_to_le32(0),
202 /* CE4: host->target HTT */
204 .pipenum
= __cpu_to_le32(4),
205 .pipedir
= __cpu_to_le32(PIPEDIR_OUT
),
206 .nentries
= __cpu_to_le32(256),
207 .nbytes_max
= __cpu_to_le32(256),
208 .flags
= __cpu_to_le32(CE_ATTR_FLAGS
),
209 .reserved
= __cpu_to_le32(0),
212 /* NB: 50% of src nentries, since tx has 2 frags */
216 .pipenum
= __cpu_to_le32(5),
217 .pipedir
= __cpu_to_le32(PIPEDIR_OUT
),
218 .nentries
= __cpu_to_le32(32),
219 .nbytes_max
= __cpu_to_le32(2048),
220 .flags
= __cpu_to_le32(CE_ATTR_FLAGS
),
221 .reserved
= __cpu_to_le32(0),
224 /* CE6: Reserved for target autonomous hif_memcpy */
226 .pipenum
= __cpu_to_le32(6),
227 .pipedir
= __cpu_to_le32(PIPEDIR_INOUT
),
228 .nentries
= __cpu_to_le32(32),
229 .nbytes_max
= __cpu_to_le32(4096),
230 .flags
= __cpu_to_le32(CE_ATTR_FLAGS
),
231 .reserved
= __cpu_to_le32(0),
234 /* CE7 used only by Host */
238 * Map from service/endpoint to Copy Engine.
239 * This table is derived from the CE_PCI TABLE, above.
240 * It is passed to the Target at startup for use by firmware.
242 static const struct service_to_pipe target_service_to_ce_map_wlan
[] = {
244 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO
),
245 __cpu_to_le32(PIPEDIR_OUT
), /* out = UL = host -> target */
249 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO
),
250 __cpu_to_le32(PIPEDIR_IN
), /* in = DL = target -> host */
254 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK
),
255 __cpu_to_le32(PIPEDIR_OUT
), /* out = UL = host -> target */
259 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK
),
260 __cpu_to_le32(PIPEDIR_IN
), /* in = DL = target -> host */
264 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE
),
265 __cpu_to_le32(PIPEDIR_OUT
), /* out = UL = host -> target */
269 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE
),
270 __cpu_to_le32(PIPEDIR_IN
), /* in = DL = target -> host */
274 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI
),
275 __cpu_to_le32(PIPEDIR_OUT
), /* out = UL = host -> target */
279 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI
),
280 __cpu_to_le32(PIPEDIR_IN
), /* in = DL = target -> host */
284 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL
),
285 __cpu_to_le32(PIPEDIR_OUT
), /* out = UL = host -> target */
289 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL
),
290 __cpu_to_le32(PIPEDIR_IN
), /* in = DL = target -> host */
294 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL
),
295 __cpu_to_le32(PIPEDIR_OUT
), /* out = UL = host -> target */
299 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL
),
300 __cpu_to_le32(PIPEDIR_IN
), /* in = DL = target -> host */
304 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS
),
305 __cpu_to_le32(PIPEDIR_OUT
), /* out = UL = host -> target */
309 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS
),
310 __cpu_to_le32(PIPEDIR_IN
), /* in = DL = target -> host */
314 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG
),
315 __cpu_to_le32(PIPEDIR_OUT
), /* out = UL = host -> target */
319 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG
),
320 __cpu_to_le32(PIPEDIR_IN
), /* in = DL = target -> host */
324 /* (Additions here) */
333 static bool ath10k_pci_irq_pending(struct ath10k
*ar
)
337 /* Check if the shared legacy irq is for us */
338 cause
= ath10k_pci_read32(ar
, SOC_CORE_BASE_ADDRESS
+
339 PCIE_INTR_CAUSE_ADDRESS
);
340 if (cause
& (PCIE_INTR_FIRMWARE_MASK
| PCIE_INTR_CE_MASK_ALL
))
346 static void ath10k_pci_disable_and_clear_legacy_irq(struct ath10k
*ar
)
348 /* IMPORTANT: INTR_CLR register has to be set after
349 * INTR_ENABLE is set to 0, otherwise interrupt can not be
351 ath10k_pci_write32(ar
, SOC_CORE_BASE_ADDRESS
+ PCIE_INTR_ENABLE_ADDRESS
,
353 ath10k_pci_write32(ar
, SOC_CORE_BASE_ADDRESS
+ PCIE_INTR_CLR_ADDRESS
,
354 PCIE_INTR_FIRMWARE_MASK
| PCIE_INTR_CE_MASK_ALL
);
356 /* IMPORTANT: this extra read transaction is required to
357 * flush the posted write buffer. */
358 (void)ath10k_pci_read32(ar
, SOC_CORE_BASE_ADDRESS
+
359 PCIE_INTR_ENABLE_ADDRESS
);
362 static void ath10k_pci_enable_legacy_irq(struct ath10k
*ar
)
364 ath10k_pci_write32(ar
, SOC_CORE_BASE_ADDRESS
+
365 PCIE_INTR_ENABLE_ADDRESS
,
366 PCIE_INTR_FIRMWARE_MASK
| PCIE_INTR_CE_MASK_ALL
);
368 /* IMPORTANT: this extra read transaction is required to
369 * flush the posted write buffer. */
370 (void)ath10k_pci_read32(ar
, SOC_CORE_BASE_ADDRESS
+
371 PCIE_INTR_ENABLE_ADDRESS
);
374 static inline const char *ath10k_pci_get_irq_method(struct ath10k
*ar
)
376 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
378 if (ar_pci
->num_msi_intrs
> 1)
381 if (ar_pci
->num_msi_intrs
== 1)
387 static int __ath10k_pci_rx_post_buf(struct ath10k_pci_pipe
*pipe
)
389 struct ath10k
*ar
= pipe
->hif_ce_state
;
390 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
391 struct ath10k_ce_pipe
*ce_pipe
= pipe
->ce_hdl
;
396 lockdep_assert_held(&ar_pci
->ce_lock
);
398 skb
= dev_alloc_skb(pipe
->buf_sz
);
402 WARN_ONCE((unsigned long)skb
->data
& 3, "unaligned skb");
404 paddr
= dma_map_single(ar
->dev
, skb
->data
,
405 skb
->len
+ skb_tailroom(skb
),
407 if (unlikely(dma_mapping_error(ar
->dev
, paddr
))) {
408 ath10k_warn(ar
, "failed to dma map pci rx buf\n");
409 dev_kfree_skb_any(skb
);
413 ATH10K_SKB_RXCB(skb
)->paddr
= paddr
;
415 ret
= __ath10k_ce_rx_post_buf(ce_pipe
, skb
, paddr
);
417 ath10k_warn(ar
, "failed to post pci rx buf: %d\n", ret
);
418 dma_unmap_single(ar
->dev
, paddr
, skb
->len
+ skb_tailroom(skb
),
420 dev_kfree_skb_any(skb
);
427 static void __ath10k_pci_rx_post_pipe(struct ath10k_pci_pipe
*pipe
)
429 struct ath10k
*ar
= pipe
->hif_ce_state
;
430 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
431 struct ath10k_ce_pipe
*ce_pipe
= pipe
->ce_hdl
;
434 lockdep_assert_held(&ar_pci
->ce_lock
);
436 if (pipe
->buf_sz
== 0)
439 if (!ce_pipe
->dest_ring
)
442 num
= __ath10k_ce_rx_num_free_bufs(ce_pipe
);
444 ret
= __ath10k_pci_rx_post_buf(pipe
);
446 ath10k_warn(ar
, "failed to post pci rx buf: %d\n", ret
);
447 mod_timer(&ar_pci
->rx_post_retry
, jiffies
+
448 ATH10K_PCI_RX_POST_RETRY_MS
);
454 static void ath10k_pci_rx_post_pipe(struct ath10k_pci_pipe
*pipe
)
456 struct ath10k
*ar
= pipe
->hif_ce_state
;
457 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
459 spin_lock_bh(&ar_pci
->ce_lock
);
460 __ath10k_pci_rx_post_pipe(pipe
);
461 spin_unlock_bh(&ar_pci
->ce_lock
);
464 static void ath10k_pci_rx_post(struct ath10k
*ar
)
466 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
469 spin_lock_bh(&ar_pci
->ce_lock
);
470 for (i
= 0; i
< CE_COUNT
; i
++)
471 __ath10k_pci_rx_post_pipe(&ar_pci
->pipe_info
[i
]);
472 spin_unlock_bh(&ar_pci
->ce_lock
);
475 static void ath10k_pci_rx_replenish_retry(unsigned long ptr
)
477 struct ath10k
*ar
= (void *)ptr
;
479 ath10k_pci_rx_post(ar
);
483 * Diagnostic read/write access is provided for startup/config/debug usage.
484 * Caller must guarantee proper alignment, when applicable, and single user
487 static int ath10k_pci_diag_read_mem(struct ath10k
*ar
, u32 address
, void *data
,
490 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
493 unsigned int completed_nbytes
, orig_nbytes
, remaining_bytes
;
496 struct ath10k_ce_pipe
*ce_diag
;
497 /* Host buffer address in CE space */
499 dma_addr_t ce_data_base
= 0;
500 void *data_buf
= NULL
;
503 spin_lock_bh(&ar_pci
->ce_lock
);
505 ce_diag
= ar_pci
->ce_diag
;
508 * Allocate a temporary bounce buffer to hold caller's data
509 * to be DMA'ed from Target. This guarantees
510 * 1) 4-byte alignment
511 * 2) Buffer in DMA-able space
513 orig_nbytes
= nbytes
;
514 data_buf
= (unsigned char *)dma_alloc_coherent(ar
->dev
,
523 memset(data_buf
, 0, orig_nbytes
);
525 remaining_bytes
= orig_nbytes
;
526 ce_data
= ce_data_base
;
527 while (remaining_bytes
) {
528 nbytes
= min_t(unsigned int, remaining_bytes
,
529 DIAG_TRANSFER_LIMIT
);
531 ret
= __ath10k_ce_rx_post_buf(ce_diag
, NULL
, ce_data
);
535 /* Request CE to send from Target(!) address to Host buffer */
537 * The address supplied by the caller is in the
538 * Target CPU virtual address space.
540 * In order to use this address with the diagnostic CE,
541 * convert it from Target CPU virtual address space
542 * to CE address space
544 address
= TARG_CPU_SPACE_TO_CE_SPACE(ar
, ar_pci
->mem
,
547 ret
= ath10k_ce_send_nolock(ce_diag
, NULL
, (u32
)address
, nbytes
, 0,
553 while (ath10k_ce_completed_send_next_nolock(ce_diag
, NULL
, &buf
,
557 if (i
++ > DIAG_ACCESS_CE_TIMEOUT_MS
) {
563 if (nbytes
!= completed_nbytes
) {
568 if (buf
!= (u32
)address
) {
574 while (ath10k_ce_completed_recv_next_nolock(ce_diag
, NULL
, &buf
,
579 if (i
++ > DIAG_ACCESS_CE_TIMEOUT_MS
) {
585 if (nbytes
!= completed_nbytes
) {
590 if (buf
!= ce_data
) {
595 remaining_bytes
-= nbytes
;
602 memcpy(data
, data_buf
, orig_nbytes
);
604 ath10k_warn(ar
, "failed to read diag value at 0x%x: %d\n",
608 dma_free_coherent(ar
->dev
, orig_nbytes
, data_buf
,
611 spin_unlock_bh(&ar_pci
->ce_lock
);
616 static int ath10k_pci_diag_read32(struct ath10k
*ar
, u32 address
, u32
*value
)
621 ret
= ath10k_pci_diag_read_mem(ar
, address
, &val
, sizeof(val
));
622 *value
= __le32_to_cpu(val
);
627 static int __ath10k_pci_diag_read_hi(struct ath10k
*ar
, void *dest
,
633 host_addr
= host_interest_item_address(src
);
635 ret
= ath10k_pci_diag_read32(ar
, host_addr
, &addr
);
637 ath10k_warn(ar
, "failed to get memcpy hi address for firmware address %d: %d\n",
642 ret
= ath10k_pci_diag_read_mem(ar
, addr
, dest
, len
);
644 ath10k_warn(ar
, "failed to memcpy firmware memory from %d (%d B): %d\n",
652 #define ath10k_pci_diag_read_hi(ar, dest, src, len) \
653 __ath10k_pci_diag_read_hi(ar, dest, HI_ITEM(src), len)
655 static int ath10k_pci_diag_write_mem(struct ath10k
*ar
, u32 address
,
656 const void *data
, int nbytes
)
658 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
661 unsigned int completed_nbytes
, orig_nbytes
, remaining_bytes
;
664 struct ath10k_ce_pipe
*ce_diag
;
665 void *data_buf
= NULL
;
666 u32 ce_data
; /* Host buffer address in CE space */
667 dma_addr_t ce_data_base
= 0;
670 spin_lock_bh(&ar_pci
->ce_lock
);
672 ce_diag
= ar_pci
->ce_diag
;
675 * Allocate a temporary bounce buffer to hold caller's data
676 * to be DMA'ed to Target. This guarantees
677 * 1) 4-byte alignment
678 * 2) Buffer in DMA-able space
680 orig_nbytes
= nbytes
;
681 data_buf
= (unsigned char *)dma_alloc_coherent(ar
->dev
,
690 /* Copy caller's data to allocated DMA buf */
691 memcpy(data_buf
, data
, orig_nbytes
);
694 * The address supplied by the caller is in the
695 * Target CPU virtual address space.
697 * In order to use this address with the diagnostic CE,
699 * Target CPU virtual address space
703 address
= TARG_CPU_SPACE_TO_CE_SPACE(ar
, ar_pci
->mem
, address
);
705 remaining_bytes
= orig_nbytes
;
706 ce_data
= ce_data_base
;
707 while (remaining_bytes
) {
708 /* FIXME: check cast */
709 nbytes
= min_t(int, remaining_bytes
, DIAG_TRANSFER_LIMIT
);
711 /* Set up to receive directly into Target(!) address */
712 ret
= __ath10k_ce_rx_post_buf(ce_diag
, NULL
, address
);
717 * Request CE to send caller-supplied data that
718 * was copied to bounce buffer to Target(!) address.
720 ret
= ath10k_ce_send_nolock(ce_diag
, NULL
, (u32
)ce_data
,
726 while (ath10k_ce_completed_send_next_nolock(ce_diag
, NULL
, &buf
,
731 if (i
++ > DIAG_ACCESS_CE_TIMEOUT_MS
) {
737 if (nbytes
!= completed_nbytes
) {
742 if (buf
!= ce_data
) {
748 while (ath10k_ce_completed_recv_next_nolock(ce_diag
, NULL
, &buf
,
753 if (i
++ > DIAG_ACCESS_CE_TIMEOUT_MS
) {
759 if (nbytes
!= completed_nbytes
) {
764 if (buf
!= address
) {
769 remaining_bytes
-= nbytes
;
776 dma_free_coherent(ar
->dev
, orig_nbytes
, data_buf
,
781 ath10k_warn(ar
, "failed to write diag value at 0x%x: %d\n",
784 spin_unlock_bh(&ar_pci
->ce_lock
);
789 static int ath10k_pci_diag_write32(struct ath10k
*ar
, u32 address
, u32 value
)
791 __le32 val
= __cpu_to_le32(value
);
793 return ath10k_pci_diag_write_mem(ar
, address
, &val
, sizeof(val
));
796 static bool ath10k_pci_is_awake(struct ath10k
*ar
)
798 u32 val
= ath10k_pci_reg_read32(ar
, RTC_STATE_ADDRESS
);
800 return RTC_STATE_V_GET(val
) == RTC_STATE_V_ON
;
803 static int ath10k_pci_wake_wait(struct ath10k
*ar
)
808 while (tot_delay
< PCIE_WAKE_TIMEOUT
) {
809 if (ath10k_pci_is_awake(ar
))
813 tot_delay
+= curr_delay
;
822 /* The rule is host is forbidden from accessing device registers while it's
823 * asleep. Currently ath10k_pci_wake() and ath10k_pci_sleep() calls aren't
824 * balanced and the device is kept awake all the time. This is intended for a
825 * simpler solution for the following problems:
827 * * device can enter sleep during s2ram without the host knowing,
829 * * irq handlers access registers which is a problem if other device asserts
830 * a shared irq line when ath10k is between hif_power_down() and
833 * FIXME: If power consumption is a concern (and there are *real* gains) then a
834 * refcounted wake/sleep needs to be implemented.
837 static int ath10k_pci_wake(struct ath10k
*ar
)
839 ath10k_pci_reg_write32(ar
, PCIE_SOC_WAKE_ADDRESS
,
840 PCIE_SOC_WAKE_V_MASK
);
841 return ath10k_pci_wake_wait(ar
);
844 static void ath10k_pci_sleep(struct ath10k
*ar
)
846 ath10k_pci_reg_write32(ar
, PCIE_SOC_WAKE_ADDRESS
,
847 PCIE_SOC_WAKE_RESET
);
850 /* Called by lower (CE) layer when a send to Target completes. */
851 static void ath10k_pci_ce_send_done(struct ath10k_ce_pipe
*ce_state
)
853 struct ath10k
*ar
= ce_state
->ar
;
854 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
855 struct ath10k_hif_cb
*cb
= &ar_pci
->msg_callbacks_current
;
856 struct sk_buff_head list
;
860 unsigned int transfer_id
;
862 __skb_queue_head_init(&list
);
863 while (ath10k_ce_completed_send_next(ce_state
, (void **)&skb
, &ce_data
,
864 &nbytes
, &transfer_id
) == 0) {
865 /* no need to call tx completion for NULL pointers */
869 __skb_queue_tail(&list
, skb
);
872 while ((skb
= __skb_dequeue(&list
)))
873 cb
->tx_completion(ar
, skb
);
876 /* Called by lower (CE) layer when data is received from the Target. */
877 static void ath10k_pci_ce_recv_data(struct ath10k_ce_pipe
*ce_state
)
879 struct ath10k
*ar
= ce_state
->ar
;
880 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
881 struct ath10k_pci_pipe
*pipe_info
= &ar_pci
->pipe_info
[ce_state
->id
];
882 struct ath10k_hif_cb
*cb
= &ar_pci
->msg_callbacks_current
;
884 struct sk_buff_head list
;
885 void *transfer_context
;
887 unsigned int nbytes
, max_nbytes
;
888 unsigned int transfer_id
;
891 __skb_queue_head_init(&list
);
892 while (ath10k_ce_completed_recv_next(ce_state
, &transfer_context
,
893 &ce_data
, &nbytes
, &transfer_id
,
895 skb
= transfer_context
;
896 max_nbytes
= skb
->len
+ skb_tailroom(skb
);
897 dma_unmap_single(ar
->dev
, ATH10K_SKB_RXCB(skb
)->paddr
,
898 max_nbytes
, DMA_FROM_DEVICE
);
900 if (unlikely(max_nbytes
< nbytes
)) {
901 ath10k_warn(ar
, "rxed more than expected (nbytes %d, max %d)",
903 dev_kfree_skb_any(skb
);
907 skb_put(skb
, nbytes
);
908 __skb_queue_tail(&list
, skb
);
911 while ((skb
= __skb_dequeue(&list
))) {
912 ath10k_dbg(ar
, ATH10K_DBG_PCI
, "pci rx ce pipe %d len %d\n",
913 ce_state
->id
, skb
->len
);
914 ath10k_dbg_dump(ar
, ATH10K_DBG_PCI_DUMP
, NULL
, "pci rx: ",
915 skb
->data
, skb
->len
);
917 cb
->rx_completion(ar
, skb
);
920 ath10k_pci_rx_post_pipe(pipe_info
);
923 static int ath10k_pci_hif_tx_sg(struct ath10k
*ar
, u8 pipe_id
,
924 struct ath10k_hif_sg_item
*items
, int n_items
)
926 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
927 struct ath10k_pci_pipe
*pci_pipe
= &ar_pci
->pipe_info
[pipe_id
];
928 struct ath10k_ce_pipe
*ce_pipe
= pci_pipe
->ce_hdl
;
929 struct ath10k_ce_ring
*src_ring
= ce_pipe
->src_ring
;
930 unsigned int nentries_mask
;
931 unsigned int sw_index
;
932 unsigned int write_index
;
935 spin_lock_bh(&ar_pci
->ce_lock
);
937 nentries_mask
= src_ring
->nentries_mask
;
938 sw_index
= src_ring
->sw_index
;
939 write_index
= src_ring
->write_index
;
941 if (unlikely(CE_RING_DELTA(nentries_mask
,
942 write_index
, sw_index
- 1) < n_items
)) {
947 for (i
= 0; i
< n_items
- 1; i
++) {
948 ath10k_dbg(ar
, ATH10K_DBG_PCI
,
949 "pci tx item %d paddr 0x%08x len %d n_items %d\n",
950 i
, items
[i
].paddr
, items
[i
].len
, n_items
);
951 ath10k_dbg_dump(ar
, ATH10K_DBG_PCI_DUMP
, NULL
, "pci tx data: ",
952 items
[i
].vaddr
, items
[i
].len
);
954 err
= ath10k_ce_send_nolock(ce_pipe
,
955 items
[i
].transfer_context
,
958 items
[i
].transfer_id
,
959 CE_SEND_FLAG_GATHER
);
964 /* `i` is equal to `n_items -1` after for() */
966 ath10k_dbg(ar
, ATH10K_DBG_PCI
,
967 "pci tx item %d paddr 0x%08x len %d n_items %d\n",
968 i
, items
[i
].paddr
, items
[i
].len
, n_items
);
969 ath10k_dbg_dump(ar
, ATH10K_DBG_PCI_DUMP
, NULL
, "pci tx data: ",
970 items
[i
].vaddr
, items
[i
].len
);
972 err
= ath10k_ce_send_nolock(ce_pipe
,
973 items
[i
].transfer_context
,
976 items
[i
].transfer_id
,
981 spin_unlock_bh(&ar_pci
->ce_lock
);
986 __ath10k_ce_send_revert(ce_pipe
);
988 spin_unlock_bh(&ar_pci
->ce_lock
);
992 static int ath10k_pci_hif_diag_read(struct ath10k
*ar
, u32 address
, void *buf
,
995 return ath10k_pci_diag_read_mem(ar
, address
, buf
, buf_len
);
998 static u16
ath10k_pci_hif_get_free_queue_number(struct ath10k
*ar
, u8 pipe
)
1000 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
1002 ath10k_dbg(ar
, ATH10K_DBG_PCI
, "pci hif get free queue number\n");
1004 return ath10k_ce_num_free_src_entries(ar_pci
->pipe_info
[pipe
].ce_hdl
);
1007 static void ath10k_pci_dump_registers(struct ath10k
*ar
,
1008 struct ath10k_fw_crash_data
*crash_data
)
1010 __le32 reg_dump_values
[REG_DUMP_COUNT_QCA988X
] = {};
1013 lockdep_assert_held(&ar
->data_lock
);
1015 ret
= ath10k_pci_diag_read_hi(ar
, ®_dump_values
[0],
1017 REG_DUMP_COUNT_QCA988X
* sizeof(__le32
));
1019 ath10k_err(ar
, "failed to read firmware dump area: %d\n", ret
);
1023 BUILD_BUG_ON(REG_DUMP_COUNT_QCA988X
% 4);
1025 ath10k_err(ar
, "firmware register dump:\n");
1026 for (i
= 0; i
< REG_DUMP_COUNT_QCA988X
; i
+= 4)
1027 ath10k_err(ar
, "[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X\n",
1029 __le32_to_cpu(reg_dump_values
[i
]),
1030 __le32_to_cpu(reg_dump_values
[i
+ 1]),
1031 __le32_to_cpu(reg_dump_values
[i
+ 2]),
1032 __le32_to_cpu(reg_dump_values
[i
+ 3]));
1037 for (i
= 0; i
< REG_DUMP_COUNT_QCA988X
; i
++)
1038 crash_data
->registers
[i
] = reg_dump_values
[i
];
1041 static void ath10k_pci_fw_crashed_dump(struct ath10k
*ar
)
1043 struct ath10k_fw_crash_data
*crash_data
;
1046 spin_lock_bh(&ar
->data_lock
);
1048 ar
->stats
.fw_crash_counter
++;
1050 crash_data
= ath10k_debug_get_new_fw_crash_data(ar
);
1053 scnprintf(uuid
, sizeof(uuid
), "%pUl", &crash_data
->uuid
);
1055 scnprintf(uuid
, sizeof(uuid
), "n/a");
1057 ath10k_err(ar
, "firmware crashed! (uuid %s)\n", uuid
);
1058 ath10k_print_driver_info(ar
);
1059 ath10k_pci_dump_registers(ar
, crash_data
);
1061 spin_unlock_bh(&ar
->data_lock
);
1063 queue_work(ar
->workqueue
, &ar
->restart_work
);
1066 static void ath10k_pci_hif_send_complete_check(struct ath10k
*ar
, u8 pipe
,
1069 ath10k_dbg(ar
, ATH10K_DBG_PCI
, "pci hif send complete check\n");
1074 * Decide whether to actually poll for completions, or just
1075 * wait for a later chance.
1076 * If there seem to be plenty of resources left, then just wait
1077 * since checking involves reading a CE register, which is a
1078 * relatively expensive operation.
1080 resources
= ath10k_pci_hif_get_free_queue_number(ar
, pipe
);
1083 * If at least 50% of the total resources are still available,
1084 * don't bother checking again yet.
1086 if (resources
> (host_ce_config_wlan
[pipe
].src_nentries
>> 1))
1089 ath10k_ce_per_engine_service(ar
, pipe
);
1092 static void ath10k_pci_hif_set_callbacks(struct ath10k
*ar
,
1093 struct ath10k_hif_cb
*callbacks
)
1095 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
1097 ath10k_dbg(ar
, ATH10K_DBG_PCI
, "pci hif set callbacks\n");
1099 memcpy(&ar_pci
->msg_callbacks_current
, callbacks
,
1100 sizeof(ar_pci
->msg_callbacks_current
));
1103 static void ath10k_pci_kill_tasklet(struct ath10k
*ar
)
1105 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
1108 tasklet_kill(&ar_pci
->intr_tq
);
1109 tasklet_kill(&ar_pci
->msi_fw_err
);
1111 for (i
= 0; i
< CE_COUNT
; i
++)
1112 tasklet_kill(&ar_pci
->pipe_info
[i
].intr
);
1114 del_timer_sync(&ar_pci
->rx_post_retry
);
1117 static int ath10k_pci_hif_map_service_to_pipe(struct ath10k
*ar
,
1118 u16 service_id
, u8
*ul_pipe
,
1119 u8
*dl_pipe
, int *ul_is_polled
,
1122 const struct service_to_pipe
*entry
;
1123 bool ul_set
= false, dl_set
= false;
1126 ath10k_dbg(ar
, ATH10K_DBG_PCI
, "pci hif map service\n");
1128 /* polling for received messages not supported */
1131 for (i
= 0; i
< ARRAY_SIZE(target_service_to_ce_map_wlan
); i
++) {
1132 entry
= &target_service_to_ce_map_wlan
[i
];
1134 if (__le32_to_cpu(entry
->service_id
) != service_id
)
1137 switch (__le32_to_cpu(entry
->pipedir
)) {
1142 *dl_pipe
= __le32_to_cpu(entry
->pipenum
);
1147 *ul_pipe
= __le32_to_cpu(entry
->pipenum
);
1153 *dl_pipe
= __le32_to_cpu(entry
->pipenum
);
1154 *ul_pipe
= __le32_to_cpu(entry
->pipenum
);
1161 if (WARN_ON(!ul_set
|| !dl_set
))
1165 (host_ce_config_wlan
[*ul_pipe
].flags
& CE_ATTR_DIS_INTR
) != 0;
1170 static void ath10k_pci_hif_get_default_pipe(struct ath10k
*ar
,
1171 u8
*ul_pipe
, u8
*dl_pipe
)
1173 int ul_is_polled
, dl_is_polled
;
1175 ath10k_dbg(ar
, ATH10K_DBG_PCI
, "pci hif get default pipe\n");
1177 (void)ath10k_pci_hif_map_service_to_pipe(ar
,
1178 ATH10K_HTC_SVC_ID_RSVD_CTRL
,
1185 static void ath10k_pci_irq_msi_fw_mask(struct ath10k
*ar
)
1189 val
= ath10k_pci_read32(ar
, SOC_CORE_BASE_ADDRESS
+ CORE_CTRL_ADDRESS
);
1190 val
&= ~CORE_CTRL_PCIE_REG_31_MASK
;
1192 ath10k_pci_write32(ar
, SOC_CORE_BASE_ADDRESS
+ CORE_CTRL_ADDRESS
, val
);
1195 static void ath10k_pci_irq_msi_fw_unmask(struct ath10k
*ar
)
1199 val
= ath10k_pci_read32(ar
, SOC_CORE_BASE_ADDRESS
+ CORE_CTRL_ADDRESS
);
1200 val
|= CORE_CTRL_PCIE_REG_31_MASK
;
1202 ath10k_pci_write32(ar
, SOC_CORE_BASE_ADDRESS
+ CORE_CTRL_ADDRESS
, val
);
1205 static void ath10k_pci_irq_disable(struct ath10k
*ar
)
1207 ath10k_ce_disable_interrupts(ar
);
1208 ath10k_pci_disable_and_clear_legacy_irq(ar
);
1209 ath10k_pci_irq_msi_fw_mask(ar
);
1212 static void ath10k_pci_irq_sync(struct ath10k
*ar
)
1214 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
1217 for (i
= 0; i
< max(1, ar_pci
->num_msi_intrs
); i
++)
1218 synchronize_irq(ar_pci
->pdev
->irq
+ i
);
1221 static void ath10k_pci_irq_enable(struct ath10k
*ar
)
1223 ath10k_ce_enable_interrupts(ar
);
1224 ath10k_pci_enable_legacy_irq(ar
);
1225 ath10k_pci_irq_msi_fw_unmask(ar
);
1228 static int ath10k_pci_hif_start(struct ath10k
*ar
)
1230 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot hif start\n");
1232 ath10k_pci_irq_enable(ar
);
1233 ath10k_pci_rx_post(ar
);
1238 static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe
*pci_pipe
)
1241 struct ath10k_ce_pipe
*ce_pipe
;
1242 struct ath10k_ce_ring
*ce_ring
;
1243 struct sk_buff
*skb
;
1246 ar
= pci_pipe
->hif_ce_state
;
1247 ce_pipe
= pci_pipe
->ce_hdl
;
1248 ce_ring
= ce_pipe
->dest_ring
;
1253 if (!pci_pipe
->buf_sz
)
1256 for (i
= 0; i
< ce_ring
->nentries
; i
++) {
1257 skb
= ce_ring
->per_transfer_context
[i
];
1261 ce_ring
->per_transfer_context
[i
] = NULL
;
1263 dma_unmap_single(ar
->dev
, ATH10K_SKB_RXCB(skb
)->paddr
,
1264 skb
->len
+ skb_tailroom(skb
),
1266 dev_kfree_skb_any(skb
);
1270 static void ath10k_pci_tx_pipe_cleanup(struct ath10k_pci_pipe
*pci_pipe
)
1273 struct ath10k_pci
*ar_pci
;
1274 struct ath10k_ce_pipe
*ce_pipe
;
1275 struct ath10k_ce_ring
*ce_ring
;
1276 struct ce_desc
*ce_desc
;
1277 struct sk_buff
*skb
;
1281 ar
= pci_pipe
->hif_ce_state
;
1282 ar_pci
= ath10k_pci_priv(ar
);
1283 ce_pipe
= pci_pipe
->ce_hdl
;
1284 ce_ring
= ce_pipe
->src_ring
;
1289 if (!pci_pipe
->buf_sz
)
1292 ce_desc
= ce_ring
->shadow_base
;
1293 if (WARN_ON(!ce_desc
))
1296 for (i
= 0; i
< ce_ring
->nentries
; i
++) {
1297 skb
= ce_ring
->per_transfer_context
[i
];
1301 ce_ring
->per_transfer_context
[i
] = NULL
;
1302 id
= MS(__le16_to_cpu(ce_desc
[i
].flags
),
1303 CE_DESC_FLAGS_META_DATA
);
1305 ar_pci
->msg_callbacks_current
.tx_completion(ar
, skb
);
1310 * Cleanup residual buffers for device shutdown:
1311 * buffers that were enqueued for receive
1312 * buffers that were to be sent
1313 * Note: Buffers that had completed but which were
1314 * not yet processed are on a completion queue. They
1315 * are handled when the completion thread shuts down.
1317 static void ath10k_pci_buffer_cleanup(struct ath10k
*ar
)
1319 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
1322 for (pipe_num
= 0; pipe_num
< CE_COUNT
; pipe_num
++) {
1323 struct ath10k_pci_pipe
*pipe_info
;
1325 pipe_info
= &ar_pci
->pipe_info
[pipe_num
];
1326 ath10k_pci_rx_pipe_cleanup(pipe_info
);
1327 ath10k_pci_tx_pipe_cleanup(pipe_info
);
1331 static void ath10k_pci_ce_deinit(struct ath10k
*ar
)
1335 for (i
= 0; i
< CE_COUNT
; i
++)
1336 ath10k_ce_deinit_pipe(ar
, i
);
1339 static void ath10k_pci_flush(struct ath10k
*ar
)
1341 ath10k_pci_kill_tasklet(ar
);
1342 ath10k_pci_buffer_cleanup(ar
);
1345 static void ath10k_pci_hif_stop(struct ath10k
*ar
)
1347 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot hif stop\n");
1349 /* Most likely the device has HTT Rx ring configured. The only way to
1350 * prevent the device from accessing (and possible corrupting) host
1351 * memory is to reset the chip now.
1353 * There's also no known way of masking MSI interrupts on the device.
1354 * For ranged MSI the CE-related interrupts can be masked. However
1355 * regardless how many MSI interrupts are assigned the first one
1356 * is always used for firmware indications (crashes) and cannot be
1357 * masked. To prevent the device from asserting the interrupt reset it
1358 * before proceeding with cleanup.
1360 ath10k_pci_warm_reset(ar
);
1362 ath10k_pci_irq_disable(ar
);
1363 ath10k_pci_irq_sync(ar
);
1364 ath10k_pci_flush(ar
);
1367 static int ath10k_pci_hif_exchange_bmi_msg(struct ath10k
*ar
,
1368 void *req
, u32 req_len
,
1369 void *resp
, u32
*resp_len
)
1371 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
1372 struct ath10k_pci_pipe
*pci_tx
= &ar_pci
->pipe_info
[BMI_CE_NUM_TO_TARG
];
1373 struct ath10k_pci_pipe
*pci_rx
= &ar_pci
->pipe_info
[BMI_CE_NUM_TO_HOST
];
1374 struct ath10k_ce_pipe
*ce_tx
= pci_tx
->ce_hdl
;
1375 struct ath10k_ce_pipe
*ce_rx
= pci_rx
->ce_hdl
;
1376 dma_addr_t req_paddr
= 0;
1377 dma_addr_t resp_paddr
= 0;
1378 struct bmi_xfer xfer
= {};
1379 void *treq
, *tresp
= NULL
;
1384 if (resp
&& !resp_len
)
1387 if (resp
&& resp_len
&& *resp_len
== 0)
1390 treq
= kmemdup(req
, req_len
, GFP_KERNEL
);
1394 req_paddr
= dma_map_single(ar
->dev
, treq
, req_len
, DMA_TO_DEVICE
);
1395 ret
= dma_mapping_error(ar
->dev
, req_paddr
);
1399 if (resp
&& resp_len
) {
1400 tresp
= kzalloc(*resp_len
, GFP_KERNEL
);
1406 resp_paddr
= dma_map_single(ar
->dev
, tresp
, *resp_len
,
1408 ret
= dma_mapping_error(ar
->dev
, resp_paddr
);
1412 xfer
.wait_for_resp
= true;
1415 ath10k_ce_rx_post_buf(ce_rx
, &xfer
, resp_paddr
);
1418 ret
= ath10k_ce_send(ce_tx
, &xfer
, req_paddr
, req_len
, -1, 0);
1422 ret
= ath10k_pci_bmi_wait(ce_tx
, ce_rx
, &xfer
);
1425 unsigned int unused_nbytes
;
1426 unsigned int unused_id
;
1428 ath10k_ce_cancel_send_next(ce_tx
, NULL
, &unused_buffer
,
1429 &unused_nbytes
, &unused_id
);
1431 /* non-zero means we did not time out */
1439 ath10k_ce_revoke_recv_next(ce_rx
, NULL
, &unused_buffer
);
1440 dma_unmap_single(ar
->dev
, resp_paddr
,
1441 *resp_len
, DMA_FROM_DEVICE
);
1444 dma_unmap_single(ar
->dev
, req_paddr
, req_len
, DMA_TO_DEVICE
);
1446 if (ret
== 0 && resp_len
) {
1447 *resp_len
= min(*resp_len
, xfer
.resp_len
);
1448 memcpy(resp
, tresp
, xfer
.resp_len
);
1457 static void ath10k_pci_bmi_send_done(struct ath10k_ce_pipe
*ce_state
)
1459 struct bmi_xfer
*xfer
;
1461 unsigned int nbytes
;
1462 unsigned int transfer_id
;
1464 if (ath10k_ce_completed_send_next(ce_state
, (void **)&xfer
, &ce_data
,
1465 &nbytes
, &transfer_id
))
1468 xfer
->tx_done
= true;
1471 static void ath10k_pci_bmi_recv_data(struct ath10k_ce_pipe
*ce_state
)
1473 struct ath10k
*ar
= ce_state
->ar
;
1474 struct bmi_xfer
*xfer
;
1476 unsigned int nbytes
;
1477 unsigned int transfer_id
;
1480 if (ath10k_ce_completed_recv_next(ce_state
, (void **)&xfer
, &ce_data
,
1481 &nbytes
, &transfer_id
, &flags
))
1484 if (WARN_ON_ONCE(!xfer
))
1487 if (!xfer
->wait_for_resp
) {
1488 ath10k_warn(ar
, "unexpected: BMI data received; ignoring\n");
1492 xfer
->resp_len
= nbytes
;
1493 xfer
->rx_done
= true;
1496 static int ath10k_pci_bmi_wait(struct ath10k_ce_pipe
*tx_pipe
,
1497 struct ath10k_ce_pipe
*rx_pipe
,
1498 struct bmi_xfer
*xfer
)
1500 unsigned long timeout
= jiffies
+ BMI_COMMUNICATION_TIMEOUT_HZ
;
1502 while (time_before_eq(jiffies
, timeout
)) {
1503 ath10k_pci_bmi_send_done(tx_pipe
);
1504 ath10k_pci_bmi_recv_data(rx_pipe
);
1506 if (xfer
->tx_done
&& (xfer
->rx_done
== xfer
->wait_for_resp
))
1516 * Send an interrupt to the device to wake up the Target CPU
1517 * so it has an opportunity to notice any changed state.
1519 static int ath10k_pci_wake_target_cpu(struct ath10k
*ar
)
1523 addr
= SOC_CORE_BASE_ADDRESS
| CORE_CTRL_ADDRESS
;
1524 val
= ath10k_pci_read32(ar
, addr
);
1525 val
|= CORE_CTRL_CPU_INTR_MASK
;
1526 ath10k_pci_write32(ar
, addr
, val
);
1531 static int ath10k_pci_get_num_banks(struct ath10k
*ar
)
1533 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
1535 switch (ar_pci
->pdev
->device
) {
1536 case QCA988X_2_0_DEVICE_ID
:
1538 case QCA6174_2_1_DEVICE_ID
:
1539 switch (MS(ar
->chip_id
, SOC_CHIP_ID_REV
)) {
1540 case QCA6174_HW_1_0_CHIP_ID_REV
:
1541 case QCA6174_HW_1_1_CHIP_ID_REV
:
1543 case QCA6174_HW_1_3_CHIP_ID_REV
:
1545 case QCA6174_HW_2_1_CHIP_ID_REV
:
1546 case QCA6174_HW_2_2_CHIP_ID_REV
:
1548 case QCA6174_HW_3_0_CHIP_ID_REV
:
1549 case QCA6174_HW_3_1_CHIP_ID_REV
:
1550 case QCA6174_HW_3_2_CHIP_ID_REV
:
1556 ath10k_warn(ar
, "unknown number of banks, assuming 1\n");
1560 static int ath10k_pci_init_config(struct ath10k
*ar
)
1562 u32 interconnect_targ_addr
;
1563 u32 pcie_state_targ_addr
= 0;
1564 u32 pipe_cfg_targ_addr
= 0;
1565 u32 svc_to_pipe_map
= 0;
1566 u32 pcie_config_flags
= 0;
1568 u32 ealloc_targ_addr
;
1570 u32 flag2_targ_addr
;
1573 /* Download to Target the CE Config and the service-to-CE map */
1574 interconnect_targ_addr
=
1575 host_interest_item_address(HI_ITEM(hi_interconnect_state
));
1577 /* Supply Target-side CE configuration */
1578 ret
= ath10k_pci_diag_read32(ar
, interconnect_targ_addr
,
1579 &pcie_state_targ_addr
);
1581 ath10k_err(ar
, "Failed to get pcie state addr: %d\n", ret
);
1585 if (pcie_state_targ_addr
== 0) {
1587 ath10k_err(ar
, "Invalid pcie state addr\n");
1591 ret
= ath10k_pci_diag_read32(ar
, (pcie_state_targ_addr
+
1592 offsetof(struct pcie_state
,
1594 &pipe_cfg_targ_addr
);
1596 ath10k_err(ar
, "Failed to get pipe cfg addr: %d\n", ret
);
1600 if (pipe_cfg_targ_addr
== 0) {
1602 ath10k_err(ar
, "Invalid pipe cfg addr\n");
1606 ret
= ath10k_pci_diag_write_mem(ar
, pipe_cfg_targ_addr
,
1607 target_ce_config_wlan
,
1608 sizeof(target_ce_config_wlan
));
1611 ath10k_err(ar
, "Failed to write pipe cfg: %d\n", ret
);
1615 ret
= ath10k_pci_diag_read32(ar
, (pcie_state_targ_addr
+
1616 offsetof(struct pcie_state
,
1620 ath10k_err(ar
, "Failed to get svc/pipe map: %d\n", ret
);
1624 if (svc_to_pipe_map
== 0) {
1626 ath10k_err(ar
, "Invalid svc_to_pipe map\n");
1630 ret
= ath10k_pci_diag_write_mem(ar
, svc_to_pipe_map
,
1631 target_service_to_ce_map_wlan
,
1632 sizeof(target_service_to_ce_map_wlan
));
1634 ath10k_err(ar
, "Failed to write svc/pipe map: %d\n", ret
);
1638 ret
= ath10k_pci_diag_read32(ar
, (pcie_state_targ_addr
+
1639 offsetof(struct pcie_state
,
1641 &pcie_config_flags
);
1643 ath10k_err(ar
, "Failed to get pcie config_flags: %d\n", ret
);
1647 pcie_config_flags
&= ~PCIE_CONFIG_FLAG_ENABLE_L1
;
1649 ret
= ath10k_pci_diag_write32(ar
, (pcie_state_targ_addr
+
1650 offsetof(struct pcie_state
,
1654 ath10k_err(ar
, "Failed to write pcie config_flags: %d\n", ret
);
1658 /* configure early allocation */
1659 ealloc_targ_addr
= host_interest_item_address(HI_ITEM(hi_early_alloc
));
1661 ret
= ath10k_pci_diag_read32(ar
, ealloc_targ_addr
, &ealloc_value
);
1663 ath10k_err(ar
, "Faile to get early alloc val: %d\n", ret
);
1667 /* first bank is switched to IRAM */
1668 ealloc_value
|= ((HI_EARLY_ALLOC_MAGIC
<< HI_EARLY_ALLOC_MAGIC_SHIFT
) &
1669 HI_EARLY_ALLOC_MAGIC_MASK
);
1670 ealloc_value
|= ((ath10k_pci_get_num_banks(ar
) <<
1671 HI_EARLY_ALLOC_IRAM_BANKS_SHIFT
) &
1672 HI_EARLY_ALLOC_IRAM_BANKS_MASK
);
1674 ret
= ath10k_pci_diag_write32(ar
, ealloc_targ_addr
, ealloc_value
);
1676 ath10k_err(ar
, "Failed to set early alloc val: %d\n", ret
);
1680 /* Tell Target to proceed with initialization */
1681 flag2_targ_addr
= host_interest_item_address(HI_ITEM(hi_option_flag2
));
1683 ret
= ath10k_pci_diag_read32(ar
, flag2_targ_addr
, &flag2_value
);
1685 ath10k_err(ar
, "Failed to get option val: %d\n", ret
);
1689 flag2_value
|= HI_OPTION_EARLY_CFG_DONE
;
1691 ret
= ath10k_pci_diag_write32(ar
, flag2_targ_addr
, flag2_value
);
1693 ath10k_err(ar
, "Failed to set option val: %d\n", ret
);
1700 static int ath10k_pci_alloc_pipes(struct ath10k
*ar
)
1702 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
1703 struct ath10k_pci_pipe
*pipe
;
1706 for (i
= 0; i
< CE_COUNT
; i
++) {
1707 pipe
= &ar_pci
->pipe_info
[i
];
1708 pipe
->ce_hdl
= &ar_pci
->ce_states
[i
];
1710 pipe
->hif_ce_state
= ar
;
1712 ret
= ath10k_ce_alloc_pipe(ar
, i
, &host_ce_config_wlan
[i
],
1713 ath10k_pci_ce_send_done
,
1714 ath10k_pci_ce_recv_data
);
1716 ath10k_err(ar
, "failed to allocate copy engine pipe %d: %d\n",
1721 /* Last CE is Diagnostic Window */
1722 if (i
== CE_COUNT
- 1) {
1723 ar_pci
->ce_diag
= pipe
->ce_hdl
;
1727 pipe
->buf_sz
= (size_t)(host_ce_config_wlan
[i
].src_sz_max
);
1733 static void ath10k_pci_free_pipes(struct ath10k
*ar
)
1737 for (i
= 0; i
< CE_COUNT
; i
++)
1738 ath10k_ce_free_pipe(ar
, i
);
1741 static int ath10k_pci_init_pipes(struct ath10k
*ar
)
1745 for (i
= 0; i
< CE_COUNT
; i
++) {
1746 ret
= ath10k_ce_init_pipe(ar
, i
, &host_ce_config_wlan
[i
]);
1748 ath10k_err(ar
, "failed to initialize copy engine pipe %d: %d\n",
1757 static bool ath10k_pci_has_fw_crashed(struct ath10k
*ar
)
1759 return ath10k_pci_read32(ar
, FW_INDICATOR_ADDRESS
) &
1760 FW_IND_EVENT_PENDING
;
1763 static void ath10k_pci_fw_crashed_clear(struct ath10k
*ar
)
1767 val
= ath10k_pci_read32(ar
, FW_INDICATOR_ADDRESS
);
1768 val
&= ~FW_IND_EVENT_PENDING
;
1769 ath10k_pci_write32(ar
, FW_INDICATOR_ADDRESS
, val
);
1772 /* this function effectively clears target memory controller assert line */
1773 static void ath10k_pci_warm_reset_si0(struct ath10k
*ar
)
1777 val
= ath10k_pci_soc_read32(ar
, SOC_RESET_CONTROL_ADDRESS
);
1778 ath10k_pci_soc_write32(ar
, SOC_RESET_CONTROL_ADDRESS
,
1779 val
| SOC_RESET_CONTROL_SI0_RST_MASK
);
1780 val
= ath10k_pci_soc_read32(ar
, SOC_RESET_CONTROL_ADDRESS
);
1784 val
= ath10k_pci_soc_read32(ar
, SOC_RESET_CONTROL_ADDRESS
);
1785 ath10k_pci_soc_write32(ar
, SOC_RESET_CONTROL_ADDRESS
,
1786 val
& ~SOC_RESET_CONTROL_SI0_RST_MASK
);
1787 val
= ath10k_pci_soc_read32(ar
, SOC_RESET_CONTROL_ADDRESS
);
1792 static void ath10k_pci_warm_reset_cpu(struct ath10k
*ar
)
1796 ath10k_pci_write32(ar
, FW_INDICATOR_ADDRESS
, 0);
1798 val
= ath10k_pci_read32(ar
, RTC_SOC_BASE_ADDRESS
+
1799 SOC_RESET_CONTROL_ADDRESS
);
1800 ath10k_pci_write32(ar
, RTC_SOC_BASE_ADDRESS
+ SOC_RESET_CONTROL_ADDRESS
,
1801 val
| SOC_RESET_CONTROL_CPU_WARM_RST_MASK
);
1804 static void ath10k_pci_warm_reset_ce(struct ath10k
*ar
)
1808 val
= ath10k_pci_read32(ar
, RTC_SOC_BASE_ADDRESS
+
1809 SOC_RESET_CONTROL_ADDRESS
);
1811 ath10k_pci_write32(ar
, RTC_SOC_BASE_ADDRESS
+ SOC_RESET_CONTROL_ADDRESS
,
1812 val
| SOC_RESET_CONTROL_CE_RST_MASK
);
1814 ath10k_pci_write32(ar
, RTC_SOC_BASE_ADDRESS
+ SOC_RESET_CONTROL_ADDRESS
,
1815 val
& ~SOC_RESET_CONTROL_CE_RST_MASK
);
1818 static void ath10k_pci_warm_reset_clear_lf(struct ath10k
*ar
)
1822 val
= ath10k_pci_read32(ar
, RTC_SOC_BASE_ADDRESS
+
1823 SOC_LF_TIMER_CONTROL0_ADDRESS
);
1824 ath10k_pci_write32(ar
, RTC_SOC_BASE_ADDRESS
+
1825 SOC_LF_TIMER_CONTROL0_ADDRESS
,
1826 val
& ~SOC_LF_TIMER_CONTROL0_ENABLE_MASK
);
1829 static int ath10k_pci_warm_reset(struct ath10k
*ar
)
1833 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot warm reset\n");
1835 spin_lock_bh(&ar
->data_lock
);
1836 ar
->stats
.fw_warm_reset_counter
++;
1837 spin_unlock_bh(&ar
->data_lock
);
1839 ath10k_pci_irq_disable(ar
);
1841 /* Make sure the target CPU is not doing anything dangerous, e.g. if it
1842 * were to access copy engine while host performs copy engine reset
1843 * then it is possible for the device to confuse pci-e controller to
1844 * the point of bringing host system to a complete stop (i.e. hang).
1846 ath10k_pci_warm_reset_si0(ar
);
1847 ath10k_pci_warm_reset_cpu(ar
);
1848 ath10k_pci_init_pipes(ar
);
1849 ath10k_pci_wait_for_target_init(ar
);
1851 ath10k_pci_warm_reset_clear_lf(ar
);
1852 ath10k_pci_warm_reset_ce(ar
);
1853 ath10k_pci_warm_reset_cpu(ar
);
1854 ath10k_pci_init_pipes(ar
);
1856 ret
= ath10k_pci_wait_for_target_init(ar
);
1858 ath10k_warn(ar
, "failed to wait for target init: %d\n", ret
);
1862 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot warm reset complete\n");
1867 static int ath10k_pci_qca988x_chip_reset(struct ath10k
*ar
)
1872 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot 988x chip reset\n");
1874 /* Some hardware revisions (e.g. CUS223v2) has issues with cold reset.
1875 * It is thus preferred to use warm reset which is safer but may not be
1876 * able to recover the device from all possible fail scenarios.
1878 * Warm reset doesn't always work on first try so attempt it a few
1879 * times before giving up.
1881 for (i
= 0; i
< ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS
; i
++) {
1882 ret
= ath10k_pci_warm_reset(ar
);
1884 ath10k_warn(ar
, "failed to warm reset attempt %d of %d: %d\n",
1885 i
+ 1, ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS
,
1890 /* FIXME: Sometimes copy engine doesn't recover after warm
1891 * reset. In most cases this needs cold reset. In some of these
1892 * cases the device is in such a state that a cold reset may
1895 * Reading any host interest register via copy engine is
1896 * sufficient to verify if device is capable of booting
1899 ret
= ath10k_pci_init_pipes(ar
);
1901 ath10k_warn(ar
, "failed to init copy engine: %d\n",
1906 ret
= ath10k_pci_diag_read32(ar
, QCA988X_HOST_INTEREST_ADDRESS
,
1909 ath10k_warn(ar
, "failed to poke copy engine: %d\n",
1914 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot chip reset complete (warm)\n");
1918 if (ath10k_pci_reset_mode
== ATH10K_PCI_RESET_WARM_ONLY
) {
1919 ath10k_warn(ar
, "refusing cold reset as requested\n");
1923 ret
= ath10k_pci_cold_reset(ar
);
1925 ath10k_warn(ar
, "failed to cold reset: %d\n", ret
);
1929 ret
= ath10k_pci_wait_for_target_init(ar
);
1931 ath10k_warn(ar
, "failed to wait for target after cold reset: %d\n",
1936 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot qca988x chip reset complete (cold)\n");
1941 static int ath10k_pci_qca6174_chip_reset(struct ath10k
*ar
)
1945 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot qca6174 chip reset\n");
1947 /* FIXME: QCA6174 requires cold + warm reset to work. */
1949 ret
= ath10k_pci_cold_reset(ar
);
1951 ath10k_warn(ar
, "failed to cold reset: %d\n", ret
);
1955 ret
= ath10k_pci_wait_for_target_init(ar
);
1957 ath10k_warn(ar
, "failed to wait for target after cold reset: %d\n",
1962 ret
= ath10k_pci_warm_reset(ar
);
1964 ath10k_warn(ar
, "failed to warm reset: %d\n", ret
);
1968 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot qca6174 chip reset complete (cold)\n");
1973 static int ath10k_pci_chip_reset(struct ath10k
*ar
)
1975 if (QCA_REV_988X(ar
))
1976 return ath10k_pci_qca988x_chip_reset(ar
);
1977 else if (QCA_REV_6174(ar
))
1978 return ath10k_pci_qca6174_chip_reset(ar
);
1983 static int ath10k_pci_hif_power_up(struct ath10k
*ar
)
1987 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot hif power up\n");
1989 ret
= ath10k_pci_wake(ar
);
1991 ath10k_err(ar
, "failed to wake up target: %d\n", ret
);
1996 * Bring the target up cleanly.
1998 * The target may be in an undefined state with an AUX-powered Target
1999 * and a Host in WoW mode. If the Host crashes, loses power, or is
2000 * restarted (without unloading the driver) then the Target is left
2001 * (aux) powered and running. On a subsequent driver load, the Target
2002 * is in an unexpected state. We try to catch that here in order to
2003 * reset the Target and retry the probe.
2005 ret
= ath10k_pci_chip_reset(ar
);
2007 if (ath10k_pci_has_fw_crashed(ar
)) {
2008 ath10k_warn(ar
, "firmware crashed during chip reset\n");
2009 ath10k_pci_fw_crashed_clear(ar
);
2010 ath10k_pci_fw_crashed_dump(ar
);
2013 ath10k_err(ar
, "failed to reset chip: %d\n", ret
);
2017 ret
= ath10k_pci_init_pipes(ar
);
2019 ath10k_err(ar
, "failed to initialize CE: %d\n", ret
);
2023 ret
= ath10k_pci_init_config(ar
);
2025 ath10k_err(ar
, "failed to setup init config: %d\n", ret
);
2029 ret
= ath10k_pci_wake_target_cpu(ar
);
2031 ath10k_err(ar
, "could not wake up target CPU: %d\n", ret
);
2038 ath10k_pci_ce_deinit(ar
);
2041 ath10k_pci_sleep(ar
);
2045 static void ath10k_pci_hif_power_down(struct ath10k
*ar
)
2047 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot hif power down\n");
2049 /* Currently hif_power_up performs effectively a reset and hif_stop
2050 * resets the chip as well so there's no point in resetting here.
2056 static int ath10k_pci_hif_suspend(struct ath10k
*ar
)
2058 ath10k_pci_sleep(ar
);
2063 static int ath10k_pci_hif_resume(struct ath10k
*ar
)
2065 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2066 struct pci_dev
*pdev
= ar_pci
->pdev
;
2070 ret
= ath10k_pci_wake(ar
);
2072 ath10k_err(ar
, "failed to wake device up on resume: %d\n", ret
);
2076 /* Suspend/Resume resets the PCI configuration space, so we have to
2077 * re-disable the RETRY_TIMEOUT register (0x41) to keep PCI Tx retries
2078 * from interfering with C3 CPU state. pci_restore_state won't help
2079 * here since it only restores the first 64 bytes pci config header.
2081 pci_read_config_dword(pdev
, 0x40, &val
);
2082 if ((val
& 0x0000ff00) != 0)
2083 pci_write_config_dword(pdev
, 0x40, val
& 0xffff00ff);
2089 static const struct ath10k_hif_ops ath10k_pci_hif_ops
= {
2090 .tx_sg
= ath10k_pci_hif_tx_sg
,
2091 .diag_read
= ath10k_pci_hif_diag_read
,
2092 .diag_write
= ath10k_pci_diag_write_mem
,
2093 .exchange_bmi_msg
= ath10k_pci_hif_exchange_bmi_msg
,
2094 .start
= ath10k_pci_hif_start
,
2095 .stop
= ath10k_pci_hif_stop
,
2096 .map_service_to_pipe
= ath10k_pci_hif_map_service_to_pipe
,
2097 .get_default_pipe
= ath10k_pci_hif_get_default_pipe
,
2098 .send_complete_check
= ath10k_pci_hif_send_complete_check
,
2099 .set_callbacks
= ath10k_pci_hif_set_callbacks
,
2100 .get_free_queue_number
= ath10k_pci_hif_get_free_queue_number
,
2101 .power_up
= ath10k_pci_hif_power_up
,
2102 .power_down
= ath10k_pci_hif_power_down
,
2103 .read32
= ath10k_pci_read32
,
2104 .write32
= ath10k_pci_write32
,
2106 .suspend
= ath10k_pci_hif_suspend
,
2107 .resume
= ath10k_pci_hif_resume
,
2111 static void ath10k_pci_ce_tasklet(unsigned long ptr
)
2113 struct ath10k_pci_pipe
*pipe
= (struct ath10k_pci_pipe
*)ptr
;
2114 struct ath10k_pci
*ar_pci
= pipe
->ar_pci
;
2116 ath10k_ce_per_engine_service(ar_pci
->ar
, pipe
->pipe_num
);
2119 static void ath10k_msi_err_tasklet(unsigned long data
)
2121 struct ath10k
*ar
= (struct ath10k
*)data
;
2123 if (!ath10k_pci_has_fw_crashed(ar
)) {
2124 ath10k_warn(ar
, "received unsolicited fw crash interrupt\n");
2128 ath10k_pci_irq_disable(ar
);
2129 ath10k_pci_fw_crashed_clear(ar
);
2130 ath10k_pci_fw_crashed_dump(ar
);
2134 * Handler for a per-engine interrupt on a PARTICULAR CE.
2135 * This is used in cases where each CE has a private MSI interrupt.
2137 static irqreturn_t
ath10k_pci_per_engine_handler(int irq
, void *arg
)
2139 struct ath10k
*ar
= arg
;
2140 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2141 int ce_id
= irq
- ar_pci
->pdev
->irq
- MSI_ASSIGN_CE_INITIAL
;
2143 if (ce_id
< 0 || ce_id
>= ARRAY_SIZE(ar_pci
->pipe_info
)) {
2144 ath10k_warn(ar
, "unexpected/invalid irq %d ce_id %d\n", irq
,
2150 * NOTE: We are able to derive ce_id from irq because we
2151 * use a one-to-one mapping for CE's 0..5.
2152 * CE's 6 & 7 do not use interrupts at all.
2154 * This mapping must be kept in sync with the mapping
2157 tasklet_schedule(&ar_pci
->pipe_info
[ce_id
].intr
);
2161 static irqreturn_t
ath10k_pci_msi_fw_handler(int irq
, void *arg
)
2163 struct ath10k
*ar
= arg
;
2164 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2166 tasklet_schedule(&ar_pci
->msi_fw_err
);
2171 * Top-level interrupt handler for all PCI interrupts from a Target.
2172 * When a block of MSI interrupts is allocated, this top-level handler
2173 * is not used; instead, we directly call the correct sub-handler.
2175 static irqreturn_t
ath10k_pci_interrupt_handler(int irq
, void *arg
)
2177 struct ath10k
*ar
= arg
;
2178 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2181 ret
= ath10k_pci_wake(ar
);
2183 ath10k_warn(ar
, "failed to wake device up on irq: %d\n", ret
);
2187 if (ar_pci
->num_msi_intrs
== 0) {
2188 if (!ath10k_pci_irq_pending(ar
))
2191 ath10k_pci_disable_and_clear_legacy_irq(ar
);
2194 tasklet_schedule(&ar_pci
->intr_tq
);
2199 static void ath10k_pci_tasklet(unsigned long data
)
2201 struct ath10k
*ar
= (struct ath10k
*)data
;
2202 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2204 if (ath10k_pci_has_fw_crashed(ar
)) {
2205 ath10k_pci_irq_disable(ar
);
2206 ath10k_pci_fw_crashed_clear(ar
);
2207 ath10k_pci_fw_crashed_dump(ar
);
2211 ath10k_ce_per_engine_service_any(ar
);
2213 /* Re-enable legacy irq that was disabled in the irq handler */
2214 if (ar_pci
->num_msi_intrs
== 0)
2215 ath10k_pci_enable_legacy_irq(ar
);
2218 static int ath10k_pci_request_irq_msix(struct ath10k
*ar
)
2220 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2223 ret
= request_irq(ar_pci
->pdev
->irq
+ MSI_ASSIGN_FW
,
2224 ath10k_pci_msi_fw_handler
,
2225 IRQF_SHARED
, "ath10k_pci", ar
);
2227 ath10k_warn(ar
, "failed to request MSI-X fw irq %d: %d\n",
2228 ar_pci
->pdev
->irq
+ MSI_ASSIGN_FW
, ret
);
2232 for (i
= MSI_ASSIGN_CE_INITIAL
; i
<= MSI_ASSIGN_CE_MAX
; i
++) {
2233 ret
= request_irq(ar_pci
->pdev
->irq
+ i
,
2234 ath10k_pci_per_engine_handler
,
2235 IRQF_SHARED
, "ath10k_pci", ar
);
2237 ath10k_warn(ar
, "failed to request MSI-X ce irq %d: %d\n",
2238 ar_pci
->pdev
->irq
+ i
, ret
);
2240 for (i
--; i
>= MSI_ASSIGN_CE_INITIAL
; i
--)
2241 free_irq(ar_pci
->pdev
->irq
+ i
, ar
);
2243 free_irq(ar_pci
->pdev
->irq
+ MSI_ASSIGN_FW
, ar
);
2251 static int ath10k_pci_request_irq_msi(struct ath10k
*ar
)
2253 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2256 ret
= request_irq(ar_pci
->pdev
->irq
,
2257 ath10k_pci_interrupt_handler
,
2258 IRQF_SHARED
, "ath10k_pci", ar
);
2260 ath10k_warn(ar
, "failed to request MSI irq %d: %d\n",
2261 ar_pci
->pdev
->irq
, ret
);
2268 static int ath10k_pci_request_irq_legacy(struct ath10k
*ar
)
2270 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2273 ret
= request_irq(ar_pci
->pdev
->irq
,
2274 ath10k_pci_interrupt_handler
,
2275 IRQF_SHARED
, "ath10k_pci", ar
);
2277 ath10k_warn(ar
, "failed to request legacy irq %d: %d\n",
2278 ar_pci
->pdev
->irq
, ret
);
2285 static int ath10k_pci_request_irq(struct ath10k
*ar
)
2287 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2289 switch (ar_pci
->num_msi_intrs
) {
2291 return ath10k_pci_request_irq_legacy(ar
);
2293 return ath10k_pci_request_irq_msi(ar
);
2294 case MSI_NUM_REQUEST
:
2295 return ath10k_pci_request_irq_msix(ar
);
2298 ath10k_warn(ar
, "unknown irq configuration upon request\n");
2302 static void ath10k_pci_free_irq(struct ath10k
*ar
)
2304 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2307 /* There's at least one interrupt irregardless whether its legacy INTR
2308 * or MSI or MSI-X */
2309 for (i
= 0; i
< max(1, ar_pci
->num_msi_intrs
); i
++)
2310 free_irq(ar_pci
->pdev
->irq
+ i
, ar
);
2313 static void ath10k_pci_init_irq_tasklets(struct ath10k
*ar
)
2315 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2318 tasklet_init(&ar_pci
->intr_tq
, ath10k_pci_tasklet
, (unsigned long)ar
);
2319 tasklet_init(&ar_pci
->msi_fw_err
, ath10k_msi_err_tasklet
,
2322 for (i
= 0; i
< CE_COUNT
; i
++) {
2323 ar_pci
->pipe_info
[i
].ar_pci
= ar_pci
;
2324 tasklet_init(&ar_pci
->pipe_info
[i
].intr
, ath10k_pci_ce_tasklet
,
2325 (unsigned long)&ar_pci
->pipe_info
[i
]);
2329 static int ath10k_pci_init_irq(struct ath10k
*ar
)
2331 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2334 ath10k_pci_init_irq_tasklets(ar
);
2336 if (ath10k_pci_irq_mode
!= ATH10K_PCI_IRQ_AUTO
)
2337 ath10k_info(ar
, "limiting irq mode to: %d\n",
2338 ath10k_pci_irq_mode
);
2341 if (ath10k_pci_irq_mode
== ATH10K_PCI_IRQ_AUTO
) {
2342 ar_pci
->num_msi_intrs
= MSI_NUM_REQUEST
;
2343 ret
= pci_enable_msi_range(ar_pci
->pdev
, ar_pci
->num_msi_intrs
,
2344 ar_pci
->num_msi_intrs
);
2352 if (ath10k_pci_irq_mode
!= ATH10K_PCI_IRQ_LEGACY
) {
2353 ar_pci
->num_msi_intrs
= 1;
2354 ret
= pci_enable_msi(ar_pci
->pdev
);
2363 * A potential race occurs here: The CORE_BASE write
2364 * depends on target correctly decoding AXI address but
2365 * host won't know when target writes BAR to CORE_CTRL.
2366 * This write might get lost if target has NOT written BAR.
2367 * For now, fix the race by repeating the write in below
2368 * synchronization checking. */
2369 ar_pci
->num_msi_intrs
= 0;
2371 ath10k_pci_write32(ar
, SOC_CORE_BASE_ADDRESS
+ PCIE_INTR_ENABLE_ADDRESS
,
2372 PCIE_INTR_FIRMWARE_MASK
| PCIE_INTR_CE_MASK_ALL
);
2377 static void ath10k_pci_deinit_irq_legacy(struct ath10k
*ar
)
2379 ath10k_pci_write32(ar
, SOC_CORE_BASE_ADDRESS
+ PCIE_INTR_ENABLE_ADDRESS
,
2383 static int ath10k_pci_deinit_irq(struct ath10k
*ar
)
2385 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2387 switch (ar_pci
->num_msi_intrs
) {
2389 ath10k_pci_deinit_irq_legacy(ar
);
2393 case MSI_NUM_REQUEST
:
2394 pci_disable_msi(ar_pci
->pdev
);
2397 pci_disable_msi(ar_pci
->pdev
);
2400 ath10k_warn(ar
, "unknown irq configuration upon deinit\n");
2404 static int ath10k_pci_wait_for_target_init(struct ath10k
*ar
)
2406 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2407 unsigned long timeout
;
2410 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot waiting target to initialise\n");
2412 timeout
= jiffies
+ msecs_to_jiffies(ATH10K_PCI_TARGET_WAIT
);
2415 val
= ath10k_pci_read32(ar
, FW_INDICATOR_ADDRESS
);
2417 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot target indicator %x\n",
2420 /* target should never return this */
2421 if (val
== 0xffffffff)
2424 /* the device has crashed so don't bother trying anymore */
2425 if (val
& FW_IND_EVENT_PENDING
)
2428 if (val
& FW_IND_INITIALIZED
)
2431 if (ar_pci
->num_msi_intrs
== 0)
2432 /* Fix potential race by repeating CORE_BASE writes */
2433 ath10k_pci_enable_legacy_irq(ar
);
2436 } while (time_before(jiffies
, timeout
));
2438 ath10k_pci_disable_and_clear_legacy_irq(ar
);
2439 ath10k_pci_irq_msi_fw_mask(ar
);
2441 if (val
== 0xffffffff) {
2442 ath10k_err(ar
, "failed to read device register, device is gone\n");
2446 if (val
& FW_IND_EVENT_PENDING
) {
2447 ath10k_warn(ar
, "device has crashed during init\n");
2451 if (!(val
& FW_IND_INITIALIZED
)) {
2452 ath10k_err(ar
, "failed to receive initialized event from target: %08x\n",
2457 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot target initialised\n");
2461 static int ath10k_pci_cold_reset(struct ath10k
*ar
)
2466 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot cold reset\n");
2468 spin_lock_bh(&ar
->data_lock
);
2470 ar
->stats
.fw_cold_reset_counter
++;
2472 spin_unlock_bh(&ar
->data_lock
);
2474 /* Put Target, including PCIe, into RESET. */
2475 val
= ath10k_pci_reg_read32(ar
, SOC_GLOBAL_RESET_ADDRESS
);
2477 ath10k_pci_reg_write32(ar
, SOC_GLOBAL_RESET_ADDRESS
, val
);
2479 for (i
= 0; i
< ATH_PCI_RESET_WAIT_MAX
; i
++) {
2480 if (ath10k_pci_reg_read32(ar
, RTC_STATE_ADDRESS
) &
2481 RTC_STATE_COLD_RESET_MASK
)
2486 /* Pull Target, including PCIe, out of RESET. */
2488 ath10k_pci_reg_write32(ar
, SOC_GLOBAL_RESET_ADDRESS
, val
);
2490 for (i
= 0; i
< ATH_PCI_RESET_WAIT_MAX
; i
++) {
2491 if (!(ath10k_pci_reg_read32(ar
, RTC_STATE_ADDRESS
) &
2492 RTC_STATE_COLD_RESET_MASK
))
2497 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot cold reset complete\n");
2502 static int ath10k_pci_claim(struct ath10k
*ar
)
2504 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2505 struct pci_dev
*pdev
= ar_pci
->pdev
;
2509 pci_set_drvdata(pdev
, ar
);
2511 ret
= pci_enable_device(pdev
);
2513 ath10k_err(ar
, "failed to enable pci device: %d\n", ret
);
2517 ret
= pci_request_region(pdev
, BAR_NUM
, "ath");
2519 ath10k_err(ar
, "failed to request region BAR%d: %d\n", BAR_NUM
,
2524 /* Target expects 32 bit DMA. Enforce it. */
2525 ret
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
2527 ath10k_err(ar
, "failed to set dma mask to 32-bit: %d\n", ret
);
2531 ret
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(32));
2533 ath10k_err(ar
, "failed to set consistent dma mask to 32-bit: %d\n",
2538 pci_set_master(pdev
);
2540 /* Workaround: Disable ASPM */
2541 pci_read_config_dword(pdev
, 0x80, &lcr_val
);
2542 pci_write_config_dword(pdev
, 0x80, (lcr_val
& 0xffffff00));
2544 /* Arrange for access to Target SoC registers. */
2545 ar_pci
->mem
= pci_iomap(pdev
, BAR_NUM
, 0);
2547 ath10k_err(ar
, "failed to iomap BAR%d\n", BAR_NUM
);
2552 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot pci_mem 0x%p\n", ar_pci
->mem
);
2556 pci_clear_master(pdev
);
2559 pci_release_region(pdev
, BAR_NUM
);
2562 pci_disable_device(pdev
);
2567 static void ath10k_pci_release(struct ath10k
*ar
)
2569 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2570 struct pci_dev
*pdev
= ar_pci
->pdev
;
2572 pci_iounmap(pdev
, ar_pci
->mem
);
2573 pci_release_region(pdev
, BAR_NUM
);
2574 pci_clear_master(pdev
);
2575 pci_disable_device(pdev
);
2578 static bool ath10k_pci_chip_is_supported(u32 dev_id
, u32 chip_id
)
2580 const struct ath10k_pci_supp_chip
*supp_chip
;
2582 u32 rev_id
= MS(chip_id
, SOC_CHIP_ID_REV
);
2584 for (i
= 0; i
< ARRAY_SIZE(ath10k_pci_supp_chips
); i
++) {
2585 supp_chip
= &ath10k_pci_supp_chips
[i
];
2587 if (supp_chip
->dev_id
== dev_id
&&
2588 supp_chip
->rev_id
== rev_id
)
2595 static int ath10k_pci_probe(struct pci_dev
*pdev
,
2596 const struct pci_device_id
*pci_dev
)
2600 struct ath10k_pci
*ar_pci
;
2601 enum ath10k_hw_rev hw_rev
;
2604 switch (pci_dev
->device
) {
2605 case QCA988X_2_0_DEVICE_ID
:
2606 hw_rev
= ATH10K_HW_QCA988X
;
2608 case QCA6174_2_1_DEVICE_ID
:
2609 hw_rev
= ATH10K_HW_QCA6174
;
2616 ar
= ath10k_core_create(sizeof(*ar_pci
), &pdev
->dev
, ATH10K_BUS_PCI
,
2617 hw_rev
, &ath10k_pci_hif_ops
);
2619 dev_err(&pdev
->dev
, "failed to allocate core\n");
2623 ath10k_dbg(ar
, ATH10K_DBG_PCI
, "pci probe\n");
2625 ar_pci
= ath10k_pci_priv(ar
);
2626 ar_pci
->pdev
= pdev
;
2627 ar_pci
->dev
= &pdev
->dev
;
2630 spin_lock_init(&ar_pci
->ce_lock
);
2631 setup_timer(&ar_pci
->rx_post_retry
, ath10k_pci_rx_replenish_retry
,
2634 ret
= ath10k_pci_claim(ar
);
2636 ath10k_err(ar
, "failed to claim device: %d\n", ret
);
2637 goto err_core_destroy
;
2640 ret
= ath10k_pci_wake(ar
);
2642 ath10k_err(ar
, "failed to wake up: %d\n", ret
);
2646 ret
= ath10k_pci_alloc_pipes(ar
);
2648 ath10k_err(ar
, "failed to allocate copy engine pipes: %d\n",
2653 ath10k_pci_ce_deinit(ar
);
2654 ath10k_pci_irq_disable(ar
);
2656 ret
= ath10k_pci_init_irq(ar
);
2658 ath10k_err(ar
, "failed to init irqs: %d\n", ret
);
2659 goto err_free_pipes
;
2662 ath10k_info(ar
, "pci irq %s interrupts %d irq_mode %d reset_mode %d\n",
2663 ath10k_pci_get_irq_method(ar
), ar_pci
->num_msi_intrs
,
2664 ath10k_pci_irq_mode
, ath10k_pci_reset_mode
);
2666 ret
= ath10k_pci_request_irq(ar
);
2668 ath10k_warn(ar
, "failed to request irqs: %d\n", ret
);
2669 goto err_deinit_irq
;
2672 ret
= ath10k_pci_chip_reset(ar
);
2674 ath10k_err(ar
, "failed to reset chip: %d\n", ret
);
2678 chip_id
= ath10k_pci_soc_read32(ar
, SOC_CHIP_ID_ADDRESS
);
2679 if (chip_id
== 0xffffffff) {
2680 ath10k_err(ar
, "failed to get chip id\n");
2684 if (!ath10k_pci_chip_is_supported(pdev
->device
, chip_id
)) {
2685 ath10k_err(ar
, "device %04x with chip_id %08x isn't supported\n",
2686 pdev
->device
, chip_id
);
2690 ret
= ath10k_core_register(ar
, chip_id
);
2692 ath10k_err(ar
, "failed to register driver core: %d\n", ret
);
2699 ath10k_pci_free_irq(ar
);
2700 ath10k_pci_kill_tasklet(ar
);
2703 ath10k_pci_deinit_irq(ar
);
2706 ath10k_pci_free_pipes(ar
);
2709 ath10k_pci_sleep(ar
);
2712 ath10k_pci_release(ar
);
2715 ath10k_core_destroy(ar
);
2720 static void ath10k_pci_remove(struct pci_dev
*pdev
)
2722 struct ath10k
*ar
= pci_get_drvdata(pdev
);
2723 struct ath10k_pci
*ar_pci
;
2725 ath10k_dbg(ar
, ATH10K_DBG_PCI
, "pci remove\n");
2730 ar_pci
= ath10k_pci_priv(ar
);
2735 ath10k_core_unregister(ar
);
2736 ath10k_pci_free_irq(ar
);
2737 ath10k_pci_kill_tasklet(ar
);
2738 ath10k_pci_deinit_irq(ar
);
2739 ath10k_pci_ce_deinit(ar
);
2740 ath10k_pci_free_pipes(ar
);
2741 ath10k_pci_release(ar
);
2742 ath10k_core_destroy(ar
);
2745 MODULE_DEVICE_TABLE(pci
, ath10k_pci_id_table
);
2747 static struct pci_driver ath10k_pci_driver
= {
2748 .name
= "ath10k_pci",
2749 .id_table
= ath10k_pci_id_table
,
2750 .probe
= ath10k_pci_probe
,
2751 .remove
= ath10k_pci_remove
,
2754 static int __init
ath10k_pci_init(void)
2758 ret
= pci_register_driver(&ath10k_pci_driver
);
2760 printk(KERN_ERR
"failed to register ath10k pci driver: %d\n",
2765 module_init(ath10k_pci_init
);
2767 static void __exit
ath10k_pci_exit(void)
2769 pci_unregister_driver(&ath10k_pci_driver
);
2772 module_exit(ath10k_pci_exit
);
2774 MODULE_AUTHOR("Qualcomm Atheros");
2775 MODULE_DESCRIPTION("Driver support for Atheros QCA988X PCIe devices");
2776 MODULE_LICENSE("Dual BSD/GPL");
2778 /* QCA988x 2.0 firmware files */
2779 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR
"/" QCA988X_HW_2_0_FW_FILE
);
2780 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR
"/" ATH10K_FW_API2_FILE
);
2781 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR
"/" ATH10K_FW_API3_FILE
);
2782 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR
"/" ATH10K_FW_API4_FILE
);
2783 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR
"/" ATH10K_FW_API5_FILE
);
2784 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR
"/" QCA988X_HW_2_0_BOARD_DATA_FILE
);
2786 /* QCA6174 2.1 firmware files */
2787 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR
"/" ATH10K_FW_API4_FILE
);
2788 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR
"/" QCA6174_HW_2_1_BOARD_DATA_FILE
);
2790 /* QCA6174 3.1 firmware files */
2791 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR
"/" ATH10K_FW_API4_FILE
);
2792 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR
"/" QCA6174_HW_3_0_BOARD_DATA_FILE
);