2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <linux/pci.h>
19 #include <linux/module.h>
20 #include <linux/interrupt.h>
21 #include <linux/spinlock.h>
22 #include <linux/bitops.h>
27 #include "targaddrs.h"
36 enum ath10k_pci_irq_mode
{
37 ATH10K_PCI_IRQ_AUTO
= 0,
38 ATH10K_PCI_IRQ_LEGACY
= 1,
39 ATH10K_PCI_IRQ_MSI
= 2,
42 enum ath10k_pci_reset_mode
{
43 ATH10K_PCI_RESET_AUTO
= 0,
44 ATH10K_PCI_RESET_WARM_ONLY
= 1,
47 static unsigned int ath10k_pci_irq_mode
= ATH10K_PCI_IRQ_AUTO
;
48 static unsigned int ath10k_pci_reset_mode
= ATH10K_PCI_RESET_AUTO
;
50 module_param_named(irq_mode
, ath10k_pci_irq_mode
, uint
, 0644);
51 MODULE_PARM_DESC(irq_mode
, "0: auto, 1: legacy, 2: msi (default: 0)");
53 module_param_named(reset_mode
, ath10k_pci_reset_mode
, uint
, 0644);
54 MODULE_PARM_DESC(reset_mode
, "0: auto, 1: warm only (default: 0)");
56 /* how long wait to wait for target to initialise, in ms */
57 #define ATH10K_PCI_TARGET_WAIT 3000
58 #define ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS 3
60 #define QCA988X_2_0_DEVICE_ID (0x003c)
62 static const struct pci_device_id ath10k_pci_id_table
[] = {
63 { PCI_VDEVICE(ATHEROS
, QCA988X_2_0_DEVICE_ID
) }, /* PCI-E QCA988X V2 */
67 static void ath10k_pci_buffer_cleanup(struct ath10k
*ar
);
68 static int ath10k_pci_cold_reset(struct ath10k
*ar
);
69 static int ath10k_pci_warm_reset(struct ath10k
*ar
);
70 static int ath10k_pci_wait_for_target_init(struct ath10k
*ar
);
71 static int ath10k_pci_init_irq(struct ath10k
*ar
);
72 static int ath10k_pci_deinit_irq(struct ath10k
*ar
);
73 static int ath10k_pci_request_irq(struct ath10k
*ar
);
74 static void ath10k_pci_free_irq(struct ath10k
*ar
);
75 static int ath10k_pci_bmi_wait(struct ath10k_ce_pipe
*tx_pipe
,
76 struct ath10k_ce_pipe
*rx_pipe
,
77 struct bmi_xfer
*xfer
);
79 static const struct ce_attr host_ce_config_wlan
[] = {
80 /* CE0: host->target HTC control and raw streams */
82 .flags
= CE_ATTR_FLAGS
,
88 /* CE1: target->host HTT + HTC control */
90 .flags
= CE_ATTR_FLAGS
,
96 /* CE2: target->host WMI */
98 .flags
= CE_ATTR_FLAGS
,
104 /* CE3: host->target WMI */
106 .flags
= CE_ATTR_FLAGS
,
112 /* CE4: host->target HTT */
114 .flags
= CE_ATTR_FLAGS
| CE_ATTR_DIS_INTR
,
115 .src_nentries
= CE_HTT_H2T_MSG_SRC_NENTRIES
,
122 .flags
= CE_ATTR_FLAGS
,
128 /* CE6: target autonomous hif_memcpy */
130 .flags
= CE_ATTR_FLAGS
,
136 /* CE7: ce_diag, the Diagnostic Window */
138 .flags
= CE_ATTR_FLAGS
,
140 .src_sz_max
= DIAG_TRANSFER_LIMIT
,
145 /* Target firmware's Copy Engine configuration. */
146 static const struct ce_pipe_config target_ce_config_wlan
[] = {
147 /* CE0: host->target HTC control and raw streams */
149 .pipenum
= __cpu_to_le32(0),
150 .pipedir
= __cpu_to_le32(PIPEDIR_OUT
),
151 .nentries
= __cpu_to_le32(32),
152 .nbytes_max
= __cpu_to_le32(256),
153 .flags
= __cpu_to_le32(CE_ATTR_FLAGS
),
154 .reserved
= __cpu_to_le32(0),
157 /* CE1: target->host HTT + HTC control */
159 .pipenum
= __cpu_to_le32(1),
160 .pipedir
= __cpu_to_le32(PIPEDIR_IN
),
161 .nentries
= __cpu_to_le32(32),
162 .nbytes_max
= __cpu_to_le32(512),
163 .flags
= __cpu_to_le32(CE_ATTR_FLAGS
),
164 .reserved
= __cpu_to_le32(0),
167 /* CE2: target->host WMI */
169 .pipenum
= __cpu_to_le32(2),
170 .pipedir
= __cpu_to_le32(PIPEDIR_IN
),
171 .nentries
= __cpu_to_le32(32),
172 .nbytes_max
= __cpu_to_le32(2048),
173 .flags
= __cpu_to_le32(CE_ATTR_FLAGS
),
174 .reserved
= __cpu_to_le32(0),
177 /* CE3: host->target WMI */
179 .pipenum
= __cpu_to_le32(3),
180 .pipedir
= __cpu_to_le32(PIPEDIR_OUT
),
181 .nentries
= __cpu_to_le32(32),
182 .nbytes_max
= __cpu_to_le32(2048),
183 .flags
= __cpu_to_le32(CE_ATTR_FLAGS
),
184 .reserved
= __cpu_to_le32(0),
187 /* CE4: host->target HTT */
189 .pipenum
= __cpu_to_le32(4),
190 .pipedir
= __cpu_to_le32(PIPEDIR_OUT
),
191 .nentries
= __cpu_to_le32(256),
192 .nbytes_max
= __cpu_to_le32(256),
193 .flags
= __cpu_to_le32(CE_ATTR_FLAGS
),
194 .reserved
= __cpu_to_le32(0),
197 /* NB: 50% of src nentries, since tx has 2 frags */
201 .pipenum
= __cpu_to_le32(5),
202 .pipedir
= __cpu_to_le32(PIPEDIR_OUT
),
203 .nentries
= __cpu_to_le32(32),
204 .nbytes_max
= __cpu_to_le32(2048),
205 .flags
= __cpu_to_le32(CE_ATTR_FLAGS
),
206 .reserved
= __cpu_to_le32(0),
209 /* CE6: Reserved for target autonomous hif_memcpy */
211 .pipenum
= __cpu_to_le32(6),
212 .pipedir
= __cpu_to_le32(PIPEDIR_INOUT
),
213 .nentries
= __cpu_to_le32(32),
214 .nbytes_max
= __cpu_to_le32(4096),
215 .flags
= __cpu_to_le32(CE_ATTR_FLAGS
),
216 .reserved
= __cpu_to_le32(0),
219 /* CE7 used only by Host */
223 * Map from service/endpoint to Copy Engine.
224 * This table is derived from the CE_PCI TABLE, above.
225 * It is passed to the Target at startup for use by firmware.
227 static const struct service_to_pipe target_service_to_ce_map_wlan
[] = {
229 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO
),
230 __cpu_to_le32(PIPEDIR_OUT
), /* out = UL = host -> target */
234 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO
),
235 __cpu_to_le32(PIPEDIR_IN
), /* in = DL = target -> host */
239 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK
),
240 __cpu_to_le32(PIPEDIR_OUT
), /* out = UL = host -> target */
244 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK
),
245 __cpu_to_le32(PIPEDIR_IN
), /* in = DL = target -> host */
249 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE
),
250 __cpu_to_le32(PIPEDIR_OUT
), /* out = UL = host -> target */
254 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE
),
255 __cpu_to_le32(PIPEDIR_IN
), /* in = DL = target -> host */
259 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI
),
260 __cpu_to_le32(PIPEDIR_OUT
), /* out = UL = host -> target */
264 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI
),
265 __cpu_to_le32(PIPEDIR_IN
), /* in = DL = target -> host */
269 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL
),
270 __cpu_to_le32(PIPEDIR_OUT
), /* out = UL = host -> target */
274 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL
),
275 __cpu_to_le32(PIPEDIR_IN
), /* in = DL = target -> host */
279 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL
),
280 __cpu_to_le32(PIPEDIR_OUT
), /* out = UL = host -> target */
284 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL
),
285 __cpu_to_le32(PIPEDIR_IN
), /* in = DL = target -> host */
289 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS
),
290 __cpu_to_le32(PIPEDIR_OUT
), /* out = UL = host -> target */
294 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS
),
295 __cpu_to_le32(PIPEDIR_IN
), /* in = DL = target -> host */
299 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG
),
300 __cpu_to_le32(PIPEDIR_OUT
), /* out = UL = host -> target */
304 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG
),
305 __cpu_to_le32(PIPEDIR_IN
), /* in = DL = target -> host */
309 /* (Additions here) */
318 static bool ath10k_pci_irq_pending(struct ath10k
*ar
)
322 /* Check if the shared legacy irq is for us */
323 cause
= ath10k_pci_read32(ar
, SOC_CORE_BASE_ADDRESS
+
324 PCIE_INTR_CAUSE_ADDRESS
);
325 if (cause
& (PCIE_INTR_FIRMWARE_MASK
| PCIE_INTR_CE_MASK_ALL
))
331 static void ath10k_pci_disable_and_clear_legacy_irq(struct ath10k
*ar
)
333 /* IMPORTANT: INTR_CLR register has to be set after
334 * INTR_ENABLE is set to 0, otherwise interrupt can not be
336 ath10k_pci_write32(ar
, SOC_CORE_BASE_ADDRESS
+ PCIE_INTR_ENABLE_ADDRESS
,
338 ath10k_pci_write32(ar
, SOC_CORE_BASE_ADDRESS
+ PCIE_INTR_CLR_ADDRESS
,
339 PCIE_INTR_FIRMWARE_MASK
| PCIE_INTR_CE_MASK_ALL
);
341 /* IMPORTANT: this extra read transaction is required to
342 * flush the posted write buffer. */
343 (void)ath10k_pci_read32(ar
, SOC_CORE_BASE_ADDRESS
+
344 PCIE_INTR_ENABLE_ADDRESS
);
347 static void ath10k_pci_enable_legacy_irq(struct ath10k
*ar
)
349 ath10k_pci_write32(ar
, SOC_CORE_BASE_ADDRESS
+
350 PCIE_INTR_ENABLE_ADDRESS
,
351 PCIE_INTR_FIRMWARE_MASK
| PCIE_INTR_CE_MASK_ALL
);
353 /* IMPORTANT: this extra read transaction is required to
354 * flush the posted write buffer. */
355 (void)ath10k_pci_read32(ar
, SOC_CORE_BASE_ADDRESS
+
356 PCIE_INTR_ENABLE_ADDRESS
);
359 static inline const char *ath10k_pci_get_irq_method(struct ath10k
*ar
)
361 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
363 if (ar_pci
->num_msi_intrs
> 1)
366 if (ar_pci
->num_msi_intrs
== 1)
372 static int __ath10k_pci_rx_post_buf(struct ath10k_pci_pipe
*pipe
)
374 struct ath10k
*ar
= pipe
->hif_ce_state
;
375 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
376 struct ath10k_ce_pipe
*ce_pipe
= pipe
->ce_hdl
;
381 lockdep_assert_held(&ar_pci
->ce_lock
);
383 skb
= dev_alloc_skb(pipe
->buf_sz
);
387 WARN_ONCE((unsigned long)skb
->data
& 3, "unaligned skb");
389 paddr
= dma_map_single(ar
->dev
, skb
->data
,
390 skb
->len
+ skb_tailroom(skb
),
392 if (unlikely(dma_mapping_error(ar
->dev
, paddr
))) {
393 ath10k_warn(ar
, "failed to dma map pci rx buf\n");
394 dev_kfree_skb_any(skb
);
398 ATH10K_SKB_CB(skb
)->paddr
= paddr
;
400 ret
= __ath10k_ce_rx_post_buf(ce_pipe
, skb
, paddr
);
402 ath10k_warn(ar
, "failed to post pci rx buf: %d\n", ret
);
403 dma_unmap_single(ar
->dev
, paddr
, skb
->len
+ skb_tailroom(skb
),
405 dev_kfree_skb_any(skb
);
412 static void __ath10k_pci_rx_post_pipe(struct ath10k_pci_pipe
*pipe
)
414 struct ath10k
*ar
= pipe
->hif_ce_state
;
415 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
416 struct ath10k_ce_pipe
*ce_pipe
= pipe
->ce_hdl
;
419 lockdep_assert_held(&ar_pci
->ce_lock
);
421 if (pipe
->buf_sz
== 0)
424 if (!ce_pipe
->dest_ring
)
427 num
= __ath10k_ce_rx_num_free_bufs(ce_pipe
);
429 ret
= __ath10k_pci_rx_post_buf(pipe
);
431 ath10k_warn(ar
, "failed to post pci rx buf: %d\n", ret
);
432 mod_timer(&ar_pci
->rx_post_retry
, jiffies
+
433 ATH10K_PCI_RX_POST_RETRY_MS
);
439 static void ath10k_pci_rx_post_pipe(struct ath10k_pci_pipe
*pipe
)
441 struct ath10k
*ar
= pipe
->hif_ce_state
;
442 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
444 spin_lock_bh(&ar_pci
->ce_lock
);
445 __ath10k_pci_rx_post_pipe(pipe
);
446 spin_unlock_bh(&ar_pci
->ce_lock
);
449 static void ath10k_pci_rx_post(struct ath10k
*ar
)
451 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
454 spin_lock_bh(&ar_pci
->ce_lock
);
455 for (i
= 0; i
< CE_COUNT
; i
++)
456 __ath10k_pci_rx_post_pipe(&ar_pci
->pipe_info
[i
]);
457 spin_unlock_bh(&ar_pci
->ce_lock
);
460 static void ath10k_pci_rx_replenish_retry(unsigned long ptr
)
462 struct ath10k
*ar
= (void *)ptr
;
464 ath10k_pci_rx_post(ar
);
468 * Diagnostic read/write access is provided for startup/config/debug usage.
469 * Caller must guarantee proper alignment, when applicable, and single user
472 static int ath10k_pci_diag_read_mem(struct ath10k
*ar
, u32 address
, void *data
,
475 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
478 unsigned int completed_nbytes
, orig_nbytes
, remaining_bytes
;
481 struct ath10k_ce_pipe
*ce_diag
;
482 /* Host buffer address in CE space */
484 dma_addr_t ce_data_base
= 0;
485 void *data_buf
= NULL
;
488 spin_lock_bh(&ar_pci
->ce_lock
);
490 ce_diag
= ar_pci
->ce_diag
;
493 * Allocate a temporary bounce buffer to hold caller's data
494 * to be DMA'ed from Target. This guarantees
495 * 1) 4-byte alignment
496 * 2) Buffer in DMA-able space
498 orig_nbytes
= nbytes
;
499 data_buf
= (unsigned char *)dma_alloc_coherent(ar
->dev
,
508 memset(data_buf
, 0, orig_nbytes
);
510 remaining_bytes
= orig_nbytes
;
511 ce_data
= ce_data_base
;
512 while (remaining_bytes
) {
513 nbytes
= min_t(unsigned int, remaining_bytes
,
514 DIAG_TRANSFER_LIMIT
);
516 ret
= __ath10k_ce_rx_post_buf(ce_diag
, NULL
, ce_data
);
520 /* Request CE to send from Target(!) address to Host buffer */
522 * The address supplied by the caller is in the
523 * Target CPU virtual address space.
525 * In order to use this address with the diagnostic CE,
526 * convert it from Target CPU virtual address space
527 * to CE address space
529 address
= TARG_CPU_SPACE_TO_CE_SPACE(ar
, ar_pci
->mem
,
532 ret
= ath10k_ce_send_nolock(ce_diag
, NULL
, (u32
)address
, nbytes
, 0,
538 while (ath10k_ce_completed_send_next_nolock(ce_diag
, NULL
, &buf
,
542 if (i
++ > DIAG_ACCESS_CE_TIMEOUT_MS
) {
548 if (nbytes
!= completed_nbytes
) {
553 if (buf
!= (u32
)address
) {
559 while (ath10k_ce_completed_recv_next_nolock(ce_diag
, NULL
, &buf
,
564 if (i
++ > DIAG_ACCESS_CE_TIMEOUT_MS
) {
570 if (nbytes
!= completed_nbytes
) {
575 if (buf
!= ce_data
) {
580 remaining_bytes
-= nbytes
;
587 memcpy(data
, data_buf
, orig_nbytes
);
589 ath10k_warn(ar
, "failed to read diag value at 0x%x: %d\n",
593 dma_free_coherent(ar
->dev
, orig_nbytes
, data_buf
,
596 spin_unlock_bh(&ar_pci
->ce_lock
);
601 static int ath10k_pci_diag_read32(struct ath10k
*ar
, u32 address
, u32
*value
)
606 ret
= ath10k_pci_diag_read_mem(ar
, address
, &val
, sizeof(val
));
607 *value
= __le32_to_cpu(val
);
612 static int __ath10k_pci_diag_read_hi(struct ath10k
*ar
, void *dest
,
618 host_addr
= host_interest_item_address(src
);
620 ret
= ath10k_pci_diag_read32(ar
, host_addr
, &addr
);
622 ath10k_warn(ar
, "failed to get memcpy hi address for firmware address %d: %d\n",
627 ret
= ath10k_pci_diag_read_mem(ar
, addr
, dest
, len
);
629 ath10k_warn(ar
, "failed to memcpy firmware memory from %d (%d B): %d\n",
637 #define ath10k_pci_diag_read_hi(ar, dest, src, len) \
638 __ath10k_pci_diag_read_hi(ar, dest, HI_ITEM(src), len)
640 static int ath10k_pci_diag_write_mem(struct ath10k
*ar
, u32 address
,
641 const void *data
, int nbytes
)
643 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
646 unsigned int completed_nbytes
, orig_nbytes
, remaining_bytes
;
649 struct ath10k_ce_pipe
*ce_diag
;
650 void *data_buf
= NULL
;
651 u32 ce_data
; /* Host buffer address in CE space */
652 dma_addr_t ce_data_base
= 0;
655 spin_lock_bh(&ar_pci
->ce_lock
);
657 ce_diag
= ar_pci
->ce_diag
;
660 * Allocate a temporary bounce buffer to hold caller's data
661 * to be DMA'ed to Target. This guarantees
662 * 1) 4-byte alignment
663 * 2) Buffer in DMA-able space
665 orig_nbytes
= nbytes
;
666 data_buf
= (unsigned char *)dma_alloc_coherent(ar
->dev
,
675 /* Copy caller's data to allocated DMA buf */
676 memcpy(data_buf
, data
, orig_nbytes
);
679 * The address supplied by the caller is in the
680 * Target CPU virtual address space.
682 * In order to use this address with the diagnostic CE,
684 * Target CPU virtual address space
688 address
= TARG_CPU_SPACE_TO_CE_SPACE(ar
, ar_pci
->mem
, address
);
690 remaining_bytes
= orig_nbytes
;
691 ce_data
= ce_data_base
;
692 while (remaining_bytes
) {
693 /* FIXME: check cast */
694 nbytes
= min_t(int, remaining_bytes
, DIAG_TRANSFER_LIMIT
);
696 /* Set up to receive directly into Target(!) address */
697 ret
= __ath10k_ce_rx_post_buf(ce_diag
, NULL
, address
);
702 * Request CE to send caller-supplied data that
703 * was copied to bounce buffer to Target(!) address.
705 ret
= ath10k_ce_send_nolock(ce_diag
, NULL
, (u32
)ce_data
,
711 while (ath10k_ce_completed_send_next_nolock(ce_diag
, NULL
, &buf
,
716 if (i
++ > DIAG_ACCESS_CE_TIMEOUT_MS
) {
722 if (nbytes
!= completed_nbytes
) {
727 if (buf
!= ce_data
) {
733 while (ath10k_ce_completed_recv_next_nolock(ce_diag
, NULL
, &buf
,
738 if (i
++ > DIAG_ACCESS_CE_TIMEOUT_MS
) {
744 if (nbytes
!= completed_nbytes
) {
749 if (buf
!= address
) {
754 remaining_bytes
-= nbytes
;
761 dma_free_coherent(ar
->dev
, orig_nbytes
, data_buf
,
766 ath10k_warn(ar
, "failed to write diag value at 0x%x: %d\n",
769 spin_unlock_bh(&ar_pci
->ce_lock
);
774 static int ath10k_pci_diag_write32(struct ath10k
*ar
, u32 address
, u32 value
)
776 __le32 val
= __cpu_to_le32(value
);
778 return ath10k_pci_diag_write_mem(ar
, address
, &val
, sizeof(val
));
781 static bool ath10k_pci_is_awake(struct ath10k
*ar
)
783 u32 val
= ath10k_pci_reg_read32(ar
, RTC_STATE_ADDRESS
);
785 return RTC_STATE_V_GET(val
) == RTC_STATE_V_ON
;
788 static int ath10k_pci_wake_wait(struct ath10k
*ar
)
793 while (tot_delay
< PCIE_WAKE_TIMEOUT
) {
794 if (ath10k_pci_is_awake(ar
))
798 tot_delay
+= curr_delay
;
807 static int ath10k_pci_wake(struct ath10k
*ar
)
809 ath10k_pci_reg_write32(ar
, PCIE_SOC_WAKE_ADDRESS
,
810 PCIE_SOC_WAKE_V_MASK
);
811 return ath10k_pci_wake_wait(ar
);
814 static void ath10k_pci_sleep(struct ath10k
*ar
)
816 ath10k_pci_reg_write32(ar
, PCIE_SOC_WAKE_ADDRESS
,
817 PCIE_SOC_WAKE_RESET
);
820 /* Called by lower (CE) layer when a send to Target completes. */
821 static void ath10k_pci_ce_send_done(struct ath10k_ce_pipe
*ce_state
)
823 struct ath10k
*ar
= ce_state
->ar
;
824 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
825 struct ath10k_hif_cb
*cb
= &ar_pci
->msg_callbacks_current
;
826 struct sk_buff_head list
;
830 unsigned int transfer_id
;
832 __skb_queue_head_init(&list
);
833 while (ath10k_ce_completed_send_next(ce_state
, (void **)&skb
, &ce_data
,
834 &nbytes
, &transfer_id
) == 0) {
835 /* no need to call tx completion for NULL pointers */
839 __skb_queue_tail(&list
, skb
);
842 while ((skb
= __skb_dequeue(&list
)))
843 cb
->tx_completion(ar
, skb
);
846 /* Called by lower (CE) layer when data is received from the Target. */
847 static void ath10k_pci_ce_recv_data(struct ath10k_ce_pipe
*ce_state
)
849 struct ath10k
*ar
= ce_state
->ar
;
850 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
851 struct ath10k_pci_pipe
*pipe_info
= &ar_pci
->pipe_info
[ce_state
->id
];
852 struct ath10k_hif_cb
*cb
= &ar_pci
->msg_callbacks_current
;
854 struct sk_buff_head list
;
855 void *transfer_context
;
857 unsigned int nbytes
, max_nbytes
;
858 unsigned int transfer_id
;
861 __skb_queue_head_init(&list
);
862 while (ath10k_ce_completed_recv_next(ce_state
, &transfer_context
,
863 &ce_data
, &nbytes
, &transfer_id
,
865 skb
= transfer_context
;
866 max_nbytes
= skb
->len
+ skb_tailroom(skb
);
867 dma_unmap_single(ar
->dev
, ATH10K_SKB_CB(skb
)->paddr
,
868 max_nbytes
, DMA_FROM_DEVICE
);
870 if (unlikely(max_nbytes
< nbytes
)) {
871 ath10k_warn(ar
, "rxed more than expected (nbytes %d, max %d)",
873 dev_kfree_skb_any(skb
);
877 skb_put(skb
, nbytes
);
878 __skb_queue_tail(&list
, skb
);
881 while ((skb
= __skb_dequeue(&list
))) {
882 ath10k_dbg(ar
, ATH10K_DBG_PCI
, "pci rx ce pipe %d len %d\n",
883 ce_state
->id
, skb
->len
);
884 ath10k_dbg_dump(ar
, ATH10K_DBG_PCI_DUMP
, NULL
, "pci rx: ",
885 skb
->data
, skb
->len
);
887 cb
->rx_completion(ar
, skb
);
890 ath10k_pci_rx_post_pipe(pipe_info
);
893 static int ath10k_pci_hif_tx_sg(struct ath10k
*ar
, u8 pipe_id
,
894 struct ath10k_hif_sg_item
*items
, int n_items
)
896 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
897 struct ath10k_pci_pipe
*pci_pipe
= &ar_pci
->pipe_info
[pipe_id
];
898 struct ath10k_ce_pipe
*ce_pipe
= pci_pipe
->ce_hdl
;
899 struct ath10k_ce_ring
*src_ring
= ce_pipe
->src_ring
;
900 unsigned int nentries_mask
;
901 unsigned int sw_index
;
902 unsigned int write_index
;
905 spin_lock_bh(&ar_pci
->ce_lock
);
907 nentries_mask
= src_ring
->nentries_mask
;
908 sw_index
= src_ring
->sw_index
;
909 write_index
= src_ring
->write_index
;
911 if (unlikely(CE_RING_DELTA(nentries_mask
,
912 write_index
, sw_index
- 1) < n_items
)) {
917 for (i
= 0; i
< n_items
- 1; i
++) {
918 ath10k_dbg(ar
, ATH10K_DBG_PCI
,
919 "pci tx item %d paddr 0x%08x len %d n_items %d\n",
920 i
, items
[i
].paddr
, items
[i
].len
, n_items
);
921 ath10k_dbg_dump(ar
, ATH10K_DBG_PCI_DUMP
, NULL
, "pci tx data: ",
922 items
[i
].vaddr
, items
[i
].len
);
924 err
= ath10k_ce_send_nolock(ce_pipe
,
925 items
[i
].transfer_context
,
928 items
[i
].transfer_id
,
929 CE_SEND_FLAG_GATHER
);
934 /* `i` is equal to `n_items -1` after for() */
936 ath10k_dbg(ar
, ATH10K_DBG_PCI
,
937 "pci tx item %d paddr 0x%08x len %d n_items %d\n",
938 i
, items
[i
].paddr
, items
[i
].len
, n_items
);
939 ath10k_dbg_dump(ar
, ATH10K_DBG_PCI_DUMP
, NULL
, "pci tx data: ",
940 items
[i
].vaddr
, items
[i
].len
);
942 err
= ath10k_ce_send_nolock(ce_pipe
,
943 items
[i
].transfer_context
,
946 items
[i
].transfer_id
,
951 spin_unlock_bh(&ar_pci
->ce_lock
);
956 __ath10k_ce_send_revert(ce_pipe
);
958 spin_unlock_bh(&ar_pci
->ce_lock
);
962 static int ath10k_pci_hif_diag_read(struct ath10k
*ar
, u32 address
, void *buf
,
965 return ath10k_pci_diag_read_mem(ar
, address
, buf
, buf_len
);
968 static u16
ath10k_pci_hif_get_free_queue_number(struct ath10k
*ar
, u8 pipe
)
970 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
972 ath10k_dbg(ar
, ATH10K_DBG_PCI
, "pci hif get free queue number\n");
974 return ath10k_ce_num_free_src_entries(ar_pci
->pipe_info
[pipe
].ce_hdl
);
977 static void ath10k_pci_dump_registers(struct ath10k
*ar
,
978 struct ath10k_fw_crash_data
*crash_data
)
980 __le32 reg_dump_values
[REG_DUMP_COUNT_QCA988X
] = {};
983 lockdep_assert_held(&ar
->data_lock
);
985 ret
= ath10k_pci_diag_read_hi(ar
, ®_dump_values
[0],
987 REG_DUMP_COUNT_QCA988X
* sizeof(__le32
));
989 ath10k_err(ar
, "failed to read firmware dump area: %d\n", ret
);
993 BUILD_BUG_ON(REG_DUMP_COUNT_QCA988X
% 4);
995 ath10k_err(ar
, "firmware register dump:\n");
996 for (i
= 0; i
< REG_DUMP_COUNT_QCA988X
; i
+= 4)
997 ath10k_err(ar
, "[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X\n",
999 __le32_to_cpu(reg_dump_values
[i
]),
1000 __le32_to_cpu(reg_dump_values
[i
+ 1]),
1001 __le32_to_cpu(reg_dump_values
[i
+ 2]),
1002 __le32_to_cpu(reg_dump_values
[i
+ 3]));
1007 for (i
= 0; i
< REG_DUMP_COUNT_QCA988X
; i
++)
1008 crash_data
->registers
[i
] = reg_dump_values
[i
];
1011 static void ath10k_pci_fw_crashed_dump(struct ath10k
*ar
)
1013 struct ath10k_fw_crash_data
*crash_data
;
1016 spin_lock_bh(&ar
->data_lock
);
1018 ar
->stats
.fw_crash_counter
++;
1020 crash_data
= ath10k_debug_get_new_fw_crash_data(ar
);
1023 scnprintf(uuid
, sizeof(uuid
), "%pUl", &crash_data
->uuid
);
1025 scnprintf(uuid
, sizeof(uuid
), "n/a");
1027 ath10k_err(ar
, "firmware crashed! (uuid %s)\n", uuid
);
1028 ath10k_print_driver_info(ar
);
1029 ath10k_pci_dump_registers(ar
, crash_data
);
1031 spin_unlock_bh(&ar
->data_lock
);
1033 queue_work(ar
->workqueue
, &ar
->restart_work
);
1036 static void ath10k_pci_hif_send_complete_check(struct ath10k
*ar
, u8 pipe
,
1039 ath10k_dbg(ar
, ATH10K_DBG_PCI
, "pci hif send complete check\n");
1044 * Decide whether to actually poll for completions, or just
1045 * wait for a later chance.
1046 * If there seem to be plenty of resources left, then just wait
1047 * since checking involves reading a CE register, which is a
1048 * relatively expensive operation.
1050 resources
= ath10k_pci_hif_get_free_queue_number(ar
, pipe
);
1053 * If at least 50% of the total resources are still available,
1054 * don't bother checking again yet.
1056 if (resources
> (host_ce_config_wlan
[pipe
].src_nentries
>> 1))
1059 ath10k_ce_per_engine_service(ar
, pipe
);
1062 static void ath10k_pci_hif_set_callbacks(struct ath10k
*ar
,
1063 struct ath10k_hif_cb
*callbacks
)
1065 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
1067 ath10k_dbg(ar
, ATH10K_DBG_PCI
, "pci hif set callbacks\n");
1069 memcpy(&ar_pci
->msg_callbacks_current
, callbacks
,
1070 sizeof(ar_pci
->msg_callbacks_current
));
1073 static void ath10k_pci_kill_tasklet(struct ath10k
*ar
)
1075 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
1078 tasklet_kill(&ar_pci
->intr_tq
);
1079 tasklet_kill(&ar_pci
->msi_fw_err
);
1081 for (i
= 0; i
< CE_COUNT
; i
++)
1082 tasklet_kill(&ar_pci
->pipe_info
[i
].intr
);
1084 del_timer_sync(&ar_pci
->rx_post_retry
);
1087 static int ath10k_pci_hif_map_service_to_pipe(struct ath10k
*ar
,
1088 u16 service_id
, u8
*ul_pipe
,
1089 u8
*dl_pipe
, int *ul_is_polled
,
1092 const struct service_to_pipe
*entry
;
1093 bool ul_set
= false, dl_set
= false;
1096 ath10k_dbg(ar
, ATH10K_DBG_PCI
, "pci hif map service\n");
1098 /* polling for received messages not supported */
1101 for (i
= 0; i
< ARRAY_SIZE(target_service_to_ce_map_wlan
); i
++) {
1102 entry
= &target_service_to_ce_map_wlan
[i
];
1104 if (__le32_to_cpu(entry
->service_id
) != service_id
)
1107 switch (__le32_to_cpu(entry
->pipedir
)) {
1112 *dl_pipe
= __le32_to_cpu(entry
->pipenum
);
1117 *ul_pipe
= __le32_to_cpu(entry
->pipenum
);
1123 *dl_pipe
= __le32_to_cpu(entry
->pipenum
);
1124 *ul_pipe
= __le32_to_cpu(entry
->pipenum
);
1131 if (WARN_ON(!ul_set
|| !dl_set
))
1135 (host_ce_config_wlan
[*ul_pipe
].flags
& CE_ATTR_DIS_INTR
) != 0;
1140 static void ath10k_pci_hif_get_default_pipe(struct ath10k
*ar
,
1141 u8
*ul_pipe
, u8
*dl_pipe
)
1143 int ul_is_polled
, dl_is_polled
;
1145 ath10k_dbg(ar
, ATH10K_DBG_PCI
, "pci hif get default pipe\n");
1147 (void)ath10k_pci_hif_map_service_to_pipe(ar
,
1148 ATH10K_HTC_SVC_ID_RSVD_CTRL
,
1155 static void ath10k_pci_irq_msi_fw_mask(struct ath10k
*ar
)
1159 val
= ath10k_pci_read32(ar
, SOC_CORE_BASE_ADDRESS
+ CORE_CTRL_ADDRESS
);
1160 val
&= ~CORE_CTRL_PCIE_REG_31_MASK
;
1162 ath10k_pci_write32(ar
, SOC_CORE_BASE_ADDRESS
+ CORE_CTRL_ADDRESS
, val
);
1165 static void ath10k_pci_irq_msi_fw_unmask(struct ath10k
*ar
)
1169 val
= ath10k_pci_read32(ar
, SOC_CORE_BASE_ADDRESS
+ CORE_CTRL_ADDRESS
);
1170 val
|= CORE_CTRL_PCIE_REG_31_MASK
;
1172 ath10k_pci_write32(ar
, SOC_CORE_BASE_ADDRESS
+ CORE_CTRL_ADDRESS
, val
);
1175 static void ath10k_pci_irq_disable(struct ath10k
*ar
)
1177 ath10k_ce_disable_interrupts(ar
);
1178 ath10k_pci_disable_and_clear_legacy_irq(ar
);
1179 ath10k_pci_irq_msi_fw_mask(ar
);
1182 static void ath10k_pci_irq_sync(struct ath10k
*ar
)
1184 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
1187 for (i
= 0; i
< max(1, ar_pci
->num_msi_intrs
); i
++)
1188 synchronize_irq(ar_pci
->pdev
->irq
+ i
);
1191 static void ath10k_pci_irq_enable(struct ath10k
*ar
)
1193 ath10k_ce_enable_interrupts(ar
);
1194 ath10k_pci_enable_legacy_irq(ar
);
1195 ath10k_pci_irq_msi_fw_unmask(ar
);
1198 static int ath10k_pci_hif_start(struct ath10k
*ar
)
1200 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot hif start\n");
1202 ath10k_pci_irq_enable(ar
);
1203 ath10k_pci_rx_post(ar
);
1208 static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe
*pci_pipe
)
1211 struct ath10k_ce_pipe
*ce_pipe
;
1212 struct ath10k_ce_ring
*ce_ring
;
1213 struct sk_buff
*skb
;
1216 ar
= pci_pipe
->hif_ce_state
;
1217 ce_pipe
= pci_pipe
->ce_hdl
;
1218 ce_ring
= ce_pipe
->dest_ring
;
1223 if (!pci_pipe
->buf_sz
)
1226 for (i
= 0; i
< ce_ring
->nentries
; i
++) {
1227 skb
= ce_ring
->per_transfer_context
[i
];
1231 ce_ring
->per_transfer_context
[i
] = NULL
;
1233 dma_unmap_single(ar
->dev
, ATH10K_SKB_CB(skb
)->paddr
,
1234 skb
->len
+ skb_tailroom(skb
),
1236 dev_kfree_skb_any(skb
);
1240 static void ath10k_pci_tx_pipe_cleanup(struct ath10k_pci_pipe
*pci_pipe
)
1243 struct ath10k_pci
*ar_pci
;
1244 struct ath10k_ce_pipe
*ce_pipe
;
1245 struct ath10k_ce_ring
*ce_ring
;
1246 struct ce_desc
*ce_desc
;
1247 struct sk_buff
*skb
;
1251 ar
= pci_pipe
->hif_ce_state
;
1252 ar_pci
= ath10k_pci_priv(ar
);
1253 ce_pipe
= pci_pipe
->ce_hdl
;
1254 ce_ring
= ce_pipe
->src_ring
;
1259 if (!pci_pipe
->buf_sz
)
1262 ce_desc
= ce_ring
->shadow_base
;
1263 if (WARN_ON(!ce_desc
))
1266 for (i
= 0; i
< ce_ring
->nentries
; i
++) {
1267 skb
= ce_ring
->per_transfer_context
[i
];
1271 ce_ring
->per_transfer_context
[i
] = NULL
;
1272 id
= MS(__le16_to_cpu(ce_desc
[i
].flags
),
1273 CE_DESC_FLAGS_META_DATA
);
1275 ar_pci
->msg_callbacks_current
.tx_completion(ar
, skb
);
1280 * Cleanup residual buffers for device shutdown:
1281 * buffers that were enqueued for receive
1282 * buffers that were to be sent
1283 * Note: Buffers that had completed but which were
1284 * not yet processed are on a completion queue. They
1285 * are handled when the completion thread shuts down.
1287 static void ath10k_pci_buffer_cleanup(struct ath10k
*ar
)
1289 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
1292 for (pipe_num
= 0; pipe_num
< CE_COUNT
; pipe_num
++) {
1293 struct ath10k_pci_pipe
*pipe_info
;
1295 pipe_info
= &ar_pci
->pipe_info
[pipe_num
];
1296 ath10k_pci_rx_pipe_cleanup(pipe_info
);
1297 ath10k_pci_tx_pipe_cleanup(pipe_info
);
1301 static void ath10k_pci_ce_deinit(struct ath10k
*ar
)
1305 for (i
= 0; i
< CE_COUNT
; i
++)
1306 ath10k_ce_deinit_pipe(ar
, i
);
1309 static void ath10k_pci_flush(struct ath10k
*ar
)
1311 ath10k_pci_kill_tasklet(ar
);
1312 ath10k_pci_buffer_cleanup(ar
);
1315 static void ath10k_pci_hif_stop(struct ath10k
*ar
)
1317 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot hif stop\n");
1319 /* Most likely the device has HTT Rx ring configured. The only way to
1320 * prevent the device from accessing (and possible corrupting) host
1321 * memory is to reset the chip now.
1323 * There's also no known way of masking MSI interrupts on the device.
1324 * For ranged MSI the CE-related interrupts can be masked. However
1325 * regardless how many MSI interrupts are assigned the first one
1326 * is always used for firmware indications (crashes) and cannot be
1327 * masked. To prevent the device from asserting the interrupt reset it
1328 * before proceeding with cleanup.
1330 ath10k_pci_warm_reset(ar
);
1332 ath10k_pci_irq_disable(ar
);
1333 ath10k_pci_irq_sync(ar
);
1334 ath10k_pci_flush(ar
);
1337 static int ath10k_pci_hif_exchange_bmi_msg(struct ath10k
*ar
,
1338 void *req
, u32 req_len
,
1339 void *resp
, u32
*resp_len
)
1341 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
1342 struct ath10k_pci_pipe
*pci_tx
= &ar_pci
->pipe_info
[BMI_CE_NUM_TO_TARG
];
1343 struct ath10k_pci_pipe
*pci_rx
= &ar_pci
->pipe_info
[BMI_CE_NUM_TO_HOST
];
1344 struct ath10k_ce_pipe
*ce_tx
= pci_tx
->ce_hdl
;
1345 struct ath10k_ce_pipe
*ce_rx
= pci_rx
->ce_hdl
;
1346 dma_addr_t req_paddr
= 0;
1347 dma_addr_t resp_paddr
= 0;
1348 struct bmi_xfer xfer
= {};
1349 void *treq
, *tresp
= NULL
;
1354 if (resp
&& !resp_len
)
1357 if (resp
&& resp_len
&& *resp_len
== 0)
1360 treq
= kmemdup(req
, req_len
, GFP_KERNEL
);
1364 req_paddr
= dma_map_single(ar
->dev
, treq
, req_len
, DMA_TO_DEVICE
);
1365 ret
= dma_mapping_error(ar
->dev
, req_paddr
);
1369 if (resp
&& resp_len
) {
1370 tresp
= kzalloc(*resp_len
, GFP_KERNEL
);
1376 resp_paddr
= dma_map_single(ar
->dev
, tresp
, *resp_len
,
1378 ret
= dma_mapping_error(ar
->dev
, resp_paddr
);
1382 xfer
.wait_for_resp
= true;
1385 ath10k_ce_rx_post_buf(ce_rx
, &xfer
, resp_paddr
);
1388 ret
= ath10k_ce_send(ce_tx
, &xfer
, req_paddr
, req_len
, -1, 0);
1392 ret
= ath10k_pci_bmi_wait(ce_tx
, ce_rx
, &xfer
);
1395 unsigned int unused_nbytes
;
1396 unsigned int unused_id
;
1398 ath10k_ce_cancel_send_next(ce_tx
, NULL
, &unused_buffer
,
1399 &unused_nbytes
, &unused_id
);
1401 /* non-zero means we did not time out */
1409 ath10k_ce_revoke_recv_next(ce_rx
, NULL
, &unused_buffer
);
1410 dma_unmap_single(ar
->dev
, resp_paddr
,
1411 *resp_len
, DMA_FROM_DEVICE
);
1414 dma_unmap_single(ar
->dev
, req_paddr
, req_len
, DMA_TO_DEVICE
);
1416 if (ret
== 0 && resp_len
) {
1417 *resp_len
= min(*resp_len
, xfer
.resp_len
);
1418 memcpy(resp
, tresp
, xfer
.resp_len
);
1427 static void ath10k_pci_bmi_send_done(struct ath10k_ce_pipe
*ce_state
)
1429 struct bmi_xfer
*xfer
;
1431 unsigned int nbytes
;
1432 unsigned int transfer_id
;
1434 if (ath10k_ce_completed_send_next(ce_state
, (void **)&xfer
, &ce_data
,
1435 &nbytes
, &transfer_id
))
1438 xfer
->tx_done
= true;
1441 static void ath10k_pci_bmi_recv_data(struct ath10k_ce_pipe
*ce_state
)
1443 struct ath10k
*ar
= ce_state
->ar
;
1444 struct bmi_xfer
*xfer
;
1446 unsigned int nbytes
;
1447 unsigned int transfer_id
;
1450 if (ath10k_ce_completed_recv_next(ce_state
, (void **)&xfer
, &ce_data
,
1451 &nbytes
, &transfer_id
, &flags
))
1454 if (WARN_ON_ONCE(!xfer
))
1457 if (!xfer
->wait_for_resp
) {
1458 ath10k_warn(ar
, "unexpected: BMI data received; ignoring\n");
1462 xfer
->resp_len
= nbytes
;
1463 xfer
->rx_done
= true;
1466 static int ath10k_pci_bmi_wait(struct ath10k_ce_pipe
*tx_pipe
,
1467 struct ath10k_ce_pipe
*rx_pipe
,
1468 struct bmi_xfer
*xfer
)
1470 unsigned long timeout
= jiffies
+ BMI_COMMUNICATION_TIMEOUT_HZ
;
1472 while (time_before_eq(jiffies
, timeout
)) {
1473 ath10k_pci_bmi_send_done(tx_pipe
);
1474 ath10k_pci_bmi_recv_data(rx_pipe
);
1476 if (xfer
->tx_done
&& (xfer
->rx_done
== xfer
->wait_for_resp
))
1486 * Send an interrupt to the device to wake up the Target CPU
1487 * so it has an opportunity to notice any changed state.
1489 static int ath10k_pci_wake_target_cpu(struct ath10k
*ar
)
1493 addr
= SOC_CORE_BASE_ADDRESS
| CORE_CTRL_ADDRESS
;
1494 val
= ath10k_pci_read32(ar
, addr
);
1495 val
|= CORE_CTRL_CPU_INTR_MASK
;
1496 ath10k_pci_write32(ar
, addr
, val
);
1501 static int ath10k_pci_init_config(struct ath10k
*ar
)
1503 u32 interconnect_targ_addr
;
1504 u32 pcie_state_targ_addr
= 0;
1505 u32 pipe_cfg_targ_addr
= 0;
1506 u32 svc_to_pipe_map
= 0;
1507 u32 pcie_config_flags
= 0;
1509 u32 ealloc_targ_addr
;
1511 u32 flag2_targ_addr
;
1514 /* Download to Target the CE Config and the service-to-CE map */
1515 interconnect_targ_addr
=
1516 host_interest_item_address(HI_ITEM(hi_interconnect_state
));
1518 /* Supply Target-side CE configuration */
1519 ret
= ath10k_pci_diag_read32(ar
, interconnect_targ_addr
,
1520 &pcie_state_targ_addr
);
1522 ath10k_err(ar
, "Failed to get pcie state addr: %d\n", ret
);
1526 if (pcie_state_targ_addr
== 0) {
1528 ath10k_err(ar
, "Invalid pcie state addr\n");
1532 ret
= ath10k_pci_diag_read32(ar
, (pcie_state_targ_addr
+
1533 offsetof(struct pcie_state
,
1535 &pipe_cfg_targ_addr
);
1537 ath10k_err(ar
, "Failed to get pipe cfg addr: %d\n", ret
);
1541 if (pipe_cfg_targ_addr
== 0) {
1543 ath10k_err(ar
, "Invalid pipe cfg addr\n");
1547 ret
= ath10k_pci_diag_write_mem(ar
, pipe_cfg_targ_addr
,
1548 target_ce_config_wlan
,
1549 sizeof(target_ce_config_wlan
));
1552 ath10k_err(ar
, "Failed to write pipe cfg: %d\n", ret
);
1556 ret
= ath10k_pci_diag_read32(ar
, (pcie_state_targ_addr
+
1557 offsetof(struct pcie_state
,
1561 ath10k_err(ar
, "Failed to get svc/pipe map: %d\n", ret
);
1565 if (svc_to_pipe_map
== 0) {
1567 ath10k_err(ar
, "Invalid svc_to_pipe map\n");
1571 ret
= ath10k_pci_diag_write_mem(ar
, svc_to_pipe_map
,
1572 target_service_to_ce_map_wlan
,
1573 sizeof(target_service_to_ce_map_wlan
));
1575 ath10k_err(ar
, "Failed to write svc/pipe map: %d\n", ret
);
1579 ret
= ath10k_pci_diag_read32(ar
, (pcie_state_targ_addr
+
1580 offsetof(struct pcie_state
,
1582 &pcie_config_flags
);
1584 ath10k_err(ar
, "Failed to get pcie config_flags: %d\n", ret
);
1588 pcie_config_flags
&= ~PCIE_CONFIG_FLAG_ENABLE_L1
;
1590 ret
= ath10k_pci_diag_write32(ar
, (pcie_state_targ_addr
+
1591 offsetof(struct pcie_state
,
1595 ath10k_err(ar
, "Failed to write pcie config_flags: %d\n", ret
);
1599 /* configure early allocation */
1600 ealloc_targ_addr
= host_interest_item_address(HI_ITEM(hi_early_alloc
));
1602 ret
= ath10k_pci_diag_read32(ar
, ealloc_targ_addr
, &ealloc_value
);
1604 ath10k_err(ar
, "Faile to get early alloc val: %d\n", ret
);
1608 /* first bank is switched to IRAM */
1609 ealloc_value
|= ((HI_EARLY_ALLOC_MAGIC
<< HI_EARLY_ALLOC_MAGIC_SHIFT
) &
1610 HI_EARLY_ALLOC_MAGIC_MASK
);
1611 ealloc_value
|= ((1 << HI_EARLY_ALLOC_IRAM_BANKS_SHIFT
) &
1612 HI_EARLY_ALLOC_IRAM_BANKS_MASK
);
1614 ret
= ath10k_pci_diag_write32(ar
, ealloc_targ_addr
, ealloc_value
);
1616 ath10k_err(ar
, "Failed to set early alloc val: %d\n", ret
);
1620 /* Tell Target to proceed with initialization */
1621 flag2_targ_addr
= host_interest_item_address(HI_ITEM(hi_option_flag2
));
1623 ret
= ath10k_pci_diag_read32(ar
, flag2_targ_addr
, &flag2_value
);
1625 ath10k_err(ar
, "Failed to get option val: %d\n", ret
);
1629 flag2_value
|= HI_OPTION_EARLY_CFG_DONE
;
1631 ret
= ath10k_pci_diag_write32(ar
, flag2_targ_addr
, flag2_value
);
1633 ath10k_err(ar
, "Failed to set option val: %d\n", ret
);
1640 static int ath10k_pci_alloc_pipes(struct ath10k
*ar
)
1642 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
1643 struct ath10k_pci_pipe
*pipe
;
1646 for (i
= 0; i
< CE_COUNT
; i
++) {
1647 pipe
= &ar_pci
->pipe_info
[i
];
1648 pipe
->ce_hdl
= &ar_pci
->ce_states
[i
];
1650 pipe
->hif_ce_state
= ar
;
1652 ret
= ath10k_ce_alloc_pipe(ar
, i
, &host_ce_config_wlan
[i
],
1653 ath10k_pci_ce_send_done
,
1654 ath10k_pci_ce_recv_data
);
1656 ath10k_err(ar
, "failed to allocate copy engine pipe %d: %d\n",
1661 /* Last CE is Diagnostic Window */
1662 if (i
== CE_COUNT
- 1) {
1663 ar_pci
->ce_diag
= pipe
->ce_hdl
;
1667 pipe
->buf_sz
= (size_t)(host_ce_config_wlan
[i
].src_sz_max
);
1673 static void ath10k_pci_free_pipes(struct ath10k
*ar
)
1677 for (i
= 0; i
< CE_COUNT
; i
++)
1678 ath10k_ce_free_pipe(ar
, i
);
1681 static int ath10k_pci_init_pipes(struct ath10k
*ar
)
1685 for (i
= 0; i
< CE_COUNT
; i
++) {
1686 ret
= ath10k_ce_init_pipe(ar
, i
, &host_ce_config_wlan
[i
]);
1688 ath10k_err(ar
, "failed to initialize copy engine pipe %d: %d\n",
1697 static bool ath10k_pci_has_fw_crashed(struct ath10k
*ar
)
1699 return ath10k_pci_read32(ar
, FW_INDICATOR_ADDRESS
) &
1700 FW_IND_EVENT_PENDING
;
1703 static void ath10k_pci_fw_crashed_clear(struct ath10k
*ar
)
1707 val
= ath10k_pci_read32(ar
, FW_INDICATOR_ADDRESS
);
1708 val
&= ~FW_IND_EVENT_PENDING
;
1709 ath10k_pci_write32(ar
, FW_INDICATOR_ADDRESS
, val
);
1712 /* this function effectively clears target memory controller assert line */
1713 static void ath10k_pci_warm_reset_si0(struct ath10k
*ar
)
1717 val
= ath10k_pci_soc_read32(ar
, SOC_RESET_CONTROL_ADDRESS
);
1718 ath10k_pci_soc_write32(ar
, SOC_RESET_CONTROL_ADDRESS
,
1719 val
| SOC_RESET_CONTROL_SI0_RST_MASK
);
1720 val
= ath10k_pci_soc_read32(ar
, SOC_RESET_CONTROL_ADDRESS
);
1724 val
= ath10k_pci_soc_read32(ar
, SOC_RESET_CONTROL_ADDRESS
);
1725 ath10k_pci_soc_write32(ar
, SOC_RESET_CONTROL_ADDRESS
,
1726 val
& ~SOC_RESET_CONTROL_SI0_RST_MASK
);
1727 val
= ath10k_pci_soc_read32(ar
, SOC_RESET_CONTROL_ADDRESS
);
1732 static void ath10k_pci_warm_reset_cpu(struct ath10k
*ar
)
1736 ath10k_pci_write32(ar
, FW_INDICATOR_ADDRESS
, 0);
1738 val
= ath10k_pci_read32(ar
, RTC_SOC_BASE_ADDRESS
+
1739 SOC_RESET_CONTROL_ADDRESS
);
1740 ath10k_pci_write32(ar
, RTC_SOC_BASE_ADDRESS
+ SOC_RESET_CONTROL_ADDRESS
,
1741 val
| SOC_RESET_CONTROL_CPU_WARM_RST_MASK
);
1744 static void ath10k_pci_warm_reset_ce(struct ath10k
*ar
)
1748 val
= ath10k_pci_read32(ar
, RTC_SOC_BASE_ADDRESS
+
1749 SOC_RESET_CONTROL_ADDRESS
);
1751 ath10k_pci_write32(ar
, RTC_SOC_BASE_ADDRESS
+ SOC_RESET_CONTROL_ADDRESS
,
1752 val
| SOC_RESET_CONTROL_CE_RST_MASK
);
1754 ath10k_pci_write32(ar
, RTC_SOC_BASE_ADDRESS
+ SOC_RESET_CONTROL_ADDRESS
,
1755 val
& ~SOC_RESET_CONTROL_CE_RST_MASK
);
1758 static void ath10k_pci_warm_reset_clear_lf(struct ath10k
*ar
)
1762 val
= ath10k_pci_read32(ar
, RTC_SOC_BASE_ADDRESS
+
1763 SOC_LF_TIMER_CONTROL0_ADDRESS
);
1764 ath10k_pci_write32(ar
, RTC_SOC_BASE_ADDRESS
+
1765 SOC_LF_TIMER_CONTROL0_ADDRESS
,
1766 val
& ~SOC_LF_TIMER_CONTROL0_ENABLE_MASK
);
1769 static int ath10k_pci_warm_reset(struct ath10k
*ar
)
1773 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot warm reset\n");
1775 spin_lock_bh(&ar
->data_lock
);
1776 ar
->stats
.fw_warm_reset_counter
++;
1777 spin_unlock_bh(&ar
->data_lock
);
1779 ath10k_pci_irq_disable(ar
);
1781 /* Make sure the target CPU is not doing anything dangerous, e.g. if it
1782 * were to access copy engine while host performs copy engine reset
1783 * then it is possible for the device to confuse pci-e controller to
1784 * the point of bringing host system to a complete stop (i.e. hang).
1786 ath10k_pci_warm_reset_si0(ar
);
1787 ath10k_pci_warm_reset_cpu(ar
);
1788 ath10k_pci_init_pipes(ar
);
1789 ath10k_pci_wait_for_target_init(ar
);
1791 ath10k_pci_warm_reset_clear_lf(ar
);
1792 ath10k_pci_warm_reset_ce(ar
);
1793 ath10k_pci_warm_reset_cpu(ar
);
1794 ath10k_pci_init_pipes(ar
);
1796 ret
= ath10k_pci_wait_for_target_init(ar
);
1798 ath10k_warn(ar
, "failed to wait for target init: %d\n", ret
);
1802 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot warm reset complete\n");
1807 static int ath10k_pci_chip_reset(struct ath10k
*ar
)
1812 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot chip reset\n");
1814 /* Some hardware revisions (e.g. CUS223v2) has issues with cold reset.
1815 * It is thus preferred to use warm reset which is safer but may not be
1816 * able to recover the device from all possible fail scenarios.
1818 * Warm reset doesn't always work on first try so attempt it a few
1819 * times before giving up.
1821 for (i
= 0; i
< ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS
; i
++) {
1822 ret
= ath10k_pci_warm_reset(ar
);
1824 ath10k_warn(ar
, "failed to warm reset attempt %d of %d: %d\n",
1825 i
+ 1, ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS
,
1830 /* FIXME: Sometimes copy engine doesn't recover after warm
1831 * reset. In most cases this needs cold reset. In some of these
1832 * cases the device is in such a state that a cold reset may
1835 * Reading any host interest register via copy engine is
1836 * sufficient to verify if device is capable of booting
1839 ret
= ath10k_pci_init_pipes(ar
);
1841 ath10k_warn(ar
, "failed to init copy engine: %d\n",
1846 ret
= ath10k_pci_diag_read32(ar
, QCA988X_HOST_INTEREST_ADDRESS
,
1849 ath10k_warn(ar
, "failed to poke copy engine: %d\n",
1854 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot chip reset complete (warm)\n");
1858 if (ath10k_pci_reset_mode
== ATH10K_PCI_RESET_WARM_ONLY
) {
1859 ath10k_warn(ar
, "refusing cold reset as requested\n");
1863 ret
= ath10k_pci_cold_reset(ar
);
1865 ath10k_warn(ar
, "failed to cold reset: %d\n", ret
);
1869 ret
= ath10k_pci_wait_for_target_init(ar
);
1871 ath10k_warn(ar
, "failed to wait for target after cold reset: %d\n",
1876 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot chip reset complete (cold)\n");
1881 static int ath10k_pci_hif_power_up(struct ath10k
*ar
)
1885 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot hif power up\n");
1887 ret
= ath10k_pci_wake(ar
);
1889 ath10k_err(ar
, "failed to wake up target: %d\n", ret
);
1894 * Bring the target up cleanly.
1896 * The target may be in an undefined state with an AUX-powered Target
1897 * and a Host in WoW mode. If the Host crashes, loses power, or is
1898 * restarted (without unloading the driver) then the Target is left
1899 * (aux) powered and running. On a subsequent driver load, the Target
1900 * is in an unexpected state. We try to catch that here in order to
1901 * reset the Target and retry the probe.
1903 ret
= ath10k_pci_chip_reset(ar
);
1905 ath10k_err(ar
, "failed to reset chip: %d\n", ret
);
1909 ret
= ath10k_pci_init_pipes(ar
);
1911 ath10k_err(ar
, "failed to initialize CE: %d\n", ret
);
1915 ret
= ath10k_pci_init_config(ar
);
1917 ath10k_err(ar
, "failed to setup init config: %d\n", ret
);
1921 ret
= ath10k_pci_wake_target_cpu(ar
);
1923 ath10k_err(ar
, "could not wake up target CPU: %d\n", ret
);
1930 ath10k_pci_ce_deinit(ar
);
1933 ath10k_pci_sleep(ar
);
1937 static void ath10k_pci_hif_power_down(struct ath10k
*ar
)
1939 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot hif power down\n");
1941 /* Currently hif_power_up performs effectively a reset and hif_stop
1942 * resets the chip as well so there's no point in resetting here.
1945 ath10k_pci_sleep(ar
);
1950 #define ATH10K_PCI_PM_CONTROL 0x44
1952 static int ath10k_pci_hif_suspend(struct ath10k
*ar
)
1954 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
1955 struct pci_dev
*pdev
= ar_pci
->pdev
;
1958 pci_read_config_dword(pdev
, ATH10K_PCI_PM_CONTROL
, &val
);
1960 if ((val
& 0x000000ff) != 0x3) {
1961 pci_save_state(pdev
);
1962 pci_disable_device(pdev
);
1963 pci_write_config_dword(pdev
, ATH10K_PCI_PM_CONTROL
,
1964 (val
& 0xffffff00) | 0x03);
1970 static int ath10k_pci_hif_resume(struct ath10k
*ar
)
1972 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
1973 struct pci_dev
*pdev
= ar_pci
->pdev
;
1976 pci_read_config_dword(pdev
, ATH10K_PCI_PM_CONTROL
, &val
);
1978 if ((val
& 0x000000ff) != 0) {
1979 pci_restore_state(pdev
);
1980 pci_write_config_dword(pdev
, ATH10K_PCI_PM_CONTROL
,
1983 * Suspend/Resume resets the PCI configuration space,
1984 * so we have to re-disable the RETRY_TIMEOUT register (0x41)
1985 * to keep PCI Tx retries from interfering with C3 CPU state
1987 pci_read_config_dword(pdev
, 0x40, &val
);
1989 if ((val
& 0x0000ff00) != 0)
1990 pci_write_config_dword(pdev
, 0x40, val
& 0xffff00ff);
1997 static const struct ath10k_hif_ops ath10k_pci_hif_ops
= {
1998 .tx_sg
= ath10k_pci_hif_tx_sg
,
1999 .diag_read
= ath10k_pci_hif_diag_read
,
2000 .diag_write
= ath10k_pci_diag_write_mem
,
2001 .exchange_bmi_msg
= ath10k_pci_hif_exchange_bmi_msg
,
2002 .start
= ath10k_pci_hif_start
,
2003 .stop
= ath10k_pci_hif_stop
,
2004 .map_service_to_pipe
= ath10k_pci_hif_map_service_to_pipe
,
2005 .get_default_pipe
= ath10k_pci_hif_get_default_pipe
,
2006 .send_complete_check
= ath10k_pci_hif_send_complete_check
,
2007 .set_callbacks
= ath10k_pci_hif_set_callbacks
,
2008 .get_free_queue_number
= ath10k_pci_hif_get_free_queue_number
,
2009 .power_up
= ath10k_pci_hif_power_up
,
2010 .power_down
= ath10k_pci_hif_power_down
,
2011 .read32
= ath10k_pci_read32
,
2012 .write32
= ath10k_pci_write32
,
2014 .suspend
= ath10k_pci_hif_suspend
,
2015 .resume
= ath10k_pci_hif_resume
,
2019 static void ath10k_pci_ce_tasklet(unsigned long ptr
)
2021 struct ath10k_pci_pipe
*pipe
= (struct ath10k_pci_pipe
*)ptr
;
2022 struct ath10k_pci
*ar_pci
= pipe
->ar_pci
;
2024 ath10k_ce_per_engine_service(ar_pci
->ar
, pipe
->pipe_num
);
2027 static void ath10k_msi_err_tasklet(unsigned long data
)
2029 struct ath10k
*ar
= (struct ath10k
*)data
;
2031 if (!ath10k_pci_has_fw_crashed(ar
)) {
2032 ath10k_warn(ar
, "received unsolicited fw crash interrupt\n");
2036 ath10k_pci_fw_crashed_clear(ar
);
2037 ath10k_pci_fw_crashed_dump(ar
);
2041 * Handler for a per-engine interrupt on a PARTICULAR CE.
2042 * This is used in cases where each CE has a private MSI interrupt.
2044 static irqreturn_t
ath10k_pci_per_engine_handler(int irq
, void *arg
)
2046 struct ath10k
*ar
= arg
;
2047 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2048 int ce_id
= irq
- ar_pci
->pdev
->irq
- MSI_ASSIGN_CE_INITIAL
;
2050 if (ce_id
< 0 || ce_id
>= ARRAY_SIZE(ar_pci
->pipe_info
)) {
2051 ath10k_warn(ar
, "unexpected/invalid irq %d ce_id %d\n", irq
,
2057 * NOTE: We are able to derive ce_id from irq because we
2058 * use a one-to-one mapping for CE's 0..5.
2059 * CE's 6 & 7 do not use interrupts at all.
2061 * This mapping must be kept in sync with the mapping
2064 tasklet_schedule(&ar_pci
->pipe_info
[ce_id
].intr
);
2068 static irqreturn_t
ath10k_pci_msi_fw_handler(int irq
, void *arg
)
2070 struct ath10k
*ar
= arg
;
2071 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2073 tasklet_schedule(&ar_pci
->msi_fw_err
);
2078 * Top-level interrupt handler for all PCI interrupts from a Target.
2079 * When a block of MSI interrupts is allocated, this top-level handler
2080 * is not used; instead, we directly call the correct sub-handler.
2082 static irqreturn_t
ath10k_pci_interrupt_handler(int irq
, void *arg
)
2084 struct ath10k
*ar
= arg
;
2085 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2087 if (ar_pci
->num_msi_intrs
== 0) {
2088 if (!ath10k_pci_irq_pending(ar
))
2091 ath10k_pci_disable_and_clear_legacy_irq(ar
);
2094 tasklet_schedule(&ar_pci
->intr_tq
);
2099 static void ath10k_pci_tasklet(unsigned long data
)
2101 struct ath10k
*ar
= (struct ath10k
*)data
;
2102 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2104 if (ath10k_pci_has_fw_crashed(ar
)) {
2105 ath10k_pci_fw_crashed_clear(ar
);
2106 ath10k_pci_fw_crashed_dump(ar
);
2110 ath10k_ce_per_engine_service_any(ar
);
2112 /* Re-enable legacy irq that was disabled in the irq handler */
2113 if (ar_pci
->num_msi_intrs
== 0)
2114 ath10k_pci_enable_legacy_irq(ar
);
2117 static int ath10k_pci_request_irq_msix(struct ath10k
*ar
)
2119 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2122 ret
= request_irq(ar_pci
->pdev
->irq
+ MSI_ASSIGN_FW
,
2123 ath10k_pci_msi_fw_handler
,
2124 IRQF_SHARED
, "ath10k_pci", ar
);
2126 ath10k_warn(ar
, "failed to request MSI-X fw irq %d: %d\n",
2127 ar_pci
->pdev
->irq
+ MSI_ASSIGN_FW
, ret
);
2131 for (i
= MSI_ASSIGN_CE_INITIAL
; i
<= MSI_ASSIGN_CE_MAX
; i
++) {
2132 ret
= request_irq(ar_pci
->pdev
->irq
+ i
,
2133 ath10k_pci_per_engine_handler
,
2134 IRQF_SHARED
, "ath10k_pci", ar
);
2136 ath10k_warn(ar
, "failed to request MSI-X ce irq %d: %d\n",
2137 ar_pci
->pdev
->irq
+ i
, ret
);
2139 for (i
--; i
>= MSI_ASSIGN_CE_INITIAL
; i
--)
2140 free_irq(ar_pci
->pdev
->irq
+ i
, ar
);
2142 free_irq(ar_pci
->pdev
->irq
+ MSI_ASSIGN_FW
, ar
);
2150 static int ath10k_pci_request_irq_msi(struct ath10k
*ar
)
2152 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2155 ret
= request_irq(ar_pci
->pdev
->irq
,
2156 ath10k_pci_interrupt_handler
,
2157 IRQF_SHARED
, "ath10k_pci", ar
);
2159 ath10k_warn(ar
, "failed to request MSI irq %d: %d\n",
2160 ar_pci
->pdev
->irq
, ret
);
2167 static int ath10k_pci_request_irq_legacy(struct ath10k
*ar
)
2169 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2172 ret
= request_irq(ar_pci
->pdev
->irq
,
2173 ath10k_pci_interrupt_handler
,
2174 IRQF_SHARED
, "ath10k_pci", ar
);
2176 ath10k_warn(ar
, "failed to request legacy irq %d: %d\n",
2177 ar_pci
->pdev
->irq
, ret
);
2184 static int ath10k_pci_request_irq(struct ath10k
*ar
)
2186 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2188 switch (ar_pci
->num_msi_intrs
) {
2190 return ath10k_pci_request_irq_legacy(ar
);
2192 return ath10k_pci_request_irq_msi(ar
);
2193 case MSI_NUM_REQUEST
:
2194 return ath10k_pci_request_irq_msix(ar
);
2197 ath10k_warn(ar
, "unknown irq configuration upon request\n");
2201 static void ath10k_pci_free_irq(struct ath10k
*ar
)
2203 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2206 /* There's at least one interrupt irregardless whether its legacy INTR
2207 * or MSI or MSI-X */
2208 for (i
= 0; i
< max(1, ar_pci
->num_msi_intrs
); i
++)
2209 free_irq(ar_pci
->pdev
->irq
+ i
, ar
);
2212 static void ath10k_pci_init_irq_tasklets(struct ath10k
*ar
)
2214 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2217 tasklet_init(&ar_pci
->intr_tq
, ath10k_pci_tasklet
, (unsigned long)ar
);
2218 tasklet_init(&ar_pci
->msi_fw_err
, ath10k_msi_err_tasklet
,
2221 for (i
= 0; i
< CE_COUNT
; i
++) {
2222 ar_pci
->pipe_info
[i
].ar_pci
= ar_pci
;
2223 tasklet_init(&ar_pci
->pipe_info
[i
].intr
, ath10k_pci_ce_tasklet
,
2224 (unsigned long)&ar_pci
->pipe_info
[i
]);
2228 static int ath10k_pci_init_irq(struct ath10k
*ar
)
2230 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2233 ath10k_pci_init_irq_tasklets(ar
);
2235 if (ath10k_pci_irq_mode
!= ATH10K_PCI_IRQ_AUTO
)
2236 ath10k_info(ar
, "limiting irq mode to: %d\n",
2237 ath10k_pci_irq_mode
);
2240 if (ath10k_pci_irq_mode
== ATH10K_PCI_IRQ_AUTO
) {
2241 ar_pci
->num_msi_intrs
= MSI_NUM_REQUEST
;
2242 ret
= pci_enable_msi_range(ar_pci
->pdev
, ar_pci
->num_msi_intrs
,
2243 ar_pci
->num_msi_intrs
);
2251 if (ath10k_pci_irq_mode
!= ATH10K_PCI_IRQ_LEGACY
) {
2252 ar_pci
->num_msi_intrs
= 1;
2253 ret
= pci_enable_msi(ar_pci
->pdev
);
2262 * A potential race occurs here: The CORE_BASE write
2263 * depends on target correctly decoding AXI address but
2264 * host won't know when target writes BAR to CORE_CTRL.
2265 * This write might get lost if target has NOT written BAR.
2266 * For now, fix the race by repeating the write in below
2267 * synchronization checking. */
2268 ar_pci
->num_msi_intrs
= 0;
2270 ath10k_pci_write32(ar
, SOC_CORE_BASE_ADDRESS
+ PCIE_INTR_ENABLE_ADDRESS
,
2271 PCIE_INTR_FIRMWARE_MASK
| PCIE_INTR_CE_MASK_ALL
);
2276 static void ath10k_pci_deinit_irq_legacy(struct ath10k
*ar
)
2278 ath10k_pci_write32(ar
, SOC_CORE_BASE_ADDRESS
+ PCIE_INTR_ENABLE_ADDRESS
,
2282 static int ath10k_pci_deinit_irq(struct ath10k
*ar
)
2284 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2286 switch (ar_pci
->num_msi_intrs
) {
2288 ath10k_pci_deinit_irq_legacy(ar
);
2292 case MSI_NUM_REQUEST
:
2293 pci_disable_msi(ar_pci
->pdev
);
2296 pci_disable_msi(ar_pci
->pdev
);
2299 ath10k_warn(ar
, "unknown irq configuration upon deinit\n");
2303 static int ath10k_pci_wait_for_target_init(struct ath10k
*ar
)
2305 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2306 unsigned long timeout
;
2309 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot waiting target to initialise\n");
2311 timeout
= jiffies
+ msecs_to_jiffies(ATH10K_PCI_TARGET_WAIT
);
2314 val
= ath10k_pci_read32(ar
, FW_INDICATOR_ADDRESS
);
2316 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot target indicator %x\n",
2319 /* target should never return this */
2320 if (val
== 0xffffffff)
2323 /* the device has crashed so don't bother trying anymore */
2324 if (val
& FW_IND_EVENT_PENDING
)
2327 if (val
& FW_IND_INITIALIZED
)
2330 if (ar_pci
->num_msi_intrs
== 0)
2331 /* Fix potential race by repeating CORE_BASE writes */
2332 ath10k_pci_enable_legacy_irq(ar
);
2335 } while (time_before(jiffies
, timeout
));
2337 ath10k_pci_disable_and_clear_legacy_irq(ar
);
2338 ath10k_pci_irq_msi_fw_mask(ar
);
2340 if (val
== 0xffffffff) {
2341 ath10k_err(ar
, "failed to read device register, device is gone\n");
2345 if (val
& FW_IND_EVENT_PENDING
) {
2346 ath10k_warn(ar
, "device has crashed during init\n");
2347 ath10k_pci_fw_crashed_clear(ar
);
2348 ath10k_pci_fw_crashed_dump(ar
);
2352 if (!(val
& FW_IND_INITIALIZED
)) {
2353 ath10k_err(ar
, "failed to receive initialized event from target: %08x\n",
2358 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot target initialised\n");
2362 static int ath10k_pci_cold_reset(struct ath10k
*ar
)
2367 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot cold reset\n");
2369 spin_lock_bh(&ar
->data_lock
);
2371 ar
->stats
.fw_cold_reset_counter
++;
2373 spin_unlock_bh(&ar
->data_lock
);
2375 /* Put Target, including PCIe, into RESET. */
2376 val
= ath10k_pci_reg_read32(ar
, SOC_GLOBAL_RESET_ADDRESS
);
2378 ath10k_pci_reg_write32(ar
, SOC_GLOBAL_RESET_ADDRESS
, val
);
2380 for (i
= 0; i
< ATH_PCI_RESET_WAIT_MAX
; i
++) {
2381 if (ath10k_pci_reg_read32(ar
, RTC_STATE_ADDRESS
) &
2382 RTC_STATE_COLD_RESET_MASK
)
2387 /* Pull Target, including PCIe, out of RESET. */
2389 ath10k_pci_reg_write32(ar
, SOC_GLOBAL_RESET_ADDRESS
, val
);
2391 for (i
= 0; i
< ATH_PCI_RESET_WAIT_MAX
; i
++) {
2392 if (!(ath10k_pci_reg_read32(ar
, RTC_STATE_ADDRESS
) &
2393 RTC_STATE_COLD_RESET_MASK
))
2398 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot cold reset complete\n");
2403 static int ath10k_pci_claim(struct ath10k
*ar
)
2405 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2406 struct pci_dev
*pdev
= ar_pci
->pdev
;
2410 pci_set_drvdata(pdev
, ar
);
2412 ret
= pci_enable_device(pdev
);
2414 ath10k_err(ar
, "failed to enable pci device: %d\n", ret
);
2418 ret
= pci_request_region(pdev
, BAR_NUM
, "ath");
2420 ath10k_err(ar
, "failed to request region BAR%d: %d\n", BAR_NUM
,
2425 /* Target expects 32 bit DMA. Enforce it. */
2426 ret
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
2428 ath10k_err(ar
, "failed to set dma mask to 32-bit: %d\n", ret
);
2432 ret
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(32));
2434 ath10k_err(ar
, "failed to set consistent dma mask to 32-bit: %d\n",
2439 pci_set_master(pdev
);
2441 /* Workaround: Disable ASPM */
2442 pci_read_config_dword(pdev
, 0x80, &lcr_val
);
2443 pci_write_config_dword(pdev
, 0x80, (lcr_val
& 0xffffff00));
2445 /* Arrange for access to Target SoC registers. */
2446 ar_pci
->mem
= pci_iomap(pdev
, BAR_NUM
, 0);
2448 ath10k_err(ar
, "failed to iomap BAR%d\n", BAR_NUM
);
2453 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot pci_mem 0x%p\n", ar_pci
->mem
);
2457 pci_clear_master(pdev
);
2460 pci_release_region(pdev
, BAR_NUM
);
2463 pci_disable_device(pdev
);
2468 static void ath10k_pci_release(struct ath10k
*ar
)
2470 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2471 struct pci_dev
*pdev
= ar_pci
->pdev
;
2473 pci_iounmap(pdev
, ar_pci
->mem
);
2474 pci_release_region(pdev
, BAR_NUM
);
2475 pci_clear_master(pdev
);
2476 pci_disable_device(pdev
);
2479 static int ath10k_pci_probe(struct pci_dev
*pdev
,
2480 const struct pci_device_id
*pci_dev
)
2484 struct ath10k_pci
*ar_pci
;
2487 ar
= ath10k_core_create(sizeof(*ar_pci
), &pdev
->dev
,
2489 &ath10k_pci_hif_ops
);
2491 dev_err(&pdev
->dev
, "failed to allocate core\n");
2495 ath10k_dbg(ar
, ATH10K_DBG_PCI
, "pci probe\n");
2497 ar_pci
= ath10k_pci_priv(ar
);
2498 ar_pci
->pdev
= pdev
;
2499 ar_pci
->dev
= &pdev
->dev
;
2502 spin_lock_init(&ar_pci
->ce_lock
);
2503 setup_timer(&ar_pci
->rx_post_retry
, ath10k_pci_rx_replenish_retry
,
2506 ret
= ath10k_pci_claim(ar
);
2508 ath10k_err(ar
, "failed to claim device: %d\n", ret
);
2509 goto err_core_destroy
;
2512 ret
= ath10k_pci_wake(ar
);
2514 ath10k_err(ar
, "failed to wake up: %d\n", ret
);
2518 chip_id
= ath10k_pci_soc_read32(ar
, SOC_CHIP_ID_ADDRESS
);
2519 if (chip_id
== 0xffffffff) {
2520 ath10k_err(ar
, "failed to get chip id\n");
2524 ret
= ath10k_pci_alloc_pipes(ar
);
2526 ath10k_err(ar
, "failed to allocate copy engine pipes: %d\n",
2531 ath10k_pci_ce_deinit(ar
);
2532 ath10k_pci_irq_disable(ar
);
2534 ret
= ath10k_pci_init_irq(ar
);
2536 ath10k_err(ar
, "failed to init irqs: %d\n", ret
);
2537 goto err_free_pipes
;
2540 ath10k_info(ar
, "pci irq %s interrupts %d irq_mode %d reset_mode %d\n",
2541 ath10k_pci_get_irq_method(ar
), ar_pci
->num_msi_intrs
,
2542 ath10k_pci_irq_mode
, ath10k_pci_reset_mode
);
2544 ret
= ath10k_pci_request_irq(ar
);
2546 ath10k_warn(ar
, "failed to request irqs: %d\n", ret
);
2547 goto err_deinit_irq
;
2550 ath10k_pci_sleep(ar
);
2552 ret
= ath10k_core_register(ar
, chip_id
);
2554 ath10k_err(ar
, "failed to register driver core: %d\n", ret
);
2561 ath10k_pci_free_irq(ar
);
2562 ath10k_pci_kill_tasklet(ar
);
2565 ath10k_pci_deinit_irq(ar
);
2568 ath10k_pci_free_pipes(ar
);
2571 ath10k_pci_sleep(ar
);
2574 ath10k_pci_release(ar
);
2577 ath10k_core_destroy(ar
);
2582 static void ath10k_pci_remove(struct pci_dev
*pdev
)
2584 struct ath10k
*ar
= pci_get_drvdata(pdev
);
2585 struct ath10k_pci
*ar_pci
;
2587 ath10k_dbg(ar
, ATH10K_DBG_PCI
, "pci remove\n");
2592 ar_pci
= ath10k_pci_priv(ar
);
2597 ath10k_core_unregister(ar
);
2598 ath10k_pci_free_irq(ar
);
2599 ath10k_pci_kill_tasklet(ar
);
2600 ath10k_pci_deinit_irq(ar
);
2601 ath10k_pci_ce_deinit(ar
);
2602 ath10k_pci_free_pipes(ar
);
2603 ath10k_pci_release(ar
);
2604 ath10k_core_destroy(ar
);
2607 MODULE_DEVICE_TABLE(pci
, ath10k_pci_id_table
);
2609 static struct pci_driver ath10k_pci_driver
= {
2610 .name
= "ath10k_pci",
2611 .id_table
= ath10k_pci_id_table
,
2612 .probe
= ath10k_pci_probe
,
2613 .remove
= ath10k_pci_remove
,
2616 static int __init
ath10k_pci_init(void)
2620 ret
= pci_register_driver(&ath10k_pci_driver
);
2622 printk(KERN_ERR
"failed to register ath10k pci driver: %d\n",
2627 module_init(ath10k_pci_init
);
2629 static void __exit
ath10k_pci_exit(void)
2631 pci_unregister_driver(&ath10k_pci_driver
);
2634 module_exit(ath10k_pci_exit
);
2636 MODULE_AUTHOR("Qualcomm Atheros");
2637 MODULE_DESCRIPTION("Driver support for Atheros QCA988X PCIe devices");
2638 MODULE_LICENSE("Dual BSD/GPL");
2639 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR
"/" QCA988X_HW_2_0_FW_FILE
);
2640 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR
"/" ATH10K_FW_API2_FILE
);
2641 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR
"/" ATH10K_FW_API3_FILE
);
2642 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR
"/" QCA988X_HW_2_0_BOARD_DATA_FILE
);