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ath10k: use ath10k_do_pci_wake/sleep
[deliverable/linux.git] / drivers / net / wireless / ath / ath10k / pci.c
1 /*
2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18 #include <linux/pci.h>
19 #include <linux/module.h>
20 #include <linux/interrupt.h>
21 #include <linux/spinlock.h>
22
23 #include "core.h"
24 #include "debug.h"
25
26 #include "targaddrs.h"
27 #include "bmi.h"
28
29 #include "hif.h"
30 #include "htc.h"
31
32 #include "ce.h"
33 #include "pci.h"
34
35 static unsigned int ath10k_target_ps;
36 module_param(ath10k_target_ps, uint, 0644);
37 MODULE_PARM_DESC(ath10k_target_ps, "Enable ath10k Target (SoC) PS option");
38
39 #define QCA988X_2_0_DEVICE_ID (0x003c)
40
41 static DEFINE_PCI_DEVICE_TABLE(ath10k_pci_id_table) = {
42 { PCI_VDEVICE(ATHEROS, QCA988X_2_0_DEVICE_ID) }, /* PCI-E QCA988X V2 */
43 {0}
44 };
45
46 static int ath10k_pci_diag_read_access(struct ath10k *ar, u32 address,
47 u32 *data);
48
49 static void ath10k_pci_process_ce(struct ath10k *ar);
50 static int ath10k_pci_post_rx(struct ath10k *ar);
51 static int ath10k_pci_post_rx_pipe(struct ath10k_pci_pipe *pipe_info,
52 int num);
53 static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe *pipe_info);
54 static void ath10k_pci_stop_ce(struct ath10k *ar);
55 static int ath10k_pci_device_reset(struct ath10k *ar);
56 static int ath10k_pci_wait_for_target_init(struct ath10k *ar);
57 static int ath10k_pci_start_intr(struct ath10k *ar);
58 static void ath10k_pci_stop_intr(struct ath10k *ar);
59
60 static const struct ce_attr host_ce_config_wlan[] = {
61 /* CE0: host->target HTC control and raw streams */
62 {
63 .flags = CE_ATTR_FLAGS,
64 .src_nentries = 16,
65 .src_sz_max = 256,
66 .dest_nentries = 0,
67 },
68
69 /* CE1: target->host HTT + HTC control */
70 {
71 .flags = CE_ATTR_FLAGS,
72 .src_nentries = 0,
73 .src_sz_max = 512,
74 .dest_nentries = 512,
75 },
76
77 /* CE2: target->host WMI */
78 {
79 .flags = CE_ATTR_FLAGS,
80 .src_nentries = 0,
81 .src_sz_max = 2048,
82 .dest_nentries = 32,
83 },
84
85 /* CE3: host->target WMI */
86 {
87 .flags = CE_ATTR_FLAGS,
88 .src_nentries = 32,
89 .src_sz_max = 2048,
90 .dest_nentries = 0,
91 },
92
93 /* CE4: host->target HTT */
94 {
95 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
96 .src_nentries = CE_HTT_H2T_MSG_SRC_NENTRIES,
97 .src_sz_max = 256,
98 .dest_nentries = 0,
99 },
100
101 /* CE5: unused */
102 {
103 .flags = CE_ATTR_FLAGS,
104 .src_nentries = 0,
105 .src_sz_max = 0,
106 .dest_nentries = 0,
107 },
108
109 /* CE6: target autonomous hif_memcpy */
110 {
111 .flags = CE_ATTR_FLAGS,
112 .src_nentries = 0,
113 .src_sz_max = 0,
114 .dest_nentries = 0,
115 },
116
117 /* CE7: ce_diag, the Diagnostic Window */
118 {
119 .flags = CE_ATTR_FLAGS,
120 .src_nentries = 2,
121 .src_sz_max = DIAG_TRANSFER_LIMIT,
122 .dest_nentries = 2,
123 },
124 };
125
126 /* Target firmware's Copy Engine configuration. */
127 static const struct ce_pipe_config target_ce_config_wlan[] = {
128 /* CE0: host->target HTC control and raw streams */
129 {
130 .pipenum = 0,
131 .pipedir = PIPEDIR_OUT,
132 .nentries = 32,
133 .nbytes_max = 256,
134 .flags = CE_ATTR_FLAGS,
135 .reserved = 0,
136 },
137
138 /* CE1: target->host HTT + HTC control */
139 {
140 .pipenum = 1,
141 .pipedir = PIPEDIR_IN,
142 .nentries = 32,
143 .nbytes_max = 512,
144 .flags = CE_ATTR_FLAGS,
145 .reserved = 0,
146 },
147
148 /* CE2: target->host WMI */
149 {
150 .pipenum = 2,
151 .pipedir = PIPEDIR_IN,
152 .nentries = 32,
153 .nbytes_max = 2048,
154 .flags = CE_ATTR_FLAGS,
155 .reserved = 0,
156 },
157
158 /* CE3: host->target WMI */
159 {
160 .pipenum = 3,
161 .pipedir = PIPEDIR_OUT,
162 .nentries = 32,
163 .nbytes_max = 2048,
164 .flags = CE_ATTR_FLAGS,
165 .reserved = 0,
166 },
167
168 /* CE4: host->target HTT */
169 {
170 .pipenum = 4,
171 .pipedir = PIPEDIR_OUT,
172 .nentries = 256,
173 .nbytes_max = 256,
174 .flags = CE_ATTR_FLAGS,
175 .reserved = 0,
176 },
177
178 /* NB: 50% of src nentries, since tx has 2 frags */
179
180 /* CE5: unused */
181 {
182 .pipenum = 5,
183 .pipedir = PIPEDIR_OUT,
184 .nentries = 32,
185 .nbytes_max = 2048,
186 .flags = CE_ATTR_FLAGS,
187 .reserved = 0,
188 },
189
190 /* CE6: Reserved for target autonomous hif_memcpy */
191 {
192 .pipenum = 6,
193 .pipedir = PIPEDIR_INOUT,
194 .nentries = 32,
195 .nbytes_max = 4096,
196 .flags = CE_ATTR_FLAGS,
197 .reserved = 0,
198 },
199
200 /* CE7 used only by Host */
201 };
202
203 /*
204 * Diagnostic read/write access is provided for startup/config/debug usage.
205 * Caller must guarantee proper alignment, when applicable, and single user
206 * at any moment.
207 */
208 static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, void *data,
209 int nbytes)
210 {
211 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
212 int ret = 0;
213 u32 buf;
214 unsigned int completed_nbytes, orig_nbytes, remaining_bytes;
215 unsigned int id;
216 unsigned int flags;
217 struct ath10k_ce_pipe *ce_diag;
218 /* Host buffer address in CE space */
219 u32 ce_data;
220 dma_addr_t ce_data_base = 0;
221 void *data_buf = NULL;
222 int i;
223
224 /*
225 * This code cannot handle reads to non-memory space. Redirect to the
226 * register read fn but preserve the multi word read capability of
227 * this fn
228 */
229 if (address < DRAM_BASE_ADDRESS) {
230 if (!IS_ALIGNED(address, 4) ||
231 !IS_ALIGNED((unsigned long)data, 4))
232 return -EIO;
233
234 while ((nbytes >= 4) && ((ret = ath10k_pci_diag_read_access(
235 ar, address, (u32 *)data)) == 0)) {
236 nbytes -= sizeof(u32);
237 address += sizeof(u32);
238 data += sizeof(u32);
239 }
240 return ret;
241 }
242
243 ce_diag = ar_pci->ce_diag;
244
245 /*
246 * Allocate a temporary bounce buffer to hold caller's data
247 * to be DMA'ed from Target. This guarantees
248 * 1) 4-byte alignment
249 * 2) Buffer in DMA-able space
250 */
251 orig_nbytes = nbytes;
252 data_buf = (unsigned char *)pci_alloc_consistent(ar_pci->pdev,
253 orig_nbytes,
254 &ce_data_base);
255
256 if (!data_buf) {
257 ret = -ENOMEM;
258 goto done;
259 }
260 memset(data_buf, 0, orig_nbytes);
261
262 remaining_bytes = orig_nbytes;
263 ce_data = ce_data_base;
264 while (remaining_bytes) {
265 nbytes = min_t(unsigned int, remaining_bytes,
266 DIAG_TRANSFER_LIMIT);
267
268 ret = ath10k_ce_recv_buf_enqueue(ce_diag, NULL, ce_data);
269 if (ret != 0)
270 goto done;
271
272 /* Request CE to send from Target(!) address to Host buffer */
273 /*
274 * The address supplied by the caller is in the
275 * Target CPU virtual address space.
276 *
277 * In order to use this address with the diagnostic CE,
278 * convert it from Target CPU virtual address space
279 * to CE address space
280 */
281 ath10k_pci_wake(ar);
282 address = TARG_CPU_SPACE_TO_CE_SPACE(ar, ar_pci->mem,
283 address);
284 ath10k_pci_sleep(ar);
285
286 ret = ath10k_ce_send(ce_diag, NULL, (u32)address, nbytes, 0,
287 0);
288 if (ret)
289 goto done;
290
291 i = 0;
292 while (ath10k_ce_completed_send_next(ce_diag, NULL, &buf,
293 &completed_nbytes,
294 &id) != 0) {
295 mdelay(1);
296 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
297 ret = -EBUSY;
298 goto done;
299 }
300 }
301
302 if (nbytes != completed_nbytes) {
303 ret = -EIO;
304 goto done;
305 }
306
307 if (buf != (u32) address) {
308 ret = -EIO;
309 goto done;
310 }
311
312 i = 0;
313 while (ath10k_ce_completed_recv_next(ce_diag, NULL, &buf,
314 &completed_nbytes,
315 &id, &flags) != 0) {
316 mdelay(1);
317
318 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
319 ret = -EBUSY;
320 goto done;
321 }
322 }
323
324 if (nbytes != completed_nbytes) {
325 ret = -EIO;
326 goto done;
327 }
328
329 if (buf != ce_data) {
330 ret = -EIO;
331 goto done;
332 }
333
334 remaining_bytes -= nbytes;
335 address += nbytes;
336 ce_data += nbytes;
337 }
338
339 done:
340 if (ret == 0) {
341 /* Copy data from allocated DMA buf to caller's buf */
342 WARN_ON_ONCE(orig_nbytes & 3);
343 for (i = 0; i < orig_nbytes / sizeof(__le32); i++) {
344 ((u32 *)data)[i] =
345 __le32_to_cpu(((__le32 *)data_buf)[i]);
346 }
347 } else
348 ath10k_dbg(ATH10K_DBG_PCI, "%s failure (0x%x)\n",
349 __func__, address);
350
351 if (data_buf)
352 pci_free_consistent(ar_pci->pdev, orig_nbytes,
353 data_buf, ce_data_base);
354
355 return ret;
356 }
357
358 /* Read 4-byte aligned data from Target memory or register */
359 static int ath10k_pci_diag_read_access(struct ath10k *ar, u32 address,
360 u32 *data)
361 {
362 /* Assume range doesn't cross this boundary */
363 if (address >= DRAM_BASE_ADDRESS)
364 return ath10k_pci_diag_read_mem(ar, address, data, sizeof(u32));
365
366 ath10k_pci_wake(ar);
367 *data = ath10k_pci_read32(ar, address);
368 ath10k_pci_sleep(ar);
369 return 0;
370 }
371
372 static int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address,
373 const void *data, int nbytes)
374 {
375 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
376 int ret = 0;
377 u32 buf;
378 unsigned int completed_nbytes, orig_nbytes, remaining_bytes;
379 unsigned int id;
380 unsigned int flags;
381 struct ath10k_ce_pipe *ce_diag;
382 void *data_buf = NULL;
383 u32 ce_data; /* Host buffer address in CE space */
384 dma_addr_t ce_data_base = 0;
385 int i;
386
387 ce_diag = ar_pci->ce_diag;
388
389 /*
390 * Allocate a temporary bounce buffer to hold caller's data
391 * to be DMA'ed to Target. This guarantees
392 * 1) 4-byte alignment
393 * 2) Buffer in DMA-able space
394 */
395 orig_nbytes = nbytes;
396 data_buf = (unsigned char *)pci_alloc_consistent(ar_pci->pdev,
397 orig_nbytes,
398 &ce_data_base);
399 if (!data_buf) {
400 ret = -ENOMEM;
401 goto done;
402 }
403
404 /* Copy caller's data to allocated DMA buf */
405 WARN_ON_ONCE(orig_nbytes & 3);
406 for (i = 0; i < orig_nbytes / sizeof(__le32); i++)
407 ((__le32 *)data_buf)[i] = __cpu_to_le32(((u32 *)data)[i]);
408
409 /*
410 * The address supplied by the caller is in the
411 * Target CPU virtual address space.
412 *
413 * In order to use this address with the diagnostic CE,
414 * convert it from
415 * Target CPU virtual address space
416 * to
417 * CE address space
418 */
419 ath10k_pci_wake(ar);
420 address = TARG_CPU_SPACE_TO_CE_SPACE(ar, ar_pci->mem, address);
421 ath10k_pci_sleep(ar);
422
423 remaining_bytes = orig_nbytes;
424 ce_data = ce_data_base;
425 while (remaining_bytes) {
426 /* FIXME: check cast */
427 nbytes = min_t(int, remaining_bytes, DIAG_TRANSFER_LIMIT);
428
429 /* Set up to receive directly into Target(!) address */
430 ret = ath10k_ce_recv_buf_enqueue(ce_diag, NULL, address);
431 if (ret != 0)
432 goto done;
433
434 /*
435 * Request CE to send caller-supplied data that
436 * was copied to bounce buffer to Target(!) address.
437 */
438 ret = ath10k_ce_send(ce_diag, NULL, (u32) ce_data,
439 nbytes, 0, 0);
440 if (ret != 0)
441 goto done;
442
443 i = 0;
444 while (ath10k_ce_completed_send_next(ce_diag, NULL, &buf,
445 &completed_nbytes,
446 &id) != 0) {
447 mdelay(1);
448
449 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
450 ret = -EBUSY;
451 goto done;
452 }
453 }
454
455 if (nbytes != completed_nbytes) {
456 ret = -EIO;
457 goto done;
458 }
459
460 if (buf != ce_data) {
461 ret = -EIO;
462 goto done;
463 }
464
465 i = 0;
466 while (ath10k_ce_completed_recv_next(ce_diag, NULL, &buf,
467 &completed_nbytes,
468 &id, &flags) != 0) {
469 mdelay(1);
470
471 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
472 ret = -EBUSY;
473 goto done;
474 }
475 }
476
477 if (nbytes != completed_nbytes) {
478 ret = -EIO;
479 goto done;
480 }
481
482 if (buf != address) {
483 ret = -EIO;
484 goto done;
485 }
486
487 remaining_bytes -= nbytes;
488 address += nbytes;
489 ce_data += nbytes;
490 }
491
492 done:
493 if (data_buf) {
494 pci_free_consistent(ar_pci->pdev, orig_nbytes, data_buf,
495 ce_data_base);
496 }
497
498 if (ret != 0)
499 ath10k_dbg(ATH10K_DBG_PCI, "%s failure (0x%x)\n", __func__,
500 address);
501
502 return ret;
503 }
504
505 /* Write 4B data to Target memory or register */
506 static int ath10k_pci_diag_write_access(struct ath10k *ar, u32 address,
507 u32 data)
508 {
509 /* Assume range doesn't cross this boundary */
510 if (address >= DRAM_BASE_ADDRESS)
511 return ath10k_pci_diag_write_mem(ar, address, &data,
512 sizeof(u32));
513
514 ath10k_pci_wake(ar);
515 ath10k_pci_write32(ar, address, data);
516 ath10k_pci_sleep(ar);
517 return 0;
518 }
519
520 static bool ath10k_pci_target_is_awake(struct ath10k *ar)
521 {
522 void __iomem *mem = ath10k_pci_priv(ar)->mem;
523 u32 val;
524 val = ioread32(mem + PCIE_LOCAL_BASE_ADDRESS +
525 RTC_STATE_ADDRESS);
526 return (RTC_STATE_V_GET(val) == RTC_STATE_V_ON);
527 }
528
529 int ath10k_do_pci_wake(struct ath10k *ar)
530 {
531 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
532 void __iomem *pci_addr = ar_pci->mem;
533 int tot_delay = 0;
534 int curr_delay = 5;
535
536 if (atomic_read(&ar_pci->keep_awake_count) == 0) {
537 /* Force AWAKE */
538 iowrite32(PCIE_SOC_WAKE_V_MASK,
539 pci_addr + PCIE_LOCAL_BASE_ADDRESS +
540 PCIE_SOC_WAKE_ADDRESS);
541 }
542 atomic_inc(&ar_pci->keep_awake_count);
543
544 if (ar_pci->verified_awake)
545 return 0;
546
547 for (;;) {
548 if (ath10k_pci_target_is_awake(ar)) {
549 ar_pci->verified_awake = true;
550 return 0;
551 }
552
553 if (tot_delay > PCIE_WAKE_TIMEOUT) {
554 ath10k_warn("target took longer %d us to wake up (awake count %d)\n",
555 PCIE_WAKE_TIMEOUT,
556 atomic_read(&ar_pci->keep_awake_count));
557 return -ETIMEDOUT;
558 }
559
560 udelay(curr_delay);
561 tot_delay += curr_delay;
562
563 if (curr_delay < 50)
564 curr_delay += 5;
565 }
566 }
567
568 void ath10k_do_pci_sleep(struct ath10k *ar)
569 {
570 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
571 void __iomem *pci_addr = ar_pci->mem;
572
573 if (atomic_dec_and_test(&ar_pci->keep_awake_count)) {
574 /* Allow sleep */
575 ar_pci->verified_awake = false;
576 iowrite32(PCIE_SOC_WAKE_RESET,
577 pci_addr + PCIE_LOCAL_BASE_ADDRESS +
578 PCIE_SOC_WAKE_ADDRESS);
579 }
580 }
581
582 /*
583 * FIXME: Handle OOM properly.
584 */
585 static inline
586 struct ath10k_pci_compl *get_free_compl(struct ath10k_pci_pipe *pipe_info)
587 {
588 struct ath10k_pci_compl *compl = NULL;
589
590 spin_lock_bh(&pipe_info->pipe_lock);
591 if (list_empty(&pipe_info->compl_free)) {
592 ath10k_warn("Completion buffers are full\n");
593 goto exit;
594 }
595 compl = list_first_entry(&pipe_info->compl_free,
596 struct ath10k_pci_compl, list);
597 list_del(&compl->list);
598 exit:
599 spin_unlock_bh(&pipe_info->pipe_lock);
600 return compl;
601 }
602
603 /* Called by lower (CE) layer when a send to Target completes. */
604 static void ath10k_pci_ce_send_done(struct ath10k_ce_pipe *ce_state)
605 {
606 struct ath10k *ar = ce_state->ar;
607 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
608 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id];
609 struct ath10k_pci_compl *compl;
610 void *transfer_context;
611 u32 ce_data;
612 unsigned int nbytes;
613 unsigned int transfer_id;
614
615 while (ath10k_ce_completed_send_next(ce_state, &transfer_context,
616 &ce_data, &nbytes,
617 &transfer_id) == 0) {
618 compl = get_free_compl(pipe_info);
619 if (!compl)
620 break;
621
622 compl->state = ATH10K_PCI_COMPL_SEND;
623 compl->ce_state = ce_state;
624 compl->pipe_info = pipe_info;
625 compl->skb = transfer_context;
626 compl->nbytes = nbytes;
627 compl->transfer_id = transfer_id;
628 compl->flags = 0;
629
630 /*
631 * Add the completion to the processing queue.
632 */
633 spin_lock_bh(&ar_pci->compl_lock);
634 list_add_tail(&compl->list, &ar_pci->compl_process);
635 spin_unlock_bh(&ar_pci->compl_lock);
636 }
637
638 ath10k_pci_process_ce(ar);
639 }
640
641 /* Called by lower (CE) layer when data is received from the Target. */
642 static void ath10k_pci_ce_recv_data(struct ath10k_ce_pipe *ce_state)
643 {
644 struct ath10k *ar = ce_state->ar;
645 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
646 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id];
647 struct ath10k_pci_compl *compl;
648 struct sk_buff *skb;
649 void *transfer_context;
650 u32 ce_data;
651 unsigned int nbytes;
652 unsigned int transfer_id;
653 unsigned int flags;
654
655 while (ath10k_ce_completed_recv_next(ce_state, &transfer_context,
656 &ce_data, &nbytes, &transfer_id,
657 &flags) == 0) {
658 compl = get_free_compl(pipe_info);
659 if (!compl)
660 break;
661
662 compl->state = ATH10K_PCI_COMPL_RECV;
663 compl->ce_state = ce_state;
664 compl->pipe_info = pipe_info;
665 compl->skb = transfer_context;
666 compl->nbytes = nbytes;
667 compl->transfer_id = transfer_id;
668 compl->flags = flags;
669
670 skb = transfer_context;
671 dma_unmap_single(ar->dev, ATH10K_SKB_CB(skb)->paddr,
672 skb->len + skb_tailroom(skb),
673 DMA_FROM_DEVICE);
674 /*
675 * Add the completion to the processing queue.
676 */
677 spin_lock_bh(&ar_pci->compl_lock);
678 list_add_tail(&compl->list, &ar_pci->compl_process);
679 spin_unlock_bh(&ar_pci->compl_lock);
680 }
681
682 ath10k_pci_process_ce(ar);
683 }
684
685 /* Send the first nbytes bytes of the buffer */
686 static int ath10k_pci_hif_send_head(struct ath10k *ar, u8 pipe_id,
687 unsigned int transfer_id,
688 unsigned int bytes, struct sk_buff *nbuf)
689 {
690 struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(nbuf);
691 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
692 struct ath10k_pci_pipe *pipe_info = &(ar_pci->pipe_info[pipe_id]);
693 struct ath10k_ce_pipe *ce_hdl = pipe_info->ce_hdl;
694 unsigned int len;
695 u32 flags = 0;
696 int ret;
697
698 len = min(bytes, nbuf->len);
699 bytes -= len;
700
701 if (len & 3)
702 ath10k_warn("skb not aligned to 4-byte boundary (%d)\n", len);
703
704 ath10k_dbg(ATH10K_DBG_PCI,
705 "pci send data vaddr %p paddr 0x%llx len %d as %d bytes\n",
706 nbuf->data, (unsigned long long) skb_cb->paddr,
707 nbuf->len, len);
708 ath10k_dbg_dump(ATH10K_DBG_PCI_DUMP, NULL,
709 "ath10k tx: data: ",
710 nbuf->data, nbuf->len);
711
712 ret = ath10k_ce_send(ce_hdl, nbuf, skb_cb->paddr, len, transfer_id,
713 flags);
714 if (ret)
715 ath10k_warn("CE send failed: %p\n", nbuf);
716
717 return ret;
718 }
719
720 static u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe)
721 {
722 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
723 return ath10k_ce_num_free_src_entries(ar_pci->pipe_info[pipe].ce_hdl);
724 }
725
726 static void ath10k_pci_hif_dump_area(struct ath10k *ar)
727 {
728 u32 reg_dump_area = 0;
729 u32 reg_dump_values[REG_DUMP_COUNT_QCA988X] = {};
730 u32 host_addr;
731 int ret;
732 u32 i;
733
734 ath10k_err("firmware crashed!\n");
735 ath10k_err("hardware name %s version 0x%x\n",
736 ar->hw_params.name, ar->target_version);
737 ath10k_err("firmware version: %u.%u.%u.%u\n", ar->fw_version_major,
738 ar->fw_version_minor, ar->fw_version_release,
739 ar->fw_version_build);
740
741 host_addr = host_interest_item_address(HI_ITEM(hi_failure_state));
742 if (ath10k_pci_diag_read_mem(ar, host_addr,
743 &reg_dump_area, sizeof(u32)) != 0) {
744 ath10k_warn("could not read hi_failure_state\n");
745 return;
746 }
747
748 ath10k_err("target register Dump Location: 0x%08X\n", reg_dump_area);
749
750 ret = ath10k_pci_diag_read_mem(ar, reg_dump_area,
751 &reg_dump_values[0],
752 REG_DUMP_COUNT_QCA988X * sizeof(u32));
753 if (ret != 0) {
754 ath10k_err("could not dump FW Dump Area\n");
755 return;
756 }
757
758 BUILD_BUG_ON(REG_DUMP_COUNT_QCA988X % 4);
759
760 ath10k_err("target Register Dump\n");
761 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i += 4)
762 ath10k_err("[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X\n",
763 i,
764 reg_dump_values[i],
765 reg_dump_values[i + 1],
766 reg_dump_values[i + 2],
767 reg_dump_values[i + 3]);
768
769 queue_work(ar->workqueue, &ar->restart_work);
770 }
771
772 static void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe,
773 int force)
774 {
775 if (!force) {
776 int resources;
777 /*
778 * Decide whether to actually poll for completions, or just
779 * wait for a later chance.
780 * If there seem to be plenty of resources left, then just wait
781 * since checking involves reading a CE register, which is a
782 * relatively expensive operation.
783 */
784 resources = ath10k_pci_hif_get_free_queue_number(ar, pipe);
785
786 /*
787 * If at least 50% of the total resources are still available,
788 * don't bother checking again yet.
789 */
790 if (resources > (host_ce_config_wlan[pipe].src_nentries >> 1))
791 return;
792 }
793 ath10k_ce_per_engine_service(ar, pipe);
794 }
795
796 static void ath10k_pci_hif_set_callbacks(struct ath10k *ar,
797 struct ath10k_hif_cb *callbacks)
798 {
799 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
800
801 ath10k_dbg(ATH10K_DBG_PCI, "%s\n", __func__);
802
803 memcpy(&ar_pci->msg_callbacks_current, callbacks,
804 sizeof(ar_pci->msg_callbacks_current));
805 }
806
807 static int ath10k_pci_start_ce(struct ath10k *ar)
808 {
809 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
810 struct ath10k_ce_pipe *ce_diag = ar_pci->ce_diag;
811 const struct ce_attr *attr;
812 struct ath10k_pci_pipe *pipe_info;
813 struct ath10k_pci_compl *compl;
814 int i, pipe_num, completions, disable_interrupts;
815
816 spin_lock_init(&ar_pci->compl_lock);
817 INIT_LIST_HEAD(&ar_pci->compl_process);
818
819 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
820 pipe_info = &ar_pci->pipe_info[pipe_num];
821
822 spin_lock_init(&pipe_info->pipe_lock);
823 INIT_LIST_HEAD(&pipe_info->compl_free);
824
825 /* Handle Diagnostic CE specially */
826 if (pipe_info->ce_hdl == ce_diag)
827 continue;
828
829 attr = &host_ce_config_wlan[pipe_num];
830 completions = 0;
831
832 if (attr->src_nentries) {
833 disable_interrupts = attr->flags & CE_ATTR_DIS_INTR;
834 ath10k_ce_send_cb_register(pipe_info->ce_hdl,
835 ath10k_pci_ce_send_done,
836 disable_interrupts);
837 completions += attr->src_nentries;
838 }
839
840 if (attr->dest_nentries) {
841 ath10k_ce_recv_cb_register(pipe_info->ce_hdl,
842 ath10k_pci_ce_recv_data);
843 completions += attr->dest_nentries;
844 }
845
846 if (completions == 0)
847 continue;
848
849 for (i = 0; i < completions; i++) {
850 compl = kmalloc(sizeof(*compl), GFP_KERNEL);
851 if (!compl) {
852 ath10k_warn("No memory for completion state\n");
853 ath10k_pci_stop_ce(ar);
854 return -ENOMEM;
855 }
856
857 compl->state = ATH10K_PCI_COMPL_FREE;
858 list_add_tail(&compl->list, &pipe_info->compl_free);
859 }
860 }
861
862 return 0;
863 }
864
865 static void ath10k_pci_kill_tasklet(struct ath10k *ar)
866 {
867 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
868 int i;
869
870 tasklet_kill(&ar_pci->intr_tq);
871 tasklet_kill(&ar_pci->msi_fw_err);
872
873 for (i = 0; i < CE_COUNT; i++)
874 tasklet_kill(&ar_pci->pipe_info[i].intr);
875 }
876
877 static void ath10k_pci_stop_ce(struct ath10k *ar)
878 {
879 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
880 struct ath10k_pci_compl *compl;
881 struct sk_buff *skb;
882
883 ath10k_ce_disable_interrupts(ar);
884 ath10k_pci_kill_tasklet(ar);
885
886 /* Mark pending completions as aborted, so that upper layers free up
887 * their associated resources */
888 spin_lock_bh(&ar_pci->compl_lock);
889 list_for_each_entry(compl, &ar_pci->compl_process, list) {
890 skb = compl->skb;
891 ATH10K_SKB_CB(skb)->is_aborted = true;
892 }
893 spin_unlock_bh(&ar_pci->compl_lock);
894 }
895
896 static void ath10k_pci_cleanup_ce(struct ath10k *ar)
897 {
898 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
899 struct ath10k_pci_compl *compl, *tmp;
900 struct ath10k_pci_pipe *pipe_info;
901 struct sk_buff *netbuf;
902 int pipe_num;
903
904 /* Free pending completions. */
905 spin_lock_bh(&ar_pci->compl_lock);
906 if (!list_empty(&ar_pci->compl_process))
907 ath10k_warn("pending completions still present! possible memory leaks.\n");
908
909 list_for_each_entry_safe(compl, tmp, &ar_pci->compl_process, list) {
910 list_del(&compl->list);
911 netbuf = compl->skb;
912 dev_kfree_skb_any(netbuf);
913 kfree(compl);
914 }
915 spin_unlock_bh(&ar_pci->compl_lock);
916
917 /* Free unused completions for each pipe. */
918 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
919 pipe_info = &ar_pci->pipe_info[pipe_num];
920
921 spin_lock_bh(&pipe_info->pipe_lock);
922 list_for_each_entry_safe(compl, tmp,
923 &pipe_info->compl_free, list) {
924 list_del(&compl->list);
925 kfree(compl);
926 }
927 spin_unlock_bh(&pipe_info->pipe_lock);
928 }
929 }
930
931 static void ath10k_pci_process_ce(struct ath10k *ar)
932 {
933 struct ath10k_pci *ar_pci = ar->hif.priv;
934 struct ath10k_hif_cb *cb = &ar_pci->msg_callbacks_current;
935 struct ath10k_pci_compl *compl;
936 struct sk_buff *skb;
937 unsigned int nbytes;
938 int ret, send_done = 0;
939
940 /* Upper layers aren't ready to handle tx/rx completions in parallel so
941 * we must serialize all completion processing. */
942
943 spin_lock_bh(&ar_pci->compl_lock);
944 if (ar_pci->compl_processing) {
945 spin_unlock_bh(&ar_pci->compl_lock);
946 return;
947 }
948 ar_pci->compl_processing = true;
949 spin_unlock_bh(&ar_pci->compl_lock);
950
951 for (;;) {
952 spin_lock_bh(&ar_pci->compl_lock);
953 if (list_empty(&ar_pci->compl_process)) {
954 spin_unlock_bh(&ar_pci->compl_lock);
955 break;
956 }
957 compl = list_first_entry(&ar_pci->compl_process,
958 struct ath10k_pci_compl, list);
959 list_del(&compl->list);
960 spin_unlock_bh(&ar_pci->compl_lock);
961
962 switch (compl->state) {
963 case ATH10K_PCI_COMPL_SEND:
964 cb->tx_completion(ar,
965 compl->skb,
966 compl->transfer_id);
967 send_done = 1;
968 break;
969 case ATH10K_PCI_COMPL_RECV:
970 ret = ath10k_pci_post_rx_pipe(compl->pipe_info, 1);
971 if (ret) {
972 ath10k_warn("Unable to post recv buffer for pipe: %d\n",
973 compl->pipe_info->pipe_num);
974 break;
975 }
976
977 skb = compl->skb;
978 nbytes = compl->nbytes;
979
980 ath10k_dbg(ATH10K_DBG_PCI,
981 "ath10k_pci_ce_recv_data netbuf=%p nbytes=%d\n",
982 skb, nbytes);
983 ath10k_dbg_dump(ATH10K_DBG_PCI_DUMP, NULL,
984 "ath10k rx: ", skb->data, nbytes);
985
986 if (skb->len + skb_tailroom(skb) >= nbytes) {
987 skb_trim(skb, 0);
988 skb_put(skb, nbytes);
989 cb->rx_completion(ar, skb,
990 compl->pipe_info->pipe_num);
991 } else {
992 ath10k_warn("rxed more than expected (nbytes %d, max %d)",
993 nbytes,
994 skb->len + skb_tailroom(skb));
995 }
996 break;
997 case ATH10K_PCI_COMPL_FREE:
998 ath10k_warn("free completion cannot be processed\n");
999 break;
1000 default:
1001 ath10k_warn("invalid completion state (%d)\n",
1002 compl->state);
1003 break;
1004 }
1005
1006 compl->state = ATH10K_PCI_COMPL_FREE;
1007
1008 /*
1009 * Add completion back to the pipe's free list.
1010 */
1011 spin_lock_bh(&compl->pipe_info->pipe_lock);
1012 list_add_tail(&compl->list, &compl->pipe_info->compl_free);
1013 spin_unlock_bh(&compl->pipe_info->pipe_lock);
1014 }
1015
1016 spin_lock_bh(&ar_pci->compl_lock);
1017 ar_pci->compl_processing = false;
1018 spin_unlock_bh(&ar_pci->compl_lock);
1019 }
1020
1021 /* TODO - temporary mapping while we have too few CE's */
1022 static int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar,
1023 u16 service_id, u8 *ul_pipe,
1024 u8 *dl_pipe, int *ul_is_polled,
1025 int *dl_is_polled)
1026 {
1027 int ret = 0;
1028
1029 /* polling for received messages not supported */
1030 *dl_is_polled = 0;
1031
1032 switch (service_id) {
1033 case ATH10K_HTC_SVC_ID_HTT_DATA_MSG:
1034 /*
1035 * Host->target HTT gets its own pipe, so it can be polled
1036 * while other pipes are interrupt driven.
1037 */
1038 *ul_pipe = 4;
1039 /*
1040 * Use the same target->host pipe for HTC ctrl, HTC raw
1041 * streams, and HTT.
1042 */
1043 *dl_pipe = 1;
1044 break;
1045
1046 case ATH10K_HTC_SVC_ID_RSVD_CTRL:
1047 case ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS:
1048 /*
1049 * Note: HTC_RAW_STREAMS_SVC is currently unused, and
1050 * HTC_CTRL_RSVD_SVC could share the same pipe as the
1051 * WMI services. So, if another CE is needed, change
1052 * this to *ul_pipe = 3, which frees up CE 0.
1053 */
1054 /* *ul_pipe = 3; */
1055 *ul_pipe = 0;
1056 *dl_pipe = 1;
1057 break;
1058
1059 case ATH10K_HTC_SVC_ID_WMI_DATA_BK:
1060 case ATH10K_HTC_SVC_ID_WMI_DATA_BE:
1061 case ATH10K_HTC_SVC_ID_WMI_DATA_VI:
1062 case ATH10K_HTC_SVC_ID_WMI_DATA_VO:
1063
1064 case ATH10K_HTC_SVC_ID_WMI_CONTROL:
1065 *ul_pipe = 3;
1066 *dl_pipe = 2;
1067 break;
1068
1069 /* pipe 5 unused */
1070 /* pipe 6 reserved */
1071 /* pipe 7 reserved */
1072
1073 default:
1074 ret = -1;
1075 break;
1076 }
1077 *ul_is_polled =
1078 (host_ce_config_wlan[*ul_pipe].flags & CE_ATTR_DIS_INTR) != 0;
1079
1080 return ret;
1081 }
1082
1083 static void ath10k_pci_hif_get_default_pipe(struct ath10k *ar,
1084 u8 *ul_pipe, u8 *dl_pipe)
1085 {
1086 int ul_is_polled, dl_is_polled;
1087
1088 (void)ath10k_pci_hif_map_service_to_pipe(ar,
1089 ATH10K_HTC_SVC_ID_RSVD_CTRL,
1090 ul_pipe,
1091 dl_pipe,
1092 &ul_is_polled,
1093 &dl_is_polled);
1094 }
1095
1096 static int ath10k_pci_post_rx_pipe(struct ath10k_pci_pipe *pipe_info,
1097 int num)
1098 {
1099 struct ath10k *ar = pipe_info->hif_ce_state;
1100 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1101 struct ath10k_ce_pipe *ce_state = pipe_info->ce_hdl;
1102 struct sk_buff *skb;
1103 dma_addr_t ce_data;
1104 int i, ret = 0;
1105
1106 if (pipe_info->buf_sz == 0)
1107 return 0;
1108
1109 for (i = 0; i < num; i++) {
1110 skb = dev_alloc_skb(pipe_info->buf_sz);
1111 if (!skb) {
1112 ath10k_warn("could not allocate skbuff for pipe %d\n",
1113 num);
1114 ret = -ENOMEM;
1115 goto err;
1116 }
1117
1118 WARN_ONCE((unsigned long)skb->data & 3, "unaligned skb");
1119
1120 ce_data = dma_map_single(ar->dev, skb->data,
1121 skb->len + skb_tailroom(skb),
1122 DMA_FROM_DEVICE);
1123
1124 if (unlikely(dma_mapping_error(ar->dev, ce_data))) {
1125 ath10k_warn("could not dma map skbuff\n");
1126 dev_kfree_skb_any(skb);
1127 ret = -EIO;
1128 goto err;
1129 }
1130
1131 ATH10K_SKB_CB(skb)->paddr = ce_data;
1132
1133 pci_dma_sync_single_for_device(ar_pci->pdev, ce_data,
1134 pipe_info->buf_sz,
1135 PCI_DMA_FROMDEVICE);
1136
1137 ret = ath10k_ce_recv_buf_enqueue(ce_state, (void *)skb,
1138 ce_data);
1139 if (ret) {
1140 ath10k_warn("could not enqueue to pipe %d (%d)\n",
1141 num, ret);
1142 goto err;
1143 }
1144 }
1145
1146 return ret;
1147
1148 err:
1149 ath10k_pci_rx_pipe_cleanup(pipe_info);
1150 return ret;
1151 }
1152
1153 static int ath10k_pci_post_rx(struct ath10k *ar)
1154 {
1155 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1156 struct ath10k_pci_pipe *pipe_info;
1157 const struct ce_attr *attr;
1158 int pipe_num, ret = 0;
1159
1160 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
1161 pipe_info = &ar_pci->pipe_info[pipe_num];
1162 attr = &host_ce_config_wlan[pipe_num];
1163
1164 if (attr->dest_nentries == 0)
1165 continue;
1166
1167 ret = ath10k_pci_post_rx_pipe(pipe_info,
1168 attr->dest_nentries - 1);
1169 if (ret) {
1170 ath10k_warn("Unable to replenish recv buffers for pipe: %d\n",
1171 pipe_num);
1172
1173 for (; pipe_num >= 0; pipe_num--) {
1174 pipe_info = &ar_pci->pipe_info[pipe_num];
1175 ath10k_pci_rx_pipe_cleanup(pipe_info);
1176 }
1177 return ret;
1178 }
1179 }
1180
1181 return 0;
1182 }
1183
1184 static int ath10k_pci_hif_start(struct ath10k *ar)
1185 {
1186 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1187 int ret;
1188
1189 ret = ath10k_pci_start_ce(ar);
1190 if (ret) {
1191 ath10k_warn("could not start CE (%d)\n", ret);
1192 return ret;
1193 }
1194
1195 /* Post buffers once to start things off. */
1196 ret = ath10k_pci_post_rx(ar);
1197 if (ret) {
1198 ath10k_warn("could not post rx pipes (%d)\n", ret);
1199 return ret;
1200 }
1201
1202 ar_pci->started = 1;
1203 return 0;
1204 }
1205
1206 static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe *pipe_info)
1207 {
1208 struct ath10k *ar;
1209 struct ath10k_pci *ar_pci;
1210 struct ath10k_ce_pipe *ce_hdl;
1211 u32 buf_sz;
1212 struct sk_buff *netbuf;
1213 u32 ce_data;
1214
1215 buf_sz = pipe_info->buf_sz;
1216
1217 /* Unused Copy Engine */
1218 if (buf_sz == 0)
1219 return;
1220
1221 ar = pipe_info->hif_ce_state;
1222 ar_pci = ath10k_pci_priv(ar);
1223
1224 if (!ar_pci->started)
1225 return;
1226
1227 ce_hdl = pipe_info->ce_hdl;
1228
1229 while (ath10k_ce_revoke_recv_next(ce_hdl, (void **)&netbuf,
1230 &ce_data) == 0) {
1231 dma_unmap_single(ar->dev, ATH10K_SKB_CB(netbuf)->paddr,
1232 netbuf->len + skb_tailroom(netbuf),
1233 DMA_FROM_DEVICE);
1234 dev_kfree_skb_any(netbuf);
1235 }
1236 }
1237
1238 static void ath10k_pci_tx_pipe_cleanup(struct ath10k_pci_pipe *pipe_info)
1239 {
1240 struct ath10k *ar;
1241 struct ath10k_pci *ar_pci;
1242 struct ath10k_ce_pipe *ce_hdl;
1243 struct sk_buff *netbuf;
1244 u32 ce_data;
1245 unsigned int nbytes;
1246 unsigned int id;
1247 u32 buf_sz;
1248
1249 buf_sz = pipe_info->buf_sz;
1250
1251 /* Unused Copy Engine */
1252 if (buf_sz == 0)
1253 return;
1254
1255 ar = pipe_info->hif_ce_state;
1256 ar_pci = ath10k_pci_priv(ar);
1257
1258 if (!ar_pci->started)
1259 return;
1260
1261 ce_hdl = pipe_info->ce_hdl;
1262
1263 while (ath10k_ce_cancel_send_next(ce_hdl, (void **)&netbuf,
1264 &ce_data, &nbytes, &id) == 0) {
1265 /*
1266 * Indicate the completion to higer layer to free
1267 * the buffer
1268 */
1269 ATH10K_SKB_CB(netbuf)->is_aborted = true;
1270 ar_pci->msg_callbacks_current.tx_completion(ar,
1271 netbuf,
1272 id);
1273 }
1274 }
1275
1276 /*
1277 * Cleanup residual buffers for device shutdown:
1278 * buffers that were enqueued for receive
1279 * buffers that were to be sent
1280 * Note: Buffers that had completed but which were
1281 * not yet processed are on a completion queue. They
1282 * are handled when the completion thread shuts down.
1283 */
1284 static void ath10k_pci_buffer_cleanup(struct ath10k *ar)
1285 {
1286 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1287 int pipe_num;
1288
1289 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
1290 struct ath10k_pci_pipe *pipe_info;
1291
1292 pipe_info = &ar_pci->pipe_info[pipe_num];
1293 ath10k_pci_rx_pipe_cleanup(pipe_info);
1294 ath10k_pci_tx_pipe_cleanup(pipe_info);
1295 }
1296 }
1297
1298 static void ath10k_pci_ce_deinit(struct ath10k *ar)
1299 {
1300 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1301 struct ath10k_pci_pipe *pipe_info;
1302 int pipe_num;
1303
1304 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
1305 pipe_info = &ar_pci->pipe_info[pipe_num];
1306 if (pipe_info->ce_hdl) {
1307 ath10k_ce_deinit(pipe_info->ce_hdl);
1308 pipe_info->ce_hdl = NULL;
1309 pipe_info->buf_sz = 0;
1310 }
1311 }
1312 }
1313
1314 static void ath10k_pci_disable_irqs(struct ath10k *ar)
1315 {
1316 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1317 int i;
1318
1319 for (i = 0; i < max(1, ar_pci->num_msi_intrs); i++)
1320 disable_irq(ar_pci->pdev->irq + i);
1321 }
1322
1323 static void ath10k_pci_hif_stop(struct ath10k *ar)
1324 {
1325 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1326
1327 ath10k_dbg(ATH10K_DBG_PCI, "%s\n", __func__);
1328
1329 /* Irqs are never explicitly re-enabled. They are implicitly re-enabled
1330 * by ath10k_pci_start_intr(). */
1331 ath10k_pci_disable_irqs(ar);
1332
1333 ath10k_pci_stop_ce(ar);
1334
1335 /* At this point, asynchronous threads are stopped, the target should
1336 * not DMA nor interrupt. We process the leftovers and then free
1337 * everything else up. */
1338
1339 ath10k_pci_process_ce(ar);
1340 ath10k_pci_cleanup_ce(ar);
1341 ath10k_pci_buffer_cleanup(ar);
1342
1343 ar_pci->started = 0;
1344 }
1345
1346 static int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar,
1347 void *req, u32 req_len,
1348 void *resp, u32 *resp_len)
1349 {
1350 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1351 struct ath10k_pci_pipe *pci_tx = &ar_pci->pipe_info[BMI_CE_NUM_TO_TARG];
1352 struct ath10k_pci_pipe *pci_rx = &ar_pci->pipe_info[BMI_CE_NUM_TO_HOST];
1353 struct ath10k_ce_pipe *ce_tx = pci_tx->ce_hdl;
1354 struct ath10k_ce_pipe *ce_rx = pci_rx->ce_hdl;
1355 dma_addr_t req_paddr = 0;
1356 dma_addr_t resp_paddr = 0;
1357 struct bmi_xfer xfer = {};
1358 void *treq, *tresp = NULL;
1359 int ret = 0;
1360
1361 if (resp && !resp_len)
1362 return -EINVAL;
1363
1364 if (resp && resp_len && *resp_len == 0)
1365 return -EINVAL;
1366
1367 treq = kmemdup(req, req_len, GFP_KERNEL);
1368 if (!treq)
1369 return -ENOMEM;
1370
1371 req_paddr = dma_map_single(ar->dev, treq, req_len, DMA_TO_DEVICE);
1372 ret = dma_mapping_error(ar->dev, req_paddr);
1373 if (ret)
1374 goto err_dma;
1375
1376 if (resp && resp_len) {
1377 tresp = kzalloc(*resp_len, GFP_KERNEL);
1378 if (!tresp) {
1379 ret = -ENOMEM;
1380 goto err_req;
1381 }
1382
1383 resp_paddr = dma_map_single(ar->dev, tresp, *resp_len,
1384 DMA_FROM_DEVICE);
1385 ret = dma_mapping_error(ar->dev, resp_paddr);
1386 if (ret)
1387 goto err_req;
1388
1389 xfer.wait_for_resp = true;
1390 xfer.resp_len = 0;
1391
1392 ath10k_ce_recv_buf_enqueue(ce_rx, &xfer, resp_paddr);
1393 }
1394
1395 init_completion(&xfer.done);
1396
1397 ret = ath10k_ce_send(ce_tx, &xfer, req_paddr, req_len, -1, 0);
1398 if (ret)
1399 goto err_resp;
1400
1401 ret = wait_for_completion_timeout(&xfer.done,
1402 BMI_COMMUNICATION_TIMEOUT_HZ);
1403 if (ret <= 0) {
1404 u32 unused_buffer;
1405 unsigned int unused_nbytes;
1406 unsigned int unused_id;
1407
1408 ret = -ETIMEDOUT;
1409 ath10k_ce_cancel_send_next(ce_tx, NULL, &unused_buffer,
1410 &unused_nbytes, &unused_id);
1411 } else {
1412 /* non-zero means we did not time out */
1413 ret = 0;
1414 }
1415
1416 err_resp:
1417 if (resp) {
1418 u32 unused_buffer;
1419
1420 ath10k_ce_revoke_recv_next(ce_rx, NULL, &unused_buffer);
1421 dma_unmap_single(ar->dev, resp_paddr,
1422 *resp_len, DMA_FROM_DEVICE);
1423 }
1424 err_req:
1425 dma_unmap_single(ar->dev, req_paddr, req_len, DMA_TO_DEVICE);
1426
1427 if (ret == 0 && resp_len) {
1428 *resp_len = min(*resp_len, xfer.resp_len);
1429 memcpy(resp, tresp, xfer.resp_len);
1430 }
1431 err_dma:
1432 kfree(treq);
1433 kfree(tresp);
1434
1435 return ret;
1436 }
1437
1438 static void ath10k_pci_bmi_send_done(struct ath10k_ce_pipe *ce_state)
1439 {
1440 struct bmi_xfer *xfer;
1441 u32 ce_data;
1442 unsigned int nbytes;
1443 unsigned int transfer_id;
1444
1445 if (ath10k_ce_completed_send_next(ce_state, (void **)&xfer, &ce_data,
1446 &nbytes, &transfer_id))
1447 return;
1448
1449 if (xfer->wait_for_resp)
1450 return;
1451
1452 complete(&xfer->done);
1453 }
1454
1455 static void ath10k_pci_bmi_recv_data(struct ath10k_ce_pipe *ce_state)
1456 {
1457 struct bmi_xfer *xfer;
1458 u32 ce_data;
1459 unsigned int nbytes;
1460 unsigned int transfer_id;
1461 unsigned int flags;
1462
1463 if (ath10k_ce_completed_recv_next(ce_state, (void **)&xfer, &ce_data,
1464 &nbytes, &transfer_id, &flags))
1465 return;
1466
1467 if (!xfer->wait_for_resp) {
1468 ath10k_warn("unexpected: BMI data received; ignoring\n");
1469 return;
1470 }
1471
1472 xfer->resp_len = nbytes;
1473 complete(&xfer->done);
1474 }
1475
1476 /*
1477 * Map from service/endpoint to Copy Engine.
1478 * This table is derived from the CE_PCI TABLE, above.
1479 * It is passed to the Target at startup for use by firmware.
1480 */
1481 static const struct service_to_pipe target_service_to_ce_map_wlan[] = {
1482 {
1483 ATH10K_HTC_SVC_ID_WMI_DATA_VO,
1484 PIPEDIR_OUT, /* out = UL = host -> target */
1485 3,
1486 },
1487 {
1488 ATH10K_HTC_SVC_ID_WMI_DATA_VO,
1489 PIPEDIR_IN, /* in = DL = target -> host */
1490 2,
1491 },
1492 {
1493 ATH10K_HTC_SVC_ID_WMI_DATA_BK,
1494 PIPEDIR_OUT, /* out = UL = host -> target */
1495 3,
1496 },
1497 {
1498 ATH10K_HTC_SVC_ID_WMI_DATA_BK,
1499 PIPEDIR_IN, /* in = DL = target -> host */
1500 2,
1501 },
1502 {
1503 ATH10K_HTC_SVC_ID_WMI_DATA_BE,
1504 PIPEDIR_OUT, /* out = UL = host -> target */
1505 3,
1506 },
1507 {
1508 ATH10K_HTC_SVC_ID_WMI_DATA_BE,
1509 PIPEDIR_IN, /* in = DL = target -> host */
1510 2,
1511 },
1512 {
1513 ATH10K_HTC_SVC_ID_WMI_DATA_VI,
1514 PIPEDIR_OUT, /* out = UL = host -> target */
1515 3,
1516 },
1517 {
1518 ATH10K_HTC_SVC_ID_WMI_DATA_VI,
1519 PIPEDIR_IN, /* in = DL = target -> host */
1520 2,
1521 },
1522 {
1523 ATH10K_HTC_SVC_ID_WMI_CONTROL,
1524 PIPEDIR_OUT, /* out = UL = host -> target */
1525 3,
1526 },
1527 {
1528 ATH10K_HTC_SVC_ID_WMI_CONTROL,
1529 PIPEDIR_IN, /* in = DL = target -> host */
1530 2,
1531 },
1532 {
1533 ATH10K_HTC_SVC_ID_RSVD_CTRL,
1534 PIPEDIR_OUT, /* out = UL = host -> target */
1535 0, /* could be moved to 3 (share with WMI) */
1536 },
1537 {
1538 ATH10K_HTC_SVC_ID_RSVD_CTRL,
1539 PIPEDIR_IN, /* in = DL = target -> host */
1540 1,
1541 },
1542 {
1543 ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS, /* not currently used */
1544 PIPEDIR_OUT, /* out = UL = host -> target */
1545 0,
1546 },
1547 {
1548 ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS, /* not currently used */
1549 PIPEDIR_IN, /* in = DL = target -> host */
1550 1,
1551 },
1552 {
1553 ATH10K_HTC_SVC_ID_HTT_DATA_MSG,
1554 PIPEDIR_OUT, /* out = UL = host -> target */
1555 4,
1556 },
1557 {
1558 ATH10K_HTC_SVC_ID_HTT_DATA_MSG,
1559 PIPEDIR_IN, /* in = DL = target -> host */
1560 1,
1561 },
1562
1563 /* (Additions here) */
1564
1565 { /* Must be last */
1566 0,
1567 0,
1568 0,
1569 },
1570 };
1571
1572 /*
1573 * Send an interrupt to the device to wake up the Target CPU
1574 * so it has an opportunity to notice any changed state.
1575 */
1576 static int ath10k_pci_wake_target_cpu(struct ath10k *ar)
1577 {
1578 int ret;
1579 u32 core_ctrl;
1580
1581 ret = ath10k_pci_diag_read_access(ar, SOC_CORE_BASE_ADDRESS |
1582 CORE_CTRL_ADDRESS,
1583 &core_ctrl);
1584 if (ret) {
1585 ath10k_warn("Unable to read core ctrl\n");
1586 return ret;
1587 }
1588
1589 /* A_INUM_FIRMWARE interrupt to Target CPU */
1590 core_ctrl |= CORE_CTRL_CPU_INTR_MASK;
1591
1592 ret = ath10k_pci_diag_write_access(ar, SOC_CORE_BASE_ADDRESS |
1593 CORE_CTRL_ADDRESS,
1594 core_ctrl);
1595 if (ret)
1596 ath10k_warn("Unable to set interrupt mask\n");
1597
1598 return ret;
1599 }
1600
1601 static int ath10k_pci_init_config(struct ath10k *ar)
1602 {
1603 u32 interconnect_targ_addr;
1604 u32 pcie_state_targ_addr = 0;
1605 u32 pipe_cfg_targ_addr = 0;
1606 u32 svc_to_pipe_map = 0;
1607 u32 pcie_config_flags = 0;
1608 u32 ealloc_value;
1609 u32 ealloc_targ_addr;
1610 u32 flag2_value;
1611 u32 flag2_targ_addr;
1612 int ret = 0;
1613
1614 /* Download to Target the CE Config and the service-to-CE map */
1615 interconnect_targ_addr =
1616 host_interest_item_address(HI_ITEM(hi_interconnect_state));
1617
1618 /* Supply Target-side CE configuration */
1619 ret = ath10k_pci_diag_read_access(ar, interconnect_targ_addr,
1620 &pcie_state_targ_addr);
1621 if (ret != 0) {
1622 ath10k_err("Failed to get pcie state addr: %d\n", ret);
1623 return ret;
1624 }
1625
1626 if (pcie_state_targ_addr == 0) {
1627 ret = -EIO;
1628 ath10k_err("Invalid pcie state addr\n");
1629 return ret;
1630 }
1631
1632 ret = ath10k_pci_diag_read_access(ar, pcie_state_targ_addr +
1633 offsetof(struct pcie_state,
1634 pipe_cfg_addr),
1635 &pipe_cfg_targ_addr);
1636 if (ret != 0) {
1637 ath10k_err("Failed to get pipe cfg addr: %d\n", ret);
1638 return ret;
1639 }
1640
1641 if (pipe_cfg_targ_addr == 0) {
1642 ret = -EIO;
1643 ath10k_err("Invalid pipe cfg addr\n");
1644 return ret;
1645 }
1646
1647 ret = ath10k_pci_diag_write_mem(ar, pipe_cfg_targ_addr,
1648 target_ce_config_wlan,
1649 sizeof(target_ce_config_wlan));
1650
1651 if (ret != 0) {
1652 ath10k_err("Failed to write pipe cfg: %d\n", ret);
1653 return ret;
1654 }
1655
1656 ret = ath10k_pci_diag_read_access(ar, pcie_state_targ_addr +
1657 offsetof(struct pcie_state,
1658 svc_to_pipe_map),
1659 &svc_to_pipe_map);
1660 if (ret != 0) {
1661 ath10k_err("Failed to get svc/pipe map: %d\n", ret);
1662 return ret;
1663 }
1664
1665 if (svc_to_pipe_map == 0) {
1666 ret = -EIO;
1667 ath10k_err("Invalid svc_to_pipe map\n");
1668 return ret;
1669 }
1670
1671 ret = ath10k_pci_diag_write_mem(ar, svc_to_pipe_map,
1672 target_service_to_ce_map_wlan,
1673 sizeof(target_service_to_ce_map_wlan));
1674 if (ret != 0) {
1675 ath10k_err("Failed to write svc/pipe map: %d\n", ret);
1676 return ret;
1677 }
1678
1679 ret = ath10k_pci_diag_read_access(ar, pcie_state_targ_addr +
1680 offsetof(struct pcie_state,
1681 config_flags),
1682 &pcie_config_flags);
1683 if (ret != 0) {
1684 ath10k_err("Failed to get pcie config_flags: %d\n", ret);
1685 return ret;
1686 }
1687
1688 pcie_config_flags &= ~PCIE_CONFIG_FLAG_ENABLE_L1;
1689
1690 ret = ath10k_pci_diag_write_mem(ar, pcie_state_targ_addr +
1691 offsetof(struct pcie_state, config_flags),
1692 &pcie_config_flags,
1693 sizeof(pcie_config_flags));
1694 if (ret != 0) {
1695 ath10k_err("Failed to write pcie config_flags: %d\n", ret);
1696 return ret;
1697 }
1698
1699 /* configure early allocation */
1700 ealloc_targ_addr = host_interest_item_address(HI_ITEM(hi_early_alloc));
1701
1702 ret = ath10k_pci_diag_read_access(ar, ealloc_targ_addr, &ealloc_value);
1703 if (ret != 0) {
1704 ath10k_err("Faile to get early alloc val: %d\n", ret);
1705 return ret;
1706 }
1707
1708 /* first bank is switched to IRAM */
1709 ealloc_value |= ((HI_EARLY_ALLOC_MAGIC << HI_EARLY_ALLOC_MAGIC_SHIFT) &
1710 HI_EARLY_ALLOC_MAGIC_MASK);
1711 ealloc_value |= ((1 << HI_EARLY_ALLOC_IRAM_BANKS_SHIFT) &
1712 HI_EARLY_ALLOC_IRAM_BANKS_MASK);
1713
1714 ret = ath10k_pci_diag_write_access(ar, ealloc_targ_addr, ealloc_value);
1715 if (ret != 0) {
1716 ath10k_err("Failed to set early alloc val: %d\n", ret);
1717 return ret;
1718 }
1719
1720 /* Tell Target to proceed with initialization */
1721 flag2_targ_addr = host_interest_item_address(HI_ITEM(hi_option_flag2));
1722
1723 ret = ath10k_pci_diag_read_access(ar, flag2_targ_addr, &flag2_value);
1724 if (ret != 0) {
1725 ath10k_err("Failed to get option val: %d\n", ret);
1726 return ret;
1727 }
1728
1729 flag2_value |= HI_OPTION_EARLY_CFG_DONE;
1730
1731 ret = ath10k_pci_diag_write_access(ar, flag2_targ_addr, flag2_value);
1732 if (ret != 0) {
1733 ath10k_err("Failed to set option val: %d\n", ret);
1734 return ret;
1735 }
1736
1737 return 0;
1738 }
1739
1740
1741
1742 static int ath10k_pci_ce_init(struct ath10k *ar)
1743 {
1744 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1745 struct ath10k_pci_pipe *pipe_info;
1746 const struct ce_attr *attr;
1747 int pipe_num;
1748
1749 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
1750 pipe_info = &ar_pci->pipe_info[pipe_num];
1751 pipe_info->pipe_num = pipe_num;
1752 pipe_info->hif_ce_state = ar;
1753 attr = &host_ce_config_wlan[pipe_num];
1754
1755 pipe_info->ce_hdl = ath10k_ce_init(ar, pipe_num, attr);
1756 if (pipe_info->ce_hdl == NULL) {
1757 ath10k_err("Unable to initialize CE for pipe: %d\n",
1758 pipe_num);
1759
1760 /* It is safe to call it here. It checks if ce_hdl is
1761 * valid for each pipe */
1762 ath10k_pci_ce_deinit(ar);
1763 return -1;
1764 }
1765
1766 if (pipe_num == CE_COUNT - 1) {
1767 /*
1768 * Reserve the ultimate CE for
1769 * diagnostic Window support
1770 */
1771 ar_pci->ce_diag = pipe_info->ce_hdl;
1772 continue;
1773 }
1774
1775 pipe_info->buf_sz = (size_t) (attr->src_sz_max);
1776 }
1777
1778 /*
1779 * Initially, establish CE completion handlers for use with BMI.
1780 * These are overwritten with generic handlers after we exit BMI phase.
1781 */
1782 pipe_info = &ar_pci->pipe_info[BMI_CE_NUM_TO_TARG];
1783 ath10k_ce_send_cb_register(pipe_info->ce_hdl,
1784 ath10k_pci_bmi_send_done, 0);
1785
1786 pipe_info = &ar_pci->pipe_info[BMI_CE_NUM_TO_HOST];
1787 ath10k_ce_recv_cb_register(pipe_info->ce_hdl,
1788 ath10k_pci_bmi_recv_data);
1789
1790 return 0;
1791 }
1792
1793 static void ath10k_pci_fw_interrupt_handler(struct ath10k *ar)
1794 {
1795 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1796 u32 fw_indicator_address, fw_indicator;
1797
1798 ath10k_pci_wake(ar);
1799
1800 fw_indicator_address = ar_pci->fw_indicator_address;
1801 fw_indicator = ath10k_pci_read32(ar, fw_indicator_address);
1802
1803 if (fw_indicator & FW_IND_EVENT_PENDING) {
1804 /* ACK: clear Target-side pending event */
1805 ath10k_pci_write32(ar, fw_indicator_address,
1806 fw_indicator & ~FW_IND_EVENT_PENDING);
1807
1808 if (ar_pci->started) {
1809 ath10k_pci_hif_dump_area(ar);
1810 } else {
1811 /*
1812 * Probable Target failure before we're prepared
1813 * to handle it. Generally unexpected.
1814 */
1815 ath10k_warn("early firmware event indicated\n");
1816 }
1817 }
1818
1819 ath10k_pci_sleep(ar);
1820 }
1821
1822 static int ath10k_pci_hif_power_up(struct ath10k *ar)
1823 {
1824 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1825 int ret;
1826
1827 ret = ath10k_pci_start_intr(ar);
1828 if (ret) {
1829 ath10k_err("could not start interrupt handling (%d)\n", ret);
1830 goto err;
1831 }
1832
1833 /*
1834 * Bring the target up cleanly.
1835 *
1836 * The target may be in an undefined state with an AUX-powered Target
1837 * and a Host in WoW mode. If the Host crashes, loses power, or is
1838 * restarted (without unloading the driver) then the Target is left
1839 * (aux) powered and running. On a subsequent driver load, the Target
1840 * is in an unexpected state. We try to catch that here in order to
1841 * reset the Target and retry the probe.
1842 */
1843 ret = ath10k_pci_device_reset(ar);
1844 if (ret) {
1845 ath10k_err("failed to reset target: %d\n", ret);
1846 goto err_irq;
1847 }
1848
1849 ret = ath10k_pci_wait_for_target_init(ar);
1850 if (ret)
1851 goto err_irq;
1852
1853 if (!test_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE, ar_pci->features))
1854 /* Force AWAKE forever */
1855 ath10k_do_pci_wake(ar);
1856
1857 ret = ath10k_pci_ce_init(ar);
1858 if (ret)
1859 goto err_ps;
1860
1861 ret = ath10k_pci_init_config(ar);
1862 if (ret)
1863 goto err_ce;
1864
1865 ret = ath10k_pci_wake_target_cpu(ar);
1866 if (ret) {
1867 ath10k_err("could not wake up target CPU (%d)\n", ret);
1868 goto err_ce;
1869 }
1870
1871 return 0;
1872
1873 err_ce:
1874 ath10k_pci_ce_deinit(ar);
1875 err_ps:
1876 if (!test_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE, ar_pci->features))
1877 ath10k_do_pci_sleep(ar);
1878 err_irq:
1879 ath10k_pci_stop_intr(ar);
1880 err:
1881 return ret;
1882 }
1883
1884 static void ath10k_pci_hif_power_down(struct ath10k *ar)
1885 {
1886 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1887
1888 ath10k_pci_stop_intr(ar);
1889
1890 ath10k_pci_ce_deinit(ar);
1891 if (!test_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE, ar_pci->features))
1892 ath10k_do_pci_sleep(ar);
1893 }
1894
1895 #ifdef CONFIG_PM
1896
1897 #define ATH10K_PCI_PM_CONTROL 0x44
1898
1899 static int ath10k_pci_hif_suspend(struct ath10k *ar)
1900 {
1901 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1902 struct pci_dev *pdev = ar_pci->pdev;
1903 u32 val;
1904
1905 pci_read_config_dword(pdev, ATH10K_PCI_PM_CONTROL, &val);
1906
1907 if ((val & 0x000000ff) != 0x3) {
1908 pci_save_state(pdev);
1909 pci_disable_device(pdev);
1910 pci_write_config_dword(pdev, ATH10K_PCI_PM_CONTROL,
1911 (val & 0xffffff00) | 0x03);
1912 }
1913
1914 return 0;
1915 }
1916
1917 static int ath10k_pci_hif_resume(struct ath10k *ar)
1918 {
1919 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1920 struct pci_dev *pdev = ar_pci->pdev;
1921 u32 val;
1922
1923 pci_read_config_dword(pdev, ATH10K_PCI_PM_CONTROL, &val);
1924
1925 if ((val & 0x000000ff) != 0) {
1926 pci_restore_state(pdev);
1927 pci_write_config_dword(pdev, ATH10K_PCI_PM_CONTROL,
1928 val & 0xffffff00);
1929 /*
1930 * Suspend/Resume resets the PCI configuration space,
1931 * so we have to re-disable the RETRY_TIMEOUT register (0x41)
1932 * to keep PCI Tx retries from interfering with C3 CPU state
1933 */
1934 pci_read_config_dword(pdev, 0x40, &val);
1935
1936 if ((val & 0x0000ff00) != 0)
1937 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
1938 }
1939
1940 return 0;
1941 }
1942 #endif
1943
1944 static const struct ath10k_hif_ops ath10k_pci_hif_ops = {
1945 .send_head = ath10k_pci_hif_send_head,
1946 .exchange_bmi_msg = ath10k_pci_hif_exchange_bmi_msg,
1947 .start = ath10k_pci_hif_start,
1948 .stop = ath10k_pci_hif_stop,
1949 .map_service_to_pipe = ath10k_pci_hif_map_service_to_pipe,
1950 .get_default_pipe = ath10k_pci_hif_get_default_pipe,
1951 .send_complete_check = ath10k_pci_hif_send_complete_check,
1952 .set_callbacks = ath10k_pci_hif_set_callbacks,
1953 .get_free_queue_number = ath10k_pci_hif_get_free_queue_number,
1954 .power_up = ath10k_pci_hif_power_up,
1955 .power_down = ath10k_pci_hif_power_down,
1956 #ifdef CONFIG_PM
1957 .suspend = ath10k_pci_hif_suspend,
1958 .resume = ath10k_pci_hif_resume,
1959 #endif
1960 };
1961
1962 static void ath10k_pci_ce_tasklet(unsigned long ptr)
1963 {
1964 struct ath10k_pci_pipe *pipe = (struct ath10k_pci_pipe *)ptr;
1965 struct ath10k_pci *ar_pci = pipe->ar_pci;
1966
1967 ath10k_ce_per_engine_service(ar_pci->ar, pipe->pipe_num);
1968 }
1969
1970 static void ath10k_msi_err_tasklet(unsigned long data)
1971 {
1972 struct ath10k *ar = (struct ath10k *)data;
1973
1974 ath10k_pci_fw_interrupt_handler(ar);
1975 }
1976
1977 /*
1978 * Handler for a per-engine interrupt on a PARTICULAR CE.
1979 * This is used in cases where each CE has a private MSI interrupt.
1980 */
1981 static irqreturn_t ath10k_pci_per_engine_handler(int irq, void *arg)
1982 {
1983 struct ath10k *ar = arg;
1984 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1985 int ce_id = irq - ar_pci->pdev->irq - MSI_ASSIGN_CE_INITIAL;
1986
1987 if (ce_id < 0 || ce_id >= ARRAY_SIZE(ar_pci->pipe_info)) {
1988 ath10k_warn("unexpected/invalid irq %d ce_id %d\n", irq, ce_id);
1989 return IRQ_HANDLED;
1990 }
1991
1992 /*
1993 * NOTE: We are able to derive ce_id from irq because we
1994 * use a one-to-one mapping for CE's 0..5.
1995 * CE's 6 & 7 do not use interrupts at all.
1996 *
1997 * This mapping must be kept in sync with the mapping
1998 * used by firmware.
1999 */
2000 tasklet_schedule(&ar_pci->pipe_info[ce_id].intr);
2001 return IRQ_HANDLED;
2002 }
2003
2004 static irqreturn_t ath10k_pci_msi_fw_handler(int irq, void *arg)
2005 {
2006 struct ath10k *ar = arg;
2007 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2008
2009 tasklet_schedule(&ar_pci->msi_fw_err);
2010 return IRQ_HANDLED;
2011 }
2012
2013 /*
2014 * Top-level interrupt handler for all PCI interrupts from a Target.
2015 * When a block of MSI interrupts is allocated, this top-level handler
2016 * is not used; instead, we directly call the correct sub-handler.
2017 */
2018 static irqreturn_t ath10k_pci_interrupt_handler(int irq, void *arg)
2019 {
2020 struct ath10k *ar = arg;
2021 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2022
2023 if (ar_pci->num_msi_intrs == 0) {
2024 /*
2025 * IMPORTANT: INTR_CLR regiser has to be set after
2026 * INTR_ENABLE is set to 0, otherwise interrupt can not be
2027 * really cleared.
2028 */
2029 iowrite32(0, ar_pci->mem +
2030 (SOC_CORE_BASE_ADDRESS |
2031 PCIE_INTR_ENABLE_ADDRESS));
2032 iowrite32(PCIE_INTR_FIRMWARE_MASK |
2033 PCIE_INTR_CE_MASK_ALL,
2034 ar_pci->mem + (SOC_CORE_BASE_ADDRESS |
2035 PCIE_INTR_CLR_ADDRESS));
2036 /*
2037 * IMPORTANT: this extra read transaction is required to
2038 * flush the posted write buffer.
2039 */
2040 (void) ioread32(ar_pci->mem +
2041 (SOC_CORE_BASE_ADDRESS |
2042 PCIE_INTR_ENABLE_ADDRESS));
2043 }
2044
2045 tasklet_schedule(&ar_pci->intr_tq);
2046
2047 return IRQ_HANDLED;
2048 }
2049
2050 static void ath10k_pci_tasklet(unsigned long data)
2051 {
2052 struct ath10k *ar = (struct ath10k *)data;
2053 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2054
2055 ath10k_pci_fw_interrupt_handler(ar); /* FIXME: Handle FW error */
2056 ath10k_ce_per_engine_service_any(ar);
2057
2058 if (ar_pci->num_msi_intrs == 0) {
2059 /* Enable Legacy PCI line interrupts */
2060 iowrite32(PCIE_INTR_FIRMWARE_MASK |
2061 PCIE_INTR_CE_MASK_ALL,
2062 ar_pci->mem + (SOC_CORE_BASE_ADDRESS |
2063 PCIE_INTR_ENABLE_ADDRESS));
2064 /*
2065 * IMPORTANT: this extra read transaction is required to
2066 * flush the posted write buffer
2067 */
2068 (void) ioread32(ar_pci->mem +
2069 (SOC_CORE_BASE_ADDRESS |
2070 PCIE_INTR_ENABLE_ADDRESS));
2071 }
2072 }
2073
2074 static int ath10k_pci_start_intr_msix(struct ath10k *ar, int num)
2075 {
2076 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2077 int ret;
2078 int i;
2079
2080 ret = pci_enable_msi_block(ar_pci->pdev, num);
2081 if (ret)
2082 return ret;
2083
2084 ret = request_irq(ar_pci->pdev->irq + MSI_ASSIGN_FW,
2085 ath10k_pci_msi_fw_handler,
2086 IRQF_SHARED, "ath10k_pci", ar);
2087 if (ret) {
2088 ath10k_warn("request_irq(%d) failed %d\n",
2089 ar_pci->pdev->irq + MSI_ASSIGN_FW, ret);
2090
2091 pci_disable_msi(ar_pci->pdev);
2092 return ret;
2093 }
2094
2095 for (i = MSI_ASSIGN_CE_INITIAL; i <= MSI_ASSIGN_CE_MAX; i++) {
2096 ret = request_irq(ar_pci->pdev->irq + i,
2097 ath10k_pci_per_engine_handler,
2098 IRQF_SHARED, "ath10k_pci", ar);
2099 if (ret) {
2100 ath10k_warn("request_irq(%d) failed %d\n",
2101 ar_pci->pdev->irq + i, ret);
2102
2103 for (i--; i >= MSI_ASSIGN_CE_INITIAL; i--)
2104 free_irq(ar_pci->pdev->irq + i, ar);
2105
2106 free_irq(ar_pci->pdev->irq + MSI_ASSIGN_FW, ar);
2107 pci_disable_msi(ar_pci->pdev);
2108 return ret;
2109 }
2110 }
2111
2112 ath10k_info("MSI-X interrupt handling (%d intrs)\n", num);
2113 return 0;
2114 }
2115
2116 static int ath10k_pci_start_intr_msi(struct ath10k *ar)
2117 {
2118 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2119 int ret;
2120
2121 ret = pci_enable_msi(ar_pci->pdev);
2122 if (ret < 0)
2123 return ret;
2124
2125 ret = request_irq(ar_pci->pdev->irq,
2126 ath10k_pci_interrupt_handler,
2127 IRQF_SHARED, "ath10k_pci", ar);
2128 if (ret < 0) {
2129 pci_disable_msi(ar_pci->pdev);
2130 return ret;
2131 }
2132
2133 ath10k_info("MSI interrupt handling\n");
2134 return 0;
2135 }
2136
2137 static int ath10k_pci_start_intr_legacy(struct ath10k *ar)
2138 {
2139 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2140 int ret;
2141
2142 ret = request_irq(ar_pci->pdev->irq,
2143 ath10k_pci_interrupt_handler,
2144 IRQF_SHARED, "ath10k_pci", ar);
2145 if (ret < 0)
2146 return ret;
2147
2148 ret = ath10k_do_pci_wake(ar);
2149 if (ret) {
2150 free_irq(ar_pci->pdev->irq, ar);
2151 ath10k_err("failed to wake up target: %d\n", ret);
2152 return ret;
2153 }
2154
2155 /*
2156 * A potential race occurs here: The CORE_BASE write
2157 * depends on target correctly decoding AXI address but
2158 * host won't know when target writes BAR to CORE_CTRL.
2159 * This write might get lost if target has NOT written BAR.
2160 * For now, fix the race by repeating the write in below
2161 * synchronization checking.
2162 */
2163 iowrite32(PCIE_INTR_FIRMWARE_MASK |
2164 PCIE_INTR_CE_MASK_ALL,
2165 ar_pci->mem + (SOC_CORE_BASE_ADDRESS |
2166 PCIE_INTR_ENABLE_ADDRESS));
2167
2168 ath10k_do_pci_sleep(ar);
2169 ath10k_info("legacy interrupt handling\n");
2170 return 0;
2171 }
2172
2173 static int ath10k_pci_start_intr(struct ath10k *ar)
2174 {
2175 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2176 int num = MSI_NUM_REQUEST;
2177 int ret;
2178 int i;
2179
2180 tasklet_init(&ar_pci->intr_tq, ath10k_pci_tasklet, (unsigned long) ar);
2181 tasklet_init(&ar_pci->msi_fw_err, ath10k_msi_err_tasklet,
2182 (unsigned long) ar);
2183
2184 for (i = 0; i < CE_COUNT; i++) {
2185 ar_pci->pipe_info[i].ar_pci = ar_pci;
2186 tasklet_init(&ar_pci->pipe_info[i].intr,
2187 ath10k_pci_ce_tasklet,
2188 (unsigned long)&ar_pci->pipe_info[i]);
2189 }
2190
2191 if (!test_bit(ATH10K_PCI_FEATURE_MSI_X, ar_pci->features))
2192 num = 1;
2193
2194 if (num > 1) {
2195 ret = ath10k_pci_start_intr_msix(ar, num);
2196 if (ret == 0)
2197 goto exit;
2198
2199 ath10k_warn("MSI-X didn't succeed (%d), trying MSI\n", ret);
2200 num = 1;
2201 }
2202
2203 if (num == 1) {
2204 ret = ath10k_pci_start_intr_msi(ar);
2205 if (ret == 0)
2206 goto exit;
2207
2208 ath10k_warn("MSI didn't succeed (%d), trying legacy INTR\n",
2209 ret);
2210 num = 0;
2211 }
2212
2213 ret = ath10k_pci_start_intr_legacy(ar);
2214 if (ret) {
2215 ath10k_warn("Failed to start legacy interrupts: %d\n", ret);
2216 return ret;
2217 }
2218
2219 exit:
2220 ar_pci->num_msi_intrs = num;
2221 return ret;
2222 }
2223
2224 static void ath10k_pci_stop_intr(struct ath10k *ar)
2225 {
2226 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2227 int i;
2228
2229 /* There's at least one interrupt irregardless whether its legacy INTR
2230 * or MSI or MSI-X */
2231 for (i = 0; i < max(1, ar_pci->num_msi_intrs); i++)
2232 free_irq(ar_pci->pdev->irq + i, ar);
2233
2234 if (ar_pci->num_msi_intrs > 0)
2235 pci_disable_msi(ar_pci->pdev);
2236 }
2237
2238 static int ath10k_pci_wait_for_target_init(struct ath10k *ar)
2239 {
2240 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2241 int wait_limit = 300; /* 3 sec */
2242 int ret;
2243
2244 ret = ath10k_do_pci_wake(ar);
2245 if (ret) {
2246 ath10k_err("failed to wake up target: %d\n", ret);
2247 return ret;
2248 }
2249
2250 while (wait_limit-- &&
2251 !(ioread32(ar_pci->mem + FW_INDICATOR_ADDRESS) &
2252 FW_IND_INITIALIZED)) {
2253 if (ar_pci->num_msi_intrs == 0)
2254 /* Fix potential race by repeating CORE_BASE writes */
2255 iowrite32(PCIE_INTR_FIRMWARE_MASK |
2256 PCIE_INTR_CE_MASK_ALL,
2257 ar_pci->mem + (SOC_CORE_BASE_ADDRESS |
2258 PCIE_INTR_ENABLE_ADDRESS));
2259 mdelay(10);
2260 }
2261
2262 if (wait_limit < 0) {
2263 ath10k_err("target stalled\n");
2264 ret = -EIO;
2265 goto out;
2266 }
2267
2268 out:
2269 ath10k_do_pci_sleep(ar);
2270 return ret;
2271 }
2272
2273 static int ath10k_pci_device_reset(struct ath10k *ar)
2274 {
2275 int i, ret;
2276 u32 val;
2277
2278 ret = ath10k_do_pci_wake(ar);
2279 if (ret) {
2280 ath10k_err("failed to wake up target: %d\n",
2281 ret);
2282 return ret;
2283 }
2284
2285 /* Put Target, including PCIe, into RESET. */
2286 val = ath10k_pci_reg_read32(ar, SOC_GLOBAL_RESET_ADDRESS);
2287 val |= 1;
2288 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val);
2289
2290 for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) {
2291 if (ath10k_pci_reg_read32(ar, RTC_STATE_ADDRESS) &
2292 RTC_STATE_COLD_RESET_MASK)
2293 break;
2294 msleep(1);
2295 }
2296
2297 /* Pull Target, including PCIe, out of RESET. */
2298 val &= ~1;
2299 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val);
2300
2301 for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) {
2302 if (!(ath10k_pci_reg_read32(ar, RTC_STATE_ADDRESS) &
2303 RTC_STATE_COLD_RESET_MASK))
2304 break;
2305 msleep(1);
2306 }
2307
2308 ath10k_do_pci_sleep(ar);
2309 return 0;
2310 }
2311
2312 static void ath10k_pci_dump_features(struct ath10k_pci *ar_pci)
2313 {
2314 int i;
2315
2316 for (i = 0; i < ATH10K_PCI_FEATURE_COUNT; i++) {
2317 if (!test_bit(i, ar_pci->features))
2318 continue;
2319
2320 switch (i) {
2321 case ATH10K_PCI_FEATURE_MSI_X:
2322 ath10k_dbg(ATH10K_DBG_BOOT, "device supports MSI-X\n");
2323 break;
2324 case ATH10K_PCI_FEATURE_SOC_POWER_SAVE:
2325 ath10k_dbg(ATH10K_DBG_BOOT, "QCA98XX SoC power save enabled\n");
2326 break;
2327 }
2328 }
2329 }
2330
2331 static int ath10k_pci_probe(struct pci_dev *pdev,
2332 const struct pci_device_id *pci_dev)
2333 {
2334 void __iomem *mem;
2335 int ret = 0;
2336 struct ath10k *ar;
2337 struct ath10k_pci *ar_pci;
2338 u32 lcr_val, chip_id;
2339
2340 ath10k_dbg(ATH10K_DBG_PCI, "%s\n", __func__);
2341
2342 ar_pci = kzalloc(sizeof(*ar_pci), GFP_KERNEL);
2343 if (ar_pci == NULL)
2344 return -ENOMEM;
2345
2346 ar_pci->pdev = pdev;
2347 ar_pci->dev = &pdev->dev;
2348
2349 switch (pci_dev->device) {
2350 case QCA988X_2_0_DEVICE_ID:
2351 set_bit(ATH10K_PCI_FEATURE_MSI_X, ar_pci->features);
2352 break;
2353 default:
2354 ret = -ENODEV;
2355 ath10k_err("Unkown device ID: %d\n", pci_dev->device);
2356 goto err_ar_pci;
2357 }
2358
2359 if (ath10k_target_ps)
2360 set_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE, ar_pci->features);
2361
2362 ath10k_pci_dump_features(ar_pci);
2363
2364 ar = ath10k_core_create(ar_pci, ar_pci->dev, &ath10k_pci_hif_ops);
2365 if (!ar) {
2366 ath10k_err("ath10k_core_create failed!\n");
2367 ret = -EINVAL;
2368 goto err_ar_pci;
2369 }
2370
2371 ar_pci->ar = ar;
2372 ar_pci->fw_indicator_address = FW_INDICATOR_ADDRESS;
2373 atomic_set(&ar_pci->keep_awake_count, 0);
2374
2375 pci_set_drvdata(pdev, ar);
2376
2377 /*
2378 * Without any knowledge of the Host, the Target may have been reset or
2379 * power cycled and its Config Space may no longer reflect the PCI
2380 * address space that was assigned earlier by the PCI infrastructure.
2381 * Refresh it now.
2382 */
2383 ret = pci_assign_resource(pdev, BAR_NUM);
2384 if (ret) {
2385 ath10k_err("cannot assign PCI space: %d\n", ret);
2386 goto err_ar;
2387 }
2388
2389 ret = pci_enable_device(pdev);
2390 if (ret) {
2391 ath10k_err("cannot enable PCI device: %d\n", ret);
2392 goto err_ar;
2393 }
2394
2395 /* Request MMIO resources */
2396 ret = pci_request_region(pdev, BAR_NUM, "ath");
2397 if (ret) {
2398 ath10k_err("PCI MMIO reservation error: %d\n", ret);
2399 goto err_device;
2400 }
2401
2402 /*
2403 * Target structures have a limit of 32 bit DMA pointers.
2404 * DMA pointers can be wider than 32 bits by default on some systems.
2405 */
2406 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2407 if (ret) {
2408 ath10k_err("32-bit DMA not available: %d\n", ret);
2409 goto err_region;
2410 }
2411
2412 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
2413 if (ret) {
2414 ath10k_err("cannot enable 32-bit consistent DMA\n");
2415 goto err_region;
2416 }
2417
2418 /* Set bus master bit in PCI_COMMAND to enable DMA */
2419 pci_set_master(pdev);
2420
2421 /*
2422 * Temporary FIX: disable ASPM
2423 * Will be removed after the OTP is programmed
2424 */
2425 pci_read_config_dword(pdev, 0x80, &lcr_val);
2426 pci_write_config_dword(pdev, 0x80, (lcr_val & 0xffffff00));
2427
2428 /* Arrange for access to Target SoC registers. */
2429 mem = pci_iomap(pdev, BAR_NUM, 0);
2430 if (!mem) {
2431 ath10k_err("PCI iomap error\n");
2432 ret = -EIO;
2433 goto err_master;
2434 }
2435
2436 ar_pci->mem = mem;
2437
2438 spin_lock_init(&ar_pci->ce_lock);
2439
2440 ret = ath10k_do_pci_wake(ar);
2441 if (ret) {
2442 ath10k_err("Failed to get chip id: %d\n", ret);
2443 goto err_iomap;
2444 }
2445
2446 chip_id = ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS);
2447
2448 ath10k_do_pci_sleep(ar);
2449
2450 ath10k_dbg(ATH10K_DBG_BOOT, "boot pci_mem 0x%p\n", ar_pci->mem);
2451
2452 ret = ath10k_core_register(ar, chip_id);
2453 if (ret) {
2454 ath10k_err("could not register driver core (%d)\n", ret);
2455 goto err_iomap;
2456 }
2457
2458 return 0;
2459
2460 err_iomap:
2461 pci_iounmap(pdev, mem);
2462 err_master:
2463 pci_clear_master(pdev);
2464 err_region:
2465 pci_release_region(pdev, BAR_NUM);
2466 err_device:
2467 pci_disable_device(pdev);
2468 err_ar:
2469 ath10k_core_destroy(ar);
2470 err_ar_pci:
2471 /* call HIF PCI free here */
2472 kfree(ar_pci);
2473
2474 return ret;
2475 }
2476
2477 static void ath10k_pci_remove(struct pci_dev *pdev)
2478 {
2479 struct ath10k *ar = pci_get_drvdata(pdev);
2480 struct ath10k_pci *ar_pci;
2481
2482 ath10k_dbg(ATH10K_DBG_PCI, "%s\n", __func__);
2483
2484 if (!ar)
2485 return;
2486
2487 ar_pci = ath10k_pci_priv(ar);
2488
2489 if (!ar_pci)
2490 return;
2491
2492 tasklet_kill(&ar_pci->msi_fw_err);
2493
2494 ath10k_core_unregister(ar);
2495
2496 pci_iounmap(pdev, ar_pci->mem);
2497 pci_release_region(pdev, BAR_NUM);
2498 pci_clear_master(pdev);
2499 pci_disable_device(pdev);
2500
2501 ath10k_core_destroy(ar);
2502 kfree(ar_pci);
2503 }
2504
2505 MODULE_DEVICE_TABLE(pci, ath10k_pci_id_table);
2506
2507 static struct pci_driver ath10k_pci_driver = {
2508 .name = "ath10k_pci",
2509 .id_table = ath10k_pci_id_table,
2510 .probe = ath10k_pci_probe,
2511 .remove = ath10k_pci_remove,
2512 };
2513
2514 static int __init ath10k_pci_init(void)
2515 {
2516 int ret;
2517
2518 ret = pci_register_driver(&ath10k_pci_driver);
2519 if (ret)
2520 ath10k_err("pci_register_driver failed [%d]\n", ret);
2521
2522 return ret;
2523 }
2524 module_init(ath10k_pci_init);
2525
2526 static void __exit ath10k_pci_exit(void)
2527 {
2528 pci_unregister_driver(&ath10k_pci_driver);
2529 }
2530
2531 module_exit(ath10k_pci_exit);
2532
2533 MODULE_AUTHOR("Qualcomm Atheros");
2534 MODULE_DESCRIPTION("Driver support for Atheros QCA988X PCIe devices");
2535 MODULE_LICENSE("Dual BSD/GPL");
2536 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_FW_FILE);
2537 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_OTP_FILE);
2538 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_BOARD_DATA_FILE);
Linux kernel - Deliverables
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