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ath10k: show hardware and firmware info prints only once
[deliverable/linux.git] / drivers / net / wireless / ath / ath10k / pci.c
1 /*
2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18 #include <linux/pci.h>
19 #include <linux/module.h>
20 #include <linux/interrupt.h>
21 #include <linux/spinlock.h>
22 #include <linux/bitops.h>
23
24 #include "core.h"
25 #include "debug.h"
26
27 #include "targaddrs.h"
28 #include "bmi.h"
29
30 #include "hif.h"
31 #include "htc.h"
32
33 #include "ce.h"
34 #include "pci.h"
35
36 static unsigned int ath10k_target_ps;
37 module_param(ath10k_target_ps, uint, 0644);
38 MODULE_PARM_DESC(ath10k_target_ps, "Enable ath10k Target (SoC) PS option");
39
40 #define QCA988X_2_0_DEVICE_ID (0x003c)
41
42 static DEFINE_PCI_DEVICE_TABLE(ath10k_pci_id_table) = {
43 { PCI_VDEVICE(ATHEROS, QCA988X_2_0_DEVICE_ID) }, /* PCI-E QCA988X V2 */
44 {0}
45 };
46
47 static int ath10k_pci_diag_read_access(struct ath10k *ar, u32 address,
48 u32 *data);
49
50 static void ath10k_pci_process_ce(struct ath10k *ar);
51 static int ath10k_pci_post_rx(struct ath10k *ar);
52 static int ath10k_pci_post_rx_pipe(struct ath10k_pci_pipe *pipe_info,
53 int num);
54 static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe *pipe_info);
55 static void ath10k_pci_stop_ce(struct ath10k *ar);
56 static int ath10k_pci_device_reset(struct ath10k *ar);
57 static int ath10k_pci_wait_for_target_init(struct ath10k *ar);
58 static int ath10k_pci_start_intr(struct ath10k *ar);
59 static void ath10k_pci_stop_intr(struct ath10k *ar);
60
61 static const struct ce_attr host_ce_config_wlan[] = {
62 /* CE0: host->target HTC control and raw streams */
63 {
64 .flags = CE_ATTR_FLAGS,
65 .src_nentries = 16,
66 .src_sz_max = 256,
67 .dest_nentries = 0,
68 },
69
70 /* CE1: target->host HTT + HTC control */
71 {
72 .flags = CE_ATTR_FLAGS,
73 .src_nentries = 0,
74 .src_sz_max = 512,
75 .dest_nentries = 512,
76 },
77
78 /* CE2: target->host WMI */
79 {
80 .flags = CE_ATTR_FLAGS,
81 .src_nentries = 0,
82 .src_sz_max = 2048,
83 .dest_nentries = 32,
84 },
85
86 /* CE3: host->target WMI */
87 {
88 .flags = CE_ATTR_FLAGS,
89 .src_nentries = 32,
90 .src_sz_max = 2048,
91 .dest_nentries = 0,
92 },
93
94 /* CE4: host->target HTT */
95 {
96 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
97 .src_nentries = CE_HTT_H2T_MSG_SRC_NENTRIES,
98 .src_sz_max = 256,
99 .dest_nentries = 0,
100 },
101
102 /* CE5: unused */
103 {
104 .flags = CE_ATTR_FLAGS,
105 .src_nentries = 0,
106 .src_sz_max = 0,
107 .dest_nentries = 0,
108 },
109
110 /* CE6: target autonomous hif_memcpy */
111 {
112 .flags = CE_ATTR_FLAGS,
113 .src_nentries = 0,
114 .src_sz_max = 0,
115 .dest_nentries = 0,
116 },
117
118 /* CE7: ce_diag, the Diagnostic Window */
119 {
120 .flags = CE_ATTR_FLAGS,
121 .src_nentries = 2,
122 .src_sz_max = DIAG_TRANSFER_LIMIT,
123 .dest_nentries = 2,
124 },
125 };
126
127 /* Target firmware's Copy Engine configuration. */
128 static const struct ce_pipe_config target_ce_config_wlan[] = {
129 /* CE0: host->target HTC control and raw streams */
130 {
131 .pipenum = 0,
132 .pipedir = PIPEDIR_OUT,
133 .nentries = 32,
134 .nbytes_max = 256,
135 .flags = CE_ATTR_FLAGS,
136 .reserved = 0,
137 },
138
139 /* CE1: target->host HTT + HTC control */
140 {
141 .pipenum = 1,
142 .pipedir = PIPEDIR_IN,
143 .nentries = 32,
144 .nbytes_max = 512,
145 .flags = CE_ATTR_FLAGS,
146 .reserved = 0,
147 },
148
149 /* CE2: target->host WMI */
150 {
151 .pipenum = 2,
152 .pipedir = PIPEDIR_IN,
153 .nentries = 32,
154 .nbytes_max = 2048,
155 .flags = CE_ATTR_FLAGS,
156 .reserved = 0,
157 },
158
159 /* CE3: host->target WMI */
160 {
161 .pipenum = 3,
162 .pipedir = PIPEDIR_OUT,
163 .nentries = 32,
164 .nbytes_max = 2048,
165 .flags = CE_ATTR_FLAGS,
166 .reserved = 0,
167 },
168
169 /* CE4: host->target HTT */
170 {
171 .pipenum = 4,
172 .pipedir = PIPEDIR_OUT,
173 .nentries = 256,
174 .nbytes_max = 256,
175 .flags = CE_ATTR_FLAGS,
176 .reserved = 0,
177 },
178
179 /* NB: 50% of src nentries, since tx has 2 frags */
180
181 /* CE5: unused */
182 {
183 .pipenum = 5,
184 .pipedir = PIPEDIR_OUT,
185 .nentries = 32,
186 .nbytes_max = 2048,
187 .flags = CE_ATTR_FLAGS,
188 .reserved = 0,
189 },
190
191 /* CE6: Reserved for target autonomous hif_memcpy */
192 {
193 .pipenum = 6,
194 .pipedir = PIPEDIR_INOUT,
195 .nentries = 32,
196 .nbytes_max = 4096,
197 .flags = CE_ATTR_FLAGS,
198 .reserved = 0,
199 },
200
201 /* CE7 used only by Host */
202 };
203
204 /*
205 * Diagnostic read/write access is provided for startup/config/debug usage.
206 * Caller must guarantee proper alignment, when applicable, and single user
207 * at any moment.
208 */
209 static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, void *data,
210 int nbytes)
211 {
212 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
213 int ret = 0;
214 u32 buf;
215 unsigned int completed_nbytes, orig_nbytes, remaining_bytes;
216 unsigned int id;
217 unsigned int flags;
218 struct ath10k_ce_pipe *ce_diag;
219 /* Host buffer address in CE space */
220 u32 ce_data;
221 dma_addr_t ce_data_base = 0;
222 void *data_buf = NULL;
223 int i;
224
225 /*
226 * This code cannot handle reads to non-memory space. Redirect to the
227 * register read fn but preserve the multi word read capability of
228 * this fn
229 */
230 if (address < DRAM_BASE_ADDRESS) {
231 if (!IS_ALIGNED(address, 4) ||
232 !IS_ALIGNED((unsigned long)data, 4))
233 return -EIO;
234
235 while ((nbytes >= 4) && ((ret = ath10k_pci_diag_read_access(
236 ar, address, (u32 *)data)) == 0)) {
237 nbytes -= sizeof(u32);
238 address += sizeof(u32);
239 data += sizeof(u32);
240 }
241 return ret;
242 }
243
244 ce_diag = ar_pci->ce_diag;
245
246 /*
247 * Allocate a temporary bounce buffer to hold caller's data
248 * to be DMA'ed from Target. This guarantees
249 * 1) 4-byte alignment
250 * 2) Buffer in DMA-able space
251 */
252 orig_nbytes = nbytes;
253 data_buf = (unsigned char *)pci_alloc_consistent(ar_pci->pdev,
254 orig_nbytes,
255 &ce_data_base);
256
257 if (!data_buf) {
258 ret = -ENOMEM;
259 goto done;
260 }
261 memset(data_buf, 0, orig_nbytes);
262
263 remaining_bytes = orig_nbytes;
264 ce_data = ce_data_base;
265 while (remaining_bytes) {
266 nbytes = min_t(unsigned int, remaining_bytes,
267 DIAG_TRANSFER_LIMIT);
268
269 ret = ath10k_ce_recv_buf_enqueue(ce_diag, NULL, ce_data);
270 if (ret != 0)
271 goto done;
272
273 /* Request CE to send from Target(!) address to Host buffer */
274 /*
275 * The address supplied by the caller is in the
276 * Target CPU virtual address space.
277 *
278 * In order to use this address with the diagnostic CE,
279 * convert it from Target CPU virtual address space
280 * to CE address space
281 */
282 ath10k_pci_wake(ar);
283 address = TARG_CPU_SPACE_TO_CE_SPACE(ar, ar_pci->mem,
284 address);
285 ath10k_pci_sleep(ar);
286
287 ret = ath10k_ce_send(ce_diag, NULL, (u32)address, nbytes, 0,
288 0);
289 if (ret)
290 goto done;
291
292 i = 0;
293 while (ath10k_ce_completed_send_next(ce_diag, NULL, &buf,
294 &completed_nbytes,
295 &id) != 0) {
296 mdelay(1);
297 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
298 ret = -EBUSY;
299 goto done;
300 }
301 }
302
303 if (nbytes != completed_nbytes) {
304 ret = -EIO;
305 goto done;
306 }
307
308 if (buf != (u32) address) {
309 ret = -EIO;
310 goto done;
311 }
312
313 i = 0;
314 while (ath10k_ce_completed_recv_next(ce_diag, NULL, &buf,
315 &completed_nbytes,
316 &id, &flags) != 0) {
317 mdelay(1);
318
319 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
320 ret = -EBUSY;
321 goto done;
322 }
323 }
324
325 if (nbytes != completed_nbytes) {
326 ret = -EIO;
327 goto done;
328 }
329
330 if (buf != ce_data) {
331 ret = -EIO;
332 goto done;
333 }
334
335 remaining_bytes -= nbytes;
336 address += nbytes;
337 ce_data += nbytes;
338 }
339
340 done:
341 if (ret == 0) {
342 /* Copy data from allocated DMA buf to caller's buf */
343 WARN_ON_ONCE(orig_nbytes & 3);
344 for (i = 0; i < orig_nbytes / sizeof(__le32); i++) {
345 ((u32 *)data)[i] =
346 __le32_to_cpu(((__le32 *)data_buf)[i]);
347 }
348 } else
349 ath10k_dbg(ATH10K_DBG_PCI, "%s failure (0x%x)\n",
350 __func__, address);
351
352 if (data_buf)
353 pci_free_consistent(ar_pci->pdev, orig_nbytes,
354 data_buf, ce_data_base);
355
356 return ret;
357 }
358
359 /* Read 4-byte aligned data from Target memory or register */
360 static int ath10k_pci_diag_read_access(struct ath10k *ar, u32 address,
361 u32 *data)
362 {
363 /* Assume range doesn't cross this boundary */
364 if (address >= DRAM_BASE_ADDRESS)
365 return ath10k_pci_diag_read_mem(ar, address, data, sizeof(u32));
366
367 ath10k_pci_wake(ar);
368 *data = ath10k_pci_read32(ar, address);
369 ath10k_pci_sleep(ar);
370 return 0;
371 }
372
373 static int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address,
374 const void *data, int nbytes)
375 {
376 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
377 int ret = 0;
378 u32 buf;
379 unsigned int completed_nbytes, orig_nbytes, remaining_bytes;
380 unsigned int id;
381 unsigned int flags;
382 struct ath10k_ce_pipe *ce_diag;
383 void *data_buf = NULL;
384 u32 ce_data; /* Host buffer address in CE space */
385 dma_addr_t ce_data_base = 0;
386 int i;
387
388 ce_diag = ar_pci->ce_diag;
389
390 /*
391 * Allocate a temporary bounce buffer to hold caller's data
392 * to be DMA'ed to Target. This guarantees
393 * 1) 4-byte alignment
394 * 2) Buffer in DMA-able space
395 */
396 orig_nbytes = nbytes;
397 data_buf = (unsigned char *)pci_alloc_consistent(ar_pci->pdev,
398 orig_nbytes,
399 &ce_data_base);
400 if (!data_buf) {
401 ret = -ENOMEM;
402 goto done;
403 }
404
405 /* Copy caller's data to allocated DMA buf */
406 WARN_ON_ONCE(orig_nbytes & 3);
407 for (i = 0; i < orig_nbytes / sizeof(__le32); i++)
408 ((__le32 *)data_buf)[i] = __cpu_to_le32(((u32 *)data)[i]);
409
410 /*
411 * The address supplied by the caller is in the
412 * Target CPU virtual address space.
413 *
414 * In order to use this address with the diagnostic CE,
415 * convert it from
416 * Target CPU virtual address space
417 * to
418 * CE address space
419 */
420 ath10k_pci_wake(ar);
421 address = TARG_CPU_SPACE_TO_CE_SPACE(ar, ar_pci->mem, address);
422 ath10k_pci_sleep(ar);
423
424 remaining_bytes = orig_nbytes;
425 ce_data = ce_data_base;
426 while (remaining_bytes) {
427 /* FIXME: check cast */
428 nbytes = min_t(int, remaining_bytes, DIAG_TRANSFER_LIMIT);
429
430 /* Set up to receive directly into Target(!) address */
431 ret = ath10k_ce_recv_buf_enqueue(ce_diag, NULL, address);
432 if (ret != 0)
433 goto done;
434
435 /*
436 * Request CE to send caller-supplied data that
437 * was copied to bounce buffer to Target(!) address.
438 */
439 ret = ath10k_ce_send(ce_diag, NULL, (u32) ce_data,
440 nbytes, 0, 0);
441 if (ret != 0)
442 goto done;
443
444 i = 0;
445 while (ath10k_ce_completed_send_next(ce_diag, NULL, &buf,
446 &completed_nbytes,
447 &id) != 0) {
448 mdelay(1);
449
450 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
451 ret = -EBUSY;
452 goto done;
453 }
454 }
455
456 if (nbytes != completed_nbytes) {
457 ret = -EIO;
458 goto done;
459 }
460
461 if (buf != ce_data) {
462 ret = -EIO;
463 goto done;
464 }
465
466 i = 0;
467 while (ath10k_ce_completed_recv_next(ce_diag, NULL, &buf,
468 &completed_nbytes,
469 &id, &flags) != 0) {
470 mdelay(1);
471
472 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
473 ret = -EBUSY;
474 goto done;
475 }
476 }
477
478 if (nbytes != completed_nbytes) {
479 ret = -EIO;
480 goto done;
481 }
482
483 if (buf != address) {
484 ret = -EIO;
485 goto done;
486 }
487
488 remaining_bytes -= nbytes;
489 address += nbytes;
490 ce_data += nbytes;
491 }
492
493 done:
494 if (data_buf) {
495 pci_free_consistent(ar_pci->pdev, orig_nbytes, data_buf,
496 ce_data_base);
497 }
498
499 if (ret != 0)
500 ath10k_dbg(ATH10K_DBG_PCI, "%s failure (0x%x)\n", __func__,
501 address);
502
503 return ret;
504 }
505
506 /* Write 4B data to Target memory or register */
507 static int ath10k_pci_diag_write_access(struct ath10k *ar, u32 address,
508 u32 data)
509 {
510 /* Assume range doesn't cross this boundary */
511 if (address >= DRAM_BASE_ADDRESS)
512 return ath10k_pci_diag_write_mem(ar, address, &data,
513 sizeof(u32));
514
515 ath10k_pci_wake(ar);
516 ath10k_pci_write32(ar, address, data);
517 ath10k_pci_sleep(ar);
518 return 0;
519 }
520
521 static bool ath10k_pci_target_is_awake(struct ath10k *ar)
522 {
523 void __iomem *mem = ath10k_pci_priv(ar)->mem;
524 u32 val;
525 val = ioread32(mem + PCIE_LOCAL_BASE_ADDRESS +
526 RTC_STATE_ADDRESS);
527 return (RTC_STATE_V_GET(val) == RTC_STATE_V_ON);
528 }
529
530 int ath10k_do_pci_wake(struct ath10k *ar)
531 {
532 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
533 void __iomem *pci_addr = ar_pci->mem;
534 int tot_delay = 0;
535 int curr_delay = 5;
536
537 if (atomic_read(&ar_pci->keep_awake_count) == 0) {
538 /* Force AWAKE */
539 iowrite32(PCIE_SOC_WAKE_V_MASK,
540 pci_addr + PCIE_LOCAL_BASE_ADDRESS +
541 PCIE_SOC_WAKE_ADDRESS);
542 }
543 atomic_inc(&ar_pci->keep_awake_count);
544
545 if (ar_pci->verified_awake)
546 return 0;
547
548 for (;;) {
549 if (ath10k_pci_target_is_awake(ar)) {
550 ar_pci->verified_awake = true;
551 return 0;
552 }
553
554 if (tot_delay > PCIE_WAKE_TIMEOUT) {
555 ath10k_warn("target took longer %d us to wake up (awake count %d)\n",
556 PCIE_WAKE_TIMEOUT,
557 atomic_read(&ar_pci->keep_awake_count));
558 return -ETIMEDOUT;
559 }
560
561 udelay(curr_delay);
562 tot_delay += curr_delay;
563
564 if (curr_delay < 50)
565 curr_delay += 5;
566 }
567 }
568
569 void ath10k_do_pci_sleep(struct ath10k *ar)
570 {
571 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
572 void __iomem *pci_addr = ar_pci->mem;
573
574 if (atomic_dec_and_test(&ar_pci->keep_awake_count)) {
575 /* Allow sleep */
576 ar_pci->verified_awake = false;
577 iowrite32(PCIE_SOC_WAKE_RESET,
578 pci_addr + PCIE_LOCAL_BASE_ADDRESS +
579 PCIE_SOC_WAKE_ADDRESS);
580 }
581 }
582
583 /*
584 * FIXME: Handle OOM properly.
585 */
586 static inline
587 struct ath10k_pci_compl *get_free_compl(struct ath10k_pci_pipe *pipe_info)
588 {
589 struct ath10k_pci_compl *compl = NULL;
590
591 spin_lock_bh(&pipe_info->pipe_lock);
592 if (list_empty(&pipe_info->compl_free)) {
593 ath10k_warn("Completion buffers are full\n");
594 goto exit;
595 }
596 compl = list_first_entry(&pipe_info->compl_free,
597 struct ath10k_pci_compl, list);
598 list_del(&compl->list);
599 exit:
600 spin_unlock_bh(&pipe_info->pipe_lock);
601 return compl;
602 }
603
604 /* Called by lower (CE) layer when a send to Target completes. */
605 static void ath10k_pci_ce_send_done(struct ath10k_ce_pipe *ce_state)
606 {
607 struct ath10k *ar = ce_state->ar;
608 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
609 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id];
610 struct ath10k_pci_compl *compl;
611 void *transfer_context;
612 u32 ce_data;
613 unsigned int nbytes;
614 unsigned int transfer_id;
615
616 while (ath10k_ce_completed_send_next(ce_state, &transfer_context,
617 &ce_data, &nbytes,
618 &transfer_id) == 0) {
619 compl = get_free_compl(pipe_info);
620 if (!compl)
621 break;
622
623 compl->state = ATH10K_PCI_COMPL_SEND;
624 compl->ce_state = ce_state;
625 compl->pipe_info = pipe_info;
626 compl->skb = transfer_context;
627 compl->nbytes = nbytes;
628 compl->transfer_id = transfer_id;
629 compl->flags = 0;
630
631 /*
632 * Add the completion to the processing queue.
633 */
634 spin_lock_bh(&ar_pci->compl_lock);
635 list_add_tail(&compl->list, &ar_pci->compl_process);
636 spin_unlock_bh(&ar_pci->compl_lock);
637 }
638
639 ath10k_pci_process_ce(ar);
640 }
641
642 /* Called by lower (CE) layer when data is received from the Target. */
643 static void ath10k_pci_ce_recv_data(struct ath10k_ce_pipe *ce_state)
644 {
645 struct ath10k *ar = ce_state->ar;
646 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
647 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id];
648 struct ath10k_pci_compl *compl;
649 struct sk_buff *skb;
650 void *transfer_context;
651 u32 ce_data;
652 unsigned int nbytes;
653 unsigned int transfer_id;
654 unsigned int flags;
655
656 while (ath10k_ce_completed_recv_next(ce_state, &transfer_context,
657 &ce_data, &nbytes, &transfer_id,
658 &flags) == 0) {
659 compl = get_free_compl(pipe_info);
660 if (!compl)
661 break;
662
663 compl->state = ATH10K_PCI_COMPL_RECV;
664 compl->ce_state = ce_state;
665 compl->pipe_info = pipe_info;
666 compl->skb = transfer_context;
667 compl->nbytes = nbytes;
668 compl->transfer_id = transfer_id;
669 compl->flags = flags;
670
671 skb = transfer_context;
672 dma_unmap_single(ar->dev, ATH10K_SKB_CB(skb)->paddr,
673 skb->len + skb_tailroom(skb),
674 DMA_FROM_DEVICE);
675 /*
676 * Add the completion to the processing queue.
677 */
678 spin_lock_bh(&ar_pci->compl_lock);
679 list_add_tail(&compl->list, &ar_pci->compl_process);
680 spin_unlock_bh(&ar_pci->compl_lock);
681 }
682
683 ath10k_pci_process_ce(ar);
684 }
685
686 /* Send the first nbytes bytes of the buffer */
687 static int ath10k_pci_hif_send_head(struct ath10k *ar, u8 pipe_id,
688 unsigned int transfer_id,
689 unsigned int bytes, struct sk_buff *nbuf)
690 {
691 struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(nbuf);
692 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
693 struct ath10k_pci_pipe *pipe_info = &(ar_pci->pipe_info[pipe_id]);
694 struct ath10k_ce_pipe *ce_hdl = pipe_info->ce_hdl;
695 unsigned int len;
696 u32 flags = 0;
697 int ret;
698
699 len = min(bytes, nbuf->len);
700 bytes -= len;
701
702 if (len & 3)
703 ath10k_warn("skb not aligned to 4-byte boundary (%d)\n", len);
704
705 ath10k_dbg(ATH10K_DBG_PCI,
706 "pci send data vaddr %p paddr 0x%llx len %d as %d bytes\n",
707 nbuf->data, (unsigned long long) skb_cb->paddr,
708 nbuf->len, len);
709 ath10k_dbg_dump(ATH10K_DBG_PCI_DUMP, NULL,
710 "ath10k tx: data: ",
711 nbuf->data, nbuf->len);
712
713 ret = ath10k_ce_send(ce_hdl, nbuf, skb_cb->paddr, len, transfer_id,
714 flags);
715 if (ret)
716 ath10k_warn("failed to send sk_buff to CE: %p\n", nbuf);
717
718 return ret;
719 }
720
721 static u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe)
722 {
723 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
724 return ath10k_ce_num_free_src_entries(ar_pci->pipe_info[pipe].ce_hdl);
725 }
726
727 static void ath10k_pci_hif_dump_area(struct ath10k *ar)
728 {
729 u32 reg_dump_area = 0;
730 u32 reg_dump_values[REG_DUMP_COUNT_QCA988X] = {};
731 u32 host_addr;
732 int ret;
733 u32 i;
734
735 ath10k_err("firmware crashed!\n");
736 ath10k_err("hardware name %s version 0x%x\n",
737 ar->hw_params.name, ar->target_version);
738 ath10k_err("firmware version: %u.%u.%u.%u\n", ar->fw_version_major,
739 ar->fw_version_minor, ar->fw_version_release,
740 ar->fw_version_build);
741
742 host_addr = host_interest_item_address(HI_ITEM(hi_failure_state));
743 ret = ath10k_pci_diag_read_mem(ar, host_addr,
744 &reg_dump_area, sizeof(u32));
745 if (ret) {
746 ath10k_err("failed to read FW dump area address: %d\n", ret);
747 return;
748 }
749
750 ath10k_err("target register Dump Location: 0x%08X\n", reg_dump_area);
751
752 ret = ath10k_pci_diag_read_mem(ar, reg_dump_area,
753 &reg_dump_values[0],
754 REG_DUMP_COUNT_QCA988X * sizeof(u32));
755 if (ret != 0) {
756 ath10k_err("failed to read FW dump area: %d\n", ret);
757 return;
758 }
759
760 BUILD_BUG_ON(REG_DUMP_COUNT_QCA988X % 4);
761
762 ath10k_err("target Register Dump\n");
763 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i += 4)
764 ath10k_err("[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X\n",
765 i,
766 reg_dump_values[i],
767 reg_dump_values[i + 1],
768 reg_dump_values[i + 2],
769 reg_dump_values[i + 3]);
770
771 queue_work(ar->workqueue, &ar->restart_work);
772 }
773
774 static void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe,
775 int force)
776 {
777 if (!force) {
778 int resources;
779 /*
780 * Decide whether to actually poll for completions, or just
781 * wait for a later chance.
782 * If there seem to be plenty of resources left, then just wait
783 * since checking involves reading a CE register, which is a
784 * relatively expensive operation.
785 */
786 resources = ath10k_pci_hif_get_free_queue_number(ar, pipe);
787
788 /*
789 * If at least 50% of the total resources are still available,
790 * don't bother checking again yet.
791 */
792 if (resources > (host_ce_config_wlan[pipe].src_nentries >> 1))
793 return;
794 }
795 ath10k_ce_per_engine_service(ar, pipe);
796 }
797
798 static void ath10k_pci_hif_set_callbacks(struct ath10k *ar,
799 struct ath10k_hif_cb *callbacks)
800 {
801 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
802
803 ath10k_dbg(ATH10K_DBG_PCI, "%s\n", __func__);
804
805 memcpy(&ar_pci->msg_callbacks_current, callbacks,
806 sizeof(ar_pci->msg_callbacks_current));
807 }
808
809 static int ath10k_pci_start_ce(struct ath10k *ar)
810 {
811 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
812 struct ath10k_ce_pipe *ce_diag = ar_pci->ce_diag;
813 const struct ce_attr *attr;
814 struct ath10k_pci_pipe *pipe_info;
815 struct ath10k_pci_compl *compl;
816 int i, pipe_num, completions, disable_interrupts;
817
818 spin_lock_init(&ar_pci->compl_lock);
819 INIT_LIST_HEAD(&ar_pci->compl_process);
820
821 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
822 pipe_info = &ar_pci->pipe_info[pipe_num];
823
824 spin_lock_init(&pipe_info->pipe_lock);
825 INIT_LIST_HEAD(&pipe_info->compl_free);
826
827 /* Handle Diagnostic CE specially */
828 if (pipe_info->ce_hdl == ce_diag)
829 continue;
830
831 attr = &host_ce_config_wlan[pipe_num];
832 completions = 0;
833
834 if (attr->src_nentries) {
835 disable_interrupts = attr->flags & CE_ATTR_DIS_INTR;
836 ath10k_ce_send_cb_register(pipe_info->ce_hdl,
837 ath10k_pci_ce_send_done,
838 disable_interrupts);
839 completions += attr->src_nentries;
840 }
841
842 if (attr->dest_nentries) {
843 ath10k_ce_recv_cb_register(pipe_info->ce_hdl,
844 ath10k_pci_ce_recv_data);
845 completions += attr->dest_nentries;
846 }
847
848 if (completions == 0)
849 continue;
850
851 for (i = 0; i < completions; i++) {
852 compl = kmalloc(sizeof(*compl), GFP_KERNEL);
853 if (!compl) {
854 ath10k_warn("No memory for completion state\n");
855 ath10k_pci_stop_ce(ar);
856 return -ENOMEM;
857 }
858
859 compl->state = ATH10K_PCI_COMPL_FREE;
860 list_add_tail(&compl->list, &pipe_info->compl_free);
861 }
862 }
863
864 return 0;
865 }
866
867 static void ath10k_pci_kill_tasklet(struct ath10k *ar)
868 {
869 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
870 int i;
871
872 tasklet_kill(&ar_pci->intr_tq);
873 tasklet_kill(&ar_pci->msi_fw_err);
874
875 for (i = 0; i < CE_COUNT; i++)
876 tasklet_kill(&ar_pci->pipe_info[i].intr);
877 }
878
879 static void ath10k_pci_stop_ce(struct ath10k *ar)
880 {
881 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
882 struct ath10k_pci_compl *compl;
883 struct sk_buff *skb;
884 int ret;
885
886 ret = ath10k_ce_disable_interrupts(ar);
887 if (ret)
888 ath10k_warn("failed to disable CE interrupts: %d\n", ret);
889
890 ath10k_pci_kill_tasklet(ar);
891
892 /* Mark pending completions as aborted, so that upper layers free up
893 * their associated resources */
894 spin_lock_bh(&ar_pci->compl_lock);
895 list_for_each_entry(compl, &ar_pci->compl_process, list) {
896 skb = compl->skb;
897 ATH10K_SKB_CB(skb)->is_aborted = true;
898 }
899 spin_unlock_bh(&ar_pci->compl_lock);
900 }
901
902 static void ath10k_pci_cleanup_ce(struct ath10k *ar)
903 {
904 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
905 struct ath10k_pci_compl *compl, *tmp;
906 struct ath10k_pci_pipe *pipe_info;
907 struct sk_buff *netbuf;
908 int pipe_num;
909
910 /* Free pending completions. */
911 spin_lock_bh(&ar_pci->compl_lock);
912 if (!list_empty(&ar_pci->compl_process))
913 ath10k_warn("pending completions still present! possible memory leaks.\n");
914
915 list_for_each_entry_safe(compl, tmp, &ar_pci->compl_process, list) {
916 list_del(&compl->list);
917 netbuf = compl->skb;
918 dev_kfree_skb_any(netbuf);
919 kfree(compl);
920 }
921 spin_unlock_bh(&ar_pci->compl_lock);
922
923 /* Free unused completions for each pipe. */
924 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
925 pipe_info = &ar_pci->pipe_info[pipe_num];
926
927 spin_lock_bh(&pipe_info->pipe_lock);
928 list_for_each_entry_safe(compl, tmp,
929 &pipe_info->compl_free, list) {
930 list_del(&compl->list);
931 kfree(compl);
932 }
933 spin_unlock_bh(&pipe_info->pipe_lock);
934 }
935 }
936
937 static void ath10k_pci_process_ce(struct ath10k *ar)
938 {
939 struct ath10k_pci *ar_pci = ar->hif.priv;
940 struct ath10k_hif_cb *cb = &ar_pci->msg_callbacks_current;
941 struct ath10k_pci_compl *compl;
942 struct sk_buff *skb;
943 unsigned int nbytes;
944 int ret, send_done = 0;
945
946 /* Upper layers aren't ready to handle tx/rx completions in parallel so
947 * we must serialize all completion processing. */
948
949 spin_lock_bh(&ar_pci->compl_lock);
950 if (ar_pci->compl_processing) {
951 spin_unlock_bh(&ar_pci->compl_lock);
952 return;
953 }
954 ar_pci->compl_processing = true;
955 spin_unlock_bh(&ar_pci->compl_lock);
956
957 for (;;) {
958 spin_lock_bh(&ar_pci->compl_lock);
959 if (list_empty(&ar_pci->compl_process)) {
960 spin_unlock_bh(&ar_pci->compl_lock);
961 break;
962 }
963 compl = list_first_entry(&ar_pci->compl_process,
964 struct ath10k_pci_compl, list);
965 list_del(&compl->list);
966 spin_unlock_bh(&ar_pci->compl_lock);
967
968 switch (compl->state) {
969 case ATH10K_PCI_COMPL_SEND:
970 cb->tx_completion(ar,
971 compl->skb,
972 compl->transfer_id);
973 send_done = 1;
974 break;
975 case ATH10K_PCI_COMPL_RECV:
976 ret = ath10k_pci_post_rx_pipe(compl->pipe_info, 1);
977 if (ret) {
978 ath10k_warn("failed to post RX buffer for pipe %d: %d\n",
979 compl->pipe_info->pipe_num, ret);
980 break;
981 }
982
983 skb = compl->skb;
984 nbytes = compl->nbytes;
985
986 ath10k_dbg(ATH10K_DBG_PCI,
987 "ath10k_pci_ce_recv_data netbuf=%p nbytes=%d\n",
988 skb, nbytes);
989 ath10k_dbg_dump(ATH10K_DBG_PCI_DUMP, NULL,
990 "ath10k rx: ", skb->data, nbytes);
991
992 if (skb->len + skb_tailroom(skb) >= nbytes) {
993 skb_trim(skb, 0);
994 skb_put(skb, nbytes);
995 cb->rx_completion(ar, skb,
996 compl->pipe_info->pipe_num);
997 } else {
998 ath10k_warn("rxed more than expected (nbytes %d, max %d)",
999 nbytes,
1000 skb->len + skb_tailroom(skb));
1001 }
1002 break;
1003 case ATH10K_PCI_COMPL_FREE:
1004 ath10k_warn("free completion cannot be processed\n");
1005 break;
1006 default:
1007 ath10k_warn("invalid completion state (%d)\n",
1008 compl->state);
1009 break;
1010 }
1011
1012 compl->state = ATH10K_PCI_COMPL_FREE;
1013
1014 /*
1015 * Add completion back to the pipe's free list.
1016 */
1017 spin_lock_bh(&compl->pipe_info->pipe_lock);
1018 list_add_tail(&compl->list, &compl->pipe_info->compl_free);
1019 spin_unlock_bh(&compl->pipe_info->pipe_lock);
1020 }
1021
1022 spin_lock_bh(&ar_pci->compl_lock);
1023 ar_pci->compl_processing = false;
1024 spin_unlock_bh(&ar_pci->compl_lock);
1025 }
1026
1027 /* TODO - temporary mapping while we have too few CE's */
1028 static int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar,
1029 u16 service_id, u8 *ul_pipe,
1030 u8 *dl_pipe, int *ul_is_polled,
1031 int *dl_is_polled)
1032 {
1033 int ret = 0;
1034
1035 /* polling for received messages not supported */
1036 *dl_is_polled = 0;
1037
1038 switch (service_id) {
1039 case ATH10K_HTC_SVC_ID_HTT_DATA_MSG:
1040 /*
1041 * Host->target HTT gets its own pipe, so it can be polled
1042 * while other pipes are interrupt driven.
1043 */
1044 *ul_pipe = 4;
1045 /*
1046 * Use the same target->host pipe for HTC ctrl, HTC raw
1047 * streams, and HTT.
1048 */
1049 *dl_pipe = 1;
1050 break;
1051
1052 case ATH10K_HTC_SVC_ID_RSVD_CTRL:
1053 case ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS:
1054 /*
1055 * Note: HTC_RAW_STREAMS_SVC is currently unused, and
1056 * HTC_CTRL_RSVD_SVC could share the same pipe as the
1057 * WMI services. So, if another CE is needed, change
1058 * this to *ul_pipe = 3, which frees up CE 0.
1059 */
1060 /* *ul_pipe = 3; */
1061 *ul_pipe = 0;
1062 *dl_pipe = 1;
1063 break;
1064
1065 case ATH10K_HTC_SVC_ID_WMI_DATA_BK:
1066 case ATH10K_HTC_SVC_ID_WMI_DATA_BE:
1067 case ATH10K_HTC_SVC_ID_WMI_DATA_VI:
1068 case ATH10K_HTC_SVC_ID_WMI_DATA_VO:
1069
1070 case ATH10K_HTC_SVC_ID_WMI_CONTROL:
1071 *ul_pipe = 3;
1072 *dl_pipe = 2;
1073 break;
1074
1075 /* pipe 5 unused */
1076 /* pipe 6 reserved */
1077 /* pipe 7 reserved */
1078
1079 default:
1080 ret = -1;
1081 break;
1082 }
1083 *ul_is_polled =
1084 (host_ce_config_wlan[*ul_pipe].flags & CE_ATTR_DIS_INTR) != 0;
1085
1086 return ret;
1087 }
1088
1089 static void ath10k_pci_hif_get_default_pipe(struct ath10k *ar,
1090 u8 *ul_pipe, u8 *dl_pipe)
1091 {
1092 int ul_is_polled, dl_is_polled;
1093
1094 (void)ath10k_pci_hif_map_service_to_pipe(ar,
1095 ATH10K_HTC_SVC_ID_RSVD_CTRL,
1096 ul_pipe,
1097 dl_pipe,
1098 &ul_is_polled,
1099 &dl_is_polled);
1100 }
1101
1102 static int ath10k_pci_post_rx_pipe(struct ath10k_pci_pipe *pipe_info,
1103 int num)
1104 {
1105 struct ath10k *ar = pipe_info->hif_ce_state;
1106 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1107 struct ath10k_ce_pipe *ce_state = pipe_info->ce_hdl;
1108 struct sk_buff *skb;
1109 dma_addr_t ce_data;
1110 int i, ret = 0;
1111
1112 if (pipe_info->buf_sz == 0)
1113 return 0;
1114
1115 for (i = 0; i < num; i++) {
1116 skb = dev_alloc_skb(pipe_info->buf_sz);
1117 if (!skb) {
1118 ath10k_warn("failed to allocate skbuff for pipe %d\n",
1119 num);
1120 ret = -ENOMEM;
1121 goto err;
1122 }
1123
1124 WARN_ONCE((unsigned long)skb->data & 3, "unaligned skb");
1125
1126 ce_data = dma_map_single(ar->dev, skb->data,
1127 skb->len + skb_tailroom(skb),
1128 DMA_FROM_DEVICE);
1129
1130 if (unlikely(dma_mapping_error(ar->dev, ce_data))) {
1131 ath10k_warn("failed to DMA map sk_buff\n");
1132 dev_kfree_skb_any(skb);
1133 ret = -EIO;
1134 goto err;
1135 }
1136
1137 ATH10K_SKB_CB(skb)->paddr = ce_data;
1138
1139 pci_dma_sync_single_for_device(ar_pci->pdev, ce_data,
1140 pipe_info->buf_sz,
1141 PCI_DMA_FROMDEVICE);
1142
1143 ret = ath10k_ce_recv_buf_enqueue(ce_state, (void *)skb,
1144 ce_data);
1145 if (ret) {
1146 ath10k_warn("failed to enqueue to pipe %d: %d\n",
1147 num, ret);
1148 goto err;
1149 }
1150 }
1151
1152 return ret;
1153
1154 err:
1155 ath10k_pci_rx_pipe_cleanup(pipe_info);
1156 return ret;
1157 }
1158
1159 static int ath10k_pci_post_rx(struct ath10k *ar)
1160 {
1161 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1162 struct ath10k_pci_pipe *pipe_info;
1163 const struct ce_attr *attr;
1164 int pipe_num, ret = 0;
1165
1166 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
1167 pipe_info = &ar_pci->pipe_info[pipe_num];
1168 attr = &host_ce_config_wlan[pipe_num];
1169
1170 if (attr->dest_nentries == 0)
1171 continue;
1172
1173 ret = ath10k_pci_post_rx_pipe(pipe_info,
1174 attr->dest_nentries - 1);
1175 if (ret) {
1176 ath10k_warn("failed to post RX buffer for pipe %d: %d\n",
1177 pipe_num, ret);
1178
1179 for (; pipe_num >= 0; pipe_num--) {
1180 pipe_info = &ar_pci->pipe_info[pipe_num];
1181 ath10k_pci_rx_pipe_cleanup(pipe_info);
1182 }
1183 return ret;
1184 }
1185 }
1186
1187 return 0;
1188 }
1189
1190 static int ath10k_pci_hif_start(struct ath10k *ar)
1191 {
1192 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1193 int ret;
1194
1195 ret = ath10k_pci_start_ce(ar);
1196 if (ret) {
1197 ath10k_warn("failed to start CE: %d\n", ret);
1198 return ret;
1199 }
1200
1201 /* Post buffers once to start things off. */
1202 ret = ath10k_pci_post_rx(ar);
1203 if (ret) {
1204 ath10k_warn("failed to post RX buffers for all pipes: %d\n",
1205 ret);
1206 return ret;
1207 }
1208
1209 ar_pci->started = 1;
1210 return 0;
1211 }
1212
1213 static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe *pipe_info)
1214 {
1215 struct ath10k *ar;
1216 struct ath10k_pci *ar_pci;
1217 struct ath10k_ce_pipe *ce_hdl;
1218 u32 buf_sz;
1219 struct sk_buff *netbuf;
1220 u32 ce_data;
1221
1222 buf_sz = pipe_info->buf_sz;
1223
1224 /* Unused Copy Engine */
1225 if (buf_sz == 0)
1226 return;
1227
1228 ar = pipe_info->hif_ce_state;
1229 ar_pci = ath10k_pci_priv(ar);
1230
1231 if (!ar_pci->started)
1232 return;
1233
1234 ce_hdl = pipe_info->ce_hdl;
1235
1236 while (ath10k_ce_revoke_recv_next(ce_hdl, (void **)&netbuf,
1237 &ce_data) == 0) {
1238 dma_unmap_single(ar->dev, ATH10K_SKB_CB(netbuf)->paddr,
1239 netbuf->len + skb_tailroom(netbuf),
1240 DMA_FROM_DEVICE);
1241 dev_kfree_skb_any(netbuf);
1242 }
1243 }
1244
1245 static void ath10k_pci_tx_pipe_cleanup(struct ath10k_pci_pipe *pipe_info)
1246 {
1247 struct ath10k *ar;
1248 struct ath10k_pci *ar_pci;
1249 struct ath10k_ce_pipe *ce_hdl;
1250 struct sk_buff *netbuf;
1251 u32 ce_data;
1252 unsigned int nbytes;
1253 unsigned int id;
1254 u32 buf_sz;
1255
1256 buf_sz = pipe_info->buf_sz;
1257
1258 /* Unused Copy Engine */
1259 if (buf_sz == 0)
1260 return;
1261
1262 ar = pipe_info->hif_ce_state;
1263 ar_pci = ath10k_pci_priv(ar);
1264
1265 if (!ar_pci->started)
1266 return;
1267
1268 ce_hdl = pipe_info->ce_hdl;
1269
1270 while (ath10k_ce_cancel_send_next(ce_hdl, (void **)&netbuf,
1271 &ce_data, &nbytes, &id) == 0) {
1272 /*
1273 * Indicate the completion to higer layer to free
1274 * the buffer
1275 */
1276
1277 if (!netbuf) {
1278 ath10k_warn("invalid sk_buff on CE %d - NULL pointer. firmware crashed?\n",
1279 ce_hdl->id);
1280 continue;
1281 }
1282
1283 ATH10K_SKB_CB(netbuf)->is_aborted = true;
1284 ar_pci->msg_callbacks_current.tx_completion(ar,
1285 netbuf,
1286 id);
1287 }
1288 }
1289
1290 /*
1291 * Cleanup residual buffers for device shutdown:
1292 * buffers that were enqueued for receive
1293 * buffers that were to be sent
1294 * Note: Buffers that had completed but which were
1295 * not yet processed are on a completion queue. They
1296 * are handled when the completion thread shuts down.
1297 */
1298 static void ath10k_pci_buffer_cleanup(struct ath10k *ar)
1299 {
1300 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1301 int pipe_num;
1302
1303 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
1304 struct ath10k_pci_pipe *pipe_info;
1305
1306 pipe_info = &ar_pci->pipe_info[pipe_num];
1307 ath10k_pci_rx_pipe_cleanup(pipe_info);
1308 ath10k_pci_tx_pipe_cleanup(pipe_info);
1309 }
1310 }
1311
1312 static void ath10k_pci_ce_deinit(struct ath10k *ar)
1313 {
1314 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1315 struct ath10k_pci_pipe *pipe_info;
1316 int pipe_num;
1317
1318 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
1319 pipe_info = &ar_pci->pipe_info[pipe_num];
1320 if (pipe_info->ce_hdl) {
1321 ath10k_ce_deinit(pipe_info->ce_hdl);
1322 pipe_info->ce_hdl = NULL;
1323 pipe_info->buf_sz = 0;
1324 }
1325 }
1326 }
1327
1328 static void ath10k_pci_disable_irqs(struct ath10k *ar)
1329 {
1330 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1331 int i;
1332
1333 for (i = 0; i < max(1, ar_pci->num_msi_intrs); i++)
1334 disable_irq(ar_pci->pdev->irq + i);
1335 }
1336
1337 static void ath10k_pci_hif_stop(struct ath10k *ar)
1338 {
1339 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1340
1341 ath10k_dbg(ATH10K_DBG_PCI, "%s\n", __func__);
1342
1343 /* Irqs are never explicitly re-enabled. They are implicitly re-enabled
1344 * by ath10k_pci_start_intr(). */
1345 ath10k_pci_disable_irqs(ar);
1346
1347 ath10k_pci_stop_ce(ar);
1348
1349 /* At this point, asynchronous threads are stopped, the target should
1350 * not DMA nor interrupt. We process the leftovers and then free
1351 * everything else up. */
1352
1353 ath10k_pci_process_ce(ar);
1354 ath10k_pci_cleanup_ce(ar);
1355 ath10k_pci_buffer_cleanup(ar);
1356
1357 /* Make the sure the device won't access any structures on the host by
1358 * resetting it. The device was fed with PCI CE ringbuffer
1359 * configuration during init. If ringbuffers are freed and the device
1360 * were to access them this could lead to memory corruption on the
1361 * host. */
1362 ath10k_pci_device_reset(ar);
1363
1364 ar_pci->started = 0;
1365 }
1366
1367 static int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar,
1368 void *req, u32 req_len,
1369 void *resp, u32 *resp_len)
1370 {
1371 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1372 struct ath10k_pci_pipe *pci_tx = &ar_pci->pipe_info[BMI_CE_NUM_TO_TARG];
1373 struct ath10k_pci_pipe *pci_rx = &ar_pci->pipe_info[BMI_CE_NUM_TO_HOST];
1374 struct ath10k_ce_pipe *ce_tx = pci_tx->ce_hdl;
1375 struct ath10k_ce_pipe *ce_rx = pci_rx->ce_hdl;
1376 dma_addr_t req_paddr = 0;
1377 dma_addr_t resp_paddr = 0;
1378 struct bmi_xfer xfer = {};
1379 void *treq, *tresp = NULL;
1380 int ret = 0;
1381
1382 if (resp && !resp_len)
1383 return -EINVAL;
1384
1385 if (resp && resp_len && *resp_len == 0)
1386 return -EINVAL;
1387
1388 treq = kmemdup(req, req_len, GFP_KERNEL);
1389 if (!treq)
1390 return -ENOMEM;
1391
1392 req_paddr = dma_map_single(ar->dev, treq, req_len, DMA_TO_DEVICE);
1393 ret = dma_mapping_error(ar->dev, req_paddr);
1394 if (ret)
1395 goto err_dma;
1396
1397 if (resp && resp_len) {
1398 tresp = kzalloc(*resp_len, GFP_KERNEL);
1399 if (!tresp) {
1400 ret = -ENOMEM;
1401 goto err_req;
1402 }
1403
1404 resp_paddr = dma_map_single(ar->dev, tresp, *resp_len,
1405 DMA_FROM_DEVICE);
1406 ret = dma_mapping_error(ar->dev, resp_paddr);
1407 if (ret)
1408 goto err_req;
1409
1410 xfer.wait_for_resp = true;
1411 xfer.resp_len = 0;
1412
1413 ath10k_ce_recv_buf_enqueue(ce_rx, &xfer, resp_paddr);
1414 }
1415
1416 init_completion(&xfer.done);
1417
1418 ret = ath10k_ce_send(ce_tx, &xfer, req_paddr, req_len, -1, 0);
1419 if (ret)
1420 goto err_resp;
1421
1422 ret = wait_for_completion_timeout(&xfer.done,
1423 BMI_COMMUNICATION_TIMEOUT_HZ);
1424 if (ret <= 0) {
1425 u32 unused_buffer;
1426 unsigned int unused_nbytes;
1427 unsigned int unused_id;
1428
1429 ret = -ETIMEDOUT;
1430 ath10k_ce_cancel_send_next(ce_tx, NULL, &unused_buffer,
1431 &unused_nbytes, &unused_id);
1432 } else {
1433 /* non-zero means we did not time out */
1434 ret = 0;
1435 }
1436
1437 err_resp:
1438 if (resp) {
1439 u32 unused_buffer;
1440
1441 ath10k_ce_revoke_recv_next(ce_rx, NULL, &unused_buffer);
1442 dma_unmap_single(ar->dev, resp_paddr,
1443 *resp_len, DMA_FROM_DEVICE);
1444 }
1445 err_req:
1446 dma_unmap_single(ar->dev, req_paddr, req_len, DMA_TO_DEVICE);
1447
1448 if (ret == 0 && resp_len) {
1449 *resp_len = min(*resp_len, xfer.resp_len);
1450 memcpy(resp, tresp, xfer.resp_len);
1451 }
1452 err_dma:
1453 kfree(treq);
1454 kfree(tresp);
1455
1456 return ret;
1457 }
1458
1459 static void ath10k_pci_bmi_send_done(struct ath10k_ce_pipe *ce_state)
1460 {
1461 struct bmi_xfer *xfer;
1462 u32 ce_data;
1463 unsigned int nbytes;
1464 unsigned int transfer_id;
1465
1466 if (ath10k_ce_completed_send_next(ce_state, (void **)&xfer, &ce_data,
1467 &nbytes, &transfer_id))
1468 return;
1469
1470 if (xfer->wait_for_resp)
1471 return;
1472
1473 complete(&xfer->done);
1474 }
1475
1476 static void ath10k_pci_bmi_recv_data(struct ath10k_ce_pipe *ce_state)
1477 {
1478 struct bmi_xfer *xfer;
1479 u32 ce_data;
1480 unsigned int nbytes;
1481 unsigned int transfer_id;
1482 unsigned int flags;
1483
1484 if (ath10k_ce_completed_recv_next(ce_state, (void **)&xfer, &ce_data,
1485 &nbytes, &transfer_id, &flags))
1486 return;
1487
1488 if (!xfer->wait_for_resp) {
1489 ath10k_warn("unexpected: BMI data received; ignoring\n");
1490 return;
1491 }
1492
1493 xfer->resp_len = nbytes;
1494 complete(&xfer->done);
1495 }
1496
1497 /*
1498 * Map from service/endpoint to Copy Engine.
1499 * This table is derived from the CE_PCI TABLE, above.
1500 * It is passed to the Target at startup for use by firmware.
1501 */
1502 static const struct service_to_pipe target_service_to_ce_map_wlan[] = {
1503 {
1504 ATH10K_HTC_SVC_ID_WMI_DATA_VO,
1505 PIPEDIR_OUT, /* out = UL = host -> target */
1506 3,
1507 },
1508 {
1509 ATH10K_HTC_SVC_ID_WMI_DATA_VO,
1510 PIPEDIR_IN, /* in = DL = target -> host */
1511 2,
1512 },
1513 {
1514 ATH10K_HTC_SVC_ID_WMI_DATA_BK,
1515 PIPEDIR_OUT, /* out = UL = host -> target */
1516 3,
1517 },
1518 {
1519 ATH10K_HTC_SVC_ID_WMI_DATA_BK,
1520 PIPEDIR_IN, /* in = DL = target -> host */
1521 2,
1522 },
1523 {
1524 ATH10K_HTC_SVC_ID_WMI_DATA_BE,
1525 PIPEDIR_OUT, /* out = UL = host -> target */
1526 3,
1527 },
1528 {
1529 ATH10K_HTC_SVC_ID_WMI_DATA_BE,
1530 PIPEDIR_IN, /* in = DL = target -> host */
1531 2,
1532 },
1533 {
1534 ATH10K_HTC_SVC_ID_WMI_DATA_VI,
1535 PIPEDIR_OUT, /* out = UL = host -> target */
1536 3,
1537 },
1538 {
1539 ATH10K_HTC_SVC_ID_WMI_DATA_VI,
1540 PIPEDIR_IN, /* in = DL = target -> host */
1541 2,
1542 },
1543 {
1544 ATH10K_HTC_SVC_ID_WMI_CONTROL,
1545 PIPEDIR_OUT, /* out = UL = host -> target */
1546 3,
1547 },
1548 {
1549 ATH10K_HTC_SVC_ID_WMI_CONTROL,
1550 PIPEDIR_IN, /* in = DL = target -> host */
1551 2,
1552 },
1553 {
1554 ATH10K_HTC_SVC_ID_RSVD_CTRL,
1555 PIPEDIR_OUT, /* out = UL = host -> target */
1556 0, /* could be moved to 3 (share with WMI) */
1557 },
1558 {
1559 ATH10K_HTC_SVC_ID_RSVD_CTRL,
1560 PIPEDIR_IN, /* in = DL = target -> host */
1561 1,
1562 },
1563 {
1564 ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS, /* not currently used */
1565 PIPEDIR_OUT, /* out = UL = host -> target */
1566 0,
1567 },
1568 {
1569 ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS, /* not currently used */
1570 PIPEDIR_IN, /* in = DL = target -> host */
1571 1,
1572 },
1573 {
1574 ATH10K_HTC_SVC_ID_HTT_DATA_MSG,
1575 PIPEDIR_OUT, /* out = UL = host -> target */
1576 4,
1577 },
1578 {
1579 ATH10K_HTC_SVC_ID_HTT_DATA_MSG,
1580 PIPEDIR_IN, /* in = DL = target -> host */
1581 1,
1582 },
1583
1584 /* (Additions here) */
1585
1586 { /* Must be last */
1587 0,
1588 0,
1589 0,
1590 },
1591 };
1592
1593 /*
1594 * Send an interrupt to the device to wake up the Target CPU
1595 * so it has an opportunity to notice any changed state.
1596 */
1597 static int ath10k_pci_wake_target_cpu(struct ath10k *ar)
1598 {
1599 int ret;
1600 u32 core_ctrl;
1601
1602 ret = ath10k_pci_diag_read_access(ar, SOC_CORE_BASE_ADDRESS |
1603 CORE_CTRL_ADDRESS,
1604 &core_ctrl);
1605 if (ret) {
1606 ath10k_warn("failed to read core_ctrl: %d\n", ret);
1607 return ret;
1608 }
1609
1610 /* A_INUM_FIRMWARE interrupt to Target CPU */
1611 core_ctrl |= CORE_CTRL_CPU_INTR_MASK;
1612
1613 ret = ath10k_pci_diag_write_access(ar, SOC_CORE_BASE_ADDRESS |
1614 CORE_CTRL_ADDRESS,
1615 core_ctrl);
1616 if (ret) {
1617 ath10k_warn("failed to set target CPU interrupt mask: %d\n",
1618 ret);
1619 return ret;
1620 }
1621
1622 return 0;
1623 }
1624
1625 static int ath10k_pci_init_config(struct ath10k *ar)
1626 {
1627 u32 interconnect_targ_addr;
1628 u32 pcie_state_targ_addr = 0;
1629 u32 pipe_cfg_targ_addr = 0;
1630 u32 svc_to_pipe_map = 0;
1631 u32 pcie_config_flags = 0;
1632 u32 ealloc_value;
1633 u32 ealloc_targ_addr;
1634 u32 flag2_value;
1635 u32 flag2_targ_addr;
1636 int ret = 0;
1637
1638 /* Download to Target the CE Config and the service-to-CE map */
1639 interconnect_targ_addr =
1640 host_interest_item_address(HI_ITEM(hi_interconnect_state));
1641
1642 /* Supply Target-side CE configuration */
1643 ret = ath10k_pci_diag_read_access(ar, interconnect_targ_addr,
1644 &pcie_state_targ_addr);
1645 if (ret != 0) {
1646 ath10k_err("Failed to get pcie state addr: %d\n", ret);
1647 return ret;
1648 }
1649
1650 if (pcie_state_targ_addr == 0) {
1651 ret = -EIO;
1652 ath10k_err("Invalid pcie state addr\n");
1653 return ret;
1654 }
1655
1656 ret = ath10k_pci_diag_read_access(ar, pcie_state_targ_addr +
1657 offsetof(struct pcie_state,
1658 pipe_cfg_addr),
1659 &pipe_cfg_targ_addr);
1660 if (ret != 0) {
1661 ath10k_err("Failed to get pipe cfg addr: %d\n", ret);
1662 return ret;
1663 }
1664
1665 if (pipe_cfg_targ_addr == 0) {
1666 ret = -EIO;
1667 ath10k_err("Invalid pipe cfg addr\n");
1668 return ret;
1669 }
1670
1671 ret = ath10k_pci_diag_write_mem(ar, pipe_cfg_targ_addr,
1672 target_ce_config_wlan,
1673 sizeof(target_ce_config_wlan));
1674
1675 if (ret != 0) {
1676 ath10k_err("Failed to write pipe cfg: %d\n", ret);
1677 return ret;
1678 }
1679
1680 ret = ath10k_pci_diag_read_access(ar, pcie_state_targ_addr +
1681 offsetof(struct pcie_state,
1682 svc_to_pipe_map),
1683 &svc_to_pipe_map);
1684 if (ret != 0) {
1685 ath10k_err("Failed to get svc/pipe map: %d\n", ret);
1686 return ret;
1687 }
1688
1689 if (svc_to_pipe_map == 0) {
1690 ret = -EIO;
1691 ath10k_err("Invalid svc_to_pipe map\n");
1692 return ret;
1693 }
1694
1695 ret = ath10k_pci_diag_write_mem(ar, svc_to_pipe_map,
1696 target_service_to_ce_map_wlan,
1697 sizeof(target_service_to_ce_map_wlan));
1698 if (ret != 0) {
1699 ath10k_err("Failed to write svc/pipe map: %d\n", ret);
1700 return ret;
1701 }
1702
1703 ret = ath10k_pci_diag_read_access(ar, pcie_state_targ_addr +
1704 offsetof(struct pcie_state,
1705 config_flags),
1706 &pcie_config_flags);
1707 if (ret != 0) {
1708 ath10k_err("Failed to get pcie config_flags: %d\n", ret);
1709 return ret;
1710 }
1711
1712 pcie_config_flags &= ~PCIE_CONFIG_FLAG_ENABLE_L1;
1713
1714 ret = ath10k_pci_diag_write_mem(ar, pcie_state_targ_addr +
1715 offsetof(struct pcie_state, config_flags),
1716 &pcie_config_flags,
1717 sizeof(pcie_config_flags));
1718 if (ret != 0) {
1719 ath10k_err("Failed to write pcie config_flags: %d\n", ret);
1720 return ret;
1721 }
1722
1723 /* configure early allocation */
1724 ealloc_targ_addr = host_interest_item_address(HI_ITEM(hi_early_alloc));
1725
1726 ret = ath10k_pci_diag_read_access(ar, ealloc_targ_addr, &ealloc_value);
1727 if (ret != 0) {
1728 ath10k_err("Faile to get early alloc val: %d\n", ret);
1729 return ret;
1730 }
1731
1732 /* first bank is switched to IRAM */
1733 ealloc_value |= ((HI_EARLY_ALLOC_MAGIC << HI_EARLY_ALLOC_MAGIC_SHIFT) &
1734 HI_EARLY_ALLOC_MAGIC_MASK);
1735 ealloc_value |= ((1 << HI_EARLY_ALLOC_IRAM_BANKS_SHIFT) &
1736 HI_EARLY_ALLOC_IRAM_BANKS_MASK);
1737
1738 ret = ath10k_pci_diag_write_access(ar, ealloc_targ_addr, ealloc_value);
1739 if (ret != 0) {
1740 ath10k_err("Failed to set early alloc val: %d\n", ret);
1741 return ret;
1742 }
1743
1744 /* Tell Target to proceed with initialization */
1745 flag2_targ_addr = host_interest_item_address(HI_ITEM(hi_option_flag2));
1746
1747 ret = ath10k_pci_diag_read_access(ar, flag2_targ_addr, &flag2_value);
1748 if (ret != 0) {
1749 ath10k_err("Failed to get option val: %d\n", ret);
1750 return ret;
1751 }
1752
1753 flag2_value |= HI_OPTION_EARLY_CFG_DONE;
1754
1755 ret = ath10k_pci_diag_write_access(ar, flag2_targ_addr, flag2_value);
1756 if (ret != 0) {
1757 ath10k_err("Failed to set option val: %d\n", ret);
1758 return ret;
1759 }
1760
1761 return 0;
1762 }
1763
1764
1765
1766 static int ath10k_pci_ce_init(struct ath10k *ar)
1767 {
1768 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1769 struct ath10k_pci_pipe *pipe_info;
1770 const struct ce_attr *attr;
1771 int pipe_num;
1772
1773 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
1774 pipe_info = &ar_pci->pipe_info[pipe_num];
1775 pipe_info->pipe_num = pipe_num;
1776 pipe_info->hif_ce_state = ar;
1777 attr = &host_ce_config_wlan[pipe_num];
1778
1779 pipe_info->ce_hdl = ath10k_ce_init(ar, pipe_num, attr);
1780 if (pipe_info->ce_hdl == NULL) {
1781 ath10k_err("failed to initialize CE for pipe: %d\n",
1782 pipe_num);
1783
1784 /* It is safe to call it here. It checks if ce_hdl is
1785 * valid for each pipe */
1786 ath10k_pci_ce_deinit(ar);
1787 return -1;
1788 }
1789
1790 if (pipe_num == CE_COUNT - 1) {
1791 /*
1792 * Reserve the ultimate CE for
1793 * diagnostic Window support
1794 */
1795 ar_pci->ce_diag = pipe_info->ce_hdl;
1796 continue;
1797 }
1798
1799 pipe_info->buf_sz = (size_t) (attr->src_sz_max);
1800 }
1801
1802 return 0;
1803 }
1804
1805 static void ath10k_pci_fw_interrupt_handler(struct ath10k *ar)
1806 {
1807 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1808 u32 fw_indicator_address, fw_indicator;
1809
1810 ath10k_pci_wake(ar);
1811
1812 fw_indicator_address = ar_pci->fw_indicator_address;
1813 fw_indicator = ath10k_pci_read32(ar, fw_indicator_address);
1814
1815 if (fw_indicator & FW_IND_EVENT_PENDING) {
1816 /* ACK: clear Target-side pending event */
1817 ath10k_pci_write32(ar, fw_indicator_address,
1818 fw_indicator & ~FW_IND_EVENT_PENDING);
1819
1820 if (ar_pci->started) {
1821 ath10k_pci_hif_dump_area(ar);
1822 } else {
1823 /*
1824 * Probable Target failure before we're prepared
1825 * to handle it. Generally unexpected.
1826 */
1827 ath10k_warn("early firmware event indicated\n");
1828 }
1829 }
1830
1831 ath10k_pci_sleep(ar);
1832 }
1833
1834 static void ath10k_pci_start_bmi(struct ath10k *ar)
1835 {
1836 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1837 struct ath10k_pci_pipe *pipe;
1838
1839 /*
1840 * Initially, establish CE completion handlers for use with BMI.
1841 * These are overwritten with generic handlers after we exit BMI phase.
1842 */
1843 pipe = &ar_pci->pipe_info[BMI_CE_NUM_TO_TARG];
1844 ath10k_ce_send_cb_register(pipe->ce_hdl, ath10k_pci_bmi_send_done, 0);
1845
1846 pipe = &ar_pci->pipe_info[BMI_CE_NUM_TO_HOST];
1847 ath10k_ce_recv_cb_register(pipe->ce_hdl, ath10k_pci_bmi_recv_data);
1848
1849 ath10k_dbg(ATH10K_DBG_BOOT, "boot start bmi\n");
1850 }
1851
1852 static int ath10k_pci_hif_power_up(struct ath10k *ar)
1853 {
1854 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1855 const char *irq_mode;
1856 int ret;
1857
1858 /*
1859 * Bring the target up cleanly.
1860 *
1861 * The target may be in an undefined state with an AUX-powered Target
1862 * and a Host in WoW mode. If the Host crashes, loses power, or is
1863 * restarted (without unloading the driver) then the Target is left
1864 * (aux) powered and running. On a subsequent driver load, the Target
1865 * is in an unexpected state. We try to catch that here in order to
1866 * reset the Target and retry the probe.
1867 */
1868 ret = ath10k_pci_device_reset(ar);
1869 if (ret) {
1870 ath10k_err("failed to reset target: %d\n", ret);
1871 goto err;
1872 }
1873
1874 if (!test_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE, ar_pci->features))
1875 /* Force AWAKE forever */
1876 ath10k_do_pci_wake(ar);
1877
1878 ret = ath10k_pci_ce_init(ar);
1879 if (ret) {
1880 ath10k_err("failed to initialize CE: %d\n", ret);
1881 goto err_ps;
1882 }
1883
1884 ret = ath10k_ce_disable_interrupts(ar);
1885 if (ret) {
1886 ath10k_err("failed to disable CE interrupts: %d\n", ret);
1887 goto err_ce;
1888 }
1889
1890 ret = ath10k_pci_start_intr(ar);
1891 if (ret) {
1892 ath10k_err("failed to start interrupt handling: %d\n", ret);
1893 goto err_ce;
1894 }
1895
1896 ret = ath10k_pci_wait_for_target_init(ar);
1897 if (ret) {
1898 ath10k_err("failed to wait for target to init: %d\n", ret);
1899 goto err_irq;
1900 }
1901
1902 ret = ath10k_ce_enable_err_irq(ar);
1903 if (ret) {
1904 ath10k_err("failed to enable CE error irq: %d\n", ret);
1905 goto err_irq;
1906 }
1907
1908 ret = ath10k_pci_init_config(ar);
1909 if (ret) {
1910 ath10k_err("failed to setup init config: %d\n", ret);
1911 goto err_irq;
1912 }
1913
1914 ret = ath10k_pci_wake_target_cpu(ar);
1915 if (ret) {
1916 ath10k_err("could not wake up target CPU: %d\n", ret);
1917 goto err_irq;
1918 }
1919
1920 ath10k_pci_start_bmi(ar);
1921
1922 if (ar_pci->num_msi_intrs > 1)
1923 irq_mode = "MSI-X";
1924 else if (ar_pci->num_msi_intrs == 1)
1925 irq_mode = "MSI";
1926 else
1927 irq_mode = "legacy";
1928
1929 if (!test_bit(ATH10K_FLAG_FIRST_BOOT_DONE, &ar->dev_flags))
1930 ath10k_info("pci irq %s\n", irq_mode);
1931
1932 return 0;
1933
1934 err_irq:
1935 ath10k_ce_disable_interrupts(ar);
1936 ath10k_pci_stop_intr(ar);
1937 ath10k_pci_kill_tasklet(ar);
1938 ath10k_pci_device_reset(ar);
1939 err_ce:
1940 ath10k_pci_ce_deinit(ar);
1941 err_ps:
1942 if (!test_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE, ar_pci->features))
1943 ath10k_do_pci_sleep(ar);
1944 err:
1945 return ret;
1946 }
1947
1948 static void ath10k_pci_hif_power_down(struct ath10k *ar)
1949 {
1950 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1951
1952 ath10k_pci_stop_intr(ar);
1953 ath10k_pci_device_reset(ar);
1954
1955 ath10k_pci_ce_deinit(ar);
1956 if (!test_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE, ar_pci->features))
1957 ath10k_do_pci_sleep(ar);
1958 }
1959
1960 #ifdef CONFIG_PM
1961
1962 #define ATH10K_PCI_PM_CONTROL 0x44
1963
1964 static int ath10k_pci_hif_suspend(struct ath10k *ar)
1965 {
1966 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1967 struct pci_dev *pdev = ar_pci->pdev;
1968 u32 val;
1969
1970 pci_read_config_dword(pdev, ATH10K_PCI_PM_CONTROL, &val);
1971
1972 if ((val & 0x000000ff) != 0x3) {
1973 pci_save_state(pdev);
1974 pci_disable_device(pdev);
1975 pci_write_config_dword(pdev, ATH10K_PCI_PM_CONTROL,
1976 (val & 0xffffff00) | 0x03);
1977 }
1978
1979 return 0;
1980 }
1981
1982 static int ath10k_pci_hif_resume(struct ath10k *ar)
1983 {
1984 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1985 struct pci_dev *pdev = ar_pci->pdev;
1986 u32 val;
1987
1988 pci_read_config_dword(pdev, ATH10K_PCI_PM_CONTROL, &val);
1989
1990 if ((val & 0x000000ff) != 0) {
1991 pci_restore_state(pdev);
1992 pci_write_config_dword(pdev, ATH10K_PCI_PM_CONTROL,
1993 val & 0xffffff00);
1994 /*
1995 * Suspend/Resume resets the PCI configuration space,
1996 * so we have to re-disable the RETRY_TIMEOUT register (0x41)
1997 * to keep PCI Tx retries from interfering with C3 CPU state
1998 */
1999 pci_read_config_dword(pdev, 0x40, &val);
2000
2001 if ((val & 0x0000ff00) != 0)
2002 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2003 }
2004
2005 return 0;
2006 }
2007 #endif
2008
2009 static const struct ath10k_hif_ops ath10k_pci_hif_ops = {
2010 .send_head = ath10k_pci_hif_send_head,
2011 .exchange_bmi_msg = ath10k_pci_hif_exchange_bmi_msg,
2012 .start = ath10k_pci_hif_start,
2013 .stop = ath10k_pci_hif_stop,
2014 .map_service_to_pipe = ath10k_pci_hif_map_service_to_pipe,
2015 .get_default_pipe = ath10k_pci_hif_get_default_pipe,
2016 .send_complete_check = ath10k_pci_hif_send_complete_check,
2017 .set_callbacks = ath10k_pci_hif_set_callbacks,
2018 .get_free_queue_number = ath10k_pci_hif_get_free_queue_number,
2019 .power_up = ath10k_pci_hif_power_up,
2020 .power_down = ath10k_pci_hif_power_down,
2021 #ifdef CONFIG_PM
2022 .suspend = ath10k_pci_hif_suspend,
2023 .resume = ath10k_pci_hif_resume,
2024 #endif
2025 };
2026
2027 static void ath10k_pci_ce_tasklet(unsigned long ptr)
2028 {
2029 struct ath10k_pci_pipe *pipe = (struct ath10k_pci_pipe *)ptr;
2030 struct ath10k_pci *ar_pci = pipe->ar_pci;
2031
2032 ath10k_ce_per_engine_service(ar_pci->ar, pipe->pipe_num);
2033 }
2034
2035 static void ath10k_msi_err_tasklet(unsigned long data)
2036 {
2037 struct ath10k *ar = (struct ath10k *)data;
2038
2039 ath10k_pci_fw_interrupt_handler(ar);
2040 }
2041
2042 /*
2043 * Handler for a per-engine interrupt on a PARTICULAR CE.
2044 * This is used in cases where each CE has a private MSI interrupt.
2045 */
2046 static irqreturn_t ath10k_pci_per_engine_handler(int irq, void *arg)
2047 {
2048 struct ath10k *ar = arg;
2049 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2050 int ce_id = irq - ar_pci->pdev->irq - MSI_ASSIGN_CE_INITIAL;
2051
2052 if (ce_id < 0 || ce_id >= ARRAY_SIZE(ar_pci->pipe_info)) {
2053 ath10k_warn("unexpected/invalid irq %d ce_id %d\n", irq, ce_id);
2054 return IRQ_HANDLED;
2055 }
2056
2057 /*
2058 * NOTE: We are able to derive ce_id from irq because we
2059 * use a one-to-one mapping for CE's 0..5.
2060 * CE's 6 & 7 do not use interrupts at all.
2061 *
2062 * This mapping must be kept in sync with the mapping
2063 * used by firmware.
2064 */
2065 tasklet_schedule(&ar_pci->pipe_info[ce_id].intr);
2066 return IRQ_HANDLED;
2067 }
2068
2069 static irqreturn_t ath10k_pci_msi_fw_handler(int irq, void *arg)
2070 {
2071 struct ath10k *ar = arg;
2072 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2073
2074 tasklet_schedule(&ar_pci->msi_fw_err);
2075 return IRQ_HANDLED;
2076 }
2077
2078 /*
2079 * Top-level interrupt handler for all PCI interrupts from a Target.
2080 * When a block of MSI interrupts is allocated, this top-level handler
2081 * is not used; instead, we directly call the correct sub-handler.
2082 */
2083 static irqreturn_t ath10k_pci_interrupt_handler(int irq, void *arg)
2084 {
2085 struct ath10k *ar = arg;
2086 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2087
2088 if (ar_pci->num_msi_intrs == 0) {
2089 /*
2090 * IMPORTANT: INTR_CLR regiser has to be set after
2091 * INTR_ENABLE is set to 0, otherwise interrupt can not be
2092 * really cleared.
2093 */
2094 iowrite32(0, ar_pci->mem +
2095 (SOC_CORE_BASE_ADDRESS |
2096 PCIE_INTR_ENABLE_ADDRESS));
2097 iowrite32(PCIE_INTR_FIRMWARE_MASK |
2098 PCIE_INTR_CE_MASK_ALL,
2099 ar_pci->mem + (SOC_CORE_BASE_ADDRESS |
2100 PCIE_INTR_CLR_ADDRESS));
2101 /*
2102 * IMPORTANT: this extra read transaction is required to
2103 * flush the posted write buffer.
2104 */
2105 (void) ioread32(ar_pci->mem +
2106 (SOC_CORE_BASE_ADDRESS |
2107 PCIE_INTR_ENABLE_ADDRESS));
2108 }
2109
2110 tasklet_schedule(&ar_pci->intr_tq);
2111
2112 return IRQ_HANDLED;
2113 }
2114
2115 static void ath10k_pci_tasklet(unsigned long data)
2116 {
2117 struct ath10k *ar = (struct ath10k *)data;
2118 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2119
2120 ath10k_pci_fw_interrupt_handler(ar); /* FIXME: Handle FW error */
2121 ath10k_ce_per_engine_service_any(ar);
2122
2123 if (ar_pci->num_msi_intrs == 0) {
2124 /* Enable Legacy PCI line interrupts */
2125 iowrite32(PCIE_INTR_FIRMWARE_MASK |
2126 PCIE_INTR_CE_MASK_ALL,
2127 ar_pci->mem + (SOC_CORE_BASE_ADDRESS |
2128 PCIE_INTR_ENABLE_ADDRESS));
2129 /*
2130 * IMPORTANT: this extra read transaction is required to
2131 * flush the posted write buffer
2132 */
2133 (void) ioread32(ar_pci->mem +
2134 (SOC_CORE_BASE_ADDRESS |
2135 PCIE_INTR_ENABLE_ADDRESS));
2136 }
2137 }
2138
2139 static int ath10k_pci_start_intr_msix(struct ath10k *ar, int num)
2140 {
2141 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2142 int ret;
2143 int i;
2144
2145 ret = pci_enable_msi_block(ar_pci->pdev, num);
2146 if (ret)
2147 return ret;
2148
2149 ret = request_irq(ar_pci->pdev->irq + MSI_ASSIGN_FW,
2150 ath10k_pci_msi_fw_handler,
2151 IRQF_SHARED, "ath10k_pci", ar);
2152 if (ret) {
2153 ath10k_warn("request_irq(%d) failed %d\n",
2154 ar_pci->pdev->irq + MSI_ASSIGN_FW, ret);
2155
2156 pci_disable_msi(ar_pci->pdev);
2157 return ret;
2158 }
2159
2160 for (i = MSI_ASSIGN_CE_INITIAL; i <= MSI_ASSIGN_CE_MAX; i++) {
2161 ret = request_irq(ar_pci->pdev->irq + i,
2162 ath10k_pci_per_engine_handler,
2163 IRQF_SHARED, "ath10k_pci", ar);
2164 if (ret) {
2165 ath10k_warn("request_irq(%d) failed %d\n",
2166 ar_pci->pdev->irq + i, ret);
2167
2168 for (i--; i >= MSI_ASSIGN_CE_INITIAL; i--)
2169 free_irq(ar_pci->pdev->irq + i, ar);
2170
2171 free_irq(ar_pci->pdev->irq + MSI_ASSIGN_FW, ar);
2172 pci_disable_msi(ar_pci->pdev);
2173 return ret;
2174 }
2175 }
2176
2177 ath10k_dbg(ATH10K_DBG_BOOT,
2178 "MSI-X interrupt handling (%d intrs)\n", num);
2179 return 0;
2180 }
2181
2182 static int ath10k_pci_start_intr_msi(struct ath10k *ar)
2183 {
2184 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2185 int ret;
2186
2187 ret = pci_enable_msi(ar_pci->pdev);
2188 if (ret < 0)
2189 return ret;
2190
2191 ret = request_irq(ar_pci->pdev->irq,
2192 ath10k_pci_interrupt_handler,
2193 IRQF_SHARED, "ath10k_pci", ar);
2194 if (ret < 0) {
2195 pci_disable_msi(ar_pci->pdev);
2196 return ret;
2197 }
2198
2199 ath10k_dbg(ATH10K_DBG_BOOT, "MSI interrupt handling\n");
2200 return 0;
2201 }
2202
2203 static int ath10k_pci_start_intr_legacy(struct ath10k *ar)
2204 {
2205 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2206 int ret;
2207
2208 ret = request_irq(ar_pci->pdev->irq,
2209 ath10k_pci_interrupt_handler,
2210 IRQF_SHARED, "ath10k_pci", ar);
2211 if (ret < 0)
2212 return ret;
2213
2214 ret = ath10k_pci_wake(ar);
2215 if (ret) {
2216 free_irq(ar_pci->pdev->irq, ar);
2217 ath10k_err("failed to wake up target: %d\n", ret);
2218 return ret;
2219 }
2220
2221 /*
2222 * A potential race occurs here: The CORE_BASE write
2223 * depends on target correctly decoding AXI address but
2224 * host won't know when target writes BAR to CORE_CTRL.
2225 * This write might get lost if target has NOT written BAR.
2226 * For now, fix the race by repeating the write in below
2227 * synchronization checking.
2228 */
2229 iowrite32(PCIE_INTR_FIRMWARE_MASK |
2230 PCIE_INTR_CE_MASK_ALL,
2231 ar_pci->mem + (SOC_CORE_BASE_ADDRESS |
2232 PCIE_INTR_ENABLE_ADDRESS));
2233
2234 ath10k_pci_sleep(ar);
2235 ath10k_dbg(ATH10K_DBG_BOOT, "legacy interrupt handling\n");
2236 return 0;
2237 }
2238
2239 static int ath10k_pci_start_intr(struct ath10k *ar)
2240 {
2241 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2242 int num = MSI_NUM_REQUEST;
2243 int ret;
2244 int i;
2245
2246 tasklet_init(&ar_pci->intr_tq, ath10k_pci_tasklet, (unsigned long) ar);
2247 tasklet_init(&ar_pci->msi_fw_err, ath10k_msi_err_tasklet,
2248 (unsigned long) ar);
2249
2250 for (i = 0; i < CE_COUNT; i++) {
2251 ar_pci->pipe_info[i].ar_pci = ar_pci;
2252 tasklet_init(&ar_pci->pipe_info[i].intr,
2253 ath10k_pci_ce_tasklet,
2254 (unsigned long)&ar_pci->pipe_info[i]);
2255 }
2256
2257 if (!test_bit(ATH10K_PCI_FEATURE_MSI_X, ar_pci->features))
2258 num = 1;
2259
2260 if (num > 1) {
2261 ret = ath10k_pci_start_intr_msix(ar, num);
2262 if (ret == 0)
2263 goto exit;
2264
2265 ath10k_dbg(ATH10K_DBG_BOOT,
2266 "MSI-X didn't succeed (%d), trying MSI\n", ret);
2267 num = 1;
2268 }
2269
2270 if (num == 1) {
2271 ret = ath10k_pci_start_intr_msi(ar);
2272 if (ret == 0)
2273 goto exit;
2274
2275 ath10k_dbg(ATH10K_DBG_BOOT,
2276 "MSI didn't succeed (%d), trying legacy INTR\n",
2277 ret);
2278 num = 0;
2279 }
2280
2281 ret = ath10k_pci_start_intr_legacy(ar);
2282 if (ret) {
2283 ath10k_warn("Failed to start legacy interrupts: %d\n", ret);
2284 return ret;
2285 }
2286
2287 exit:
2288 ar_pci->num_msi_intrs = num;
2289 return ret;
2290 }
2291
2292 static void ath10k_pci_stop_intr(struct ath10k *ar)
2293 {
2294 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2295 int i;
2296
2297 /* There's at least one interrupt irregardless whether its legacy INTR
2298 * or MSI or MSI-X */
2299 for (i = 0; i < max(1, ar_pci->num_msi_intrs); i++)
2300 free_irq(ar_pci->pdev->irq + i, ar);
2301
2302 if (ar_pci->num_msi_intrs > 0)
2303 pci_disable_msi(ar_pci->pdev);
2304 }
2305
2306 static int ath10k_pci_wait_for_target_init(struct ath10k *ar)
2307 {
2308 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2309 int wait_limit = 300; /* 3 sec */
2310 int ret;
2311
2312 ret = ath10k_pci_wake(ar);
2313 if (ret) {
2314 ath10k_err("failed to wake up target: %d\n", ret);
2315 return ret;
2316 }
2317
2318 while (wait_limit-- &&
2319 !(ioread32(ar_pci->mem + FW_INDICATOR_ADDRESS) &
2320 FW_IND_INITIALIZED)) {
2321 if (ar_pci->num_msi_intrs == 0)
2322 /* Fix potential race by repeating CORE_BASE writes */
2323 iowrite32(PCIE_INTR_FIRMWARE_MASK |
2324 PCIE_INTR_CE_MASK_ALL,
2325 ar_pci->mem + (SOC_CORE_BASE_ADDRESS |
2326 PCIE_INTR_ENABLE_ADDRESS));
2327 mdelay(10);
2328 }
2329
2330 if (wait_limit < 0) {
2331 ath10k_err("target stalled\n");
2332 ret = -EIO;
2333 goto out;
2334 }
2335
2336 out:
2337 ath10k_pci_sleep(ar);
2338 return ret;
2339 }
2340
2341 static int ath10k_pci_device_reset(struct ath10k *ar)
2342 {
2343 int i, ret;
2344 u32 val;
2345
2346 ret = ath10k_do_pci_wake(ar);
2347 if (ret) {
2348 ath10k_err("failed to wake up target: %d\n",
2349 ret);
2350 return ret;
2351 }
2352
2353 /* Put Target, including PCIe, into RESET. */
2354 val = ath10k_pci_reg_read32(ar, SOC_GLOBAL_RESET_ADDRESS);
2355 val |= 1;
2356 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val);
2357
2358 for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) {
2359 if (ath10k_pci_reg_read32(ar, RTC_STATE_ADDRESS) &
2360 RTC_STATE_COLD_RESET_MASK)
2361 break;
2362 msleep(1);
2363 }
2364
2365 /* Pull Target, including PCIe, out of RESET. */
2366 val &= ~1;
2367 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val);
2368
2369 for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) {
2370 if (!(ath10k_pci_reg_read32(ar, RTC_STATE_ADDRESS) &
2371 RTC_STATE_COLD_RESET_MASK))
2372 break;
2373 msleep(1);
2374 }
2375
2376 ath10k_do_pci_sleep(ar);
2377 return 0;
2378 }
2379
2380 static void ath10k_pci_dump_features(struct ath10k_pci *ar_pci)
2381 {
2382 int i;
2383
2384 for (i = 0; i < ATH10K_PCI_FEATURE_COUNT; i++) {
2385 if (!test_bit(i, ar_pci->features))
2386 continue;
2387
2388 switch (i) {
2389 case ATH10K_PCI_FEATURE_MSI_X:
2390 ath10k_dbg(ATH10K_DBG_BOOT, "device supports MSI-X\n");
2391 break;
2392 case ATH10K_PCI_FEATURE_SOC_POWER_SAVE:
2393 ath10k_dbg(ATH10K_DBG_BOOT, "QCA98XX SoC power save enabled\n");
2394 break;
2395 }
2396 }
2397 }
2398
2399 static int ath10k_pci_probe(struct pci_dev *pdev,
2400 const struct pci_device_id *pci_dev)
2401 {
2402 void __iomem *mem;
2403 int ret = 0;
2404 struct ath10k *ar;
2405 struct ath10k_pci *ar_pci;
2406 u32 lcr_val, chip_id;
2407
2408 ath10k_dbg(ATH10K_DBG_PCI, "%s\n", __func__);
2409
2410 ar_pci = kzalloc(sizeof(*ar_pci), GFP_KERNEL);
2411 if (ar_pci == NULL)
2412 return -ENOMEM;
2413
2414 ar_pci->pdev = pdev;
2415 ar_pci->dev = &pdev->dev;
2416
2417 switch (pci_dev->device) {
2418 case QCA988X_2_0_DEVICE_ID:
2419 set_bit(ATH10K_PCI_FEATURE_MSI_X, ar_pci->features);
2420 break;
2421 default:
2422 ret = -ENODEV;
2423 ath10k_err("Unkown device ID: %d\n", pci_dev->device);
2424 goto err_ar_pci;
2425 }
2426
2427 if (ath10k_target_ps)
2428 set_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE, ar_pci->features);
2429
2430 ath10k_pci_dump_features(ar_pci);
2431
2432 ar = ath10k_core_create(ar_pci, ar_pci->dev, &ath10k_pci_hif_ops);
2433 if (!ar) {
2434 ath10k_err("failed to create driver core\n");
2435 ret = -EINVAL;
2436 goto err_ar_pci;
2437 }
2438
2439 ar_pci->ar = ar;
2440 ar_pci->fw_indicator_address = FW_INDICATOR_ADDRESS;
2441 atomic_set(&ar_pci->keep_awake_count, 0);
2442
2443 pci_set_drvdata(pdev, ar);
2444
2445 /*
2446 * Without any knowledge of the Host, the Target may have been reset or
2447 * power cycled and its Config Space may no longer reflect the PCI
2448 * address space that was assigned earlier by the PCI infrastructure.
2449 * Refresh it now.
2450 */
2451 ret = pci_assign_resource(pdev, BAR_NUM);
2452 if (ret) {
2453 ath10k_err("failed to assign PCI space: %d\n", ret);
2454 goto err_ar;
2455 }
2456
2457 ret = pci_enable_device(pdev);
2458 if (ret) {
2459 ath10k_err("failed to enable PCI device: %d\n", ret);
2460 goto err_ar;
2461 }
2462
2463 /* Request MMIO resources */
2464 ret = pci_request_region(pdev, BAR_NUM, "ath");
2465 if (ret) {
2466 ath10k_err("failed to request MMIO region: %d\n", ret);
2467 goto err_device;
2468 }
2469
2470 /*
2471 * Target structures have a limit of 32 bit DMA pointers.
2472 * DMA pointers can be wider than 32 bits by default on some systems.
2473 */
2474 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2475 if (ret) {
2476 ath10k_err("failed to set DMA mask to 32-bit: %d\n", ret);
2477 goto err_region;
2478 }
2479
2480 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
2481 if (ret) {
2482 ath10k_err("failed to set consistent DMA mask to 32-bit\n");
2483 goto err_region;
2484 }
2485
2486 /* Set bus master bit in PCI_COMMAND to enable DMA */
2487 pci_set_master(pdev);
2488
2489 /*
2490 * Temporary FIX: disable ASPM
2491 * Will be removed after the OTP is programmed
2492 */
2493 pci_read_config_dword(pdev, 0x80, &lcr_val);
2494 pci_write_config_dword(pdev, 0x80, (lcr_val & 0xffffff00));
2495
2496 /* Arrange for access to Target SoC registers. */
2497 mem = pci_iomap(pdev, BAR_NUM, 0);
2498 if (!mem) {
2499 ath10k_err("failed to perform IOMAP for BAR%d\n", BAR_NUM);
2500 ret = -EIO;
2501 goto err_master;
2502 }
2503
2504 ar_pci->mem = mem;
2505
2506 spin_lock_init(&ar_pci->ce_lock);
2507
2508 ret = ath10k_do_pci_wake(ar);
2509 if (ret) {
2510 ath10k_err("Failed to get chip id: %d\n", ret);
2511 goto err_iomap;
2512 }
2513
2514 chip_id = ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS);
2515
2516 ath10k_do_pci_sleep(ar);
2517
2518 ath10k_dbg(ATH10K_DBG_BOOT, "boot pci_mem 0x%p\n", ar_pci->mem);
2519
2520 ret = ath10k_core_register(ar, chip_id);
2521 if (ret) {
2522 ath10k_err("failed to register driver core: %d\n", ret);
2523 goto err_iomap;
2524 }
2525
2526 return 0;
2527
2528 err_iomap:
2529 pci_iounmap(pdev, mem);
2530 err_master:
2531 pci_clear_master(pdev);
2532 err_region:
2533 pci_release_region(pdev, BAR_NUM);
2534 err_device:
2535 pci_disable_device(pdev);
2536 err_ar:
2537 ath10k_core_destroy(ar);
2538 err_ar_pci:
2539 /* call HIF PCI free here */
2540 kfree(ar_pci);
2541
2542 return ret;
2543 }
2544
2545 static void ath10k_pci_remove(struct pci_dev *pdev)
2546 {
2547 struct ath10k *ar = pci_get_drvdata(pdev);
2548 struct ath10k_pci *ar_pci;
2549
2550 ath10k_dbg(ATH10K_DBG_PCI, "%s\n", __func__);
2551
2552 if (!ar)
2553 return;
2554
2555 ar_pci = ath10k_pci_priv(ar);
2556
2557 if (!ar_pci)
2558 return;
2559
2560 tasklet_kill(&ar_pci->msi_fw_err);
2561
2562 ath10k_core_unregister(ar);
2563
2564 pci_iounmap(pdev, ar_pci->mem);
2565 pci_release_region(pdev, BAR_NUM);
2566 pci_clear_master(pdev);
2567 pci_disable_device(pdev);
2568
2569 ath10k_core_destroy(ar);
2570 kfree(ar_pci);
2571 }
2572
2573 MODULE_DEVICE_TABLE(pci, ath10k_pci_id_table);
2574
2575 static struct pci_driver ath10k_pci_driver = {
2576 .name = "ath10k_pci",
2577 .id_table = ath10k_pci_id_table,
2578 .probe = ath10k_pci_probe,
2579 .remove = ath10k_pci_remove,
2580 };
2581
2582 static int __init ath10k_pci_init(void)
2583 {
2584 int ret;
2585
2586 ret = pci_register_driver(&ath10k_pci_driver);
2587 if (ret)
2588 ath10k_err("failed to register PCI driver: %d\n", ret);
2589
2590 return ret;
2591 }
2592 module_init(ath10k_pci_init);
2593
2594 static void __exit ath10k_pci_exit(void)
2595 {
2596 pci_unregister_driver(&ath10k_pci_driver);
2597 }
2598
2599 module_exit(ath10k_pci_exit);
2600
2601 MODULE_AUTHOR("Qualcomm Atheros");
2602 MODULE_DESCRIPTION("Driver support for Atheros QCA988X PCIe devices");
2603 MODULE_LICENSE("Dual BSD/GPL");
2604 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_FW_FILE);
2605 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_OTP_FILE);
2606 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_BOARD_DATA_FILE);
Linux kernel - Deliverables
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