2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <linux/pci.h>
19 #include <linux/module.h>
20 #include <linux/interrupt.h>
21 #include <linux/spinlock.h>
26 #include "targaddrs.h"
35 static unsigned int ath10k_target_ps
;
36 module_param(ath10k_target_ps
, uint
, 0644);
37 MODULE_PARM_DESC(ath10k_target_ps
, "Enable ath10k Target (SoC) PS option");
39 #define QCA988X_2_0_DEVICE_ID (0x003c)
41 static DEFINE_PCI_DEVICE_TABLE(ath10k_pci_id_table
) = {
42 { PCI_VDEVICE(ATHEROS
, QCA988X_2_0_DEVICE_ID
) }, /* PCI-E QCA988X V2 */
46 static int ath10k_pci_diag_read_access(struct ath10k
*ar
, u32 address
,
49 static void ath10k_pci_process_ce(struct ath10k
*ar
);
50 static int ath10k_pci_post_rx(struct ath10k
*ar
);
51 static int ath10k_pci_post_rx_pipe(struct ath10k_pci_pipe
*pipe_info
,
53 static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe
*pipe_info
);
54 static void ath10k_pci_stop_ce(struct ath10k
*ar
);
55 static int ath10k_pci_device_reset(struct ath10k
*ar
);
56 static int ath10k_pci_wait_for_target_init(struct ath10k
*ar
);
57 static int ath10k_pci_start_intr(struct ath10k
*ar
);
58 static void ath10k_pci_stop_intr(struct ath10k
*ar
);
60 static const struct ce_attr host_ce_config_wlan
[] = {
61 /* CE0: host->target HTC control and raw streams */
63 .flags
= CE_ATTR_FLAGS
,
69 /* CE1: target->host HTT + HTC control */
71 .flags
= CE_ATTR_FLAGS
,
77 /* CE2: target->host WMI */
79 .flags
= CE_ATTR_FLAGS
,
85 /* CE3: host->target WMI */
87 .flags
= CE_ATTR_FLAGS
,
93 /* CE4: host->target HTT */
95 .flags
= CE_ATTR_FLAGS
| CE_ATTR_DIS_INTR
,
96 .src_nentries
= CE_HTT_H2T_MSG_SRC_NENTRIES
,
103 .flags
= CE_ATTR_FLAGS
,
109 /* CE6: target autonomous hif_memcpy */
111 .flags
= CE_ATTR_FLAGS
,
117 /* CE7: ce_diag, the Diagnostic Window */
119 .flags
= CE_ATTR_FLAGS
,
121 .src_sz_max
= DIAG_TRANSFER_LIMIT
,
126 /* Target firmware's Copy Engine configuration. */
127 static const struct ce_pipe_config target_ce_config_wlan
[] = {
128 /* CE0: host->target HTC control and raw streams */
131 .pipedir
= PIPEDIR_OUT
,
134 .flags
= CE_ATTR_FLAGS
,
138 /* CE1: target->host HTT + HTC control */
141 .pipedir
= PIPEDIR_IN
,
144 .flags
= CE_ATTR_FLAGS
,
148 /* CE2: target->host WMI */
151 .pipedir
= PIPEDIR_IN
,
154 .flags
= CE_ATTR_FLAGS
,
158 /* CE3: host->target WMI */
161 .pipedir
= PIPEDIR_OUT
,
164 .flags
= CE_ATTR_FLAGS
,
168 /* CE4: host->target HTT */
171 .pipedir
= PIPEDIR_OUT
,
174 .flags
= CE_ATTR_FLAGS
,
178 /* NB: 50% of src nentries, since tx has 2 frags */
183 .pipedir
= PIPEDIR_OUT
,
186 .flags
= CE_ATTR_FLAGS
,
190 /* CE6: Reserved for target autonomous hif_memcpy */
193 .pipedir
= PIPEDIR_INOUT
,
196 .flags
= CE_ATTR_FLAGS
,
200 /* CE7 used only by Host */
204 * Diagnostic read/write access is provided for startup/config/debug usage.
205 * Caller must guarantee proper alignment, when applicable, and single user
208 static int ath10k_pci_diag_read_mem(struct ath10k
*ar
, u32 address
, void *data
,
211 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
214 unsigned int completed_nbytes
, orig_nbytes
, remaining_bytes
;
217 struct ath10k_ce_pipe
*ce_diag
;
218 /* Host buffer address in CE space */
220 dma_addr_t ce_data_base
= 0;
221 void *data_buf
= NULL
;
225 * This code cannot handle reads to non-memory space. Redirect to the
226 * register read fn but preserve the multi word read capability of
229 if (address
< DRAM_BASE_ADDRESS
) {
230 if (!IS_ALIGNED(address
, 4) ||
231 !IS_ALIGNED((unsigned long)data
, 4))
234 while ((nbytes
>= 4) && ((ret
= ath10k_pci_diag_read_access(
235 ar
, address
, (u32
*)data
)) == 0)) {
236 nbytes
-= sizeof(u32
);
237 address
+= sizeof(u32
);
243 ce_diag
= ar_pci
->ce_diag
;
246 * Allocate a temporary bounce buffer to hold caller's data
247 * to be DMA'ed from Target. This guarantees
248 * 1) 4-byte alignment
249 * 2) Buffer in DMA-able space
251 orig_nbytes
= nbytes
;
252 data_buf
= (unsigned char *)pci_alloc_consistent(ar_pci
->pdev
,
260 memset(data_buf
, 0, orig_nbytes
);
262 remaining_bytes
= orig_nbytes
;
263 ce_data
= ce_data_base
;
264 while (remaining_bytes
) {
265 nbytes
= min_t(unsigned int, remaining_bytes
,
266 DIAG_TRANSFER_LIMIT
);
268 ret
= ath10k_ce_recv_buf_enqueue(ce_diag
, NULL
, ce_data
);
272 /* Request CE to send from Target(!) address to Host buffer */
274 * The address supplied by the caller is in the
275 * Target CPU virtual address space.
277 * In order to use this address with the diagnostic CE,
278 * convert it from Target CPU virtual address space
279 * to CE address space
282 address
= TARG_CPU_SPACE_TO_CE_SPACE(ar
, ar_pci
->mem
,
284 ath10k_pci_sleep(ar
);
286 ret
= ath10k_ce_send(ce_diag
, NULL
, (u32
)address
, nbytes
, 0,
292 while (ath10k_ce_completed_send_next(ce_diag
, NULL
, &buf
,
296 if (i
++ > DIAG_ACCESS_CE_TIMEOUT_MS
) {
302 if (nbytes
!= completed_nbytes
) {
307 if (buf
!= (u32
) address
) {
313 while (ath10k_ce_completed_recv_next(ce_diag
, NULL
, &buf
,
318 if (i
++ > DIAG_ACCESS_CE_TIMEOUT_MS
) {
324 if (nbytes
!= completed_nbytes
) {
329 if (buf
!= ce_data
) {
334 remaining_bytes
-= nbytes
;
341 /* Copy data from allocated DMA buf to caller's buf */
342 WARN_ON_ONCE(orig_nbytes
& 3);
343 for (i
= 0; i
< orig_nbytes
/ sizeof(__le32
); i
++) {
345 __le32_to_cpu(((__le32
*)data_buf
)[i
]);
348 ath10k_dbg(ATH10K_DBG_PCI
, "%s failure (0x%x)\n",
352 pci_free_consistent(ar_pci
->pdev
, orig_nbytes
,
353 data_buf
, ce_data_base
);
358 /* Read 4-byte aligned data from Target memory or register */
359 static int ath10k_pci_diag_read_access(struct ath10k
*ar
, u32 address
,
362 /* Assume range doesn't cross this boundary */
363 if (address
>= DRAM_BASE_ADDRESS
)
364 return ath10k_pci_diag_read_mem(ar
, address
, data
, sizeof(u32
));
367 *data
= ath10k_pci_read32(ar
, address
);
368 ath10k_pci_sleep(ar
);
372 static int ath10k_pci_diag_write_mem(struct ath10k
*ar
, u32 address
,
373 const void *data
, int nbytes
)
375 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
378 unsigned int completed_nbytes
, orig_nbytes
, remaining_bytes
;
381 struct ath10k_ce_pipe
*ce_diag
;
382 void *data_buf
= NULL
;
383 u32 ce_data
; /* Host buffer address in CE space */
384 dma_addr_t ce_data_base
= 0;
387 ce_diag
= ar_pci
->ce_diag
;
390 * Allocate a temporary bounce buffer to hold caller's data
391 * to be DMA'ed to Target. This guarantees
392 * 1) 4-byte alignment
393 * 2) Buffer in DMA-able space
395 orig_nbytes
= nbytes
;
396 data_buf
= (unsigned char *)pci_alloc_consistent(ar_pci
->pdev
,
404 /* Copy caller's data to allocated DMA buf */
405 WARN_ON_ONCE(orig_nbytes
& 3);
406 for (i
= 0; i
< orig_nbytes
/ sizeof(__le32
); i
++)
407 ((__le32
*)data_buf
)[i
] = __cpu_to_le32(((u32
*)data
)[i
]);
410 * The address supplied by the caller is in the
411 * Target CPU virtual address space.
413 * In order to use this address with the diagnostic CE,
415 * Target CPU virtual address space
420 address
= TARG_CPU_SPACE_TO_CE_SPACE(ar
, ar_pci
->mem
, address
);
421 ath10k_pci_sleep(ar
);
423 remaining_bytes
= orig_nbytes
;
424 ce_data
= ce_data_base
;
425 while (remaining_bytes
) {
426 /* FIXME: check cast */
427 nbytes
= min_t(int, remaining_bytes
, DIAG_TRANSFER_LIMIT
);
429 /* Set up to receive directly into Target(!) address */
430 ret
= ath10k_ce_recv_buf_enqueue(ce_diag
, NULL
, address
);
435 * Request CE to send caller-supplied data that
436 * was copied to bounce buffer to Target(!) address.
438 ret
= ath10k_ce_send(ce_diag
, NULL
, (u32
) ce_data
,
444 while (ath10k_ce_completed_send_next(ce_diag
, NULL
, &buf
,
449 if (i
++ > DIAG_ACCESS_CE_TIMEOUT_MS
) {
455 if (nbytes
!= completed_nbytes
) {
460 if (buf
!= ce_data
) {
466 while (ath10k_ce_completed_recv_next(ce_diag
, NULL
, &buf
,
471 if (i
++ > DIAG_ACCESS_CE_TIMEOUT_MS
) {
477 if (nbytes
!= completed_nbytes
) {
482 if (buf
!= address
) {
487 remaining_bytes
-= nbytes
;
494 pci_free_consistent(ar_pci
->pdev
, orig_nbytes
, data_buf
,
499 ath10k_dbg(ATH10K_DBG_PCI
, "%s failure (0x%x)\n", __func__
,
505 /* Write 4B data to Target memory or register */
506 static int ath10k_pci_diag_write_access(struct ath10k
*ar
, u32 address
,
509 /* Assume range doesn't cross this boundary */
510 if (address
>= DRAM_BASE_ADDRESS
)
511 return ath10k_pci_diag_write_mem(ar
, address
, &data
,
515 ath10k_pci_write32(ar
, address
, data
);
516 ath10k_pci_sleep(ar
);
520 static bool ath10k_pci_target_is_awake(struct ath10k
*ar
)
522 void __iomem
*mem
= ath10k_pci_priv(ar
)->mem
;
524 val
= ioread32(mem
+ PCIE_LOCAL_BASE_ADDRESS
+
526 return (RTC_STATE_V_GET(val
) == RTC_STATE_V_ON
);
529 int ath10k_do_pci_wake(struct ath10k
*ar
)
531 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
532 void __iomem
*pci_addr
= ar_pci
->mem
;
536 if (atomic_read(&ar_pci
->keep_awake_count
) == 0) {
538 iowrite32(PCIE_SOC_WAKE_V_MASK
,
539 pci_addr
+ PCIE_LOCAL_BASE_ADDRESS
+
540 PCIE_SOC_WAKE_ADDRESS
);
542 atomic_inc(&ar_pci
->keep_awake_count
);
544 if (ar_pci
->verified_awake
)
548 if (ath10k_pci_target_is_awake(ar
)) {
549 ar_pci
->verified_awake
= true;
553 if (tot_delay
> PCIE_WAKE_TIMEOUT
) {
554 ath10k_warn("target took longer %d us to wake up (awake count %d)\n",
556 atomic_read(&ar_pci
->keep_awake_count
));
561 tot_delay
+= curr_delay
;
568 void ath10k_do_pci_sleep(struct ath10k
*ar
)
570 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
571 void __iomem
*pci_addr
= ar_pci
->mem
;
573 if (atomic_dec_and_test(&ar_pci
->keep_awake_count
)) {
575 ar_pci
->verified_awake
= false;
576 iowrite32(PCIE_SOC_WAKE_RESET
,
577 pci_addr
+ PCIE_LOCAL_BASE_ADDRESS
+
578 PCIE_SOC_WAKE_ADDRESS
);
583 * FIXME: Handle OOM properly.
586 struct ath10k_pci_compl
*get_free_compl(struct ath10k_pci_pipe
*pipe_info
)
588 struct ath10k_pci_compl
*compl = NULL
;
590 spin_lock_bh(&pipe_info
->pipe_lock
);
591 if (list_empty(&pipe_info
->compl_free
)) {
592 ath10k_warn("Completion buffers are full\n");
595 compl = list_first_entry(&pipe_info
->compl_free
,
596 struct ath10k_pci_compl
, list
);
597 list_del(&compl->list
);
599 spin_unlock_bh(&pipe_info
->pipe_lock
);
603 /* Called by lower (CE) layer when a send to Target completes. */
604 static void ath10k_pci_ce_send_done(struct ath10k_ce_pipe
*ce_state
)
606 struct ath10k
*ar
= ce_state
->ar
;
607 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
608 struct ath10k_pci_pipe
*pipe_info
= &ar_pci
->pipe_info
[ce_state
->id
];
609 struct ath10k_pci_compl
*compl;
610 void *transfer_context
;
613 unsigned int transfer_id
;
615 while (ath10k_ce_completed_send_next(ce_state
, &transfer_context
,
617 &transfer_id
) == 0) {
618 compl = get_free_compl(pipe_info
);
622 compl->state
= ATH10K_PCI_COMPL_SEND
;
623 compl->ce_state
= ce_state
;
624 compl->pipe_info
= pipe_info
;
625 compl->skb
= transfer_context
;
626 compl->nbytes
= nbytes
;
627 compl->transfer_id
= transfer_id
;
631 * Add the completion to the processing queue.
633 spin_lock_bh(&ar_pci
->compl_lock
);
634 list_add_tail(&compl->list
, &ar_pci
->compl_process
);
635 spin_unlock_bh(&ar_pci
->compl_lock
);
638 ath10k_pci_process_ce(ar
);
641 /* Called by lower (CE) layer when data is received from the Target. */
642 static void ath10k_pci_ce_recv_data(struct ath10k_ce_pipe
*ce_state
)
644 struct ath10k
*ar
= ce_state
->ar
;
645 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
646 struct ath10k_pci_pipe
*pipe_info
= &ar_pci
->pipe_info
[ce_state
->id
];
647 struct ath10k_pci_compl
*compl;
649 void *transfer_context
;
652 unsigned int transfer_id
;
655 while (ath10k_ce_completed_recv_next(ce_state
, &transfer_context
,
656 &ce_data
, &nbytes
, &transfer_id
,
658 compl = get_free_compl(pipe_info
);
662 compl->state
= ATH10K_PCI_COMPL_RECV
;
663 compl->ce_state
= ce_state
;
664 compl->pipe_info
= pipe_info
;
665 compl->skb
= transfer_context
;
666 compl->nbytes
= nbytes
;
667 compl->transfer_id
= transfer_id
;
668 compl->flags
= flags
;
670 skb
= transfer_context
;
671 dma_unmap_single(ar
->dev
, ATH10K_SKB_CB(skb
)->paddr
,
672 skb
->len
+ skb_tailroom(skb
),
675 * Add the completion to the processing queue.
677 spin_lock_bh(&ar_pci
->compl_lock
);
678 list_add_tail(&compl->list
, &ar_pci
->compl_process
);
679 spin_unlock_bh(&ar_pci
->compl_lock
);
682 ath10k_pci_process_ce(ar
);
685 /* Send the first nbytes bytes of the buffer */
686 static int ath10k_pci_hif_send_head(struct ath10k
*ar
, u8 pipe_id
,
687 unsigned int transfer_id
,
688 unsigned int bytes
, struct sk_buff
*nbuf
)
690 struct ath10k_skb_cb
*skb_cb
= ATH10K_SKB_CB(nbuf
);
691 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
692 struct ath10k_pci_pipe
*pipe_info
= &(ar_pci
->pipe_info
[pipe_id
]);
693 struct ath10k_ce_pipe
*ce_hdl
= pipe_info
->ce_hdl
;
698 len
= min(bytes
, nbuf
->len
);
702 ath10k_warn("skb not aligned to 4-byte boundary (%d)\n", len
);
704 ath10k_dbg(ATH10K_DBG_PCI
,
705 "pci send data vaddr %p paddr 0x%llx len %d as %d bytes\n",
706 nbuf
->data
, (unsigned long long) skb_cb
->paddr
,
708 ath10k_dbg_dump(ATH10K_DBG_PCI_DUMP
, NULL
,
710 nbuf
->data
, nbuf
->len
);
712 ret
= ath10k_ce_send(ce_hdl
, nbuf
, skb_cb
->paddr
, len
, transfer_id
,
715 ath10k_warn("failed to send sk_buff to CE: %p\n", nbuf
);
720 static u16
ath10k_pci_hif_get_free_queue_number(struct ath10k
*ar
, u8 pipe
)
722 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
723 return ath10k_ce_num_free_src_entries(ar_pci
->pipe_info
[pipe
].ce_hdl
);
726 static void ath10k_pci_hif_dump_area(struct ath10k
*ar
)
728 u32 reg_dump_area
= 0;
729 u32 reg_dump_values
[REG_DUMP_COUNT_QCA988X
] = {};
734 ath10k_err("firmware crashed!\n");
735 ath10k_err("hardware name %s version 0x%x\n",
736 ar
->hw_params
.name
, ar
->target_version
);
737 ath10k_err("firmware version: %u.%u.%u.%u\n", ar
->fw_version_major
,
738 ar
->fw_version_minor
, ar
->fw_version_release
,
739 ar
->fw_version_build
);
741 host_addr
= host_interest_item_address(HI_ITEM(hi_failure_state
));
742 ret
= ath10k_pci_diag_read_mem(ar
, host_addr
,
743 ®_dump_area
, sizeof(u32
));
745 ath10k_err("failed to read FW dump area address: %d\n", ret
);
749 ath10k_err("target register Dump Location: 0x%08X\n", reg_dump_area
);
751 ret
= ath10k_pci_diag_read_mem(ar
, reg_dump_area
,
753 REG_DUMP_COUNT_QCA988X
* sizeof(u32
));
755 ath10k_err("failed to read FW dump area: %d\n", ret
);
759 BUILD_BUG_ON(REG_DUMP_COUNT_QCA988X
% 4);
761 ath10k_err("target Register Dump\n");
762 for (i
= 0; i
< REG_DUMP_COUNT_QCA988X
; i
+= 4)
763 ath10k_err("[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X\n",
766 reg_dump_values
[i
+ 1],
767 reg_dump_values
[i
+ 2],
768 reg_dump_values
[i
+ 3]);
770 queue_work(ar
->workqueue
, &ar
->restart_work
);
773 static void ath10k_pci_hif_send_complete_check(struct ath10k
*ar
, u8 pipe
,
779 * Decide whether to actually poll for completions, or just
780 * wait for a later chance.
781 * If there seem to be plenty of resources left, then just wait
782 * since checking involves reading a CE register, which is a
783 * relatively expensive operation.
785 resources
= ath10k_pci_hif_get_free_queue_number(ar
, pipe
);
788 * If at least 50% of the total resources are still available,
789 * don't bother checking again yet.
791 if (resources
> (host_ce_config_wlan
[pipe
].src_nentries
>> 1))
794 ath10k_ce_per_engine_service(ar
, pipe
);
797 static void ath10k_pci_hif_set_callbacks(struct ath10k
*ar
,
798 struct ath10k_hif_cb
*callbacks
)
800 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
802 ath10k_dbg(ATH10K_DBG_PCI
, "%s\n", __func__
);
804 memcpy(&ar_pci
->msg_callbacks_current
, callbacks
,
805 sizeof(ar_pci
->msg_callbacks_current
));
808 static int ath10k_pci_start_ce(struct ath10k
*ar
)
810 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
811 struct ath10k_ce_pipe
*ce_diag
= ar_pci
->ce_diag
;
812 const struct ce_attr
*attr
;
813 struct ath10k_pci_pipe
*pipe_info
;
814 struct ath10k_pci_compl
*compl;
815 int i
, pipe_num
, completions
, disable_interrupts
;
817 spin_lock_init(&ar_pci
->compl_lock
);
818 INIT_LIST_HEAD(&ar_pci
->compl_process
);
820 for (pipe_num
= 0; pipe_num
< CE_COUNT
; pipe_num
++) {
821 pipe_info
= &ar_pci
->pipe_info
[pipe_num
];
823 spin_lock_init(&pipe_info
->pipe_lock
);
824 INIT_LIST_HEAD(&pipe_info
->compl_free
);
826 /* Handle Diagnostic CE specially */
827 if (pipe_info
->ce_hdl
== ce_diag
)
830 attr
= &host_ce_config_wlan
[pipe_num
];
833 if (attr
->src_nentries
) {
834 disable_interrupts
= attr
->flags
& CE_ATTR_DIS_INTR
;
835 ath10k_ce_send_cb_register(pipe_info
->ce_hdl
,
836 ath10k_pci_ce_send_done
,
838 completions
+= attr
->src_nentries
;
841 if (attr
->dest_nentries
) {
842 ath10k_ce_recv_cb_register(pipe_info
->ce_hdl
,
843 ath10k_pci_ce_recv_data
);
844 completions
+= attr
->dest_nentries
;
847 if (completions
== 0)
850 for (i
= 0; i
< completions
; i
++) {
851 compl = kmalloc(sizeof(*compl), GFP_KERNEL
);
853 ath10k_warn("No memory for completion state\n");
854 ath10k_pci_stop_ce(ar
);
858 compl->state
= ATH10K_PCI_COMPL_FREE
;
859 list_add_tail(&compl->list
, &pipe_info
->compl_free
);
866 static void ath10k_pci_kill_tasklet(struct ath10k
*ar
)
868 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
871 tasklet_kill(&ar_pci
->intr_tq
);
872 tasklet_kill(&ar_pci
->msi_fw_err
);
874 for (i
= 0; i
< CE_COUNT
; i
++)
875 tasklet_kill(&ar_pci
->pipe_info
[i
].intr
);
878 static void ath10k_pci_stop_ce(struct ath10k
*ar
)
880 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
881 struct ath10k_pci_compl
*compl;
885 ret
= ath10k_ce_disable_interrupts(ar
);
887 ath10k_warn("failed to disable CE interrupts: %d\n", ret
);
889 ath10k_pci_kill_tasklet(ar
);
891 /* Mark pending completions as aborted, so that upper layers free up
892 * their associated resources */
893 spin_lock_bh(&ar_pci
->compl_lock
);
894 list_for_each_entry(compl, &ar_pci
->compl_process
, list
) {
896 ATH10K_SKB_CB(skb
)->is_aborted
= true;
898 spin_unlock_bh(&ar_pci
->compl_lock
);
901 static void ath10k_pci_cleanup_ce(struct ath10k
*ar
)
903 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
904 struct ath10k_pci_compl
*compl, *tmp
;
905 struct ath10k_pci_pipe
*pipe_info
;
906 struct sk_buff
*netbuf
;
909 /* Free pending completions. */
910 spin_lock_bh(&ar_pci
->compl_lock
);
911 if (!list_empty(&ar_pci
->compl_process
))
912 ath10k_warn("pending completions still present! possible memory leaks.\n");
914 list_for_each_entry_safe(compl, tmp
, &ar_pci
->compl_process
, list
) {
915 list_del(&compl->list
);
917 dev_kfree_skb_any(netbuf
);
920 spin_unlock_bh(&ar_pci
->compl_lock
);
922 /* Free unused completions for each pipe. */
923 for (pipe_num
= 0; pipe_num
< CE_COUNT
; pipe_num
++) {
924 pipe_info
= &ar_pci
->pipe_info
[pipe_num
];
926 spin_lock_bh(&pipe_info
->pipe_lock
);
927 list_for_each_entry_safe(compl, tmp
,
928 &pipe_info
->compl_free
, list
) {
929 list_del(&compl->list
);
932 spin_unlock_bh(&pipe_info
->pipe_lock
);
936 static void ath10k_pci_process_ce(struct ath10k
*ar
)
938 struct ath10k_pci
*ar_pci
= ar
->hif
.priv
;
939 struct ath10k_hif_cb
*cb
= &ar_pci
->msg_callbacks_current
;
940 struct ath10k_pci_compl
*compl;
943 int ret
, send_done
= 0;
945 /* Upper layers aren't ready to handle tx/rx completions in parallel so
946 * we must serialize all completion processing. */
948 spin_lock_bh(&ar_pci
->compl_lock
);
949 if (ar_pci
->compl_processing
) {
950 spin_unlock_bh(&ar_pci
->compl_lock
);
953 ar_pci
->compl_processing
= true;
954 spin_unlock_bh(&ar_pci
->compl_lock
);
957 spin_lock_bh(&ar_pci
->compl_lock
);
958 if (list_empty(&ar_pci
->compl_process
)) {
959 spin_unlock_bh(&ar_pci
->compl_lock
);
962 compl = list_first_entry(&ar_pci
->compl_process
,
963 struct ath10k_pci_compl
, list
);
964 list_del(&compl->list
);
965 spin_unlock_bh(&ar_pci
->compl_lock
);
967 switch (compl->state
) {
968 case ATH10K_PCI_COMPL_SEND
:
969 cb
->tx_completion(ar
,
974 case ATH10K_PCI_COMPL_RECV
:
975 ret
= ath10k_pci_post_rx_pipe(compl->pipe_info
, 1);
977 ath10k_warn("failed to post RX buffer for pipe %d: %d\n",
978 compl->pipe_info
->pipe_num
, ret
);
983 nbytes
= compl->nbytes
;
985 ath10k_dbg(ATH10K_DBG_PCI
,
986 "ath10k_pci_ce_recv_data netbuf=%p nbytes=%d\n",
988 ath10k_dbg_dump(ATH10K_DBG_PCI_DUMP
, NULL
,
989 "ath10k rx: ", skb
->data
, nbytes
);
991 if (skb
->len
+ skb_tailroom(skb
) >= nbytes
) {
993 skb_put(skb
, nbytes
);
994 cb
->rx_completion(ar
, skb
,
995 compl->pipe_info
->pipe_num
);
997 ath10k_warn("rxed more than expected (nbytes %d, max %d)",
999 skb
->len
+ skb_tailroom(skb
));
1002 case ATH10K_PCI_COMPL_FREE
:
1003 ath10k_warn("free completion cannot be processed\n");
1006 ath10k_warn("invalid completion state (%d)\n",
1011 compl->state
= ATH10K_PCI_COMPL_FREE
;
1014 * Add completion back to the pipe's free list.
1016 spin_lock_bh(&compl->pipe_info
->pipe_lock
);
1017 list_add_tail(&compl->list
, &compl->pipe_info
->compl_free
);
1018 spin_unlock_bh(&compl->pipe_info
->pipe_lock
);
1021 spin_lock_bh(&ar_pci
->compl_lock
);
1022 ar_pci
->compl_processing
= false;
1023 spin_unlock_bh(&ar_pci
->compl_lock
);
1026 /* TODO - temporary mapping while we have too few CE's */
1027 static int ath10k_pci_hif_map_service_to_pipe(struct ath10k
*ar
,
1028 u16 service_id
, u8
*ul_pipe
,
1029 u8
*dl_pipe
, int *ul_is_polled
,
1034 /* polling for received messages not supported */
1037 switch (service_id
) {
1038 case ATH10K_HTC_SVC_ID_HTT_DATA_MSG
:
1040 * Host->target HTT gets its own pipe, so it can be polled
1041 * while other pipes are interrupt driven.
1045 * Use the same target->host pipe for HTC ctrl, HTC raw
1051 case ATH10K_HTC_SVC_ID_RSVD_CTRL
:
1052 case ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS
:
1054 * Note: HTC_RAW_STREAMS_SVC is currently unused, and
1055 * HTC_CTRL_RSVD_SVC could share the same pipe as the
1056 * WMI services. So, if another CE is needed, change
1057 * this to *ul_pipe = 3, which frees up CE 0.
1064 case ATH10K_HTC_SVC_ID_WMI_DATA_BK
:
1065 case ATH10K_HTC_SVC_ID_WMI_DATA_BE
:
1066 case ATH10K_HTC_SVC_ID_WMI_DATA_VI
:
1067 case ATH10K_HTC_SVC_ID_WMI_DATA_VO
:
1069 case ATH10K_HTC_SVC_ID_WMI_CONTROL
:
1075 /* pipe 6 reserved */
1076 /* pipe 7 reserved */
1083 (host_ce_config_wlan
[*ul_pipe
].flags
& CE_ATTR_DIS_INTR
) != 0;
1088 static void ath10k_pci_hif_get_default_pipe(struct ath10k
*ar
,
1089 u8
*ul_pipe
, u8
*dl_pipe
)
1091 int ul_is_polled
, dl_is_polled
;
1093 (void)ath10k_pci_hif_map_service_to_pipe(ar
,
1094 ATH10K_HTC_SVC_ID_RSVD_CTRL
,
1101 static int ath10k_pci_post_rx_pipe(struct ath10k_pci_pipe
*pipe_info
,
1104 struct ath10k
*ar
= pipe_info
->hif_ce_state
;
1105 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
1106 struct ath10k_ce_pipe
*ce_state
= pipe_info
->ce_hdl
;
1107 struct sk_buff
*skb
;
1111 if (pipe_info
->buf_sz
== 0)
1114 for (i
= 0; i
< num
; i
++) {
1115 skb
= dev_alloc_skb(pipe_info
->buf_sz
);
1117 ath10k_warn("failed to allocate skbuff for pipe %d\n",
1123 WARN_ONCE((unsigned long)skb
->data
& 3, "unaligned skb");
1125 ce_data
= dma_map_single(ar
->dev
, skb
->data
,
1126 skb
->len
+ skb_tailroom(skb
),
1129 if (unlikely(dma_mapping_error(ar
->dev
, ce_data
))) {
1130 ath10k_warn("failed to DMA map sk_buff\n");
1131 dev_kfree_skb_any(skb
);
1136 ATH10K_SKB_CB(skb
)->paddr
= ce_data
;
1138 pci_dma_sync_single_for_device(ar_pci
->pdev
, ce_data
,
1140 PCI_DMA_FROMDEVICE
);
1142 ret
= ath10k_ce_recv_buf_enqueue(ce_state
, (void *)skb
,
1145 ath10k_warn("failed to enqueue to pipe %d: %d\n",
1154 ath10k_pci_rx_pipe_cleanup(pipe_info
);
1158 static int ath10k_pci_post_rx(struct ath10k
*ar
)
1160 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
1161 struct ath10k_pci_pipe
*pipe_info
;
1162 const struct ce_attr
*attr
;
1163 int pipe_num
, ret
= 0;
1165 for (pipe_num
= 0; pipe_num
< CE_COUNT
; pipe_num
++) {
1166 pipe_info
= &ar_pci
->pipe_info
[pipe_num
];
1167 attr
= &host_ce_config_wlan
[pipe_num
];
1169 if (attr
->dest_nentries
== 0)
1172 ret
= ath10k_pci_post_rx_pipe(pipe_info
,
1173 attr
->dest_nentries
- 1);
1175 ath10k_warn("failed to post RX buffer for pipe %d: %d\n",
1178 for (; pipe_num
>= 0; pipe_num
--) {
1179 pipe_info
= &ar_pci
->pipe_info
[pipe_num
];
1180 ath10k_pci_rx_pipe_cleanup(pipe_info
);
1189 static int ath10k_pci_hif_start(struct ath10k
*ar
)
1191 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
1194 ret
= ath10k_pci_start_ce(ar
);
1196 ath10k_warn("failed to start CE: %d\n", ret
);
1200 /* Post buffers once to start things off. */
1201 ret
= ath10k_pci_post_rx(ar
);
1203 ath10k_warn("failed to post RX buffers for all pipes: %d\n",
1208 ar_pci
->started
= 1;
1212 static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe
*pipe_info
)
1215 struct ath10k_pci
*ar_pci
;
1216 struct ath10k_ce_pipe
*ce_hdl
;
1218 struct sk_buff
*netbuf
;
1221 buf_sz
= pipe_info
->buf_sz
;
1223 /* Unused Copy Engine */
1227 ar
= pipe_info
->hif_ce_state
;
1228 ar_pci
= ath10k_pci_priv(ar
);
1230 if (!ar_pci
->started
)
1233 ce_hdl
= pipe_info
->ce_hdl
;
1235 while (ath10k_ce_revoke_recv_next(ce_hdl
, (void **)&netbuf
,
1237 dma_unmap_single(ar
->dev
, ATH10K_SKB_CB(netbuf
)->paddr
,
1238 netbuf
->len
+ skb_tailroom(netbuf
),
1240 dev_kfree_skb_any(netbuf
);
1244 static void ath10k_pci_tx_pipe_cleanup(struct ath10k_pci_pipe
*pipe_info
)
1247 struct ath10k_pci
*ar_pci
;
1248 struct ath10k_ce_pipe
*ce_hdl
;
1249 struct sk_buff
*netbuf
;
1251 unsigned int nbytes
;
1255 buf_sz
= pipe_info
->buf_sz
;
1257 /* Unused Copy Engine */
1261 ar
= pipe_info
->hif_ce_state
;
1262 ar_pci
= ath10k_pci_priv(ar
);
1264 if (!ar_pci
->started
)
1267 ce_hdl
= pipe_info
->ce_hdl
;
1269 while (ath10k_ce_cancel_send_next(ce_hdl
, (void **)&netbuf
,
1270 &ce_data
, &nbytes
, &id
) == 0) {
1272 * Indicate the completion to higer layer to free
1277 ath10k_warn("invalid sk_buff on CE %d - NULL pointer. firmware crashed?\n",
1282 ATH10K_SKB_CB(netbuf
)->is_aborted
= true;
1283 ar_pci
->msg_callbacks_current
.tx_completion(ar
,
1290 * Cleanup residual buffers for device shutdown:
1291 * buffers that were enqueued for receive
1292 * buffers that were to be sent
1293 * Note: Buffers that had completed but which were
1294 * not yet processed are on a completion queue. They
1295 * are handled when the completion thread shuts down.
1297 static void ath10k_pci_buffer_cleanup(struct ath10k
*ar
)
1299 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
1302 for (pipe_num
= 0; pipe_num
< CE_COUNT
; pipe_num
++) {
1303 struct ath10k_pci_pipe
*pipe_info
;
1305 pipe_info
= &ar_pci
->pipe_info
[pipe_num
];
1306 ath10k_pci_rx_pipe_cleanup(pipe_info
);
1307 ath10k_pci_tx_pipe_cleanup(pipe_info
);
1311 static void ath10k_pci_ce_deinit(struct ath10k
*ar
)
1313 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
1314 struct ath10k_pci_pipe
*pipe_info
;
1317 for (pipe_num
= 0; pipe_num
< CE_COUNT
; pipe_num
++) {
1318 pipe_info
= &ar_pci
->pipe_info
[pipe_num
];
1319 if (pipe_info
->ce_hdl
) {
1320 ath10k_ce_deinit(pipe_info
->ce_hdl
);
1321 pipe_info
->ce_hdl
= NULL
;
1322 pipe_info
->buf_sz
= 0;
1327 static void ath10k_pci_disable_irqs(struct ath10k
*ar
)
1329 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
1332 for (i
= 0; i
< max(1, ar_pci
->num_msi_intrs
); i
++)
1333 disable_irq(ar_pci
->pdev
->irq
+ i
);
1336 static void ath10k_pci_hif_stop(struct ath10k
*ar
)
1338 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
1340 ath10k_dbg(ATH10K_DBG_PCI
, "%s\n", __func__
);
1342 /* Irqs are never explicitly re-enabled. They are implicitly re-enabled
1343 * by ath10k_pci_start_intr(). */
1344 ath10k_pci_disable_irqs(ar
);
1346 ath10k_pci_stop_ce(ar
);
1348 /* At this point, asynchronous threads are stopped, the target should
1349 * not DMA nor interrupt. We process the leftovers and then free
1350 * everything else up. */
1352 ath10k_pci_process_ce(ar
);
1353 ath10k_pci_cleanup_ce(ar
);
1354 ath10k_pci_buffer_cleanup(ar
);
1356 /* Make the sure the device won't access any structures on the host by
1357 * resetting it. The device was fed with PCI CE ringbuffer
1358 * configuration during init. If ringbuffers are freed and the device
1359 * were to access them this could lead to memory corruption on the
1361 ath10k_pci_device_reset(ar
);
1363 ar_pci
->started
= 0;
1366 static int ath10k_pci_hif_exchange_bmi_msg(struct ath10k
*ar
,
1367 void *req
, u32 req_len
,
1368 void *resp
, u32
*resp_len
)
1370 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
1371 struct ath10k_pci_pipe
*pci_tx
= &ar_pci
->pipe_info
[BMI_CE_NUM_TO_TARG
];
1372 struct ath10k_pci_pipe
*pci_rx
= &ar_pci
->pipe_info
[BMI_CE_NUM_TO_HOST
];
1373 struct ath10k_ce_pipe
*ce_tx
= pci_tx
->ce_hdl
;
1374 struct ath10k_ce_pipe
*ce_rx
= pci_rx
->ce_hdl
;
1375 dma_addr_t req_paddr
= 0;
1376 dma_addr_t resp_paddr
= 0;
1377 struct bmi_xfer xfer
= {};
1378 void *treq
, *tresp
= NULL
;
1381 if (resp
&& !resp_len
)
1384 if (resp
&& resp_len
&& *resp_len
== 0)
1387 treq
= kmemdup(req
, req_len
, GFP_KERNEL
);
1391 req_paddr
= dma_map_single(ar
->dev
, treq
, req_len
, DMA_TO_DEVICE
);
1392 ret
= dma_mapping_error(ar
->dev
, req_paddr
);
1396 if (resp
&& resp_len
) {
1397 tresp
= kzalloc(*resp_len
, GFP_KERNEL
);
1403 resp_paddr
= dma_map_single(ar
->dev
, tresp
, *resp_len
,
1405 ret
= dma_mapping_error(ar
->dev
, resp_paddr
);
1409 xfer
.wait_for_resp
= true;
1412 ath10k_ce_recv_buf_enqueue(ce_rx
, &xfer
, resp_paddr
);
1415 init_completion(&xfer
.done
);
1417 ret
= ath10k_ce_send(ce_tx
, &xfer
, req_paddr
, req_len
, -1, 0);
1421 ret
= wait_for_completion_timeout(&xfer
.done
,
1422 BMI_COMMUNICATION_TIMEOUT_HZ
);
1425 unsigned int unused_nbytes
;
1426 unsigned int unused_id
;
1429 ath10k_ce_cancel_send_next(ce_tx
, NULL
, &unused_buffer
,
1430 &unused_nbytes
, &unused_id
);
1432 /* non-zero means we did not time out */
1440 ath10k_ce_revoke_recv_next(ce_rx
, NULL
, &unused_buffer
);
1441 dma_unmap_single(ar
->dev
, resp_paddr
,
1442 *resp_len
, DMA_FROM_DEVICE
);
1445 dma_unmap_single(ar
->dev
, req_paddr
, req_len
, DMA_TO_DEVICE
);
1447 if (ret
== 0 && resp_len
) {
1448 *resp_len
= min(*resp_len
, xfer
.resp_len
);
1449 memcpy(resp
, tresp
, xfer
.resp_len
);
1458 static void ath10k_pci_bmi_send_done(struct ath10k_ce_pipe
*ce_state
)
1460 struct bmi_xfer
*xfer
;
1462 unsigned int nbytes
;
1463 unsigned int transfer_id
;
1465 if (ath10k_ce_completed_send_next(ce_state
, (void **)&xfer
, &ce_data
,
1466 &nbytes
, &transfer_id
))
1469 if (xfer
->wait_for_resp
)
1472 complete(&xfer
->done
);
1475 static void ath10k_pci_bmi_recv_data(struct ath10k_ce_pipe
*ce_state
)
1477 struct bmi_xfer
*xfer
;
1479 unsigned int nbytes
;
1480 unsigned int transfer_id
;
1483 if (ath10k_ce_completed_recv_next(ce_state
, (void **)&xfer
, &ce_data
,
1484 &nbytes
, &transfer_id
, &flags
))
1487 if (!xfer
->wait_for_resp
) {
1488 ath10k_warn("unexpected: BMI data received; ignoring\n");
1492 xfer
->resp_len
= nbytes
;
1493 complete(&xfer
->done
);
1497 * Map from service/endpoint to Copy Engine.
1498 * This table is derived from the CE_PCI TABLE, above.
1499 * It is passed to the Target at startup for use by firmware.
1501 static const struct service_to_pipe target_service_to_ce_map_wlan
[] = {
1503 ATH10K_HTC_SVC_ID_WMI_DATA_VO
,
1504 PIPEDIR_OUT
, /* out = UL = host -> target */
1508 ATH10K_HTC_SVC_ID_WMI_DATA_VO
,
1509 PIPEDIR_IN
, /* in = DL = target -> host */
1513 ATH10K_HTC_SVC_ID_WMI_DATA_BK
,
1514 PIPEDIR_OUT
, /* out = UL = host -> target */
1518 ATH10K_HTC_SVC_ID_WMI_DATA_BK
,
1519 PIPEDIR_IN
, /* in = DL = target -> host */
1523 ATH10K_HTC_SVC_ID_WMI_DATA_BE
,
1524 PIPEDIR_OUT
, /* out = UL = host -> target */
1528 ATH10K_HTC_SVC_ID_WMI_DATA_BE
,
1529 PIPEDIR_IN
, /* in = DL = target -> host */
1533 ATH10K_HTC_SVC_ID_WMI_DATA_VI
,
1534 PIPEDIR_OUT
, /* out = UL = host -> target */
1538 ATH10K_HTC_SVC_ID_WMI_DATA_VI
,
1539 PIPEDIR_IN
, /* in = DL = target -> host */
1543 ATH10K_HTC_SVC_ID_WMI_CONTROL
,
1544 PIPEDIR_OUT
, /* out = UL = host -> target */
1548 ATH10K_HTC_SVC_ID_WMI_CONTROL
,
1549 PIPEDIR_IN
, /* in = DL = target -> host */
1553 ATH10K_HTC_SVC_ID_RSVD_CTRL
,
1554 PIPEDIR_OUT
, /* out = UL = host -> target */
1555 0, /* could be moved to 3 (share with WMI) */
1558 ATH10K_HTC_SVC_ID_RSVD_CTRL
,
1559 PIPEDIR_IN
, /* in = DL = target -> host */
1563 ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS
, /* not currently used */
1564 PIPEDIR_OUT
, /* out = UL = host -> target */
1568 ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS
, /* not currently used */
1569 PIPEDIR_IN
, /* in = DL = target -> host */
1573 ATH10K_HTC_SVC_ID_HTT_DATA_MSG
,
1574 PIPEDIR_OUT
, /* out = UL = host -> target */
1578 ATH10K_HTC_SVC_ID_HTT_DATA_MSG
,
1579 PIPEDIR_IN
, /* in = DL = target -> host */
1583 /* (Additions here) */
1585 { /* Must be last */
1593 * Send an interrupt to the device to wake up the Target CPU
1594 * so it has an opportunity to notice any changed state.
1596 static int ath10k_pci_wake_target_cpu(struct ath10k
*ar
)
1601 ret
= ath10k_pci_diag_read_access(ar
, SOC_CORE_BASE_ADDRESS
|
1605 ath10k_warn("failed to read core_ctrl: %d\n", ret
);
1609 /* A_INUM_FIRMWARE interrupt to Target CPU */
1610 core_ctrl
|= CORE_CTRL_CPU_INTR_MASK
;
1612 ret
= ath10k_pci_diag_write_access(ar
, SOC_CORE_BASE_ADDRESS
|
1616 ath10k_warn("failed to set target CPU interrupt mask: %d\n",
1624 static int ath10k_pci_init_config(struct ath10k
*ar
)
1626 u32 interconnect_targ_addr
;
1627 u32 pcie_state_targ_addr
= 0;
1628 u32 pipe_cfg_targ_addr
= 0;
1629 u32 svc_to_pipe_map
= 0;
1630 u32 pcie_config_flags
= 0;
1632 u32 ealloc_targ_addr
;
1634 u32 flag2_targ_addr
;
1637 /* Download to Target the CE Config and the service-to-CE map */
1638 interconnect_targ_addr
=
1639 host_interest_item_address(HI_ITEM(hi_interconnect_state
));
1641 /* Supply Target-side CE configuration */
1642 ret
= ath10k_pci_diag_read_access(ar
, interconnect_targ_addr
,
1643 &pcie_state_targ_addr
);
1645 ath10k_err("Failed to get pcie state addr: %d\n", ret
);
1649 if (pcie_state_targ_addr
== 0) {
1651 ath10k_err("Invalid pcie state addr\n");
1655 ret
= ath10k_pci_diag_read_access(ar
, pcie_state_targ_addr
+
1656 offsetof(struct pcie_state
,
1658 &pipe_cfg_targ_addr
);
1660 ath10k_err("Failed to get pipe cfg addr: %d\n", ret
);
1664 if (pipe_cfg_targ_addr
== 0) {
1666 ath10k_err("Invalid pipe cfg addr\n");
1670 ret
= ath10k_pci_diag_write_mem(ar
, pipe_cfg_targ_addr
,
1671 target_ce_config_wlan
,
1672 sizeof(target_ce_config_wlan
));
1675 ath10k_err("Failed to write pipe cfg: %d\n", ret
);
1679 ret
= ath10k_pci_diag_read_access(ar
, pcie_state_targ_addr
+
1680 offsetof(struct pcie_state
,
1684 ath10k_err("Failed to get svc/pipe map: %d\n", ret
);
1688 if (svc_to_pipe_map
== 0) {
1690 ath10k_err("Invalid svc_to_pipe map\n");
1694 ret
= ath10k_pci_diag_write_mem(ar
, svc_to_pipe_map
,
1695 target_service_to_ce_map_wlan
,
1696 sizeof(target_service_to_ce_map_wlan
));
1698 ath10k_err("Failed to write svc/pipe map: %d\n", ret
);
1702 ret
= ath10k_pci_diag_read_access(ar
, pcie_state_targ_addr
+
1703 offsetof(struct pcie_state
,
1705 &pcie_config_flags
);
1707 ath10k_err("Failed to get pcie config_flags: %d\n", ret
);
1711 pcie_config_flags
&= ~PCIE_CONFIG_FLAG_ENABLE_L1
;
1713 ret
= ath10k_pci_diag_write_mem(ar
, pcie_state_targ_addr
+
1714 offsetof(struct pcie_state
, config_flags
),
1716 sizeof(pcie_config_flags
));
1718 ath10k_err("Failed to write pcie config_flags: %d\n", ret
);
1722 /* configure early allocation */
1723 ealloc_targ_addr
= host_interest_item_address(HI_ITEM(hi_early_alloc
));
1725 ret
= ath10k_pci_diag_read_access(ar
, ealloc_targ_addr
, &ealloc_value
);
1727 ath10k_err("Faile to get early alloc val: %d\n", ret
);
1731 /* first bank is switched to IRAM */
1732 ealloc_value
|= ((HI_EARLY_ALLOC_MAGIC
<< HI_EARLY_ALLOC_MAGIC_SHIFT
) &
1733 HI_EARLY_ALLOC_MAGIC_MASK
);
1734 ealloc_value
|= ((1 << HI_EARLY_ALLOC_IRAM_BANKS_SHIFT
) &
1735 HI_EARLY_ALLOC_IRAM_BANKS_MASK
);
1737 ret
= ath10k_pci_diag_write_access(ar
, ealloc_targ_addr
, ealloc_value
);
1739 ath10k_err("Failed to set early alloc val: %d\n", ret
);
1743 /* Tell Target to proceed with initialization */
1744 flag2_targ_addr
= host_interest_item_address(HI_ITEM(hi_option_flag2
));
1746 ret
= ath10k_pci_diag_read_access(ar
, flag2_targ_addr
, &flag2_value
);
1748 ath10k_err("Failed to get option val: %d\n", ret
);
1752 flag2_value
|= HI_OPTION_EARLY_CFG_DONE
;
1754 ret
= ath10k_pci_diag_write_access(ar
, flag2_targ_addr
, flag2_value
);
1756 ath10k_err("Failed to set option val: %d\n", ret
);
1765 static int ath10k_pci_ce_init(struct ath10k
*ar
)
1767 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
1768 struct ath10k_pci_pipe
*pipe_info
;
1769 const struct ce_attr
*attr
;
1772 for (pipe_num
= 0; pipe_num
< CE_COUNT
; pipe_num
++) {
1773 pipe_info
= &ar_pci
->pipe_info
[pipe_num
];
1774 pipe_info
->pipe_num
= pipe_num
;
1775 pipe_info
->hif_ce_state
= ar
;
1776 attr
= &host_ce_config_wlan
[pipe_num
];
1778 pipe_info
->ce_hdl
= ath10k_ce_init(ar
, pipe_num
, attr
);
1779 if (pipe_info
->ce_hdl
== NULL
) {
1780 ath10k_err("failed to initialize CE for pipe: %d\n",
1783 /* It is safe to call it here. It checks if ce_hdl is
1784 * valid for each pipe */
1785 ath10k_pci_ce_deinit(ar
);
1789 if (pipe_num
== CE_COUNT
- 1) {
1791 * Reserve the ultimate CE for
1792 * diagnostic Window support
1794 ar_pci
->ce_diag
= pipe_info
->ce_hdl
;
1798 pipe_info
->buf_sz
= (size_t) (attr
->src_sz_max
);
1804 static void ath10k_pci_fw_interrupt_handler(struct ath10k
*ar
)
1806 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
1807 u32 fw_indicator_address
, fw_indicator
;
1809 ath10k_pci_wake(ar
);
1811 fw_indicator_address
= ar_pci
->fw_indicator_address
;
1812 fw_indicator
= ath10k_pci_read32(ar
, fw_indicator_address
);
1814 if (fw_indicator
& FW_IND_EVENT_PENDING
) {
1815 /* ACK: clear Target-side pending event */
1816 ath10k_pci_write32(ar
, fw_indicator_address
,
1817 fw_indicator
& ~FW_IND_EVENT_PENDING
);
1819 if (ar_pci
->started
) {
1820 ath10k_pci_hif_dump_area(ar
);
1823 * Probable Target failure before we're prepared
1824 * to handle it. Generally unexpected.
1826 ath10k_warn("early firmware event indicated\n");
1830 ath10k_pci_sleep(ar
);
1833 static void ath10k_pci_start_bmi(struct ath10k
*ar
)
1835 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
1836 struct ath10k_pci_pipe
*pipe
;
1839 * Initially, establish CE completion handlers for use with BMI.
1840 * These are overwritten with generic handlers after we exit BMI phase.
1842 pipe
= &ar_pci
->pipe_info
[BMI_CE_NUM_TO_TARG
];
1843 ath10k_ce_send_cb_register(pipe
->ce_hdl
, ath10k_pci_bmi_send_done
, 0);
1845 pipe
= &ar_pci
->pipe_info
[BMI_CE_NUM_TO_HOST
];
1846 ath10k_ce_recv_cb_register(pipe
->ce_hdl
, ath10k_pci_bmi_recv_data
);
1848 ath10k_dbg(ATH10K_DBG_BOOT
, "boot start bmi\n");
1851 static int ath10k_pci_hif_power_up(struct ath10k
*ar
)
1853 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
1854 const char *irq_mode
;
1858 * Bring the target up cleanly.
1860 * The target may be in an undefined state with an AUX-powered Target
1861 * and a Host in WoW mode. If the Host crashes, loses power, or is
1862 * restarted (without unloading the driver) then the Target is left
1863 * (aux) powered and running. On a subsequent driver load, the Target
1864 * is in an unexpected state. We try to catch that here in order to
1865 * reset the Target and retry the probe.
1867 ret
= ath10k_pci_device_reset(ar
);
1869 ath10k_err("failed to reset target: %d\n", ret
);
1873 if (!test_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE
, ar_pci
->features
))
1874 /* Force AWAKE forever */
1875 ath10k_do_pci_wake(ar
);
1877 ret
= ath10k_pci_ce_init(ar
);
1879 ath10k_err("failed to initialize CE: %d\n", ret
);
1883 ret
= ath10k_ce_disable_interrupts(ar
);
1885 ath10k_err("failed to disable CE interrupts: %d\n", ret
);
1889 ret
= ath10k_pci_start_intr(ar
);
1891 ath10k_err("failed to start interrupt handling: %d\n", ret
);
1895 ret
= ath10k_pci_wait_for_target_init(ar
);
1897 ath10k_err("failed to wait for target to init: %d\n", ret
);
1901 ret
= ath10k_ce_enable_err_irq(ar
);
1903 ath10k_err("failed to enable CE error irq: %d\n", ret
);
1907 ret
= ath10k_pci_init_config(ar
);
1909 ath10k_err("failed to setup init config: %d\n", ret
);
1913 ret
= ath10k_pci_wake_target_cpu(ar
);
1915 ath10k_err("could not wake up target CPU: %d\n", ret
);
1919 ath10k_pci_start_bmi(ar
);
1921 if (ar_pci
->num_msi_intrs
> 1)
1923 else if (ar_pci
->num_msi_intrs
== 1)
1926 irq_mode
= "legacy";
1928 ath10k_info("pci irq %s\n", irq_mode
);
1933 ath10k_ce_disable_interrupts(ar
);
1934 ath10k_pci_stop_intr(ar
);
1935 ath10k_pci_kill_tasklet(ar
);
1936 ath10k_pci_device_reset(ar
);
1938 ath10k_pci_ce_deinit(ar
);
1940 if (!test_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE
, ar_pci
->features
))
1941 ath10k_do_pci_sleep(ar
);
1946 static void ath10k_pci_hif_power_down(struct ath10k
*ar
)
1948 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
1950 ath10k_pci_stop_intr(ar
);
1951 ath10k_pci_device_reset(ar
);
1953 ath10k_pci_ce_deinit(ar
);
1954 if (!test_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE
, ar_pci
->features
))
1955 ath10k_do_pci_sleep(ar
);
1960 #define ATH10K_PCI_PM_CONTROL 0x44
1962 static int ath10k_pci_hif_suspend(struct ath10k
*ar
)
1964 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
1965 struct pci_dev
*pdev
= ar_pci
->pdev
;
1968 pci_read_config_dword(pdev
, ATH10K_PCI_PM_CONTROL
, &val
);
1970 if ((val
& 0x000000ff) != 0x3) {
1971 pci_save_state(pdev
);
1972 pci_disable_device(pdev
);
1973 pci_write_config_dword(pdev
, ATH10K_PCI_PM_CONTROL
,
1974 (val
& 0xffffff00) | 0x03);
1980 static int ath10k_pci_hif_resume(struct ath10k
*ar
)
1982 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
1983 struct pci_dev
*pdev
= ar_pci
->pdev
;
1986 pci_read_config_dword(pdev
, ATH10K_PCI_PM_CONTROL
, &val
);
1988 if ((val
& 0x000000ff) != 0) {
1989 pci_restore_state(pdev
);
1990 pci_write_config_dword(pdev
, ATH10K_PCI_PM_CONTROL
,
1993 * Suspend/Resume resets the PCI configuration space,
1994 * so we have to re-disable the RETRY_TIMEOUT register (0x41)
1995 * to keep PCI Tx retries from interfering with C3 CPU state
1997 pci_read_config_dword(pdev
, 0x40, &val
);
1999 if ((val
& 0x0000ff00) != 0)
2000 pci_write_config_dword(pdev
, 0x40, val
& 0xffff00ff);
2007 static const struct ath10k_hif_ops ath10k_pci_hif_ops
= {
2008 .send_head
= ath10k_pci_hif_send_head
,
2009 .exchange_bmi_msg
= ath10k_pci_hif_exchange_bmi_msg
,
2010 .start
= ath10k_pci_hif_start
,
2011 .stop
= ath10k_pci_hif_stop
,
2012 .map_service_to_pipe
= ath10k_pci_hif_map_service_to_pipe
,
2013 .get_default_pipe
= ath10k_pci_hif_get_default_pipe
,
2014 .send_complete_check
= ath10k_pci_hif_send_complete_check
,
2015 .set_callbacks
= ath10k_pci_hif_set_callbacks
,
2016 .get_free_queue_number
= ath10k_pci_hif_get_free_queue_number
,
2017 .power_up
= ath10k_pci_hif_power_up
,
2018 .power_down
= ath10k_pci_hif_power_down
,
2020 .suspend
= ath10k_pci_hif_suspend
,
2021 .resume
= ath10k_pci_hif_resume
,
2025 static void ath10k_pci_ce_tasklet(unsigned long ptr
)
2027 struct ath10k_pci_pipe
*pipe
= (struct ath10k_pci_pipe
*)ptr
;
2028 struct ath10k_pci
*ar_pci
= pipe
->ar_pci
;
2030 ath10k_ce_per_engine_service(ar_pci
->ar
, pipe
->pipe_num
);
2033 static void ath10k_msi_err_tasklet(unsigned long data
)
2035 struct ath10k
*ar
= (struct ath10k
*)data
;
2037 ath10k_pci_fw_interrupt_handler(ar
);
2041 * Handler for a per-engine interrupt on a PARTICULAR CE.
2042 * This is used in cases where each CE has a private MSI interrupt.
2044 static irqreturn_t
ath10k_pci_per_engine_handler(int irq
, void *arg
)
2046 struct ath10k
*ar
= arg
;
2047 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2048 int ce_id
= irq
- ar_pci
->pdev
->irq
- MSI_ASSIGN_CE_INITIAL
;
2050 if (ce_id
< 0 || ce_id
>= ARRAY_SIZE(ar_pci
->pipe_info
)) {
2051 ath10k_warn("unexpected/invalid irq %d ce_id %d\n", irq
, ce_id
);
2056 * NOTE: We are able to derive ce_id from irq because we
2057 * use a one-to-one mapping for CE's 0..5.
2058 * CE's 6 & 7 do not use interrupts at all.
2060 * This mapping must be kept in sync with the mapping
2063 tasklet_schedule(&ar_pci
->pipe_info
[ce_id
].intr
);
2067 static irqreturn_t
ath10k_pci_msi_fw_handler(int irq
, void *arg
)
2069 struct ath10k
*ar
= arg
;
2070 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2072 tasklet_schedule(&ar_pci
->msi_fw_err
);
2077 * Top-level interrupt handler for all PCI interrupts from a Target.
2078 * When a block of MSI interrupts is allocated, this top-level handler
2079 * is not used; instead, we directly call the correct sub-handler.
2081 static irqreturn_t
ath10k_pci_interrupt_handler(int irq
, void *arg
)
2083 struct ath10k
*ar
= arg
;
2084 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2086 if (ar_pci
->num_msi_intrs
== 0) {
2088 * IMPORTANT: INTR_CLR regiser has to be set after
2089 * INTR_ENABLE is set to 0, otherwise interrupt can not be
2092 iowrite32(0, ar_pci
->mem
+
2093 (SOC_CORE_BASE_ADDRESS
|
2094 PCIE_INTR_ENABLE_ADDRESS
));
2095 iowrite32(PCIE_INTR_FIRMWARE_MASK
|
2096 PCIE_INTR_CE_MASK_ALL
,
2097 ar_pci
->mem
+ (SOC_CORE_BASE_ADDRESS
|
2098 PCIE_INTR_CLR_ADDRESS
));
2100 * IMPORTANT: this extra read transaction is required to
2101 * flush the posted write buffer.
2103 (void) ioread32(ar_pci
->mem
+
2104 (SOC_CORE_BASE_ADDRESS
|
2105 PCIE_INTR_ENABLE_ADDRESS
));
2108 tasklet_schedule(&ar_pci
->intr_tq
);
2113 static void ath10k_pci_tasklet(unsigned long data
)
2115 struct ath10k
*ar
= (struct ath10k
*)data
;
2116 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2118 ath10k_pci_fw_interrupt_handler(ar
); /* FIXME: Handle FW error */
2119 ath10k_ce_per_engine_service_any(ar
);
2121 if (ar_pci
->num_msi_intrs
== 0) {
2122 /* Enable Legacy PCI line interrupts */
2123 iowrite32(PCIE_INTR_FIRMWARE_MASK
|
2124 PCIE_INTR_CE_MASK_ALL
,
2125 ar_pci
->mem
+ (SOC_CORE_BASE_ADDRESS
|
2126 PCIE_INTR_ENABLE_ADDRESS
));
2128 * IMPORTANT: this extra read transaction is required to
2129 * flush the posted write buffer
2131 (void) ioread32(ar_pci
->mem
+
2132 (SOC_CORE_BASE_ADDRESS
|
2133 PCIE_INTR_ENABLE_ADDRESS
));
2137 static int ath10k_pci_start_intr_msix(struct ath10k
*ar
, int num
)
2139 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2143 ret
= pci_enable_msi_block(ar_pci
->pdev
, num
);
2147 ret
= request_irq(ar_pci
->pdev
->irq
+ MSI_ASSIGN_FW
,
2148 ath10k_pci_msi_fw_handler
,
2149 IRQF_SHARED
, "ath10k_pci", ar
);
2151 ath10k_warn("request_irq(%d) failed %d\n",
2152 ar_pci
->pdev
->irq
+ MSI_ASSIGN_FW
, ret
);
2154 pci_disable_msi(ar_pci
->pdev
);
2158 for (i
= MSI_ASSIGN_CE_INITIAL
; i
<= MSI_ASSIGN_CE_MAX
; i
++) {
2159 ret
= request_irq(ar_pci
->pdev
->irq
+ i
,
2160 ath10k_pci_per_engine_handler
,
2161 IRQF_SHARED
, "ath10k_pci", ar
);
2163 ath10k_warn("request_irq(%d) failed %d\n",
2164 ar_pci
->pdev
->irq
+ i
, ret
);
2166 for (i
--; i
>= MSI_ASSIGN_CE_INITIAL
; i
--)
2167 free_irq(ar_pci
->pdev
->irq
+ i
, ar
);
2169 free_irq(ar_pci
->pdev
->irq
+ MSI_ASSIGN_FW
, ar
);
2170 pci_disable_msi(ar_pci
->pdev
);
2175 ath10k_dbg(ATH10K_DBG_BOOT
,
2176 "MSI-X interrupt handling (%d intrs)\n", num
);
2180 static int ath10k_pci_start_intr_msi(struct ath10k
*ar
)
2182 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2185 ret
= pci_enable_msi(ar_pci
->pdev
);
2189 ret
= request_irq(ar_pci
->pdev
->irq
,
2190 ath10k_pci_interrupt_handler
,
2191 IRQF_SHARED
, "ath10k_pci", ar
);
2193 pci_disable_msi(ar_pci
->pdev
);
2197 ath10k_dbg(ATH10K_DBG_BOOT
, "MSI interrupt handling\n");
2201 static int ath10k_pci_start_intr_legacy(struct ath10k
*ar
)
2203 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2206 ret
= request_irq(ar_pci
->pdev
->irq
,
2207 ath10k_pci_interrupt_handler
,
2208 IRQF_SHARED
, "ath10k_pci", ar
);
2212 ret
= ath10k_pci_wake(ar
);
2214 free_irq(ar_pci
->pdev
->irq
, ar
);
2215 ath10k_err("failed to wake up target: %d\n", ret
);
2220 * A potential race occurs here: The CORE_BASE write
2221 * depends on target correctly decoding AXI address but
2222 * host won't know when target writes BAR to CORE_CTRL.
2223 * This write might get lost if target has NOT written BAR.
2224 * For now, fix the race by repeating the write in below
2225 * synchronization checking.
2227 iowrite32(PCIE_INTR_FIRMWARE_MASK
|
2228 PCIE_INTR_CE_MASK_ALL
,
2229 ar_pci
->mem
+ (SOC_CORE_BASE_ADDRESS
|
2230 PCIE_INTR_ENABLE_ADDRESS
));
2232 ath10k_pci_sleep(ar
);
2233 ath10k_dbg(ATH10K_DBG_BOOT
, "legacy interrupt handling\n");
2237 static int ath10k_pci_start_intr(struct ath10k
*ar
)
2239 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2240 int num
= MSI_NUM_REQUEST
;
2244 tasklet_init(&ar_pci
->intr_tq
, ath10k_pci_tasklet
, (unsigned long) ar
);
2245 tasklet_init(&ar_pci
->msi_fw_err
, ath10k_msi_err_tasklet
,
2246 (unsigned long) ar
);
2248 for (i
= 0; i
< CE_COUNT
; i
++) {
2249 ar_pci
->pipe_info
[i
].ar_pci
= ar_pci
;
2250 tasklet_init(&ar_pci
->pipe_info
[i
].intr
,
2251 ath10k_pci_ce_tasklet
,
2252 (unsigned long)&ar_pci
->pipe_info
[i
]);
2255 if (!test_bit(ATH10K_PCI_FEATURE_MSI_X
, ar_pci
->features
))
2259 ret
= ath10k_pci_start_intr_msix(ar
, num
);
2263 ath10k_dbg(ATH10K_DBG_BOOT
,
2264 "MSI-X didn't succeed (%d), trying MSI\n", ret
);
2269 ret
= ath10k_pci_start_intr_msi(ar
);
2273 ath10k_dbg(ATH10K_DBG_BOOT
,
2274 "MSI didn't succeed (%d), trying legacy INTR\n",
2279 ret
= ath10k_pci_start_intr_legacy(ar
);
2281 ath10k_warn("Failed to start legacy interrupts: %d\n", ret
);
2286 ar_pci
->num_msi_intrs
= num
;
2290 static void ath10k_pci_stop_intr(struct ath10k
*ar
)
2292 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2295 /* There's at least one interrupt irregardless whether its legacy INTR
2296 * or MSI or MSI-X */
2297 for (i
= 0; i
< max(1, ar_pci
->num_msi_intrs
); i
++)
2298 free_irq(ar_pci
->pdev
->irq
+ i
, ar
);
2300 if (ar_pci
->num_msi_intrs
> 0)
2301 pci_disable_msi(ar_pci
->pdev
);
2304 static int ath10k_pci_wait_for_target_init(struct ath10k
*ar
)
2306 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2307 int wait_limit
= 300; /* 3 sec */
2310 ret
= ath10k_pci_wake(ar
);
2312 ath10k_err("failed to wake up target: %d\n", ret
);
2316 while (wait_limit
-- &&
2317 !(ioread32(ar_pci
->mem
+ FW_INDICATOR_ADDRESS
) &
2318 FW_IND_INITIALIZED
)) {
2319 if (ar_pci
->num_msi_intrs
== 0)
2320 /* Fix potential race by repeating CORE_BASE writes */
2321 iowrite32(PCIE_INTR_FIRMWARE_MASK
|
2322 PCIE_INTR_CE_MASK_ALL
,
2323 ar_pci
->mem
+ (SOC_CORE_BASE_ADDRESS
|
2324 PCIE_INTR_ENABLE_ADDRESS
));
2328 if (wait_limit
< 0) {
2329 ath10k_err("target stalled\n");
2335 ath10k_pci_sleep(ar
);
2339 static int ath10k_pci_device_reset(struct ath10k
*ar
)
2344 ret
= ath10k_do_pci_wake(ar
);
2346 ath10k_err("failed to wake up target: %d\n",
2351 /* Put Target, including PCIe, into RESET. */
2352 val
= ath10k_pci_reg_read32(ar
, SOC_GLOBAL_RESET_ADDRESS
);
2354 ath10k_pci_reg_write32(ar
, SOC_GLOBAL_RESET_ADDRESS
, val
);
2356 for (i
= 0; i
< ATH_PCI_RESET_WAIT_MAX
; i
++) {
2357 if (ath10k_pci_reg_read32(ar
, RTC_STATE_ADDRESS
) &
2358 RTC_STATE_COLD_RESET_MASK
)
2363 /* Pull Target, including PCIe, out of RESET. */
2365 ath10k_pci_reg_write32(ar
, SOC_GLOBAL_RESET_ADDRESS
, val
);
2367 for (i
= 0; i
< ATH_PCI_RESET_WAIT_MAX
; i
++) {
2368 if (!(ath10k_pci_reg_read32(ar
, RTC_STATE_ADDRESS
) &
2369 RTC_STATE_COLD_RESET_MASK
))
2374 ath10k_do_pci_sleep(ar
);
2378 static void ath10k_pci_dump_features(struct ath10k_pci
*ar_pci
)
2382 for (i
= 0; i
< ATH10K_PCI_FEATURE_COUNT
; i
++) {
2383 if (!test_bit(i
, ar_pci
->features
))
2387 case ATH10K_PCI_FEATURE_MSI_X
:
2388 ath10k_dbg(ATH10K_DBG_BOOT
, "device supports MSI-X\n");
2390 case ATH10K_PCI_FEATURE_SOC_POWER_SAVE
:
2391 ath10k_dbg(ATH10K_DBG_BOOT
, "QCA98XX SoC power save enabled\n");
2397 static int ath10k_pci_probe(struct pci_dev
*pdev
,
2398 const struct pci_device_id
*pci_dev
)
2403 struct ath10k_pci
*ar_pci
;
2404 u32 lcr_val
, chip_id
;
2406 ath10k_dbg(ATH10K_DBG_PCI
, "%s\n", __func__
);
2408 ar_pci
= kzalloc(sizeof(*ar_pci
), GFP_KERNEL
);
2412 ar_pci
->pdev
= pdev
;
2413 ar_pci
->dev
= &pdev
->dev
;
2415 switch (pci_dev
->device
) {
2416 case QCA988X_2_0_DEVICE_ID
:
2417 set_bit(ATH10K_PCI_FEATURE_MSI_X
, ar_pci
->features
);
2421 ath10k_err("Unkown device ID: %d\n", pci_dev
->device
);
2425 if (ath10k_target_ps
)
2426 set_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE
, ar_pci
->features
);
2428 ath10k_pci_dump_features(ar_pci
);
2430 ar
= ath10k_core_create(ar_pci
, ar_pci
->dev
, &ath10k_pci_hif_ops
);
2432 ath10k_err("failed to create driver core\n");
2438 ar_pci
->fw_indicator_address
= FW_INDICATOR_ADDRESS
;
2439 atomic_set(&ar_pci
->keep_awake_count
, 0);
2441 pci_set_drvdata(pdev
, ar
);
2444 * Without any knowledge of the Host, the Target may have been reset or
2445 * power cycled and its Config Space may no longer reflect the PCI
2446 * address space that was assigned earlier by the PCI infrastructure.
2449 ret
= pci_assign_resource(pdev
, BAR_NUM
);
2451 ath10k_err("failed to assign PCI space: %d\n", ret
);
2455 ret
= pci_enable_device(pdev
);
2457 ath10k_err("failed to enable PCI device: %d\n", ret
);
2461 /* Request MMIO resources */
2462 ret
= pci_request_region(pdev
, BAR_NUM
, "ath");
2464 ath10k_err("failed to request MMIO region: %d\n", ret
);
2469 * Target structures have a limit of 32 bit DMA pointers.
2470 * DMA pointers can be wider than 32 bits by default on some systems.
2472 ret
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
2474 ath10k_err("failed to set DMA mask to 32-bit: %d\n", ret
);
2478 ret
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(32));
2480 ath10k_err("failed to set consistent DMA mask to 32-bit\n");
2484 /* Set bus master bit in PCI_COMMAND to enable DMA */
2485 pci_set_master(pdev
);
2488 * Temporary FIX: disable ASPM
2489 * Will be removed after the OTP is programmed
2491 pci_read_config_dword(pdev
, 0x80, &lcr_val
);
2492 pci_write_config_dword(pdev
, 0x80, (lcr_val
& 0xffffff00));
2494 /* Arrange for access to Target SoC registers. */
2495 mem
= pci_iomap(pdev
, BAR_NUM
, 0);
2497 ath10k_err("failed to perform IOMAP for BAR%d\n", BAR_NUM
);
2504 spin_lock_init(&ar_pci
->ce_lock
);
2506 ret
= ath10k_do_pci_wake(ar
);
2508 ath10k_err("Failed to get chip id: %d\n", ret
);
2512 chip_id
= ath10k_pci_soc_read32(ar
, SOC_CHIP_ID_ADDRESS
);
2514 ath10k_do_pci_sleep(ar
);
2516 ath10k_dbg(ATH10K_DBG_BOOT
, "boot pci_mem 0x%p\n", ar_pci
->mem
);
2518 ret
= ath10k_core_register(ar
, chip_id
);
2520 ath10k_err("failed to register driver core: %d\n", ret
);
2527 pci_iounmap(pdev
, mem
);
2529 pci_clear_master(pdev
);
2531 pci_release_region(pdev
, BAR_NUM
);
2533 pci_disable_device(pdev
);
2535 ath10k_core_destroy(ar
);
2537 /* call HIF PCI free here */
2543 static void ath10k_pci_remove(struct pci_dev
*pdev
)
2545 struct ath10k
*ar
= pci_get_drvdata(pdev
);
2546 struct ath10k_pci
*ar_pci
;
2548 ath10k_dbg(ATH10K_DBG_PCI
, "%s\n", __func__
);
2553 ar_pci
= ath10k_pci_priv(ar
);
2558 tasklet_kill(&ar_pci
->msi_fw_err
);
2560 ath10k_core_unregister(ar
);
2562 pci_iounmap(pdev
, ar_pci
->mem
);
2563 pci_release_region(pdev
, BAR_NUM
);
2564 pci_clear_master(pdev
);
2565 pci_disable_device(pdev
);
2567 ath10k_core_destroy(ar
);
2571 MODULE_DEVICE_TABLE(pci
, ath10k_pci_id_table
);
2573 static struct pci_driver ath10k_pci_driver
= {
2574 .name
= "ath10k_pci",
2575 .id_table
= ath10k_pci_id_table
,
2576 .probe
= ath10k_pci_probe
,
2577 .remove
= ath10k_pci_remove
,
2580 static int __init
ath10k_pci_init(void)
2584 ret
= pci_register_driver(&ath10k_pci_driver
);
2586 ath10k_err("failed to register PCI driver: %d\n", ret
);
2590 module_init(ath10k_pci_init
);
2592 static void __exit
ath10k_pci_exit(void)
2594 pci_unregister_driver(&ath10k_pci_driver
);
2597 module_exit(ath10k_pci_exit
);
2599 MODULE_AUTHOR("Qualcomm Atheros");
2600 MODULE_DESCRIPTION("Driver support for Atheros QCA988X PCIe devices");
2601 MODULE_LICENSE("Dual BSD/GPL");
2602 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR
"/" QCA988X_HW_2_0_FW_FILE
);
2603 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR
"/" QCA988X_HW_2_0_OTP_FILE
);
2604 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR
"/" QCA988X_HW_2_0_BOARD_DATA_FILE
);