drivers/net/wireless/ath/ath10k/pci.h

   1 /*
   2  * Copyright (c) 2005-2011 Atheros Communications Inc.
   3  * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
   4  *
   5  * Permission to use, copy, modify, and/or distribute this software for any
   6  * purpose with or without fee is hereby granted, provided that the above
   7  * copyright notice and this permission notice appear in all copies.
   8  *
   9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16  */
  17
  18 #ifndef _PCI_H_
  19 #define _PCI_H_
  20
  21 #include <linux/interrupt.h>
  22
  23 #include "hw.h"
  24 #include "ce.h"
  25 #include "ahb.h"
  26
  27 /*
  28  * maximum number of bytes that can be handled atomically by DiagRead/DiagWrite
  29  */
  30 #define DIAG_TRANSFER_LIMIT 2048
  31
  32 /*
  33  * maximum number of bytes that can be
  34  * handled atomically by DiagRead/DiagWrite
  35  */
  36 #define DIAG_TRANSFER_LIMIT 2048
  37
  38 struct bmi_xfer {
  39         bool tx_done;
  40         bool rx_done;
  41         bool wait_for_resp;
  42         u32 resp_len;
  43 };
  44
  45 /*
  46  * PCI-specific Target state
  47  *
  48  * NOTE: Structure is shared between Host software and Target firmware!
  49  *
  50  * Much of this may be of interest to the Host so
  51  * HOST_INTEREST->hi_interconnect_state points here
  52  * (and all members are 32-bit quantities in order to
  53  * facilitate Host access). In particular, Host software is
  54  * required to initialize pipe_cfg_addr and svc_to_pipe_map.
  55  */
  56 struct pcie_state {
  57         /* Pipe configuration Target address */
  58         /* NB: ce_pipe_config[CE_COUNT] */
  59         u32 pipe_cfg_addr;
  60
  61         /* Service to pipe map Target address */
  62         /* NB: service_to_pipe[PIPE_TO_CE_MAP_CN] */
  63         u32 svc_to_pipe_map;
  64
  65         /* number of MSI interrupts requested */
  66         u32 msi_requested;
  67
  68         /* number of MSI interrupts granted */
  69         u32 msi_granted;
  70
  71         /* Message Signalled Interrupt address */
  72         u32 msi_addr;
  73
  74         /* Base data */
  75         u32 msi_data;
  76
  77         /*
  78          * Data for firmware interrupt;
  79          * MSI data for other interrupts are
  80          * in various SoC registers
  81          */
  82         u32 msi_fw_intr_data;
  83
  84         /* PCIE_PWR_METHOD_* */
  85         u32 power_mgmt_method;
  86
  87         /* PCIE_CONFIG_FLAG_* */
  88         u32 config_flags;
  89 };
  90
  91 /* PCIE_CONFIG_FLAG definitions */
  92 #define PCIE_CONFIG_FLAG_ENABLE_L1  0x0000001
  93
  94 /* Host software's Copy Engine configuration. */
  95 #define CE_ATTR_FLAGS 0
  96
  97 /*
  98  * Configuration information for a Copy Engine pipe.
  99  * Passed from Host to Target during startup (one per CE).
 100  *
 101  * NOTE: Structure is shared between Host software and Target firmware!
 102  */
 103 struct ce_pipe_config {
 104         __le32 pipenum;
 105         __le32 pipedir;
 106         __le32 nentries;
 107         __le32 nbytes_max;
 108         __le32 flags;
 109         __le32 reserved;
 110 };
 111
 112 /*
 113  * Directions for interconnect pipe configuration.
 114  * These definitions may be used during configuration and are shared
 115  * between Host and Target.
 116  *
 117  * Pipe Directions are relative to the Host, so PIPEDIR_IN means
 118  * "coming IN over air through Target to Host" as with a WiFi Rx operation.
 119  * Conversely, PIPEDIR_OUT means "going OUT from Host through Target over air"
 120  * as with a WiFi Tx operation. This is somewhat awkward for the "middle-man"
 121  * Target since things that are "PIPEDIR_OUT" are coming IN to the Target
 122  * over the interconnect.
 123  */
 124 #define PIPEDIR_NONE    0
 125 #define PIPEDIR_IN      1  /* Target-->Host, WiFi Rx direction */
 126 #define PIPEDIR_OUT     2  /* Host->Target, WiFi Tx direction */
 127 #define PIPEDIR_INOUT   3  /* bidirectional */
 128
 129 /* Establish a mapping between a service/direction and a pipe. */
 130 struct service_to_pipe {
 131         __le32 service_id;
 132         __le32 pipedir;
 133         __le32 pipenum;
 134 };
 135
 136 /* Per-pipe state. */
 137 struct ath10k_pci_pipe {
 138         /* Handle of underlying Copy Engine */
 139         struct ath10k_ce_pipe *ce_hdl;
 140
 141         /* Our pipe number; facilitiates use of pipe_info ptrs. */
 142         u8 pipe_num;
 143
 144         /* Convenience back pointer to hif_ce_state. */
 145         struct ath10k *hif_ce_state;
 146
 147         size_t buf_sz;
 148
 149         /* protects compl_free and num_send_allowed */
 150         spinlock_t pipe_lock;
 151 };
 152
 153 struct ath10k_pci_supp_chip {
 154         u32 dev_id;
 155         u32 rev_id;
 156 };
 157
 158 struct ath10k_bus_ops {
 159         u32 (*read32)(struct ath10k *ar, u32 offset);
 160         void (*write32)(struct ath10k *ar, u32 offset, u32 value);
 161         int (*get_num_banks)(struct ath10k *ar);
 162 };
 163
 164 enum ath10k_pci_irq_mode {
 165         ATH10K_PCI_IRQ_AUTO = 0,
 166         ATH10K_PCI_IRQ_LEGACY = 1,
 167         ATH10K_PCI_IRQ_MSI = 2,
 168 };
 169
 170 struct ath10k_pci {
 171         struct pci_dev *pdev;
 172         struct device *dev;
 173         struct ath10k *ar;
 174         void __iomem *mem;
 175         size_t mem_len;
 176
 177         /* Operating interrupt mode */
 178         enum ath10k_pci_irq_mode oper_irq_mode;
 179
 180         struct tasklet_struct intr_tq;
 181
 182         struct ath10k_pci_pipe pipe_info[CE_COUNT_MAX];
 183
 184         /* Copy Engine used for Diagnostic Accesses */
 185         struct ath10k_ce_pipe *ce_diag;
 186
 187         /* FIXME: document what this really protects */
 188         spinlock_t ce_lock;
 189
 190         /* Map CE id to ce_state */
 191         struct ath10k_ce_pipe ce_states[CE_COUNT_MAX];
 192         struct timer_list rx_post_retry;
 193
 194         /* Due to HW quirks it is recommended to disable ASPM during device
 195          * bootup. To do that the original PCI-E Link Control is stored before
 196          * device bootup is executed and re-programmed later.
 197          */
 198         u16 link_ctl;
 199
 200         /* Protects ps_awake and ps_wake_refcount */
 201         spinlock_t ps_lock;
 202
 203         /* The device has a special powersave-oriented register. When device is
 204          * considered asleep it drains less power and driver is forbidden from
 205          * accessing most MMIO registers. If host were to access them without
 206          * waking up the device might scribble over host memory or return
 207          * 0xdeadbeef readouts.
 208          */
 209         unsigned long ps_wake_refcount;
 210
 211         /* Waking up takes some time (up to 2ms in some cases) so it can be bad
 212          * for latency. To mitigate this the device isn't immediately allowed
 213          * to sleep after all references are undone - instead there's a grace
 214          * period after which the powersave register is updated unless some
 215          * activity to/from device happened in the meantime.
 216          *
 217          * Also see comments on ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC.
 218          */
 219         struct timer_list ps_timer;
 220
 221         /* MMIO registers are used to communicate with the device. With
 222          * intensive traffic accessing powersave register would be a bit
 223          * wasteful overhead and would needlessly stall CPU. It is far more
 224          * efficient to rely on a variable in RAM and update it only upon
 225          * powersave register state changes.
 226          */
 227         bool ps_awake;
 228
 229         /* pci power save, disable for QCA988X and QCA99X0.
 230          * Writing 'false' to this variable avoids frequent locking
 231          * on MMIO read/write.
 232          */
 233         bool pci_ps;
 234
 235         const struct ath10k_bus_ops *bus_ops;
 236
 237         /* Keep this entry in the last, memory for struct ath10k_ahb is
 238          * allocated (ahb support enabled case) in the continuation of
 239          * this struct.
 240          */
 241         struct ath10k_ahb ahb[0];
 242 };
 243
 244 static inline struct ath10k_pci *ath10k_pci_priv(struct ath10k *ar)
 245 {
 246         return (struct ath10k_pci *)ar->drv_priv;
 247 }
 248
 249 #define ATH10K_PCI_RX_POST_RETRY_MS 50
 250 #define ATH_PCI_RESET_WAIT_MAX 10 /* ms */
 251 #define PCIE_WAKE_TIMEOUT 30000 /* 30ms */
 252 #define PCIE_WAKE_LATE_US 10000 /* 10ms */
 253
 254 #define BAR_NUM 0
 255
 256 #define CDC_WAR_MAGIC_STR   0xceef0000
 257 #define CDC_WAR_DATA_CE     4
 258
 259 /* Wait up to this many Ms for a Diagnostic Access CE operation to complete */
 260 #define DIAG_ACCESS_CE_TIMEOUT_MS 10
 261
 262 void ath10k_pci_write32(struct ath10k *ar, u32 offset, u32 value);
 263 void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val);
 264 void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val);
 265
 266 u32 ath10k_pci_read32(struct ath10k *ar, u32 offset);
 267 u32 ath10k_pci_soc_read32(struct ath10k *ar, u32 addr);
 268 u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr);
 269
 270 int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id,
 271                          struct ath10k_hif_sg_item *items, int n_items);
 272 int ath10k_pci_hif_diag_read(struct ath10k *ar, u32 address, void *buf,
 273                              size_t buf_len);
 274 int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address,
 275                               const void *data, int nbytes);
 276 int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar, void *req, u32 req_len,
 277                                     void *resp, u32 *resp_len);
 278 int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar, u16 service_id,
 279                                        u8 *ul_pipe, u8 *dl_pipe);
 280 void ath10k_pci_hif_get_default_pipe(struct ath10k *ar, u8 *ul_pipe,
 281                                      u8 *dl_pipe);
 282 void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe,
 283                                         int force);
 284 u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe);
 285 void ath10k_pci_hif_power_down(struct ath10k *ar);
 286 int ath10k_pci_alloc_pipes(struct ath10k *ar);
 287 void ath10k_pci_free_pipes(struct ath10k *ar);
 288 void ath10k_pci_free_pipes(struct ath10k *ar);
 289 void ath10k_pci_rx_replenish_retry(unsigned long ptr);
 290 void ath10k_pci_ce_deinit(struct ath10k *ar);
 291 void ath10k_pci_init_irq_tasklets(struct ath10k *ar);
 292 void ath10k_pci_kill_tasklet(struct ath10k *ar);
 293 int ath10k_pci_init_pipes(struct ath10k *ar);
 294 int ath10k_pci_init_config(struct ath10k *ar);
 295 void ath10k_pci_rx_post(struct ath10k *ar);
 296 void ath10k_pci_flush(struct ath10k *ar);
 297 void ath10k_pci_enable_legacy_irq(struct ath10k *ar);
 298 bool ath10k_pci_irq_pending(struct ath10k *ar);
 299 void ath10k_pci_disable_and_clear_legacy_irq(struct ath10k *ar);
 300 int ath10k_pci_wait_for_target_init(struct ath10k *ar);
 301 int ath10k_pci_setup_resource(struct ath10k *ar);
 302 void ath10k_pci_release_resource(struct ath10k *ar);
 303
 304 /* QCA6174 is known to have Tx/Rx issues when SOC_WAKE register is poked too
 305  * frequently. To avoid this put SoC to sleep after a very conservative grace
 306  * period. Adjust with great care.
 307  */
 308 #define ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC 60
 309
 310 #endif /* _PCI_H_ */