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[deliverable/linux.git] / drivers / net / wireless / ath / ath5k / base.c
1 /*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
43 #include <linux/module.h>
44 #include <linux/delay.h>
45 #include <linux/hardirq.h>
46 #include <linux/if.h>
47 #include <linux/io.h>
48 #include <linux/netdevice.h>
49 #include <linux/cache.h>
50 #include <linux/pci.h>
51 #include <linux/ethtool.h>
52 #include <linux/uaccess.h>
53
54 #include <net/ieee80211_radiotap.h>
55
56 #include <asm/unaligned.h>
57
58 #include "base.h"
59 #include "reg.h"
60 #include "debug.h"
61
62 static u8 ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
63 static int modparam_nohwcrypt;
64 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
65 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
66
67 static int modparam_all_channels;
68 module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
69 MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
70
71
72 /******************\
73 * Internal defines *
74 \******************/
75
76 /* Module info */
77 MODULE_AUTHOR("Jiri Slaby");
78 MODULE_AUTHOR("Nick Kossifidis");
79 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
80 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
81 MODULE_LICENSE("Dual BSD/GPL");
82 MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
83
84
85 /* Known PCI ids */
86 static const struct pci_device_id ath5k_pci_id_table[] = {
87 { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
88 { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
89 { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
90 { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
91 { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
92 { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
93 { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
94 { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
95 { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
96 { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
98 { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
99 { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
101 { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
102 { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
103 { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* PCI-E cards */
104 { PCI_VDEVICE(ATHEROS, 0x001d), .driver_data = AR5K_AR5212 }, /* 2417 Nala */
105 { 0 }
106 };
107 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
108
109 /* Known SREVs */
110 static const struct ath5k_srev_name srev_names[] = {
111 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
112 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
113 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
114 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
115 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
116 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
117 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
118 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
119 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
120 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
121 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
122 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
123 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
124 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
125 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
126 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
127 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
128 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
129 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
130 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
131 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
132 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
133 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
134 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
135 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
136 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
137 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
138 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
139 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
140 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
141 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
142 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
143 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
144 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
145 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
146 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
147 };
148
149 static const struct ieee80211_rate ath5k_rates[] = {
150 { .bitrate = 10,
151 .hw_value = ATH5K_RATE_CODE_1M, },
152 { .bitrate = 20,
153 .hw_value = ATH5K_RATE_CODE_2M,
154 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
155 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
156 { .bitrate = 55,
157 .hw_value = ATH5K_RATE_CODE_5_5M,
158 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
159 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
160 { .bitrate = 110,
161 .hw_value = ATH5K_RATE_CODE_11M,
162 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
163 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
164 { .bitrate = 60,
165 .hw_value = ATH5K_RATE_CODE_6M,
166 .flags = 0 },
167 { .bitrate = 90,
168 .hw_value = ATH5K_RATE_CODE_9M,
169 .flags = 0 },
170 { .bitrate = 120,
171 .hw_value = ATH5K_RATE_CODE_12M,
172 .flags = 0 },
173 { .bitrate = 180,
174 .hw_value = ATH5K_RATE_CODE_18M,
175 .flags = 0 },
176 { .bitrate = 240,
177 .hw_value = ATH5K_RATE_CODE_24M,
178 .flags = 0 },
179 { .bitrate = 360,
180 .hw_value = ATH5K_RATE_CODE_36M,
181 .flags = 0 },
182 { .bitrate = 480,
183 .hw_value = ATH5K_RATE_CODE_48M,
184 .flags = 0 },
185 { .bitrate = 540,
186 .hw_value = ATH5K_RATE_CODE_54M,
187 .flags = 0 },
188 /* XR missing */
189 };
190
191 /*
192 * Prototypes - PCI stack related functions
193 */
194 static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
195 const struct pci_device_id *id);
196 static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
197 #ifdef CONFIG_PM
198 static int ath5k_pci_suspend(struct pci_dev *pdev,
199 pm_message_t state);
200 static int ath5k_pci_resume(struct pci_dev *pdev);
201 #else
202 #define ath5k_pci_suspend NULL
203 #define ath5k_pci_resume NULL
204 #endif /* CONFIG_PM */
205
206 static struct pci_driver ath5k_pci_driver = {
207 .name = KBUILD_MODNAME,
208 .id_table = ath5k_pci_id_table,
209 .probe = ath5k_pci_probe,
210 .remove = __devexit_p(ath5k_pci_remove),
211 .suspend = ath5k_pci_suspend,
212 .resume = ath5k_pci_resume,
213 };
214
215
216
217 /*
218 * Prototypes - MAC 802.11 stack related functions
219 */
220 static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
221 static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
222 struct ath5k_txq *txq);
223 static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan);
224 static int ath5k_reset_wake(struct ath5k_softc *sc);
225 static int ath5k_start(struct ieee80211_hw *hw);
226 static void ath5k_stop(struct ieee80211_hw *hw);
227 static int ath5k_add_interface(struct ieee80211_hw *hw,
228 struct ieee80211_if_init_conf *conf);
229 static void ath5k_remove_interface(struct ieee80211_hw *hw,
230 struct ieee80211_if_init_conf *conf);
231 static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
232 static void ath5k_configure_filter(struct ieee80211_hw *hw,
233 unsigned int changed_flags,
234 unsigned int *new_flags,
235 int mc_count, struct dev_mc_list *mclist);
236 static int ath5k_set_key(struct ieee80211_hw *hw,
237 enum set_key_cmd cmd,
238 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
239 struct ieee80211_key_conf *key);
240 static int ath5k_get_stats(struct ieee80211_hw *hw,
241 struct ieee80211_low_level_stats *stats);
242 static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
243 struct ieee80211_tx_queue_stats *stats);
244 static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
245 static void ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf);
246 static void ath5k_reset_tsf(struct ieee80211_hw *hw);
247 static int ath5k_beacon_update(struct ieee80211_hw *hw,
248 struct ieee80211_vif *vif);
249 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
250 struct ieee80211_vif *vif,
251 struct ieee80211_bss_conf *bss_conf,
252 u32 changes);
253 static void ath5k_sw_scan_start(struct ieee80211_hw *hw);
254 static void ath5k_sw_scan_complete(struct ieee80211_hw *hw);
255
256 static const struct ieee80211_ops ath5k_hw_ops = {
257 .tx = ath5k_tx,
258 .start = ath5k_start,
259 .stop = ath5k_stop,
260 .add_interface = ath5k_add_interface,
261 .remove_interface = ath5k_remove_interface,
262 .config = ath5k_config,
263 .configure_filter = ath5k_configure_filter,
264 .set_key = ath5k_set_key,
265 .get_stats = ath5k_get_stats,
266 .conf_tx = NULL,
267 .get_tx_stats = ath5k_get_tx_stats,
268 .get_tsf = ath5k_get_tsf,
269 .set_tsf = ath5k_set_tsf,
270 .reset_tsf = ath5k_reset_tsf,
271 .bss_info_changed = ath5k_bss_info_changed,
272 .sw_scan_start = ath5k_sw_scan_start,
273 .sw_scan_complete = ath5k_sw_scan_complete,
274 };
275
276 /*
277 * Prototypes - Internal functions
278 */
279 /* Attach detach */
280 static int ath5k_attach(struct pci_dev *pdev,
281 struct ieee80211_hw *hw);
282 static void ath5k_detach(struct pci_dev *pdev,
283 struct ieee80211_hw *hw);
284 /* Channel/mode setup */
285 static inline short ath5k_ieee2mhz(short chan);
286 static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
287 struct ieee80211_channel *channels,
288 unsigned int mode,
289 unsigned int max);
290 static int ath5k_setup_bands(struct ieee80211_hw *hw);
291 static int ath5k_chan_set(struct ath5k_softc *sc,
292 struct ieee80211_channel *chan);
293 static void ath5k_setcurmode(struct ath5k_softc *sc,
294 unsigned int mode);
295 static void ath5k_mode_setup(struct ath5k_softc *sc);
296
297 /* Descriptor setup */
298 static int ath5k_desc_alloc(struct ath5k_softc *sc,
299 struct pci_dev *pdev);
300 static void ath5k_desc_free(struct ath5k_softc *sc,
301 struct pci_dev *pdev);
302 /* Buffers setup */
303 static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
304 struct ath5k_buf *bf);
305 static int ath5k_txbuf_setup(struct ath5k_softc *sc,
306 struct ath5k_buf *bf,
307 struct ath5k_txq *txq);
308 static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
309 struct ath5k_buf *bf)
310 {
311 BUG_ON(!bf);
312 if (!bf->skb)
313 return;
314 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
315 PCI_DMA_TODEVICE);
316 dev_kfree_skb_any(bf->skb);
317 bf->skb = NULL;
318 }
319
320 static inline void ath5k_rxbuf_free(struct ath5k_softc *sc,
321 struct ath5k_buf *bf)
322 {
323 BUG_ON(!bf);
324 if (!bf->skb)
325 return;
326 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
327 PCI_DMA_FROMDEVICE);
328 dev_kfree_skb_any(bf->skb);
329 bf->skb = NULL;
330 }
331
332
333 /* Queues setup */
334 static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
335 int qtype, int subtype);
336 static int ath5k_beaconq_setup(struct ath5k_hw *ah);
337 static int ath5k_beaconq_config(struct ath5k_softc *sc);
338 static void ath5k_txq_drainq(struct ath5k_softc *sc,
339 struct ath5k_txq *txq);
340 static void ath5k_txq_cleanup(struct ath5k_softc *sc);
341 static void ath5k_txq_release(struct ath5k_softc *sc);
342 /* Rx handling */
343 static int ath5k_rx_start(struct ath5k_softc *sc);
344 static void ath5k_rx_stop(struct ath5k_softc *sc);
345 static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
346 struct ath5k_desc *ds,
347 struct sk_buff *skb,
348 struct ath5k_rx_status *rs);
349 static void ath5k_tasklet_rx(unsigned long data);
350 /* Tx handling */
351 static void ath5k_tx_processq(struct ath5k_softc *sc,
352 struct ath5k_txq *txq);
353 static void ath5k_tasklet_tx(unsigned long data);
354 /* Beacon handling */
355 static int ath5k_beacon_setup(struct ath5k_softc *sc,
356 struct ath5k_buf *bf);
357 static void ath5k_beacon_send(struct ath5k_softc *sc);
358 static void ath5k_beacon_config(struct ath5k_softc *sc);
359 static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
360 static void ath5k_tasklet_beacon(unsigned long data);
361
362 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
363 {
364 u64 tsf = ath5k_hw_get_tsf64(ah);
365
366 if ((tsf & 0x7fff) < rstamp)
367 tsf -= 0x8000;
368
369 return (tsf & ~0x7fff) | rstamp;
370 }
371
372 /* Interrupt handling */
373 static int ath5k_init(struct ath5k_softc *sc);
374 static int ath5k_stop_locked(struct ath5k_softc *sc);
375 static int ath5k_stop_hw(struct ath5k_softc *sc);
376 static irqreturn_t ath5k_intr(int irq, void *dev_id);
377 static void ath5k_tasklet_reset(unsigned long data);
378
379 static void ath5k_tasklet_calibrate(unsigned long data);
380
381 /*
382 * Module init/exit functions
383 */
384 static int __init
385 init_ath5k_pci(void)
386 {
387 int ret;
388
389 ath5k_debug_init();
390
391 ret = pci_register_driver(&ath5k_pci_driver);
392 if (ret) {
393 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
394 return ret;
395 }
396
397 return 0;
398 }
399
400 static void __exit
401 exit_ath5k_pci(void)
402 {
403 pci_unregister_driver(&ath5k_pci_driver);
404
405 ath5k_debug_finish();
406 }
407
408 module_init(init_ath5k_pci);
409 module_exit(exit_ath5k_pci);
410
411
412 /********************\
413 * PCI Initialization *
414 \********************/
415
416 static const char *
417 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
418 {
419 const char *name = "xxxxx";
420 unsigned int i;
421
422 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
423 if (srev_names[i].sr_type != type)
424 continue;
425
426 if ((val & 0xf0) == srev_names[i].sr_val)
427 name = srev_names[i].sr_name;
428
429 if ((val & 0xff) == srev_names[i].sr_val) {
430 name = srev_names[i].sr_name;
431 break;
432 }
433 }
434
435 return name;
436 }
437
438 static int __devinit
439 ath5k_pci_probe(struct pci_dev *pdev,
440 const struct pci_device_id *id)
441 {
442 void __iomem *mem;
443 struct ath5k_softc *sc;
444 struct ieee80211_hw *hw;
445 int ret;
446 u8 csz;
447
448 ret = pci_enable_device(pdev);
449 if (ret) {
450 dev_err(&pdev->dev, "can't enable device\n");
451 goto err;
452 }
453
454 /* XXX 32-bit addressing only */
455 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
456 if (ret) {
457 dev_err(&pdev->dev, "32-bit DMA not available\n");
458 goto err_dis;
459 }
460
461 /*
462 * Cache line size is used to size and align various
463 * structures used to communicate with the hardware.
464 */
465 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
466 if (csz == 0) {
467 /*
468 * Linux 2.4.18 (at least) writes the cache line size
469 * register as a 16-bit wide register which is wrong.
470 * We must have this setup properly for rx buffer
471 * DMA to work so force a reasonable value here if it
472 * comes up zero.
473 */
474 csz = L1_CACHE_BYTES >> 2;
475 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
476 }
477 /*
478 * The default setting of latency timer yields poor results,
479 * set it to the value used by other systems. It may be worth
480 * tweaking this setting more.
481 */
482 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
483
484 /* Enable bus mastering */
485 pci_set_master(pdev);
486
487 /*
488 * Disable the RETRY_TIMEOUT register (0x41) to keep
489 * PCI Tx retries from interfering with C3 CPU state.
490 */
491 pci_write_config_byte(pdev, 0x41, 0);
492
493 ret = pci_request_region(pdev, 0, "ath5k");
494 if (ret) {
495 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
496 goto err_dis;
497 }
498
499 mem = pci_iomap(pdev, 0, 0);
500 if (!mem) {
501 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
502 ret = -EIO;
503 goto err_reg;
504 }
505
506 /*
507 * Allocate hw (mac80211 main struct)
508 * and hw->priv (driver private data)
509 */
510 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
511 if (hw == NULL) {
512 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
513 ret = -ENOMEM;
514 goto err_map;
515 }
516
517 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
518
519 /* Initialize driver private data */
520 SET_IEEE80211_DEV(hw, &pdev->dev);
521 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
522 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
523 IEEE80211_HW_SIGNAL_DBM |
524 IEEE80211_HW_NOISE_DBM;
525
526 hw->wiphy->interface_modes =
527 BIT(NL80211_IFTYPE_AP) |
528 BIT(NL80211_IFTYPE_STATION) |
529 BIT(NL80211_IFTYPE_ADHOC) |
530 BIT(NL80211_IFTYPE_MESH_POINT);
531
532 hw->extra_tx_headroom = 2;
533 hw->channel_change_time = 5000;
534 sc = hw->priv;
535 sc->hw = hw;
536 sc->pdev = pdev;
537
538 ath5k_debug_init_device(sc);
539
540 /*
541 * Mark the device as detached to avoid processing
542 * interrupts until setup is complete.
543 */
544 __set_bit(ATH_STAT_INVALID, sc->status);
545
546 sc->iobase = mem; /* So we can unmap it on detach */
547 sc->common.cachelsz = csz << 2; /* convert to bytes */
548 sc->opmode = NL80211_IFTYPE_STATION;
549 sc->bintval = 1000;
550 mutex_init(&sc->lock);
551 spin_lock_init(&sc->rxbuflock);
552 spin_lock_init(&sc->txbuflock);
553 spin_lock_init(&sc->block);
554
555 /* Set private data */
556 pci_set_drvdata(pdev, hw);
557
558 /* Setup interrupt handler */
559 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
560 if (ret) {
561 ATH5K_ERR(sc, "request_irq failed\n");
562 goto err_free;
563 }
564
565 /* Initialize device */
566 sc->ah = ath5k_hw_attach(sc, id->driver_data);
567 if (IS_ERR(sc->ah)) {
568 ret = PTR_ERR(sc->ah);
569 goto err_irq;
570 }
571
572 /* set up multi-rate retry capabilities */
573 if (sc->ah->ah_version == AR5K_AR5212) {
574 hw->max_rates = 4;
575 hw->max_rate_tries = 11;
576 }
577
578 /* Finish private driver data initialization */
579 ret = ath5k_attach(pdev, hw);
580 if (ret)
581 goto err_ah;
582
583 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
584 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
585 sc->ah->ah_mac_srev,
586 sc->ah->ah_phy_revision);
587
588 if (!sc->ah->ah_single_chip) {
589 /* Single chip radio (!RF5111) */
590 if (sc->ah->ah_radio_5ghz_revision &&
591 !sc->ah->ah_radio_2ghz_revision) {
592 /* No 5GHz support -> report 2GHz radio */
593 if (!test_bit(AR5K_MODE_11A,
594 sc->ah->ah_capabilities.cap_mode)) {
595 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
596 ath5k_chip_name(AR5K_VERSION_RAD,
597 sc->ah->ah_radio_5ghz_revision),
598 sc->ah->ah_radio_5ghz_revision);
599 /* No 2GHz support (5110 and some
600 * 5Ghz only cards) -> report 5Ghz radio */
601 } else if (!test_bit(AR5K_MODE_11B,
602 sc->ah->ah_capabilities.cap_mode)) {
603 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
604 ath5k_chip_name(AR5K_VERSION_RAD,
605 sc->ah->ah_radio_5ghz_revision),
606 sc->ah->ah_radio_5ghz_revision);
607 /* Multiband radio */
608 } else {
609 ATH5K_INFO(sc, "RF%s multiband radio found"
610 " (0x%x)\n",
611 ath5k_chip_name(AR5K_VERSION_RAD,
612 sc->ah->ah_radio_5ghz_revision),
613 sc->ah->ah_radio_5ghz_revision);
614 }
615 }
616 /* Multi chip radio (RF5111 - RF2111) ->
617 * report both 2GHz/5GHz radios */
618 else if (sc->ah->ah_radio_5ghz_revision &&
619 sc->ah->ah_radio_2ghz_revision){
620 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
621 ath5k_chip_name(AR5K_VERSION_RAD,
622 sc->ah->ah_radio_5ghz_revision),
623 sc->ah->ah_radio_5ghz_revision);
624 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
625 ath5k_chip_name(AR5K_VERSION_RAD,
626 sc->ah->ah_radio_2ghz_revision),
627 sc->ah->ah_radio_2ghz_revision);
628 }
629 }
630
631
632 /* ready to process interrupts */
633 __clear_bit(ATH_STAT_INVALID, sc->status);
634
635 return 0;
636 err_ah:
637 ath5k_hw_detach(sc->ah);
638 err_irq:
639 free_irq(pdev->irq, sc);
640 err_free:
641 ieee80211_free_hw(hw);
642 err_map:
643 pci_iounmap(pdev, mem);
644 err_reg:
645 pci_release_region(pdev, 0);
646 err_dis:
647 pci_disable_device(pdev);
648 err:
649 return ret;
650 }
651
652 static void __devexit
653 ath5k_pci_remove(struct pci_dev *pdev)
654 {
655 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
656 struct ath5k_softc *sc = hw->priv;
657
658 ath5k_debug_finish_device(sc);
659 ath5k_detach(pdev, hw);
660 ath5k_hw_detach(sc->ah);
661 free_irq(pdev->irq, sc);
662 pci_iounmap(pdev, sc->iobase);
663 pci_release_region(pdev, 0);
664 pci_disable_device(pdev);
665 ieee80211_free_hw(hw);
666 }
667
668 #ifdef CONFIG_PM
669 static int
670 ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
671 {
672 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
673 struct ath5k_softc *sc = hw->priv;
674
675 ath5k_led_off(sc);
676
677 pci_save_state(pdev);
678 pci_disable_device(pdev);
679 pci_set_power_state(pdev, PCI_D3hot);
680
681 return 0;
682 }
683
684 static int
685 ath5k_pci_resume(struct pci_dev *pdev)
686 {
687 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
688 struct ath5k_softc *sc = hw->priv;
689 int err;
690
691 pci_restore_state(pdev);
692
693 err = pci_enable_device(pdev);
694 if (err)
695 return err;
696
697 /*
698 * Suspend/Resume resets the PCI configuration space, so we have to
699 * re-disable the RETRY_TIMEOUT register (0x41) to keep
700 * PCI Tx retries from interfering with C3 CPU state
701 */
702 pci_write_config_byte(pdev, 0x41, 0);
703
704 ath5k_led_enable(sc);
705 return 0;
706 }
707 #endif /* CONFIG_PM */
708
709
710 /***********************\
711 * Driver Initialization *
712 \***********************/
713
714 static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
715 {
716 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
717 struct ath5k_softc *sc = hw->priv;
718 struct ath_regulatory *reg = &sc->ah->ah_regulatory;
719
720 return ath_reg_notifier_apply(wiphy, request, reg);
721 }
722
723 static int
724 ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
725 {
726 struct ath5k_softc *sc = hw->priv;
727 struct ath5k_hw *ah = sc->ah;
728 u8 mac[ETH_ALEN] = {};
729 int ret;
730
731 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
732
733 /*
734 * Check if the MAC has multi-rate retry support.
735 * We do this by trying to setup a fake extended
736 * descriptor. MAC's that don't have support will
737 * return false w/o doing anything. MAC's that do
738 * support it will return true w/o doing anything.
739 */
740 ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
741 if (ret < 0)
742 goto err;
743 if (ret > 0)
744 __set_bit(ATH_STAT_MRRETRY, sc->status);
745
746 /*
747 * Collect the channel list. The 802.11 layer
748 * is resposible for filtering this list based
749 * on settings like the phy mode and regulatory
750 * domain restrictions.
751 */
752 ret = ath5k_setup_bands(hw);
753 if (ret) {
754 ATH5K_ERR(sc, "can't get channels\n");
755 goto err;
756 }
757
758 /* NB: setup here so ath5k_rate_update is happy */
759 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
760 ath5k_setcurmode(sc, AR5K_MODE_11A);
761 else
762 ath5k_setcurmode(sc, AR5K_MODE_11B);
763
764 /*
765 * Allocate tx+rx descriptors and populate the lists.
766 */
767 ret = ath5k_desc_alloc(sc, pdev);
768 if (ret) {
769 ATH5K_ERR(sc, "can't allocate descriptors\n");
770 goto err;
771 }
772
773 /*
774 * Allocate hardware transmit queues: one queue for
775 * beacon frames and one data queue for each QoS
776 * priority. Note that hw functions handle reseting
777 * these queues at the needed time.
778 */
779 ret = ath5k_beaconq_setup(ah);
780 if (ret < 0) {
781 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
782 goto err_desc;
783 }
784 sc->bhalq = ret;
785 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0);
786 if (IS_ERR(sc->cabq)) {
787 ATH5K_ERR(sc, "can't setup cab queue\n");
788 ret = PTR_ERR(sc->cabq);
789 goto err_bhal;
790 }
791
792 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
793 if (IS_ERR(sc->txq)) {
794 ATH5K_ERR(sc, "can't setup xmit queue\n");
795 ret = PTR_ERR(sc->txq);
796 goto err_queues;
797 }
798
799 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
800 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
801 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
802 tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc);
803 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
804
805 ret = ath5k_eeprom_read_mac(ah, mac);
806 if (ret) {
807 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
808 sc->pdev->device);
809 goto err_queues;
810 }
811
812 SET_IEEE80211_PERM_ADDR(hw, mac);
813 /* All MAC address bits matter for ACKs */
814 memset(sc->bssidmask, 0xff, ETH_ALEN);
815 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
816
817 ah->ah_regulatory.current_rd =
818 ah->ah_capabilities.cap_eeprom.ee_regdomain;
819 ret = ath_regd_init(&ah->ah_regulatory, hw->wiphy, ath5k_reg_notifier);
820 if (ret) {
821 ATH5K_ERR(sc, "can't initialize regulatory system\n");
822 goto err_queues;
823 }
824
825 ret = ieee80211_register_hw(hw);
826 if (ret) {
827 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
828 goto err_queues;
829 }
830
831 if (!ath_is_world_regd(&sc->ah->ah_regulatory))
832 regulatory_hint(hw->wiphy, sc->ah->ah_regulatory.alpha2);
833
834 ath5k_init_leds(sc);
835
836 return 0;
837 err_queues:
838 ath5k_txq_release(sc);
839 err_bhal:
840 ath5k_hw_release_tx_queue(ah, sc->bhalq);
841 err_desc:
842 ath5k_desc_free(sc, pdev);
843 err:
844 return ret;
845 }
846
847 static void
848 ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
849 {
850 struct ath5k_softc *sc = hw->priv;
851
852 /*
853 * NB: the order of these is important:
854 * o call the 802.11 layer before detaching ath5k_hw to
855 * insure callbacks into the driver to delete global
856 * key cache entries can be handled
857 * o reclaim the tx queue data structures after calling
858 * the 802.11 layer as we'll get called back to reclaim
859 * node state and potentially want to use them
860 * o to cleanup the tx queues the hal is called, so detach
861 * it last
862 * XXX: ??? detach ath5k_hw ???
863 * Other than that, it's straightforward...
864 */
865 ieee80211_unregister_hw(hw);
866 ath5k_desc_free(sc, pdev);
867 ath5k_txq_release(sc);
868 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
869 ath5k_unregister_leds(sc);
870
871 /*
872 * NB: can't reclaim these until after ieee80211_ifdetach
873 * returns because we'll get called back to reclaim node
874 * state and potentially want to use them.
875 */
876 }
877
878
879
880
881 /********************\
882 * Channel/mode setup *
883 \********************/
884
885 /*
886 * Convert IEEE channel number to MHz frequency.
887 */
888 static inline short
889 ath5k_ieee2mhz(short chan)
890 {
891 if (chan <= 14 || chan >= 27)
892 return ieee80211chan2mhz(chan);
893 else
894 return 2212 + chan * 20;
895 }
896
897 /*
898 * Returns true for the channel numbers used without all_channels modparam.
899 */
900 static bool ath5k_is_standard_channel(short chan)
901 {
902 return ((chan <= 14) ||
903 /* UNII 1,2 */
904 ((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
905 /* midband */
906 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
907 /* UNII-3 */
908 ((chan & 3) == 1 && chan >= 149 && chan <= 165));
909 }
910
911 static unsigned int
912 ath5k_copy_channels(struct ath5k_hw *ah,
913 struct ieee80211_channel *channels,
914 unsigned int mode,
915 unsigned int max)
916 {
917 unsigned int i, count, size, chfreq, freq, ch;
918
919 if (!test_bit(mode, ah->ah_modes))
920 return 0;
921
922 switch (mode) {
923 case AR5K_MODE_11A:
924 case AR5K_MODE_11A_TURBO:
925 /* 1..220, but 2GHz frequencies are filtered by check_channel */
926 size = 220 ;
927 chfreq = CHANNEL_5GHZ;
928 break;
929 case AR5K_MODE_11B:
930 case AR5K_MODE_11G:
931 case AR5K_MODE_11G_TURBO:
932 size = 26;
933 chfreq = CHANNEL_2GHZ;
934 break;
935 default:
936 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
937 return 0;
938 }
939
940 for (i = 0, count = 0; i < size && max > 0; i++) {
941 ch = i + 1 ;
942 freq = ath5k_ieee2mhz(ch);
943
944 /* Check if channel is supported by the chipset */
945 if (!ath5k_channel_ok(ah, freq, chfreq))
946 continue;
947
948 if (!modparam_all_channels && !ath5k_is_standard_channel(ch))
949 continue;
950
951 /* Write channel info and increment counter */
952 channels[count].center_freq = freq;
953 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
954 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
955 switch (mode) {
956 case AR5K_MODE_11A:
957 case AR5K_MODE_11G:
958 channels[count].hw_value = chfreq | CHANNEL_OFDM;
959 break;
960 case AR5K_MODE_11A_TURBO:
961 case AR5K_MODE_11G_TURBO:
962 channels[count].hw_value = chfreq |
963 CHANNEL_OFDM | CHANNEL_TURBO;
964 break;
965 case AR5K_MODE_11B:
966 channels[count].hw_value = CHANNEL_B;
967 }
968
969 count++;
970 max--;
971 }
972
973 return count;
974 }
975
976 static void
977 ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
978 {
979 u8 i;
980
981 for (i = 0; i < AR5K_MAX_RATES; i++)
982 sc->rate_idx[b->band][i] = -1;
983
984 for (i = 0; i < b->n_bitrates; i++) {
985 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
986 if (b->bitrates[i].hw_value_short)
987 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
988 }
989 }
990
991 static int
992 ath5k_setup_bands(struct ieee80211_hw *hw)
993 {
994 struct ath5k_softc *sc = hw->priv;
995 struct ath5k_hw *ah = sc->ah;
996 struct ieee80211_supported_band *sband;
997 int max_c, count_c = 0;
998 int i;
999
1000 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
1001 max_c = ARRAY_SIZE(sc->channels);
1002
1003 /* 2GHz band */
1004 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
1005 sband->band = IEEE80211_BAND_2GHZ;
1006 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
1007
1008 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
1009 /* G mode */
1010 memcpy(sband->bitrates, &ath5k_rates[0],
1011 sizeof(struct ieee80211_rate) * 12);
1012 sband->n_bitrates = 12;
1013
1014 sband->channels = sc->channels;
1015 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1016 AR5K_MODE_11G, max_c);
1017
1018 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1019 count_c = sband->n_channels;
1020 max_c -= count_c;
1021 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
1022 /* B mode */
1023 memcpy(sband->bitrates, &ath5k_rates[0],
1024 sizeof(struct ieee80211_rate) * 4);
1025 sband->n_bitrates = 4;
1026
1027 /* 5211 only supports B rates and uses 4bit rate codes
1028 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
1029 * fix them up here:
1030 */
1031 if (ah->ah_version == AR5K_AR5211) {
1032 for (i = 0; i < 4; i++) {
1033 sband->bitrates[i].hw_value =
1034 sband->bitrates[i].hw_value & 0xF;
1035 sband->bitrates[i].hw_value_short =
1036 sband->bitrates[i].hw_value_short & 0xF;
1037 }
1038 }
1039
1040 sband->channels = sc->channels;
1041 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1042 AR5K_MODE_11B, max_c);
1043
1044 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1045 count_c = sband->n_channels;
1046 max_c -= count_c;
1047 }
1048 ath5k_setup_rate_idx(sc, sband);
1049
1050 /* 5GHz band, A mode */
1051 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
1052 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
1053 sband->band = IEEE80211_BAND_5GHZ;
1054 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
1055
1056 memcpy(sband->bitrates, &ath5k_rates[4],
1057 sizeof(struct ieee80211_rate) * 8);
1058 sband->n_bitrates = 8;
1059
1060 sband->channels = &sc->channels[count_c];
1061 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1062 AR5K_MODE_11A, max_c);
1063
1064 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1065 }
1066 ath5k_setup_rate_idx(sc, sband);
1067
1068 ath5k_debug_dump_bands(sc);
1069
1070 return 0;
1071 }
1072
1073 /*
1074 * Set/change channels. We always reset the chip.
1075 * To accomplish this we must first cleanup any pending DMA,
1076 * then restart stuff after a la ath5k_init.
1077 *
1078 * Called with sc->lock.
1079 */
1080 static int
1081 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1082 {
1083 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1084 sc->curchan->center_freq, chan->center_freq);
1085
1086 /*
1087 * To switch channels clear any pending DMA operations;
1088 * wait long enough for the RX fifo to drain, reset the
1089 * hardware at the new frequency, and then re-enable
1090 * the relevant bits of the h/w.
1091 */
1092 return ath5k_reset(sc, chan);
1093 }
1094
1095 static void
1096 ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1097 {
1098 sc->curmode = mode;
1099
1100 if (mode == AR5K_MODE_11A) {
1101 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1102 } else {
1103 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1104 }
1105 }
1106
1107 static void
1108 ath5k_mode_setup(struct ath5k_softc *sc)
1109 {
1110 struct ath5k_hw *ah = sc->ah;
1111 u32 rfilt;
1112
1113 ah->ah_op_mode = sc->opmode;
1114
1115 /* configure rx filter */
1116 rfilt = sc->filter_flags;
1117 ath5k_hw_set_rx_filter(ah, rfilt);
1118
1119 if (ath5k_hw_hasbssidmask(ah))
1120 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1121
1122 /* configure operational mode */
1123 ath5k_hw_set_opmode(ah);
1124
1125 ath5k_hw_set_mcast_filter(ah, 0, 0);
1126 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1127 }
1128
1129 static inline int
1130 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1131 {
1132 int rix;
1133
1134 /* return base rate on errors */
1135 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
1136 "hw_rix out of bounds: %x\n", hw_rix))
1137 return 0;
1138
1139 rix = sc->rate_idx[sc->curband->band][hw_rix];
1140 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
1141 rix = 0;
1142
1143 return rix;
1144 }
1145
1146 /***************\
1147 * Buffers setup *
1148 \***************/
1149
1150 static
1151 struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
1152 {
1153 struct sk_buff *skb;
1154
1155 /*
1156 * Allocate buffer with headroom_needed space for the
1157 * fake physical layer header at the start.
1158 */
1159 skb = ath_rxbuf_alloc(&sc->common,
1160 sc->rxbufsize + sc->common.cachelsz - 1,
1161 GFP_ATOMIC);
1162
1163 if (!skb) {
1164 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1165 sc->rxbufsize + sc->common.cachelsz - 1);
1166 return NULL;
1167 }
1168
1169 *skb_addr = pci_map_single(sc->pdev,
1170 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
1171 if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
1172 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1173 dev_kfree_skb(skb);
1174 return NULL;
1175 }
1176 return skb;
1177 }
1178
1179 static int
1180 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1181 {
1182 struct ath5k_hw *ah = sc->ah;
1183 struct sk_buff *skb = bf->skb;
1184 struct ath5k_desc *ds;
1185
1186 if (!skb) {
1187 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
1188 if (!skb)
1189 return -ENOMEM;
1190 bf->skb = skb;
1191 }
1192
1193 /*
1194 * Setup descriptors. For receive we always terminate
1195 * the descriptor list with a self-linked entry so we'll
1196 * not get overrun under high load (as can happen with a
1197 * 5212 when ANI processing enables PHY error frames).
1198 *
1199 * To insure the last descriptor is self-linked we create
1200 * each descriptor as self-linked and add it to the end. As
1201 * each additional descriptor is added the previous self-linked
1202 * entry is ``fixed'' naturally. This should be safe even
1203 * if DMA is happening. When processing RX interrupts we
1204 * never remove/process the last, self-linked, entry on the
1205 * descriptor list. This insures the hardware always has
1206 * someplace to write a new frame.
1207 */
1208 ds = bf->desc;
1209 ds->ds_link = bf->daddr; /* link to self */
1210 ds->ds_data = bf->skbaddr;
1211 ah->ah_setup_rx_desc(ah, ds,
1212 skb_tailroom(skb), /* buffer size */
1213 0);
1214
1215 if (sc->rxlink != NULL)
1216 *sc->rxlink = bf->daddr;
1217 sc->rxlink = &ds->ds_link;
1218 return 0;
1219 }
1220
1221 static int
1222 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
1223 struct ath5k_txq *txq)
1224 {
1225 struct ath5k_hw *ah = sc->ah;
1226 struct ath5k_desc *ds = bf->desc;
1227 struct sk_buff *skb = bf->skb;
1228 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1229 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1230 struct ieee80211_rate *rate;
1231 unsigned int mrr_rate[3], mrr_tries[3];
1232 int i, ret;
1233 u16 hw_rate;
1234 u16 cts_rate = 0;
1235 u16 duration = 0;
1236 u8 rc_flags;
1237
1238 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
1239
1240 /* XXX endianness */
1241 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1242 PCI_DMA_TODEVICE);
1243
1244 rate = ieee80211_get_tx_rate(sc->hw, info);
1245
1246 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
1247 flags |= AR5K_TXDESC_NOACK;
1248
1249 rc_flags = info->control.rates[0].flags;
1250 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
1251 rate->hw_value_short : rate->hw_value;
1252
1253 pktlen = skb->len;
1254
1255 /* FIXME: If we are in g mode and rate is a CCK rate
1256 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1257 * from tx power (value is in dB units already) */
1258 if (info->control.hw_key) {
1259 keyidx = info->control.hw_key->hw_key_idx;
1260 pktlen += info->control.hw_key->icv_len;
1261 }
1262 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1263 flags |= AR5K_TXDESC_RTSENA;
1264 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1265 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
1266 sc->vif, pktlen, info));
1267 }
1268 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1269 flags |= AR5K_TXDESC_CTSENA;
1270 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1271 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
1272 sc->vif, pktlen, info));
1273 }
1274 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1275 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
1276 (sc->power_level * 2),
1277 hw_rate,
1278 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
1279 cts_rate, duration);
1280 if (ret)
1281 goto err_unmap;
1282
1283 memset(mrr_rate, 0, sizeof(mrr_rate));
1284 memset(mrr_tries, 0, sizeof(mrr_tries));
1285 for (i = 0; i < 3; i++) {
1286 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
1287 if (!rate)
1288 break;
1289
1290 mrr_rate[i] = rate->hw_value;
1291 mrr_tries[i] = info->control.rates[i + 1].count;
1292 }
1293
1294 ah->ah_setup_mrr_tx_desc(ah, ds,
1295 mrr_rate[0], mrr_tries[0],
1296 mrr_rate[1], mrr_tries[1],
1297 mrr_rate[2], mrr_tries[2]);
1298
1299 ds->ds_link = 0;
1300 ds->ds_data = bf->skbaddr;
1301
1302 spin_lock_bh(&txq->lock);
1303 list_add_tail(&bf->list, &txq->q);
1304 sc->tx_stats[txq->qnum].len++;
1305 if (txq->link == NULL) /* is this first packet? */
1306 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
1307 else /* no, so only link it */
1308 *txq->link = bf->daddr;
1309
1310 txq->link = &ds->ds_link;
1311 ath5k_hw_start_tx_dma(ah, txq->qnum);
1312 mmiowb();
1313 spin_unlock_bh(&txq->lock);
1314
1315 return 0;
1316 err_unmap:
1317 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1318 return ret;
1319 }
1320
1321 /*******************\
1322 * Descriptors setup *
1323 \*******************/
1324
1325 static int
1326 ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1327 {
1328 struct ath5k_desc *ds;
1329 struct ath5k_buf *bf;
1330 dma_addr_t da;
1331 unsigned int i;
1332 int ret;
1333
1334 /* allocate descriptors */
1335 sc->desc_len = sizeof(struct ath5k_desc) *
1336 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1337 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1338 if (sc->desc == NULL) {
1339 ATH5K_ERR(sc, "can't allocate descriptors\n");
1340 ret = -ENOMEM;
1341 goto err;
1342 }
1343 ds = sc->desc;
1344 da = sc->desc_daddr;
1345 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1346 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1347
1348 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1349 sizeof(struct ath5k_buf), GFP_KERNEL);
1350 if (bf == NULL) {
1351 ATH5K_ERR(sc, "can't allocate bufptr\n");
1352 ret = -ENOMEM;
1353 goto err_free;
1354 }
1355 sc->bufptr = bf;
1356
1357 INIT_LIST_HEAD(&sc->rxbuf);
1358 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1359 bf->desc = ds;
1360 bf->daddr = da;
1361 list_add_tail(&bf->list, &sc->rxbuf);
1362 }
1363
1364 INIT_LIST_HEAD(&sc->txbuf);
1365 sc->txbuf_len = ATH_TXBUF;
1366 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1367 da += sizeof(*ds)) {
1368 bf->desc = ds;
1369 bf->daddr = da;
1370 list_add_tail(&bf->list, &sc->txbuf);
1371 }
1372
1373 /* beacon buffer */
1374 bf->desc = ds;
1375 bf->daddr = da;
1376 sc->bbuf = bf;
1377
1378 return 0;
1379 err_free:
1380 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1381 err:
1382 sc->desc = NULL;
1383 return ret;
1384 }
1385
1386 static void
1387 ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1388 {
1389 struct ath5k_buf *bf;
1390
1391 ath5k_txbuf_free(sc, sc->bbuf);
1392 list_for_each_entry(bf, &sc->txbuf, list)
1393 ath5k_txbuf_free(sc, bf);
1394 list_for_each_entry(bf, &sc->rxbuf, list)
1395 ath5k_rxbuf_free(sc, bf);
1396
1397 /* Free memory associated with all descriptors */
1398 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1399
1400 kfree(sc->bufptr);
1401 sc->bufptr = NULL;
1402 }
1403
1404
1405
1406
1407
1408 /**************\
1409 * Queues setup *
1410 \**************/
1411
1412 static struct ath5k_txq *
1413 ath5k_txq_setup(struct ath5k_softc *sc,
1414 int qtype, int subtype)
1415 {
1416 struct ath5k_hw *ah = sc->ah;
1417 struct ath5k_txq *txq;
1418 struct ath5k_txq_info qi = {
1419 .tqi_subtype = subtype,
1420 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1421 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1422 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1423 };
1424 int qnum;
1425
1426 /*
1427 * Enable interrupts only for EOL and DESC conditions.
1428 * We mark tx descriptors to receive a DESC interrupt
1429 * when a tx queue gets deep; otherwise waiting for the
1430 * EOL to reap descriptors. Note that this is done to
1431 * reduce interrupt load and this only defers reaping
1432 * descriptors, never transmitting frames. Aside from
1433 * reducing interrupts this also permits more concurrency.
1434 * The only potential downside is if the tx queue backs
1435 * up in which case the top half of the kernel may backup
1436 * due to a lack of tx descriptors.
1437 */
1438 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1439 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1440 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1441 if (qnum < 0) {
1442 /*
1443 * NB: don't print a message, this happens
1444 * normally on parts with too few tx queues
1445 */
1446 return ERR_PTR(qnum);
1447 }
1448 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1449 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1450 qnum, ARRAY_SIZE(sc->txqs));
1451 ath5k_hw_release_tx_queue(ah, qnum);
1452 return ERR_PTR(-EINVAL);
1453 }
1454 txq = &sc->txqs[qnum];
1455 if (!txq->setup) {
1456 txq->qnum = qnum;
1457 txq->link = NULL;
1458 INIT_LIST_HEAD(&txq->q);
1459 spin_lock_init(&txq->lock);
1460 txq->setup = true;
1461 }
1462 return &sc->txqs[qnum];
1463 }
1464
1465 static int
1466 ath5k_beaconq_setup(struct ath5k_hw *ah)
1467 {
1468 struct ath5k_txq_info qi = {
1469 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1470 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1471 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1472 /* NB: for dynamic turbo, don't enable any other interrupts */
1473 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1474 };
1475
1476 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1477 }
1478
1479 static int
1480 ath5k_beaconq_config(struct ath5k_softc *sc)
1481 {
1482 struct ath5k_hw *ah = sc->ah;
1483 struct ath5k_txq_info qi;
1484 int ret;
1485
1486 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1487 if (ret)
1488 return ret;
1489 if (sc->opmode == NL80211_IFTYPE_AP ||
1490 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
1491 /*
1492 * Always burst out beacon and CAB traffic
1493 * (aifs = cwmin = cwmax = 0)
1494 */
1495 qi.tqi_aifs = 0;
1496 qi.tqi_cw_min = 0;
1497 qi.tqi_cw_max = 0;
1498 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
1499 /*
1500 * Adhoc mode; backoff between 0 and (2 * cw_min).
1501 */
1502 qi.tqi_aifs = 0;
1503 qi.tqi_cw_min = 0;
1504 qi.tqi_cw_max = 2 * ah->ah_cw_min;
1505 }
1506
1507 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1508 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1509 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1510
1511 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
1512 if (ret) {
1513 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1514 "hardware queue!\n", __func__);
1515 return ret;
1516 }
1517
1518 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1519 }
1520
1521 static void
1522 ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1523 {
1524 struct ath5k_buf *bf, *bf0;
1525
1526 /*
1527 * NB: this assumes output has been stopped and
1528 * we do not need to block ath5k_tx_tasklet
1529 */
1530 spin_lock_bh(&txq->lock);
1531 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1532 ath5k_debug_printtxbuf(sc, bf);
1533
1534 ath5k_txbuf_free(sc, bf);
1535
1536 spin_lock_bh(&sc->txbuflock);
1537 sc->tx_stats[txq->qnum].len--;
1538 list_move_tail(&bf->list, &sc->txbuf);
1539 sc->txbuf_len++;
1540 spin_unlock_bh(&sc->txbuflock);
1541 }
1542 txq->link = NULL;
1543 spin_unlock_bh(&txq->lock);
1544 }
1545
1546 /*
1547 * Drain the transmit queues and reclaim resources.
1548 */
1549 static void
1550 ath5k_txq_cleanup(struct ath5k_softc *sc)
1551 {
1552 struct ath5k_hw *ah = sc->ah;
1553 unsigned int i;
1554
1555 /* XXX return value */
1556 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1557 /* don't touch the hardware if marked invalid */
1558 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1559 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1560 ath5k_hw_get_txdp(ah, sc->bhalq));
1561 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1562 if (sc->txqs[i].setup) {
1563 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1564 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1565 "link %p\n",
1566 sc->txqs[i].qnum,
1567 ath5k_hw_get_txdp(ah,
1568 sc->txqs[i].qnum),
1569 sc->txqs[i].link);
1570 }
1571 }
1572 ieee80211_wake_queues(sc->hw); /* XXX move to callers */
1573
1574 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1575 if (sc->txqs[i].setup)
1576 ath5k_txq_drainq(sc, &sc->txqs[i]);
1577 }
1578
1579 static void
1580 ath5k_txq_release(struct ath5k_softc *sc)
1581 {
1582 struct ath5k_txq *txq = sc->txqs;
1583 unsigned int i;
1584
1585 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1586 if (txq->setup) {
1587 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1588 txq->setup = false;
1589 }
1590 }
1591
1592
1593
1594
1595 /*************\
1596 * RX Handling *
1597 \*************/
1598
1599 /*
1600 * Enable the receive h/w following a reset.
1601 */
1602 static int
1603 ath5k_rx_start(struct ath5k_softc *sc)
1604 {
1605 struct ath5k_hw *ah = sc->ah;
1606 struct ath5k_buf *bf;
1607 int ret;
1608
1609 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->common.cachelsz);
1610
1611 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1612 sc->common.cachelsz, sc->rxbufsize);
1613
1614 spin_lock_bh(&sc->rxbuflock);
1615 sc->rxlink = NULL;
1616 list_for_each_entry(bf, &sc->rxbuf, list) {
1617 ret = ath5k_rxbuf_setup(sc, bf);
1618 if (ret != 0) {
1619 spin_unlock_bh(&sc->rxbuflock);
1620 goto err;
1621 }
1622 }
1623 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1624 ath5k_hw_set_rxdp(ah, bf->daddr);
1625 spin_unlock_bh(&sc->rxbuflock);
1626
1627 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
1628 ath5k_mode_setup(sc); /* set filters, etc. */
1629 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1630
1631 return 0;
1632 err:
1633 return ret;
1634 }
1635
1636 /*
1637 * Disable the receive h/w in preparation for a reset.
1638 */
1639 static void
1640 ath5k_rx_stop(struct ath5k_softc *sc)
1641 {
1642 struct ath5k_hw *ah = sc->ah;
1643
1644 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
1645 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1646 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
1647
1648 ath5k_debug_printrxbuffs(sc, ah);
1649
1650 sc->rxlink = NULL; /* just in case */
1651 }
1652
1653 static unsigned int
1654 ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
1655 struct sk_buff *skb, struct ath5k_rx_status *rs)
1656 {
1657 struct ieee80211_hdr *hdr = (void *)skb->data;
1658 unsigned int keyix, hlen;
1659
1660 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1661 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1662 return RX_FLAG_DECRYPTED;
1663
1664 /* Apparently when a default key is used to decrypt the packet
1665 the hw does not set the index used to decrypt. In such cases
1666 get the index from the packet. */
1667 hlen = ieee80211_hdrlen(hdr->frame_control);
1668 if (ieee80211_has_protected(hdr->frame_control) &&
1669 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1670 skb->len >= hlen + 4) {
1671 keyix = skb->data[hlen + 3] >> 6;
1672
1673 if (test_bit(keyix, sc->keymap))
1674 return RX_FLAG_DECRYPTED;
1675 }
1676
1677 return 0;
1678 }
1679
1680
1681 static void
1682 ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1683 struct ieee80211_rx_status *rxs)
1684 {
1685 u64 tsf, bc_tstamp;
1686 u32 hw_tu;
1687 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1688
1689 if (ieee80211_is_beacon(mgmt->frame_control) &&
1690 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1691 memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1692 /*
1693 * Received an IBSS beacon with the same BSSID. Hardware *must*
1694 * have updated the local TSF. We have to work around various
1695 * hardware bugs, though...
1696 */
1697 tsf = ath5k_hw_get_tsf64(sc->ah);
1698 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1699 hw_tu = TSF_TO_TU(tsf);
1700
1701 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1702 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1703 (unsigned long long)bc_tstamp,
1704 (unsigned long long)rxs->mactime,
1705 (unsigned long long)(rxs->mactime - bc_tstamp),
1706 (unsigned long long)tsf);
1707
1708 /*
1709 * Sometimes the HW will give us a wrong tstamp in the rx
1710 * status, causing the timestamp extension to go wrong.
1711 * (This seems to happen especially with beacon frames bigger
1712 * than 78 byte (incl. FCS))
1713 * But we know that the receive timestamp must be later than the
1714 * timestamp of the beacon since HW must have synced to that.
1715 *
1716 * NOTE: here we assume mactime to be after the frame was
1717 * received, not like mac80211 which defines it at the start.
1718 */
1719 if (bc_tstamp > rxs->mactime) {
1720 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1721 "fixing mactime from %llx to %llx\n",
1722 (unsigned long long)rxs->mactime,
1723 (unsigned long long)tsf);
1724 rxs->mactime = tsf;
1725 }
1726
1727 /*
1728 * Local TSF might have moved higher than our beacon timers,
1729 * in that case we have to update them to continue sending
1730 * beacons. This also takes care of synchronizing beacon sending
1731 * times with other stations.
1732 */
1733 if (hw_tu >= sc->nexttbtt)
1734 ath5k_beacon_update_timers(sc, bc_tstamp);
1735 }
1736 }
1737
1738 static void
1739 ath5k_tasklet_rx(unsigned long data)
1740 {
1741 struct ieee80211_rx_status rxs = {};
1742 struct ath5k_rx_status rs = {};
1743 struct sk_buff *skb, *next_skb;
1744 dma_addr_t next_skb_addr;
1745 struct ath5k_softc *sc = (void *)data;
1746 struct ath5k_buf *bf;
1747 struct ath5k_desc *ds;
1748 int ret;
1749 int hdrlen;
1750 int padsize;
1751
1752 spin_lock(&sc->rxbuflock);
1753 if (list_empty(&sc->rxbuf)) {
1754 ATH5K_WARN(sc, "empty rx buf pool\n");
1755 goto unlock;
1756 }
1757 do {
1758 rxs.flag = 0;
1759
1760 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1761 BUG_ON(bf->skb == NULL);
1762 skb = bf->skb;
1763 ds = bf->desc;
1764
1765 /* bail if HW is still using self-linked descriptor */
1766 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
1767 break;
1768
1769 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1770 if (unlikely(ret == -EINPROGRESS))
1771 break;
1772 else if (unlikely(ret)) {
1773 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1774 spin_unlock(&sc->rxbuflock);
1775 return;
1776 }
1777
1778 if (unlikely(rs.rs_more)) {
1779 ATH5K_WARN(sc, "unsupported jumbo\n");
1780 goto next;
1781 }
1782
1783 if (unlikely(rs.rs_status)) {
1784 if (rs.rs_status & AR5K_RXERR_PHY)
1785 goto next;
1786 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
1787 /*
1788 * Decrypt error. If the error occurred
1789 * because there was no hardware key, then
1790 * let the frame through so the upper layers
1791 * can process it. This is necessary for 5210
1792 * parts which have no way to setup a ``clear''
1793 * key cache entry.
1794 *
1795 * XXX do key cache faulting
1796 */
1797 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1798 !(rs.rs_status & AR5K_RXERR_CRC))
1799 goto accept;
1800 }
1801 if (rs.rs_status & AR5K_RXERR_MIC) {
1802 rxs.flag |= RX_FLAG_MMIC_ERROR;
1803 goto accept;
1804 }
1805
1806 /* let crypto-error packets fall through in MNTR */
1807 if ((rs.rs_status &
1808 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
1809 sc->opmode != NL80211_IFTYPE_MONITOR)
1810 goto next;
1811 }
1812 accept:
1813 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
1814
1815 /*
1816 * If we can't replace bf->skb with a new skb under memory
1817 * pressure, just skip this packet
1818 */
1819 if (!next_skb)
1820 goto next;
1821
1822 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1823 PCI_DMA_FROMDEVICE);
1824 skb_put(skb, rs.rs_datalen);
1825
1826 /* The MAC header is padded to have 32-bit boundary if the
1827 * packet payload is non-zero. The general calculation for
1828 * padsize would take into account odd header lengths:
1829 * padsize = (4 - hdrlen % 4) % 4; However, since only
1830 * even-length headers are used, padding can only be 0 or 2
1831 * bytes and we can optimize this a bit. In addition, we must
1832 * not try to remove padding from short control frames that do
1833 * not have payload. */
1834 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1835 padsize = ath5k_pad_size(hdrlen);
1836 if (padsize) {
1837 memmove(skb->data + padsize, skb->data, hdrlen);
1838 skb_pull(skb, padsize);
1839 }
1840
1841 /*
1842 * always extend the mac timestamp, since this information is
1843 * also needed for proper IBSS merging.
1844 *
1845 * XXX: it might be too late to do it here, since rs_tstamp is
1846 * 15bit only. that means TSF extension has to be done within
1847 * 32768usec (about 32ms). it might be necessary to move this to
1848 * the interrupt handler, like it is done in madwifi.
1849 *
1850 * Unfortunately we don't know when the hardware takes the rx
1851 * timestamp (beginning of phy frame, data frame, end of rx?).
1852 * The only thing we know is that it is hardware specific...
1853 * On AR5213 it seems the rx timestamp is at the end of the
1854 * frame, but i'm not sure.
1855 *
1856 * NOTE: mac80211 defines mactime at the beginning of the first
1857 * data symbol. Since we don't have any time references it's
1858 * impossible to comply to that. This affects IBSS merge only
1859 * right now, so it's not too bad...
1860 */
1861 rxs.mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
1862 rxs.flag |= RX_FLAG_TSFT;
1863
1864 rxs.freq = sc->curchan->center_freq;
1865 rxs.band = sc->curband->band;
1866
1867 rxs.noise = sc->ah->ah_noise_floor;
1868 rxs.signal = rxs.noise + rs.rs_rssi;
1869
1870 /* An rssi of 35 indicates you should be able use
1871 * 54 Mbps reliably. A more elaborate scheme can be used
1872 * here but it requires a map of SNR/throughput for each
1873 * possible mode used */
1874 rxs.qual = rs.rs_rssi * 100 / 35;
1875
1876 /* rssi can be more than 35 though, anything above that
1877 * should be considered at 100% */
1878 if (rxs.qual > 100)
1879 rxs.qual = 100;
1880
1881 rxs.antenna = rs.rs_antenna;
1882 rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1883 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
1884
1885 if (rxs.rate_idx >= 0 && rs.rs_rate ==
1886 sc->curband->bitrates[rxs.rate_idx].hw_value_short)
1887 rxs.flag |= RX_FLAG_SHORTPRE;
1888
1889 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1890
1891 /* check beacons in IBSS mode */
1892 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1893 ath5k_check_ibss_tsf(sc, skb, &rxs);
1894
1895 memcpy(IEEE80211_SKB_RXCB(skb), &rxs, sizeof(rxs));
1896 ieee80211_rx(sc->hw, skb);
1897
1898 bf->skb = next_skb;
1899 bf->skbaddr = next_skb_addr;
1900 next:
1901 list_move_tail(&bf->list, &sc->rxbuf);
1902 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1903 unlock:
1904 spin_unlock(&sc->rxbuflock);
1905 }
1906
1907
1908
1909
1910 /*************\
1911 * TX Handling *
1912 \*************/
1913
1914 static void
1915 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1916 {
1917 struct ath5k_tx_status ts = {};
1918 struct ath5k_buf *bf, *bf0;
1919 struct ath5k_desc *ds;
1920 struct sk_buff *skb;
1921 struct ieee80211_tx_info *info;
1922 int i, ret;
1923
1924 spin_lock(&txq->lock);
1925 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1926 ds = bf->desc;
1927
1928 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
1929 if (unlikely(ret == -EINPROGRESS))
1930 break;
1931 else if (unlikely(ret)) {
1932 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1933 ret, txq->qnum);
1934 break;
1935 }
1936
1937 skb = bf->skb;
1938 info = IEEE80211_SKB_CB(skb);
1939 bf->skb = NULL;
1940
1941 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1942 PCI_DMA_TODEVICE);
1943
1944 ieee80211_tx_info_clear_status(info);
1945 for (i = 0; i < 4; i++) {
1946 struct ieee80211_tx_rate *r =
1947 &info->status.rates[i];
1948
1949 if (ts.ts_rate[i]) {
1950 r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
1951 r->count = ts.ts_retry[i];
1952 } else {
1953 r->idx = -1;
1954 r->count = 0;
1955 }
1956 }
1957
1958 /* count the successful attempt as well */
1959 info->status.rates[ts.ts_final_idx].count++;
1960
1961 if (unlikely(ts.ts_status)) {
1962 sc->ll_stats.dot11ACKFailureCount++;
1963 if (ts.ts_status & AR5K_TXERR_FILT)
1964 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1965 } else {
1966 info->flags |= IEEE80211_TX_STAT_ACK;
1967 info->status.ack_signal = ts.ts_rssi;
1968 }
1969
1970 ieee80211_tx_status(sc->hw, skb);
1971 sc->tx_stats[txq->qnum].count++;
1972
1973 spin_lock(&sc->txbuflock);
1974 sc->tx_stats[txq->qnum].len--;
1975 list_move_tail(&bf->list, &sc->txbuf);
1976 sc->txbuf_len++;
1977 spin_unlock(&sc->txbuflock);
1978 }
1979 if (likely(list_empty(&txq->q)))
1980 txq->link = NULL;
1981 spin_unlock(&txq->lock);
1982 if (sc->txbuf_len > ATH_TXBUF / 5)
1983 ieee80211_wake_queues(sc->hw);
1984 }
1985
1986 static void
1987 ath5k_tasklet_tx(unsigned long data)
1988 {
1989 int i;
1990 struct ath5k_softc *sc = (void *)data;
1991
1992 for (i=0; i < AR5K_NUM_TX_QUEUES; i++)
1993 if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i)))
1994 ath5k_tx_processq(sc, &sc->txqs[i]);
1995 }
1996
1997
1998 /*****************\
1999 * Beacon handling *
2000 \*****************/
2001
2002 /*
2003 * Setup the beacon frame for transmit.
2004 */
2005 static int
2006 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
2007 {
2008 struct sk_buff *skb = bf->skb;
2009 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2010 struct ath5k_hw *ah = sc->ah;
2011 struct ath5k_desc *ds;
2012 int ret = 0;
2013 u8 antenna;
2014 u32 flags;
2015
2016 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
2017 PCI_DMA_TODEVICE);
2018 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
2019 "skbaddr %llx\n", skb, skb->data, skb->len,
2020 (unsigned long long)bf->skbaddr);
2021 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
2022 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
2023 return -EIO;
2024 }
2025
2026 ds = bf->desc;
2027 antenna = ah->ah_tx_ant;
2028
2029 flags = AR5K_TXDESC_NOACK;
2030 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
2031 ds->ds_link = bf->daddr; /* self-linked */
2032 flags |= AR5K_TXDESC_VEOL;
2033 } else
2034 ds->ds_link = 0;
2035
2036 /*
2037 * If we use multiple antennas on AP and use
2038 * the Sectored AP scenario, switch antenna every
2039 * 4 beacons to make sure everybody hears our AP.
2040 * When a client tries to associate, hw will keep
2041 * track of the tx antenna to be used for this client
2042 * automaticaly, based on ACKed packets.
2043 *
2044 * Note: AP still listens and transmits RTS on the
2045 * default antenna which is supposed to be an omni.
2046 *
2047 * Note2: On sectored scenarios it's possible to have
2048 * multiple antennas (1omni -the default- and 14 sectors)
2049 * so if we choose to actually support this mode we need
2050 * to allow user to set how many antennas we have and tweak
2051 * the code below to send beacons on all of them.
2052 */
2053 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
2054 antenna = sc->bsent & 4 ? 2 : 1;
2055
2056
2057 /* FIXME: If we are in g mode and rate is a CCK rate
2058 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
2059 * from tx power (value is in dB units already) */
2060 ds->ds_data = bf->skbaddr;
2061 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
2062 ieee80211_get_hdrlen_from_skb(skb),
2063 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
2064 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2065 1, AR5K_TXKEYIX_INVALID,
2066 antenna, flags, 0, 0);
2067 if (ret)
2068 goto err_unmap;
2069
2070 return 0;
2071 err_unmap:
2072 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
2073 return ret;
2074 }
2075
2076 /*
2077 * Transmit a beacon frame at SWBA. Dynamic updates to the
2078 * frame contents are done as needed and the slot time is
2079 * also adjusted based on current state.
2080 *
2081 * This is called from software irq context (beacontq or restq
2082 * tasklets) or user context from ath5k_beacon_config.
2083 */
2084 static void
2085 ath5k_beacon_send(struct ath5k_softc *sc)
2086 {
2087 struct ath5k_buf *bf = sc->bbuf;
2088 struct ath5k_hw *ah = sc->ah;
2089 struct sk_buff *skb;
2090
2091 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
2092
2093 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
2094 sc->opmode == NL80211_IFTYPE_MONITOR)) {
2095 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2096 return;
2097 }
2098 /*
2099 * Check if the previous beacon has gone out. If
2100 * not don't don't try to post another, skip this
2101 * period and wait for the next. Missed beacons
2102 * indicate a problem and should not occur. If we
2103 * miss too many consecutive beacons reset the device.
2104 */
2105 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2106 sc->bmisscount++;
2107 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2108 "missed %u consecutive beacons\n", sc->bmisscount);
2109 if (sc->bmisscount > 10) { /* NB: 10 is a guess */
2110 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2111 "stuck beacon time (%u missed)\n",
2112 sc->bmisscount);
2113 tasklet_schedule(&sc->restq);
2114 }
2115 return;
2116 }
2117 if (unlikely(sc->bmisscount != 0)) {
2118 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2119 "resume beacon xmit after %u misses\n",
2120 sc->bmisscount);
2121 sc->bmisscount = 0;
2122 }
2123
2124 /*
2125 * Stop any current dma and put the new frame on the queue.
2126 * This should never fail since we check above that no frames
2127 * are still pending on the queue.
2128 */
2129 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2130 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
2131 /* NB: hw still stops DMA, so proceed */
2132 }
2133
2134 /* refresh the beacon for AP mode */
2135 if (sc->opmode == NL80211_IFTYPE_AP)
2136 ath5k_beacon_update(sc->hw, sc->vif);
2137
2138 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
2139 ath5k_hw_start_tx_dma(ah, sc->bhalq);
2140 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
2141 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2142
2143 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
2144 while (skb) {
2145 ath5k_tx_queue(sc->hw, skb, sc->cabq);
2146 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
2147 }
2148
2149 sc->bsent++;
2150 }
2151
2152
2153 /**
2154 * ath5k_beacon_update_timers - update beacon timers
2155 *
2156 * @sc: struct ath5k_softc pointer we are operating on
2157 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2158 * beacon timer update based on the current HW TSF.
2159 *
2160 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2161 * of a received beacon or the current local hardware TSF and write it to the
2162 * beacon timer registers.
2163 *
2164 * This is called in a variety of situations, e.g. when a beacon is received,
2165 * when a TSF update has been detected, but also when an new IBSS is created or
2166 * when we otherwise know we have to update the timers, but we keep it in this
2167 * function to have it all together in one place.
2168 */
2169 static void
2170 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
2171 {
2172 struct ath5k_hw *ah = sc->ah;
2173 u32 nexttbtt, intval, hw_tu, bc_tu;
2174 u64 hw_tsf;
2175
2176 intval = sc->bintval & AR5K_BEACON_PERIOD;
2177 if (WARN_ON(!intval))
2178 return;
2179
2180 /* beacon TSF converted to TU */
2181 bc_tu = TSF_TO_TU(bc_tsf);
2182
2183 /* current TSF converted to TU */
2184 hw_tsf = ath5k_hw_get_tsf64(ah);
2185 hw_tu = TSF_TO_TU(hw_tsf);
2186
2187 #define FUDGE 3
2188 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2189 if (bc_tsf == -1) {
2190 /*
2191 * no beacons received, called internally.
2192 * just need to refresh timers based on HW TSF.
2193 */
2194 nexttbtt = roundup(hw_tu + FUDGE, intval);
2195 } else if (bc_tsf == 0) {
2196 /*
2197 * no beacon received, probably called by ath5k_reset_tsf().
2198 * reset TSF to start with 0.
2199 */
2200 nexttbtt = intval;
2201 intval |= AR5K_BEACON_RESET_TSF;
2202 } else if (bc_tsf > hw_tsf) {
2203 /*
2204 * beacon received, SW merge happend but HW TSF not yet updated.
2205 * not possible to reconfigure timers yet, but next time we
2206 * receive a beacon with the same BSSID, the hardware will
2207 * automatically update the TSF and then we need to reconfigure
2208 * the timers.
2209 */
2210 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2211 "need to wait for HW TSF sync\n");
2212 return;
2213 } else {
2214 /*
2215 * most important case for beacon synchronization between STA.
2216 *
2217 * beacon received and HW TSF has been already updated by HW.
2218 * update next TBTT based on the TSF of the beacon, but make
2219 * sure it is ahead of our local TSF timer.
2220 */
2221 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2222 }
2223 #undef FUDGE
2224
2225 sc->nexttbtt = nexttbtt;
2226
2227 intval |= AR5K_BEACON_ENA;
2228 ath5k_hw_init_beacon(ah, nexttbtt, intval);
2229
2230 /*
2231 * debugging output last in order to preserve the time critical aspect
2232 * of this function
2233 */
2234 if (bc_tsf == -1)
2235 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2236 "reconfigured timers based on HW TSF\n");
2237 else if (bc_tsf == 0)
2238 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2239 "reset HW TSF and timers\n");
2240 else
2241 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2242 "updated timers based on beacon TSF\n");
2243
2244 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2245 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2246 (unsigned long long) bc_tsf,
2247 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2248 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2249 intval & AR5K_BEACON_PERIOD,
2250 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2251 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2252 }
2253
2254
2255 /**
2256 * ath5k_beacon_config - Configure the beacon queues and interrupts
2257 *
2258 * @sc: struct ath5k_softc pointer we are operating on
2259 *
2260 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2261 * interrupts to detect TSF updates only.
2262 */
2263 static void
2264 ath5k_beacon_config(struct ath5k_softc *sc)
2265 {
2266 struct ath5k_hw *ah = sc->ah;
2267 unsigned long flags;
2268
2269 spin_lock_irqsave(&sc->block, flags);
2270 sc->bmisscount = 0;
2271 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2272
2273 if (sc->enable_beacon) {
2274 /*
2275 * In IBSS mode we use a self-linked tx descriptor and let the
2276 * hardware send the beacons automatically. We have to load it
2277 * only once here.
2278 * We use the SWBA interrupt only to keep track of the beacon
2279 * timers in order to detect automatic TSF updates.
2280 */
2281 ath5k_beaconq_config(sc);
2282
2283 sc->imask |= AR5K_INT_SWBA;
2284
2285 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2286 if (ath5k_hw_hasveol(ah))
2287 ath5k_beacon_send(sc);
2288 } else
2289 ath5k_beacon_update_timers(sc, -1);
2290 } else {
2291 ath5k_hw_stop_tx_dma(sc->ah, sc->bhalq);
2292 }
2293
2294 ath5k_hw_set_imr(ah, sc->imask);
2295 mmiowb();
2296 spin_unlock_irqrestore(&sc->block, flags);
2297 }
2298
2299 static void ath5k_tasklet_beacon(unsigned long data)
2300 {
2301 struct ath5k_softc *sc = (struct ath5k_softc *) data;
2302
2303 /*
2304 * Software beacon alert--time to send a beacon.
2305 *
2306 * In IBSS mode we use this interrupt just to
2307 * keep track of the next TBTT (target beacon
2308 * transmission time) in order to detect wether
2309 * automatic TSF updates happened.
2310 */
2311 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2312 /* XXX: only if VEOL suppported */
2313 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
2314 sc->nexttbtt += sc->bintval;
2315 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2316 "SWBA nexttbtt: %x hw_tu: %x "
2317 "TSF: %llx\n",
2318 sc->nexttbtt,
2319 TSF_TO_TU(tsf),
2320 (unsigned long long) tsf);
2321 } else {
2322 spin_lock(&sc->block);
2323 ath5k_beacon_send(sc);
2324 spin_unlock(&sc->block);
2325 }
2326 }
2327
2328
2329 /********************\
2330 * Interrupt handling *
2331 \********************/
2332
2333 static int
2334 ath5k_init(struct ath5k_softc *sc)
2335 {
2336 struct ath5k_hw *ah = sc->ah;
2337 int ret, i;
2338
2339 mutex_lock(&sc->lock);
2340
2341 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2342
2343 /*
2344 * Stop anything previously setup. This is safe
2345 * no matter this is the first time through or not.
2346 */
2347 ath5k_stop_locked(sc);
2348
2349 /*
2350 * The basic interface to setting the hardware in a good
2351 * state is ``reset''. On return the hardware is known to
2352 * be powered up and with interrupts disabled. This must
2353 * be followed by initialization of the appropriate bits
2354 * and then setup of the interrupt mask.
2355 */
2356 sc->curchan = sc->hw->conf.channel;
2357 sc->curband = &sc->sbands[sc->curchan->band];
2358 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2359 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2360 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_SWI;
2361 ret = ath5k_reset(sc, NULL);
2362 if (ret)
2363 goto done;
2364
2365 ath5k_rfkill_hw_start(ah);
2366
2367 /*
2368 * Reset the key cache since some parts do not reset the
2369 * contents on initial power up or resume from suspend.
2370 */
2371 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
2372 ath5k_hw_reset_key(ah, i);
2373
2374 /* Set ack to be sent at low bit-rates */
2375 ath5k_hw_set_ack_bitrate_high(ah, false);
2376
2377 /* Set PHY calibration inteval */
2378 ah->ah_cal_intval = ath5k_calinterval;
2379
2380 ret = 0;
2381 done:
2382 mmiowb();
2383 mutex_unlock(&sc->lock);
2384 return ret;
2385 }
2386
2387 static int
2388 ath5k_stop_locked(struct ath5k_softc *sc)
2389 {
2390 struct ath5k_hw *ah = sc->ah;
2391
2392 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2393 test_bit(ATH_STAT_INVALID, sc->status));
2394
2395 /*
2396 * Shutdown the hardware and driver:
2397 * stop output from above
2398 * disable interrupts
2399 * turn off timers
2400 * turn off the radio
2401 * clear transmit machinery
2402 * clear receive machinery
2403 * drain and release tx queues
2404 * reclaim beacon resources
2405 * power down hardware
2406 *
2407 * Note that some of this work is not possible if the
2408 * hardware is gone (invalid).
2409 */
2410 ieee80211_stop_queues(sc->hw);
2411
2412 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2413 ath5k_led_off(sc);
2414 ath5k_hw_set_imr(ah, 0);
2415 synchronize_irq(sc->pdev->irq);
2416 }
2417 ath5k_txq_cleanup(sc);
2418 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2419 ath5k_rx_stop(sc);
2420 ath5k_hw_phy_disable(ah);
2421 } else
2422 sc->rxlink = NULL;
2423
2424 return 0;
2425 }
2426
2427 /*
2428 * Stop the device, grabbing the top-level lock to protect
2429 * against concurrent entry through ath5k_init (which can happen
2430 * if another thread does a system call and the thread doing the
2431 * stop is preempted).
2432 */
2433 static int
2434 ath5k_stop_hw(struct ath5k_softc *sc)
2435 {
2436 int ret;
2437
2438 mutex_lock(&sc->lock);
2439 ret = ath5k_stop_locked(sc);
2440 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2441 /*
2442 * Don't set the card in full sleep mode!
2443 *
2444 * a) When the device is in this state it must be carefully
2445 * woken up or references to registers in the PCI clock
2446 * domain may freeze the bus (and system). This varies
2447 * by chip and is mostly an issue with newer parts
2448 * (madwifi sources mentioned srev >= 0x78) that go to
2449 * sleep more quickly.
2450 *
2451 * b) On older chips full sleep results a weird behaviour
2452 * during wakeup. I tested various cards with srev < 0x78
2453 * and they don't wake up after module reload, a second
2454 * module reload is needed to bring the card up again.
2455 *
2456 * Until we figure out what's going on don't enable
2457 * full chip reset on any chip (this is what Legacy HAL
2458 * and Sam's HAL do anyway). Instead Perform a full reset
2459 * on the device (same as initial state after attach) and
2460 * leave it idle (keep MAC/BB on warm reset) */
2461 ret = ath5k_hw_on_hold(sc->ah);
2462
2463 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2464 "putting device to sleep\n");
2465 }
2466 ath5k_txbuf_free(sc, sc->bbuf);
2467
2468 mmiowb();
2469 mutex_unlock(&sc->lock);
2470
2471 tasklet_kill(&sc->rxtq);
2472 tasklet_kill(&sc->txtq);
2473 tasklet_kill(&sc->restq);
2474 tasklet_kill(&sc->calib);
2475 tasklet_kill(&sc->beacontq);
2476
2477 ath5k_rfkill_hw_stop(sc->ah);
2478
2479 return ret;
2480 }
2481
2482 static irqreturn_t
2483 ath5k_intr(int irq, void *dev_id)
2484 {
2485 struct ath5k_softc *sc = dev_id;
2486 struct ath5k_hw *ah = sc->ah;
2487 enum ath5k_int status;
2488 unsigned int counter = 1000;
2489
2490 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2491 !ath5k_hw_is_intr_pending(ah)))
2492 return IRQ_NONE;
2493
2494 do {
2495 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2496 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2497 status, sc->imask);
2498 if (unlikely(status & AR5K_INT_FATAL)) {
2499 /*
2500 * Fatal errors are unrecoverable.
2501 * Typically these are caused by DMA errors.
2502 */
2503 tasklet_schedule(&sc->restq);
2504 } else if (unlikely(status & AR5K_INT_RXORN)) {
2505 tasklet_schedule(&sc->restq);
2506 } else {
2507 if (status & AR5K_INT_SWBA) {
2508 tasklet_hi_schedule(&sc->beacontq);
2509 }
2510 if (status & AR5K_INT_RXEOL) {
2511 /*
2512 * NB: the hardware should re-read the link when
2513 * RXE bit is written, but it doesn't work at
2514 * least on older hardware revs.
2515 */
2516 sc->rxlink = NULL;
2517 }
2518 if (status & AR5K_INT_TXURN) {
2519 /* bump tx trigger level */
2520 ath5k_hw_update_tx_triglevel(ah, true);
2521 }
2522 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
2523 tasklet_schedule(&sc->rxtq);
2524 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2525 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
2526 tasklet_schedule(&sc->txtq);
2527 if (status & AR5K_INT_BMISS) {
2528 /* TODO */
2529 }
2530 if (status & AR5K_INT_SWI) {
2531 tasklet_schedule(&sc->calib);
2532 }
2533 if (status & AR5K_INT_MIB) {
2534 /*
2535 * These stats are also used for ANI i think
2536 * so how about updating them more often ?
2537 */
2538 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
2539 }
2540 if (status & AR5K_INT_GPIO)
2541 tasklet_schedule(&sc->rf_kill.toggleq);
2542
2543 }
2544 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
2545
2546 if (unlikely(!counter))
2547 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2548
2549 ath5k_hw_calibration_poll(ah);
2550
2551 return IRQ_HANDLED;
2552 }
2553
2554 static void
2555 ath5k_tasklet_reset(unsigned long data)
2556 {
2557 struct ath5k_softc *sc = (void *)data;
2558
2559 ath5k_reset_wake(sc);
2560 }
2561
2562 /*
2563 * Periodically recalibrate the PHY to account
2564 * for temperature/environment changes.
2565 */
2566 static void
2567 ath5k_tasklet_calibrate(unsigned long data)
2568 {
2569 struct ath5k_softc *sc = (void *)data;
2570 struct ath5k_hw *ah = sc->ah;
2571
2572 /* Only full calibration for now */
2573 if (ah->ah_swi_mask != AR5K_SWI_FULL_CALIBRATION)
2574 return;
2575
2576 /* Stop queues so that calibration
2577 * doesn't interfere with tx */
2578 ieee80211_stop_queues(sc->hw);
2579
2580 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2581 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2582 sc->curchan->hw_value);
2583
2584 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2585 /*
2586 * Rfgain is out of bounds, reset the chip
2587 * to load new gain values.
2588 */
2589 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2590 ath5k_reset_wake(sc);
2591 }
2592 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2593 ATH5K_ERR(sc, "calibration of channel %u failed\n",
2594 ieee80211_frequency_to_channel(
2595 sc->curchan->center_freq));
2596
2597 ah->ah_swi_mask = 0;
2598
2599 /* Wake queues */
2600 ieee80211_wake_queues(sc->hw);
2601
2602 }
2603
2604
2605 /********************\
2606 * Mac80211 functions *
2607 \********************/
2608
2609 static int
2610 ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2611 {
2612 struct ath5k_softc *sc = hw->priv;
2613
2614 return ath5k_tx_queue(hw, skb, sc->txq);
2615 }
2616
2617 static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
2618 struct ath5k_txq *txq)
2619 {
2620 struct ath5k_softc *sc = hw->priv;
2621 struct ath5k_buf *bf;
2622 unsigned long flags;
2623 int hdrlen;
2624 int padsize;
2625
2626 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2627
2628 if (sc->opmode == NL80211_IFTYPE_MONITOR)
2629 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2630
2631 /*
2632 * the hardware expects the header padded to 4 byte boundaries
2633 * if this is not the case we add the padding after the header
2634 */
2635 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2636 padsize = ath5k_pad_size(hdrlen);
2637 if (padsize) {
2638
2639 if (skb_headroom(skb) < padsize) {
2640 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
2641 " headroom to pad %d\n", hdrlen, padsize);
2642 goto drop_packet;
2643 }
2644 skb_push(skb, padsize);
2645 memmove(skb->data, skb->data+padsize, hdrlen);
2646 }
2647
2648 spin_lock_irqsave(&sc->txbuflock, flags);
2649 if (list_empty(&sc->txbuf)) {
2650 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2651 spin_unlock_irqrestore(&sc->txbuflock, flags);
2652 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
2653 goto drop_packet;
2654 }
2655 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2656 list_del(&bf->list);
2657 sc->txbuf_len--;
2658 if (list_empty(&sc->txbuf))
2659 ieee80211_stop_queues(hw);
2660 spin_unlock_irqrestore(&sc->txbuflock, flags);
2661
2662 bf->skb = skb;
2663
2664 if (ath5k_txbuf_setup(sc, bf, txq)) {
2665 bf->skb = NULL;
2666 spin_lock_irqsave(&sc->txbuflock, flags);
2667 list_add_tail(&bf->list, &sc->txbuf);
2668 sc->txbuf_len++;
2669 spin_unlock_irqrestore(&sc->txbuflock, flags);
2670 goto drop_packet;
2671 }
2672 return NETDEV_TX_OK;
2673
2674 drop_packet:
2675 dev_kfree_skb_any(skb);
2676 return NETDEV_TX_OK;
2677 }
2678
2679 /*
2680 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2681 * and change to the given channel.
2682 */
2683 static int
2684 ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan)
2685 {
2686 struct ath5k_hw *ah = sc->ah;
2687 int ret;
2688
2689 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
2690
2691 if (chan) {
2692 ath5k_hw_set_imr(ah, 0);
2693 ath5k_txq_cleanup(sc);
2694 ath5k_rx_stop(sc);
2695
2696 sc->curchan = chan;
2697 sc->curband = &sc->sbands[chan->band];
2698 }
2699 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL);
2700 if (ret) {
2701 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2702 goto err;
2703 }
2704
2705 ret = ath5k_rx_start(sc);
2706 if (ret) {
2707 ATH5K_ERR(sc, "can't start recv logic\n");
2708 goto err;
2709 }
2710
2711 /*
2712 * Change channels and update the h/w rate map if we're switching;
2713 * e.g. 11a to 11b/g.
2714 *
2715 * We may be doing a reset in response to an ioctl that changes the
2716 * channel so update any state that might change as a result.
2717 *
2718 * XXX needed?
2719 */
2720 /* ath5k_chan_change(sc, c); */
2721
2722 ath5k_beacon_config(sc);
2723 /* intrs are enabled by ath5k_beacon_config */
2724
2725 return 0;
2726 err:
2727 return ret;
2728 }
2729
2730 static int
2731 ath5k_reset_wake(struct ath5k_softc *sc)
2732 {
2733 int ret;
2734
2735 ret = ath5k_reset(sc, sc->curchan);
2736 if (!ret)
2737 ieee80211_wake_queues(sc->hw);
2738
2739 return ret;
2740 }
2741
2742 static int ath5k_start(struct ieee80211_hw *hw)
2743 {
2744 return ath5k_init(hw->priv);
2745 }
2746
2747 static void ath5k_stop(struct ieee80211_hw *hw)
2748 {
2749 ath5k_stop_hw(hw->priv);
2750 }
2751
2752 static int ath5k_add_interface(struct ieee80211_hw *hw,
2753 struct ieee80211_if_init_conf *conf)
2754 {
2755 struct ath5k_softc *sc = hw->priv;
2756 int ret;
2757
2758 mutex_lock(&sc->lock);
2759 if (sc->vif) {
2760 ret = 0;
2761 goto end;
2762 }
2763
2764 sc->vif = conf->vif;
2765
2766 switch (conf->type) {
2767 case NL80211_IFTYPE_AP:
2768 case NL80211_IFTYPE_STATION:
2769 case NL80211_IFTYPE_ADHOC:
2770 case NL80211_IFTYPE_MESH_POINT:
2771 case NL80211_IFTYPE_MONITOR:
2772 sc->opmode = conf->type;
2773 break;
2774 default:
2775 ret = -EOPNOTSUPP;
2776 goto end;
2777 }
2778
2779 ath5k_hw_set_lladdr(sc->ah, conf->mac_addr);
2780 ath5k_mode_setup(sc);
2781
2782 ret = 0;
2783 end:
2784 mutex_unlock(&sc->lock);
2785 return ret;
2786 }
2787
2788 static void
2789 ath5k_remove_interface(struct ieee80211_hw *hw,
2790 struct ieee80211_if_init_conf *conf)
2791 {
2792 struct ath5k_softc *sc = hw->priv;
2793 u8 mac[ETH_ALEN] = {};
2794
2795 mutex_lock(&sc->lock);
2796 if (sc->vif != conf->vif)
2797 goto end;
2798
2799 ath5k_hw_set_lladdr(sc->ah, mac);
2800 sc->vif = NULL;
2801 end:
2802 mutex_unlock(&sc->lock);
2803 }
2804
2805 /*
2806 * TODO: Phy disable/diversity etc
2807 */
2808 static int
2809 ath5k_config(struct ieee80211_hw *hw, u32 changed)
2810 {
2811 struct ath5k_softc *sc = hw->priv;
2812 struct ath5k_hw *ah = sc->ah;
2813 struct ieee80211_conf *conf = &hw->conf;
2814 int ret = 0;
2815
2816 mutex_lock(&sc->lock);
2817
2818 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2819 ret = ath5k_chan_set(sc, conf->channel);
2820 if (ret < 0)
2821 goto unlock;
2822 }
2823
2824 if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
2825 (sc->power_level != conf->power_level)) {
2826 sc->power_level = conf->power_level;
2827
2828 /* Half dB steps */
2829 ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2));
2830 }
2831
2832 /* TODO:
2833 * 1) Move this on config_interface and handle each case
2834 * separately eg. when we have only one STA vif, use
2835 * AR5K_ANTMODE_SINGLE_AP
2836 *
2837 * 2) Allow the user to change antenna mode eg. when only
2838 * one antenna is present
2839 *
2840 * 3) Allow the user to set default/tx antenna when possible
2841 *
2842 * 4) Default mode should handle 90% of the cases, together
2843 * with fixed a/b and single AP modes we should be able to
2844 * handle 99%. Sectored modes are extreme cases and i still
2845 * haven't found a usage for them. If we decide to support them,
2846 * then we must allow the user to set how many tx antennas we
2847 * have available
2848 */
2849 ath5k_hw_set_antenna_mode(ah, AR5K_ANTMODE_DEFAULT);
2850
2851 unlock:
2852 mutex_unlock(&sc->lock);
2853 return ret;
2854 }
2855
2856 #define SUPPORTED_FIF_FLAGS \
2857 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2858 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2859 FIF_BCN_PRBRESP_PROMISC
2860 /*
2861 * o always accept unicast, broadcast, and multicast traffic
2862 * o multicast traffic for all BSSIDs will be enabled if mac80211
2863 * says it should be
2864 * o maintain current state of phy ofdm or phy cck error reception.
2865 * If the hardware detects any of these type of errors then
2866 * ath5k_hw_get_rx_filter() will pass to us the respective
2867 * hardware filters to be able to receive these type of frames.
2868 * o probe request frames are accepted only when operating in
2869 * hostap, adhoc, or monitor modes
2870 * o enable promiscuous mode according to the interface state
2871 * o accept beacons:
2872 * - when operating in adhoc mode so the 802.11 layer creates
2873 * node table entries for peers,
2874 * - when operating in station mode for collecting rssi data when
2875 * the station is otherwise quiet, or
2876 * - when scanning
2877 */
2878 static void ath5k_configure_filter(struct ieee80211_hw *hw,
2879 unsigned int changed_flags,
2880 unsigned int *new_flags,
2881 int mc_count, struct dev_mc_list *mclist)
2882 {
2883 struct ath5k_softc *sc = hw->priv;
2884 struct ath5k_hw *ah = sc->ah;
2885 u32 mfilt[2], val, rfilt;
2886 u8 pos;
2887 int i;
2888
2889 mfilt[0] = 0;
2890 mfilt[1] = 0;
2891
2892 /* Only deal with supported flags */
2893 changed_flags &= SUPPORTED_FIF_FLAGS;
2894 *new_flags &= SUPPORTED_FIF_FLAGS;
2895
2896 /* If HW detects any phy or radar errors, leave those filters on.
2897 * Also, always enable Unicast, Broadcasts and Multicast
2898 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2899 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2900 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2901 AR5K_RX_FILTER_MCAST);
2902
2903 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2904 if (*new_flags & FIF_PROMISC_IN_BSS) {
2905 rfilt |= AR5K_RX_FILTER_PROM;
2906 __set_bit(ATH_STAT_PROMISC, sc->status);
2907 } else {
2908 __clear_bit(ATH_STAT_PROMISC, sc->status);
2909 }
2910 }
2911
2912 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2913 if (*new_flags & FIF_ALLMULTI) {
2914 mfilt[0] = ~0;
2915 mfilt[1] = ~0;
2916 } else {
2917 for (i = 0; i < mc_count; i++) {
2918 if (!mclist)
2919 break;
2920 /* calculate XOR of eight 6-bit values */
2921 val = get_unaligned_le32(mclist->dmi_addr + 0);
2922 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2923 val = get_unaligned_le32(mclist->dmi_addr + 3);
2924 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2925 pos &= 0x3f;
2926 mfilt[pos / 32] |= (1 << (pos % 32));
2927 /* XXX: we might be able to just do this instead,
2928 * but not sure, needs testing, if we do use this we'd
2929 * neet to inform below to not reset the mcast */
2930 /* ath5k_hw_set_mcast_filterindex(ah,
2931 * mclist->dmi_addr[5]); */
2932 mclist = mclist->next;
2933 }
2934 }
2935
2936 /* This is the best we can do */
2937 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2938 rfilt |= AR5K_RX_FILTER_PHYERR;
2939
2940 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2941 * and probes for any BSSID, this needs testing */
2942 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2943 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2944
2945 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2946 * set we should only pass on control frames for this
2947 * station. This needs testing. I believe right now this
2948 * enables *all* control frames, which is OK.. but
2949 * but we should see if we can improve on granularity */
2950 if (*new_flags & FIF_CONTROL)
2951 rfilt |= AR5K_RX_FILTER_CONTROL;
2952
2953 /* Additional settings per mode -- this is per ath5k */
2954
2955 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2956
2957 if (sc->opmode == NL80211_IFTYPE_MONITOR)
2958 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2959 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
2960 if (sc->opmode != NL80211_IFTYPE_STATION)
2961 rfilt |= AR5K_RX_FILTER_PROBEREQ;
2962 if (sc->opmode != NL80211_IFTYPE_AP &&
2963 sc->opmode != NL80211_IFTYPE_MESH_POINT &&
2964 test_bit(ATH_STAT_PROMISC, sc->status))
2965 rfilt |= AR5K_RX_FILTER_PROM;
2966 if ((sc->opmode == NL80211_IFTYPE_STATION && sc->assoc) ||
2967 sc->opmode == NL80211_IFTYPE_ADHOC ||
2968 sc->opmode == NL80211_IFTYPE_AP)
2969 rfilt |= AR5K_RX_FILTER_BEACON;
2970 if (sc->opmode == NL80211_IFTYPE_MESH_POINT)
2971 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2972 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
2973
2974 /* Set filters */
2975 ath5k_hw_set_rx_filter(ah, rfilt);
2976
2977 /* Set multicast bits */
2978 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
2979 /* Set the cached hw filter flags, this will alter actually
2980 * be set in HW */
2981 sc->filter_flags = rfilt;
2982 }
2983
2984 static int
2985 ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2986 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
2987 struct ieee80211_key_conf *key)
2988 {
2989 struct ath5k_softc *sc = hw->priv;
2990 int ret = 0;
2991
2992 if (modparam_nohwcrypt)
2993 return -EOPNOTSUPP;
2994
2995 if (sc->opmode == NL80211_IFTYPE_AP)
2996 return -EOPNOTSUPP;
2997
2998 switch (key->alg) {
2999 case ALG_WEP:
3000 case ALG_TKIP:
3001 break;
3002 case ALG_CCMP:
3003 return -EOPNOTSUPP;
3004 default:
3005 WARN_ON(1);
3006 return -EINVAL;
3007 }
3008
3009 mutex_lock(&sc->lock);
3010
3011 switch (cmd) {
3012 case SET_KEY:
3013 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key,
3014 sta ? sta->addr : NULL);
3015 if (ret) {
3016 ATH5K_ERR(sc, "can't set the key\n");
3017 goto unlock;
3018 }
3019 __set_bit(key->keyidx, sc->keymap);
3020 key->hw_key_idx = key->keyidx;
3021 key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV |
3022 IEEE80211_KEY_FLAG_GENERATE_MMIC);
3023 break;
3024 case DISABLE_KEY:
3025 ath5k_hw_reset_key(sc->ah, key->keyidx);
3026 __clear_bit(key->keyidx, sc->keymap);
3027 break;
3028 default:
3029 ret = -EINVAL;
3030 goto unlock;
3031 }
3032
3033 unlock:
3034 mmiowb();
3035 mutex_unlock(&sc->lock);
3036 return ret;
3037 }
3038
3039 static int
3040 ath5k_get_stats(struct ieee80211_hw *hw,
3041 struct ieee80211_low_level_stats *stats)
3042 {
3043 struct ath5k_softc *sc = hw->priv;
3044 struct ath5k_hw *ah = sc->ah;
3045
3046 /* Force update */
3047 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
3048
3049 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
3050
3051 return 0;
3052 }
3053
3054 static int
3055 ath5k_get_tx_stats(struct ieee80211_hw *hw,
3056 struct ieee80211_tx_queue_stats *stats)
3057 {
3058 struct ath5k_softc *sc = hw->priv;
3059
3060 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
3061
3062 return 0;
3063 }
3064
3065 static u64
3066 ath5k_get_tsf(struct ieee80211_hw *hw)
3067 {
3068 struct ath5k_softc *sc = hw->priv;
3069
3070 return ath5k_hw_get_tsf64(sc->ah);
3071 }
3072
3073 static void
3074 ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3075 {
3076 struct ath5k_softc *sc = hw->priv;
3077
3078 ath5k_hw_set_tsf64(sc->ah, tsf);
3079 }
3080
3081 static void
3082 ath5k_reset_tsf(struct ieee80211_hw *hw)
3083 {
3084 struct ath5k_softc *sc = hw->priv;
3085
3086 /*
3087 * in IBSS mode we need to update the beacon timers too.
3088 * this will also reset the TSF if we call it with 0
3089 */
3090 if (sc->opmode == NL80211_IFTYPE_ADHOC)
3091 ath5k_beacon_update_timers(sc, 0);
3092 else
3093 ath5k_hw_reset_tsf(sc->ah);
3094 }
3095
3096 /*
3097 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
3098 * this is called only once at config_bss time, for AP we do it every
3099 * SWBA interrupt so that the TIM will reflect buffered frames.
3100 *
3101 * Called with the beacon lock.
3102 */
3103 static int
3104 ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
3105 {
3106 int ret;
3107 struct ath5k_softc *sc = hw->priv;
3108 struct sk_buff *skb;
3109
3110 if (WARN_ON(!vif)) {
3111 ret = -EINVAL;
3112 goto out;
3113 }
3114
3115 skb = ieee80211_beacon_get(hw, vif);
3116
3117 if (!skb) {
3118 ret = -ENOMEM;
3119 goto out;
3120 }
3121
3122 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3123
3124 ath5k_txbuf_free(sc, sc->bbuf);
3125 sc->bbuf->skb = skb;
3126 ret = ath5k_beacon_setup(sc, sc->bbuf);
3127 if (ret)
3128 sc->bbuf->skb = NULL;
3129 out:
3130 return ret;
3131 }
3132
3133 static void
3134 set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3135 {
3136 struct ath5k_softc *sc = hw->priv;
3137 struct ath5k_hw *ah = sc->ah;
3138 u32 rfilt;
3139 rfilt = ath5k_hw_get_rx_filter(ah);
3140 if (enable)
3141 rfilt |= AR5K_RX_FILTER_BEACON;
3142 else
3143 rfilt &= ~AR5K_RX_FILTER_BEACON;
3144 ath5k_hw_set_rx_filter(ah, rfilt);
3145 sc->filter_flags = rfilt;
3146 }
3147
3148 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3149 struct ieee80211_vif *vif,
3150 struct ieee80211_bss_conf *bss_conf,
3151 u32 changes)
3152 {
3153 struct ath5k_softc *sc = hw->priv;
3154 struct ath5k_hw *ah = sc->ah;
3155 unsigned long flags;
3156
3157 mutex_lock(&sc->lock);
3158 if (WARN_ON(sc->vif != vif))
3159 goto unlock;
3160
3161 if (changes & BSS_CHANGED_BSSID) {
3162 /* Cache for later use during resets */
3163 memcpy(ah->ah_bssid, bss_conf->bssid, ETH_ALEN);
3164 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
3165 * a clean way of letting us retrieve this yet. */
3166 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
3167 mmiowb();
3168 }
3169
3170 if (changes & BSS_CHANGED_BEACON_INT)
3171 sc->bintval = bss_conf->beacon_int;
3172
3173 if (changes & BSS_CHANGED_ASSOC) {
3174 sc->assoc = bss_conf->assoc;
3175 if (sc->opmode == NL80211_IFTYPE_STATION)
3176 set_beacon_filter(hw, sc->assoc);
3177 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3178 AR5K_LED_ASSOC : AR5K_LED_INIT);
3179 }
3180
3181 if (changes & BSS_CHANGED_BEACON) {
3182 spin_lock_irqsave(&sc->block, flags);
3183 ath5k_beacon_update(hw, vif);
3184 spin_unlock_irqrestore(&sc->block, flags);
3185 }
3186
3187 if (changes & BSS_CHANGED_BEACON_ENABLED)
3188 sc->enable_beacon = bss_conf->enable_beacon;
3189
3190 if (changes & (BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED |
3191 BSS_CHANGED_BEACON_INT))
3192 ath5k_beacon_config(sc);
3193
3194 unlock:
3195 mutex_unlock(&sc->lock);
3196 }
3197
3198 static void ath5k_sw_scan_start(struct ieee80211_hw *hw)
3199 {
3200 struct ath5k_softc *sc = hw->priv;
3201 if (!sc->assoc)
3202 ath5k_hw_set_ledstate(sc->ah, AR5K_LED_SCAN);
3203 }
3204
3205 static void ath5k_sw_scan_complete(struct ieee80211_hw *hw)
3206 {
3207 struct ath5k_softc *sc = hw->priv;
3208 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3209 AR5K_LED_ASSOC : AR5K_LED_INIT);
3210 }
Linux kernel - Deliverables
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