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[deliverable/linux.git] / drivers / net / wireless / ath / ath5k / base.c
1 /*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
43 #include <linux/module.h>
44 #include <linux/delay.h>
45 #include <linux/hardirq.h>
46 #include <linux/if.h>
47 #include <linux/io.h>
48 #include <linux/netdevice.h>
49 #include <linux/cache.h>
50 #include <linux/ethtool.h>
51 #include <linux/uaccess.h>
52 #include <linux/slab.h>
53 #include <linux/etherdevice.h>
54
55 #include <net/ieee80211_radiotap.h>
56
57 #include <asm/unaligned.h>
58
59 #include "base.h"
60 #include "reg.h"
61 #include "debug.h"
62 #include "ani.h"
63
64 #define CREATE_TRACE_POINTS
65 #include "trace.h"
66
67 int ath5k_modparam_nohwcrypt;
68 module_param_named(nohwcrypt, ath5k_modparam_nohwcrypt, bool, S_IRUGO);
69 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
70
71 static int modparam_all_channels;
72 module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
73 MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
74
75 static int modparam_fastchanswitch;
76 module_param_named(fastchanswitch, modparam_fastchanswitch, bool, S_IRUGO);
77 MODULE_PARM_DESC(fastchanswitch, "Enable fast channel switching for AR2413/AR5413 radios.");
78
79
80 /* Module info */
81 MODULE_AUTHOR("Jiri Slaby");
82 MODULE_AUTHOR("Nick Kossifidis");
83 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
84 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
85 MODULE_LICENSE("Dual BSD/GPL");
86
87 static int ath5k_init(struct ieee80211_hw *hw);
88 static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan,
89 bool skip_pcu);
90
91 /* Known SREVs */
92 static const struct ath5k_srev_name srev_names[] = {
93 #ifdef CONFIG_ATHEROS_AR231X
94 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R2 },
95 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R7 },
96 { "2313", AR5K_VERSION_MAC, AR5K_SREV_AR2313_R8 },
97 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R6 },
98 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R7 },
99 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R1 },
100 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R2 },
101 #else
102 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
103 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
104 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
105 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
106 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
107 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
108 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
109 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
110 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
111 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
112 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
113 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
114 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
115 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
116 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
117 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
118 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
119 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
120 #endif
121 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
122 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
123 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
124 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
125 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
126 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
127 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
128 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
129 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
130 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
131 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
132 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
133 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
134 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
135 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
136 #ifdef CONFIG_ATHEROS_AR231X
137 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
138 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
139 #endif
140 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
141 };
142
143 static const struct ieee80211_rate ath5k_rates[] = {
144 { .bitrate = 10,
145 .hw_value = ATH5K_RATE_CODE_1M, },
146 { .bitrate = 20,
147 .hw_value = ATH5K_RATE_CODE_2M,
148 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
149 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
150 { .bitrate = 55,
151 .hw_value = ATH5K_RATE_CODE_5_5M,
152 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
153 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
154 { .bitrate = 110,
155 .hw_value = ATH5K_RATE_CODE_11M,
156 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
157 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
158 { .bitrate = 60,
159 .hw_value = ATH5K_RATE_CODE_6M,
160 .flags = 0 },
161 { .bitrate = 90,
162 .hw_value = ATH5K_RATE_CODE_9M,
163 .flags = 0 },
164 { .bitrate = 120,
165 .hw_value = ATH5K_RATE_CODE_12M,
166 .flags = 0 },
167 { .bitrate = 180,
168 .hw_value = ATH5K_RATE_CODE_18M,
169 .flags = 0 },
170 { .bitrate = 240,
171 .hw_value = ATH5K_RATE_CODE_24M,
172 .flags = 0 },
173 { .bitrate = 360,
174 .hw_value = ATH5K_RATE_CODE_36M,
175 .flags = 0 },
176 { .bitrate = 480,
177 .hw_value = ATH5K_RATE_CODE_48M,
178 .flags = 0 },
179 { .bitrate = 540,
180 .hw_value = ATH5K_RATE_CODE_54M,
181 .flags = 0 },
182 /* XR missing */
183 };
184
185 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
186 {
187 u64 tsf = ath5k_hw_get_tsf64(ah);
188
189 if ((tsf & 0x7fff) < rstamp)
190 tsf -= 0x8000;
191
192 return (tsf & ~0x7fff) | rstamp;
193 }
194
195 const char *
196 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
197 {
198 const char *name = "xxxxx";
199 unsigned int i;
200
201 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
202 if (srev_names[i].sr_type != type)
203 continue;
204
205 if ((val & 0xf0) == srev_names[i].sr_val)
206 name = srev_names[i].sr_name;
207
208 if ((val & 0xff) == srev_names[i].sr_val) {
209 name = srev_names[i].sr_name;
210 break;
211 }
212 }
213
214 return name;
215 }
216 static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
217 {
218 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
219 return ath5k_hw_reg_read(ah, reg_offset);
220 }
221
222 static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
223 {
224 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
225 ath5k_hw_reg_write(ah, val, reg_offset);
226 }
227
228 static const struct ath_ops ath5k_common_ops = {
229 .read = ath5k_ioread32,
230 .write = ath5k_iowrite32,
231 };
232
233 /***********************\
234 * Driver Initialization *
235 \***********************/
236
237 static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
238 {
239 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
240 struct ath5k_softc *sc = hw->priv;
241 struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah);
242
243 return ath_reg_notifier_apply(wiphy, request, regulatory);
244 }
245
246 /********************\
247 * Channel/mode setup *
248 \********************/
249
250 /*
251 * Returns true for the channel numbers used without all_channels modparam.
252 */
253 static bool ath5k_is_standard_channel(short chan, enum ieee80211_band band)
254 {
255 if (band == IEEE80211_BAND_2GHZ && chan <= 14)
256 return true;
257
258 return /* UNII 1,2 */
259 (((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
260 /* midband */
261 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
262 /* UNII-3 */
263 ((chan & 3) == 1 && chan >= 149 && chan <= 165) ||
264 /* 802.11j 5.030-5.080 GHz (20MHz) */
265 (chan == 8 || chan == 12 || chan == 16) ||
266 /* 802.11j 4.9GHz (20MHz) */
267 (chan == 184 || chan == 188 || chan == 192 || chan == 196));
268 }
269
270 static unsigned int
271 ath5k_setup_channels(struct ath5k_hw *ah, struct ieee80211_channel *channels,
272 unsigned int mode, unsigned int max)
273 {
274 unsigned int count, size, chfreq, freq, ch;
275 enum ieee80211_band band;
276
277 switch (mode) {
278 case AR5K_MODE_11A:
279 /* 1..220, but 2GHz frequencies are filtered by check_channel */
280 size = 220;
281 chfreq = CHANNEL_5GHZ;
282 band = IEEE80211_BAND_5GHZ;
283 break;
284 case AR5K_MODE_11B:
285 case AR5K_MODE_11G:
286 size = 26;
287 chfreq = CHANNEL_2GHZ;
288 band = IEEE80211_BAND_2GHZ;
289 break;
290 default:
291 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
292 return 0;
293 }
294
295 count = 0;
296 for (ch = 1; ch <= size && count < max; ch++) {
297 freq = ieee80211_channel_to_frequency(ch, band);
298
299 if (freq == 0) /* mapping failed - not a standard channel */
300 continue;
301
302 /* Check if channel is supported by the chipset */
303 if (!ath5k_channel_ok(ah, freq, chfreq))
304 continue;
305
306 if (!modparam_all_channels &&
307 !ath5k_is_standard_channel(ch, band))
308 continue;
309
310 /* Write channel info and increment counter */
311 channels[count].center_freq = freq;
312 channels[count].band = band;
313 switch (mode) {
314 case AR5K_MODE_11A:
315 case AR5K_MODE_11G:
316 channels[count].hw_value = chfreq | CHANNEL_OFDM;
317 break;
318 case AR5K_MODE_11B:
319 channels[count].hw_value = CHANNEL_B;
320 }
321
322 count++;
323 }
324
325 return count;
326 }
327
328 static void
329 ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
330 {
331 u8 i;
332
333 for (i = 0; i < AR5K_MAX_RATES; i++)
334 sc->rate_idx[b->band][i] = -1;
335
336 for (i = 0; i < b->n_bitrates; i++) {
337 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
338 if (b->bitrates[i].hw_value_short)
339 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
340 }
341 }
342
343 static int
344 ath5k_setup_bands(struct ieee80211_hw *hw)
345 {
346 struct ath5k_softc *sc = hw->priv;
347 struct ath5k_hw *ah = sc->ah;
348 struct ieee80211_supported_band *sband;
349 int max_c, count_c = 0;
350 int i;
351
352 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
353 max_c = ARRAY_SIZE(sc->channels);
354
355 /* 2GHz band */
356 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
357 sband->band = IEEE80211_BAND_2GHZ;
358 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
359
360 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
361 /* G mode */
362 memcpy(sband->bitrates, &ath5k_rates[0],
363 sizeof(struct ieee80211_rate) * 12);
364 sband->n_bitrates = 12;
365
366 sband->channels = sc->channels;
367 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
368 AR5K_MODE_11G, max_c);
369
370 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
371 count_c = sband->n_channels;
372 max_c -= count_c;
373 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
374 /* B mode */
375 memcpy(sband->bitrates, &ath5k_rates[0],
376 sizeof(struct ieee80211_rate) * 4);
377 sband->n_bitrates = 4;
378
379 /* 5211 only supports B rates and uses 4bit rate codes
380 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
381 * fix them up here:
382 */
383 if (ah->ah_version == AR5K_AR5211) {
384 for (i = 0; i < 4; i++) {
385 sband->bitrates[i].hw_value =
386 sband->bitrates[i].hw_value & 0xF;
387 sband->bitrates[i].hw_value_short =
388 sband->bitrates[i].hw_value_short & 0xF;
389 }
390 }
391
392 sband->channels = sc->channels;
393 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
394 AR5K_MODE_11B, max_c);
395
396 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
397 count_c = sband->n_channels;
398 max_c -= count_c;
399 }
400 ath5k_setup_rate_idx(sc, sband);
401
402 /* 5GHz band, A mode */
403 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
404 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
405 sband->band = IEEE80211_BAND_5GHZ;
406 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
407
408 memcpy(sband->bitrates, &ath5k_rates[4],
409 sizeof(struct ieee80211_rate) * 8);
410 sband->n_bitrates = 8;
411
412 sband->channels = &sc->channels[count_c];
413 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
414 AR5K_MODE_11A, max_c);
415
416 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
417 }
418 ath5k_setup_rate_idx(sc, sband);
419
420 ath5k_debug_dump_bands(sc);
421
422 return 0;
423 }
424
425 /*
426 * Set/change channels. We always reset the chip.
427 * To accomplish this we must first cleanup any pending DMA,
428 * then restart stuff after a la ath5k_init.
429 *
430 * Called with sc->lock.
431 */
432 int
433 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
434 {
435 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
436 "channel set, resetting (%u -> %u MHz)\n",
437 sc->curchan->center_freq, chan->center_freq);
438
439 /*
440 * To switch channels clear any pending DMA operations;
441 * wait long enough for the RX fifo to drain, reset the
442 * hardware at the new frequency, and then re-enable
443 * the relevant bits of the h/w.
444 */
445 return ath5k_reset(sc, chan, true);
446 }
447
448 void ath5k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
449 {
450 struct ath5k_vif_iter_data *iter_data = data;
451 int i;
452 struct ath5k_vif *avf = (void *)vif->drv_priv;
453
454 if (iter_data->hw_macaddr)
455 for (i = 0; i < ETH_ALEN; i++)
456 iter_data->mask[i] &=
457 ~(iter_data->hw_macaddr[i] ^ mac[i]);
458
459 if (!iter_data->found_active) {
460 iter_data->found_active = true;
461 memcpy(iter_data->active_mac, mac, ETH_ALEN);
462 }
463
464 if (iter_data->need_set_hw_addr && iter_data->hw_macaddr)
465 if (compare_ether_addr(iter_data->hw_macaddr, mac) == 0)
466 iter_data->need_set_hw_addr = false;
467
468 if (!iter_data->any_assoc) {
469 if (avf->assoc)
470 iter_data->any_assoc = true;
471 }
472
473 /* Calculate combined mode - when APs are active, operate in AP mode.
474 * Otherwise use the mode of the new interface. This can currently
475 * only deal with combinations of APs and STAs. Only one ad-hoc
476 * interfaces is allowed.
477 */
478 if (avf->opmode == NL80211_IFTYPE_AP)
479 iter_data->opmode = NL80211_IFTYPE_AP;
480 else {
481 if (avf->opmode == NL80211_IFTYPE_STATION)
482 iter_data->n_stas++;
483 if (iter_data->opmode == NL80211_IFTYPE_UNSPECIFIED)
484 iter_data->opmode = avf->opmode;
485 }
486 }
487
488 void
489 ath5k_update_bssid_mask_and_opmode(struct ath5k_softc *sc,
490 struct ieee80211_vif *vif)
491 {
492 struct ath_common *common = ath5k_hw_common(sc->ah);
493 struct ath5k_vif_iter_data iter_data;
494 u32 rfilt;
495
496 /*
497 * Use the hardware MAC address as reference, the hardware uses it
498 * together with the BSSID mask when matching addresses.
499 */
500 iter_data.hw_macaddr = common->macaddr;
501 memset(&iter_data.mask, 0xff, ETH_ALEN);
502 iter_data.found_active = false;
503 iter_data.need_set_hw_addr = true;
504 iter_data.opmode = NL80211_IFTYPE_UNSPECIFIED;
505 iter_data.n_stas = 0;
506
507 if (vif)
508 ath5k_vif_iter(&iter_data, vif->addr, vif);
509
510 /* Get list of all active MAC addresses */
511 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath5k_vif_iter,
512 &iter_data);
513 memcpy(sc->bssidmask, iter_data.mask, ETH_ALEN);
514
515 sc->opmode = iter_data.opmode;
516 if (sc->opmode == NL80211_IFTYPE_UNSPECIFIED)
517 /* Nothing active, default to station mode */
518 sc->opmode = NL80211_IFTYPE_STATION;
519
520 ath5k_hw_set_opmode(sc->ah, sc->opmode);
521 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n",
522 sc->opmode, ath_opmode_to_string(sc->opmode));
523
524 if (iter_data.need_set_hw_addr && iter_data.found_active)
525 ath5k_hw_set_lladdr(sc->ah, iter_data.active_mac);
526
527 if (ath5k_hw_hasbssidmask(sc->ah))
528 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
529
530 /* Set up RX Filter */
531 if (iter_data.n_stas > 1) {
532 /* If you have multiple STA interfaces connected to
533 * different APs, ARPs are not received (most of the time?)
534 * Enabling PROMISC appears to fix that problem.
535 */
536 sc->filter_flags |= AR5K_RX_FILTER_PROM;
537 }
538
539 rfilt = sc->filter_flags;
540 ath5k_hw_set_rx_filter(sc->ah, rfilt);
541 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
542 }
543
544 static inline int
545 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
546 {
547 int rix;
548
549 /* return base rate on errors */
550 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
551 "hw_rix out of bounds: %x\n", hw_rix))
552 return 0;
553
554 rix = sc->rate_idx[sc->curchan->band][hw_rix];
555 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
556 rix = 0;
557
558 return rix;
559 }
560
561 /***************\
562 * Buffers setup *
563 \***************/
564
565 static
566 struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
567 {
568 struct ath_common *common = ath5k_hw_common(sc->ah);
569 struct sk_buff *skb;
570
571 /*
572 * Allocate buffer with headroom_needed space for the
573 * fake physical layer header at the start.
574 */
575 skb = ath_rxbuf_alloc(common,
576 common->rx_bufsize,
577 GFP_ATOMIC);
578
579 if (!skb) {
580 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
581 common->rx_bufsize);
582 return NULL;
583 }
584
585 *skb_addr = dma_map_single(sc->dev,
586 skb->data, common->rx_bufsize,
587 DMA_FROM_DEVICE);
588
589 if (unlikely(dma_mapping_error(sc->dev, *skb_addr))) {
590 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
591 dev_kfree_skb(skb);
592 return NULL;
593 }
594 return skb;
595 }
596
597 static int
598 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
599 {
600 struct ath5k_hw *ah = sc->ah;
601 struct sk_buff *skb = bf->skb;
602 struct ath5k_desc *ds;
603 int ret;
604
605 if (!skb) {
606 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
607 if (!skb)
608 return -ENOMEM;
609 bf->skb = skb;
610 }
611
612 /*
613 * Setup descriptors. For receive we always terminate
614 * the descriptor list with a self-linked entry so we'll
615 * not get overrun under high load (as can happen with a
616 * 5212 when ANI processing enables PHY error frames).
617 *
618 * To ensure the last descriptor is self-linked we create
619 * each descriptor as self-linked and add it to the end. As
620 * each additional descriptor is added the previous self-linked
621 * entry is "fixed" naturally. This should be safe even
622 * if DMA is happening. When processing RX interrupts we
623 * never remove/process the last, self-linked, entry on the
624 * descriptor list. This ensures the hardware always has
625 * someplace to write a new frame.
626 */
627 ds = bf->desc;
628 ds->ds_link = bf->daddr; /* link to self */
629 ds->ds_data = bf->skbaddr;
630 ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0);
631 if (ret) {
632 ATH5K_ERR(sc, "%s: could not setup RX desc\n", __func__);
633 return ret;
634 }
635
636 if (sc->rxlink != NULL)
637 *sc->rxlink = bf->daddr;
638 sc->rxlink = &ds->ds_link;
639 return 0;
640 }
641
642 static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
643 {
644 struct ieee80211_hdr *hdr;
645 enum ath5k_pkt_type htype;
646 __le16 fc;
647
648 hdr = (struct ieee80211_hdr *)skb->data;
649 fc = hdr->frame_control;
650
651 if (ieee80211_is_beacon(fc))
652 htype = AR5K_PKT_TYPE_BEACON;
653 else if (ieee80211_is_probe_resp(fc))
654 htype = AR5K_PKT_TYPE_PROBE_RESP;
655 else if (ieee80211_is_atim(fc))
656 htype = AR5K_PKT_TYPE_ATIM;
657 else if (ieee80211_is_pspoll(fc))
658 htype = AR5K_PKT_TYPE_PSPOLL;
659 else
660 htype = AR5K_PKT_TYPE_NORMAL;
661
662 return htype;
663 }
664
665 static int
666 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
667 struct ath5k_txq *txq, int padsize)
668 {
669 struct ath5k_hw *ah = sc->ah;
670 struct ath5k_desc *ds = bf->desc;
671 struct sk_buff *skb = bf->skb;
672 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
673 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
674 struct ieee80211_rate *rate;
675 unsigned int mrr_rate[3], mrr_tries[3];
676 int i, ret;
677 u16 hw_rate;
678 u16 cts_rate = 0;
679 u16 duration = 0;
680 u8 rc_flags;
681
682 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
683
684 /* XXX endianness */
685 bf->skbaddr = dma_map_single(sc->dev, skb->data, skb->len,
686 DMA_TO_DEVICE);
687
688 rate = ieee80211_get_tx_rate(sc->hw, info);
689 if (!rate) {
690 ret = -EINVAL;
691 goto err_unmap;
692 }
693
694 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
695 flags |= AR5K_TXDESC_NOACK;
696
697 rc_flags = info->control.rates[0].flags;
698 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
699 rate->hw_value_short : rate->hw_value;
700
701 pktlen = skb->len;
702
703 /* FIXME: If we are in g mode and rate is a CCK rate
704 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
705 * from tx power (value is in dB units already) */
706 if (info->control.hw_key) {
707 keyidx = info->control.hw_key->hw_key_idx;
708 pktlen += info->control.hw_key->icv_len;
709 }
710 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
711 flags |= AR5K_TXDESC_RTSENA;
712 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
713 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
714 info->control.vif, pktlen, info));
715 }
716 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
717 flags |= AR5K_TXDESC_CTSENA;
718 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
719 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
720 info->control.vif, pktlen, info));
721 }
722 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
723 ieee80211_get_hdrlen_from_skb(skb), padsize,
724 get_hw_packet_type(skb),
725 (sc->power_level * 2),
726 hw_rate,
727 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
728 cts_rate, duration);
729 if (ret)
730 goto err_unmap;
731
732 memset(mrr_rate, 0, sizeof(mrr_rate));
733 memset(mrr_tries, 0, sizeof(mrr_tries));
734 for (i = 0; i < 3; i++) {
735 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
736 if (!rate)
737 break;
738
739 mrr_rate[i] = rate->hw_value;
740 mrr_tries[i] = info->control.rates[i + 1].count;
741 }
742
743 ath5k_hw_setup_mrr_tx_desc(ah, ds,
744 mrr_rate[0], mrr_tries[0],
745 mrr_rate[1], mrr_tries[1],
746 mrr_rate[2], mrr_tries[2]);
747
748 ds->ds_link = 0;
749 ds->ds_data = bf->skbaddr;
750
751 spin_lock_bh(&txq->lock);
752 list_add_tail(&bf->list, &txq->q);
753 txq->txq_len++;
754 if (txq->link == NULL) /* is this first packet? */
755 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
756 else /* no, so only link it */
757 *txq->link = bf->daddr;
758
759 txq->link = &ds->ds_link;
760 ath5k_hw_start_tx_dma(ah, txq->qnum);
761 mmiowb();
762 spin_unlock_bh(&txq->lock);
763
764 return 0;
765 err_unmap:
766 dma_unmap_single(sc->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
767 return ret;
768 }
769
770 /*******************\
771 * Descriptors setup *
772 \*******************/
773
774 static int
775 ath5k_desc_alloc(struct ath5k_softc *sc)
776 {
777 struct ath5k_desc *ds;
778 struct ath5k_buf *bf;
779 dma_addr_t da;
780 unsigned int i;
781 int ret;
782
783 /* allocate descriptors */
784 sc->desc_len = sizeof(struct ath5k_desc) *
785 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
786
787 sc->desc = dma_alloc_coherent(sc->dev, sc->desc_len,
788 &sc->desc_daddr, GFP_KERNEL);
789 if (sc->desc == NULL) {
790 ATH5K_ERR(sc, "can't allocate descriptors\n");
791 ret = -ENOMEM;
792 goto err;
793 }
794 ds = sc->desc;
795 da = sc->desc_daddr;
796 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
797 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
798
799 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
800 sizeof(struct ath5k_buf), GFP_KERNEL);
801 if (bf == NULL) {
802 ATH5K_ERR(sc, "can't allocate bufptr\n");
803 ret = -ENOMEM;
804 goto err_free;
805 }
806 sc->bufptr = bf;
807
808 INIT_LIST_HEAD(&sc->rxbuf);
809 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
810 bf->desc = ds;
811 bf->daddr = da;
812 list_add_tail(&bf->list, &sc->rxbuf);
813 }
814
815 INIT_LIST_HEAD(&sc->txbuf);
816 sc->txbuf_len = ATH_TXBUF;
817 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
818 bf->desc = ds;
819 bf->daddr = da;
820 list_add_tail(&bf->list, &sc->txbuf);
821 }
822
823 /* beacon buffers */
824 INIT_LIST_HEAD(&sc->bcbuf);
825 for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) {
826 bf->desc = ds;
827 bf->daddr = da;
828 list_add_tail(&bf->list, &sc->bcbuf);
829 }
830
831 return 0;
832 err_free:
833 dma_free_coherent(sc->dev, sc->desc_len, sc->desc, sc->desc_daddr);
834 err:
835 sc->desc = NULL;
836 return ret;
837 }
838
839 void
840 ath5k_txbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf)
841 {
842 BUG_ON(!bf);
843 if (!bf->skb)
844 return;
845 dma_unmap_single(sc->dev, bf->skbaddr, bf->skb->len,
846 DMA_TO_DEVICE);
847 dev_kfree_skb_any(bf->skb);
848 bf->skb = NULL;
849 bf->skbaddr = 0;
850 bf->desc->ds_data = 0;
851 }
852
853 void
854 ath5k_rxbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf)
855 {
856 struct ath5k_hw *ah = sc->ah;
857 struct ath_common *common = ath5k_hw_common(ah);
858
859 BUG_ON(!bf);
860 if (!bf->skb)
861 return;
862 dma_unmap_single(sc->dev, bf->skbaddr, common->rx_bufsize,
863 DMA_FROM_DEVICE);
864 dev_kfree_skb_any(bf->skb);
865 bf->skb = NULL;
866 bf->skbaddr = 0;
867 bf->desc->ds_data = 0;
868 }
869
870 static void
871 ath5k_desc_free(struct ath5k_softc *sc)
872 {
873 struct ath5k_buf *bf;
874
875 list_for_each_entry(bf, &sc->txbuf, list)
876 ath5k_txbuf_free_skb(sc, bf);
877 list_for_each_entry(bf, &sc->rxbuf, list)
878 ath5k_rxbuf_free_skb(sc, bf);
879 list_for_each_entry(bf, &sc->bcbuf, list)
880 ath5k_txbuf_free_skb(sc, bf);
881
882 /* Free memory associated with all descriptors */
883 dma_free_coherent(sc->dev, sc->desc_len, sc->desc, sc->desc_daddr);
884 sc->desc = NULL;
885 sc->desc_daddr = 0;
886
887 kfree(sc->bufptr);
888 sc->bufptr = NULL;
889 }
890
891
892 /**************\
893 * Queues setup *
894 \**************/
895
896 static struct ath5k_txq *
897 ath5k_txq_setup(struct ath5k_softc *sc,
898 int qtype, int subtype)
899 {
900 struct ath5k_hw *ah = sc->ah;
901 struct ath5k_txq *txq;
902 struct ath5k_txq_info qi = {
903 .tqi_subtype = subtype,
904 /* XXX: default values not correct for B and XR channels,
905 * but who cares? */
906 .tqi_aifs = AR5K_TUNE_AIFS,
907 .tqi_cw_min = AR5K_TUNE_CWMIN,
908 .tqi_cw_max = AR5K_TUNE_CWMAX
909 };
910 int qnum;
911
912 /*
913 * Enable interrupts only for EOL and DESC conditions.
914 * We mark tx descriptors to receive a DESC interrupt
915 * when a tx queue gets deep; otherwise we wait for the
916 * EOL to reap descriptors. Note that this is done to
917 * reduce interrupt load and this only defers reaping
918 * descriptors, never transmitting frames. Aside from
919 * reducing interrupts this also permits more concurrency.
920 * The only potential downside is if the tx queue backs
921 * up in which case the top half of the kernel may backup
922 * due to a lack of tx descriptors.
923 */
924 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
925 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
926 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
927 if (qnum < 0) {
928 /*
929 * NB: don't print a message, this happens
930 * normally on parts with too few tx queues
931 */
932 return ERR_PTR(qnum);
933 }
934 if (qnum >= ARRAY_SIZE(sc->txqs)) {
935 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
936 qnum, ARRAY_SIZE(sc->txqs));
937 ath5k_hw_release_tx_queue(ah, qnum);
938 return ERR_PTR(-EINVAL);
939 }
940 txq = &sc->txqs[qnum];
941 if (!txq->setup) {
942 txq->qnum = qnum;
943 txq->link = NULL;
944 INIT_LIST_HEAD(&txq->q);
945 spin_lock_init(&txq->lock);
946 txq->setup = true;
947 txq->txq_len = 0;
948 txq->txq_max = ATH5K_TXQ_LEN_MAX;
949 txq->txq_poll_mark = false;
950 txq->txq_stuck = 0;
951 }
952 return &sc->txqs[qnum];
953 }
954
955 static int
956 ath5k_beaconq_setup(struct ath5k_hw *ah)
957 {
958 struct ath5k_txq_info qi = {
959 /* XXX: default values not correct for B and XR channels,
960 * but who cares? */
961 .tqi_aifs = AR5K_TUNE_AIFS,
962 .tqi_cw_min = AR5K_TUNE_CWMIN,
963 .tqi_cw_max = AR5K_TUNE_CWMAX,
964 /* NB: for dynamic turbo, don't enable any other interrupts */
965 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
966 };
967
968 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
969 }
970
971 static int
972 ath5k_beaconq_config(struct ath5k_softc *sc)
973 {
974 struct ath5k_hw *ah = sc->ah;
975 struct ath5k_txq_info qi;
976 int ret;
977
978 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
979 if (ret)
980 goto err;
981
982 if (sc->opmode == NL80211_IFTYPE_AP ||
983 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
984 /*
985 * Always burst out beacon and CAB traffic
986 * (aifs = cwmin = cwmax = 0)
987 */
988 qi.tqi_aifs = 0;
989 qi.tqi_cw_min = 0;
990 qi.tqi_cw_max = 0;
991 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
992 /*
993 * Adhoc mode; backoff between 0 and (2 * cw_min).
994 */
995 qi.tqi_aifs = 0;
996 qi.tqi_cw_min = 0;
997 qi.tqi_cw_max = 2 * AR5K_TUNE_CWMIN;
998 }
999
1000 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1001 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1002 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1003
1004 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
1005 if (ret) {
1006 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1007 "hardware queue!\n", __func__);
1008 goto err;
1009 }
1010 ret = ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */
1011 if (ret)
1012 goto err;
1013
1014 /* reconfigure cabq with ready time to 80% of beacon_interval */
1015 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1016 if (ret)
1017 goto err;
1018
1019 qi.tqi_ready_time = (sc->bintval * 80) / 100;
1020 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1021 if (ret)
1022 goto err;
1023
1024 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB);
1025 err:
1026 return ret;
1027 }
1028
1029 /**
1030 * ath5k_drain_tx_buffs - Empty tx buffers
1031 *
1032 * @sc The &struct ath5k_softc
1033 *
1034 * Empty tx buffers from all queues in preparation
1035 * of a reset or during shutdown.
1036 *
1037 * NB: this assumes output has been stopped and
1038 * we do not need to block ath5k_tx_tasklet
1039 */
1040 static void
1041 ath5k_drain_tx_buffs(struct ath5k_softc *sc)
1042 {
1043 struct ath5k_txq *txq;
1044 struct ath5k_buf *bf, *bf0;
1045 int i;
1046
1047 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) {
1048 if (sc->txqs[i].setup) {
1049 txq = &sc->txqs[i];
1050 spin_lock_bh(&txq->lock);
1051 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1052 ath5k_debug_printtxbuf(sc, bf);
1053
1054 ath5k_txbuf_free_skb(sc, bf);
1055
1056 spin_lock_bh(&sc->txbuflock);
1057 list_move_tail(&bf->list, &sc->txbuf);
1058 sc->txbuf_len++;
1059 txq->txq_len--;
1060 spin_unlock_bh(&sc->txbuflock);
1061 }
1062 txq->link = NULL;
1063 txq->txq_poll_mark = false;
1064 spin_unlock_bh(&txq->lock);
1065 }
1066 }
1067 }
1068
1069 static void
1070 ath5k_txq_release(struct ath5k_softc *sc)
1071 {
1072 struct ath5k_txq *txq = sc->txqs;
1073 unsigned int i;
1074
1075 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1076 if (txq->setup) {
1077 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1078 txq->setup = false;
1079 }
1080 }
1081
1082
1083 /*************\
1084 * RX Handling *
1085 \*************/
1086
1087 /*
1088 * Enable the receive h/w following a reset.
1089 */
1090 static int
1091 ath5k_rx_start(struct ath5k_softc *sc)
1092 {
1093 struct ath5k_hw *ah = sc->ah;
1094 struct ath_common *common = ath5k_hw_common(ah);
1095 struct ath5k_buf *bf;
1096 int ret;
1097
1098 common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz);
1099
1100 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
1101 common->cachelsz, common->rx_bufsize);
1102
1103 spin_lock_bh(&sc->rxbuflock);
1104 sc->rxlink = NULL;
1105 list_for_each_entry(bf, &sc->rxbuf, list) {
1106 ret = ath5k_rxbuf_setup(sc, bf);
1107 if (ret != 0) {
1108 spin_unlock_bh(&sc->rxbuflock);
1109 goto err;
1110 }
1111 }
1112 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1113 ath5k_hw_set_rxdp(ah, bf->daddr);
1114 spin_unlock_bh(&sc->rxbuflock);
1115
1116 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
1117 ath5k_update_bssid_mask_and_opmode(sc, NULL); /* set filters, etc. */
1118 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1119
1120 return 0;
1121 err:
1122 return ret;
1123 }
1124
1125 /*
1126 * Disable the receive logic on PCU (DRU)
1127 * In preparation for a shutdown.
1128 *
1129 * Note: Doesn't stop rx DMA, ath5k_hw_dma_stop
1130 * does.
1131 */
1132 static void
1133 ath5k_rx_stop(struct ath5k_softc *sc)
1134 {
1135 struct ath5k_hw *ah = sc->ah;
1136
1137 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1138 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
1139
1140 ath5k_debug_printrxbuffs(sc, ah);
1141 }
1142
1143 static unsigned int
1144 ath5k_rx_decrypted(struct ath5k_softc *sc, struct sk_buff *skb,
1145 struct ath5k_rx_status *rs)
1146 {
1147 struct ath5k_hw *ah = sc->ah;
1148 struct ath_common *common = ath5k_hw_common(ah);
1149 struct ieee80211_hdr *hdr = (void *)skb->data;
1150 unsigned int keyix, hlen;
1151
1152 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1153 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1154 return RX_FLAG_DECRYPTED;
1155
1156 /* Apparently when a default key is used to decrypt the packet
1157 the hw does not set the index used to decrypt. In such cases
1158 get the index from the packet. */
1159 hlen = ieee80211_hdrlen(hdr->frame_control);
1160 if (ieee80211_has_protected(hdr->frame_control) &&
1161 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1162 skb->len >= hlen + 4) {
1163 keyix = skb->data[hlen + 3] >> 6;
1164
1165 if (test_bit(keyix, common->keymap))
1166 return RX_FLAG_DECRYPTED;
1167 }
1168
1169 return 0;
1170 }
1171
1172
1173 static void
1174 ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1175 struct ieee80211_rx_status *rxs)
1176 {
1177 struct ath_common *common = ath5k_hw_common(sc->ah);
1178 u64 tsf, bc_tstamp;
1179 u32 hw_tu;
1180 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1181
1182 if (ieee80211_is_beacon(mgmt->frame_control) &&
1183 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1184 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) {
1185 /*
1186 * Received an IBSS beacon with the same BSSID. Hardware *must*
1187 * have updated the local TSF. We have to work around various
1188 * hardware bugs, though...
1189 */
1190 tsf = ath5k_hw_get_tsf64(sc->ah);
1191 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1192 hw_tu = TSF_TO_TU(tsf);
1193
1194 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1195 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1196 (unsigned long long)bc_tstamp,
1197 (unsigned long long)rxs->mactime,
1198 (unsigned long long)(rxs->mactime - bc_tstamp),
1199 (unsigned long long)tsf);
1200
1201 /*
1202 * Sometimes the HW will give us a wrong tstamp in the rx
1203 * status, causing the timestamp extension to go wrong.
1204 * (This seems to happen especially with beacon frames bigger
1205 * than 78 byte (incl. FCS))
1206 * But we know that the receive timestamp must be later than the
1207 * timestamp of the beacon since HW must have synced to that.
1208 *
1209 * NOTE: here we assume mactime to be after the frame was
1210 * received, not like mac80211 which defines it at the start.
1211 */
1212 if (bc_tstamp > rxs->mactime) {
1213 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1214 "fixing mactime from %llx to %llx\n",
1215 (unsigned long long)rxs->mactime,
1216 (unsigned long long)tsf);
1217 rxs->mactime = tsf;
1218 }
1219
1220 /*
1221 * Local TSF might have moved higher than our beacon timers,
1222 * in that case we have to update them to continue sending
1223 * beacons. This also takes care of synchronizing beacon sending
1224 * times with other stations.
1225 */
1226 if (hw_tu >= sc->nexttbtt)
1227 ath5k_beacon_update_timers(sc, bc_tstamp);
1228
1229 /* Check if the beacon timers are still correct, because a TSF
1230 * update might have created a window between them - for a
1231 * longer description see the comment of this function: */
1232 if (!ath5k_hw_check_beacon_timers(sc->ah, sc->bintval)) {
1233 ath5k_beacon_update_timers(sc, bc_tstamp);
1234 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1235 "fixed beacon timers after beacon receive\n");
1236 }
1237 }
1238 }
1239
1240 static void
1241 ath5k_update_beacon_rssi(struct ath5k_softc *sc, struct sk_buff *skb, int rssi)
1242 {
1243 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1244 struct ath5k_hw *ah = sc->ah;
1245 struct ath_common *common = ath5k_hw_common(ah);
1246
1247 /* only beacons from our BSSID */
1248 if (!ieee80211_is_beacon(mgmt->frame_control) ||
1249 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) != 0)
1250 return;
1251
1252 ewma_add(&ah->ah_beacon_rssi_avg, rssi);
1253
1254 /* in IBSS mode we should keep RSSI statistics per neighbour */
1255 /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */
1256 }
1257
1258 /*
1259 * Compute padding position. skb must contain an IEEE 802.11 frame
1260 */
1261 static int ath5k_common_padpos(struct sk_buff *skb)
1262 {
1263 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1264 __le16 frame_control = hdr->frame_control;
1265 int padpos = 24;
1266
1267 if (ieee80211_has_a4(frame_control))
1268 padpos += ETH_ALEN;
1269
1270 if (ieee80211_is_data_qos(frame_control))
1271 padpos += IEEE80211_QOS_CTL_LEN;
1272
1273 return padpos;
1274 }
1275
1276 /*
1277 * This function expects an 802.11 frame and returns the number of
1278 * bytes added, or -1 if we don't have enough header room.
1279 */
1280 static int ath5k_add_padding(struct sk_buff *skb)
1281 {
1282 int padpos = ath5k_common_padpos(skb);
1283 int padsize = padpos & 3;
1284
1285 if (padsize && skb->len > padpos) {
1286
1287 if (skb_headroom(skb) < padsize)
1288 return -1;
1289
1290 skb_push(skb, padsize);
1291 memmove(skb->data, skb->data + padsize, padpos);
1292 return padsize;
1293 }
1294
1295 return 0;
1296 }
1297
1298 /*
1299 * The MAC header is padded to have 32-bit boundary if the
1300 * packet payload is non-zero. The general calculation for
1301 * padsize would take into account odd header lengths:
1302 * padsize = 4 - (hdrlen & 3); however, since only
1303 * even-length headers are used, padding can only be 0 or 2
1304 * bytes and we can optimize this a bit. We must not try to
1305 * remove padding from short control frames that do not have a
1306 * payload.
1307 *
1308 * This function expects an 802.11 frame and returns the number of
1309 * bytes removed.
1310 */
1311 static int ath5k_remove_padding(struct sk_buff *skb)
1312 {
1313 int padpos = ath5k_common_padpos(skb);
1314 int padsize = padpos & 3;
1315
1316 if (padsize && skb->len >= padpos + padsize) {
1317 memmove(skb->data + padsize, skb->data, padpos);
1318 skb_pull(skb, padsize);
1319 return padsize;
1320 }
1321
1322 return 0;
1323 }
1324
1325 static void
1326 ath5k_receive_frame(struct ath5k_softc *sc, struct sk_buff *skb,
1327 struct ath5k_rx_status *rs)
1328 {
1329 struct ieee80211_rx_status *rxs;
1330
1331 ath5k_remove_padding(skb);
1332
1333 rxs = IEEE80211_SKB_RXCB(skb);
1334
1335 rxs->flag = 0;
1336 if (unlikely(rs->rs_status & AR5K_RXERR_MIC))
1337 rxs->flag |= RX_FLAG_MMIC_ERROR;
1338
1339 /*
1340 * always extend the mac timestamp, since this information is
1341 * also needed for proper IBSS merging.
1342 *
1343 * XXX: it might be too late to do it here, since rs_tstamp is
1344 * 15bit only. that means TSF extension has to be done within
1345 * 32768usec (about 32ms). it might be necessary to move this to
1346 * the interrupt handler, like it is done in madwifi.
1347 *
1348 * Unfortunately we don't know when the hardware takes the rx
1349 * timestamp (beginning of phy frame, data frame, end of rx?).
1350 * The only thing we know is that it is hardware specific...
1351 * On AR5213 it seems the rx timestamp is at the end of the
1352 * frame, but I'm not sure.
1353 *
1354 * NOTE: mac80211 defines mactime at the beginning of the first
1355 * data symbol. Since we don't have any time references it's
1356 * impossible to comply to that. This affects IBSS merge only
1357 * right now, so it's not too bad...
1358 */
1359 rxs->mactime = ath5k_extend_tsf(sc->ah, rs->rs_tstamp);
1360 rxs->flag |= RX_FLAG_MACTIME_MPDU;
1361
1362 rxs->freq = sc->curchan->center_freq;
1363 rxs->band = sc->curchan->band;
1364
1365 rxs->signal = sc->ah->ah_noise_floor + rs->rs_rssi;
1366
1367 rxs->antenna = rs->rs_antenna;
1368
1369 if (rs->rs_antenna > 0 && rs->rs_antenna < 5)
1370 sc->stats.antenna_rx[rs->rs_antenna]++;
1371 else
1372 sc->stats.antenna_rx[0]++; /* invalid */
1373
1374 rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs->rs_rate);
1375 rxs->flag |= ath5k_rx_decrypted(sc, skb, rs);
1376
1377 if (rxs->rate_idx >= 0 && rs->rs_rate ==
1378 sc->sbands[sc->curchan->band].bitrates[rxs->rate_idx].hw_value_short)
1379 rxs->flag |= RX_FLAG_SHORTPRE;
1380
1381 trace_ath5k_rx(sc, skb);
1382
1383 ath5k_update_beacon_rssi(sc, skb, rs->rs_rssi);
1384
1385 /* check beacons in IBSS mode */
1386 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1387 ath5k_check_ibss_tsf(sc, skb, rxs);
1388
1389 ieee80211_rx(sc->hw, skb);
1390 }
1391
1392 /** ath5k_frame_receive_ok() - Do we want to receive this frame or not?
1393 *
1394 * Check if we want to further process this frame or not. Also update
1395 * statistics. Return true if we want this frame, false if not.
1396 */
1397 static bool
1398 ath5k_receive_frame_ok(struct ath5k_softc *sc, struct ath5k_rx_status *rs)
1399 {
1400 sc->stats.rx_all_count++;
1401 sc->stats.rx_bytes_count += rs->rs_datalen;
1402
1403 if (unlikely(rs->rs_status)) {
1404 if (rs->rs_status & AR5K_RXERR_CRC)
1405 sc->stats.rxerr_crc++;
1406 if (rs->rs_status & AR5K_RXERR_FIFO)
1407 sc->stats.rxerr_fifo++;
1408 if (rs->rs_status & AR5K_RXERR_PHY) {
1409 sc->stats.rxerr_phy++;
1410 if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32)
1411 sc->stats.rxerr_phy_code[rs->rs_phyerr]++;
1412 return false;
1413 }
1414 if (rs->rs_status & AR5K_RXERR_DECRYPT) {
1415 /*
1416 * Decrypt error. If the error occurred
1417 * because there was no hardware key, then
1418 * let the frame through so the upper layers
1419 * can process it. This is necessary for 5210
1420 * parts which have no way to setup a ``clear''
1421 * key cache entry.
1422 *
1423 * XXX do key cache faulting
1424 */
1425 sc->stats.rxerr_decrypt++;
1426 if (rs->rs_keyix == AR5K_RXKEYIX_INVALID &&
1427 !(rs->rs_status & AR5K_RXERR_CRC))
1428 return true;
1429 }
1430 if (rs->rs_status & AR5K_RXERR_MIC) {
1431 sc->stats.rxerr_mic++;
1432 return true;
1433 }
1434
1435 /* reject any frames with non-crypto errors */
1436 if (rs->rs_status & ~(AR5K_RXERR_DECRYPT))
1437 return false;
1438 }
1439
1440 if (unlikely(rs->rs_more)) {
1441 sc->stats.rxerr_jumbo++;
1442 return false;
1443 }
1444 return true;
1445 }
1446
1447 static void
1448 ath5k_set_current_imask(struct ath5k_softc *sc)
1449 {
1450 enum ath5k_int imask;
1451 unsigned long flags;
1452
1453 spin_lock_irqsave(&sc->irqlock, flags);
1454 imask = sc->imask;
1455 if (sc->rx_pending)
1456 imask &= ~AR5K_INT_RX_ALL;
1457 if (sc->tx_pending)
1458 imask &= ~AR5K_INT_TX_ALL;
1459 ath5k_hw_set_imr(sc->ah, imask);
1460 spin_unlock_irqrestore(&sc->irqlock, flags);
1461 }
1462
1463 static void
1464 ath5k_tasklet_rx(unsigned long data)
1465 {
1466 struct ath5k_rx_status rs = {};
1467 struct sk_buff *skb, *next_skb;
1468 dma_addr_t next_skb_addr;
1469 struct ath5k_softc *sc = (void *)data;
1470 struct ath5k_hw *ah = sc->ah;
1471 struct ath_common *common = ath5k_hw_common(ah);
1472 struct ath5k_buf *bf;
1473 struct ath5k_desc *ds;
1474 int ret;
1475
1476 spin_lock(&sc->rxbuflock);
1477 if (list_empty(&sc->rxbuf)) {
1478 ATH5K_WARN(sc, "empty rx buf pool\n");
1479 goto unlock;
1480 }
1481 do {
1482 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1483 BUG_ON(bf->skb == NULL);
1484 skb = bf->skb;
1485 ds = bf->desc;
1486
1487 /* bail if HW is still using self-linked descriptor */
1488 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
1489 break;
1490
1491 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1492 if (unlikely(ret == -EINPROGRESS))
1493 break;
1494 else if (unlikely(ret)) {
1495 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1496 sc->stats.rxerr_proc++;
1497 break;
1498 }
1499
1500 if (ath5k_receive_frame_ok(sc, &rs)) {
1501 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
1502
1503 /*
1504 * If we can't replace bf->skb with a new skb under
1505 * memory pressure, just skip this packet
1506 */
1507 if (!next_skb)
1508 goto next;
1509
1510 dma_unmap_single(sc->dev, bf->skbaddr,
1511 common->rx_bufsize,
1512 DMA_FROM_DEVICE);
1513
1514 skb_put(skb, rs.rs_datalen);
1515
1516 ath5k_receive_frame(sc, skb, &rs);
1517
1518 bf->skb = next_skb;
1519 bf->skbaddr = next_skb_addr;
1520 }
1521 next:
1522 list_move_tail(&bf->list, &sc->rxbuf);
1523 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1524 unlock:
1525 spin_unlock(&sc->rxbuflock);
1526 sc->rx_pending = false;
1527 ath5k_set_current_imask(sc);
1528 }
1529
1530
1531 /*************\
1532 * TX Handling *
1533 \*************/
1534
1535 void
1536 ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
1537 struct ath5k_txq *txq)
1538 {
1539 struct ath5k_softc *sc = hw->priv;
1540 struct ath5k_buf *bf;
1541 unsigned long flags;
1542 int padsize;
1543
1544 trace_ath5k_tx(sc, skb, txq);
1545
1546 /*
1547 * The hardware expects the header padded to 4 byte boundaries.
1548 * If this is not the case, we add the padding after the header.
1549 */
1550 padsize = ath5k_add_padding(skb);
1551 if (padsize < 0) {
1552 ATH5K_ERR(sc, "tx hdrlen not %%4: not enough"
1553 " headroom to pad");
1554 goto drop_packet;
1555 }
1556
1557 if (txq->txq_len >= txq->txq_max &&
1558 txq->qnum <= AR5K_TX_QUEUE_ID_DATA_MAX)
1559 ieee80211_stop_queue(hw, txq->qnum);
1560
1561 spin_lock_irqsave(&sc->txbuflock, flags);
1562 if (list_empty(&sc->txbuf)) {
1563 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
1564 spin_unlock_irqrestore(&sc->txbuflock, flags);
1565 ieee80211_stop_queues(hw);
1566 goto drop_packet;
1567 }
1568 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
1569 list_del(&bf->list);
1570 sc->txbuf_len--;
1571 if (list_empty(&sc->txbuf))
1572 ieee80211_stop_queues(hw);
1573 spin_unlock_irqrestore(&sc->txbuflock, flags);
1574
1575 bf->skb = skb;
1576
1577 if (ath5k_txbuf_setup(sc, bf, txq, padsize)) {
1578 bf->skb = NULL;
1579 spin_lock_irqsave(&sc->txbuflock, flags);
1580 list_add_tail(&bf->list, &sc->txbuf);
1581 sc->txbuf_len++;
1582 spin_unlock_irqrestore(&sc->txbuflock, flags);
1583 goto drop_packet;
1584 }
1585 return;
1586
1587 drop_packet:
1588 dev_kfree_skb_any(skb);
1589 }
1590
1591 static void
1592 ath5k_tx_frame_completed(struct ath5k_softc *sc, struct sk_buff *skb,
1593 struct ath5k_txq *txq, struct ath5k_tx_status *ts)
1594 {
1595 struct ieee80211_tx_info *info;
1596 u8 tries[3];
1597 int i;
1598
1599 sc->stats.tx_all_count++;
1600 sc->stats.tx_bytes_count += skb->len;
1601 info = IEEE80211_SKB_CB(skb);
1602
1603 tries[0] = info->status.rates[0].count;
1604 tries[1] = info->status.rates[1].count;
1605 tries[2] = info->status.rates[2].count;
1606
1607 ieee80211_tx_info_clear_status(info);
1608
1609 for (i = 0; i < ts->ts_final_idx; i++) {
1610 struct ieee80211_tx_rate *r =
1611 &info->status.rates[i];
1612
1613 r->count = tries[i];
1614 }
1615
1616 info->status.rates[ts->ts_final_idx].count = ts->ts_final_retry;
1617 info->status.rates[ts->ts_final_idx + 1].idx = -1;
1618
1619 if (unlikely(ts->ts_status)) {
1620 sc->stats.ack_fail++;
1621 if (ts->ts_status & AR5K_TXERR_FILT) {
1622 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1623 sc->stats.txerr_filt++;
1624 }
1625 if (ts->ts_status & AR5K_TXERR_XRETRY)
1626 sc->stats.txerr_retry++;
1627 if (ts->ts_status & AR5K_TXERR_FIFO)
1628 sc->stats.txerr_fifo++;
1629 } else {
1630 info->flags |= IEEE80211_TX_STAT_ACK;
1631 info->status.ack_signal = ts->ts_rssi;
1632
1633 /* count the successful attempt as well */
1634 info->status.rates[ts->ts_final_idx].count++;
1635 }
1636
1637 /*
1638 * Remove MAC header padding before giving the frame
1639 * back to mac80211.
1640 */
1641 ath5k_remove_padding(skb);
1642
1643 if (ts->ts_antenna > 0 && ts->ts_antenna < 5)
1644 sc->stats.antenna_tx[ts->ts_antenna]++;
1645 else
1646 sc->stats.antenna_tx[0]++; /* invalid */
1647
1648 trace_ath5k_tx_complete(sc, skb, txq, ts);
1649 ieee80211_tx_status(sc->hw, skb);
1650 }
1651
1652 static void
1653 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1654 {
1655 struct ath5k_tx_status ts = {};
1656 struct ath5k_buf *bf, *bf0;
1657 struct ath5k_desc *ds;
1658 struct sk_buff *skb;
1659 int ret;
1660
1661 spin_lock(&txq->lock);
1662 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1663
1664 txq->txq_poll_mark = false;
1665
1666 /* skb might already have been processed last time. */
1667 if (bf->skb != NULL) {
1668 ds = bf->desc;
1669
1670 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
1671 if (unlikely(ret == -EINPROGRESS))
1672 break;
1673 else if (unlikely(ret)) {
1674 ATH5K_ERR(sc,
1675 "error %d while processing "
1676 "queue %u\n", ret, txq->qnum);
1677 break;
1678 }
1679
1680 skb = bf->skb;
1681 bf->skb = NULL;
1682
1683 dma_unmap_single(sc->dev, bf->skbaddr, skb->len,
1684 DMA_TO_DEVICE);
1685 ath5k_tx_frame_completed(sc, skb, txq, &ts);
1686 }
1687
1688 /*
1689 * It's possible that the hardware can say the buffer is
1690 * completed when it hasn't yet loaded the ds_link from
1691 * host memory and moved on.
1692 * Always keep the last descriptor to avoid HW races...
1693 */
1694 if (ath5k_hw_get_txdp(sc->ah, txq->qnum) != bf->daddr) {
1695 spin_lock(&sc->txbuflock);
1696 list_move_tail(&bf->list, &sc->txbuf);
1697 sc->txbuf_len++;
1698 txq->txq_len--;
1699 spin_unlock(&sc->txbuflock);
1700 }
1701 }
1702 spin_unlock(&txq->lock);
1703 if (txq->txq_len < ATH5K_TXQ_LEN_LOW && txq->qnum < 4)
1704 ieee80211_wake_queue(sc->hw, txq->qnum);
1705 }
1706
1707 static void
1708 ath5k_tasklet_tx(unsigned long data)
1709 {
1710 int i;
1711 struct ath5k_softc *sc = (void *)data;
1712
1713 for (i = 0; i < AR5K_NUM_TX_QUEUES; i++)
1714 if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i)))
1715 ath5k_tx_processq(sc, &sc->txqs[i]);
1716
1717 sc->tx_pending = false;
1718 ath5k_set_current_imask(sc);
1719 }
1720
1721
1722 /*****************\
1723 * Beacon handling *
1724 \*****************/
1725
1726 /*
1727 * Setup the beacon frame for transmit.
1728 */
1729 static int
1730 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1731 {
1732 struct sk_buff *skb = bf->skb;
1733 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1734 struct ath5k_hw *ah = sc->ah;
1735 struct ath5k_desc *ds;
1736 int ret = 0;
1737 u8 antenna;
1738 u32 flags;
1739 const int padsize = 0;
1740
1741 bf->skbaddr = dma_map_single(sc->dev, skb->data, skb->len,
1742 DMA_TO_DEVICE);
1743 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1744 "skbaddr %llx\n", skb, skb->data, skb->len,
1745 (unsigned long long)bf->skbaddr);
1746
1747 if (dma_mapping_error(sc->dev, bf->skbaddr)) {
1748 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1749 return -EIO;
1750 }
1751
1752 ds = bf->desc;
1753 antenna = ah->ah_tx_ant;
1754
1755 flags = AR5K_TXDESC_NOACK;
1756 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
1757 ds->ds_link = bf->daddr; /* self-linked */
1758 flags |= AR5K_TXDESC_VEOL;
1759 } else
1760 ds->ds_link = 0;
1761
1762 /*
1763 * If we use multiple antennas on AP and use
1764 * the Sectored AP scenario, switch antenna every
1765 * 4 beacons to make sure everybody hears our AP.
1766 * When a client tries to associate, hw will keep
1767 * track of the tx antenna to be used for this client
1768 * automatically, based on ACKed packets.
1769 *
1770 * Note: AP still listens and transmits RTS on the
1771 * default antenna which is supposed to be an omni.
1772 *
1773 * Note2: On sectored scenarios it's possible to have
1774 * multiple antennas (1 omni -- the default -- and 14
1775 * sectors), so if we choose to actually support this
1776 * mode, we need to allow the user to set how many antennas
1777 * we have and tweak the code below to send beacons
1778 * on all of them.
1779 */
1780 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
1781 antenna = sc->bsent & 4 ? 2 : 1;
1782
1783
1784 /* FIXME: If we are in g mode and rate is a CCK rate
1785 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1786 * from tx power (value is in dB units already) */
1787 ds->ds_data = bf->skbaddr;
1788 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
1789 ieee80211_get_hdrlen_from_skb(skb), padsize,
1790 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
1791 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
1792 1, AR5K_TXKEYIX_INVALID,
1793 antenna, flags, 0, 0);
1794 if (ret)
1795 goto err_unmap;
1796
1797 return 0;
1798 err_unmap:
1799 dma_unmap_single(sc->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
1800 return ret;
1801 }
1802
1803 /*
1804 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
1805 * this is called only once at config_bss time, for AP we do it every
1806 * SWBA interrupt so that the TIM will reflect buffered frames.
1807 *
1808 * Called with the beacon lock.
1809 */
1810 int
1811 ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1812 {
1813 int ret;
1814 struct ath5k_softc *sc = hw->priv;
1815 struct ath5k_vif *avf = (void *)vif->drv_priv;
1816 struct sk_buff *skb;
1817
1818 if (WARN_ON(!vif)) {
1819 ret = -EINVAL;
1820 goto out;
1821 }
1822
1823 skb = ieee80211_beacon_get(hw, vif);
1824
1825 if (!skb) {
1826 ret = -ENOMEM;
1827 goto out;
1828 }
1829
1830 ath5k_txbuf_free_skb(sc, avf->bbuf);
1831 avf->bbuf->skb = skb;
1832 ret = ath5k_beacon_setup(sc, avf->bbuf);
1833 if (ret)
1834 avf->bbuf->skb = NULL;
1835 out:
1836 return ret;
1837 }
1838
1839 /*
1840 * Transmit a beacon frame at SWBA. Dynamic updates to the
1841 * frame contents are done as needed and the slot time is
1842 * also adjusted based on current state.
1843 *
1844 * This is called from software irq context (beacontq tasklets)
1845 * or user context from ath5k_beacon_config.
1846 */
1847 static void
1848 ath5k_beacon_send(struct ath5k_softc *sc)
1849 {
1850 struct ath5k_hw *ah = sc->ah;
1851 struct ieee80211_vif *vif;
1852 struct ath5k_vif *avf;
1853 struct ath5k_buf *bf;
1854 struct sk_buff *skb;
1855
1856 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
1857
1858 /*
1859 * Check if the previous beacon has gone out. If
1860 * not, don't don't try to post another: skip this
1861 * period and wait for the next. Missed beacons
1862 * indicate a problem and should not occur. If we
1863 * miss too many consecutive beacons reset the device.
1864 */
1865 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
1866 sc->bmisscount++;
1867 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1868 "missed %u consecutive beacons\n", sc->bmisscount);
1869 if (sc->bmisscount > 10) { /* NB: 10 is a guess */
1870 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1871 "stuck beacon time (%u missed)\n",
1872 sc->bmisscount);
1873 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
1874 "stuck beacon, resetting\n");
1875 ieee80211_queue_work(sc->hw, &sc->reset_work);
1876 }
1877 return;
1878 }
1879 if (unlikely(sc->bmisscount != 0)) {
1880 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1881 "resume beacon xmit after %u misses\n",
1882 sc->bmisscount);
1883 sc->bmisscount = 0;
1884 }
1885
1886 if ((sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) ||
1887 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
1888 u64 tsf = ath5k_hw_get_tsf64(ah);
1889 u32 tsftu = TSF_TO_TU(tsf);
1890 int slot = ((tsftu % sc->bintval) * ATH_BCBUF) / sc->bintval;
1891 vif = sc->bslot[(slot + 1) % ATH_BCBUF];
1892 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1893 "tsf %llx tsftu %x intval %u slot %u vif %p\n",
1894 (unsigned long long)tsf, tsftu, sc->bintval, slot, vif);
1895 } else /* only one interface */
1896 vif = sc->bslot[0];
1897
1898 if (!vif)
1899 return;
1900
1901 avf = (void *)vif->drv_priv;
1902 bf = avf->bbuf;
1903 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
1904 sc->opmode == NL80211_IFTYPE_MONITOR)) {
1905 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
1906 return;
1907 }
1908
1909 /*
1910 * Stop any current dma and put the new frame on the queue.
1911 * This should never fail since we check above that no frames
1912 * are still pending on the queue.
1913 */
1914 if (unlikely(ath5k_hw_stop_beacon_queue(ah, sc->bhalq))) {
1915 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
1916 /* NB: hw still stops DMA, so proceed */
1917 }
1918
1919 /* refresh the beacon for AP or MESH mode */
1920 if (sc->opmode == NL80211_IFTYPE_AP ||
1921 sc->opmode == NL80211_IFTYPE_MESH_POINT)
1922 ath5k_beacon_update(sc->hw, vif);
1923
1924 trace_ath5k_tx(sc, bf->skb, &sc->txqs[sc->bhalq]);
1925
1926 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
1927 ath5k_hw_start_tx_dma(ah, sc->bhalq);
1928 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
1929 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
1930
1931 skb = ieee80211_get_buffered_bc(sc->hw, vif);
1932 while (skb) {
1933 ath5k_tx_queue(sc->hw, skb, sc->cabq);
1934
1935 if (sc->cabq->txq_len >= sc->cabq->txq_max)
1936 break;
1937
1938 skb = ieee80211_get_buffered_bc(sc->hw, vif);
1939 }
1940
1941 sc->bsent++;
1942 }
1943
1944 /**
1945 * ath5k_beacon_update_timers - update beacon timers
1946 *
1947 * @sc: struct ath5k_softc pointer we are operating on
1948 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
1949 * beacon timer update based on the current HW TSF.
1950 *
1951 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
1952 * of a received beacon or the current local hardware TSF and write it to the
1953 * beacon timer registers.
1954 *
1955 * This is called in a variety of situations, e.g. when a beacon is received,
1956 * when a TSF update has been detected, but also when an new IBSS is created or
1957 * when we otherwise know we have to update the timers, but we keep it in this
1958 * function to have it all together in one place.
1959 */
1960 void
1961 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
1962 {
1963 struct ath5k_hw *ah = sc->ah;
1964 u32 nexttbtt, intval, hw_tu, bc_tu;
1965 u64 hw_tsf;
1966
1967 intval = sc->bintval & AR5K_BEACON_PERIOD;
1968 if (sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) {
1969 intval /= ATH_BCBUF; /* staggered multi-bss beacons */
1970 if (intval < 15)
1971 ATH5K_WARN(sc, "intval %u is too low, min 15\n",
1972 intval);
1973 }
1974 if (WARN_ON(!intval))
1975 return;
1976
1977 /* beacon TSF converted to TU */
1978 bc_tu = TSF_TO_TU(bc_tsf);
1979
1980 /* current TSF converted to TU */
1981 hw_tsf = ath5k_hw_get_tsf64(ah);
1982 hw_tu = TSF_TO_TU(hw_tsf);
1983
1984 #define FUDGE (AR5K_TUNE_SW_BEACON_RESP + 3)
1985 /* We use FUDGE to make sure the next TBTT is ahead of the current TU.
1986 * Since we later subtract AR5K_TUNE_SW_BEACON_RESP (10) in the timer
1987 * configuration we need to make sure it is bigger than that. */
1988
1989 if (bc_tsf == -1) {
1990 /*
1991 * no beacons received, called internally.
1992 * just need to refresh timers based on HW TSF.
1993 */
1994 nexttbtt = roundup(hw_tu + FUDGE, intval);
1995 } else if (bc_tsf == 0) {
1996 /*
1997 * no beacon received, probably called by ath5k_reset_tsf().
1998 * reset TSF to start with 0.
1999 */
2000 nexttbtt = intval;
2001 intval |= AR5K_BEACON_RESET_TSF;
2002 } else if (bc_tsf > hw_tsf) {
2003 /*
2004 * beacon received, SW merge happened but HW TSF not yet updated.
2005 * not possible to reconfigure timers yet, but next time we
2006 * receive a beacon with the same BSSID, the hardware will
2007 * automatically update the TSF and then we need to reconfigure
2008 * the timers.
2009 */
2010 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2011 "need to wait for HW TSF sync\n");
2012 return;
2013 } else {
2014 /*
2015 * most important case for beacon synchronization between STA.
2016 *
2017 * beacon received and HW TSF has been already updated by HW.
2018 * update next TBTT based on the TSF of the beacon, but make
2019 * sure it is ahead of our local TSF timer.
2020 */
2021 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2022 }
2023 #undef FUDGE
2024
2025 sc->nexttbtt = nexttbtt;
2026
2027 intval |= AR5K_BEACON_ENA;
2028 ath5k_hw_init_beacon(ah, nexttbtt, intval);
2029
2030 /*
2031 * debugging output last in order to preserve the time critical aspect
2032 * of this function
2033 */
2034 if (bc_tsf == -1)
2035 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2036 "reconfigured timers based on HW TSF\n");
2037 else if (bc_tsf == 0)
2038 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2039 "reset HW TSF and timers\n");
2040 else
2041 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2042 "updated timers based on beacon TSF\n");
2043
2044 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2045 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2046 (unsigned long long) bc_tsf,
2047 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2048 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2049 intval & AR5K_BEACON_PERIOD,
2050 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2051 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2052 }
2053
2054 /**
2055 * ath5k_beacon_config - Configure the beacon queues and interrupts
2056 *
2057 * @sc: struct ath5k_softc pointer we are operating on
2058 *
2059 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2060 * interrupts to detect TSF updates only.
2061 */
2062 void
2063 ath5k_beacon_config(struct ath5k_softc *sc)
2064 {
2065 struct ath5k_hw *ah = sc->ah;
2066 unsigned long flags;
2067
2068 spin_lock_irqsave(&sc->block, flags);
2069 sc->bmisscount = 0;
2070 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2071
2072 if (sc->enable_beacon) {
2073 /*
2074 * In IBSS mode we use a self-linked tx descriptor and let the
2075 * hardware send the beacons automatically. We have to load it
2076 * only once here.
2077 * We use the SWBA interrupt only to keep track of the beacon
2078 * timers in order to detect automatic TSF updates.
2079 */
2080 ath5k_beaconq_config(sc);
2081
2082 sc->imask |= AR5K_INT_SWBA;
2083
2084 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2085 if (ath5k_hw_hasveol(ah))
2086 ath5k_beacon_send(sc);
2087 } else
2088 ath5k_beacon_update_timers(sc, -1);
2089 } else {
2090 ath5k_hw_stop_beacon_queue(sc->ah, sc->bhalq);
2091 }
2092
2093 ath5k_hw_set_imr(ah, sc->imask);
2094 mmiowb();
2095 spin_unlock_irqrestore(&sc->block, flags);
2096 }
2097
2098 static void ath5k_tasklet_beacon(unsigned long data)
2099 {
2100 struct ath5k_softc *sc = (struct ath5k_softc *) data;
2101
2102 /*
2103 * Software beacon alert--time to send a beacon.
2104 *
2105 * In IBSS mode we use this interrupt just to
2106 * keep track of the next TBTT (target beacon
2107 * transmission time) in order to detect whether
2108 * automatic TSF updates happened.
2109 */
2110 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2111 /* XXX: only if VEOL supported */
2112 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
2113 sc->nexttbtt += sc->bintval;
2114 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2115 "SWBA nexttbtt: %x hw_tu: %x "
2116 "TSF: %llx\n",
2117 sc->nexttbtt,
2118 TSF_TO_TU(tsf),
2119 (unsigned long long) tsf);
2120 } else {
2121 spin_lock(&sc->block);
2122 ath5k_beacon_send(sc);
2123 spin_unlock(&sc->block);
2124 }
2125 }
2126
2127
2128 /********************\
2129 * Interrupt handling *
2130 \********************/
2131
2132 static void
2133 ath5k_intr_calibration_poll(struct ath5k_hw *ah)
2134 {
2135 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) &&
2136 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL)) {
2137 /* run ANI only when full calibration is not active */
2138 ah->ah_cal_next_ani = jiffies +
2139 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
2140 tasklet_schedule(&ah->ah_sc->ani_tasklet);
2141
2142 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) {
2143 ah->ah_cal_next_full = jiffies +
2144 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2145 tasklet_schedule(&ah->ah_sc->calib);
2146 }
2147 /* we could use SWI to generate enough interrupts to meet our
2148 * calibration interval requirements, if necessary:
2149 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */
2150 }
2151
2152 static void
2153 ath5k_schedule_rx(struct ath5k_softc *sc)
2154 {
2155 sc->rx_pending = true;
2156 tasklet_schedule(&sc->rxtq);
2157 }
2158
2159 static void
2160 ath5k_schedule_tx(struct ath5k_softc *sc)
2161 {
2162 sc->tx_pending = true;
2163 tasklet_schedule(&sc->txtq);
2164 }
2165
2166 static irqreturn_t
2167 ath5k_intr(int irq, void *dev_id)
2168 {
2169 struct ath5k_softc *sc = dev_id;
2170 struct ath5k_hw *ah = sc->ah;
2171 enum ath5k_int status;
2172 unsigned int counter = 1000;
2173
2174 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2175 ((ath5k_get_bus_type(ah) != ATH_AHB) &&
2176 !ath5k_hw_is_intr_pending(ah))))
2177 return IRQ_NONE;
2178
2179 do {
2180 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2181 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2182 status, sc->imask);
2183 if (unlikely(status & AR5K_INT_FATAL)) {
2184 /*
2185 * Fatal errors are unrecoverable.
2186 * Typically these are caused by DMA errors.
2187 */
2188 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2189 "fatal int, resetting\n");
2190 ieee80211_queue_work(sc->hw, &sc->reset_work);
2191 } else if (unlikely(status & AR5K_INT_RXORN)) {
2192 /*
2193 * Receive buffers are full. Either the bus is busy or
2194 * the CPU is not fast enough to process all received
2195 * frames.
2196 * Older chipsets need a reset to come out of this
2197 * condition, but we treat it as RX for newer chips.
2198 * We don't know exactly which versions need a reset -
2199 * this guess is copied from the HAL.
2200 */
2201 sc->stats.rxorn_intr++;
2202 if (ah->ah_mac_srev < AR5K_SREV_AR5212) {
2203 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2204 "rx overrun, resetting\n");
2205 ieee80211_queue_work(sc->hw, &sc->reset_work);
2206 } else
2207 ath5k_schedule_rx(sc);
2208 } else {
2209 if (status & AR5K_INT_SWBA)
2210 tasklet_hi_schedule(&sc->beacontq);
2211
2212 if (status & AR5K_INT_RXEOL) {
2213 /*
2214 * NB: the hardware should re-read the link when
2215 * RXE bit is written, but it doesn't work at
2216 * least on older hardware revs.
2217 */
2218 sc->stats.rxeol_intr++;
2219 }
2220 if (status & AR5K_INT_TXURN) {
2221 /* bump tx trigger level */
2222 ath5k_hw_update_tx_triglevel(ah, true);
2223 }
2224 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
2225 ath5k_schedule_rx(sc);
2226 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2227 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
2228 ath5k_schedule_tx(sc);
2229 if (status & AR5K_INT_BMISS) {
2230 /* TODO */
2231 }
2232 if (status & AR5K_INT_MIB) {
2233 sc->stats.mib_intr++;
2234 ath5k_hw_update_mib_counters(ah);
2235 ath5k_ani_mib_intr(ah);
2236 }
2237 if (status & AR5K_INT_GPIO)
2238 tasklet_schedule(&sc->rf_kill.toggleq);
2239
2240 }
2241
2242 if (ath5k_get_bus_type(ah) == ATH_AHB)
2243 break;
2244
2245 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
2246
2247 if (sc->rx_pending || sc->tx_pending)
2248 ath5k_set_current_imask(sc);
2249
2250 if (unlikely(!counter))
2251 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2252
2253 ath5k_intr_calibration_poll(ah);
2254
2255 return IRQ_HANDLED;
2256 }
2257
2258 /*
2259 * Periodically recalibrate the PHY to account
2260 * for temperature/environment changes.
2261 */
2262 static void
2263 ath5k_tasklet_calibrate(unsigned long data)
2264 {
2265 struct ath5k_softc *sc = (void *)data;
2266 struct ath5k_hw *ah = sc->ah;
2267
2268 /* Only full calibration for now */
2269 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL;
2270
2271 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2272 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2273 sc->curchan->hw_value);
2274
2275 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2276 /*
2277 * Rfgain is out of bounds, reset the chip
2278 * to load new gain values.
2279 */
2280 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2281 ieee80211_queue_work(sc->hw, &sc->reset_work);
2282 }
2283 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2284 ATH5K_ERR(sc, "calibration of channel %u failed\n",
2285 ieee80211_frequency_to_channel(
2286 sc->curchan->center_freq));
2287
2288 /* Noise floor calibration interrupts rx/tx path while I/Q calibration
2289 * doesn't.
2290 * TODO: We should stop TX here, so that it doesn't interfere.
2291 * Note that stopping the queues is not enough to stop TX! */
2292 if (time_is_before_eq_jiffies(ah->ah_cal_next_nf)) {
2293 ah->ah_cal_next_nf = jiffies +
2294 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_NF);
2295 ath5k_hw_update_noise_floor(ah);
2296 }
2297
2298 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL;
2299 }
2300
2301
2302 static void
2303 ath5k_tasklet_ani(unsigned long data)
2304 {
2305 struct ath5k_softc *sc = (void *)data;
2306 struct ath5k_hw *ah = sc->ah;
2307
2308 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI;
2309 ath5k_ani_calibration(ah);
2310 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI;
2311 }
2312
2313
2314 static void
2315 ath5k_tx_complete_poll_work(struct work_struct *work)
2316 {
2317 struct ath5k_softc *sc = container_of(work, struct ath5k_softc,
2318 tx_complete_work.work);
2319 struct ath5k_txq *txq;
2320 int i;
2321 bool needreset = false;
2322
2323 mutex_lock(&sc->lock);
2324
2325 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) {
2326 if (sc->txqs[i].setup) {
2327 txq = &sc->txqs[i];
2328 spin_lock_bh(&txq->lock);
2329 if (txq->txq_len > 1) {
2330 if (txq->txq_poll_mark) {
2331 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT,
2332 "TX queue stuck %d\n",
2333 txq->qnum);
2334 needreset = true;
2335 txq->txq_stuck++;
2336 spin_unlock_bh(&txq->lock);
2337 break;
2338 } else {
2339 txq->txq_poll_mark = true;
2340 }
2341 }
2342 spin_unlock_bh(&txq->lock);
2343 }
2344 }
2345
2346 if (needreset) {
2347 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2348 "TX queues stuck, resetting\n");
2349 ath5k_reset(sc, NULL, true);
2350 }
2351
2352 mutex_unlock(&sc->lock);
2353
2354 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2355 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2356 }
2357
2358
2359 /*************************\
2360 * Initialization routines *
2361 \*************************/
2362
2363 int __devinit
2364 ath5k_init_softc(struct ath5k_softc *sc, const struct ath_bus_ops *bus_ops)
2365 {
2366 struct ieee80211_hw *hw = sc->hw;
2367 struct ath_common *common;
2368 int ret;
2369 int csz;
2370
2371 /* Initialize driver private data */
2372 SET_IEEE80211_DEV(hw, sc->dev);
2373 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
2374 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2375 IEEE80211_HW_SIGNAL_DBM |
2376 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
2377
2378 hw->wiphy->interface_modes =
2379 BIT(NL80211_IFTYPE_AP) |
2380 BIT(NL80211_IFTYPE_STATION) |
2381 BIT(NL80211_IFTYPE_ADHOC) |
2382 BIT(NL80211_IFTYPE_MESH_POINT);
2383
2384 /* both antennas can be configured as RX or TX */
2385 hw->wiphy->available_antennas_tx = 0x3;
2386 hw->wiphy->available_antennas_rx = 0x3;
2387
2388 hw->extra_tx_headroom = 2;
2389 hw->channel_change_time = 5000;
2390
2391 /*
2392 * Mark the device as detached to avoid processing
2393 * interrupts until setup is complete.
2394 */
2395 __set_bit(ATH_STAT_INVALID, sc->status);
2396
2397 sc->opmode = NL80211_IFTYPE_STATION;
2398 sc->bintval = 1000;
2399 mutex_init(&sc->lock);
2400 spin_lock_init(&sc->rxbuflock);
2401 spin_lock_init(&sc->txbuflock);
2402 spin_lock_init(&sc->block);
2403 spin_lock_init(&sc->irqlock);
2404
2405 /* Setup interrupt handler */
2406 ret = request_irq(sc->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
2407 if (ret) {
2408 ATH5K_ERR(sc, "request_irq failed\n");
2409 goto err;
2410 }
2411
2412 /* If we passed the test, malloc an ath5k_hw struct */
2413 sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
2414 if (!sc->ah) {
2415 ret = -ENOMEM;
2416 ATH5K_ERR(sc, "out of memory\n");
2417 goto err_irq;
2418 }
2419
2420 sc->ah->ah_sc = sc;
2421 sc->ah->ah_iobase = sc->iobase;
2422 common = ath5k_hw_common(sc->ah);
2423 common->ops = &ath5k_common_ops;
2424 common->bus_ops = bus_ops;
2425 common->ah = sc->ah;
2426 common->hw = hw;
2427 common->priv = sc;
2428 common->clockrate = 40;
2429
2430 /*
2431 * Cache line size is used to size and align various
2432 * structures used to communicate with the hardware.
2433 */
2434 ath5k_read_cachesize(common, &csz);
2435 common->cachelsz = csz << 2; /* convert to bytes */
2436
2437 spin_lock_init(&common->cc_lock);
2438
2439 /* Initialize device */
2440 ret = ath5k_hw_init(sc);
2441 if (ret)
2442 goto err_free_ah;
2443
2444 /* set up multi-rate retry capabilities */
2445 if (sc->ah->ah_version == AR5K_AR5212) {
2446 hw->max_rates = 4;
2447 hw->max_rate_tries = max(AR5K_INIT_RETRY_SHORT,
2448 AR5K_INIT_RETRY_LONG);
2449 }
2450
2451 hw->vif_data_size = sizeof(struct ath5k_vif);
2452
2453 /* Finish private driver data initialization */
2454 ret = ath5k_init(hw);
2455 if (ret)
2456 goto err_ah;
2457
2458 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
2459 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
2460 sc->ah->ah_mac_srev,
2461 sc->ah->ah_phy_revision);
2462
2463 if (!sc->ah->ah_single_chip) {
2464 /* Single chip radio (!RF5111) */
2465 if (sc->ah->ah_radio_5ghz_revision &&
2466 !sc->ah->ah_radio_2ghz_revision) {
2467 /* No 5GHz support -> report 2GHz radio */
2468 if (!test_bit(AR5K_MODE_11A,
2469 sc->ah->ah_capabilities.cap_mode)) {
2470 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
2471 ath5k_chip_name(AR5K_VERSION_RAD,
2472 sc->ah->ah_radio_5ghz_revision),
2473 sc->ah->ah_radio_5ghz_revision);
2474 /* No 2GHz support (5110 and some
2475 * 5GHz only cards) -> report 5GHz radio */
2476 } else if (!test_bit(AR5K_MODE_11B,
2477 sc->ah->ah_capabilities.cap_mode)) {
2478 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
2479 ath5k_chip_name(AR5K_VERSION_RAD,
2480 sc->ah->ah_radio_5ghz_revision),
2481 sc->ah->ah_radio_5ghz_revision);
2482 /* Multiband radio */
2483 } else {
2484 ATH5K_INFO(sc, "RF%s multiband radio found"
2485 " (0x%x)\n",
2486 ath5k_chip_name(AR5K_VERSION_RAD,
2487 sc->ah->ah_radio_5ghz_revision),
2488 sc->ah->ah_radio_5ghz_revision);
2489 }
2490 }
2491 /* Multi chip radio (RF5111 - RF2111) ->
2492 * report both 2GHz/5GHz radios */
2493 else if (sc->ah->ah_radio_5ghz_revision &&
2494 sc->ah->ah_radio_2ghz_revision) {
2495 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
2496 ath5k_chip_name(AR5K_VERSION_RAD,
2497 sc->ah->ah_radio_5ghz_revision),
2498 sc->ah->ah_radio_5ghz_revision);
2499 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
2500 ath5k_chip_name(AR5K_VERSION_RAD,
2501 sc->ah->ah_radio_2ghz_revision),
2502 sc->ah->ah_radio_2ghz_revision);
2503 }
2504 }
2505
2506 ath5k_debug_init_device(sc);
2507
2508 /* ready to process interrupts */
2509 __clear_bit(ATH_STAT_INVALID, sc->status);
2510
2511 return 0;
2512 err_ah:
2513 ath5k_hw_deinit(sc->ah);
2514 err_free_ah:
2515 kfree(sc->ah);
2516 err_irq:
2517 free_irq(sc->irq, sc);
2518 err:
2519 return ret;
2520 }
2521
2522 static int
2523 ath5k_stop_locked(struct ath5k_softc *sc)
2524 {
2525 struct ath5k_hw *ah = sc->ah;
2526
2527 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2528 test_bit(ATH_STAT_INVALID, sc->status));
2529
2530 /*
2531 * Shutdown the hardware and driver:
2532 * stop output from above
2533 * disable interrupts
2534 * turn off timers
2535 * turn off the radio
2536 * clear transmit machinery
2537 * clear receive machinery
2538 * drain and release tx queues
2539 * reclaim beacon resources
2540 * power down hardware
2541 *
2542 * Note that some of this work is not possible if the
2543 * hardware is gone (invalid).
2544 */
2545 ieee80211_stop_queues(sc->hw);
2546
2547 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2548 ath5k_led_off(sc);
2549 ath5k_hw_set_imr(ah, 0);
2550 synchronize_irq(sc->irq);
2551 ath5k_rx_stop(sc);
2552 ath5k_hw_dma_stop(ah);
2553 ath5k_drain_tx_buffs(sc);
2554 ath5k_hw_phy_disable(ah);
2555 }
2556
2557 return 0;
2558 }
2559
2560 int
2561 ath5k_init_hw(struct ath5k_softc *sc)
2562 {
2563 struct ath5k_hw *ah = sc->ah;
2564 struct ath_common *common = ath5k_hw_common(ah);
2565 int ret, i;
2566
2567 mutex_lock(&sc->lock);
2568
2569 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2570
2571 /*
2572 * Stop anything previously setup. This is safe
2573 * no matter this is the first time through or not.
2574 */
2575 ath5k_stop_locked(sc);
2576
2577 /*
2578 * The basic interface to setting the hardware in a good
2579 * state is ``reset''. On return the hardware is known to
2580 * be powered up and with interrupts disabled. This must
2581 * be followed by initialization of the appropriate bits
2582 * and then setup of the interrupt mask.
2583 */
2584 sc->curchan = sc->hw->conf.channel;
2585 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2586 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2587 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
2588
2589 ret = ath5k_reset(sc, NULL, false);
2590 if (ret)
2591 goto done;
2592
2593 ath5k_rfkill_hw_start(ah);
2594
2595 /*
2596 * Reset the key cache since some parts do not reset the
2597 * contents on initial power up or resume from suspend.
2598 */
2599 for (i = 0; i < common->keymax; i++)
2600 ath_hw_keyreset(common, (u16) i);
2601
2602 /* Use higher rates for acks instead of base
2603 * rate */
2604 ah->ah_ack_bitrate_high = true;
2605
2606 for (i = 0; i < ARRAY_SIZE(sc->bslot); i++)
2607 sc->bslot[i] = NULL;
2608
2609 ret = 0;
2610 done:
2611 mmiowb();
2612 mutex_unlock(&sc->lock);
2613
2614 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2615 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2616
2617 return ret;
2618 }
2619
2620 static void ath5k_stop_tasklets(struct ath5k_softc *sc)
2621 {
2622 sc->rx_pending = false;
2623 sc->tx_pending = false;
2624 tasklet_kill(&sc->rxtq);
2625 tasklet_kill(&sc->txtq);
2626 tasklet_kill(&sc->calib);
2627 tasklet_kill(&sc->beacontq);
2628 tasklet_kill(&sc->ani_tasklet);
2629 }
2630
2631 /*
2632 * Stop the device, grabbing the top-level lock to protect
2633 * against concurrent entry through ath5k_init (which can happen
2634 * if another thread does a system call and the thread doing the
2635 * stop is preempted).
2636 */
2637 int
2638 ath5k_stop_hw(struct ath5k_softc *sc)
2639 {
2640 int ret;
2641
2642 mutex_lock(&sc->lock);
2643 ret = ath5k_stop_locked(sc);
2644 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2645 /*
2646 * Don't set the card in full sleep mode!
2647 *
2648 * a) When the device is in this state it must be carefully
2649 * woken up or references to registers in the PCI clock
2650 * domain may freeze the bus (and system). This varies
2651 * by chip and is mostly an issue with newer parts
2652 * (madwifi sources mentioned srev >= 0x78) that go to
2653 * sleep more quickly.
2654 *
2655 * b) On older chips full sleep results a weird behaviour
2656 * during wakeup. I tested various cards with srev < 0x78
2657 * and they don't wake up after module reload, a second
2658 * module reload is needed to bring the card up again.
2659 *
2660 * Until we figure out what's going on don't enable
2661 * full chip reset on any chip (this is what Legacy HAL
2662 * and Sam's HAL do anyway). Instead Perform a full reset
2663 * on the device (same as initial state after attach) and
2664 * leave it idle (keep MAC/BB on warm reset) */
2665 ret = ath5k_hw_on_hold(sc->ah);
2666
2667 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2668 "putting device to sleep\n");
2669 }
2670
2671 mmiowb();
2672 mutex_unlock(&sc->lock);
2673
2674 ath5k_stop_tasklets(sc);
2675
2676 cancel_delayed_work_sync(&sc->tx_complete_work);
2677
2678 ath5k_rfkill_hw_stop(sc->ah);
2679
2680 return ret;
2681 }
2682
2683 /*
2684 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2685 * and change to the given channel.
2686 *
2687 * This should be called with sc->lock.
2688 */
2689 static int
2690 ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan,
2691 bool skip_pcu)
2692 {
2693 struct ath5k_hw *ah = sc->ah;
2694 struct ath_common *common = ath5k_hw_common(ah);
2695 int ret, ani_mode;
2696 bool fast;
2697
2698 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
2699
2700 ath5k_hw_set_imr(ah, 0);
2701 synchronize_irq(sc->irq);
2702 ath5k_stop_tasklets(sc);
2703
2704 /* Save ani mode and disable ANI during
2705 * reset. If we don't we might get false
2706 * PHY error interrupts. */
2707 ani_mode = ah->ah_sc->ani_state.ani_mode;
2708 ath5k_ani_init(ah, ATH5K_ANI_MODE_OFF);
2709
2710 /* We are going to empty hw queues
2711 * so we should also free any remaining
2712 * tx buffers */
2713 ath5k_drain_tx_buffs(sc);
2714 if (chan)
2715 sc->curchan = chan;
2716
2717 fast = ((chan != NULL) && modparam_fastchanswitch) ? 1 : 0;
2718
2719 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, fast, skip_pcu);
2720 if (ret) {
2721 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2722 goto err;
2723 }
2724
2725 ret = ath5k_rx_start(sc);
2726 if (ret) {
2727 ATH5K_ERR(sc, "can't start recv logic\n");
2728 goto err;
2729 }
2730
2731 ath5k_ani_init(ah, ani_mode);
2732
2733 ah->ah_cal_next_full = jiffies + msecs_to_jiffies(100);
2734 ah->ah_cal_next_ani = jiffies;
2735 ah->ah_cal_next_nf = jiffies;
2736 ewma_init(&ah->ah_beacon_rssi_avg, 1024, 8);
2737
2738 /* clear survey data and cycle counters */
2739 memset(&sc->survey, 0, sizeof(sc->survey));
2740 spin_lock_bh(&common->cc_lock);
2741 ath_hw_cycle_counters_update(common);
2742 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
2743 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
2744 spin_unlock_bh(&common->cc_lock);
2745
2746 /*
2747 * Change channels and update the h/w rate map if we're switching;
2748 * e.g. 11a to 11b/g.
2749 *
2750 * We may be doing a reset in response to an ioctl that changes the
2751 * channel so update any state that might change as a result.
2752 *
2753 * XXX needed?
2754 */
2755 /* ath5k_chan_change(sc, c); */
2756
2757 ath5k_beacon_config(sc);
2758 /* intrs are enabled by ath5k_beacon_config */
2759
2760 ieee80211_wake_queues(sc->hw);
2761
2762 return 0;
2763 err:
2764 return ret;
2765 }
2766
2767 static void ath5k_reset_work(struct work_struct *work)
2768 {
2769 struct ath5k_softc *sc = container_of(work, struct ath5k_softc,
2770 reset_work);
2771
2772 mutex_lock(&sc->lock);
2773 ath5k_reset(sc, NULL, true);
2774 mutex_unlock(&sc->lock);
2775 }
2776
2777 static int __devinit
2778 ath5k_init(struct ieee80211_hw *hw)
2779 {
2780
2781 struct ath5k_softc *sc = hw->priv;
2782 struct ath5k_hw *ah = sc->ah;
2783 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
2784 struct ath5k_txq *txq;
2785 u8 mac[ETH_ALEN] = {};
2786 int ret;
2787
2788
2789 /*
2790 * Check if the MAC has multi-rate retry support.
2791 * We do this by trying to setup a fake extended
2792 * descriptor. MACs that don't have support will
2793 * return false w/o doing anything. MACs that do
2794 * support it will return true w/o doing anything.
2795 */
2796 ret = ath5k_hw_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
2797
2798 if (ret < 0)
2799 goto err;
2800 if (ret > 0)
2801 __set_bit(ATH_STAT_MRRETRY, sc->status);
2802
2803 /*
2804 * Collect the channel list. The 802.11 layer
2805 * is responsible for filtering this list based
2806 * on settings like the phy mode and regulatory
2807 * domain restrictions.
2808 */
2809 ret = ath5k_setup_bands(hw);
2810 if (ret) {
2811 ATH5K_ERR(sc, "can't get channels\n");
2812 goto err;
2813 }
2814
2815 /*
2816 * Allocate tx+rx descriptors and populate the lists.
2817 */
2818 ret = ath5k_desc_alloc(sc);
2819 if (ret) {
2820 ATH5K_ERR(sc, "can't allocate descriptors\n");
2821 goto err;
2822 }
2823
2824 /*
2825 * Allocate hardware transmit queues: one queue for
2826 * beacon frames and one data queue for each QoS
2827 * priority. Note that hw functions handle resetting
2828 * these queues at the needed time.
2829 */
2830 ret = ath5k_beaconq_setup(ah);
2831 if (ret < 0) {
2832 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
2833 goto err_desc;
2834 }
2835 sc->bhalq = ret;
2836 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0);
2837 if (IS_ERR(sc->cabq)) {
2838 ATH5K_ERR(sc, "can't setup cab queue\n");
2839 ret = PTR_ERR(sc->cabq);
2840 goto err_bhal;
2841 }
2842
2843 /* 5211 and 5212 usually support 10 queues but we better rely on the
2844 * capability information */
2845 if (ah->ah_capabilities.cap_queues.q_tx_num >= 6) {
2846 /* This order matches mac80211's queue priority, so we can
2847 * directly use the mac80211 queue number without any mapping */
2848 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO);
2849 if (IS_ERR(txq)) {
2850 ATH5K_ERR(sc, "can't setup xmit queue\n");
2851 ret = PTR_ERR(txq);
2852 goto err_queues;
2853 }
2854 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI);
2855 if (IS_ERR(txq)) {
2856 ATH5K_ERR(sc, "can't setup xmit queue\n");
2857 ret = PTR_ERR(txq);
2858 goto err_queues;
2859 }
2860 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
2861 if (IS_ERR(txq)) {
2862 ATH5K_ERR(sc, "can't setup xmit queue\n");
2863 ret = PTR_ERR(txq);
2864 goto err_queues;
2865 }
2866 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
2867 if (IS_ERR(txq)) {
2868 ATH5K_ERR(sc, "can't setup xmit queue\n");
2869 ret = PTR_ERR(txq);
2870 goto err_queues;
2871 }
2872 hw->queues = 4;
2873 } else {
2874 /* older hardware (5210) can only support one data queue */
2875 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
2876 if (IS_ERR(txq)) {
2877 ATH5K_ERR(sc, "can't setup xmit queue\n");
2878 ret = PTR_ERR(txq);
2879 goto err_queues;
2880 }
2881 hw->queues = 1;
2882 }
2883
2884 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
2885 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
2886 tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc);
2887 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
2888 tasklet_init(&sc->ani_tasklet, ath5k_tasklet_ani, (unsigned long)sc);
2889
2890 INIT_WORK(&sc->reset_work, ath5k_reset_work);
2891 INIT_DELAYED_WORK(&sc->tx_complete_work, ath5k_tx_complete_poll_work);
2892
2893 ret = ath5k_hw_common(ah)->bus_ops->eeprom_read_mac(ah, mac);
2894 if (ret) {
2895 ATH5K_ERR(sc, "unable to read address from EEPROM\n");
2896 goto err_queues;
2897 }
2898
2899 SET_IEEE80211_PERM_ADDR(hw, mac);
2900 memcpy(&sc->lladdr, mac, ETH_ALEN);
2901 /* All MAC address bits matter for ACKs */
2902 ath5k_update_bssid_mask_and_opmode(sc, NULL);
2903
2904 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
2905 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
2906 if (ret) {
2907 ATH5K_ERR(sc, "can't initialize regulatory system\n");
2908 goto err_queues;
2909 }
2910
2911 ret = ieee80211_register_hw(hw);
2912 if (ret) {
2913 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
2914 goto err_queues;
2915 }
2916
2917 if (!ath_is_world_regd(regulatory))
2918 regulatory_hint(hw->wiphy, regulatory->alpha2);
2919
2920 ath5k_init_leds(sc);
2921
2922 ath5k_sysfs_register(sc);
2923
2924 return 0;
2925 err_queues:
2926 ath5k_txq_release(sc);
2927 err_bhal:
2928 ath5k_hw_release_tx_queue(ah, sc->bhalq);
2929 err_desc:
2930 ath5k_desc_free(sc);
2931 err:
2932 return ret;
2933 }
2934
2935 void
2936 ath5k_deinit_softc(struct ath5k_softc *sc)
2937 {
2938 struct ieee80211_hw *hw = sc->hw;
2939
2940 /*
2941 * NB: the order of these is important:
2942 * o call the 802.11 layer before detaching ath5k_hw to
2943 * ensure callbacks into the driver to delete global
2944 * key cache entries can be handled
2945 * o reclaim the tx queue data structures after calling
2946 * the 802.11 layer as we'll get called back to reclaim
2947 * node state and potentially want to use them
2948 * o to cleanup the tx queues the hal is called, so detach
2949 * it last
2950 * XXX: ??? detach ath5k_hw ???
2951 * Other than that, it's straightforward...
2952 */
2953 ieee80211_unregister_hw(hw);
2954 ath5k_desc_free(sc);
2955 ath5k_txq_release(sc);
2956 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
2957 ath5k_unregister_leds(sc);
2958
2959 ath5k_sysfs_unregister(sc);
2960 /*
2961 * NB: can't reclaim these until after ieee80211_ifdetach
2962 * returns because we'll get called back to reclaim node
2963 * state and potentially want to use them.
2964 */
2965 ath5k_hw_deinit(sc->ah);
2966 kfree(sc->ah);
2967 free_irq(sc->irq, sc);
2968 }
2969
2970 bool
2971 ath5k_any_vif_assoc(struct ath5k_softc *sc)
2972 {
2973 struct ath5k_vif_iter_data iter_data;
2974 iter_data.hw_macaddr = NULL;
2975 iter_data.any_assoc = false;
2976 iter_data.need_set_hw_addr = false;
2977 iter_data.found_active = true;
2978
2979 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath5k_vif_iter,
2980 &iter_data);
2981 return iter_data.any_assoc;
2982 }
2983
2984 void
2985 ath5k_set_beacon_filter(struct ieee80211_hw *hw, bool enable)
2986 {
2987 struct ath5k_softc *sc = hw->priv;
2988 struct ath5k_hw *ah = sc->ah;
2989 u32 rfilt;
2990 rfilt = ath5k_hw_get_rx_filter(ah);
2991 if (enable)
2992 rfilt |= AR5K_RX_FILTER_BEACON;
2993 else
2994 rfilt &= ~AR5K_RX_FILTER_BEACON;
2995 ath5k_hw_set_rx_filter(ah, rfilt);
2996 sc->filter_flags = rfilt;
2997 }
Linux kernel - Deliverables
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