2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
43 #include <linux/module.h>
44 #include <linux/delay.h>
45 #include <linux/hardirq.h>
48 #include <linux/netdevice.h>
49 #include <linux/cache.h>
50 #include <linux/ethtool.h>
51 #include <linux/uaccess.h>
52 #include <linux/slab.h>
53 #include <linux/etherdevice.h>
55 #include <net/ieee80211_radiotap.h>
57 #include <asm/unaligned.h>
64 #define CREATE_TRACE_POINTS
67 int ath5k_modparam_nohwcrypt
;
68 module_param_named(nohwcrypt
, ath5k_modparam_nohwcrypt
, bool, S_IRUGO
);
69 MODULE_PARM_DESC(nohwcrypt
, "Disable hardware encryption.");
71 static int modparam_all_channels
;
72 module_param_named(all_channels
, modparam_all_channels
, bool, S_IRUGO
);
73 MODULE_PARM_DESC(all_channels
, "Expose all channels the device can use.");
76 MODULE_AUTHOR("Jiri Slaby");
77 MODULE_AUTHOR("Nick Kossifidis");
78 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
79 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
80 MODULE_LICENSE("Dual BSD/GPL");
82 static int ath5k_init(struct ieee80211_hw
*hw
);
83 static int ath5k_reset(struct ath5k_softc
*sc
, struct ieee80211_channel
*chan
,
85 int ath5k_beacon_update(struct ieee80211_hw
*hw
, struct ieee80211_vif
*vif
);
86 void ath5k_beacon_update_timers(struct ath5k_softc
*sc
, u64 bc_tsf
);
89 static const struct ath5k_srev_name srev_names
[] = {
90 #ifdef CONFIG_ATHEROS_AR231X
91 { "5312", AR5K_VERSION_MAC
, AR5K_SREV_AR5312_R2
},
92 { "5312", AR5K_VERSION_MAC
, AR5K_SREV_AR5312_R7
},
93 { "2313", AR5K_VERSION_MAC
, AR5K_SREV_AR2313_R8
},
94 { "2315", AR5K_VERSION_MAC
, AR5K_SREV_AR2315_R6
},
95 { "2315", AR5K_VERSION_MAC
, AR5K_SREV_AR2315_R7
},
96 { "2317", AR5K_VERSION_MAC
, AR5K_SREV_AR2317_R1
},
97 { "2317", AR5K_VERSION_MAC
, AR5K_SREV_AR2317_R2
},
99 { "5210", AR5K_VERSION_MAC
, AR5K_SREV_AR5210
},
100 { "5311", AR5K_VERSION_MAC
, AR5K_SREV_AR5311
},
101 { "5311A", AR5K_VERSION_MAC
, AR5K_SREV_AR5311A
},
102 { "5311B", AR5K_VERSION_MAC
, AR5K_SREV_AR5311B
},
103 { "5211", AR5K_VERSION_MAC
, AR5K_SREV_AR5211
},
104 { "5212", AR5K_VERSION_MAC
, AR5K_SREV_AR5212
},
105 { "5213", AR5K_VERSION_MAC
, AR5K_SREV_AR5213
},
106 { "5213A", AR5K_VERSION_MAC
, AR5K_SREV_AR5213A
},
107 { "2413", AR5K_VERSION_MAC
, AR5K_SREV_AR2413
},
108 { "2414", AR5K_VERSION_MAC
, AR5K_SREV_AR2414
},
109 { "5424", AR5K_VERSION_MAC
, AR5K_SREV_AR5424
},
110 { "5413", AR5K_VERSION_MAC
, AR5K_SREV_AR5413
},
111 { "5414", AR5K_VERSION_MAC
, AR5K_SREV_AR5414
},
112 { "2415", AR5K_VERSION_MAC
, AR5K_SREV_AR2415
},
113 { "5416", AR5K_VERSION_MAC
, AR5K_SREV_AR5416
},
114 { "5418", AR5K_VERSION_MAC
, AR5K_SREV_AR5418
},
115 { "2425", AR5K_VERSION_MAC
, AR5K_SREV_AR2425
},
116 { "2417", AR5K_VERSION_MAC
, AR5K_SREV_AR2417
},
118 { "xxxxx", AR5K_VERSION_MAC
, AR5K_SREV_UNKNOWN
},
119 { "5110", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5110
},
120 { "5111", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5111
},
121 { "5111A", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5111A
},
122 { "2111", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2111
},
123 { "5112", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5112
},
124 { "5112A", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5112A
},
125 { "5112B", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5112B
},
126 { "2112", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2112
},
127 { "2112A", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2112A
},
128 { "2112B", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2112B
},
129 { "2413", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2413
},
130 { "5413", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5413
},
131 { "5424", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5424
},
132 { "5133", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5133
},
133 #ifdef CONFIG_ATHEROS_AR231X
134 { "2316", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2316
},
135 { "2317", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2317
},
137 { "xxxxx", AR5K_VERSION_RAD
, AR5K_SREV_UNKNOWN
},
140 static const struct ieee80211_rate ath5k_rates
[] = {
142 .hw_value
= ATH5K_RATE_CODE_1M
, },
144 .hw_value
= ATH5K_RATE_CODE_2M
,
145 .hw_value_short
= ATH5K_RATE_CODE_2M
| AR5K_SET_SHORT_PREAMBLE
,
146 .flags
= IEEE80211_RATE_SHORT_PREAMBLE
},
148 .hw_value
= ATH5K_RATE_CODE_5_5M
,
149 .hw_value_short
= ATH5K_RATE_CODE_5_5M
| AR5K_SET_SHORT_PREAMBLE
,
150 .flags
= IEEE80211_RATE_SHORT_PREAMBLE
},
152 .hw_value
= ATH5K_RATE_CODE_11M
,
153 .hw_value_short
= ATH5K_RATE_CODE_11M
| AR5K_SET_SHORT_PREAMBLE
,
154 .flags
= IEEE80211_RATE_SHORT_PREAMBLE
},
156 .hw_value
= ATH5K_RATE_CODE_6M
,
159 .hw_value
= ATH5K_RATE_CODE_9M
,
162 .hw_value
= ATH5K_RATE_CODE_12M
,
165 .hw_value
= ATH5K_RATE_CODE_18M
,
168 .hw_value
= ATH5K_RATE_CODE_24M
,
171 .hw_value
= ATH5K_RATE_CODE_36M
,
174 .hw_value
= ATH5K_RATE_CODE_48M
,
177 .hw_value
= ATH5K_RATE_CODE_54M
,
182 static inline u64
ath5k_extend_tsf(struct ath5k_hw
*ah
, u32 rstamp
)
184 u64 tsf
= ath5k_hw_get_tsf64(ah
);
186 if ((tsf
& 0x7fff) < rstamp
)
189 return (tsf
& ~0x7fff) | rstamp
;
193 ath5k_chip_name(enum ath5k_srev_type type
, u_int16_t val
)
195 const char *name
= "xxxxx";
198 for (i
= 0; i
< ARRAY_SIZE(srev_names
); i
++) {
199 if (srev_names
[i
].sr_type
!= type
)
202 if ((val
& 0xf0) == srev_names
[i
].sr_val
)
203 name
= srev_names
[i
].sr_name
;
205 if ((val
& 0xff) == srev_names
[i
].sr_val
) {
206 name
= srev_names
[i
].sr_name
;
213 static unsigned int ath5k_ioread32(void *hw_priv
, u32 reg_offset
)
215 struct ath5k_hw
*ah
= (struct ath5k_hw
*) hw_priv
;
216 return ath5k_hw_reg_read(ah
, reg_offset
);
219 static void ath5k_iowrite32(void *hw_priv
, u32 val
, u32 reg_offset
)
221 struct ath5k_hw
*ah
= (struct ath5k_hw
*) hw_priv
;
222 ath5k_hw_reg_write(ah
, val
, reg_offset
);
225 static const struct ath_ops ath5k_common_ops
= {
226 .read
= ath5k_ioread32
,
227 .write
= ath5k_iowrite32
,
230 /***********************\
231 * Driver Initialization *
232 \***********************/
234 static int ath5k_reg_notifier(struct wiphy
*wiphy
, struct regulatory_request
*request
)
236 struct ieee80211_hw
*hw
= wiphy_to_ieee80211_hw(wiphy
);
237 struct ath5k_softc
*sc
= hw
->priv
;
238 struct ath_regulatory
*regulatory
= ath5k_hw_regulatory(sc
->ah
);
240 return ath_reg_notifier_apply(wiphy
, request
, regulatory
);
243 /********************\
244 * Channel/mode setup *
245 \********************/
248 * Returns true for the channel numbers used without all_channels modparam.
250 static bool ath5k_is_standard_channel(short chan
, enum ieee80211_band band
)
252 if (band
== IEEE80211_BAND_2GHZ
&& chan
<= 14)
255 return /* UNII 1,2 */
256 (((chan
& 3) == 0 && chan
>= 36 && chan
<= 64) ||
258 ((chan
& 3) == 0 && chan
>= 100 && chan
<= 140) ||
260 ((chan
& 3) == 1 && chan
>= 149 && chan
<= 165) ||
261 /* 802.11j 5.030-5.080 GHz (20MHz) */
262 (chan
== 8 || chan
== 12 || chan
== 16) ||
263 /* 802.11j 4.9GHz (20MHz) */
264 (chan
== 184 || chan
== 188 || chan
== 192 || chan
== 196));
268 ath5k_setup_channels(struct ath5k_hw
*ah
, struct ieee80211_channel
*channels
,
269 unsigned int mode
, unsigned int max
)
271 unsigned int count
, size
, chfreq
, freq
, ch
;
272 enum ieee80211_band band
;
276 /* 1..220, but 2GHz frequencies are filtered by check_channel */
278 chfreq
= CHANNEL_5GHZ
;
279 band
= IEEE80211_BAND_5GHZ
;
284 chfreq
= CHANNEL_2GHZ
;
285 band
= IEEE80211_BAND_2GHZ
;
288 ATH5K_WARN(ah
->ah_sc
, "bad mode, not copying channels\n");
293 for (ch
= 1; ch
<= size
&& count
< max
; ch
++) {
294 freq
= ieee80211_channel_to_frequency(ch
, band
);
296 if (freq
== 0) /* mapping failed - not a standard channel */
299 /* Check if channel is supported by the chipset */
300 if (!ath5k_channel_ok(ah
, freq
, chfreq
))
303 if (!modparam_all_channels
&&
304 !ath5k_is_standard_channel(ch
, band
))
307 /* Write channel info and increment counter */
308 channels
[count
].center_freq
= freq
;
309 channels
[count
].band
= band
;
313 channels
[count
].hw_value
= chfreq
| CHANNEL_OFDM
;
316 channels
[count
].hw_value
= CHANNEL_B
;
326 ath5k_setup_rate_idx(struct ath5k_softc
*sc
, struct ieee80211_supported_band
*b
)
330 for (i
= 0; i
< AR5K_MAX_RATES
; i
++)
331 sc
->rate_idx
[b
->band
][i
] = -1;
333 for (i
= 0; i
< b
->n_bitrates
; i
++) {
334 sc
->rate_idx
[b
->band
][b
->bitrates
[i
].hw_value
] = i
;
335 if (b
->bitrates
[i
].hw_value_short
)
336 sc
->rate_idx
[b
->band
][b
->bitrates
[i
].hw_value_short
] = i
;
341 ath5k_setup_bands(struct ieee80211_hw
*hw
)
343 struct ath5k_softc
*sc
= hw
->priv
;
344 struct ath5k_hw
*ah
= sc
->ah
;
345 struct ieee80211_supported_band
*sband
;
346 int max_c
, count_c
= 0;
349 BUILD_BUG_ON(ARRAY_SIZE(sc
->sbands
) < IEEE80211_NUM_BANDS
);
350 max_c
= ARRAY_SIZE(sc
->channels
);
353 sband
= &sc
->sbands
[IEEE80211_BAND_2GHZ
];
354 sband
->band
= IEEE80211_BAND_2GHZ
;
355 sband
->bitrates
= &sc
->rates
[IEEE80211_BAND_2GHZ
][0];
357 if (test_bit(AR5K_MODE_11G
, sc
->ah
->ah_capabilities
.cap_mode
)) {
359 memcpy(sband
->bitrates
, &ath5k_rates
[0],
360 sizeof(struct ieee80211_rate
) * 12);
361 sband
->n_bitrates
= 12;
363 sband
->channels
= sc
->channels
;
364 sband
->n_channels
= ath5k_setup_channels(ah
, sband
->channels
,
365 AR5K_MODE_11G
, max_c
);
367 hw
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] = sband
;
368 count_c
= sband
->n_channels
;
370 } else if (test_bit(AR5K_MODE_11B
, sc
->ah
->ah_capabilities
.cap_mode
)) {
372 memcpy(sband
->bitrates
, &ath5k_rates
[0],
373 sizeof(struct ieee80211_rate
) * 4);
374 sband
->n_bitrates
= 4;
376 /* 5211 only supports B rates and uses 4bit rate codes
377 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
380 if (ah
->ah_version
== AR5K_AR5211
) {
381 for (i
= 0; i
< 4; i
++) {
382 sband
->bitrates
[i
].hw_value
=
383 sband
->bitrates
[i
].hw_value
& 0xF;
384 sband
->bitrates
[i
].hw_value_short
=
385 sband
->bitrates
[i
].hw_value_short
& 0xF;
389 sband
->channels
= sc
->channels
;
390 sband
->n_channels
= ath5k_setup_channels(ah
, sband
->channels
,
391 AR5K_MODE_11B
, max_c
);
393 hw
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] = sband
;
394 count_c
= sband
->n_channels
;
397 ath5k_setup_rate_idx(sc
, sband
);
399 /* 5GHz band, A mode */
400 if (test_bit(AR5K_MODE_11A
, sc
->ah
->ah_capabilities
.cap_mode
)) {
401 sband
= &sc
->sbands
[IEEE80211_BAND_5GHZ
];
402 sband
->band
= IEEE80211_BAND_5GHZ
;
403 sband
->bitrates
= &sc
->rates
[IEEE80211_BAND_5GHZ
][0];
405 memcpy(sband
->bitrates
, &ath5k_rates
[4],
406 sizeof(struct ieee80211_rate
) * 8);
407 sband
->n_bitrates
= 8;
409 sband
->channels
= &sc
->channels
[count_c
];
410 sband
->n_channels
= ath5k_setup_channels(ah
, sband
->channels
,
411 AR5K_MODE_11A
, max_c
);
413 hw
->wiphy
->bands
[IEEE80211_BAND_5GHZ
] = sband
;
415 ath5k_setup_rate_idx(sc
, sband
);
417 ath5k_debug_dump_bands(sc
);
423 * Set/change channels. We always reset the chip.
424 * To accomplish this we must first cleanup any pending DMA,
425 * then restart stuff after a la ath5k_init.
427 * Called with sc->lock.
430 ath5k_chan_set(struct ath5k_softc
*sc
, struct ieee80211_channel
*chan
)
432 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
,
433 "channel set, resetting (%u -> %u MHz)\n",
434 sc
->curchan
->center_freq
, chan
->center_freq
);
437 * To switch channels clear any pending DMA operations;
438 * wait long enough for the RX fifo to drain, reset the
439 * hardware at the new frequency, and then re-enable
440 * the relevant bits of the h/w.
442 return ath5k_reset(sc
, chan
, true);
445 struct ath_vif_iter_data
{
446 const u8
*hw_macaddr
;
448 u8 active_mac
[ETH_ALEN
]; /* first active MAC */
449 bool need_set_hw_addr
;
452 enum nl80211_iftype opmode
;
455 static void ath_vif_iter(void *data
, u8
*mac
, struct ieee80211_vif
*vif
)
457 struct ath_vif_iter_data
*iter_data
= data
;
459 struct ath5k_vif
*avf
= (void *)vif
->drv_priv
;
461 if (iter_data
->hw_macaddr
)
462 for (i
= 0; i
< ETH_ALEN
; i
++)
463 iter_data
->mask
[i
] &=
464 ~(iter_data
->hw_macaddr
[i
] ^ mac
[i
]);
466 if (!iter_data
->found_active
) {
467 iter_data
->found_active
= true;
468 memcpy(iter_data
->active_mac
, mac
, ETH_ALEN
);
471 if (iter_data
->need_set_hw_addr
&& iter_data
->hw_macaddr
)
472 if (compare_ether_addr(iter_data
->hw_macaddr
, mac
) == 0)
473 iter_data
->need_set_hw_addr
= false;
475 if (!iter_data
->any_assoc
) {
477 iter_data
->any_assoc
= true;
480 /* Calculate combined mode - when APs are active, operate in AP mode.
481 * Otherwise use the mode of the new interface. This can currently
482 * only deal with combinations of APs and STAs. Only one ad-hoc
483 * interfaces is allowed.
485 if (avf
->opmode
== NL80211_IFTYPE_AP
)
486 iter_data
->opmode
= NL80211_IFTYPE_AP
;
488 if (iter_data
->opmode
== NL80211_IFTYPE_UNSPECIFIED
)
489 iter_data
->opmode
= avf
->opmode
;
493 ath5k_update_bssid_mask_and_opmode(struct ath5k_softc
*sc
,
494 struct ieee80211_vif
*vif
)
496 struct ath_common
*common
= ath5k_hw_common(sc
->ah
);
497 struct ath_vif_iter_data iter_data
;
500 * Use the hardware MAC address as reference, the hardware uses it
501 * together with the BSSID mask when matching addresses.
503 iter_data
.hw_macaddr
= common
->macaddr
;
504 memset(&iter_data
.mask
, 0xff, ETH_ALEN
);
505 iter_data
.found_active
= false;
506 iter_data
.need_set_hw_addr
= true;
507 iter_data
.opmode
= NL80211_IFTYPE_UNSPECIFIED
;
510 ath_vif_iter(&iter_data
, vif
->addr
, vif
);
512 /* Get list of all active MAC addresses */
513 ieee80211_iterate_active_interfaces_atomic(sc
->hw
, ath_vif_iter
,
515 memcpy(sc
->bssidmask
, iter_data
.mask
, ETH_ALEN
);
517 sc
->opmode
= iter_data
.opmode
;
518 if (sc
->opmode
== NL80211_IFTYPE_UNSPECIFIED
)
519 /* Nothing active, default to station mode */
520 sc
->opmode
= NL80211_IFTYPE_STATION
;
522 ath5k_hw_set_opmode(sc
->ah
, sc
->opmode
);
523 ATH5K_DBG(sc
, ATH5K_DEBUG_MODE
, "mode setup opmode %d (%s)\n",
524 sc
->opmode
, ath_opmode_to_string(sc
->opmode
));
526 if (iter_data
.need_set_hw_addr
&& iter_data
.found_active
)
527 ath5k_hw_set_lladdr(sc
->ah
, iter_data
.active_mac
);
529 if (ath5k_hw_hasbssidmask(sc
->ah
))
530 ath5k_hw_set_bssid_mask(sc
->ah
, sc
->bssidmask
);
534 ath5k_mode_setup(struct ath5k_softc
*sc
, struct ieee80211_vif
*vif
)
536 struct ath5k_hw
*ah
= sc
->ah
;
539 /* configure rx filter */
540 rfilt
= sc
->filter_flags
;
541 ath5k_hw_set_rx_filter(ah
, rfilt
);
542 ATH5K_DBG(sc
, ATH5K_DEBUG_MODE
, "RX filter 0x%x\n", rfilt
);
544 ath5k_update_bssid_mask_and_opmode(sc
, vif
);
548 ath5k_hw_to_driver_rix(struct ath5k_softc
*sc
, int hw_rix
)
552 /* return base rate on errors */
553 if (WARN(hw_rix
< 0 || hw_rix
>= AR5K_MAX_RATES
,
554 "hw_rix out of bounds: %x\n", hw_rix
))
557 rix
= sc
->rate_idx
[sc
->curchan
->band
][hw_rix
];
558 if (WARN(rix
< 0, "invalid hw_rix: %x\n", hw_rix
))
569 struct sk_buff
*ath5k_rx_skb_alloc(struct ath5k_softc
*sc
, dma_addr_t
*skb_addr
)
571 struct ath_common
*common
= ath5k_hw_common(sc
->ah
);
575 * Allocate buffer with headroom_needed space for the
576 * fake physical layer header at the start.
578 skb
= ath_rxbuf_alloc(common
,
583 ATH5K_ERR(sc
, "can't alloc skbuff of size %u\n",
588 *skb_addr
= dma_map_single(sc
->dev
,
589 skb
->data
, common
->rx_bufsize
,
592 if (unlikely(dma_mapping_error(sc
->dev
, *skb_addr
))) {
593 ATH5K_ERR(sc
, "%s: DMA mapping failed\n", __func__
);
601 ath5k_rxbuf_setup(struct ath5k_softc
*sc
, struct ath5k_buf
*bf
)
603 struct ath5k_hw
*ah
= sc
->ah
;
604 struct sk_buff
*skb
= bf
->skb
;
605 struct ath5k_desc
*ds
;
609 skb
= ath5k_rx_skb_alloc(sc
, &bf
->skbaddr
);
616 * Setup descriptors. For receive we always terminate
617 * the descriptor list with a self-linked entry so we'll
618 * not get overrun under high load (as can happen with a
619 * 5212 when ANI processing enables PHY error frames).
621 * To ensure the last descriptor is self-linked we create
622 * each descriptor as self-linked and add it to the end. As
623 * each additional descriptor is added the previous self-linked
624 * entry is "fixed" naturally. This should be safe even
625 * if DMA is happening. When processing RX interrupts we
626 * never remove/process the last, self-linked, entry on the
627 * descriptor list. This ensures the hardware always has
628 * someplace to write a new frame.
631 ds
->ds_link
= bf
->daddr
; /* link to self */
632 ds
->ds_data
= bf
->skbaddr
;
633 ret
= ath5k_hw_setup_rx_desc(ah
, ds
, ah
->common
.rx_bufsize
, 0);
635 ATH5K_ERR(sc
, "%s: could not setup RX desc\n", __func__
);
639 if (sc
->rxlink
!= NULL
)
640 *sc
->rxlink
= bf
->daddr
;
641 sc
->rxlink
= &ds
->ds_link
;
645 static enum ath5k_pkt_type
get_hw_packet_type(struct sk_buff
*skb
)
647 struct ieee80211_hdr
*hdr
;
648 enum ath5k_pkt_type htype
;
651 hdr
= (struct ieee80211_hdr
*)skb
->data
;
652 fc
= hdr
->frame_control
;
654 if (ieee80211_is_beacon(fc
))
655 htype
= AR5K_PKT_TYPE_BEACON
;
656 else if (ieee80211_is_probe_resp(fc
))
657 htype
= AR5K_PKT_TYPE_PROBE_RESP
;
658 else if (ieee80211_is_atim(fc
))
659 htype
= AR5K_PKT_TYPE_ATIM
;
660 else if (ieee80211_is_pspoll(fc
))
661 htype
= AR5K_PKT_TYPE_PSPOLL
;
663 htype
= AR5K_PKT_TYPE_NORMAL
;
669 ath5k_txbuf_setup(struct ath5k_softc
*sc
, struct ath5k_buf
*bf
,
670 struct ath5k_txq
*txq
, int padsize
)
672 struct ath5k_hw
*ah
= sc
->ah
;
673 struct ath5k_desc
*ds
= bf
->desc
;
674 struct sk_buff
*skb
= bf
->skb
;
675 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
676 unsigned int pktlen
, flags
, keyidx
= AR5K_TXKEYIX_INVALID
;
677 struct ieee80211_rate
*rate
;
678 unsigned int mrr_rate
[3], mrr_tries
[3];
685 flags
= AR5K_TXDESC_INTREQ
| AR5K_TXDESC_CLRDMASK
;
688 bf
->skbaddr
= dma_map_single(sc
->dev
, skb
->data
, skb
->len
,
691 rate
= ieee80211_get_tx_rate(sc
->hw
, info
);
697 if (info
->flags
& IEEE80211_TX_CTL_NO_ACK
)
698 flags
|= AR5K_TXDESC_NOACK
;
700 rc_flags
= info
->control
.rates
[0].flags
;
701 hw_rate
= (rc_flags
& IEEE80211_TX_RC_USE_SHORT_PREAMBLE
) ?
702 rate
->hw_value_short
: rate
->hw_value
;
706 /* FIXME: If we are in g mode and rate is a CCK rate
707 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
708 * from tx power (value is in dB units already) */
709 if (info
->control
.hw_key
) {
710 keyidx
= info
->control
.hw_key
->hw_key_idx
;
711 pktlen
+= info
->control
.hw_key
->icv_len
;
713 if (rc_flags
& IEEE80211_TX_RC_USE_RTS_CTS
) {
714 flags
|= AR5K_TXDESC_RTSENA
;
715 cts_rate
= ieee80211_get_rts_cts_rate(sc
->hw
, info
)->hw_value
;
716 duration
= le16_to_cpu(ieee80211_rts_duration(sc
->hw
,
717 info
->control
.vif
, pktlen
, info
));
719 if (rc_flags
& IEEE80211_TX_RC_USE_CTS_PROTECT
) {
720 flags
|= AR5K_TXDESC_CTSENA
;
721 cts_rate
= ieee80211_get_rts_cts_rate(sc
->hw
, info
)->hw_value
;
722 duration
= le16_to_cpu(ieee80211_ctstoself_duration(sc
->hw
,
723 info
->control
.vif
, pktlen
, info
));
725 ret
= ah
->ah_setup_tx_desc(ah
, ds
, pktlen
,
726 ieee80211_get_hdrlen_from_skb(skb
), padsize
,
727 get_hw_packet_type(skb
),
728 (sc
->power_level
* 2),
730 info
->control
.rates
[0].count
, keyidx
, ah
->ah_tx_ant
, flags
,
735 memset(mrr_rate
, 0, sizeof(mrr_rate
));
736 memset(mrr_tries
, 0, sizeof(mrr_tries
));
737 for (i
= 0; i
< 3; i
++) {
738 rate
= ieee80211_get_alt_retry_rate(sc
->hw
, info
, i
);
742 mrr_rate
[i
] = rate
->hw_value
;
743 mrr_tries
[i
] = info
->control
.rates
[i
+ 1].count
;
746 ath5k_hw_setup_mrr_tx_desc(ah
, ds
,
747 mrr_rate
[0], mrr_tries
[0],
748 mrr_rate
[1], mrr_tries
[1],
749 mrr_rate
[2], mrr_tries
[2]);
752 ds
->ds_data
= bf
->skbaddr
;
754 spin_lock_bh(&txq
->lock
);
755 list_add_tail(&bf
->list
, &txq
->q
);
757 if (txq
->link
== NULL
) /* is this first packet? */
758 ath5k_hw_set_txdp(ah
, txq
->qnum
, bf
->daddr
);
759 else /* no, so only link it */
760 *txq
->link
= bf
->daddr
;
762 txq
->link
= &ds
->ds_link
;
763 ath5k_hw_start_tx_dma(ah
, txq
->qnum
);
765 spin_unlock_bh(&txq
->lock
);
769 dma_unmap_single(sc
->dev
, bf
->skbaddr
, skb
->len
, DMA_TO_DEVICE
);
773 /*******************\
774 * Descriptors setup *
775 \*******************/
778 ath5k_desc_alloc(struct ath5k_softc
*sc
)
780 struct ath5k_desc
*ds
;
781 struct ath5k_buf
*bf
;
786 /* allocate descriptors */
787 sc
->desc_len
= sizeof(struct ath5k_desc
) *
788 (ATH_TXBUF
+ ATH_RXBUF
+ ATH_BCBUF
+ 1);
790 sc
->desc
= dma_alloc_coherent(sc
->dev
, sc
->desc_len
,
791 &sc
->desc_daddr
, GFP_KERNEL
);
792 if (sc
->desc
== NULL
) {
793 ATH5K_ERR(sc
, "can't allocate descriptors\n");
799 ATH5K_DBG(sc
, ATH5K_DEBUG_ANY
, "DMA map: %p (%zu) -> %llx\n",
800 ds
, sc
->desc_len
, (unsigned long long)sc
->desc_daddr
);
802 bf
= kcalloc(1 + ATH_TXBUF
+ ATH_RXBUF
+ ATH_BCBUF
,
803 sizeof(struct ath5k_buf
), GFP_KERNEL
);
805 ATH5K_ERR(sc
, "can't allocate bufptr\n");
811 INIT_LIST_HEAD(&sc
->rxbuf
);
812 for (i
= 0; i
< ATH_RXBUF
; i
++, bf
++, ds
++, da
+= sizeof(*ds
)) {
815 list_add_tail(&bf
->list
, &sc
->rxbuf
);
818 INIT_LIST_HEAD(&sc
->txbuf
);
819 sc
->txbuf_len
= ATH_TXBUF
;
820 for (i
= 0; i
< ATH_TXBUF
; i
++, bf
++, ds
++,
824 list_add_tail(&bf
->list
, &sc
->txbuf
);
828 INIT_LIST_HEAD(&sc
->bcbuf
);
829 for (i
= 0; i
< ATH_BCBUF
; i
++, bf
++, ds
++, da
+= sizeof(*ds
)) {
832 list_add_tail(&bf
->list
, &sc
->bcbuf
);
837 dma_free_coherent(sc
->dev
, sc
->desc_len
, sc
->desc
, sc
->desc_daddr
);
844 ath5k_txbuf_free_skb(struct ath5k_softc
*sc
, struct ath5k_buf
*bf
)
849 dma_unmap_single(sc
->dev
, bf
->skbaddr
, bf
->skb
->len
,
851 dev_kfree_skb_any(bf
->skb
);
854 bf
->desc
->ds_data
= 0;
858 ath5k_rxbuf_free_skb(struct ath5k_softc
*sc
, struct ath5k_buf
*bf
)
860 struct ath5k_hw
*ah
= sc
->ah
;
861 struct ath_common
*common
= ath5k_hw_common(ah
);
866 dma_unmap_single(sc
->dev
, bf
->skbaddr
, common
->rx_bufsize
,
868 dev_kfree_skb_any(bf
->skb
);
871 bf
->desc
->ds_data
= 0;
875 ath5k_desc_free(struct ath5k_softc
*sc
)
877 struct ath5k_buf
*bf
;
879 list_for_each_entry(bf
, &sc
->txbuf
, list
)
880 ath5k_txbuf_free_skb(sc
, bf
);
881 list_for_each_entry(bf
, &sc
->rxbuf
, list
)
882 ath5k_rxbuf_free_skb(sc
, bf
);
883 list_for_each_entry(bf
, &sc
->bcbuf
, list
)
884 ath5k_txbuf_free_skb(sc
, bf
);
886 /* Free memory associated with all descriptors */
887 dma_free_coherent(sc
->dev
, sc
->desc_len
, sc
->desc
, sc
->desc_daddr
);
900 static struct ath5k_txq
*
901 ath5k_txq_setup(struct ath5k_softc
*sc
,
902 int qtype
, int subtype
)
904 struct ath5k_hw
*ah
= sc
->ah
;
905 struct ath5k_txq
*txq
;
906 struct ath5k_txq_info qi
= {
907 .tqi_subtype
= subtype
,
908 /* XXX: default values not correct for B and XR channels,
910 .tqi_aifs
= AR5K_TUNE_AIFS
,
911 .tqi_cw_min
= AR5K_TUNE_CWMIN
,
912 .tqi_cw_max
= AR5K_TUNE_CWMAX
917 * Enable interrupts only for EOL and DESC conditions.
918 * We mark tx descriptors to receive a DESC interrupt
919 * when a tx queue gets deep; otherwise we wait for the
920 * EOL to reap descriptors. Note that this is done to
921 * reduce interrupt load and this only defers reaping
922 * descriptors, never transmitting frames. Aside from
923 * reducing interrupts this also permits more concurrency.
924 * The only potential downside is if the tx queue backs
925 * up in which case the top half of the kernel may backup
926 * due to a lack of tx descriptors.
928 qi
.tqi_flags
= AR5K_TXQ_FLAG_TXEOLINT_ENABLE
|
929 AR5K_TXQ_FLAG_TXDESCINT_ENABLE
;
930 qnum
= ath5k_hw_setup_tx_queue(ah
, qtype
, &qi
);
933 * NB: don't print a message, this happens
934 * normally on parts with too few tx queues
936 return ERR_PTR(qnum
);
938 if (qnum
>= ARRAY_SIZE(sc
->txqs
)) {
939 ATH5K_ERR(sc
, "hw qnum %u out of range, max %tu!\n",
940 qnum
, ARRAY_SIZE(sc
->txqs
));
941 ath5k_hw_release_tx_queue(ah
, qnum
);
942 return ERR_PTR(-EINVAL
);
944 txq
= &sc
->txqs
[qnum
];
948 INIT_LIST_HEAD(&txq
->q
);
949 spin_lock_init(&txq
->lock
);
952 txq
->txq_poll_mark
= false;
955 return &sc
->txqs
[qnum
];
959 ath5k_beaconq_setup(struct ath5k_hw
*ah
)
961 struct ath5k_txq_info qi
= {
962 /* XXX: default values not correct for B and XR channels,
964 .tqi_aifs
= AR5K_TUNE_AIFS
,
965 .tqi_cw_min
= AR5K_TUNE_CWMIN
,
966 .tqi_cw_max
= AR5K_TUNE_CWMAX
,
967 /* NB: for dynamic turbo, don't enable any other interrupts */
968 .tqi_flags
= AR5K_TXQ_FLAG_TXDESCINT_ENABLE
971 return ath5k_hw_setup_tx_queue(ah
, AR5K_TX_QUEUE_BEACON
, &qi
);
975 ath5k_beaconq_config(struct ath5k_softc
*sc
)
977 struct ath5k_hw
*ah
= sc
->ah
;
978 struct ath5k_txq_info qi
;
981 ret
= ath5k_hw_get_tx_queueprops(ah
, sc
->bhalq
, &qi
);
985 if (sc
->opmode
== NL80211_IFTYPE_AP
||
986 sc
->opmode
== NL80211_IFTYPE_MESH_POINT
) {
988 * Always burst out beacon and CAB traffic
989 * (aifs = cwmin = cwmax = 0)
994 } else if (sc
->opmode
== NL80211_IFTYPE_ADHOC
) {
996 * Adhoc mode; backoff between 0 and (2 * cw_min).
1000 qi
.tqi_cw_max
= 2 * AR5K_TUNE_CWMIN
;
1003 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
1004 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1005 qi
.tqi_aifs
, qi
.tqi_cw_min
, qi
.tqi_cw_max
);
1007 ret
= ath5k_hw_set_tx_queueprops(ah
, sc
->bhalq
, &qi
);
1009 ATH5K_ERR(sc
, "%s: unable to update parameters for beacon "
1010 "hardware queue!\n", __func__
);
1013 ret
= ath5k_hw_reset_tx_queue(ah
, sc
->bhalq
); /* push to h/w */
1017 /* reconfigure cabq with ready time to 80% of beacon_interval */
1018 ret
= ath5k_hw_get_tx_queueprops(ah
, AR5K_TX_QUEUE_ID_CAB
, &qi
);
1022 qi
.tqi_ready_time
= (sc
->bintval
* 80) / 100;
1023 ret
= ath5k_hw_set_tx_queueprops(ah
, AR5K_TX_QUEUE_ID_CAB
, &qi
);
1027 ret
= ath5k_hw_reset_tx_queue(ah
, AR5K_TX_QUEUE_ID_CAB
);
1033 * ath5k_drain_tx_buffs - Empty tx buffers
1035 * @sc The &struct ath5k_softc
1037 * Empty tx buffers from all queues in preparation
1038 * of a reset or during shutdown.
1040 * NB: this assumes output has been stopped and
1041 * we do not need to block ath5k_tx_tasklet
1044 ath5k_drain_tx_buffs(struct ath5k_softc
*sc
)
1046 struct ath5k_txq
*txq
;
1047 struct ath5k_buf
*bf
, *bf0
;
1050 for (i
= 0; i
< ARRAY_SIZE(sc
->txqs
); i
++) {
1051 if (sc
->txqs
[i
].setup
) {
1053 spin_lock_bh(&txq
->lock
);
1054 list_for_each_entry_safe(bf
, bf0
, &txq
->q
, list
) {
1055 ath5k_debug_printtxbuf(sc
, bf
);
1057 ath5k_txbuf_free_skb(sc
, bf
);
1059 spin_lock_bh(&sc
->txbuflock
);
1060 list_move_tail(&bf
->list
, &sc
->txbuf
);
1063 spin_unlock_bh(&sc
->txbuflock
);
1066 txq
->txq_poll_mark
= false;
1067 spin_unlock_bh(&txq
->lock
);
1073 ath5k_txq_release(struct ath5k_softc
*sc
)
1075 struct ath5k_txq
*txq
= sc
->txqs
;
1078 for (i
= 0; i
< ARRAY_SIZE(sc
->txqs
); i
++, txq
++)
1080 ath5k_hw_release_tx_queue(sc
->ah
, txq
->qnum
);
1091 * Enable the receive h/w following a reset.
1094 ath5k_rx_start(struct ath5k_softc
*sc
)
1096 struct ath5k_hw
*ah
= sc
->ah
;
1097 struct ath_common
*common
= ath5k_hw_common(ah
);
1098 struct ath5k_buf
*bf
;
1101 common
->rx_bufsize
= roundup(IEEE80211_MAX_FRAME_LEN
, common
->cachelsz
);
1103 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "cachelsz %u rx_bufsize %u\n",
1104 common
->cachelsz
, common
->rx_bufsize
);
1106 spin_lock_bh(&sc
->rxbuflock
);
1108 list_for_each_entry(bf
, &sc
->rxbuf
, list
) {
1109 ret
= ath5k_rxbuf_setup(sc
, bf
);
1111 spin_unlock_bh(&sc
->rxbuflock
);
1115 bf
= list_first_entry(&sc
->rxbuf
, struct ath5k_buf
, list
);
1116 ath5k_hw_set_rxdp(ah
, bf
->daddr
);
1117 spin_unlock_bh(&sc
->rxbuflock
);
1119 ath5k_hw_start_rx_dma(ah
); /* enable recv descriptors */
1120 ath5k_mode_setup(sc
, NULL
); /* set filters, etc. */
1121 ath5k_hw_start_rx_pcu(ah
); /* re-enable PCU/DMA engine */
1129 * Disable the receive logic on PCU (DRU)
1130 * In preparation for a shutdown.
1132 * Note: Doesn't stop rx DMA, ath5k_hw_dma_stop
1136 ath5k_rx_stop(struct ath5k_softc
*sc
)
1138 struct ath5k_hw
*ah
= sc
->ah
;
1140 ath5k_hw_set_rx_filter(ah
, 0); /* clear recv filter */
1141 ath5k_hw_stop_rx_pcu(ah
); /* disable PCU */
1143 ath5k_debug_printrxbuffs(sc
, ah
);
1147 ath5k_rx_decrypted(struct ath5k_softc
*sc
, struct sk_buff
*skb
,
1148 struct ath5k_rx_status
*rs
)
1150 struct ath5k_hw
*ah
= sc
->ah
;
1151 struct ath_common
*common
= ath5k_hw_common(ah
);
1152 struct ieee80211_hdr
*hdr
= (void *)skb
->data
;
1153 unsigned int keyix
, hlen
;
1155 if (!(rs
->rs_status
& AR5K_RXERR_DECRYPT
) &&
1156 rs
->rs_keyix
!= AR5K_RXKEYIX_INVALID
)
1157 return RX_FLAG_DECRYPTED
;
1159 /* Apparently when a default key is used to decrypt the packet
1160 the hw does not set the index used to decrypt. In such cases
1161 get the index from the packet. */
1162 hlen
= ieee80211_hdrlen(hdr
->frame_control
);
1163 if (ieee80211_has_protected(hdr
->frame_control
) &&
1164 !(rs
->rs_status
& AR5K_RXERR_DECRYPT
) &&
1165 skb
->len
>= hlen
+ 4) {
1166 keyix
= skb
->data
[hlen
+ 3] >> 6;
1168 if (test_bit(keyix
, common
->keymap
))
1169 return RX_FLAG_DECRYPTED
;
1177 ath5k_check_ibss_tsf(struct ath5k_softc
*sc
, struct sk_buff
*skb
,
1178 struct ieee80211_rx_status
*rxs
)
1180 struct ath_common
*common
= ath5k_hw_common(sc
->ah
);
1183 struct ieee80211_mgmt
*mgmt
= (struct ieee80211_mgmt
*)skb
->data
;
1185 if (ieee80211_is_beacon(mgmt
->frame_control
) &&
1186 le16_to_cpu(mgmt
->u
.beacon
.capab_info
) & WLAN_CAPABILITY_IBSS
&&
1187 memcmp(mgmt
->bssid
, common
->curbssid
, ETH_ALEN
) == 0) {
1189 * Received an IBSS beacon with the same BSSID. Hardware *must*
1190 * have updated the local TSF. We have to work around various
1191 * hardware bugs, though...
1193 tsf
= ath5k_hw_get_tsf64(sc
->ah
);
1194 bc_tstamp
= le64_to_cpu(mgmt
->u
.beacon
.timestamp
);
1195 hw_tu
= TSF_TO_TU(tsf
);
1197 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
1198 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1199 (unsigned long long)bc_tstamp
,
1200 (unsigned long long)rxs
->mactime
,
1201 (unsigned long long)(rxs
->mactime
- bc_tstamp
),
1202 (unsigned long long)tsf
);
1205 * Sometimes the HW will give us a wrong tstamp in the rx
1206 * status, causing the timestamp extension to go wrong.
1207 * (This seems to happen especially with beacon frames bigger
1208 * than 78 byte (incl. FCS))
1209 * But we know that the receive timestamp must be later than the
1210 * timestamp of the beacon since HW must have synced to that.
1212 * NOTE: here we assume mactime to be after the frame was
1213 * received, not like mac80211 which defines it at the start.
1215 if (bc_tstamp
> rxs
->mactime
) {
1216 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
1217 "fixing mactime from %llx to %llx\n",
1218 (unsigned long long)rxs
->mactime
,
1219 (unsigned long long)tsf
);
1224 * Local TSF might have moved higher than our beacon timers,
1225 * in that case we have to update them to continue sending
1226 * beacons. This also takes care of synchronizing beacon sending
1227 * times with other stations.
1229 if (hw_tu
>= sc
->nexttbtt
)
1230 ath5k_beacon_update_timers(sc
, bc_tstamp
);
1232 /* Check if the beacon timers are still correct, because a TSF
1233 * update might have created a window between them - for a
1234 * longer description see the comment of this function: */
1235 if (!ath5k_hw_check_beacon_timers(sc
->ah
, sc
->bintval
)) {
1236 ath5k_beacon_update_timers(sc
, bc_tstamp
);
1237 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
1238 "fixed beacon timers after beacon receive\n");
1244 ath5k_update_beacon_rssi(struct ath5k_softc
*sc
, struct sk_buff
*skb
, int rssi
)
1246 struct ieee80211_mgmt
*mgmt
= (struct ieee80211_mgmt
*)skb
->data
;
1247 struct ath5k_hw
*ah
= sc
->ah
;
1248 struct ath_common
*common
= ath5k_hw_common(ah
);
1250 /* only beacons from our BSSID */
1251 if (!ieee80211_is_beacon(mgmt
->frame_control
) ||
1252 memcmp(mgmt
->bssid
, common
->curbssid
, ETH_ALEN
) != 0)
1255 ewma_add(&ah
->ah_beacon_rssi_avg
, rssi
);
1257 /* in IBSS mode we should keep RSSI statistics per neighbour */
1258 /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */
1262 * Compute padding position. skb must contain an IEEE 802.11 frame
1264 static int ath5k_common_padpos(struct sk_buff
*skb
)
1266 struct ieee80211_hdr
* hdr
= (struct ieee80211_hdr
*)skb
->data
;
1267 __le16 frame_control
= hdr
->frame_control
;
1270 if (ieee80211_has_a4(frame_control
)) {
1273 if (ieee80211_is_data_qos(frame_control
)) {
1274 padpos
+= IEEE80211_QOS_CTL_LEN
;
1281 * This function expects an 802.11 frame and returns the number of
1282 * bytes added, or -1 if we don't have enough header room.
1284 static int ath5k_add_padding(struct sk_buff
*skb
)
1286 int padpos
= ath5k_common_padpos(skb
);
1287 int padsize
= padpos
& 3;
1289 if (padsize
&& skb
->len
>padpos
) {
1291 if (skb_headroom(skb
) < padsize
)
1294 skb_push(skb
, padsize
);
1295 memmove(skb
->data
, skb
->data
+padsize
, padpos
);
1303 * The MAC header is padded to have 32-bit boundary if the
1304 * packet payload is non-zero. The general calculation for
1305 * padsize would take into account odd header lengths:
1306 * padsize = 4 - (hdrlen & 3); however, since only
1307 * even-length headers are used, padding can only be 0 or 2
1308 * bytes and we can optimize this a bit. We must not try to
1309 * remove padding from short control frames that do not have a
1312 * This function expects an 802.11 frame and returns the number of
1315 static int ath5k_remove_padding(struct sk_buff
*skb
)
1317 int padpos
= ath5k_common_padpos(skb
);
1318 int padsize
= padpos
& 3;
1320 if (padsize
&& skb
->len
>=padpos
+padsize
) {
1321 memmove(skb
->data
+ padsize
, skb
->data
, padpos
);
1322 skb_pull(skb
, padsize
);
1330 ath5k_receive_frame(struct ath5k_softc
*sc
, struct sk_buff
*skb
,
1331 struct ath5k_rx_status
*rs
)
1333 struct ieee80211_rx_status
*rxs
;
1335 ath5k_remove_padding(skb
);
1337 rxs
= IEEE80211_SKB_RXCB(skb
);
1340 if (unlikely(rs
->rs_status
& AR5K_RXERR_MIC
))
1341 rxs
->flag
|= RX_FLAG_MMIC_ERROR
;
1344 * always extend the mac timestamp, since this information is
1345 * also needed for proper IBSS merging.
1347 * XXX: it might be too late to do it here, since rs_tstamp is
1348 * 15bit only. that means TSF extension has to be done within
1349 * 32768usec (about 32ms). it might be necessary to move this to
1350 * the interrupt handler, like it is done in madwifi.
1352 * Unfortunately we don't know when the hardware takes the rx
1353 * timestamp (beginning of phy frame, data frame, end of rx?).
1354 * The only thing we know is that it is hardware specific...
1355 * On AR5213 it seems the rx timestamp is at the end of the
1356 * frame, but i'm not sure.
1358 * NOTE: mac80211 defines mactime at the beginning of the first
1359 * data symbol. Since we don't have any time references it's
1360 * impossible to comply to that. This affects IBSS merge only
1361 * right now, so it's not too bad...
1363 rxs
->mactime
= ath5k_extend_tsf(sc
->ah
, rs
->rs_tstamp
);
1364 rxs
->flag
|= RX_FLAG_MACTIME_MPDU
;
1366 rxs
->freq
= sc
->curchan
->center_freq
;
1367 rxs
->band
= sc
->curchan
->band
;
1369 rxs
->signal
= sc
->ah
->ah_noise_floor
+ rs
->rs_rssi
;
1371 rxs
->antenna
= rs
->rs_antenna
;
1373 if (rs
->rs_antenna
> 0 && rs
->rs_antenna
< 5)
1374 sc
->stats
.antenna_rx
[rs
->rs_antenna
]++;
1376 sc
->stats
.antenna_rx
[0]++; /* invalid */
1378 rxs
->rate_idx
= ath5k_hw_to_driver_rix(sc
, rs
->rs_rate
);
1379 rxs
->flag
|= ath5k_rx_decrypted(sc
, skb
, rs
);
1381 if (rxs
->rate_idx
>= 0 && rs
->rs_rate
==
1382 sc
->sbands
[sc
->curchan
->band
].bitrates
[rxs
->rate_idx
].hw_value_short
)
1383 rxs
->flag
|= RX_FLAG_SHORTPRE
;
1385 trace_ath5k_rx(sc
, skb
);
1387 ath5k_update_beacon_rssi(sc
, skb
, rs
->rs_rssi
);
1389 /* check beacons in IBSS mode */
1390 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
)
1391 ath5k_check_ibss_tsf(sc
, skb
, rxs
);
1393 ieee80211_rx(sc
->hw
, skb
);
1396 /** ath5k_frame_receive_ok() - Do we want to receive this frame or not?
1398 * Check if we want to further process this frame or not. Also update
1399 * statistics. Return true if we want this frame, false if not.
1402 ath5k_receive_frame_ok(struct ath5k_softc
*sc
, struct ath5k_rx_status
*rs
)
1404 sc
->stats
.rx_all_count
++;
1405 sc
->stats
.rx_bytes_count
+= rs
->rs_datalen
;
1407 if (unlikely(rs
->rs_status
)) {
1408 if (rs
->rs_status
& AR5K_RXERR_CRC
)
1409 sc
->stats
.rxerr_crc
++;
1410 if (rs
->rs_status
& AR5K_RXERR_FIFO
)
1411 sc
->stats
.rxerr_fifo
++;
1412 if (rs
->rs_status
& AR5K_RXERR_PHY
) {
1413 sc
->stats
.rxerr_phy
++;
1414 if (rs
->rs_phyerr
> 0 && rs
->rs_phyerr
< 32)
1415 sc
->stats
.rxerr_phy_code
[rs
->rs_phyerr
]++;
1418 if (rs
->rs_status
& AR5K_RXERR_DECRYPT
) {
1420 * Decrypt error. If the error occurred
1421 * because there was no hardware key, then
1422 * let the frame through so the upper layers
1423 * can process it. This is necessary for 5210
1424 * parts which have no way to setup a ``clear''
1427 * XXX do key cache faulting
1429 sc
->stats
.rxerr_decrypt
++;
1430 if (rs
->rs_keyix
== AR5K_RXKEYIX_INVALID
&&
1431 !(rs
->rs_status
& AR5K_RXERR_CRC
))
1434 if (rs
->rs_status
& AR5K_RXERR_MIC
) {
1435 sc
->stats
.rxerr_mic
++;
1439 /* reject any frames with non-crypto errors */
1440 if (rs
->rs_status
& ~(AR5K_RXERR_DECRYPT
))
1444 if (unlikely(rs
->rs_more
)) {
1445 sc
->stats
.rxerr_jumbo
++;
1452 ath5k_tasklet_rx(unsigned long data
)
1454 struct ath5k_rx_status rs
= {};
1455 struct sk_buff
*skb
, *next_skb
;
1456 dma_addr_t next_skb_addr
;
1457 struct ath5k_softc
*sc
= (void *)data
;
1458 struct ath5k_hw
*ah
= sc
->ah
;
1459 struct ath_common
*common
= ath5k_hw_common(ah
);
1460 struct ath5k_buf
*bf
;
1461 struct ath5k_desc
*ds
;
1464 spin_lock(&sc
->rxbuflock
);
1465 if (list_empty(&sc
->rxbuf
)) {
1466 ATH5K_WARN(sc
, "empty rx buf pool\n");
1470 bf
= list_first_entry(&sc
->rxbuf
, struct ath5k_buf
, list
);
1471 BUG_ON(bf
->skb
== NULL
);
1475 /* bail if HW is still using self-linked descriptor */
1476 if (ath5k_hw_get_rxdp(sc
->ah
) == bf
->daddr
)
1479 ret
= sc
->ah
->ah_proc_rx_desc(sc
->ah
, ds
, &rs
);
1480 if (unlikely(ret
== -EINPROGRESS
))
1482 else if (unlikely(ret
)) {
1483 ATH5K_ERR(sc
, "error in processing rx descriptor\n");
1484 sc
->stats
.rxerr_proc
++;
1488 if (ath5k_receive_frame_ok(sc
, &rs
)) {
1489 next_skb
= ath5k_rx_skb_alloc(sc
, &next_skb_addr
);
1492 * If we can't replace bf->skb with a new skb under
1493 * memory pressure, just skip this packet
1498 dma_unmap_single(sc
->dev
, bf
->skbaddr
,
1502 skb_put(skb
, rs
.rs_datalen
);
1504 ath5k_receive_frame(sc
, skb
, &rs
);
1507 bf
->skbaddr
= next_skb_addr
;
1510 list_move_tail(&bf
->list
, &sc
->rxbuf
);
1511 } while (ath5k_rxbuf_setup(sc
, bf
) == 0);
1513 spin_unlock(&sc
->rxbuflock
);
1522 ath5k_tx_queue(struct ieee80211_hw
*hw
, struct sk_buff
*skb
,
1523 struct ath5k_txq
*txq
)
1525 struct ath5k_softc
*sc
= hw
->priv
;
1526 struct ath5k_buf
*bf
;
1527 unsigned long flags
;
1530 trace_ath5k_tx(sc
, skb
, txq
);
1533 * The hardware expects the header padded to 4 byte boundaries.
1534 * If this is not the case, we add the padding after the header.
1536 padsize
= ath5k_add_padding(skb
);
1538 ATH5K_ERR(sc
, "tx hdrlen not %%4: not enough"
1539 " headroom to pad");
1543 if (txq
->txq_len
>= ATH5K_TXQ_LEN_MAX
)
1544 ieee80211_stop_queue(hw
, txq
->qnum
);
1546 spin_lock_irqsave(&sc
->txbuflock
, flags
);
1547 if (list_empty(&sc
->txbuf
)) {
1548 ATH5K_ERR(sc
, "no further txbuf available, dropping packet\n");
1549 spin_unlock_irqrestore(&sc
->txbuflock
, flags
);
1550 ieee80211_stop_queues(hw
);
1553 bf
= list_first_entry(&sc
->txbuf
, struct ath5k_buf
, list
);
1554 list_del(&bf
->list
);
1556 if (list_empty(&sc
->txbuf
))
1557 ieee80211_stop_queues(hw
);
1558 spin_unlock_irqrestore(&sc
->txbuflock
, flags
);
1562 if (ath5k_txbuf_setup(sc
, bf
, txq
, padsize
)) {
1564 spin_lock_irqsave(&sc
->txbuflock
, flags
);
1565 list_add_tail(&bf
->list
, &sc
->txbuf
);
1567 spin_unlock_irqrestore(&sc
->txbuflock
, flags
);
1573 dev_kfree_skb_any(skb
);
1577 ath5k_tx_frame_completed(struct ath5k_softc
*sc
, struct sk_buff
*skb
,
1578 struct ath5k_txq
*txq
, struct ath5k_tx_status
*ts
)
1580 struct ieee80211_tx_info
*info
;
1583 sc
->stats
.tx_all_count
++;
1584 sc
->stats
.tx_bytes_count
+= skb
->len
;
1585 info
= IEEE80211_SKB_CB(skb
);
1587 ieee80211_tx_info_clear_status(info
);
1588 for (i
= 0; i
< 4; i
++) {
1589 struct ieee80211_tx_rate
*r
=
1590 &info
->status
.rates
[i
];
1592 if (ts
->ts_rate
[i
]) {
1593 r
->idx
= ath5k_hw_to_driver_rix(sc
, ts
->ts_rate
[i
]);
1594 r
->count
= ts
->ts_retry
[i
];
1601 /* count the successful attempt as well */
1602 info
->status
.rates
[ts
->ts_final_idx
].count
++;
1604 if (unlikely(ts
->ts_status
)) {
1605 sc
->stats
.ack_fail
++;
1606 if (ts
->ts_status
& AR5K_TXERR_FILT
) {
1607 info
->flags
|= IEEE80211_TX_STAT_TX_FILTERED
;
1608 sc
->stats
.txerr_filt
++;
1610 if (ts
->ts_status
& AR5K_TXERR_XRETRY
)
1611 sc
->stats
.txerr_retry
++;
1612 if (ts
->ts_status
& AR5K_TXERR_FIFO
)
1613 sc
->stats
.txerr_fifo
++;
1615 info
->flags
|= IEEE80211_TX_STAT_ACK
;
1616 info
->status
.ack_signal
= ts
->ts_rssi
;
1620 * Remove MAC header padding before giving the frame
1623 ath5k_remove_padding(skb
);
1625 if (ts
->ts_antenna
> 0 && ts
->ts_antenna
< 5)
1626 sc
->stats
.antenna_tx
[ts
->ts_antenna
]++;
1628 sc
->stats
.antenna_tx
[0]++; /* invalid */
1630 trace_ath5k_tx_complete(sc
, skb
, txq
, ts
);
1631 ieee80211_tx_status(sc
->hw
, skb
);
1635 ath5k_tx_processq(struct ath5k_softc
*sc
, struct ath5k_txq
*txq
)
1637 struct ath5k_tx_status ts
= {};
1638 struct ath5k_buf
*bf
, *bf0
;
1639 struct ath5k_desc
*ds
;
1640 struct sk_buff
*skb
;
1643 spin_lock(&txq
->lock
);
1644 list_for_each_entry_safe(bf
, bf0
, &txq
->q
, list
) {
1646 txq
->txq_poll_mark
= false;
1648 /* skb might already have been processed last time. */
1649 if (bf
->skb
!= NULL
) {
1652 ret
= sc
->ah
->ah_proc_tx_desc(sc
->ah
, ds
, &ts
);
1653 if (unlikely(ret
== -EINPROGRESS
))
1655 else if (unlikely(ret
)) {
1657 "error %d while processing "
1658 "queue %u\n", ret
, txq
->qnum
);
1665 dma_unmap_single(sc
->dev
, bf
->skbaddr
, skb
->len
,
1667 ath5k_tx_frame_completed(sc
, skb
, txq
, &ts
);
1671 * It's possible that the hardware can say the buffer is
1672 * completed when it hasn't yet loaded the ds_link from
1673 * host memory and moved on.
1674 * Always keep the last descriptor to avoid HW races...
1676 if (ath5k_hw_get_txdp(sc
->ah
, txq
->qnum
) != bf
->daddr
) {
1677 spin_lock(&sc
->txbuflock
);
1678 list_move_tail(&bf
->list
, &sc
->txbuf
);
1681 spin_unlock(&sc
->txbuflock
);
1684 spin_unlock(&txq
->lock
);
1685 if (txq
->txq_len
< ATH5K_TXQ_LEN_LOW
&& txq
->qnum
< 4)
1686 ieee80211_wake_queue(sc
->hw
, txq
->qnum
);
1690 ath5k_tasklet_tx(unsigned long data
)
1693 struct ath5k_softc
*sc
= (void *)data
;
1695 for (i
=0; i
< AR5K_NUM_TX_QUEUES
; i
++)
1696 if (sc
->txqs
[i
].setup
&& (sc
->ah
->ah_txq_isr
& BIT(i
)))
1697 ath5k_tx_processq(sc
, &sc
->txqs
[i
]);
1706 * Setup the beacon frame for transmit.
1709 ath5k_beacon_setup(struct ath5k_softc
*sc
, struct ath5k_buf
*bf
)
1711 struct sk_buff
*skb
= bf
->skb
;
1712 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
1713 struct ath5k_hw
*ah
= sc
->ah
;
1714 struct ath5k_desc
*ds
;
1718 const int padsize
= 0;
1720 bf
->skbaddr
= dma_map_single(sc
->dev
, skb
->data
, skb
->len
,
1722 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
, "skb %p [data %p len %u] "
1723 "skbaddr %llx\n", skb
, skb
->data
, skb
->len
,
1724 (unsigned long long)bf
->skbaddr
);
1726 if (dma_mapping_error(sc
->dev
, bf
->skbaddr
)) {
1727 ATH5K_ERR(sc
, "beacon DMA mapping failed\n");
1732 antenna
= ah
->ah_tx_ant
;
1734 flags
= AR5K_TXDESC_NOACK
;
1735 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
&& ath5k_hw_hasveol(ah
)) {
1736 ds
->ds_link
= bf
->daddr
; /* self-linked */
1737 flags
|= AR5K_TXDESC_VEOL
;
1742 * If we use multiple antennas on AP and use
1743 * the Sectored AP scenario, switch antenna every
1744 * 4 beacons to make sure everybody hears our AP.
1745 * When a client tries to associate, hw will keep
1746 * track of the tx antenna to be used for this client
1747 * automaticaly, based on ACKed packets.
1749 * Note: AP still listens and transmits RTS on the
1750 * default antenna which is supposed to be an omni.
1752 * Note2: On sectored scenarios it's possible to have
1753 * multiple antennas (1 omni -- the default -- and 14
1754 * sectors), so if we choose to actually support this
1755 * mode, we need to allow the user to set how many antennas
1756 * we have and tweak the code below to send beacons
1759 if (ah
->ah_ant_mode
== AR5K_ANTMODE_SECTOR_AP
)
1760 antenna
= sc
->bsent
& 4 ? 2 : 1;
1763 /* FIXME: If we are in g mode and rate is a CCK rate
1764 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1765 * from tx power (value is in dB units already) */
1766 ds
->ds_data
= bf
->skbaddr
;
1767 ret
= ah
->ah_setup_tx_desc(ah
, ds
, skb
->len
,
1768 ieee80211_get_hdrlen_from_skb(skb
), padsize
,
1769 AR5K_PKT_TYPE_BEACON
, (sc
->power_level
* 2),
1770 ieee80211_get_tx_rate(sc
->hw
, info
)->hw_value
,
1771 1, AR5K_TXKEYIX_INVALID
,
1772 antenna
, flags
, 0, 0);
1778 dma_unmap_single(sc
->dev
, bf
->skbaddr
, skb
->len
, DMA_TO_DEVICE
);
1783 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
1784 * this is called only once at config_bss time, for AP we do it every
1785 * SWBA interrupt so that the TIM will reflect buffered frames.
1787 * Called with the beacon lock.
1790 ath5k_beacon_update(struct ieee80211_hw
*hw
, struct ieee80211_vif
*vif
)
1793 struct ath5k_softc
*sc
= hw
->priv
;
1794 struct ath5k_vif
*avf
= (void *)vif
->drv_priv
;
1795 struct sk_buff
*skb
;
1797 if (WARN_ON(!vif
)) {
1802 skb
= ieee80211_beacon_get(hw
, vif
);
1809 ath5k_txbuf_free_skb(sc
, avf
->bbuf
);
1810 avf
->bbuf
->skb
= skb
;
1811 ret
= ath5k_beacon_setup(sc
, avf
->bbuf
);
1813 avf
->bbuf
->skb
= NULL
;
1819 * Transmit a beacon frame at SWBA. Dynamic updates to the
1820 * frame contents are done as needed and the slot time is
1821 * also adjusted based on current state.
1823 * This is called from software irq context (beacontq tasklets)
1824 * or user context from ath5k_beacon_config.
1827 ath5k_beacon_send(struct ath5k_softc
*sc
)
1829 struct ath5k_hw
*ah
= sc
->ah
;
1830 struct ieee80211_vif
*vif
;
1831 struct ath5k_vif
*avf
;
1832 struct ath5k_buf
*bf
;
1833 struct sk_buff
*skb
;
1835 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
, "in beacon_send\n");
1838 * Check if the previous beacon has gone out. If
1839 * not, don't don't try to post another: skip this
1840 * period and wait for the next. Missed beacons
1841 * indicate a problem and should not occur. If we
1842 * miss too many consecutive beacons reset the device.
1844 if (unlikely(ath5k_hw_num_tx_pending(ah
, sc
->bhalq
) != 0)) {
1846 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
1847 "missed %u consecutive beacons\n", sc
->bmisscount
);
1848 if (sc
->bmisscount
> 10) { /* NB: 10 is a guess */
1849 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
1850 "stuck beacon time (%u missed)\n",
1852 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
,
1853 "stuck beacon, resetting\n");
1854 ieee80211_queue_work(sc
->hw
, &sc
->reset_work
);
1858 if (unlikely(sc
->bmisscount
!= 0)) {
1859 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
1860 "resume beacon xmit after %u misses\n",
1865 if ((sc
->opmode
== NL80211_IFTYPE_AP
&& sc
->num_ap_vifs
> 1) ||
1866 sc
->opmode
== NL80211_IFTYPE_MESH_POINT
) {
1867 u64 tsf
= ath5k_hw_get_tsf64(ah
);
1868 u32 tsftu
= TSF_TO_TU(tsf
);
1869 int slot
= ((tsftu
% sc
->bintval
) * ATH_BCBUF
) / sc
->bintval
;
1870 vif
= sc
->bslot
[(slot
+ 1) % ATH_BCBUF
];
1871 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
1872 "tsf %llx tsftu %x intval %u slot %u vif %p\n",
1873 (unsigned long long)tsf
, tsftu
, sc
->bintval
, slot
, vif
);
1874 } else /* only one interface */
1880 avf
= (void *)vif
->drv_priv
;
1882 if (unlikely(bf
->skb
== NULL
|| sc
->opmode
== NL80211_IFTYPE_STATION
||
1883 sc
->opmode
== NL80211_IFTYPE_MONITOR
)) {
1884 ATH5K_WARN(sc
, "bf=%p bf_skb=%p\n", bf
, bf
? bf
->skb
: NULL
);
1889 * Stop any current dma and put the new frame on the queue.
1890 * This should never fail since we check above that no frames
1891 * are still pending on the queue.
1893 if (unlikely(ath5k_hw_stop_beacon_queue(ah
, sc
->bhalq
))) {
1894 ATH5K_WARN(sc
, "beacon queue %u didn't start/stop ?\n", sc
->bhalq
);
1895 /* NB: hw still stops DMA, so proceed */
1898 /* refresh the beacon for AP or MESH mode */
1899 if (sc
->opmode
== NL80211_IFTYPE_AP
||
1900 sc
->opmode
== NL80211_IFTYPE_MESH_POINT
)
1901 ath5k_beacon_update(sc
->hw
, vif
);
1903 trace_ath5k_tx(sc
, bf
->skb
, &sc
->txqs
[sc
->bhalq
]);
1905 ath5k_hw_set_txdp(ah
, sc
->bhalq
, bf
->daddr
);
1906 ath5k_hw_start_tx_dma(ah
, sc
->bhalq
);
1907 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
, "TXDP[%u] = %llx (%p)\n",
1908 sc
->bhalq
, (unsigned long long)bf
->daddr
, bf
->desc
);
1910 skb
= ieee80211_get_buffered_bc(sc
->hw
, vif
);
1912 ath5k_tx_queue(sc
->hw
, skb
, sc
->cabq
);
1913 skb
= ieee80211_get_buffered_bc(sc
->hw
, vif
);
1920 * ath5k_beacon_update_timers - update beacon timers
1922 * @sc: struct ath5k_softc pointer we are operating on
1923 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
1924 * beacon timer update based on the current HW TSF.
1926 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
1927 * of a received beacon or the current local hardware TSF and write it to the
1928 * beacon timer registers.
1930 * This is called in a variety of situations, e.g. when a beacon is received,
1931 * when a TSF update has been detected, but also when an new IBSS is created or
1932 * when we otherwise know we have to update the timers, but we keep it in this
1933 * function to have it all together in one place.
1936 ath5k_beacon_update_timers(struct ath5k_softc
*sc
, u64 bc_tsf
)
1938 struct ath5k_hw
*ah
= sc
->ah
;
1939 u32 nexttbtt
, intval
, hw_tu
, bc_tu
;
1942 intval
= sc
->bintval
& AR5K_BEACON_PERIOD
;
1943 if (sc
->opmode
== NL80211_IFTYPE_AP
&& sc
->num_ap_vifs
> 1) {
1944 intval
/= ATH_BCBUF
; /* staggered multi-bss beacons */
1946 ATH5K_WARN(sc
, "intval %u is too low, min 15\n",
1949 if (WARN_ON(!intval
))
1952 /* beacon TSF converted to TU */
1953 bc_tu
= TSF_TO_TU(bc_tsf
);
1955 /* current TSF converted to TU */
1956 hw_tsf
= ath5k_hw_get_tsf64(ah
);
1957 hw_tu
= TSF_TO_TU(hw_tsf
);
1959 #define FUDGE AR5K_TUNE_SW_BEACON_RESP + 3
1960 /* We use FUDGE to make sure the next TBTT is ahead of the current TU.
1961 * Since we later substract AR5K_TUNE_SW_BEACON_RESP (10) in the timer
1962 * configuration we need to make sure it is bigger than that. */
1966 * no beacons received, called internally.
1967 * just need to refresh timers based on HW TSF.
1969 nexttbtt
= roundup(hw_tu
+ FUDGE
, intval
);
1970 } else if (bc_tsf
== 0) {
1972 * no beacon received, probably called by ath5k_reset_tsf().
1973 * reset TSF to start with 0.
1976 intval
|= AR5K_BEACON_RESET_TSF
;
1977 } else if (bc_tsf
> hw_tsf
) {
1979 * beacon received, SW merge happend but HW TSF not yet updated.
1980 * not possible to reconfigure timers yet, but next time we
1981 * receive a beacon with the same BSSID, the hardware will
1982 * automatically update the TSF and then we need to reconfigure
1985 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
1986 "need to wait for HW TSF sync\n");
1990 * most important case for beacon synchronization between STA.
1992 * beacon received and HW TSF has been already updated by HW.
1993 * update next TBTT based on the TSF of the beacon, but make
1994 * sure it is ahead of our local TSF timer.
1996 nexttbtt
= bc_tu
+ roundup(hw_tu
+ FUDGE
- bc_tu
, intval
);
2000 sc
->nexttbtt
= nexttbtt
;
2002 intval
|= AR5K_BEACON_ENA
;
2003 ath5k_hw_init_beacon(ah
, nexttbtt
, intval
);
2006 * debugging output last in order to preserve the time critical aspect
2010 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2011 "reconfigured timers based on HW TSF\n");
2012 else if (bc_tsf
== 0)
2013 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2014 "reset HW TSF and timers\n");
2016 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2017 "updated timers based on beacon TSF\n");
2019 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2020 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2021 (unsigned long long) bc_tsf
,
2022 (unsigned long long) hw_tsf
, bc_tu
, hw_tu
, nexttbtt
);
2023 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
, "intval %u %s %s\n",
2024 intval
& AR5K_BEACON_PERIOD
,
2025 intval
& AR5K_BEACON_ENA
? "AR5K_BEACON_ENA" : "",
2026 intval
& AR5K_BEACON_RESET_TSF
? "AR5K_BEACON_RESET_TSF" : "");
2030 * ath5k_beacon_config - Configure the beacon queues and interrupts
2032 * @sc: struct ath5k_softc pointer we are operating on
2034 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2035 * interrupts to detect TSF updates only.
2038 ath5k_beacon_config(struct ath5k_softc
*sc
)
2040 struct ath5k_hw
*ah
= sc
->ah
;
2041 unsigned long flags
;
2043 spin_lock_irqsave(&sc
->block
, flags
);
2045 sc
->imask
&= ~(AR5K_INT_BMISS
| AR5K_INT_SWBA
);
2047 if (sc
->enable_beacon
) {
2049 * In IBSS mode we use a self-linked tx descriptor and let the
2050 * hardware send the beacons automatically. We have to load it
2052 * We use the SWBA interrupt only to keep track of the beacon
2053 * timers in order to detect automatic TSF updates.
2055 ath5k_beaconq_config(sc
);
2057 sc
->imask
|= AR5K_INT_SWBA
;
2059 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
) {
2060 if (ath5k_hw_hasveol(ah
))
2061 ath5k_beacon_send(sc
);
2063 ath5k_beacon_update_timers(sc
, -1);
2065 ath5k_hw_stop_beacon_queue(sc
->ah
, sc
->bhalq
);
2068 ath5k_hw_set_imr(ah
, sc
->imask
);
2070 spin_unlock_irqrestore(&sc
->block
, flags
);
2073 static void ath5k_tasklet_beacon(unsigned long data
)
2075 struct ath5k_softc
*sc
= (struct ath5k_softc
*) data
;
2078 * Software beacon alert--time to send a beacon.
2080 * In IBSS mode we use this interrupt just to
2081 * keep track of the next TBTT (target beacon
2082 * transmission time) in order to detect wether
2083 * automatic TSF updates happened.
2085 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
) {
2086 /* XXX: only if VEOL suppported */
2087 u64 tsf
= ath5k_hw_get_tsf64(sc
->ah
);
2088 sc
->nexttbtt
+= sc
->bintval
;
2089 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
2090 "SWBA nexttbtt: %x hw_tu: %x "
2094 (unsigned long long) tsf
);
2096 spin_lock(&sc
->block
);
2097 ath5k_beacon_send(sc
);
2098 spin_unlock(&sc
->block
);
2103 /********************\
2104 * Interrupt handling *
2105 \********************/
2108 ath5k_intr_calibration_poll(struct ath5k_hw
*ah
)
2110 if (time_is_before_eq_jiffies(ah
->ah_cal_next_ani
) &&
2111 !(ah
->ah_cal_mask
& AR5K_CALIBRATION_FULL
)) {
2112 /* run ANI only when full calibration is not active */
2113 ah
->ah_cal_next_ani
= jiffies
+
2114 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI
);
2115 tasklet_schedule(&ah
->ah_sc
->ani_tasklet
);
2117 } else if (time_is_before_eq_jiffies(ah
->ah_cal_next_full
)) {
2118 ah
->ah_cal_next_full
= jiffies
+
2119 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL
);
2120 tasklet_schedule(&ah
->ah_sc
->calib
);
2122 /* we could use SWI to generate enough interrupts to meet our
2123 * calibration interval requirements, if necessary:
2124 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */
2128 ath5k_intr(int irq
, void *dev_id
)
2130 struct ath5k_softc
*sc
= dev_id
;
2131 struct ath5k_hw
*ah
= sc
->ah
;
2132 enum ath5k_int status
;
2133 unsigned int counter
= 1000;
2135 if (unlikely(test_bit(ATH_STAT_INVALID
, sc
->status
) ||
2136 ((ath5k_get_bus_type(ah
) != ATH_AHB
) &&
2137 !ath5k_hw_is_intr_pending(ah
))))
2141 ath5k_hw_get_isr(ah
, &status
); /* NB: clears IRQ too */
2142 ATH5K_DBG(sc
, ATH5K_DEBUG_INTR
, "status 0x%x/0x%x\n",
2144 if (unlikely(status
& AR5K_INT_FATAL
)) {
2146 * Fatal errors are unrecoverable.
2147 * Typically these are caused by DMA errors.
2149 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
,
2150 "fatal int, resetting\n");
2151 ieee80211_queue_work(sc
->hw
, &sc
->reset_work
);
2152 } else if (unlikely(status
& AR5K_INT_RXORN
)) {
2154 * Receive buffers are full. Either the bus is busy or
2155 * the CPU is not fast enough to process all received
2157 * Older chipsets need a reset to come out of this
2158 * condition, but we treat it as RX for newer chips.
2159 * We don't know exactly which versions need a reset -
2160 * this guess is copied from the HAL.
2162 sc
->stats
.rxorn_intr
++;
2163 if (ah
->ah_mac_srev
< AR5K_SREV_AR5212
) {
2164 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
,
2165 "rx overrun, resetting\n");
2166 ieee80211_queue_work(sc
->hw
, &sc
->reset_work
);
2169 tasklet_schedule(&sc
->rxtq
);
2171 if (status
& AR5K_INT_SWBA
) {
2172 tasklet_hi_schedule(&sc
->beacontq
);
2174 if (status
& AR5K_INT_RXEOL
) {
2176 * NB: the hardware should re-read the link when
2177 * RXE bit is written, but it doesn't work at
2178 * least on older hardware revs.
2180 sc
->stats
.rxeol_intr
++;
2182 if (status
& AR5K_INT_TXURN
) {
2183 /* bump tx trigger level */
2184 ath5k_hw_update_tx_triglevel(ah
, true);
2186 if (status
& (AR5K_INT_RXOK
| AR5K_INT_RXERR
))
2187 tasklet_schedule(&sc
->rxtq
);
2188 if (status
& (AR5K_INT_TXOK
| AR5K_INT_TXDESC
2189 | AR5K_INT_TXERR
| AR5K_INT_TXEOL
))
2190 tasklet_schedule(&sc
->txtq
);
2191 if (status
& AR5K_INT_BMISS
) {
2194 if (status
& AR5K_INT_MIB
) {
2195 sc
->stats
.mib_intr
++;
2196 ath5k_hw_update_mib_counters(ah
);
2197 ath5k_ani_mib_intr(ah
);
2199 if (status
& AR5K_INT_GPIO
)
2200 tasklet_schedule(&sc
->rf_kill
.toggleq
);
2204 if (ath5k_get_bus_type(ah
) == ATH_AHB
)
2207 } while (ath5k_hw_is_intr_pending(ah
) && --counter
> 0);
2209 if (unlikely(!counter
))
2210 ATH5K_WARN(sc
, "too many interrupts, giving up for now\n");
2212 ath5k_intr_calibration_poll(ah
);
2218 * Periodically recalibrate the PHY to account
2219 * for temperature/environment changes.
2222 ath5k_tasklet_calibrate(unsigned long data
)
2224 struct ath5k_softc
*sc
= (void *)data
;
2225 struct ath5k_hw
*ah
= sc
->ah
;
2227 /* Only full calibration for now */
2228 ah
->ah_cal_mask
|= AR5K_CALIBRATION_FULL
;
2230 ATH5K_DBG(sc
, ATH5K_DEBUG_CALIBRATE
, "channel %u/%x\n",
2231 ieee80211_frequency_to_channel(sc
->curchan
->center_freq
),
2232 sc
->curchan
->hw_value
);
2234 if (ath5k_hw_gainf_calibrate(ah
) == AR5K_RFGAIN_NEED_CHANGE
) {
2236 * Rfgain is out of bounds, reset the chip
2237 * to load new gain values.
2239 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "calibration, resetting\n");
2240 ieee80211_queue_work(sc
->hw
, &sc
->reset_work
);
2242 if (ath5k_hw_phy_calibrate(ah
, sc
->curchan
))
2243 ATH5K_ERR(sc
, "calibration of channel %u failed\n",
2244 ieee80211_frequency_to_channel(
2245 sc
->curchan
->center_freq
));
2247 /* Noise floor calibration interrupts rx/tx path while I/Q calibration
2249 * TODO: We should stop TX here, so that it doesn't interfere.
2250 * Note that stopping the queues is not enough to stop TX! */
2251 if (time_is_before_eq_jiffies(ah
->ah_cal_next_nf
)) {
2252 ah
->ah_cal_next_nf
= jiffies
+
2253 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_NF
);
2254 ath5k_hw_update_noise_floor(ah
);
2257 ah
->ah_cal_mask
&= ~AR5K_CALIBRATION_FULL
;
2262 ath5k_tasklet_ani(unsigned long data
)
2264 struct ath5k_softc
*sc
= (void *)data
;
2265 struct ath5k_hw
*ah
= sc
->ah
;
2267 ah
->ah_cal_mask
|= AR5K_CALIBRATION_ANI
;
2268 ath5k_ani_calibration(ah
);
2269 ah
->ah_cal_mask
&= ~AR5K_CALIBRATION_ANI
;
2274 ath5k_tx_complete_poll_work(struct work_struct
*work
)
2276 struct ath5k_softc
*sc
= container_of(work
, struct ath5k_softc
,
2277 tx_complete_work
.work
);
2278 struct ath5k_txq
*txq
;
2280 bool needreset
= false;
2282 mutex_lock(&sc
->lock
);
2284 for (i
= 0; i
< ARRAY_SIZE(sc
->txqs
); i
++) {
2285 if (sc
->txqs
[i
].setup
) {
2287 spin_lock_bh(&txq
->lock
);
2288 if (txq
->txq_len
> 1) {
2289 if (txq
->txq_poll_mark
) {
2290 ATH5K_DBG(sc
, ATH5K_DEBUG_XMIT
,
2291 "TX queue stuck %d\n",
2295 spin_unlock_bh(&txq
->lock
);
2298 txq
->txq_poll_mark
= true;
2301 spin_unlock_bh(&txq
->lock
);
2306 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
,
2307 "TX queues stuck, resetting\n");
2308 ath5k_reset(sc
, NULL
, true);
2311 mutex_unlock(&sc
->lock
);
2313 ieee80211_queue_delayed_work(sc
->hw
, &sc
->tx_complete_work
,
2314 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT
));
2318 /*************************\
2319 * Initialization routines *
2320 \*************************/
2323 ath5k_init_softc(struct ath5k_softc
*sc
, const struct ath_bus_ops
*bus_ops
)
2325 struct ieee80211_hw
*hw
= sc
->hw
;
2326 struct ath_common
*common
;
2330 /* Initialize driver private data */
2331 SET_IEEE80211_DEV(hw
, sc
->dev
);
2332 hw
->flags
= IEEE80211_HW_RX_INCLUDES_FCS
|
2333 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING
|
2334 IEEE80211_HW_SIGNAL_DBM
|
2335 IEEE80211_HW_REPORTS_TX_ACK_STATUS
;
2337 hw
->wiphy
->interface_modes
=
2338 BIT(NL80211_IFTYPE_AP
) |
2339 BIT(NL80211_IFTYPE_STATION
) |
2340 BIT(NL80211_IFTYPE_ADHOC
) |
2341 BIT(NL80211_IFTYPE_MESH_POINT
);
2343 /* both antennas can be configured as RX or TX */
2344 hw
->wiphy
->available_antennas_tx
= 0x3;
2345 hw
->wiphy
->available_antennas_rx
= 0x3;
2347 hw
->extra_tx_headroom
= 2;
2348 hw
->channel_change_time
= 5000;
2351 * Mark the device as detached to avoid processing
2352 * interrupts until setup is complete.
2354 __set_bit(ATH_STAT_INVALID
, sc
->status
);
2356 sc
->opmode
= NL80211_IFTYPE_STATION
;
2358 mutex_init(&sc
->lock
);
2359 spin_lock_init(&sc
->rxbuflock
);
2360 spin_lock_init(&sc
->txbuflock
);
2361 spin_lock_init(&sc
->block
);
2364 /* Setup interrupt handler */
2365 ret
= request_irq(sc
->irq
, ath5k_intr
, IRQF_SHARED
, "ath", sc
);
2367 ATH5K_ERR(sc
, "request_irq failed\n");
2371 /* If we passed the test, malloc an ath5k_hw struct */
2372 sc
->ah
= kzalloc(sizeof(struct ath5k_hw
), GFP_KERNEL
);
2375 ATH5K_ERR(sc
, "out of memory\n");
2380 sc
->ah
->ah_iobase
= sc
->iobase
;
2381 common
= ath5k_hw_common(sc
->ah
);
2382 common
->ops
= &ath5k_common_ops
;
2383 common
->bus_ops
= bus_ops
;
2384 common
->ah
= sc
->ah
;
2389 * Cache line size is used to size and align various
2390 * structures used to communicate with the hardware.
2392 ath5k_read_cachesize(common
, &csz
);
2393 common
->cachelsz
= csz
<< 2; /* convert to bytes */
2395 spin_lock_init(&common
->cc_lock
);
2397 /* Initialize device */
2398 ret
= ath5k_hw_init(sc
);
2402 /* set up multi-rate retry capabilities */
2403 if (sc
->ah
->ah_version
== AR5K_AR5212
) {
2405 hw
->max_rate_tries
= max(AR5K_INIT_RETRY_SHORT
,
2406 AR5K_INIT_RETRY_LONG
);
2409 hw
->vif_data_size
= sizeof(struct ath5k_vif
);
2411 /* Finish private driver data initialization */
2412 ret
= ath5k_init(hw
);
2416 ATH5K_INFO(sc
, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
2417 ath5k_chip_name(AR5K_VERSION_MAC
, sc
->ah
->ah_mac_srev
),
2418 sc
->ah
->ah_mac_srev
,
2419 sc
->ah
->ah_phy_revision
);
2421 if (!sc
->ah
->ah_single_chip
) {
2422 /* Single chip radio (!RF5111) */
2423 if (sc
->ah
->ah_radio_5ghz_revision
&&
2424 !sc
->ah
->ah_radio_2ghz_revision
) {
2425 /* No 5GHz support -> report 2GHz radio */
2426 if (!test_bit(AR5K_MODE_11A
,
2427 sc
->ah
->ah_capabilities
.cap_mode
)) {
2428 ATH5K_INFO(sc
, "RF%s 2GHz radio found (0x%x)\n",
2429 ath5k_chip_name(AR5K_VERSION_RAD
,
2430 sc
->ah
->ah_radio_5ghz_revision
),
2431 sc
->ah
->ah_radio_5ghz_revision
);
2432 /* No 2GHz support (5110 and some
2433 * 5Ghz only cards) -> report 5Ghz radio */
2434 } else if (!test_bit(AR5K_MODE_11B
,
2435 sc
->ah
->ah_capabilities
.cap_mode
)) {
2436 ATH5K_INFO(sc
, "RF%s 5GHz radio found (0x%x)\n",
2437 ath5k_chip_name(AR5K_VERSION_RAD
,
2438 sc
->ah
->ah_radio_5ghz_revision
),
2439 sc
->ah
->ah_radio_5ghz_revision
);
2440 /* Multiband radio */
2442 ATH5K_INFO(sc
, "RF%s multiband radio found"
2444 ath5k_chip_name(AR5K_VERSION_RAD
,
2445 sc
->ah
->ah_radio_5ghz_revision
),
2446 sc
->ah
->ah_radio_5ghz_revision
);
2449 /* Multi chip radio (RF5111 - RF2111) ->
2450 * report both 2GHz/5GHz radios */
2451 else if (sc
->ah
->ah_radio_5ghz_revision
&&
2452 sc
->ah
->ah_radio_2ghz_revision
){
2453 ATH5K_INFO(sc
, "RF%s 5GHz radio found (0x%x)\n",
2454 ath5k_chip_name(AR5K_VERSION_RAD
,
2455 sc
->ah
->ah_radio_5ghz_revision
),
2456 sc
->ah
->ah_radio_5ghz_revision
);
2457 ATH5K_INFO(sc
, "RF%s 2GHz radio found (0x%x)\n",
2458 ath5k_chip_name(AR5K_VERSION_RAD
,
2459 sc
->ah
->ah_radio_2ghz_revision
),
2460 sc
->ah
->ah_radio_2ghz_revision
);
2464 ath5k_debug_init_device(sc
);
2466 /* ready to process interrupts */
2467 __clear_bit(ATH_STAT_INVALID
, sc
->status
);
2471 ath5k_hw_deinit(sc
->ah
);
2475 free_irq(sc
->irq
, sc
);
2481 ath5k_stop_locked(struct ath5k_softc
*sc
)
2483 struct ath5k_hw
*ah
= sc
->ah
;
2485 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "invalid %u\n",
2486 test_bit(ATH_STAT_INVALID
, sc
->status
));
2489 * Shutdown the hardware and driver:
2490 * stop output from above
2491 * disable interrupts
2493 * turn off the radio
2494 * clear transmit machinery
2495 * clear receive machinery
2496 * drain and release tx queues
2497 * reclaim beacon resources
2498 * power down hardware
2500 * Note that some of this work is not possible if the
2501 * hardware is gone (invalid).
2503 ieee80211_stop_queues(sc
->hw
);
2505 if (!test_bit(ATH_STAT_INVALID
, sc
->status
)) {
2507 ath5k_hw_set_imr(ah
, 0);
2508 synchronize_irq(sc
->irq
);
2510 ath5k_hw_dma_stop(ah
);
2511 ath5k_drain_tx_buffs(sc
);
2512 ath5k_hw_phy_disable(ah
);
2519 ath5k_init_hw(struct ath5k_softc
*sc
)
2521 struct ath5k_hw
*ah
= sc
->ah
;
2522 struct ath_common
*common
= ath5k_hw_common(ah
);
2525 mutex_lock(&sc
->lock
);
2527 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "mode %d\n", sc
->opmode
);
2530 * Stop anything previously setup. This is safe
2531 * no matter this is the first time through or not.
2533 ath5k_stop_locked(sc
);
2536 * The basic interface to setting the hardware in a good
2537 * state is ``reset''. On return the hardware is known to
2538 * be powered up and with interrupts disabled. This must
2539 * be followed by initialization of the appropriate bits
2540 * and then setup of the interrupt mask.
2542 sc
->curchan
= sc
->hw
->conf
.channel
;
2543 sc
->imask
= AR5K_INT_RXOK
| AR5K_INT_RXERR
| AR5K_INT_RXEOL
|
2544 AR5K_INT_RXORN
| AR5K_INT_TXDESC
| AR5K_INT_TXEOL
|
2545 AR5K_INT_FATAL
| AR5K_INT_GLOBAL
| AR5K_INT_MIB
;
2547 ret
= ath5k_reset(sc
, NULL
, false);
2551 ath5k_rfkill_hw_start(ah
);
2554 * Reset the key cache since some parts do not reset the
2555 * contents on initial power up or resume from suspend.
2557 for (i
= 0; i
< common
->keymax
; i
++)
2558 ath_hw_keyreset(common
, (u16
) i
);
2560 /* Use higher rates for acks instead of base
2562 ah
->ah_ack_bitrate_high
= true;
2564 for (i
= 0; i
< ARRAY_SIZE(sc
->bslot
); i
++)
2565 sc
->bslot
[i
] = NULL
;
2570 mutex_unlock(&sc
->lock
);
2572 ieee80211_queue_delayed_work(sc
->hw
, &sc
->tx_complete_work
,
2573 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT
));
2578 static void stop_tasklets(struct ath5k_softc
*sc
)
2580 tasklet_kill(&sc
->rxtq
);
2581 tasklet_kill(&sc
->txtq
);
2582 tasklet_kill(&sc
->calib
);
2583 tasklet_kill(&sc
->beacontq
);
2584 tasklet_kill(&sc
->ani_tasklet
);
2588 * Stop the device, grabbing the top-level lock to protect
2589 * against concurrent entry through ath5k_init (which can happen
2590 * if another thread does a system call and the thread doing the
2591 * stop is preempted).
2594 ath5k_stop_hw(struct ath5k_softc
*sc
)
2598 mutex_lock(&sc
->lock
);
2599 ret
= ath5k_stop_locked(sc
);
2600 if (ret
== 0 && !test_bit(ATH_STAT_INVALID
, sc
->status
)) {
2602 * Don't set the card in full sleep mode!
2604 * a) When the device is in this state it must be carefully
2605 * woken up or references to registers in the PCI clock
2606 * domain may freeze the bus (and system). This varies
2607 * by chip and is mostly an issue with newer parts
2608 * (madwifi sources mentioned srev >= 0x78) that go to
2609 * sleep more quickly.
2611 * b) On older chips full sleep results a weird behaviour
2612 * during wakeup. I tested various cards with srev < 0x78
2613 * and they don't wake up after module reload, a second
2614 * module reload is needed to bring the card up again.
2616 * Until we figure out what's going on don't enable
2617 * full chip reset on any chip (this is what Legacy HAL
2618 * and Sam's HAL do anyway). Instead Perform a full reset
2619 * on the device (same as initial state after attach) and
2620 * leave it idle (keep MAC/BB on warm reset) */
2621 ret
= ath5k_hw_on_hold(sc
->ah
);
2623 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
,
2624 "putting device to sleep\n");
2628 mutex_unlock(&sc
->lock
);
2632 cancel_delayed_work_sync(&sc
->tx_complete_work
);
2634 ath5k_rfkill_hw_stop(sc
->ah
);
2640 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2641 * and change to the given channel.
2643 * This should be called with sc->lock.
2646 ath5k_reset(struct ath5k_softc
*sc
, struct ieee80211_channel
*chan
,
2649 struct ath5k_hw
*ah
= sc
->ah
;
2650 struct ath_common
*common
= ath5k_hw_common(ah
);
2653 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "resetting\n");
2655 ath5k_hw_set_imr(ah
, 0);
2656 synchronize_irq(sc
->irq
);
2659 /* Save ani mode and disable ANI durring
2660 * reset. If we don't we might get false
2661 * PHY error interrupts. */
2662 ani_mode
= ah
->ah_sc
->ani_state
.ani_mode
;
2663 ath5k_ani_init(ah
, ATH5K_ANI_MODE_OFF
);
2665 /* We are going to empty hw queues
2666 * so we should also free any remaining
2668 ath5k_drain_tx_buffs(sc
);
2671 ret
= ath5k_hw_reset(ah
, sc
->opmode
, sc
->curchan
, chan
!= NULL
,
2674 ATH5K_ERR(sc
, "can't reset hardware (%d)\n", ret
);
2678 ret
= ath5k_rx_start(sc
);
2680 ATH5K_ERR(sc
, "can't start recv logic\n");
2684 ath5k_ani_init(ah
, ani_mode
);
2686 ah
->ah_cal_next_full
= jiffies
;
2687 ah
->ah_cal_next_ani
= jiffies
;
2688 ah
->ah_cal_next_nf
= jiffies
;
2689 ewma_init(&ah
->ah_beacon_rssi_avg
, 1024, 8);
2691 /* clear survey data and cycle counters */
2692 memset(&sc
->survey
, 0, sizeof(sc
->survey
));
2693 spin_lock_bh(&common
->cc_lock
);
2694 ath_hw_cycle_counters_update(common
);
2695 memset(&common
->cc_survey
, 0, sizeof(common
->cc_survey
));
2696 memset(&common
->cc_ani
, 0, sizeof(common
->cc_ani
));
2697 spin_unlock_bh(&common
->cc_lock
);
2700 * Change channels and update the h/w rate map if we're switching;
2701 * e.g. 11a to 11b/g.
2703 * We may be doing a reset in response to an ioctl that changes the
2704 * channel so update any state that might change as a result.
2708 /* ath5k_chan_change(sc, c); */
2710 ath5k_beacon_config(sc
);
2711 /* intrs are enabled by ath5k_beacon_config */
2713 ieee80211_wake_queues(sc
->hw
);
2720 static void ath5k_reset_work(struct work_struct
*work
)
2722 struct ath5k_softc
*sc
= container_of(work
, struct ath5k_softc
,
2725 mutex_lock(&sc
->lock
);
2726 ath5k_reset(sc
, NULL
, true);
2727 mutex_unlock(&sc
->lock
);
2731 ath5k_init(struct ieee80211_hw
*hw
)
2734 struct ath5k_softc
*sc
= hw
->priv
;
2735 struct ath5k_hw
*ah
= sc
->ah
;
2736 struct ath_regulatory
*regulatory
= ath5k_hw_regulatory(ah
);
2737 struct ath5k_txq
*txq
;
2738 u8 mac
[ETH_ALEN
] = {};
2743 * Check if the MAC has multi-rate retry support.
2744 * We do this by trying to setup a fake extended
2745 * descriptor. MACs that don't have support will
2746 * return false w/o doing anything. MACs that do
2747 * support it will return true w/o doing anything.
2749 ret
= ath5k_hw_setup_mrr_tx_desc(ah
, NULL
, 0, 0, 0, 0, 0, 0);
2754 __set_bit(ATH_STAT_MRRETRY
, sc
->status
);
2757 * Collect the channel list. The 802.11 layer
2758 * is resposible for filtering this list based
2759 * on settings like the phy mode and regulatory
2760 * domain restrictions.
2762 ret
= ath5k_setup_bands(hw
);
2764 ATH5K_ERR(sc
, "can't get channels\n");
2769 * Allocate tx+rx descriptors and populate the lists.
2771 ret
= ath5k_desc_alloc(sc
);
2773 ATH5K_ERR(sc
, "can't allocate descriptors\n");
2778 * Allocate hardware transmit queues: one queue for
2779 * beacon frames and one data queue for each QoS
2780 * priority. Note that hw functions handle resetting
2781 * these queues at the needed time.
2783 ret
= ath5k_beaconq_setup(ah
);
2785 ATH5K_ERR(sc
, "can't setup a beacon xmit queue\n");
2789 sc
->cabq
= ath5k_txq_setup(sc
, AR5K_TX_QUEUE_CAB
, 0);
2790 if (IS_ERR(sc
->cabq
)) {
2791 ATH5K_ERR(sc
, "can't setup cab queue\n");
2792 ret
= PTR_ERR(sc
->cabq
);
2796 /* 5211 and 5212 usually support 10 queues but we better rely on the
2797 * capability information */
2798 if (ah
->ah_capabilities
.cap_queues
.q_tx_num
>= 6) {
2799 /* This order matches mac80211's queue priority, so we can
2800 * directly use the mac80211 queue number without any mapping */
2801 txq
= ath5k_txq_setup(sc
, AR5K_TX_QUEUE_DATA
, AR5K_WME_AC_VO
);
2803 ATH5K_ERR(sc
, "can't setup xmit queue\n");
2807 txq
= ath5k_txq_setup(sc
, AR5K_TX_QUEUE_DATA
, AR5K_WME_AC_VI
);
2809 ATH5K_ERR(sc
, "can't setup xmit queue\n");
2813 txq
= ath5k_txq_setup(sc
, AR5K_TX_QUEUE_DATA
, AR5K_WME_AC_BE
);
2815 ATH5K_ERR(sc
, "can't setup xmit queue\n");
2819 txq
= ath5k_txq_setup(sc
, AR5K_TX_QUEUE_DATA
, AR5K_WME_AC_BK
);
2821 ATH5K_ERR(sc
, "can't setup xmit queue\n");
2827 /* older hardware (5210) can only support one data queue */
2828 txq
= ath5k_txq_setup(sc
, AR5K_TX_QUEUE_DATA
, AR5K_WME_AC_BE
);
2830 ATH5K_ERR(sc
, "can't setup xmit queue\n");
2837 tasklet_init(&sc
->rxtq
, ath5k_tasklet_rx
, (unsigned long)sc
);
2838 tasklet_init(&sc
->txtq
, ath5k_tasklet_tx
, (unsigned long)sc
);
2839 tasklet_init(&sc
->calib
, ath5k_tasklet_calibrate
, (unsigned long)sc
);
2840 tasklet_init(&sc
->beacontq
, ath5k_tasklet_beacon
, (unsigned long)sc
);
2841 tasklet_init(&sc
->ani_tasklet
, ath5k_tasklet_ani
, (unsigned long)sc
);
2843 INIT_WORK(&sc
->reset_work
, ath5k_reset_work
);
2844 INIT_DELAYED_WORK(&sc
->tx_complete_work
, ath5k_tx_complete_poll_work
);
2846 ret
= ath5k_eeprom_read_mac(ah
, mac
);
2848 ATH5K_ERR(sc
, "unable to read address from EEPROM\n");
2852 SET_IEEE80211_PERM_ADDR(hw
, mac
);
2853 memcpy(&sc
->lladdr
, mac
, ETH_ALEN
);
2854 /* All MAC address bits matter for ACKs */
2855 ath5k_update_bssid_mask_and_opmode(sc
, NULL
);
2857 regulatory
->current_rd
= ah
->ah_capabilities
.cap_eeprom
.ee_regdomain
;
2858 ret
= ath_regd_init(regulatory
, hw
->wiphy
, ath5k_reg_notifier
);
2860 ATH5K_ERR(sc
, "can't initialize regulatory system\n");
2864 ret
= ieee80211_register_hw(hw
);
2866 ATH5K_ERR(sc
, "can't register ieee80211 hw\n");
2870 if (!ath_is_world_regd(regulatory
))
2871 regulatory_hint(hw
->wiphy
, regulatory
->alpha2
);
2873 ath5k_init_leds(sc
);
2875 ath5k_sysfs_register(sc
);
2879 ath5k_txq_release(sc
);
2881 ath5k_hw_release_tx_queue(ah
, sc
->bhalq
);
2883 ath5k_desc_free(sc
);
2889 ath5k_deinit_softc(struct ath5k_softc
*sc
)
2891 struct ieee80211_hw
*hw
= sc
->hw
;
2894 * NB: the order of these is important:
2895 * o call the 802.11 layer before detaching ath5k_hw to
2896 * ensure callbacks into the driver to delete global
2897 * key cache entries can be handled
2898 * o reclaim the tx queue data structures after calling
2899 * the 802.11 layer as we'll get called back to reclaim
2900 * node state and potentially want to use them
2901 * o to cleanup the tx queues the hal is called, so detach
2903 * XXX: ??? detach ath5k_hw ???
2904 * Other than that, it's straightforward...
2906 ath5k_debug_finish_device(sc
);
2907 ieee80211_unregister_hw(hw
);
2908 ath5k_desc_free(sc
);
2909 ath5k_txq_release(sc
);
2910 ath5k_hw_release_tx_queue(sc
->ah
, sc
->bhalq
);
2911 ath5k_unregister_leds(sc
);
2913 ath5k_sysfs_unregister(sc
);
2915 * NB: can't reclaim these until after ieee80211_ifdetach
2916 * returns because we'll get called back to reclaim node
2917 * state and potentially want to use them.
2919 ath5k_hw_deinit(sc
->ah
);
2920 free_irq(sc
->irq
, sc
);
2924 ath_any_vif_assoc(struct ath5k_softc
*sc
)
2926 struct ath_vif_iter_data iter_data
;
2927 iter_data
.hw_macaddr
= NULL
;
2928 iter_data
.any_assoc
= false;
2929 iter_data
.need_set_hw_addr
= false;
2930 iter_data
.found_active
= true;
2932 ieee80211_iterate_active_interfaces_atomic(sc
->hw
, ath_vif_iter
,
2934 return iter_data
.any_assoc
;
2938 set_beacon_filter(struct ieee80211_hw
*hw
, bool enable
)
2940 struct ath5k_softc
*sc
= hw
->priv
;
2941 struct ath5k_hw
*ah
= sc
->ah
;
2943 rfilt
= ath5k_hw_get_rx_filter(ah
);
2945 rfilt
|= AR5K_RX_FILTER_BEACON
;
2947 rfilt
&= ~AR5K_RX_FILTER_BEACON
;
2948 ath5k_hw_set_rx_filter(ah
, rfilt
);
2949 sc
->filter_flags
= rfilt
;