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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
[deliverable/linux.git] / drivers / net / wireless / ath / ath5k / base.c
1 /*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
43 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44
45 #include <linux/module.h>
46 #include <linux/delay.h>
47 #include <linux/dma-mapping.h>
48 #include <linux/hardirq.h>
49 #include <linux/if.h>
50 #include <linux/io.h>
51 #include <linux/netdevice.h>
52 #include <linux/cache.h>
53 #include <linux/ethtool.h>
54 #include <linux/uaccess.h>
55 #include <linux/slab.h>
56 #include <linux/etherdevice.h>
57 #include <linux/nl80211.h>
58
59 #include <net/ieee80211_radiotap.h>
60
61 #include <asm/unaligned.h>
62
63 #include "base.h"
64 #include "reg.h"
65 #include "debug.h"
66 #include "ani.h"
67 #include "ath5k.h"
68 #include "../regd.h"
69
70 #define CREATE_TRACE_POINTS
71 #include "trace.h"
72
73 bool ath5k_modparam_nohwcrypt;
74 module_param_named(nohwcrypt, ath5k_modparam_nohwcrypt, bool, S_IRUGO);
75 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
76
77 static bool modparam_fastchanswitch;
78 module_param_named(fastchanswitch, modparam_fastchanswitch, bool, S_IRUGO);
79 MODULE_PARM_DESC(fastchanswitch, "Enable fast channel switching for AR2413/AR5413 radios.");
80
81 static bool ath5k_modparam_no_hw_rfkill_switch;
82 module_param_named(no_hw_rfkill_switch, ath5k_modparam_no_hw_rfkill_switch,
83 bool, S_IRUGO);
84 MODULE_PARM_DESC(no_hw_rfkill_switch, "Ignore the GPIO RFKill switch state");
85
86
87 /* Module info */
88 MODULE_AUTHOR("Jiri Slaby");
89 MODULE_AUTHOR("Nick Kossifidis");
90 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
91 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
92 MODULE_LICENSE("Dual BSD/GPL");
93
94 static int ath5k_init(struct ieee80211_hw *hw);
95 static int ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan,
96 bool skip_pcu);
97
98 /* Known SREVs */
99 static const struct ath5k_srev_name srev_names[] = {
100 #ifdef CONFIG_ATHEROS_AR231X
101 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R2 },
102 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R7 },
103 { "2313", AR5K_VERSION_MAC, AR5K_SREV_AR2313_R8 },
104 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R6 },
105 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R7 },
106 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R1 },
107 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R2 },
108 #else
109 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
110 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
111 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
112 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
113 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
114 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
115 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
116 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
117 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
118 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
119 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
120 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
121 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
122 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
123 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
124 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
125 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
126 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
127 #endif
128 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
129 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
130 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
131 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
132 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
133 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
134 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
135 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
136 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
137 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
138 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
139 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
140 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
141 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
142 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
143 #ifdef CONFIG_ATHEROS_AR231X
144 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
145 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
146 #endif
147 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
148 };
149
150 static const struct ieee80211_rate ath5k_rates[] = {
151 { .bitrate = 10,
152 .hw_value = ATH5K_RATE_CODE_1M, },
153 { .bitrate = 20,
154 .hw_value = ATH5K_RATE_CODE_2M,
155 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
156 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
157 { .bitrate = 55,
158 .hw_value = ATH5K_RATE_CODE_5_5M,
159 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
160 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
161 { .bitrate = 110,
162 .hw_value = ATH5K_RATE_CODE_11M,
163 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
164 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
165 { .bitrate = 60,
166 .hw_value = ATH5K_RATE_CODE_6M,
167 .flags = 0 },
168 { .bitrate = 90,
169 .hw_value = ATH5K_RATE_CODE_9M,
170 .flags = 0 },
171 { .bitrate = 120,
172 .hw_value = ATH5K_RATE_CODE_12M,
173 .flags = 0 },
174 { .bitrate = 180,
175 .hw_value = ATH5K_RATE_CODE_18M,
176 .flags = 0 },
177 { .bitrate = 240,
178 .hw_value = ATH5K_RATE_CODE_24M,
179 .flags = 0 },
180 { .bitrate = 360,
181 .hw_value = ATH5K_RATE_CODE_36M,
182 .flags = 0 },
183 { .bitrate = 480,
184 .hw_value = ATH5K_RATE_CODE_48M,
185 .flags = 0 },
186 { .bitrate = 540,
187 .hw_value = ATH5K_RATE_CODE_54M,
188 .flags = 0 },
189 };
190
191 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
192 {
193 u64 tsf = ath5k_hw_get_tsf64(ah);
194
195 if ((tsf & 0x7fff) < rstamp)
196 tsf -= 0x8000;
197
198 return (tsf & ~0x7fff) | rstamp;
199 }
200
201 const char *
202 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
203 {
204 const char *name = "xxxxx";
205 unsigned int i;
206
207 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
208 if (srev_names[i].sr_type != type)
209 continue;
210
211 if ((val & 0xf0) == srev_names[i].sr_val)
212 name = srev_names[i].sr_name;
213
214 if ((val & 0xff) == srev_names[i].sr_val) {
215 name = srev_names[i].sr_name;
216 break;
217 }
218 }
219
220 return name;
221 }
222 static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
223 {
224 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
225 return ath5k_hw_reg_read(ah, reg_offset);
226 }
227
228 static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
229 {
230 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
231 ath5k_hw_reg_write(ah, val, reg_offset);
232 }
233
234 static const struct ath_ops ath5k_common_ops = {
235 .read = ath5k_ioread32,
236 .write = ath5k_iowrite32,
237 };
238
239 /***********************\
240 * Driver Initialization *
241 \***********************/
242
243 static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
244 {
245 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
246 struct ath5k_hw *ah = hw->priv;
247 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
248
249 return ath_reg_notifier_apply(wiphy, request, regulatory);
250 }
251
252 /********************\
253 * Channel/mode setup *
254 \********************/
255
256 /*
257 * Returns true for the channel numbers used.
258 */
259 #ifdef CONFIG_ATH5K_TEST_CHANNELS
260 static bool ath5k_is_standard_channel(short chan, enum ieee80211_band band)
261 {
262 return true;
263 }
264
265 #else
266 static bool ath5k_is_standard_channel(short chan, enum ieee80211_band band)
267 {
268 if (band == IEEE80211_BAND_2GHZ && chan <= 14)
269 return true;
270
271 return /* UNII 1,2 */
272 (((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
273 /* midband */
274 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
275 /* UNII-3 */
276 ((chan & 3) == 1 && chan >= 149 && chan <= 165) ||
277 /* 802.11j 5.030-5.080 GHz (20MHz) */
278 (chan == 8 || chan == 12 || chan == 16) ||
279 /* 802.11j 4.9GHz (20MHz) */
280 (chan == 184 || chan == 188 || chan == 192 || chan == 196));
281 }
282 #endif
283
284 static unsigned int
285 ath5k_setup_channels(struct ath5k_hw *ah, struct ieee80211_channel *channels,
286 unsigned int mode, unsigned int max)
287 {
288 unsigned int count, size, freq, ch;
289 enum ieee80211_band band;
290
291 switch (mode) {
292 case AR5K_MODE_11A:
293 /* 1..220, but 2GHz frequencies are filtered by check_channel */
294 size = 220;
295 band = IEEE80211_BAND_5GHZ;
296 break;
297 case AR5K_MODE_11B:
298 case AR5K_MODE_11G:
299 size = 26;
300 band = IEEE80211_BAND_2GHZ;
301 break;
302 default:
303 ATH5K_WARN(ah, "bad mode, not copying channels\n");
304 return 0;
305 }
306
307 count = 0;
308 for (ch = 1; ch <= size && count < max; ch++) {
309 freq = ieee80211_channel_to_frequency(ch, band);
310
311 if (freq == 0) /* mapping failed - not a standard channel */
312 continue;
313
314 /* Write channel info, needed for ath5k_channel_ok() */
315 channels[count].center_freq = freq;
316 channels[count].band = band;
317 channels[count].hw_value = mode;
318
319 /* Check if channel is supported by the chipset */
320 if (!ath5k_channel_ok(ah, &channels[count]))
321 continue;
322
323 if (!ath5k_is_standard_channel(ch, band))
324 continue;
325
326 count++;
327 }
328
329 return count;
330 }
331
332 static void
333 ath5k_setup_rate_idx(struct ath5k_hw *ah, struct ieee80211_supported_band *b)
334 {
335 u8 i;
336
337 for (i = 0; i < AR5K_MAX_RATES; i++)
338 ah->rate_idx[b->band][i] = -1;
339
340 for (i = 0; i < b->n_bitrates; i++) {
341 ah->rate_idx[b->band][b->bitrates[i].hw_value] = i;
342 if (b->bitrates[i].hw_value_short)
343 ah->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
344 }
345 }
346
347 static int
348 ath5k_setup_bands(struct ieee80211_hw *hw)
349 {
350 struct ath5k_hw *ah = hw->priv;
351 struct ieee80211_supported_band *sband;
352 int max_c, count_c = 0;
353 int i;
354
355 BUILD_BUG_ON(ARRAY_SIZE(ah->sbands) < IEEE80211_NUM_BANDS);
356 max_c = ARRAY_SIZE(ah->channels);
357
358 /* 2GHz band */
359 sband = &ah->sbands[IEEE80211_BAND_2GHZ];
360 sband->band = IEEE80211_BAND_2GHZ;
361 sband->bitrates = &ah->rates[IEEE80211_BAND_2GHZ][0];
362
363 if (test_bit(AR5K_MODE_11G, ah->ah_capabilities.cap_mode)) {
364 /* G mode */
365 memcpy(sband->bitrates, &ath5k_rates[0],
366 sizeof(struct ieee80211_rate) * 12);
367 sband->n_bitrates = 12;
368
369 sband->channels = ah->channels;
370 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
371 AR5K_MODE_11G, max_c);
372
373 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
374 count_c = sband->n_channels;
375 max_c -= count_c;
376 } else if (test_bit(AR5K_MODE_11B, ah->ah_capabilities.cap_mode)) {
377 /* B mode */
378 memcpy(sband->bitrates, &ath5k_rates[0],
379 sizeof(struct ieee80211_rate) * 4);
380 sband->n_bitrates = 4;
381
382 /* 5211 only supports B rates and uses 4bit rate codes
383 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
384 * fix them up here:
385 */
386 if (ah->ah_version == AR5K_AR5211) {
387 for (i = 0; i < 4; i++) {
388 sband->bitrates[i].hw_value =
389 sband->bitrates[i].hw_value & 0xF;
390 sband->bitrates[i].hw_value_short =
391 sband->bitrates[i].hw_value_short & 0xF;
392 }
393 }
394
395 sband->channels = ah->channels;
396 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
397 AR5K_MODE_11B, max_c);
398
399 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
400 count_c = sband->n_channels;
401 max_c -= count_c;
402 }
403 ath5k_setup_rate_idx(ah, sband);
404
405 /* 5GHz band, A mode */
406 if (test_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode)) {
407 sband = &ah->sbands[IEEE80211_BAND_5GHZ];
408 sband->band = IEEE80211_BAND_5GHZ;
409 sband->bitrates = &ah->rates[IEEE80211_BAND_5GHZ][0];
410
411 memcpy(sband->bitrates, &ath5k_rates[4],
412 sizeof(struct ieee80211_rate) * 8);
413 sband->n_bitrates = 8;
414
415 sband->channels = &ah->channels[count_c];
416 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
417 AR5K_MODE_11A, max_c);
418
419 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
420 }
421 ath5k_setup_rate_idx(ah, sband);
422
423 ath5k_debug_dump_bands(ah);
424
425 return 0;
426 }
427
428 /*
429 * Set/change channels. We always reset the chip.
430 * To accomplish this we must first cleanup any pending DMA,
431 * then restart stuff after a la ath5k_init.
432 *
433 * Called with ah->lock.
434 */
435 int
436 ath5k_chan_set(struct ath5k_hw *ah, struct ieee80211_channel *chan)
437 {
438 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
439 "channel set, resetting (%u -> %u MHz)\n",
440 ah->curchan->center_freq, chan->center_freq);
441
442 /*
443 * To switch channels clear any pending DMA operations;
444 * wait long enough for the RX fifo to drain, reset the
445 * hardware at the new frequency, and then re-enable
446 * the relevant bits of the h/w.
447 */
448 return ath5k_reset(ah, chan, true);
449 }
450
451 void ath5k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
452 {
453 struct ath5k_vif_iter_data *iter_data = data;
454 int i;
455 struct ath5k_vif *avf = (void *)vif->drv_priv;
456
457 if (iter_data->hw_macaddr)
458 for (i = 0; i < ETH_ALEN; i++)
459 iter_data->mask[i] &=
460 ~(iter_data->hw_macaddr[i] ^ mac[i]);
461
462 if (!iter_data->found_active) {
463 iter_data->found_active = true;
464 memcpy(iter_data->active_mac, mac, ETH_ALEN);
465 }
466
467 if (iter_data->need_set_hw_addr && iter_data->hw_macaddr)
468 if (ether_addr_equal(iter_data->hw_macaddr, mac))
469 iter_data->need_set_hw_addr = false;
470
471 if (!iter_data->any_assoc) {
472 if (avf->assoc)
473 iter_data->any_assoc = true;
474 }
475
476 /* Calculate combined mode - when APs are active, operate in AP mode.
477 * Otherwise use the mode of the new interface. This can currently
478 * only deal with combinations of APs and STAs. Only one ad-hoc
479 * interfaces is allowed.
480 */
481 if (avf->opmode == NL80211_IFTYPE_AP)
482 iter_data->opmode = NL80211_IFTYPE_AP;
483 else {
484 if (avf->opmode == NL80211_IFTYPE_STATION)
485 iter_data->n_stas++;
486 if (iter_data->opmode == NL80211_IFTYPE_UNSPECIFIED)
487 iter_data->opmode = avf->opmode;
488 }
489 }
490
491 void
492 ath5k_update_bssid_mask_and_opmode(struct ath5k_hw *ah,
493 struct ieee80211_vif *vif)
494 {
495 struct ath_common *common = ath5k_hw_common(ah);
496 struct ath5k_vif_iter_data iter_data;
497 u32 rfilt;
498
499 /*
500 * Use the hardware MAC address as reference, the hardware uses it
501 * together with the BSSID mask when matching addresses.
502 */
503 iter_data.hw_macaddr = common->macaddr;
504 memset(&iter_data.mask, 0xff, ETH_ALEN);
505 iter_data.found_active = false;
506 iter_data.need_set_hw_addr = true;
507 iter_data.opmode = NL80211_IFTYPE_UNSPECIFIED;
508 iter_data.n_stas = 0;
509
510 if (vif)
511 ath5k_vif_iter(&iter_data, vif->addr, vif);
512
513 /* Get list of all active MAC addresses */
514 ieee80211_iterate_active_interfaces_atomic(ah->hw, ath5k_vif_iter,
515 &iter_data);
516 memcpy(ah->bssidmask, iter_data.mask, ETH_ALEN);
517
518 ah->opmode = iter_data.opmode;
519 if (ah->opmode == NL80211_IFTYPE_UNSPECIFIED)
520 /* Nothing active, default to station mode */
521 ah->opmode = NL80211_IFTYPE_STATION;
522
523 ath5k_hw_set_opmode(ah, ah->opmode);
524 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n",
525 ah->opmode, ath_opmode_to_string(ah->opmode));
526
527 if (iter_data.need_set_hw_addr && iter_data.found_active)
528 ath5k_hw_set_lladdr(ah, iter_data.active_mac);
529
530 if (ath5k_hw_hasbssidmask(ah))
531 ath5k_hw_set_bssid_mask(ah, ah->bssidmask);
532
533 /* Set up RX Filter */
534 if (iter_data.n_stas > 1) {
535 /* If you have multiple STA interfaces connected to
536 * different APs, ARPs are not received (most of the time?)
537 * Enabling PROMISC appears to fix that problem.
538 */
539 ah->filter_flags |= AR5K_RX_FILTER_PROM;
540 }
541
542 rfilt = ah->filter_flags;
543 ath5k_hw_set_rx_filter(ah, rfilt);
544 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
545 }
546
547 static inline int
548 ath5k_hw_to_driver_rix(struct ath5k_hw *ah, int hw_rix)
549 {
550 int rix;
551
552 /* return base rate on errors */
553 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
554 "hw_rix out of bounds: %x\n", hw_rix))
555 return 0;
556
557 rix = ah->rate_idx[ah->curchan->band][hw_rix];
558 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
559 rix = 0;
560
561 return rix;
562 }
563
564 /***************\
565 * Buffers setup *
566 \***************/
567
568 static
569 struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_hw *ah, dma_addr_t *skb_addr)
570 {
571 struct ath_common *common = ath5k_hw_common(ah);
572 struct sk_buff *skb;
573
574 /*
575 * Allocate buffer with headroom_needed space for the
576 * fake physical layer header at the start.
577 */
578 skb = ath_rxbuf_alloc(common,
579 common->rx_bufsize,
580 GFP_ATOMIC);
581
582 if (!skb) {
583 ATH5K_ERR(ah, "can't alloc skbuff of size %u\n",
584 common->rx_bufsize);
585 return NULL;
586 }
587
588 *skb_addr = dma_map_single(ah->dev,
589 skb->data, common->rx_bufsize,
590 DMA_FROM_DEVICE);
591
592 if (unlikely(dma_mapping_error(ah->dev, *skb_addr))) {
593 ATH5K_ERR(ah, "%s: DMA mapping failed\n", __func__);
594 dev_kfree_skb(skb);
595 return NULL;
596 }
597 return skb;
598 }
599
600 static int
601 ath5k_rxbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf)
602 {
603 struct sk_buff *skb = bf->skb;
604 struct ath5k_desc *ds;
605 int ret;
606
607 if (!skb) {
608 skb = ath5k_rx_skb_alloc(ah, &bf->skbaddr);
609 if (!skb)
610 return -ENOMEM;
611 bf->skb = skb;
612 }
613
614 /*
615 * Setup descriptors. For receive we always terminate
616 * the descriptor list with a self-linked entry so we'll
617 * not get overrun under high load (as can happen with a
618 * 5212 when ANI processing enables PHY error frames).
619 *
620 * To ensure the last descriptor is self-linked we create
621 * each descriptor as self-linked and add it to the end. As
622 * each additional descriptor is added the previous self-linked
623 * entry is "fixed" naturally. This should be safe even
624 * if DMA is happening. When processing RX interrupts we
625 * never remove/process the last, self-linked, entry on the
626 * descriptor list. This ensures the hardware always has
627 * someplace to write a new frame.
628 */
629 ds = bf->desc;
630 ds->ds_link = bf->daddr; /* link to self */
631 ds->ds_data = bf->skbaddr;
632 ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0);
633 if (ret) {
634 ATH5K_ERR(ah, "%s: could not setup RX desc\n", __func__);
635 return ret;
636 }
637
638 if (ah->rxlink != NULL)
639 *ah->rxlink = bf->daddr;
640 ah->rxlink = &ds->ds_link;
641 return 0;
642 }
643
644 static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
645 {
646 struct ieee80211_hdr *hdr;
647 enum ath5k_pkt_type htype;
648 __le16 fc;
649
650 hdr = (struct ieee80211_hdr *)skb->data;
651 fc = hdr->frame_control;
652
653 if (ieee80211_is_beacon(fc))
654 htype = AR5K_PKT_TYPE_BEACON;
655 else if (ieee80211_is_probe_resp(fc))
656 htype = AR5K_PKT_TYPE_PROBE_RESP;
657 else if (ieee80211_is_atim(fc))
658 htype = AR5K_PKT_TYPE_ATIM;
659 else if (ieee80211_is_pspoll(fc))
660 htype = AR5K_PKT_TYPE_PSPOLL;
661 else
662 htype = AR5K_PKT_TYPE_NORMAL;
663
664 return htype;
665 }
666
667 static int
668 ath5k_txbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf,
669 struct ath5k_txq *txq, int padsize)
670 {
671 struct ath5k_desc *ds = bf->desc;
672 struct sk_buff *skb = bf->skb;
673 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
674 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
675 struct ieee80211_rate *rate;
676 unsigned int mrr_rate[3], mrr_tries[3];
677 int i, ret;
678 u16 hw_rate;
679 u16 cts_rate = 0;
680 u16 duration = 0;
681 u8 rc_flags;
682
683 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
684
685 /* XXX endianness */
686 bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len,
687 DMA_TO_DEVICE);
688
689 rate = ieee80211_get_tx_rate(ah->hw, info);
690 if (!rate) {
691 ret = -EINVAL;
692 goto err_unmap;
693 }
694
695 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
696 flags |= AR5K_TXDESC_NOACK;
697
698 rc_flags = info->control.rates[0].flags;
699 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
700 rate->hw_value_short : rate->hw_value;
701
702 pktlen = skb->len;
703
704 /* FIXME: If we are in g mode and rate is a CCK rate
705 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
706 * from tx power (value is in dB units already) */
707 if (info->control.hw_key) {
708 keyidx = info->control.hw_key->hw_key_idx;
709 pktlen += info->control.hw_key->icv_len;
710 }
711 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
712 flags |= AR5K_TXDESC_RTSENA;
713 cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value;
714 duration = le16_to_cpu(ieee80211_rts_duration(ah->hw,
715 info->control.vif, pktlen, info));
716 }
717 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
718 flags |= AR5K_TXDESC_CTSENA;
719 cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value;
720 duration = le16_to_cpu(ieee80211_ctstoself_duration(ah->hw,
721 info->control.vif, pktlen, info));
722 }
723 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
724 ieee80211_get_hdrlen_from_skb(skb), padsize,
725 get_hw_packet_type(skb),
726 (ah->ah_txpower.txp_requested * 2),
727 hw_rate,
728 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
729 cts_rate, duration);
730 if (ret)
731 goto err_unmap;
732
733 /* Set up MRR descriptor */
734 if (ah->ah_capabilities.cap_has_mrr_support) {
735 memset(mrr_rate, 0, sizeof(mrr_rate));
736 memset(mrr_tries, 0, sizeof(mrr_tries));
737 for (i = 0; i < 3; i++) {
738 rate = ieee80211_get_alt_retry_rate(ah->hw, info, i);
739 if (!rate)
740 break;
741
742 mrr_rate[i] = rate->hw_value;
743 mrr_tries[i] = info->control.rates[i + 1].count;
744 }
745
746 ath5k_hw_setup_mrr_tx_desc(ah, ds,
747 mrr_rate[0], mrr_tries[0],
748 mrr_rate[1], mrr_tries[1],
749 mrr_rate[2], mrr_tries[2]);
750 }
751
752 ds->ds_link = 0;
753 ds->ds_data = bf->skbaddr;
754
755 spin_lock_bh(&txq->lock);
756 list_add_tail(&bf->list, &txq->q);
757 txq->txq_len++;
758 if (txq->link == NULL) /* is this first packet? */
759 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
760 else /* no, so only link it */
761 *txq->link = bf->daddr;
762
763 txq->link = &ds->ds_link;
764 ath5k_hw_start_tx_dma(ah, txq->qnum);
765 mmiowb();
766 spin_unlock_bh(&txq->lock);
767
768 return 0;
769 err_unmap:
770 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
771 return ret;
772 }
773
774 /*******************\
775 * Descriptors setup *
776 \*******************/
777
778 static int
779 ath5k_desc_alloc(struct ath5k_hw *ah)
780 {
781 struct ath5k_desc *ds;
782 struct ath5k_buf *bf;
783 dma_addr_t da;
784 unsigned int i;
785 int ret;
786
787 /* allocate descriptors */
788 ah->desc_len = sizeof(struct ath5k_desc) *
789 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
790
791 ah->desc = dma_alloc_coherent(ah->dev, ah->desc_len,
792 &ah->desc_daddr, GFP_KERNEL);
793 if (ah->desc == NULL) {
794 ATH5K_ERR(ah, "can't allocate descriptors\n");
795 ret = -ENOMEM;
796 goto err;
797 }
798 ds = ah->desc;
799 da = ah->desc_daddr;
800 ATH5K_DBG(ah, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
801 ds, ah->desc_len, (unsigned long long)ah->desc_daddr);
802
803 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
804 sizeof(struct ath5k_buf), GFP_KERNEL);
805 if (bf == NULL) {
806 ATH5K_ERR(ah, "can't allocate bufptr\n");
807 ret = -ENOMEM;
808 goto err_free;
809 }
810 ah->bufptr = bf;
811
812 INIT_LIST_HEAD(&ah->rxbuf);
813 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
814 bf->desc = ds;
815 bf->daddr = da;
816 list_add_tail(&bf->list, &ah->rxbuf);
817 }
818
819 INIT_LIST_HEAD(&ah->txbuf);
820 ah->txbuf_len = ATH_TXBUF;
821 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
822 bf->desc = ds;
823 bf->daddr = da;
824 list_add_tail(&bf->list, &ah->txbuf);
825 }
826
827 /* beacon buffers */
828 INIT_LIST_HEAD(&ah->bcbuf);
829 for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) {
830 bf->desc = ds;
831 bf->daddr = da;
832 list_add_tail(&bf->list, &ah->bcbuf);
833 }
834
835 return 0;
836 err_free:
837 dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr);
838 err:
839 ah->desc = NULL;
840 return ret;
841 }
842
843 void
844 ath5k_txbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf)
845 {
846 BUG_ON(!bf);
847 if (!bf->skb)
848 return;
849 dma_unmap_single(ah->dev, bf->skbaddr, bf->skb->len,
850 DMA_TO_DEVICE);
851 dev_kfree_skb_any(bf->skb);
852 bf->skb = NULL;
853 bf->skbaddr = 0;
854 bf->desc->ds_data = 0;
855 }
856
857 void
858 ath5k_rxbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf)
859 {
860 struct ath_common *common = ath5k_hw_common(ah);
861
862 BUG_ON(!bf);
863 if (!bf->skb)
864 return;
865 dma_unmap_single(ah->dev, bf->skbaddr, common->rx_bufsize,
866 DMA_FROM_DEVICE);
867 dev_kfree_skb_any(bf->skb);
868 bf->skb = NULL;
869 bf->skbaddr = 0;
870 bf->desc->ds_data = 0;
871 }
872
873 static void
874 ath5k_desc_free(struct ath5k_hw *ah)
875 {
876 struct ath5k_buf *bf;
877
878 list_for_each_entry(bf, &ah->txbuf, list)
879 ath5k_txbuf_free_skb(ah, bf);
880 list_for_each_entry(bf, &ah->rxbuf, list)
881 ath5k_rxbuf_free_skb(ah, bf);
882 list_for_each_entry(bf, &ah->bcbuf, list)
883 ath5k_txbuf_free_skb(ah, bf);
884
885 /* Free memory associated with all descriptors */
886 dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr);
887 ah->desc = NULL;
888 ah->desc_daddr = 0;
889
890 kfree(ah->bufptr);
891 ah->bufptr = NULL;
892 }
893
894
895 /**************\
896 * Queues setup *
897 \**************/
898
899 static struct ath5k_txq *
900 ath5k_txq_setup(struct ath5k_hw *ah,
901 int qtype, int subtype)
902 {
903 struct ath5k_txq *txq;
904 struct ath5k_txq_info qi = {
905 .tqi_subtype = subtype,
906 /* XXX: default values not correct for B and XR channels,
907 * but who cares? */
908 .tqi_aifs = AR5K_TUNE_AIFS,
909 .tqi_cw_min = AR5K_TUNE_CWMIN,
910 .tqi_cw_max = AR5K_TUNE_CWMAX
911 };
912 int qnum;
913
914 /*
915 * Enable interrupts only for EOL and DESC conditions.
916 * We mark tx descriptors to receive a DESC interrupt
917 * when a tx queue gets deep; otherwise we wait for the
918 * EOL to reap descriptors. Note that this is done to
919 * reduce interrupt load and this only defers reaping
920 * descriptors, never transmitting frames. Aside from
921 * reducing interrupts this also permits more concurrency.
922 * The only potential downside is if the tx queue backs
923 * up in which case the top half of the kernel may backup
924 * due to a lack of tx descriptors.
925 */
926 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
927 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
928 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
929 if (qnum < 0) {
930 /*
931 * NB: don't print a message, this happens
932 * normally on parts with too few tx queues
933 */
934 return ERR_PTR(qnum);
935 }
936 txq = &ah->txqs[qnum];
937 if (!txq->setup) {
938 txq->qnum = qnum;
939 txq->link = NULL;
940 INIT_LIST_HEAD(&txq->q);
941 spin_lock_init(&txq->lock);
942 txq->setup = true;
943 txq->txq_len = 0;
944 txq->txq_max = ATH5K_TXQ_LEN_MAX;
945 txq->txq_poll_mark = false;
946 txq->txq_stuck = 0;
947 }
948 return &ah->txqs[qnum];
949 }
950
951 static int
952 ath5k_beaconq_setup(struct ath5k_hw *ah)
953 {
954 struct ath5k_txq_info qi = {
955 /* XXX: default values not correct for B and XR channels,
956 * but who cares? */
957 .tqi_aifs = AR5K_TUNE_AIFS,
958 .tqi_cw_min = AR5K_TUNE_CWMIN,
959 .tqi_cw_max = AR5K_TUNE_CWMAX,
960 /* NB: for dynamic turbo, don't enable any other interrupts */
961 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
962 };
963
964 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
965 }
966
967 static int
968 ath5k_beaconq_config(struct ath5k_hw *ah)
969 {
970 struct ath5k_txq_info qi;
971 int ret;
972
973 ret = ath5k_hw_get_tx_queueprops(ah, ah->bhalq, &qi);
974 if (ret)
975 goto err;
976
977 if (ah->opmode == NL80211_IFTYPE_AP ||
978 ah->opmode == NL80211_IFTYPE_MESH_POINT) {
979 /*
980 * Always burst out beacon and CAB traffic
981 * (aifs = cwmin = cwmax = 0)
982 */
983 qi.tqi_aifs = 0;
984 qi.tqi_cw_min = 0;
985 qi.tqi_cw_max = 0;
986 } else if (ah->opmode == NL80211_IFTYPE_ADHOC) {
987 /*
988 * Adhoc mode; backoff between 0 and (2 * cw_min).
989 */
990 qi.tqi_aifs = 0;
991 qi.tqi_cw_min = 0;
992 qi.tqi_cw_max = 2 * AR5K_TUNE_CWMIN;
993 }
994
995 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
996 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
997 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
998
999 ret = ath5k_hw_set_tx_queueprops(ah, ah->bhalq, &qi);
1000 if (ret) {
1001 ATH5K_ERR(ah, "%s: unable to update parameters for beacon "
1002 "hardware queue!\n", __func__);
1003 goto err;
1004 }
1005 ret = ath5k_hw_reset_tx_queue(ah, ah->bhalq); /* push to h/w */
1006 if (ret)
1007 goto err;
1008
1009 /* reconfigure cabq with ready time to 80% of beacon_interval */
1010 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1011 if (ret)
1012 goto err;
1013
1014 qi.tqi_ready_time = (ah->bintval * 80) / 100;
1015 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1016 if (ret)
1017 goto err;
1018
1019 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB);
1020 err:
1021 return ret;
1022 }
1023
1024 /**
1025 * ath5k_drain_tx_buffs - Empty tx buffers
1026 *
1027 * @ah The &struct ath5k_hw
1028 *
1029 * Empty tx buffers from all queues in preparation
1030 * of a reset or during shutdown.
1031 *
1032 * NB: this assumes output has been stopped and
1033 * we do not need to block ath5k_tx_tasklet
1034 */
1035 static void
1036 ath5k_drain_tx_buffs(struct ath5k_hw *ah)
1037 {
1038 struct ath5k_txq *txq;
1039 struct ath5k_buf *bf, *bf0;
1040 int i;
1041
1042 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) {
1043 if (ah->txqs[i].setup) {
1044 txq = &ah->txqs[i];
1045 spin_lock_bh(&txq->lock);
1046 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1047 ath5k_debug_printtxbuf(ah, bf);
1048
1049 ath5k_txbuf_free_skb(ah, bf);
1050
1051 spin_lock(&ah->txbuflock);
1052 list_move_tail(&bf->list, &ah->txbuf);
1053 ah->txbuf_len++;
1054 txq->txq_len--;
1055 spin_unlock(&ah->txbuflock);
1056 }
1057 txq->link = NULL;
1058 txq->txq_poll_mark = false;
1059 spin_unlock_bh(&txq->lock);
1060 }
1061 }
1062 }
1063
1064 static void
1065 ath5k_txq_release(struct ath5k_hw *ah)
1066 {
1067 struct ath5k_txq *txq = ah->txqs;
1068 unsigned int i;
1069
1070 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++, txq++)
1071 if (txq->setup) {
1072 ath5k_hw_release_tx_queue(ah, txq->qnum);
1073 txq->setup = false;
1074 }
1075 }
1076
1077
1078 /*************\
1079 * RX Handling *
1080 \*************/
1081
1082 /*
1083 * Enable the receive h/w following a reset.
1084 */
1085 static int
1086 ath5k_rx_start(struct ath5k_hw *ah)
1087 {
1088 struct ath_common *common = ath5k_hw_common(ah);
1089 struct ath5k_buf *bf;
1090 int ret;
1091
1092 common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz);
1093
1094 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
1095 common->cachelsz, common->rx_bufsize);
1096
1097 spin_lock_bh(&ah->rxbuflock);
1098 ah->rxlink = NULL;
1099 list_for_each_entry(bf, &ah->rxbuf, list) {
1100 ret = ath5k_rxbuf_setup(ah, bf);
1101 if (ret != 0) {
1102 spin_unlock_bh(&ah->rxbuflock);
1103 goto err;
1104 }
1105 }
1106 bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list);
1107 ath5k_hw_set_rxdp(ah, bf->daddr);
1108 spin_unlock_bh(&ah->rxbuflock);
1109
1110 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
1111 ath5k_update_bssid_mask_and_opmode(ah, NULL); /* set filters, etc. */
1112 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1113
1114 return 0;
1115 err:
1116 return ret;
1117 }
1118
1119 /*
1120 * Disable the receive logic on PCU (DRU)
1121 * In preparation for a shutdown.
1122 *
1123 * Note: Doesn't stop rx DMA, ath5k_hw_dma_stop
1124 * does.
1125 */
1126 static void
1127 ath5k_rx_stop(struct ath5k_hw *ah)
1128 {
1129
1130 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1131 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
1132
1133 ath5k_debug_printrxbuffs(ah);
1134 }
1135
1136 static unsigned int
1137 ath5k_rx_decrypted(struct ath5k_hw *ah, struct sk_buff *skb,
1138 struct ath5k_rx_status *rs)
1139 {
1140 struct ath_common *common = ath5k_hw_common(ah);
1141 struct ieee80211_hdr *hdr = (void *)skb->data;
1142 unsigned int keyix, hlen;
1143
1144 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1145 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1146 return RX_FLAG_DECRYPTED;
1147
1148 /* Apparently when a default key is used to decrypt the packet
1149 the hw does not set the index used to decrypt. In such cases
1150 get the index from the packet. */
1151 hlen = ieee80211_hdrlen(hdr->frame_control);
1152 if (ieee80211_has_protected(hdr->frame_control) &&
1153 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1154 skb->len >= hlen + 4) {
1155 keyix = skb->data[hlen + 3] >> 6;
1156
1157 if (test_bit(keyix, common->keymap))
1158 return RX_FLAG_DECRYPTED;
1159 }
1160
1161 return 0;
1162 }
1163
1164
1165 static void
1166 ath5k_check_ibss_tsf(struct ath5k_hw *ah, struct sk_buff *skb,
1167 struct ieee80211_rx_status *rxs)
1168 {
1169 struct ath_common *common = ath5k_hw_common(ah);
1170 u64 tsf, bc_tstamp;
1171 u32 hw_tu;
1172 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1173
1174 if (ieee80211_is_beacon(mgmt->frame_control) &&
1175 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1176 ether_addr_equal(mgmt->bssid, common->curbssid)) {
1177 /*
1178 * Received an IBSS beacon with the same BSSID. Hardware *must*
1179 * have updated the local TSF. We have to work around various
1180 * hardware bugs, though...
1181 */
1182 tsf = ath5k_hw_get_tsf64(ah);
1183 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1184 hw_tu = TSF_TO_TU(tsf);
1185
1186 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
1187 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1188 (unsigned long long)bc_tstamp,
1189 (unsigned long long)rxs->mactime,
1190 (unsigned long long)(rxs->mactime - bc_tstamp),
1191 (unsigned long long)tsf);
1192
1193 /*
1194 * Sometimes the HW will give us a wrong tstamp in the rx
1195 * status, causing the timestamp extension to go wrong.
1196 * (This seems to happen especially with beacon frames bigger
1197 * than 78 byte (incl. FCS))
1198 * But we know that the receive timestamp must be later than the
1199 * timestamp of the beacon since HW must have synced to that.
1200 *
1201 * NOTE: here we assume mactime to be after the frame was
1202 * received, not like mac80211 which defines it at the start.
1203 */
1204 if (bc_tstamp > rxs->mactime) {
1205 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
1206 "fixing mactime from %llx to %llx\n",
1207 (unsigned long long)rxs->mactime,
1208 (unsigned long long)tsf);
1209 rxs->mactime = tsf;
1210 }
1211
1212 /*
1213 * Local TSF might have moved higher than our beacon timers,
1214 * in that case we have to update them to continue sending
1215 * beacons. This also takes care of synchronizing beacon sending
1216 * times with other stations.
1217 */
1218 if (hw_tu >= ah->nexttbtt)
1219 ath5k_beacon_update_timers(ah, bc_tstamp);
1220
1221 /* Check if the beacon timers are still correct, because a TSF
1222 * update might have created a window between them - for a
1223 * longer description see the comment of this function: */
1224 if (!ath5k_hw_check_beacon_timers(ah, ah->bintval)) {
1225 ath5k_beacon_update_timers(ah, bc_tstamp);
1226 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
1227 "fixed beacon timers after beacon receive\n");
1228 }
1229 }
1230 }
1231
1232 static void
1233 ath5k_update_beacon_rssi(struct ath5k_hw *ah, struct sk_buff *skb, int rssi)
1234 {
1235 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1236 struct ath_common *common = ath5k_hw_common(ah);
1237
1238 /* only beacons from our BSSID */
1239 if (!ieee80211_is_beacon(mgmt->frame_control) ||
1240 !ether_addr_equal(mgmt->bssid, common->curbssid))
1241 return;
1242
1243 ewma_add(&ah->ah_beacon_rssi_avg, rssi);
1244
1245 /* in IBSS mode we should keep RSSI statistics per neighbour */
1246 /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */
1247 }
1248
1249 /*
1250 * Compute padding position. skb must contain an IEEE 802.11 frame
1251 */
1252 static int ath5k_common_padpos(struct sk_buff *skb)
1253 {
1254 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1255 __le16 frame_control = hdr->frame_control;
1256 int padpos = 24;
1257
1258 if (ieee80211_has_a4(frame_control))
1259 padpos += ETH_ALEN;
1260
1261 if (ieee80211_is_data_qos(frame_control))
1262 padpos += IEEE80211_QOS_CTL_LEN;
1263
1264 return padpos;
1265 }
1266
1267 /*
1268 * This function expects an 802.11 frame and returns the number of
1269 * bytes added, or -1 if we don't have enough header room.
1270 */
1271 static int ath5k_add_padding(struct sk_buff *skb)
1272 {
1273 int padpos = ath5k_common_padpos(skb);
1274 int padsize = padpos & 3;
1275
1276 if (padsize && skb->len > padpos) {
1277
1278 if (skb_headroom(skb) < padsize)
1279 return -1;
1280
1281 skb_push(skb, padsize);
1282 memmove(skb->data, skb->data + padsize, padpos);
1283 return padsize;
1284 }
1285
1286 return 0;
1287 }
1288
1289 /*
1290 * The MAC header is padded to have 32-bit boundary if the
1291 * packet payload is non-zero. The general calculation for
1292 * padsize would take into account odd header lengths:
1293 * padsize = 4 - (hdrlen & 3); however, since only
1294 * even-length headers are used, padding can only be 0 or 2
1295 * bytes and we can optimize this a bit. We must not try to
1296 * remove padding from short control frames that do not have a
1297 * payload.
1298 *
1299 * This function expects an 802.11 frame and returns the number of
1300 * bytes removed.
1301 */
1302 static int ath5k_remove_padding(struct sk_buff *skb)
1303 {
1304 int padpos = ath5k_common_padpos(skb);
1305 int padsize = padpos & 3;
1306
1307 if (padsize && skb->len >= padpos + padsize) {
1308 memmove(skb->data + padsize, skb->data, padpos);
1309 skb_pull(skb, padsize);
1310 return padsize;
1311 }
1312
1313 return 0;
1314 }
1315
1316 static void
1317 ath5k_receive_frame(struct ath5k_hw *ah, struct sk_buff *skb,
1318 struct ath5k_rx_status *rs)
1319 {
1320 struct ieee80211_rx_status *rxs;
1321
1322 ath5k_remove_padding(skb);
1323
1324 rxs = IEEE80211_SKB_RXCB(skb);
1325
1326 rxs->flag = 0;
1327 if (unlikely(rs->rs_status & AR5K_RXERR_MIC))
1328 rxs->flag |= RX_FLAG_MMIC_ERROR;
1329
1330 /*
1331 * always extend the mac timestamp, since this information is
1332 * also needed for proper IBSS merging.
1333 *
1334 * XXX: it might be too late to do it here, since rs_tstamp is
1335 * 15bit only. that means TSF extension has to be done within
1336 * 32768usec (about 32ms). it might be necessary to move this to
1337 * the interrupt handler, like it is done in madwifi.
1338 *
1339 * Unfortunately we don't know when the hardware takes the rx
1340 * timestamp (beginning of phy frame, data frame, end of rx?).
1341 * The only thing we know is that it is hardware specific...
1342 * On AR5213 it seems the rx timestamp is at the end of the
1343 * frame, but I'm not sure.
1344 *
1345 * NOTE: mac80211 defines mactime at the beginning of the first
1346 * data symbol. Since we don't have any time references it's
1347 * impossible to comply to that. This affects IBSS merge only
1348 * right now, so it's not too bad...
1349 */
1350 rxs->mactime = ath5k_extend_tsf(ah, rs->rs_tstamp);
1351 rxs->flag |= RX_FLAG_MACTIME_MPDU;
1352
1353 rxs->freq = ah->curchan->center_freq;
1354 rxs->band = ah->curchan->band;
1355
1356 rxs->signal = ah->ah_noise_floor + rs->rs_rssi;
1357
1358 rxs->antenna = rs->rs_antenna;
1359
1360 if (rs->rs_antenna > 0 && rs->rs_antenna < 5)
1361 ah->stats.antenna_rx[rs->rs_antenna]++;
1362 else
1363 ah->stats.antenna_rx[0]++; /* invalid */
1364
1365 rxs->rate_idx = ath5k_hw_to_driver_rix(ah, rs->rs_rate);
1366 rxs->flag |= ath5k_rx_decrypted(ah, skb, rs);
1367
1368 if (rxs->rate_idx >= 0 && rs->rs_rate ==
1369 ah->sbands[ah->curchan->band].bitrates[rxs->rate_idx].hw_value_short)
1370 rxs->flag |= RX_FLAG_SHORTPRE;
1371
1372 trace_ath5k_rx(ah, skb);
1373
1374 ath5k_update_beacon_rssi(ah, skb, rs->rs_rssi);
1375
1376 /* check beacons in IBSS mode */
1377 if (ah->opmode == NL80211_IFTYPE_ADHOC)
1378 ath5k_check_ibss_tsf(ah, skb, rxs);
1379
1380 ieee80211_rx(ah->hw, skb);
1381 }
1382
1383 /** ath5k_frame_receive_ok() - Do we want to receive this frame or not?
1384 *
1385 * Check if we want to further process this frame or not. Also update
1386 * statistics. Return true if we want this frame, false if not.
1387 */
1388 static bool
1389 ath5k_receive_frame_ok(struct ath5k_hw *ah, struct ath5k_rx_status *rs)
1390 {
1391 ah->stats.rx_all_count++;
1392 ah->stats.rx_bytes_count += rs->rs_datalen;
1393
1394 if (unlikely(rs->rs_status)) {
1395 if (rs->rs_status & AR5K_RXERR_CRC)
1396 ah->stats.rxerr_crc++;
1397 if (rs->rs_status & AR5K_RXERR_FIFO)
1398 ah->stats.rxerr_fifo++;
1399 if (rs->rs_status & AR5K_RXERR_PHY) {
1400 ah->stats.rxerr_phy++;
1401 if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32)
1402 ah->stats.rxerr_phy_code[rs->rs_phyerr]++;
1403 return false;
1404 }
1405 if (rs->rs_status & AR5K_RXERR_DECRYPT) {
1406 /*
1407 * Decrypt error. If the error occurred
1408 * because there was no hardware key, then
1409 * let the frame through so the upper layers
1410 * can process it. This is necessary for 5210
1411 * parts which have no way to setup a ``clear''
1412 * key cache entry.
1413 *
1414 * XXX do key cache faulting
1415 */
1416 ah->stats.rxerr_decrypt++;
1417 if (rs->rs_keyix == AR5K_RXKEYIX_INVALID &&
1418 !(rs->rs_status & AR5K_RXERR_CRC))
1419 return true;
1420 }
1421 if (rs->rs_status & AR5K_RXERR_MIC) {
1422 ah->stats.rxerr_mic++;
1423 return true;
1424 }
1425
1426 /* reject any frames with non-crypto errors */
1427 if (rs->rs_status & ~(AR5K_RXERR_DECRYPT))
1428 return false;
1429 }
1430
1431 if (unlikely(rs->rs_more)) {
1432 ah->stats.rxerr_jumbo++;
1433 return false;
1434 }
1435 return true;
1436 }
1437
1438 static void
1439 ath5k_set_current_imask(struct ath5k_hw *ah)
1440 {
1441 enum ath5k_int imask;
1442 unsigned long flags;
1443
1444 spin_lock_irqsave(&ah->irqlock, flags);
1445 imask = ah->imask;
1446 if (ah->rx_pending)
1447 imask &= ~AR5K_INT_RX_ALL;
1448 if (ah->tx_pending)
1449 imask &= ~AR5K_INT_TX_ALL;
1450 ath5k_hw_set_imr(ah, imask);
1451 spin_unlock_irqrestore(&ah->irqlock, flags);
1452 }
1453
1454 static void
1455 ath5k_tasklet_rx(unsigned long data)
1456 {
1457 struct ath5k_rx_status rs = {};
1458 struct sk_buff *skb, *next_skb;
1459 dma_addr_t next_skb_addr;
1460 struct ath5k_hw *ah = (void *)data;
1461 struct ath_common *common = ath5k_hw_common(ah);
1462 struct ath5k_buf *bf;
1463 struct ath5k_desc *ds;
1464 int ret;
1465
1466 spin_lock(&ah->rxbuflock);
1467 if (list_empty(&ah->rxbuf)) {
1468 ATH5K_WARN(ah, "empty rx buf pool\n");
1469 goto unlock;
1470 }
1471 do {
1472 bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list);
1473 BUG_ON(bf->skb == NULL);
1474 skb = bf->skb;
1475 ds = bf->desc;
1476
1477 /* bail if HW is still using self-linked descriptor */
1478 if (ath5k_hw_get_rxdp(ah) == bf->daddr)
1479 break;
1480
1481 ret = ah->ah_proc_rx_desc(ah, ds, &rs);
1482 if (unlikely(ret == -EINPROGRESS))
1483 break;
1484 else if (unlikely(ret)) {
1485 ATH5K_ERR(ah, "error in processing rx descriptor\n");
1486 ah->stats.rxerr_proc++;
1487 break;
1488 }
1489
1490 if (ath5k_receive_frame_ok(ah, &rs)) {
1491 next_skb = ath5k_rx_skb_alloc(ah, &next_skb_addr);
1492
1493 /*
1494 * If we can't replace bf->skb with a new skb under
1495 * memory pressure, just skip this packet
1496 */
1497 if (!next_skb)
1498 goto next;
1499
1500 dma_unmap_single(ah->dev, bf->skbaddr,
1501 common->rx_bufsize,
1502 DMA_FROM_DEVICE);
1503
1504 skb_put(skb, rs.rs_datalen);
1505
1506 ath5k_receive_frame(ah, skb, &rs);
1507
1508 bf->skb = next_skb;
1509 bf->skbaddr = next_skb_addr;
1510 }
1511 next:
1512 list_move_tail(&bf->list, &ah->rxbuf);
1513 } while (ath5k_rxbuf_setup(ah, bf) == 0);
1514 unlock:
1515 spin_unlock(&ah->rxbuflock);
1516 ah->rx_pending = false;
1517 ath5k_set_current_imask(ah);
1518 }
1519
1520
1521 /*************\
1522 * TX Handling *
1523 \*************/
1524
1525 void
1526 ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
1527 struct ath5k_txq *txq)
1528 {
1529 struct ath5k_hw *ah = hw->priv;
1530 struct ath5k_buf *bf;
1531 unsigned long flags;
1532 int padsize;
1533
1534 trace_ath5k_tx(ah, skb, txq);
1535
1536 /*
1537 * The hardware expects the header padded to 4 byte boundaries.
1538 * If this is not the case, we add the padding after the header.
1539 */
1540 padsize = ath5k_add_padding(skb);
1541 if (padsize < 0) {
1542 ATH5K_ERR(ah, "tx hdrlen not %%4: not enough"
1543 " headroom to pad");
1544 goto drop_packet;
1545 }
1546
1547 if (txq->txq_len >= txq->txq_max &&
1548 txq->qnum <= AR5K_TX_QUEUE_ID_DATA_MAX)
1549 ieee80211_stop_queue(hw, txq->qnum);
1550
1551 spin_lock_irqsave(&ah->txbuflock, flags);
1552 if (list_empty(&ah->txbuf)) {
1553 ATH5K_ERR(ah, "no further txbuf available, dropping packet\n");
1554 spin_unlock_irqrestore(&ah->txbuflock, flags);
1555 ieee80211_stop_queues(hw);
1556 goto drop_packet;
1557 }
1558 bf = list_first_entry(&ah->txbuf, struct ath5k_buf, list);
1559 list_del(&bf->list);
1560 ah->txbuf_len--;
1561 if (list_empty(&ah->txbuf))
1562 ieee80211_stop_queues(hw);
1563 spin_unlock_irqrestore(&ah->txbuflock, flags);
1564
1565 bf->skb = skb;
1566
1567 if (ath5k_txbuf_setup(ah, bf, txq, padsize)) {
1568 bf->skb = NULL;
1569 spin_lock_irqsave(&ah->txbuflock, flags);
1570 list_add_tail(&bf->list, &ah->txbuf);
1571 ah->txbuf_len++;
1572 spin_unlock_irqrestore(&ah->txbuflock, flags);
1573 goto drop_packet;
1574 }
1575 return;
1576
1577 drop_packet:
1578 dev_kfree_skb_any(skb);
1579 }
1580
1581 static void
1582 ath5k_tx_frame_completed(struct ath5k_hw *ah, struct sk_buff *skb,
1583 struct ath5k_txq *txq, struct ath5k_tx_status *ts)
1584 {
1585 struct ieee80211_tx_info *info;
1586 u8 tries[3];
1587 int i;
1588
1589 ah->stats.tx_all_count++;
1590 ah->stats.tx_bytes_count += skb->len;
1591 info = IEEE80211_SKB_CB(skb);
1592
1593 tries[0] = info->status.rates[0].count;
1594 tries[1] = info->status.rates[1].count;
1595 tries[2] = info->status.rates[2].count;
1596
1597 ieee80211_tx_info_clear_status(info);
1598
1599 for (i = 0; i < ts->ts_final_idx; i++) {
1600 struct ieee80211_tx_rate *r =
1601 &info->status.rates[i];
1602
1603 r->count = tries[i];
1604 }
1605
1606 info->status.rates[ts->ts_final_idx].count = ts->ts_final_retry;
1607 info->status.rates[ts->ts_final_idx + 1].idx = -1;
1608
1609 if (unlikely(ts->ts_status)) {
1610 ah->stats.ack_fail++;
1611 if (ts->ts_status & AR5K_TXERR_FILT) {
1612 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1613 ah->stats.txerr_filt++;
1614 }
1615 if (ts->ts_status & AR5K_TXERR_XRETRY)
1616 ah->stats.txerr_retry++;
1617 if (ts->ts_status & AR5K_TXERR_FIFO)
1618 ah->stats.txerr_fifo++;
1619 } else {
1620 info->flags |= IEEE80211_TX_STAT_ACK;
1621 info->status.ack_signal = ts->ts_rssi;
1622
1623 /* count the successful attempt as well */
1624 info->status.rates[ts->ts_final_idx].count++;
1625 }
1626
1627 /*
1628 * Remove MAC header padding before giving the frame
1629 * back to mac80211.
1630 */
1631 ath5k_remove_padding(skb);
1632
1633 if (ts->ts_antenna > 0 && ts->ts_antenna < 5)
1634 ah->stats.antenna_tx[ts->ts_antenna]++;
1635 else
1636 ah->stats.antenna_tx[0]++; /* invalid */
1637
1638 trace_ath5k_tx_complete(ah, skb, txq, ts);
1639 ieee80211_tx_status(ah->hw, skb);
1640 }
1641
1642 static void
1643 ath5k_tx_processq(struct ath5k_hw *ah, struct ath5k_txq *txq)
1644 {
1645 struct ath5k_tx_status ts = {};
1646 struct ath5k_buf *bf, *bf0;
1647 struct ath5k_desc *ds;
1648 struct sk_buff *skb;
1649 int ret;
1650
1651 spin_lock(&txq->lock);
1652 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1653
1654 txq->txq_poll_mark = false;
1655
1656 /* skb might already have been processed last time. */
1657 if (bf->skb != NULL) {
1658 ds = bf->desc;
1659
1660 ret = ah->ah_proc_tx_desc(ah, ds, &ts);
1661 if (unlikely(ret == -EINPROGRESS))
1662 break;
1663 else if (unlikely(ret)) {
1664 ATH5K_ERR(ah,
1665 "error %d while processing "
1666 "queue %u\n", ret, txq->qnum);
1667 break;
1668 }
1669
1670 skb = bf->skb;
1671 bf->skb = NULL;
1672
1673 dma_unmap_single(ah->dev, bf->skbaddr, skb->len,
1674 DMA_TO_DEVICE);
1675 ath5k_tx_frame_completed(ah, skb, txq, &ts);
1676 }
1677
1678 /*
1679 * It's possible that the hardware can say the buffer is
1680 * completed when it hasn't yet loaded the ds_link from
1681 * host memory and moved on.
1682 * Always keep the last descriptor to avoid HW races...
1683 */
1684 if (ath5k_hw_get_txdp(ah, txq->qnum) != bf->daddr) {
1685 spin_lock(&ah->txbuflock);
1686 list_move_tail(&bf->list, &ah->txbuf);
1687 ah->txbuf_len++;
1688 txq->txq_len--;
1689 spin_unlock(&ah->txbuflock);
1690 }
1691 }
1692 spin_unlock(&txq->lock);
1693 if (txq->txq_len < ATH5K_TXQ_LEN_LOW && txq->qnum < 4)
1694 ieee80211_wake_queue(ah->hw, txq->qnum);
1695 }
1696
1697 static void
1698 ath5k_tasklet_tx(unsigned long data)
1699 {
1700 int i;
1701 struct ath5k_hw *ah = (void *)data;
1702
1703 for (i = 0; i < AR5K_NUM_TX_QUEUES; i++)
1704 if (ah->txqs[i].setup && (ah->ah_txq_isr_txok_all & BIT(i)))
1705 ath5k_tx_processq(ah, &ah->txqs[i]);
1706
1707 ah->tx_pending = false;
1708 ath5k_set_current_imask(ah);
1709 }
1710
1711
1712 /*****************\
1713 * Beacon handling *
1714 \*****************/
1715
1716 /*
1717 * Setup the beacon frame for transmit.
1718 */
1719 static int
1720 ath5k_beacon_setup(struct ath5k_hw *ah, struct ath5k_buf *bf)
1721 {
1722 struct sk_buff *skb = bf->skb;
1723 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1724 struct ath5k_desc *ds;
1725 int ret = 0;
1726 u8 antenna;
1727 u32 flags;
1728 const int padsize = 0;
1729
1730 bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len,
1731 DMA_TO_DEVICE);
1732 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1733 "skbaddr %llx\n", skb, skb->data, skb->len,
1734 (unsigned long long)bf->skbaddr);
1735
1736 if (dma_mapping_error(ah->dev, bf->skbaddr)) {
1737 ATH5K_ERR(ah, "beacon DMA mapping failed\n");
1738 dev_kfree_skb_any(skb);
1739 bf->skb = NULL;
1740 return -EIO;
1741 }
1742
1743 ds = bf->desc;
1744 antenna = ah->ah_tx_ant;
1745
1746 flags = AR5K_TXDESC_NOACK;
1747 if (ah->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
1748 ds->ds_link = bf->daddr; /* self-linked */
1749 flags |= AR5K_TXDESC_VEOL;
1750 } else
1751 ds->ds_link = 0;
1752
1753 /*
1754 * If we use multiple antennas on AP and use
1755 * the Sectored AP scenario, switch antenna every
1756 * 4 beacons to make sure everybody hears our AP.
1757 * When a client tries to associate, hw will keep
1758 * track of the tx antenna to be used for this client
1759 * automatically, based on ACKed packets.
1760 *
1761 * Note: AP still listens and transmits RTS on the
1762 * default antenna which is supposed to be an omni.
1763 *
1764 * Note2: On sectored scenarios it's possible to have
1765 * multiple antennas (1 omni -- the default -- and 14
1766 * sectors), so if we choose to actually support this
1767 * mode, we need to allow the user to set how many antennas
1768 * we have and tweak the code below to send beacons
1769 * on all of them.
1770 */
1771 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
1772 antenna = ah->bsent & 4 ? 2 : 1;
1773
1774
1775 /* FIXME: If we are in g mode and rate is a CCK rate
1776 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1777 * from tx power (value is in dB units already) */
1778 ds->ds_data = bf->skbaddr;
1779 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
1780 ieee80211_get_hdrlen_from_skb(skb), padsize,
1781 AR5K_PKT_TYPE_BEACON,
1782 (ah->ah_txpower.txp_requested * 2),
1783 ieee80211_get_tx_rate(ah->hw, info)->hw_value,
1784 1, AR5K_TXKEYIX_INVALID,
1785 antenna, flags, 0, 0);
1786 if (ret)
1787 goto err_unmap;
1788
1789 return 0;
1790 err_unmap:
1791 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
1792 return ret;
1793 }
1794
1795 /*
1796 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
1797 * this is called only once at config_bss time, for AP we do it every
1798 * SWBA interrupt so that the TIM will reflect buffered frames.
1799 *
1800 * Called with the beacon lock.
1801 */
1802 int
1803 ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1804 {
1805 int ret;
1806 struct ath5k_hw *ah = hw->priv;
1807 struct ath5k_vif *avf = (void *)vif->drv_priv;
1808 struct sk_buff *skb;
1809
1810 if (WARN_ON(!vif)) {
1811 ret = -EINVAL;
1812 goto out;
1813 }
1814
1815 skb = ieee80211_beacon_get(hw, vif);
1816
1817 if (!skb) {
1818 ret = -ENOMEM;
1819 goto out;
1820 }
1821
1822 ath5k_txbuf_free_skb(ah, avf->bbuf);
1823 avf->bbuf->skb = skb;
1824 ret = ath5k_beacon_setup(ah, avf->bbuf);
1825 out:
1826 return ret;
1827 }
1828
1829 /*
1830 * Transmit a beacon frame at SWBA. Dynamic updates to the
1831 * frame contents are done as needed and the slot time is
1832 * also adjusted based on current state.
1833 *
1834 * This is called from software irq context (beacontq tasklets)
1835 * or user context from ath5k_beacon_config.
1836 */
1837 static void
1838 ath5k_beacon_send(struct ath5k_hw *ah)
1839 {
1840 struct ieee80211_vif *vif;
1841 struct ath5k_vif *avf;
1842 struct ath5k_buf *bf;
1843 struct sk_buff *skb;
1844 int err;
1845
1846 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "in beacon_send\n");
1847
1848 /*
1849 * Check if the previous beacon has gone out. If
1850 * not, don't don't try to post another: skip this
1851 * period and wait for the next. Missed beacons
1852 * indicate a problem and should not occur. If we
1853 * miss too many consecutive beacons reset the device.
1854 */
1855 if (unlikely(ath5k_hw_num_tx_pending(ah, ah->bhalq) != 0)) {
1856 ah->bmisscount++;
1857 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1858 "missed %u consecutive beacons\n", ah->bmisscount);
1859 if (ah->bmisscount > 10) { /* NB: 10 is a guess */
1860 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1861 "stuck beacon time (%u missed)\n",
1862 ah->bmisscount);
1863 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
1864 "stuck beacon, resetting\n");
1865 ieee80211_queue_work(ah->hw, &ah->reset_work);
1866 }
1867 return;
1868 }
1869 if (unlikely(ah->bmisscount != 0)) {
1870 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1871 "resume beacon xmit after %u misses\n",
1872 ah->bmisscount);
1873 ah->bmisscount = 0;
1874 }
1875
1876 if ((ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs +
1877 ah->num_mesh_vifs > 1) ||
1878 ah->opmode == NL80211_IFTYPE_MESH_POINT) {
1879 u64 tsf = ath5k_hw_get_tsf64(ah);
1880 u32 tsftu = TSF_TO_TU(tsf);
1881 int slot = ((tsftu % ah->bintval) * ATH_BCBUF) / ah->bintval;
1882 vif = ah->bslot[(slot + 1) % ATH_BCBUF];
1883 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1884 "tsf %llx tsftu %x intval %u slot %u vif %p\n",
1885 (unsigned long long)tsf, tsftu, ah->bintval, slot, vif);
1886 } else /* only one interface */
1887 vif = ah->bslot[0];
1888
1889 if (!vif)
1890 return;
1891
1892 avf = (void *)vif->drv_priv;
1893 bf = avf->bbuf;
1894
1895 /*
1896 * Stop any current dma and put the new frame on the queue.
1897 * This should never fail since we check above that no frames
1898 * are still pending on the queue.
1899 */
1900 if (unlikely(ath5k_hw_stop_beacon_queue(ah, ah->bhalq))) {
1901 ATH5K_WARN(ah, "beacon queue %u didn't start/stop ?\n", ah->bhalq);
1902 /* NB: hw still stops DMA, so proceed */
1903 }
1904
1905 /* refresh the beacon for AP or MESH mode */
1906 if (ah->opmode == NL80211_IFTYPE_AP ||
1907 ah->opmode == NL80211_IFTYPE_MESH_POINT) {
1908 err = ath5k_beacon_update(ah->hw, vif);
1909 if (err)
1910 return;
1911 }
1912
1913 if (unlikely(bf->skb == NULL || ah->opmode == NL80211_IFTYPE_STATION ||
1914 ah->opmode == NL80211_IFTYPE_MONITOR)) {
1915 ATH5K_WARN(ah, "bf=%p bf_skb=%p\n", bf, bf->skb);
1916 return;
1917 }
1918
1919 trace_ath5k_tx(ah, bf->skb, &ah->txqs[ah->bhalq]);
1920
1921 ath5k_hw_set_txdp(ah, ah->bhalq, bf->daddr);
1922 ath5k_hw_start_tx_dma(ah, ah->bhalq);
1923 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
1924 ah->bhalq, (unsigned long long)bf->daddr, bf->desc);
1925
1926 skb = ieee80211_get_buffered_bc(ah->hw, vif);
1927 while (skb) {
1928 ath5k_tx_queue(ah->hw, skb, ah->cabq);
1929
1930 if (ah->cabq->txq_len >= ah->cabq->txq_max)
1931 break;
1932
1933 skb = ieee80211_get_buffered_bc(ah->hw, vif);
1934 }
1935
1936 ah->bsent++;
1937 }
1938
1939 /**
1940 * ath5k_beacon_update_timers - update beacon timers
1941 *
1942 * @ah: struct ath5k_hw pointer we are operating on
1943 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
1944 * beacon timer update based on the current HW TSF.
1945 *
1946 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
1947 * of a received beacon or the current local hardware TSF and write it to the
1948 * beacon timer registers.
1949 *
1950 * This is called in a variety of situations, e.g. when a beacon is received,
1951 * when a TSF update has been detected, but also when an new IBSS is created or
1952 * when we otherwise know we have to update the timers, but we keep it in this
1953 * function to have it all together in one place.
1954 */
1955 void
1956 ath5k_beacon_update_timers(struct ath5k_hw *ah, u64 bc_tsf)
1957 {
1958 u32 nexttbtt, intval, hw_tu, bc_tu;
1959 u64 hw_tsf;
1960
1961 intval = ah->bintval & AR5K_BEACON_PERIOD;
1962 if (ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs
1963 + ah->num_mesh_vifs > 1) {
1964 intval /= ATH_BCBUF; /* staggered multi-bss beacons */
1965 if (intval < 15)
1966 ATH5K_WARN(ah, "intval %u is too low, min 15\n",
1967 intval);
1968 }
1969 if (WARN_ON(!intval))
1970 return;
1971
1972 /* beacon TSF converted to TU */
1973 bc_tu = TSF_TO_TU(bc_tsf);
1974
1975 /* current TSF converted to TU */
1976 hw_tsf = ath5k_hw_get_tsf64(ah);
1977 hw_tu = TSF_TO_TU(hw_tsf);
1978
1979 #define FUDGE (AR5K_TUNE_SW_BEACON_RESP + 3)
1980 /* We use FUDGE to make sure the next TBTT is ahead of the current TU.
1981 * Since we later subtract AR5K_TUNE_SW_BEACON_RESP (10) in the timer
1982 * configuration we need to make sure it is bigger than that. */
1983
1984 if (bc_tsf == -1) {
1985 /*
1986 * no beacons received, called internally.
1987 * just need to refresh timers based on HW TSF.
1988 */
1989 nexttbtt = roundup(hw_tu + FUDGE, intval);
1990 } else if (bc_tsf == 0) {
1991 /*
1992 * no beacon received, probably called by ath5k_reset_tsf().
1993 * reset TSF to start with 0.
1994 */
1995 nexttbtt = intval;
1996 intval |= AR5K_BEACON_RESET_TSF;
1997 } else if (bc_tsf > hw_tsf) {
1998 /*
1999 * beacon received, SW merge happened but HW TSF not yet updated.
2000 * not possible to reconfigure timers yet, but next time we
2001 * receive a beacon with the same BSSID, the hardware will
2002 * automatically update the TSF and then we need to reconfigure
2003 * the timers.
2004 */
2005 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
2006 "need to wait for HW TSF sync\n");
2007 return;
2008 } else {
2009 /*
2010 * most important case for beacon synchronization between STA.
2011 *
2012 * beacon received and HW TSF has been already updated by HW.
2013 * update next TBTT based on the TSF of the beacon, but make
2014 * sure it is ahead of our local TSF timer.
2015 */
2016 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2017 }
2018 #undef FUDGE
2019
2020 ah->nexttbtt = nexttbtt;
2021
2022 intval |= AR5K_BEACON_ENA;
2023 ath5k_hw_init_beacon_timers(ah, nexttbtt, intval);
2024
2025 /*
2026 * debugging output last in order to preserve the time critical aspect
2027 * of this function
2028 */
2029 if (bc_tsf == -1)
2030 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
2031 "reconfigured timers based on HW TSF\n");
2032 else if (bc_tsf == 0)
2033 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
2034 "reset HW TSF and timers\n");
2035 else
2036 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
2037 "updated timers based on beacon TSF\n");
2038
2039 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
2040 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2041 (unsigned long long) bc_tsf,
2042 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2043 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2044 intval & AR5K_BEACON_PERIOD,
2045 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2046 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2047 }
2048
2049 /**
2050 * ath5k_beacon_config - Configure the beacon queues and interrupts
2051 *
2052 * @ah: struct ath5k_hw pointer we are operating on
2053 *
2054 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2055 * interrupts to detect TSF updates only.
2056 */
2057 void
2058 ath5k_beacon_config(struct ath5k_hw *ah)
2059 {
2060 spin_lock_bh(&ah->block);
2061 ah->bmisscount = 0;
2062 ah->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2063
2064 if (ah->enable_beacon) {
2065 /*
2066 * In IBSS mode we use a self-linked tx descriptor and let the
2067 * hardware send the beacons automatically. We have to load it
2068 * only once here.
2069 * We use the SWBA interrupt only to keep track of the beacon
2070 * timers in order to detect automatic TSF updates.
2071 */
2072 ath5k_beaconq_config(ah);
2073
2074 ah->imask |= AR5K_INT_SWBA;
2075
2076 if (ah->opmode == NL80211_IFTYPE_ADHOC) {
2077 if (ath5k_hw_hasveol(ah))
2078 ath5k_beacon_send(ah);
2079 } else
2080 ath5k_beacon_update_timers(ah, -1);
2081 } else {
2082 ath5k_hw_stop_beacon_queue(ah, ah->bhalq);
2083 }
2084
2085 ath5k_hw_set_imr(ah, ah->imask);
2086 mmiowb();
2087 spin_unlock_bh(&ah->block);
2088 }
2089
2090 static void ath5k_tasklet_beacon(unsigned long data)
2091 {
2092 struct ath5k_hw *ah = (struct ath5k_hw *) data;
2093
2094 /*
2095 * Software beacon alert--time to send a beacon.
2096 *
2097 * In IBSS mode we use this interrupt just to
2098 * keep track of the next TBTT (target beacon
2099 * transmission time) in order to detect whether
2100 * automatic TSF updates happened.
2101 */
2102 if (ah->opmode == NL80211_IFTYPE_ADHOC) {
2103 /* XXX: only if VEOL supported */
2104 u64 tsf = ath5k_hw_get_tsf64(ah);
2105 ah->nexttbtt += ah->bintval;
2106 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
2107 "SWBA nexttbtt: %x hw_tu: %x "
2108 "TSF: %llx\n",
2109 ah->nexttbtt,
2110 TSF_TO_TU(tsf),
2111 (unsigned long long) tsf);
2112 } else {
2113 spin_lock(&ah->block);
2114 ath5k_beacon_send(ah);
2115 spin_unlock(&ah->block);
2116 }
2117 }
2118
2119
2120 /********************\
2121 * Interrupt handling *
2122 \********************/
2123
2124 static void
2125 ath5k_intr_calibration_poll(struct ath5k_hw *ah)
2126 {
2127 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) &&
2128 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL) &&
2129 !(ah->ah_cal_mask & AR5K_CALIBRATION_SHORT)) {
2130
2131 /* Run ANI only when calibration is not active */
2132
2133 ah->ah_cal_next_ani = jiffies +
2134 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
2135 tasklet_schedule(&ah->ani_tasklet);
2136
2137 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_short) &&
2138 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL) &&
2139 !(ah->ah_cal_mask & AR5K_CALIBRATION_SHORT)) {
2140
2141 /* Run calibration only when another calibration
2142 * is not running.
2143 *
2144 * Note: This is for both full/short calibration,
2145 * if it's time for a full one, ath5k_calibrate_work will deal
2146 * with it. */
2147
2148 ah->ah_cal_next_short = jiffies +
2149 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_SHORT);
2150 ieee80211_queue_work(ah->hw, &ah->calib_work);
2151 }
2152 /* we could use SWI to generate enough interrupts to meet our
2153 * calibration interval requirements, if necessary:
2154 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */
2155 }
2156
2157 static void
2158 ath5k_schedule_rx(struct ath5k_hw *ah)
2159 {
2160 ah->rx_pending = true;
2161 tasklet_schedule(&ah->rxtq);
2162 }
2163
2164 static void
2165 ath5k_schedule_tx(struct ath5k_hw *ah)
2166 {
2167 ah->tx_pending = true;
2168 tasklet_schedule(&ah->txtq);
2169 }
2170
2171 static irqreturn_t
2172 ath5k_intr(int irq, void *dev_id)
2173 {
2174 struct ath5k_hw *ah = dev_id;
2175 enum ath5k_int status;
2176 unsigned int counter = 1000;
2177
2178
2179 /*
2180 * If hw is not ready (or detached) and we get an
2181 * interrupt, or if we have no interrupts pending
2182 * (that means it's not for us) skip it.
2183 *
2184 * NOTE: Group 0/1 PCI interface registers are not
2185 * supported on WiSOCs, so we can't check for pending
2186 * interrupts (ISR belongs to another register group
2187 * so we are ok).
2188 */
2189 if (unlikely(test_bit(ATH_STAT_INVALID, ah->status) ||
2190 ((ath5k_get_bus_type(ah) != ATH_AHB) &&
2191 !ath5k_hw_is_intr_pending(ah))))
2192 return IRQ_NONE;
2193
2194 /** Main loop **/
2195 do {
2196 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2197
2198 ATH5K_DBG(ah, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2199 status, ah->imask);
2200
2201 /*
2202 * Fatal hw error -> Log and reset
2203 *
2204 * Fatal errors are unrecoverable so we have to
2205 * reset the card. These errors include bus and
2206 * dma errors.
2207 */
2208 if (unlikely(status & AR5K_INT_FATAL)) {
2209
2210 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2211 "fatal int, resetting\n");
2212 ieee80211_queue_work(ah->hw, &ah->reset_work);
2213
2214 /*
2215 * RX Overrun -> Count and reset if needed
2216 *
2217 * Receive buffers are full. Either the bus is busy or
2218 * the CPU is not fast enough to process all received
2219 * frames.
2220 */
2221 } else if (unlikely(status & AR5K_INT_RXORN)) {
2222
2223 /*
2224 * Older chipsets need a reset to come out of this
2225 * condition, but we treat it as RX for newer chips.
2226 * We don't know exactly which versions need a reset
2227 * this guess is copied from the HAL.
2228 */
2229 ah->stats.rxorn_intr++;
2230
2231 if (ah->ah_mac_srev < AR5K_SREV_AR5212) {
2232 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2233 "rx overrun, resetting\n");
2234 ieee80211_queue_work(ah->hw, &ah->reset_work);
2235 } else
2236 ath5k_schedule_rx(ah);
2237
2238 } else {
2239
2240 /* Software Beacon Alert -> Schedule beacon tasklet */
2241 if (status & AR5K_INT_SWBA)
2242 tasklet_hi_schedule(&ah->beacontq);
2243
2244 /*
2245 * No more RX descriptors -> Just count
2246 *
2247 * NB: the hardware should re-read the link when
2248 * RXE bit is written, but it doesn't work at
2249 * least on older hardware revs.
2250 */
2251 if (status & AR5K_INT_RXEOL)
2252 ah->stats.rxeol_intr++;
2253
2254
2255 /* TX Underrun -> Bump tx trigger level */
2256 if (status & AR5K_INT_TXURN)
2257 ath5k_hw_update_tx_triglevel(ah, true);
2258
2259 /* RX -> Schedule rx tasklet */
2260 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
2261 ath5k_schedule_rx(ah);
2262
2263 /* TX -> Schedule tx tasklet */
2264 if (status & (AR5K_INT_TXOK
2265 | AR5K_INT_TXDESC
2266 | AR5K_INT_TXERR
2267 | AR5K_INT_TXEOL))
2268 ath5k_schedule_tx(ah);
2269
2270 /* Missed beacon -> TODO
2271 if (status & AR5K_INT_BMISS)
2272 */
2273
2274 /* MIB event -> Update counters and notify ANI */
2275 if (status & AR5K_INT_MIB) {
2276 ah->stats.mib_intr++;
2277 ath5k_hw_update_mib_counters(ah);
2278 ath5k_ani_mib_intr(ah);
2279 }
2280
2281 /* GPIO -> Notify RFKill layer */
2282 if (status & AR5K_INT_GPIO)
2283 tasklet_schedule(&ah->rf_kill.toggleq);
2284
2285 }
2286
2287 if (ath5k_get_bus_type(ah) == ATH_AHB)
2288 break;
2289
2290 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
2291
2292 /*
2293 * Until we handle rx/tx interrupts mask them on IMR
2294 *
2295 * NOTE: ah->(rx/tx)_pending are set when scheduling the tasklets
2296 * and unset after we 've handled the interrupts.
2297 */
2298 if (ah->rx_pending || ah->tx_pending)
2299 ath5k_set_current_imask(ah);
2300
2301 if (unlikely(!counter))
2302 ATH5K_WARN(ah, "too many interrupts, giving up for now\n");
2303
2304 /* Fire up calibration poll */
2305 ath5k_intr_calibration_poll(ah);
2306
2307 return IRQ_HANDLED;
2308 }
2309
2310 /*
2311 * Periodically recalibrate the PHY to account
2312 * for temperature/environment changes.
2313 */
2314 static void
2315 ath5k_calibrate_work(struct work_struct *work)
2316 {
2317 struct ath5k_hw *ah = container_of(work, struct ath5k_hw,
2318 calib_work);
2319
2320 /* Should we run a full calibration ? */
2321 if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) {
2322
2323 ah->ah_cal_next_full = jiffies +
2324 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2325 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL;
2326
2327 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE,
2328 "running full calibration\n");
2329
2330 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2331 /*
2332 * Rfgain is out of bounds, reset the chip
2333 * to load new gain values.
2334 */
2335 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2336 "got new rfgain, resetting\n");
2337 ieee80211_queue_work(ah->hw, &ah->reset_work);
2338 }
2339 } else
2340 ah->ah_cal_mask |= AR5K_CALIBRATION_SHORT;
2341
2342
2343 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2344 ieee80211_frequency_to_channel(ah->curchan->center_freq),
2345 ah->curchan->hw_value);
2346
2347 if (ath5k_hw_phy_calibrate(ah, ah->curchan))
2348 ATH5K_ERR(ah, "calibration of channel %u failed\n",
2349 ieee80211_frequency_to_channel(
2350 ah->curchan->center_freq));
2351
2352 /* Clear calibration flags */
2353 if (ah->ah_cal_mask & AR5K_CALIBRATION_FULL)
2354 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL;
2355 else if (ah->ah_cal_mask & AR5K_CALIBRATION_SHORT)
2356 ah->ah_cal_mask &= ~AR5K_CALIBRATION_SHORT;
2357 }
2358
2359
2360 static void
2361 ath5k_tasklet_ani(unsigned long data)
2362 {
2363 struct ath5k_hw *ah = (void *)data;
2364
2365 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI;
2366 ath5k_ani_calibration(ah);
2367 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI;
2368 }
2369
2370
2371 static void
2372 ath5k_tx_complete_poll_work(struct work_struct *work)
2373 {
2374 struct ath5k_hw *ah = container_of(work, struct ath5k_hw,
2375 tx_complete_work.work);
2376 struct ath5k_txq *txq;
2377 int i;
2378 bool needreset = false;
2379
2380 mutex_lock(&ah->lock);
2381
2382 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) {
2383 if (ah->txqs[i].setup) {
2384 txq = &ah->txqs[i];
2385 spin_lock_bh(&txq->lock);
2386 if (txq->txq_len > 1) {
2387 if (txq->txq_poll_mark) {
2388 ATH5K_DBG(ah, ATH5K_DEBUG_XMIT,
2389 "TX queue stuck %d\n",
2390 txq->qnum);
2391 needreset = true;
2392 txq->txq_stuck++;
2393 spin_unlock_bh(&txq->lock);
2394 break;
2395 } else {
2396 txq->txq_poll_mark = true;
2397 }
2398 }
2399 spin_unlock_bh(&txq->lock);
2400 }
2401 }
2402
2403 if (needreset) {
2404 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2405 "TX queues stuck, resetting\n");
2406 ath5k_reset(ah, NULL, true);
2407 }
2408
2409 mutex_unlock(&ah->lock);
2410
2411 ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work,
2412 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2413 }
2414
2415
2416 /*************************\
2417 * Initialization routines *
2418 \*************************/
2419
2420 static const struct ieee80211_iface_limit if_limits[] = {
2421 { .max = 2048, .types = BIT(NL80211_IFTYPE_STATION) },
2422 { .max = 4, .types =
2423 #ifdef CONFIG_MAC80211_MESH
2424 BIT(NL80211_IFTYPE_MESH_POINT) |
2425 #endif
2426 BIT(NL80211_IFTYPE_AP) },
2427 };
2428
2429 static const struct ieee80211_iface_combination if_comb = {
2430 .limits = if_limits,
2431 .n_limits = ARRAY_SIZE(if_limits),
2432 .max_interfaces = 2048,
2433 .num_different_channels = 1,
2434 };
2435
2436 int __devinit
2437 ath5k_init_ah(struct ath5k_hw *ah, const struct ath_bus_ops *bus_ops)
2438 {
2439 struct ieee80211_hw *hw = ah->hw;
2440 struct ath_common *common;
2441 int ret;
2442 int csz;
2443
2444 /* Initialize driver private data */
2445 SET_IEEE80211_DEV(hw, ah->dev);
2446 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
2447 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2448 IEEE80211_HW_SIGNAL_DBM |
2449 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
2450
2451 hw->wiphy->interface_modes =
2452 BIT(NL80211_IFTYPE_AP) |
2453 BIT(NL80211_IFTYPE_STATION) |
2454 BIT(NL80211_IFTYPE_ADHOC) |
2455 BIT(NL80211_IFTYPE_MESH_POINT);
2456
2457 hw->wiphy->iface_combinations = &if_comb;
2458 hw->wiphy->n_iface_combinations = 1;
2459
2460 /* SW support for IBSS_RSN is provided by mac80211 */
2461 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
2462
2463 /* both antennas can be configured as RX or TX */
2464 hw->wiphy->available_antennas_tx = 0x3;
2465 hw->wiphy->available_antennas_rx = 0x3;
2466
2467 hw->extra_tx_headroom = 2;
2468 hw->channel_change_time = 5000;
2469
2470 /*
2471 * Mark the device as detached to avoid processing
2472 * interrupts until setup is complete.
2473 */
2474 __set_bit(ATH_STAT_INVALID, ah->status);
2475
2476 ah->opmode = NL80211_IFTYPE_STATION;
2477 ah->bintval = 1000;
2478 mutex_init(&ah->lock);
2479 spin_lock_init(&ah->rxbuflock);
2480 spin_lock_init(&ah->txbuflock);
2481 spin_lock_init(&ah->block);
2482 spin_lock_init(&ah->irqlock);
2483
2484 /* Setup interrupt handler */
2485 ret = request_irq(ah->irq, ath5k_intr, IRQF_SHARED, "ath", ah);
2486 if (ret) {
2487 ATH5K_ERR(ah, "request_irq failed\n");
2488 goto err;
2489 }
2490
2491 common = ath5k_hw_common(ah);
2492 common->ops = &ath5k_common_ops;
2493 common->bus_ops = bus_ops;
2494 common->ah = ah;
2495 common->hw = hw;
2496 common->priv = ah;
2497 common->clockrate = 40;
2498
2499 /*
2500 * Cache line size is used to size and align various
2501 * structures used to communicate with the hardware.
2502 */
2503 ath5k_read_cachesize(common, &csz);
2504 common->cachelsz = csz << 2; /* convert to bytes */
2505
2506 spin_lock_init(&common->cc_lock);
2507
2508 /* Initialize device */
2509 ret = ath5k_hw_init(ah);
2510 if (ret)
2511 goto err_irq;
2512
2513 /* Set up multi-rate retry capabilities */
2514 if (ah->ah_capabilities.cap_has_mrr_support) {
2515 hw->max_rates = 4;
2516 hw->max_rate_tries = max(AR5K_INIT_RETRY_SHORT,
2517 AR5K_INIT_RETRY_LONG);
2518 }
2519
2520 hw->vif_data_size = sizeof(struct ath5k_vif);
2521
2522 /* Finish private driver data initialization */
2523 ret = ath5k_init(hw);
2524 if (ret)
2525 goto err_ah;
2526
2527 ATH5K_INFO(ah, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
2528 ath5k_chip_name(AR5K_VERSION_MAC, ah->ah_mac_srev),
2529 ah->ah_mac_srev,
2530 ah->ah_phy_revision);
2531
2532 if (!ah->ah_single_chip) {
2533 /* Single chip radio (!RF5111) */
2534 if (ah->ah_radio_5ghz_revision &&
2535 !ah->ah_radio_2ghz_revision) {
2536 /* No 5GHz support -> report 2GHz radio */
2537 if (!test_bit(AR5K_MODE_11A,
2538 ah->ah_capabilities.cap_mode)) {
2539 ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n",
2540 ath5k_chip_name(AR5K_VERSION_RAD,
2541 ah->ah_radio_5ghz_revision),
2542 ah->ah_radio_5ghz_revision);
2543 /* No 2GHz support (5110 and some
2544 * 5GHz only cards) -> report 5GHz radio */
2545 } else if (!test_bit(AR5K_MODE_11B,
2546 ah->ah_capabilities.cap_mode)) {
2547 ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n",
2548 ath5k_chip_name(AR5K_VERSION_RAD,
2549 ah->ah_radio_5ghz_revision),
2550 ah->ah_radio_5ghz_revision);
2551 /* Multiband radio */
2552 } else {
2553 ATH5K_INFO(ah, "RF%s multiband radio found"
2554 " (0x%x)\n",
2555 ath5k_chip_name(AR5K_VERSION_RAD,
2556 ah->ah_radio_5ghz_revision),
2557 ah->ah_radio_5ghz_revision);
2558 }
2559 }
2560 /* Multi chip radio (RF5111 - RF2111) ->
2561 * report both 2GHz/5GHz radios */
2562 else if (ah->ah_radio_5ghz_revision &&
2563 ah->ah_radio_2ghz_revision) {
2564 ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n",
2565 ath5k_chip_name(AR5K_VERSION_RAD,
2566 ah->ah_radio_5ghz_revision),
2567 ah->ah_radio_5ghz_revision);
2568 ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n",
2569 ath5k_chip_name(AR5K_VERSION_RAD,
2570 ah->ah_radio_2ghz_revision),
2571 ah->ah_radio_2ghz_revision);
2572 }
2573 }
2574
2575 ath5k_debug_init_device(ah);
2576
2577 /* ready to process interrupts */
2578 __clear_bit(ATH_STAT_INVALID, ah->status);
2579
2580 return 0;
2581 err_ah:
2582 ath5k_hw_deinit(ah);
2583 err_irq:
2584 free_irq(ah->irq, ah);
2585 err:
2586 return ret;
2587 }
2588
2589 static int
2590 ath5k_stop_locked(struct ath5k_hw *ah)
2591 {
2592
2593 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "invalid %u\n",
2594 test_bit(ATH_STAT_INVALID, ah->status));
2595
2596 /*
2597 * Shutdown the hardware and driver:
2598 * stop output from above
2599 * disable interrupts
2600 * turn off timers
2601 * turn off the radio
2602 * clear transmit machinery
2603 * clear receive machinery
2604 * drain and release tx queues
2605 * reclaim beacon resources
2606 * power down hardware
2607 *
2608 * Note that some of this work is not possible if the
2609 * hardware is gone (invalid).
2610 */
2611 ieee80211_stop_queues(ah->hw);
2612
2613 if (!test_bit(ATH_STAT_INVALID, ah->status)) {
2614 ath5k_led_off(ah);
2615 ath5k_hw_set_imr(ah, 0);
2616 synchronize_irq(ah->irq);
2617 ath5k_rx_stop(ah);
2618 ath5k_hw_dma_stop(ah);
2619 ath5k_drain_tx_buffs(ah);
2620 ath5k_hw_phy_disable(ah);
2621 }
2622
2623 return 0;
2624 }
2625
2626 int ath5k_start(struct ieee80211_hw *hw)
2627 {
2628 struct ath5k_hw *ah = hw->priv;
2629 struct ath_common *common = ath5k_hw_common(ah);
2630 int ret, i;
2631
2632 mutex_lock(&ah->lock);
2633
2634 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "mode %d\n", ah->opmode);
2635
2636 /*
2637 * Stop anything previously setup. This is safe
2638 * no matter this is the first time through or not.
2639 */
2640 ath5k_stop_locked(ah);
2641
2642 /*
2643 * The basic interface to setting the hardware in a good
2644 * state is ``reset''. On return the hardware is known to
2645 * be powered up and with interrupts disabled. This must
2646 * be followed by initialization of the appropriate bits
2647 * and then setup of the interrupt mask.
2648 */
2649 ah->curchan = ah->hw->conf.channel;
2650 ah->imask = AR5K_INT_RXOK
2651 | AR5K_INT_RXERR
2652 | AR5K_INT_RXEOL
2653 | AR5K_INT_RXORN
2654 | AR5K_INT_TXDESC
2655 | AR5K_INT_TXEOL
2656 | AR5K_INT_FATAL
2657 | AR5K_INT_GLOBAL
2658 | AR5K_INT_MIB;
2659
2660 ret = ath5k_reset(ah, NULL, false);
2661 if (ret)
2662 goto done;
2663
2664 if (!ath5k_modparam_no_hw_rfkill_switch)
2665 ath5k_rfkill_hw_start(ah);
2666
2667 /*
2668 * Reset the key cache since some parts do not reset the
2669 * contents on initial power up or resume from suspend.
2670 */
2671 for (i = 0; i < common->keymax; i++)
2672 ath_hw_keyreset(common, (u16) i);
2673
2674 /* Use higher rates for acks instead of base
2675 * rate */
2676 ah->ah_ack_bitrate_high = true;
2677
2678 for (i = 0; i < ARRAY_SIZE(ah->bslot); i++)
2679 ah->bslot[i] = NULL;
2680
2681 ret = 0;
2682 done:
2683 mmiowb();
2684 mutex_unlock(&ah->lock);
2685
2686 ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work,
2687 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2688
2689 return ret;
2690 }
2691
2692 static void ath5k_stop_tasklets(struct ath5k_hw *ah)
2693 {
2694 ah->rx_pending = false;
2695 ah->tx_pending = false;
2696 tasklet_kill(&ah->rxtq);
2697 tasklet_kill(&ah->txtq);
2698 tasklet_kill(&ah->beacontq);
2699 tasklet_kill(&ah->ani_tasklet);
2700 }
2701
2702 /*
2703 * Stop the device, grabbing the top-level lock to protect
2704 * against concurrent entry through ath5k_init (which can happen
2705 * if another thread does a system call and the thread doing the
2706 * stop is preempted).
2707 */
2708 void ath5k_stop(struct ieee80211_hw *hw)
2709 {
2710 struct ath5k_hw *ah = hw->priv;
2711 int ret;
2712
2713 mutex_lock(&ah->lock);
2714 ret = ath5k_stop_locked(ah);
2715 if (ret == 0 && !test_bit(ATH_STAT_INVALID, ah->status)) {
2716 /*
2717 * Don't set the card in full sleep mode!
2718 *
2719 * a) When the device is in this state it must be carefully
2720 * woken up or references to registers in the PCI clock
2721 * domain may freeze the bus (and system). This varies
2722 * by chip and is mostly an issue with newer parts
2723 * (madwifi sources mentioned srev >= 0x78) that go to
2724 * sleep more quickly.
2725 *
2726 * b) On older chips full sleep results a weird behaviour
2727 * during wakeup. I tested various cards with srev < 0x78
2728 * and they don't wake up after module reload, a second
2729 * module reload is needed to bring the card up again.
2730 *
2731 * Until we figure out what's going on don't enable
2732 * full chip reset on any chip (this is what Legacy HAL
2733 * and Sam's HAL do anyway). Instead Perform a full reset
2734 * on the device (same as initial state after attach) and
2735 * leave it idle (keep MAC/BB on warm reset) */
2736 ret = ath5k_hw_on_hold(ah);
2737
2738 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2739 "putting device to sleep\n");
2740 }
2741
2742 mmiowb();
2743 mutex_unlock(&ah->lock);
2744
2745 ath5k_stop_tasklets(ah);
2746
2747 cancel_delayed_work_sync(&ah->tx_complete_work);
2748
2749 if (!ath5k_modparam_no_hw_rfkill_switch)
2750 ath5k_rfkill_hw_stop(ah);
2751 }
2752
2753 /*
2754 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2755 * and change to the given channel.
2756 *
2757 * This should be called with ah->lock.
2758 */
2759 static int
2760 ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan,
2761 bool skip_pcu)
2762 {
2763 struct ath_common *common = ath5k_hw_common(ah);
2764 int ret, ani_mode;
2765 bool fast;
2766
2767 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "resetting\n");
2768
2769 ath5k_hw_set_imr(ah, 0);
2770 synchronize_irq(ah->irq);
2771 ath5k_stop_tasklets(ah);
2772
2773 /* Save ani mode and disable ANI during
2774 * reset. If we don't we might get false
2775 * PHY error interrupts. */
2776 ani_mode = ah->ani_state.ani_mode;
2777 ath5k_ani_init(ah, ATH5K_ANI_MODE_OFF);
2778
2779 /* We are going to empty hw queues
2780 * so we should also free any remaining
2781 * tx buffers */
2782 ath5k_drain_tx_buffs(ah);
2783 if (chan)
2784 ah->curchan = chan;
2785
2786 fast = ((chan != NULL) && modparam_fastchanswitch) ? 1 : 0;
2787
2788 ret = ath5k_hw_reset(ah, ah->opmode, ah->curchan, fast, skip_pcu);
2789 if (ret) {
2790 ATH5K_ERR(ah, "can't reset hardware (%d)\n", ret);
2791 goto err;
2792 }
2793
2794 ret = ath5k_rx_start(ah);
2795 if (ret) {
2796 ATH5K_ERR(ah, "can't start recv logic\n");
2797 goto err;
2798 }
2799
2800 ath5k_ani_init(ah, ani_mode);
2801
2802 /*
2803 * Set calibration intervals
2804 *
2805 * Note: We don't need to run calibration imediately
2806 * since some initial calibration is done on reset
2807 * even for fast channel switching. Also on scanning
2808 * this will get set again and again and it won't get
2809 * executed unless we connect somewhere and spend some
2810 * time on the channel (that's what calibration needs
2811 * anyway to be accurate).
2812 */
2813 ah->ah_cal_next_full = jiffies +
2814 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2815 ah->ah_cal_next_ani = jiffies +
2816 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
2817 ah->ah_cal_next_short = jiffies +
2818 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_SHORT);
2819
2820 ewma_init(&ah->ah_beacon_rssi_avg, 1024, 8);
2821
2822 /* clear survey data and cycle counters */
2823 memset(&ah->survey, 0, sizeof(ah->survey));
2824 spin_lock_bh(&common->cc_lock);
2825 ath_hw_cycle_counters_update(common);
2826 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
2827 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
2828 spin_unlock_bh(&common->cc_lock);
2829
2830 /*
2831 * Change channels and update the h/w rate map if we're switching;
2832 * e.g. 11a to 11b/g.
2833 *
2834 * We may be doing a reset in response to an ioctl that changes the
2835 * channel so update any state that might change as a result.
2836 *
2837 * XXX needed?
2838 */
2839 /* ath5k_chan_change(ah, c); */
2840
2841 ath5k_beacon_config(ah);
2842 /* intrs are enabled by ath5k_beacon_config */
2843
2844 ieee80211_wake_queues(ah->hw);
2845
2846 return 0;
2847 err:
2848 return ret;
2849 }
2850
2851 static void ath5k_reset_work(struct work_struct *work)
2852 {
2853 struct ath5k_hw *ah = container_of(work, struct ath5k_hw,
2854 reset_work);
2855
2856 mutex_lock(&ah->lock);
2857 ath5k_reset(ah, NULL, true);
2858 mutex_unlock(&ah->lock);
2859 }
2860
2861 static int __devinit
2862 ath5k_init(struct ieee80211_hw *hw)
2863 {
2864
2865 struct ath5k_hw *ah = hw->priv;
2866 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
2867 struct ath5k_txq *txq;
2868 u8 mac[ETH_ALEN] = {};
2869 int ret;
2870
2871
2872 /*
2873 * Collect the channel list. The 802.11 layer
2874 * is responsible for filtering this list based
2875 * on settings like the phy mode and regulatory
2876 * domain restrictions.
2877 */
2878 ret = ath5k_setup_bands(hw);
2879 if (ret) {
2880 ATH5K_ERR(ah, "can't get channels\n");
2881 goto err;
2882 }
2883
2884 /*
2885 * Allocate tx+rx descriptors and populate the lists.
2886 */
2887 ret = ath5k_desc_alloc(ah);
2888 if (ret) {
2889 ATH5K_ERR(ah, "can't allocate descriptors\n");
2890 goto err;
2891 }
2892
2893 /*
2894 * Allocate hardware transmit queues: one queue for
2895 * beacon frames and one data queue for each QoS
2896 * priority. Note that hw functions handle resetting
2897 * these queues at the needed time.
2898 */
2899 ret = ath5k_beaconq_setup(ah);
2900 if (ret < 0) {
2901 ATH5K_ERR(ah, "can't setup a beacon xmit queue\n");
2902 goto err_desc;
2903 }
2904 ah->bhalq = ret;
2905 ah->cabq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_CAB, 0);
2906 if (IS_ERR(ah->cabq)) {
2907 ATH5K_ERR(ah, "can't setup cab queue\n");
2908 ret = PTR_ERR(ah->cabq);
2909 goto err_bhal;
2910 }
2911
2912 /* 5211 and 5212 usually support 10 queues but we better rely on the
2913 * capability information */
2914 if (ah->ah_capabilities.cap_queues.q_tx_num >= 6) {
2915 /* This order matches mac80211's queue priority, so we can
2916 * directly use the mac80211 queue number without any mapping */
2917 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO);
2918 if (IS_ERR(txq)) {
2919 ATH5K_ERR(ah, "can't setup xmit queue\n");
2920 ret = PTR_ERR(txq);
2921 goto err_queues;
2922 }
2923 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI);
2924 if (IS_ERR(txq)) {
2925 ATH5K_ERR(ah, "can't setup xmit queue\n");
2926 ret = PTR_ERR(txq);
2927 goto err_queues;
2928 }
2929 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
2930 if (IS_ERR(txq)) {
2931 ATH5K_ERR(ah, "can't setup xmit queue\n");
2932 ret = PTR_ERR(txq);
2933 goto err_queues;
2934 }
2935 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
2936 if (IS_ERR(txq)) {
2937 ATH5K_ERR(ah, "can't setup xmit queue\n");
2938 ret = PTR_ERR(txq);
2939 goto err_queues;
2940 }
2941 hw->queues = 4;
2942 } else {
2943 /* older hardware (5210) can only support one data queue */
2944 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
2945 if (IS_ERR(txq)) {
2946 ATH5K_ERR(ah, "can't setup xmit queue\n");
2947 ret = PTR_ERR(txq);
2948 goto err_queues;
2949 }
2950 hw->queues = 1;
2951 }
2952
2953 tasklet_init(&ah->rxtq, ath5k_tasklet_rx, (unsigned long)ah);
2954 tasklet_init(&ah->txtq, ath5k_tasklet_tx, (unsigned long)ah);
2955 tasklet_init(&ah->beacontq, ath5k_tasklet_beacon, (unsigned long)ah);
2956 tasklet_init(&ah->ani_tasklet, ath5k_tasklet_ani, (unsigned long)ah);
2957
2958 INIT_WORK(&ah->reset_work, ath5k_reset_work);
2959 INIT_WORK(&ah->calib_work, ath5k_calibrate_work);
2960 INIT_DELAYED_WORK(&ah->tx_complete_work, ath5k_tx_complete_poll_work);
2961
2962 ret = ath5k_hw_common(ah)->bus_ops->eeprom_read_mac(ah, mac);
2963 if (ret) {
2964 ATH5K_ERR(ah, "unable to read address from EEPROM\n");
2965 goto err_queues;
2966 }
2967
2968 SET_IEEE80211_PERM_ADDR(hw, mac);
2969 /* All MAC address bits matter for ACKs */
2970 ath5k_update_bssid_mask_and_opmode(ah, NULL);
2971
2972 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
2973 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
2974 if (ret) {
2975 ATH5K_ERR(ah, "can't initialize regulatory system\n");
2976 goto err_queues;
2977 }
2978
2979 ret = ieee80211_register_hw(hw);
2980 if (ret) {
2981 ATH5K_ERR(ah, "can't register ieee80211 hw\n");
2982 goto err_queues;
2983 }
2984
2985 if (!ath_is_world_regd(regulatory))
2986 regulatory_hint(hw->wiphy, regulatory->alpha2);
2987
2988 ath5k_init_leds(ah);
2989
2990 ath5k_sysfs_register(ah);
2991
2992 return 0;
2993 err_queues:
2994 ath5k_txq_release(ah);
2995 err_bhal:
2996 ath5k_hw_release_tx_queue(ah, ah->bhalq);
2997 err_desc:
2998 ath5k_desc_free(ah);
2999 err:
3000 return ret;
3001 }
3002
3003 void
3004 ath5k_deinit_ah(struct ath5k_hw *ah)
3005 {
3006 struct ieee80211_hw *hw = ah->hw;
3007
3008 /*
3009 * NB: the order of these is important:
3010 * o call the 802.11 layer before detaching ath5k_hw to
3011 * ensure callbacks into the driver to delete global
3012 * key cache entries can be handled
3013 * o reclaim the tx queue data structures after calling
3014 * the 802.11 layer as we'll get called back to reclaim
3015 * node state and potentially want to use them
3016 * o to cleanup the tx queues the hal is called, so detach
3017 * it last
3018 * XXX: ??? detach ath5k_hw ???
3019 * Other than that, it's straightforward...
3020 */
3021 ieee80211_unregister_hw(hw);
3022 ath5k_desc_free(ah);
3023 ath5k_txq_release(ah);
3024 ath5k_hw_release_tx_queue(ah, ah->bhalq);
3025 ath5k_unregister_leds(ah);
3026
3027 ath5k_sysfs_unregister(ah);
3028 /*
3029 * NB: can't reclaim these until after ieee80211_ifdetach
3030 * returns because we'll get called back to reclaim node
3031 * state and potentially want to use them.
3032 */
3033 ath5k_hw_deinit(ah);
3034 free_irq(ah->irq, ah);
3035 }
3036
3037 bool
3038 ath5k_any_vif_assoc(struct ath5k_hw *ah)
3039 {
3040 struct ath5k_vif_iter_data iter_data;
3041 iter_data.hw_macaddr = NULL;
3042 iter_data.any_assoc = false;
3043 iter_data.need_set_hw_addr = false;
3044 iter_data.found_active = true;
3045
3046 ieee80211_iterate_active_interfaces_atomic(ah->hw, ath5k_vif_iter,
3047 &iter_data);
3048 return iter_data.any_assoc;
3049 }
3050
3051 void
3052 ath5k_set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3053 {
3054 struct ath5k_hw *ah = hw->priv;
3055 u32 rfilt;
3056 rfilt = ath5k_hw_get_rx_filter(ah);
3057 if (enable)
3058 rfilt |= AR5K_RX_FILTER_BEACON;
3059 else
3060 rfilt &= ~AR5K_RX_FILTER_BEACON;
3061 ath5k_hw_set_rx_filter(ah, rfilt);
3062 ah->filter_flags = rfilt;
3063 }
3064
3065 void _ath5k_printk(const struct ath5k_hw *ah, const char *level,
3066 const char *fmt, ...)
3067 {
3068 struct va_format vaf;
3069 va_list args;
3070
3071 va_start(args, fmt);
3072
3073 vaf.fmt = fmt;
3074 vaf.va = &args;
3075
3076 if (ah && ah->hw)
3077 printk("%s" pr_fmt("%s: %pV"),
3078 level, wiphy_name(ah->hw->wiphy), &vaf);
3079 else
3080 printk("%s" pr_fmt("%pV"), level, &vaf);
3081
3082 va_end(args);
3083 }
Linux kernel - Deliverables
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