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mac80211: push rx status into skb->cb
[deliverable/linux.git] / drivers / net / wireless / ath / ath5k / base.c
1 /*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
43 #include <linux/module.h>
44 #include <linux/delay.h>
45 #include <linux/hardirq.h>
46 #include <linux/if.h>
47 #include <linux/io.h>
48 #include <linux/netdevice.h>
49 #include <linux/cache.h>
50 #include <linux/pci.h>
51 #include <linux/ethtool.h>
52 #include <linux/uaccess.h>
53
54 #include <net/ieee80211_radiotap.h>
55
56 #include <asm/unaligned.h>
57
58 #include "base.h"
59 #include "reg.h"
60 #include "debug.h"
61
62 static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
63 static int modparam_nohwcrypt;
64 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
65 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
66
67 static int modparam_all_channels;
68 module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
69 MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
70
71
72 /******************\
73 * Internal defines *
74 \******************/
75
76 /* Module info */
77 MODULE_AUTHOR("Jiri Slaby");
78 MODULE_AUTHOR("Nick Kossifidis");
79 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
80 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
81 MODULE_LICENSE("Dual BSD/GPL");
82 MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
83
84
85 /* Known PCI ids */
86 static const struct pci_device_id ath5k_pci_id_table[] = {
87 { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
88 { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
89 { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
90 { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
91 { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
92 { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
93 { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
94 { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
95 { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
96 { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
98 { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
99 { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
101 { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
102 { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
103 { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* PCI-E cards */
104 { PCI_VDEVICE(ATHEROS, 0x001d), .driver_data = AR5K_AR5212 }, /* 2417 Nala */
105 { 0 }
106 };
107 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
108
109 /* Known SREVs */
110 static const struct ath5k_srev_name srev_names[] = {
111 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
112 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
113 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
114 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
115 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
116 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
117 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
118 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
119 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
120 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
121 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
122 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
123 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
124 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
125 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
126 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
127 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
128 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
129 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
130 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
131 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
132 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
133 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
134 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
135 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
136 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
137 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
138 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
139 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
140 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
141 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
142 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
143 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
144 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
145 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
146 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
147 };
148
149 static const struct ieee80211_rate ath5k_rates[] = {
150 { .bitrate = 10,
151 .hw_value = ATH5K_RATE_CODE_1M, },
152 { .bitrate = 20,
153 .hw_value = ATH5K_RATE_CODE_2M,
154 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
155 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
156 { .bitrate = 55,
157 .hw_value = ATH5K_RATE_CODE_5_5M,
158 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
159 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
160 { .bitrate = 110,
161 .hw_value = ATH5K_RATE_CODE_11M,
162 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
163 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
164 { .bitrate = 60,
165 .hw_value = ATH5K_RATE_CODE_6M,
166 .flags = 0 },
167 { .bitrate = 90,
168 .hw_value = ATH5K_RATE_CODE_9M,
169 .flags = 0 },
170 { .bitrate = 120,
171 .hw_value = ATH5K_RATE_CODE_12M,
172 .flags = 0 },
173 { .bitrate = 180,
174 .hw_value = ATH5K_RATE_CODE_18M,
175 .flags = 0 },
176 { .bitrate = 240,
177 .hw_value = ATH5K_RATE_CODE_24M,
178 .flags = 0 },
179 { .bitrate = 360,
180 .hw_value = ATH5K_RATE_CODE_36M,
181 .flags = 0 },
182 { .bitrate = 480,
183 .hw_value = ATH5K_RATE_CODE_48M,
184 .flags = 0 },
185 { .bitrate = 540,
186 .hw_value = ATH5K_RATE_CODE_54M,
187 .flags = 0 },
188 /* XR missing */
189 };
190
191 /*
192 * Prototypes - PCI stack related functions
193 */
194 static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
195 const struct pci_device_id *id);
196 static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
197 #ifdef CONFIG_PM
198 static int ath5k_pci_suspend(struct pci_dev *pdev,
199 pm_message_t state);
200 static int ath5k_pci_resume(struct pci_dev *pdev);
201 #else
202 #define ath5k_pci_suspend NULL
203 #define ath5k_pci_resume NULL
204 #endif /* CONFIG_PM */
205
206 static struct pci_driver ath5k_pci_driver = {
207 .name = KBUILD_MODNAME,
208 .id_table = ath5k_pci_id_table,
209 .probe = ath5k_pci_probe,
210 .remove = __devexit_p(ath5k_pci_remove),
211 .suspend = ath5k_pci_suspend,
212 .resume = ath5k_pci_resume,
213 };
214
215
216
217 /*
218 * Prototypes - MAC 802.11 stack related functions
219 */
220 static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
221 static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan);
222 static int ath5k_reset_wake(struct ath5k_softc *sc);
223 static int ath5k_start(struct ieee80211_hw *hw);
224 static void ath5k_stop(struct ieee80211_hw *hw);
225 static int ath5k_add_interface(struct ieee80211_hw *hw,
226 struct ieee80211_if_init_conf *conf);
227 static void ath5k_remove_interface(struct ieee80211_hw *hw,
228 struct ieee80211_if_init_conf *conf);
229 static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
230 static void ath5k_configure_filter(struct ieee80211_hw *hw,
231 unsigned int changed_flags,
232 unsigned int *new_flags,
233 int mc_count, struct dev_mc_list *mclist);
234 static int ath5k_set_key(struct ieee80211_hw *hw,
235 enum set_key_cmd cmd,
236 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
237 struct ieee80211_key_conf *key);
238 static int ath5k_get_stats(struct ieee80211_hw *hw,
239 struct ieee80211_low_level_stats *stats);
240 static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
241 struct ieee80211_tx_queue_stats *stats);
242 static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
243 static void ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf);
244 static void ath5k_reset_tsf(struct ieee80211_hw *hw);
245 static int ath5k_beacon_update(struct ieee80211_hw *hw,
246 struct ieee80211_vif *vif);
247 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
248 struct ieee80211_vif *vif,
249 struct ieee80211_bss_conf *bss_conf,
250 u32 changes);
251 static void ath5k_sw_scan_start(struct ieee80211_hw *hw);
252 static void ath5k_sw_scan_complete(struct ieee80211_hw *hw);
253
254 static const struct ieee80211_ops ath5k_hw_ops = {
255 .tx = ath5k_tx,
256 .start = ath5k_start,
257 .stop = ath5k_stop,
258 .add_interface = ath5k_add_interface,
259 .remove_interface = ath5k_remove_interface,
260 .config = ath5k_config,
261 .configure_filter = ath5k_configure_filter,
262 .set_key = ath5k_set_key,
263 .get_stats = ath5k_get_stats,
264 .conf_tx = NULL,
265 .get_tx_stats = ath5k_get_tx_stats,
266 .get_tsf = ath5k_get_tsf,
267 .set_tsf = ath5k_set_tsf,
268 .reset_tsf = ath5k_reset_tsf,
269 .bss_info_changed = ath5k_bss_info_changed,
270 .sw_scan_start = ath5k_sw_scan_start,
271 .sw_scan_complete = ath5k_sw_scan_complete,
272 };
273
274 /*
275 * Prototypes - Internal functions
276 */
277 /* Attach detach */
278 static int ath5k_attach(struct pci_dev *pdev,
279 struct ieee80211_hw *hw);
280 static void ath5k_detach(struct pci_dev *pdev,
281 struct ieee80211_hw *hw);
282 /* Channel/mode setup */
283 static inline short ath5k_ieee2mhz(short chan);
284 static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
285 struct ieee80211_channel *channels,
286 unsigned int mode,
287 unsigned int max);
288 static int ath5k_setup_bands(struct ieee80211_hw *hw);
289 static int ath5k_chan_set(struct ath5k_softc *sc,
290 struct ieee80211_channel *chan);
291 static void ath5k_setcurmode(struct ath5k_softc *sc,
292 unsigned int mode);
293 static void ath5k_mode_setup(struct ath5k_softc *sc);
294
295 /* Descriptor setup */
296 static int ath5k_desc_alloc(struct ath5k_softc *sc,
297 struct pci_dev *pdev);
298 static void ath5k_desc_free(struct ath5k_softc *sc,
299 struct pci_dev *pdev);
300 /* Buffers setup */
301 static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
302 struct ath5k_buf *bf);
303 static int ath5k_txbuf_setup(struct ath5k_softc *sc,
304 struct ath5k_buf *bf);
305 static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
306 struct ath5k_buf *bf)
307 {
308 BUG_ON(!bf);
309 if (!bf->skb)
310 return;
311 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
312 PCI_DMA_TODEVICE);
313 dev_kfree_skb_any(bf->skb);
314 bf->skb = NULL;
315 }
316
317 static inline void ath5k_rxbuf_free(struct ath5k_softc *sc,
318 struct ath5k_buf *bf)
319 {
320 BUG_ON(!bf);
321 if (!bf->skb)
322 return;
323 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
324 PCI_DMA_FROMDEVICE);
325 dev_kfree_skb_any(bf->skb);
326 bf->skb = NULL;
327 }
328
329
330 /* Queues setup */
331 static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
332 int qtype, int subtype);
333 static int ath5k_beaconq_setup(struct ath5k_hw *ah);
334 static int ath5k_beaconq_config(struct ath5k_softc *sc);
335 static void ath5k_txq_drainq(struct ath5k_softc *sc,
336 struct ath5k_txq *txq);
337 static void ath5k_txq_cleanup(struct ath5k_softc *sc);
338 static void ath5k_txq_release(struct ath5k_softc *sc);
339 /* Rx handling */
340 static int ath5k_rx_start(struct ath5k_softc *sc);
341 static void ath5k_rx_stop(struct ath5k_softc *sc);
342 static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
343 struct ath5k_desc *ds,
344 struct sk_buff *skb,
345 struct ath5k_rx_status *rs);
346 static void ath5k_tasklet_rx(unsigned long data);
347 /* Tx handling */
348 static void ath5k_tx_processq(struct ath5k_softc *sc,
349 struct ath5k_txq *txq);
350 static void ath5k_tasklet_tx(unsigned long data);
351 /* Beacon handling */
352 static int ath5k_beacon_setup(struct ath5k_softc *sc,
353 struct ath5k_buf *bf);
354 static void ath5k_beacon_send(struct ath5k_softc *sc);
355 static void ath5k_beacon_config(struct ath5k_softc *sc);
356 static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
357 static void ath5k_tasklet_beacon(unsigned long data);
358
359 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
360 {
361 u64 tsf = ath5k_hw_get_tsf64(ah);
362
363 if ((tsf & 0x7fff) < rstamp)
364 tsf -= 0x8000;
365
366 return (tsf & ~0x7fff) | rstamp;
367 }
368
369 /* Interrupt handling */
370 static int ath5k_init(struct ath5k_softc *sc);
371 static int ath5k_stop_locked(struct ath5k_softc *sc);
372 static int ath5k_stop_hw(struct ath5k_softc *sc);
373 static irqreturn_t ath5k_intr(int irq, void *dev_id);
374 static void ath5k_tasklet_reset(unsigned long data);
375
376 static void ath5k_calibrate(unsigned long data);
377
378 /*
379 * Module init/exit functions
380 */
381 static int __init
382 init_ath5k_pci(void)
383 {
384 int ret;
385
386 ath5k_debug_init();
387
388 ret = pci_register_driver(&ath5k_pci_driver);
389 if (ret) {
390 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
391 return ret;
392 }
393
394 return 0;
395 }
396
397 static void __exit
398 exit_ath5k_pci(void)
399 {
400 pci_unregister_driver(&ath5k_pci_driver);
401
402 ath5k_debug_finish();
403 }
404
405 module_init(init_ath5k_pci);
406 module_exit(exit_ath5k_pci);
407
408
409 /********************\
410 * PCI Initialization *
411 \********************/
412
413 static const char *
414 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
415 {
416 const char *name = "xxxxx";
417 unsigned int i;
418
419 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
420 if (srev_names[i].sr_type != type)
421 continue;
422
423 if ((val & 0xf0) == srev_names[i].sr_val)
424 name = srev_names[i].sr_name;
425
426 if ((val & 0xff) == srev_names[i].sr_val) {
427 name = srev_names[i].sr_name;
428 break;
429 }
430 }
431
432 return name;
433 }
434
435 static int __devinit
436 ath5k_pci_probe(struct pci_dev *pdev,
437 const struct pci_device_id *id)
438 {
439 void __iomem *mem;
440 struct ath5k_softc *sc;
441 struct ieee80211_hw *hw;
442 int ret;
443 u8 csz;
444
445 ret = pci_enable_device(pdev);
446 if (ret) {
447 dev_err(&pdev->dev, "can't enable device\n");
448 goto err;
449 }
450
451 /* XXX 32-bit addressing only */
452 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
453 if (ret) {
454 dev_err(&pdev->dev, "32-bit DMA not available\n");
455 goto err_dis;
456 }
457
458 /*
459 * Cache line size is used to size and align various
460 * structures used to communicate with the hardware.
461 */
462 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
463 if (csz == 0) {
464 /*
465 * Linux 2.4.18 (at least) writes the cache line size
466 * register as a 16-bit wide register which is wrong.
467 * We must have this setup properly for rx buffer
468 * DMA to work so force a reasonable value here if it
469 * comes up zero.
470 */
471 csz = L1_CACHE_BYTES / sizeof(u32);
472 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
473 }
474 /*
475 * The default setting of latency timer yields poor results,
476 * set it to the value used by other systems. It may be worth
477 * tweaking this setting more.
478 */
479 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
480
481 /* Enable bus mastering */
482 pci_set_master(pdev);
483
484 /*
485 * Disable the RETRY_TIMEOUT register (0x41) to keep
486 * PCI Tx retries from interfering with C3 CPU state.
487 */
488 pci_write_config_byte(pdev, 0x41, 0);
489
490 ret = pci_request_region(pdev, 0, "ath5k");
491 if (ret) {
492 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
493 goto err_dis;
494 }
495
496 mem = pci_iomap(pdev, 0, 0);
497 if (!mem) {
498 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
499 ret = -EIO;
500 goto err_reg;
501 }
502
503 /*
504 * Allocate hw (mac80211 main struct)
505 * and hw->priv (driver private data)
506 */
507 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
508 if (hw == NULL) {
509 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
510 ret = -ENOMEM;
511 goto err_map;
512 }
513
514 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
515
516 /* Initialize driver private data */
517 SET_IEEE80211_DEV(hw, &pdev->dev);
518 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
519 IEEE80211_HW_SIGNAL_DBM |
520 IEEE80211_HW_NOISE_DBM;
521
522 hw->wiphy->interface_modes =
523 BIT(NL80211_IFTYPE_AP) |
524 BIT(NL80211_IFTYPE_STATION) |
525 BIT(NL80211_IFTYPE_ADHOC) |
526 BIT(NL80211_IFTYPE_MESH_POINT);
527
528 hw->extra_tx_headroom = 2;
529 hw->channel_change_time = 5000;
530 sc = hw->priv;
531 sc->hw = hw;
532 sc->pdev = pdev;
533
534 ath5k_debug_init_device(sc);
535
536 /*
537 * Mark the device as detached to avoid processing
538 * interrupts until setup is complete.
539 */
540 __set_bit(ATH_STAT_INVALID, sc->status);
541
542 sc->iobase = mem; /* So we can unmap it on detach */
543 sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
544 sc->opmode = NL80211_IFTYPE_STATION;
545 sc->bintval = 1000;
546 mutex_init(&sc->lock);
547 spin_lock_init(&sc->rxbuflock);
548 spin_lock_init(&sc->txbuflock);
549 spin_lock_init(&sc->block);
550
551 /* Set private data */
552 pci_set_drvdata(pdev, hw);
553
554 /* Setup interrupt handler */
555 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
556 if (ret) {
557 ATH5K_ERR(sc, "request_irq failed\n");
558 goto err_free;
559 }
560
561 /* Initialize device */
562 sc->ah = ath5k_hw_attach(sc, id->driver_data);
563 if (IS_ERR(sc->ah)) {
564 ret = PTR_ERR(sc->ah);
565 goto err_irq;
566 }
567
568 /* set up multi-rate retry capabilities */
569 if (sc->ah->ah_version == AR5K_AR5212) {
570 hw->max_rates = 4;
571 hw->max_rate_tries = 11;
572 }
573
574 /* Finish private driver data initialization */
575 ret = ath5k_attach(pdev, hw);
576 if (ret)
577 goto err_ah;
578
579 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
580 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
581 sc->ah->ah_mac_srev,
582 sc->ah->ah_phy_revision);
583
584 if (!sc->ah->ah_single_chip) {
585 /* Single chip radio (!RF5111) */
586 if (sc->ah->ah_radio_5ghz_revision &&
587 !sc->ah->ah_radio_2ghz_revision) {
588 /* No 5GHz support -> report 2GHz radio */
589 if (!test_bit(AR5K_MODE_11A,
590 sc->ah->ah_capabilities.cap_mode)) {
591 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
592 ath5k_chip_name(AR5K_VERSION_RAD,
593 sc->ah->ah_radio_5ghz_revision),
594 sc->ah->ah_radio_5ghz_revision);
595 /* No 2GHz support (5110 and some
596 * 5Ghz only cards) -> report 5Ghz radio */
597 } else if (!test_bit(AR5K_MODE_11B,
598 sc->ah->ah_capabilities.cap_mode)) {
599 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
600 ath5k_chip_name(AR5K_VERSION_RAD,
601 sc->ah->ah_radio_5ghz_revision),
602 sc->ah->ah_radio_5ghz_revision);
603 /* Multiband radio */
604 } else {
605 ATH5K_INFO(sc, "RF%s multiband radio found"
606 " (0x%x)\n",
607 ath5k_chip_name(AR5K_VERSION_RAD,
608 sc->ah->ah_radio_5ghz_revision),
609 sc->ah->ah_radio_5ghz_revision);
610 }
611 }
612 /* Multi chip radio (RF5111 - RF2111) ->
613 * report both 2GHz/5GHz radios */
614 else if (sc->ah->ah_radio_5ghz_revision &&
615 sc->ah->ah_radio_2ghz_revision){
616 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
617 ath5k_chip_name(AR5K_VERSION_RAD,
618 sc->ah->ah_radio_5ghz_revision),
619 sc->ah->ah_radio_5ghz_revision);
620 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
621 ath5k_chip_name(AR5K_VERSION_RAD,
622 sc->ah->ah_radio_2ghz_revision),
623 sc->ah->ah_radio_2ghz_revision);
624 }
625 }
626
627
628 /* ready to process interrupts */
629 __clear_bit(ATH_STAT_INVALID, sc->status);
630
631 return 0;
632 err_ah:
633 ath5k_hw_detach(sc->ah);
634 err_irq:
635 free_irq(pdev->irq, sc);
636 err_free:
637 ieee80211_free_hw(hw);
638 err_map:
639 pci_iounmap(pdev, mem);
640 err_reg:
641 pci_release_region(pdev, 0);
642 err_dis:
643 pci_disable_device(pdev);
644 err:
645 return ret;
646 }
647
648 static void __devexit
649 ath5k_pci_remove(struct pci_dev *pdev)
650 {
651 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
652 struct ath5k_softc *sc = hw->priv;
653
654 ath5k_debug_finish_device(sc);
655 ath5k_detach(pdev, hw);
656 ath5k_hw_detach(sc->ah);
657 free_irq(pdev->irq, sc);
658 pci_iounmap(pdev, sc->iobase);
659 pci_release_region(pdev, 0);
660 pci_disable_device(pdev);
661 ieee80211_free_hw(hw);
662 }
663
664 #ifdef CONFIG_PM
665 static int
666 ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
667 {
668 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
669 struct ath5k_softc *sc = hw->priv;
670
671 ath5k_led_off(sc);
672
673 free_irq(pdev->irq, sc);
674 pci_save_state(pdev);
675 pci_disable_device(pdev);
676 pci_set_power_state(pdev, PCI_D3hot);
677
678 return 0;
679 }
680
681 static int
682 ath5k_pci_resume(struct pci_dev *pdev)
683 {
684 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
685 struct ath5k_softc *sc = hw->priv;
686 int err;
687
688 pci_restore_state(pdev);
689
690 err = pci_enable_device(pdev);
691 if (err)
692 return err;
693
694 /*
695 * Suspend/Resume resets the PCI configuration space, so we have to
696 * re-disable the RETRY_TIMEOUT register (0x41) to keep
697 * PCI Tx retries from interfering with C3 CPU state
698 */
699 pci_write_config_byte(pdev, 0x41, 0);
700
701 err = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
702 if (err) {
703 ATH5K_ERR(sc, "request_irq failed\n");
704 goto err_no_irq;
705 }
706
707 ath5k_led_enable(sc);
708 return 0;
709
710 err_no_irq:
711 pci_disable_device(pdev);
712 return err;
713 }
714 #endif /* CONFIG_PM */
715
716
717 /***********************\
718 * Driver Initialization *
719 \***********************/
720
721 static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
722 {
723 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
724 struct ath5k_softc *sc = hw->priv;
725 struct ath_regulatory *reg = &sc->ah->ah_regulatory;
726
727 return ath_reg_notifier_apply(wiphy, request, reg);
728 }
729
730 static int
731 ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
732 {
733 struct ath5k_softc *sc = hw->priv;
734 struct ath5k_hw *ah = sc->ah;
735 u8 mac[ETH_ALEN] = {};
736 int ret;
737
738 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
739
740 /*
741 * Check if the MAC has multi-rate retry support.
742 * We do this by trying to setup a fake extended
743 * descriptor. MAC's that don't have support will
744 * return false w/o doing anything. MAC's that do
745 * support it will return true w/o doing anything.
746 */
747 ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
748 if (ret < 0)
749 goto err;
750 if (ret > 0)
751 __set_bit(ATH_STAT_MRRETRY, sc->status);
752
753 /*
754 * Collect the channel list. The 802.11 layer
755 * is resposible for filtering this list based
756 * on settings like the phy mode and regulatory
757 * domain restrictions.
758 */
759 ret = ath5k_setup_bands(hw);
760 if (ret) {
761 ATH5K_ERR(sc, "can't get channels\n");
762 goto err;
763 }
764
765 /* NB: setup here so ath5k_rate_update is happy */
766 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
767 ath5k_setcurmode(sc, AR5K_MODE_11A);
768 else
769 ath5k_setcurmode(sc, AR5K_MODE_11B);
770
771 /*
772 * Allocate tx+rx descriptors and populate the lists.
773 */
774 ret = ath5k_desc_alloc(sc, pdev);
775 if (ret) {
776 ATH5K_ERR(sc, "can't allocate descriptors\n");
777 goto err;
778 }
779
780 /*
781 * Allocate hardware transmit queues: one queue for
782 * beacon frames and one data queue for each QoS
783 * priority. Note that hw functions handle reseting
784 * these queues at the needed time.
785 */
786 ret = ath5k_beaconq_setup(ah);
787 if (ret < 0) {
788 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
789 goto err_desc;
790 }
791 sc->bhalq = ret;
792
793 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
794 if (IS_ERR(sc->txq)) {
795 ATH5K_ERR(sc, "can't setup xmit queue\n");
796 ret = PTR_ERR(sc->txq);
797 goto err_bhal;
798 }
799
800 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
801 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
802 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
803 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
804 setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
805
806 ret = ath5k_eeprom_read_mac(ah, mac);
807 if (ret) {
808 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
809 sc->pdev->device);
810 goto err_queues;
811 }
812
813 SET_IEEE80211_PERM_ADDR(hw, mac);
814 /* All MAC address bits matter for ACKs */
815 memset(sc->bssidmask, 0xff, ETH_ALEN);
816 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
817
818 ah->ah_regulatory.current_rd =
819 ah->ah_capabilities.cap_eeprom.ee_regdomain;
820 ret = ath_regd_init(&ah->ah_regulatory, hw->wiphy, ath5k_reg_notifier);
821 if (ret) {
822 ATH5K_ERR(sc, "can't initialize regulatory system\n");
823 goto err_queues;
824 }
825
826 ret = ieee80211_register_hw(hw);
827 if (ret) {
828 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
829 goto err_queues;
830 }
831
832 if (!ath_is_world_regd(&sc->ah->ah_regulatory))
833 regulatory_hint(hw->wiphy, sc->ah->ah_regulatory.alpha2);
834
835 ath5k_init_leds(sc);
836
837 return 0;
838 err_queues:
839 ath5k_txq_release(sc);
840 err_bhal:
841 ath5k_hw_release_tx_queue(ah, sc->bhalq);
842 err_desc:
843 ath5k_desc_free(sc, pdev);
844 err:
845 return ret;
846 }
847
848 static void
849 ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
850 {
851 struct ath5k_softc *sc = hw->priv;
852
853 /*
854 * NB: the order of these is important:
855 * o call the 802.11 layer before detaching ath5k_hw to
856 * insure callbacks into the driver to delete global
857 * key cache entries can be handled
858 * o reclaim the tx queue data structures after calling
859 * the 802.11 layer as we'll get called back to reclaim
860 * node state and potentially want to use them
861 * o to cleanup the tx queues the hal is called, so detach
862 * it last
863 * XXX: ??? detach ath5k_hw ???
864 * Other than that, it's straightforward...
865 */
866 ieee80211_unregister_hw(hw);
867 ath5k_desc_free(sc, pdev);
868 ath5k_txq_release(sc);
869 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
870 ath5k_unregister_leds(sc);
871
872 /*
873 * NB: can't reclaim these until after ieee80211_ifdetach
874 * returns because we'll get called back to reclaim node
875 * state and potentially want to use them.
876 */
877 }
878
879
880
881
882 /********************\
883 * Channel/mode setup *
884 \********************/
885
886 /*
887 * Convert IEEE channel number to MHz frequency.
888 */
889 static inline short
890 ath5k_ieee2mhz(short chan)
891 {
892 if (chan <= 14 || chan >= 27)
893 return ieee80211chan2mhz(chan);
894 else
895 return 2212 + chan * 20;
896 }
897
898 /*
899 * Returns true for the channel numbers used without all_channels modparam.
900 */
901 static bool ath5k_is_standard_channel(short chan)
902 {
903 return ((chan <= 14) ||
904 /* UNII 1,2 */
905 ((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
906 /* midband */
907 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
908 /* UNII-3 */
909 ((chan & 3) == 1 && chan >= 149 && chan <= 165));
910 }
911
912 static unsigned int
913 ath5k_copy_channels(struct ath5k_hw *ah,
914 struct ieee80211_channel *channels,
915 unsigned int mode,
916 unsigned int max)
917 {
918 unsigned int i, count, size, chfreq, freq, ch;
919
920 if (!test_bit(mode, ah->ah_modes))
921 return 0;
922
923 switch (mode) {
924 case AR5K_MODE_11A:
925 case AR5K_MODE_11A_TURBO:
926 /* 1..220, but 2GHz frequencies are filtered by check_channel */
927 size = 220 ;
928 chfreq = CHANNEL_5GHZ;
929 break;
930 case AR5K_MODE_11B:
931 case AR5K_MODE_11G:
932 case AR5K_MODE_11G_TURBO:
933 size = 26;
934 chfreq = CHANNEL_2GHZ;
935 break;
936 default:
937 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
938 return 0;
939 }
940
941 for (i = 0, count = 0; i < size && max > 0; i++) {
942 ch = i + 1 ;
943 freq = ath5k_ieee2mhz(ch);
944
945 /* Check if channel is supported by the chipset */
946 if (!ath5k_channel_ok(ah, freq, chfreq))
947 continue;
948
949 if (!modparam_all_channels && !ath5k_is_standard_channel(ch))
950 continue;
951
952 /* Write channel info and increment counter */
953 channels[count].center_freq = freq;
954 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
955 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
956 switch (mode) {
957 case AR5K_MODE_11A:
958 case AR5K_MODE_11G:
959 channels[count].hw_value = chfreq | CHANNEL_OFDM;
960 break;
961 case AR5K_MODE_11A_TURBO:
962 case AR5K_MODE_11G_TURBO:
963 channels[count].hw_value = chfreq |
964 CHANNEL_OFDM | CHANNEL_TURBO;
965 break;
966 case AR5K_MODE_11B:
967 channels[count].hw_value = CHANNEL_B;
968 }
969
970 count++;
971 max--;
972 }
973
974 return count;
975 }
976
977 static void
978 ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
979 {
980 u8 i;
981
982 for (i = 0; i < AR5K_MAX_RATES; i++)
983 sc->rate_idx[b->band][i] = -1;
984
985 for (i = 0; i < b->n_bitrates; i++) {
986 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
987 if (b->bitrates[i].hw_value_short)
988 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
989 }
990 }
991
992 static int
993 ath5k_setup_bands(struct ieee80211_hw *hw)
994 {
995 struct ath5k_softc *sc = hw->priv;
996 struct ath5k_hw *ah = sc->ah;
997 struct ieee80211_supported_band *sband;
998 int max_c, count_c = 0;
999 int i;
1000
1001 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
1002 max_c = ARRAY_SIZE(sc->channels);
1003
1004 /* 2GHz band */
1005 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
1006 sband->band = IEEE80211_BAND_2GHZ;
1007 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
1008
1009 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
1010 /* G mode */
1011 memcpy(sband->bitrates, &ath5k_rates[0],
1012 sizeof(struct ieee80211_rate) * 12);
1013 sband->n_bitrates = 12;
1014
1015 sband->channels = sc->channels;
1016 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1017 AR5K_MODE_11G, max_c);
1018
1019 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1020 count_c = sband->n_channels;
1021 max_c -= count_c;
1022 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
1023 /* B mode */
1024 memcpy(sband->bitrates, &ath5k_rates[0],
1025 sizeof(struct ieee80211_rate) * 4);
1026 sband->n_bitrates = 4;
1027
1028 /* 5211 only supports B rates and uses 4bit rate codes
1029 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
1030 * fix them up here:
1031 */
1032 if (ah->ah_version == AR5K_AR5211) {
1033 for (i = 0; i < 4; i++) {
1034 sband->bitrates[i].hw_value =
1035 sband->bitrates[i].hw_value & 0xF;
1036 sband->bitrates[i].hw_value_short =
1037 sband->bitrates[i].hw_value_short & 0xF;
1038 }
1039 }
1040
1041 sband->channels = sc->channels;
1042 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1043 AR5K_MODE_11B, max_c);
1044
1045 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1046 count_c = sband->n_channels;
1047 max_c -= count_c;
1048 }
1049 ath5k_setup_rate_idx(sc, sband);
1050
1051 /* 5GHz band, A mode */
1052 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
1053 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
1054 sband->band = IEEE80211_BAND_5GHZ;
1055 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
1056
1057 memcpy(sband->bitrates, &ath5k_rates[4],
1058 sizeof(struct ieee80211_rate) * 8);
1059 sband->n_bitrates = 8;
1060
1061 sband->channels = &sc->channels[count_c];
1062 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1063 AR5K_MODE_11A, max_c);
1064
1065 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1066 }
1067 ath5k_setup_rate_idx(sc, sband);
1068
1069 ath5k_debug_dump_bands(sc);
1070
1071 return 0;
1072 }
1073
1074 /*
1075 * Set/change channels. If the channel is really being changed,
1076 * it's done by reseting the chip. To accomplish this we must
1077 * first cleanup any pending DMA, then restart stuff after a la
1078 * ath5k_init.
1079 *
1080 * Called with sc->lock.
1081 */
1082 static int
1083 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1084 {
1085 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1086 sc->curchan->center_freq, chan->center_freq);
1087
1088 if (chan->center_freq != sc->curchan->center_freq ||
1089 chan->hw_value != sc->curchan->hw_value) {
1090
1091 /*
1092 * To switch channels clear any pending DMA operations;
1093 * wait long enough for the RX fifo to drain, reset the
1094 * hardware at the new frequency, and then re-enable
1095 * the relevant bits of the h/w.
1096 */
1097 return ath5k_reset(sc, chan);
1098 }
1099
1100 return 0;
1101 }
1102
1103 static void
1104 ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1105 {
1106 sc->curmode = mode;
1107
1108 if (mode == AR5K_MODE_11A) {
1109 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1110 } else {
1111 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1112 }
1113 }
1114
1115 static void
1116 ath5k_mode_setup(struct ath5k_softc *sc)
1117 {
1118 struct ath5k_hw *ah = sc->ah;
1119 u32 rfilt;
1120
1121 /* configure rx filter */
1122 rfilt = sc->filter_flags;
1123 ath5k_hw_set_rx_filter(ah, rfilt);
1124
1125 if (ath5k_hw_hasbssidmask(ah))
1126 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1127
1128 /* configure operational mode */
1129 ath5k_hw_set_opmode(ah);
1130
1131 ath5k_hw_set_mcast_filter(ah, 0, 0);
1132 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1133 }
1134
1135 static inline int
1136 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1137 {
1138 int rix;
1139
1140 /* return base rate on errors */
1141 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
1142 "hw_rix out of bounds: %x\n", hw_rix))
1143 return 0;
1144
1145 rix = sc->rate_idx[sc->curband->band][hw_rix];
1146 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
1147 rix = 0;
1148
1149 return rix;
1150 }
1151
1152 /***************\
1153 * Buffers setup *
1154 \***************/
1155
1156 static
1157 struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
1158 {
1159 struct sk_buff *skb;
1160 unsigned int off;
1161
1162 /*
1163 * Allocate buffer with headroom_needed space for the
1164 * fake physical layer header at the start.
1165 */
1166 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1167
1168 if (!skb) {
1169 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1170 sc->rxbufsize + sc->cachelsz - 1);
1171 return NULL;
1172 }
1173 /*
1174 * Cache-line-align. This is important (for the
1175 * 5210 at least) as not doing so causes bogus data
1176 * in rx'd frames.
1177 */
1178 off = ((unsigned long)skb->data) % sc->cachelsz;
1179 if (off != 0)
1180 skb_reserve(skb, sc->cachelsz - off);
1181
1182 *skb_addr = pci_map_single(sc->pdev,
1183 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
1184 if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
1185 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1186 dev_kfree_skb(skb);
1187 return NULL;
1188 }
1189 return skb;
1190 }
1191
1192 static int
1193 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1194 {
1195 struct ath5k_hw *ah = sc->ah;
1196 struct sk_buff *skb = bf->skb;
1197 struct ath5k_desc *ds;
1198
1199 if (!skb) {
1200 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
1201 if (!skb)
1202 return -ENOMEM;
1203 bf->skb = skb;
1204 }
1205
1206 /*
1207 * Setup descriptors. For receive we always terminate
1208 * the descriptor list with a self-linked entry so we'll
1209 * not get overrun under high load (as can happen with a
1210 * 5212 when ANI processing enables PHY error frames).
1211 *
1212 * To insure the last descriptor is self-linked we create
1213 * each descriptor as self-linked and add it to the end. As
1214 * each additional descriptor is added the previous self-linked
1215 * entry is ``fixed'' naturally. This should be safe even
1216 * if DMA is happening. When processing RX interrupts we
1217 * never remove/process the last, self-linked, entry on the
1218 * descriptor list. This insures the hardware always has
1219 * someplace to write a new frame.
1220 */
1221 ds = bf->desc;
1222 ds->ds_link = bf->daddr; /* link to self */
1223 ds->ds_data = bf->skbaddr;
1224 ah->ah_setup_rx_desc(ah, ds,
1225 skb_tailroom(skb), /* buffer size */
1226 0);
1227
1228 if (sc->rxlink != NULL)
1229 *sc->rxlink = bf->daddr;
1230 sc->rxlink = &ds->ds_link;
1231 return 0;
1232 }
1233
1234 static int
1235 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1236 {
1237 struct ath5k_hw *ah = sc->ah;
1238 struct ath5k_txq *txq = sc->txq;
1239 struct ath5k_desc *ds = bf->desc;
1240 struct sk_buff *skb = bf->skb;
1241 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1242 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1243 struct ieee80211_rate *rate;
1244 unsigned int mrr_rate[3], mrr_tries[3];
1245 int i, ret;
1246 u16 hw_rate;
1247 u16 cts_rate = 0;
1248 u16 duration = 0;
1249 u8 rc_flags;
1250
1251 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
1252
1253 /* XXX endianness */
1254 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1255 PCI_DMA_TODEVICE);
1256
1257 rate = ieee80211_get_tx_rate(sc->hw, info);
1258
1259 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
1260 flags |= AR5K_TXDESC_NOACK;
1261
1262 rc_flags = info->control.rates[0].flags;
1263 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
1264 rate->hw_value_short : rate->hw_value;
1265
1266 pktlen = skb->len;
1267
1268 /* FIXME: If we are in g mode and rate is a CCK rate
1269 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1270 * from tx power (value is in dB units already) */
1271 if (info->control.hw_key) {
1272 keyidx = info->control.hw_key->hw_key_idx;
1273 pktlen += info->control.hw_key->icv_len;
1274 }
1275 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1276 flags |= AR5K_TXDESC_RTSENA;
1277 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1278 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
1279 sc->vif, pktlen, info));
1280 }
1281 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1282 flags |= AR5K_TXDESC_CTSENA;
1283 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1284 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
1285 sc->vif, pktlen, info));
1286 }
1287 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1288 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
1289 (sc->power_level * 2),
1290 hw_rate,
1291 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
1292 cts_rate, duration);
1293 if (ret)
1294 goto err_unmap;
1295
1296 memset(mrr_rate, 0, sizeof(mrr_rate));
1297 memset(mrr_tries, 0, sizeof(mrr_tries));
1298 for (i = 0; i < 3; i++) {
1299 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
1300 if (!rate)
1301 break;
1302
1303 mrr_rate[i] = rate->hw_value;
1304 mrr_tries[i] = info->control.rates[i + 1].count;
1305 }
1306
1307 ah->ah_setup_mrr_tx_desc(ah, ds,
1308 mrr_rate[0], mrr_tries[0],
1309 mrr_rate[1], mrr_tries[1],
1310 mrr_rate[2], mrr_tries[2]);
1311
1312 ds->ds_link = 0;
1313 ds->ds_data = bf->skbaddr;
1314
1315 spin_lock_bh(&txq->lock);
1316 list_add_tail(&bf->list, &txq->q);
1317 sc->tx_stats[txq->qnum].len++;
1318 if (txq->link == NULL) /* is this first packet? */
1319 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
1320 else /* no, so only link it */
1321 *txq->link = bf->daddr;
1322
1323 txq->link = &ds->ds_link;
1324 ath5k_hw_start_tx_dma(ah, txq->qnum);
1325 mmiowb();
1326 spin_unlock_bh(&txq->lock);
1327
1328 return 0;
1329 err_unmap:
1330 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1331 return ret;
1332 }
1333
1334 /*******************\
1335 * Descriptors setup *
1336 \*******************/
1337
1338 static int
1339 ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1340 {
1341 struct ath5k_desc *ds;
1342 struct ath5k_buf *bf;
1343 dma_addr_t da;
1344 unsigned int i;
1345 int ret;
1346
1347 /* allocate descriptors */
1348 sc->desc_len = sizeof(struct ath5k_desc) *
1349 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1350 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1351 if (sc->desc == NULL) {
1352 ATH5K_ERR(sc, "can't allocate descriptors\n");
1353 ret = -ENOMEM;
1354 goto err;
1355 }
1356 ds = sc->desc;
1357 da = sc->desc_daddr;
1358 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1359 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1360
1361 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1362 sizeof(struct ath5k_buf), GFP_KERNEL);
1363 if (bf == NULL) {
1364 ATH5K_ERR(sc, "can't allocate bufptr\n");
1365 ret = -ENOMEM;
1366 goto err_free;
1367 }
1368 sc->bufptr = bf;
1369
1370 INIT_LIST_HEAD(&sc->rxbuf);
1371 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1372 bf->desc = ds;
1373 bf->daddr = da;
1374 list_add_tail(&bf->list, &sc->rxbuf);
1375 }
1376
1377 INIT_LIST_HEAD(&sc->txbuf);
1378 sc->txbuf_len = ATH_TXBUF;
1379 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1380 da += sizeof(*ds)) {
1381 bf->desc = ds;
1382 bf->daddr = da;
1383 list_add_tail(&bf->list, &sc->txbuf);
1384 }
1385
1386 /* beacon buffer */
1387 bf->desc = ds;
1388 bf->daddr = da;
1389 sc->bbuf = bf;
1390
1391 return 0;
1392 err_free:
1393 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1394 err:
1395 sc->desc = NULL;
1396 return ret;
1397 }
1398
1399 static void
1400 ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1401 {
1402 struct ath5k_buf *bf;
1403
1404 ath5k_txbuf_free(sc, sc->bbuf);
1405 list_for_each_entry(bf, &sc->txbuf, list)
1406 ath5k_txbuf_free(sc, bf);
1407 list_for_each_entry(bf, &sc->rxbuf, list)
1408 ath5k_rxbuf_free(sc, bf);
1409
1410 /* Free memory associated with all descriptors */
1411 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1412
1413 kfree(sc->bufptr);
1414 sc->bufptr = NULL;
1415 }
1416
1417
1418
1419
1420
1421 /**************\
1422 * Queues setup *
1423 \**************/
1424
1425 static struct ath5k_txq *
1426 ath5k_txq_setup(struct ath5k_softc *sc,
1427 int qtype, int subtype)
1428 {
1429 struct ath5k_hw *ah = sc->ah;
1430 struct ath5k_txq *txq;
1431 struct ath5k_txq_info qi = {
1432 .tqi_subtype = subtype,
1433 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1434 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1435 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1436 };
1437 int qnum;
1438
1439 /*
1440 * Enable interrupts only for EOL and DESC conditions.
1441 * We mark tx descriptors to receive a DESC interrupt
1442 * when a tx queue gets deep; otherwise waiting for the
1443 * EOL to reap descriptors. Note that this is done to
1444 * reduce interrupt load and this only defers reaping
1445 * descriptors, never transmitting frames. Aside from
1446 * reducing interrupts this also permits more concurrency.
1447 * The only potential downside is if the tx queue backs
1448 * up in which case the top half of the kernel may backup
1449 * due to a lack of tx descriptors.
1450 */
1451 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1452 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1453 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1454 if (qnum < 0) {
1455 /*
1456 * NB: don't print a message, this happens
1457 * normally on parts with too few tx queues
1458 */
1459 return ERR_PTR(qnum);
1460 }
1461 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1462 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1463 qnum, ARRAY_SIZE(sc->txqs));
1464 ath5k_hw_release_tx_queue(ah, qnum);
1465 return ERR_PTR(-EINVAL);
1466 }
1467 txq = &sc->txqs[qnum];
1468 if (!txq->setup) {
1469 txq->qnum = qnum;
1470 txq->link = NULL;
1471 INIT_LIST_HEAD(&txq->q);
1472 spin_lock_init(&txq->lock);
1473 txq->setup = true;
1474 }
1475 return &sc->txqs[qnum];
1476 }
1477
1478 static int
1479 ath5k_beaconq_setup(struct ath5k_hw *ah)
1480 {
1481 struct ath5k_txq_info qi = {
1482 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1483 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1484 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1485 /* NB: for dynamic turbo, don't enable any other interrupts */
1486 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1487 };
1488
1489 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1490 }
1491
1492 static int
1493 ath5k_beaconq_config(struct ath5k_softc *sc)
1494 {
1495 struct ath5k_hw *ah = sc->ah;
1496 struct ath5k_txq_info qi;
1497 int ret;
1498
1499 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1500 if (ret)
1501 return ret;
1502 if (sc->opmode == NL80211_IFTYPE_AP ||
1503 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
1504 /*
1505 * Always burst out beacon and CAB traffic
1506 * (aifs = cwmin = cwmax = 0)
1507 */
1508 qi.tqi_aifs = 0;
1509 qi.tqi_cw_min = 0;
1510 qi.tqi_cw_max = 0;
1511 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
1512 /*
1513 * Adhoc mode; backoff between 0 and (2 * cw_min).
1514 */
1515 qi.tqi_aifs = 0;
1516 qi.tqi_cw_min = 0;
1517 qi.tqi_cw_max = 2 * ah->ah_cw_min;
1518 }
1519
1520 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1521 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1522 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1523
1524 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
1525 if (ret) {
1526 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1527 "hardware queue!\n", __func__);
1528 return ret;
1529 }
1530
1531 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1532 }
1533
1534 static void
1535 ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1536 {
1537 struct ath5k_buf *bf, *bf0;
1538
1539 /*
1540 * NB: this assumes output has been stopped and
1541 * we do not need to block ath5k_tx_tasklet
1542 */
1543 spin_lock_bh(&txq->lock);
1544 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1545 ath5k_debug_printtxbuf(sc, bf);
1546
1547 ath5k_txbuf_free(sc, bf);
1548
1549 spin_lock_bh(&sc->txbuflock);
1550 sc->tx_stats[txq->qnum].len--;
1551 list_move_tail(&bf->list, &sc->txbuf);
1552 sc->txbuf_len++;
1553 spin_unlock_bh(&sc->txbuflock);
1554 }
1555 txq->link = NULL;
1556 spin_unlock_bh(&txq->lock);
1557 }
1558
1559 /*
1560 * Drain the transmit queues and reclaim resources.
1561 */
1562 static void
1563 ath5k_txq_cleanup(struct ath5k_softc *sc)
1564 {
1565 struct ath5k_hw *ah = sc->ah;
1566 unsigned int i;
1567
1568 /* XXX return value */
1569 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1570 /* don't touch the hardware if marked invalid */
1571 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1572 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1573 ath5k_hw_get_txdp(ah, sc->bhalq));
1574 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1575 if (sc->txqs[i].setup) {
1576 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1577 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1578 "link %p\n",
1579 sc->txqs[i].qnum,
1580 ath5k_hw_get_txdp(ah,
1581 sc->txqs[i].qnum),
1582 sc->txqs[i].link);
1583 }
1584 }
1585 ieee80211_wake_queues(sc->hw); /* XXX move to callers */
1586
1587 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1588 if (sc->txqs[i].setup)
1589 ath5k_txq_drainq(sc, &sc->txqs[i]);
1590 }
1591
1592 static void
1593 ath5k_txq_release(struct ath5k_softc *sc)
1594 {
1595 struct ath5k_txq *txq = sc->txqs;
1596 unsigned int i;
1597
1598 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1599 if (txq->setup) {
1600 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1601 txq->setup = false;
1602 }
1603 }
1604
1605
1606
1607
1608 /*************\
1609 * RX Handling *
1610 \*************/
1611
1612 /*
1613 * Enable the receive h/w following a reset.
1614 */
1615 static int
1616 ath5k_rx_start(struct ath5k_softc *sc)
1617 {
1618 struct ath5k_hw *ah = sc->ah;
1619 struct ath5k_buf *bf;
1620 int ret;
1621
1622 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1623
1624 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1625 sc->cachelsz, sc->rxbufsize);
1626
1627 spin_lock_bh(&sc->rxbuflock);
1628 sc->rxlink = NULL;
1629 list_for_each_entry(bf, &sc->rxbuf, list) {
1630 ret = ath5k_rxbuf_setup(sc, bf);
1631 if (ret != 0) {
1632 spin_unlock_bh(&sc->rxbuflock);
1633 goto err;
1634 }
1635 }
1636 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1637 ath5k_hw_set_rxdp(ah, bf->daddr);
1638 spin_unlock_bh(&sc->rxbuflock);
1639
1640 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
1641 ath5k_mode_setup(sc); /* set filters, etc. */
1642 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1643
1644 return 0;
1645 err:
1646 return ret;
1647 }
1648
1649 /*
1650 * Disable the receive h/w in preparation for a reset.
1651 */
1652 static void
1653 ath5k_rx_stop(struct ath5k_softc *sc)
1654 {
1655 struct ath5k_hw *ah = sc->ah;
1656
1657 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
1658 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1659 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
1660
1661 ath5k_debug_printrxbuffs(sc, ah);
1662
1663 sc->rxlink = NULL; /* just in case */
1664 }
1665
1666 static unsigned int
1667 ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
1668 struct sk_buff *skb, struct ath5k_rx_status *rs)
1669 {
1670 struct ieee80211_hdr *hdr = (void *)skb->data;
1671 unsigned int keyix, hlen;
1672
1673 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1674 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1675 return RX_FLAG_DECRYPTED;
1676
1677 /* Apparently when a default key is used to decrypt the packet
1678 the hw does not set the index used to decrypt. In such cases
1679 get the index from the packet. */
1680 hlen = ieee80211_hdrlen(hdr->frame_control);
1681 if (ieee80211_has_protected(hdr->frame_control) &&
1682 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1683 skb->len >= hlen + 4) {
1684 keyix = skb->data[hlen + 3] >> 6;
1685
1686 if (test_bit(keyix, sc->keymap))
1687 return RX_FLAG_DECRYPTED;
1688 }
1689
1690 return 0;
1691 }
1692
1693
1694 static void
1695 ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1696 struct ieee80211_rx_status *rxs)
1697 {
1698 u64 tsf, bc_tstamp;
1699 u32 hw_tu;
1700 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1701
1702 if (ieee80211_is_beacon(mgmt->frame_control) &&
1703 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1704 memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1705 /*
1706 * Received an IBSS beacon with the same BSSID. Hardware *must*
1707 * have updated the local TSF. We have to work around various
1708 * hardware bugs, though...
1709 */
1710 tsf = ath5k_hw_get_tsf64(sc->ah);
1711 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1712 hw_tu = TSF_TO_TU(tsf);
1713
1714 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1715 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1716 (unsigned long long)bc_tstamp,
1717 (unsigned long long)rxs->mactime,
1718 (unsigned long long)(rxs->mactime - bc_tstamp),
1719 (unsigned long long)tsf);
1720
1721 /*
1722 * Sometimes the HW will give us a wrong tstamp in the rx
1723 * status, causing the timestamp extension to go wrong.
1724 * (This seems to happen especially with beacon frames bigger
1725 * than 78 byte (incl. FCS))
1726 * But we know that the receive timestamp must be later than the
1727 * timestamp of the beacon since HW must have synced to that.
1728 *
1729 * NOTE: here we assume mactime to be after the frame was
1730 * received, not like mac80211 which defines it at the start.
1731 */
1732 if (bc_tstamp > rxs->mactime) {
1733 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1734 "fixing mactime from %llx to %llx\n",
1735 (unsigned long long)rxs->mactime,
1736 (unsigned long long)tsf);
1737 rxs->mactime = tsf;
1738 }
1739
1740 /*
1741 * Local TSF might have moved higher than our beacon timers,
1742 * in that case we have to update them to continue sending
1743 * beacons. This also takes care of synchronizing beacon sending
1744 * times with other stations.
1745 */
1746 if (hw_tu >= sc->nexttbtt)
1747 ath5k_beacon_update_timers(sc, bc_tstamp);
1748 }
1749 }
1750
1751 static void
1752 ath5k_tasklet_rx(unsigned long data)
1753 {
1754 struct ieee80211_rx_status rxs = {};
1755 struct ath5k_rx_status rs = {};
1756 struct sk_buff *skb, *next_skb;
1757 dma_addr_t next_skb_addr;
1758 struct ath5k_softc *sc = (void *)data;
1759 struct ath5k_buf *bf;
1760 struct ath5k_desc *ds;
1761 int ret;
1762 int hdrlen;
1763 int padsize;
1764
1765 spin_lock(&sc->rxbuflock);
1766 if (list_empty(&sc->rxbuf)) {
1767 ATH5K_WARN(sc, "empty rx buf pool\n");
1768 goto unlock;
1769 }
1770 do {
1771 rxs.flag = 0;
1772
1773 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1774 BUG_ON(bf->skb == NULL);
1775 skb = bf->skb;
1776 ds = bf->desc;
1777
1778 /* bail if HW is still using self-linked descriptor */
1779 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
1780 break;
1781
1782 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1783 if (unlikely(ret == -EINPROGRESS))
1784 break;
1785 else if (unlikely(ret)) {
1786 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1787 spin_unlock(&sc->rxbuflock);
1788 return;
1789 }
1790
1791 if (unlikely(rs.rs_more)) {
1792 ATH5K_WARN(sc, "unsupported jumbo\n");
1793 goto next;
1794 }
1795
1796 if (unlikely(rs.rs_status)) {
1797 if (rs.rs_status & AR5K_RXERR_PHY)
1798 goto next;
1799 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
1800 /*
1801 * Decrypt error. If the error occurred
1802 * because there was no hardware key, then
1803 * let the frame through so the upper layers
1804 * can process it. This is necessary for 5210
1805 * parts which have no way to setup a ``clear''
1806 * key cache entry.
1807 *
1808 * XXX do key cache faulting
1809 */
1810 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1811 !(rs.rs_status & AR5K_RXERR_CRC))
1812 goto accept;
1813 }
1814 if (rs.rs_status & AR5K_RXERR_MIC) {
1815 rxs.flag |= RX_FLAG_MMIC_ERROR;
1816 goto accept;
1817 }
1818
1819 /* let crypto-error packets fall through in MNTR */
1820 if ((rs.rs_status &
1821 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
1822 sc->opmode != NL80211_IFTYPE_MONITOR)
1823 goto next;
1824 }
1825 accept:
1826 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
1827
1828 /*
1829 * If we can't replace bf->skb with a new skb under memory
1830 * pressure, just skip this packet
1831 */
1832 if (!next_skb)
1833 goto next;
1834
1835 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1836 PCI_DMA_FROMDEVICE);
1837 skb_put(skb, rs.rs_datalen);
1838
1839 /* The MAC header is padded to have 32-bit boundary if the
1840 * packet payload is non-zero. The general calculation for
1841 * padsize would take into account odd header lengths:
1842 * padsize = (4 - hdrlen % 4) % 4; However, since only
1843 * even-length headers are used, padding can only be 0 or 2
1844 * bytes and we can optimize this a bit. In addition, we must
1845 * not try to remove padding from short control frames that do
1846 * not have payload. */
1847 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1848 padsize = ath5k_pad_size(hdrlen);
1849 if (padsize) {
1850 memmove(skb->data + padsize, skb->data, hdrlen);
1851 skb_pull(skb, padsize);
1852 }
1853
1854 /*
1855 * always extend the mac timestamp, since this information is
1856 * also needed for proper IBSS merging.
1857 *
1858 * XXX: it might be too late to do it here, since rs_tstamp is
1859 * 15bit only. that means TSF extension has to be done within
1860 * 32768usec (about 32ms). it might be necessary to move this to
1861 * the interrupt handler, like it is done in madwifi.
1862 *
1863 * Unfortunately we don't know when the hardware takes the rx
1864 * timestamp (beginning of phy frame, data frame, end of rx?).
1865 * The only thing we know is that it is hardware specific...
1866 * On AR5213 it seems the rx timestamp is at the end of the
1867 * frame, but i'm not sure.
1868 *
1869 * NOTE: mac80211 defines mactime at the beginning of the first
1870 * data symbol. Since we don't have any time references it's
1871 * impossible to comply to that. This affects IBSS merge only
1872 * right now, so it's not too bad...
1873 */
1874 rxs.mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
1875 rxs.flag |= RX_FLAG_TSFT;
1876
1877 rxs.freq = sc->curchan->center_freq;
1878 rxs.band = sc->curband->band;
1879
1880 rxs.noise = sc->ah->ah_noise_floor;
1881 rxs.signal = rxs.noise + rs.rs_rssi;
1882
1883 /* An rssi of 35 indicates you should be able use
1884 * 54 Mbps reliably. A more elaborate scheme can be used
1885 * here but it requires a map of SNR/throughput for each
1886 * possible mode used */
1887 rxs.qual = rs.rs_rssi * 100 / 35;
1888
1889 /* rssi can be more than 35 though, anything above that
1890 * should be considered at 100% */
1891 if (rxs.qual > 100)
1892 rxs.qual = 100;
1893
1894 rxs.antenna = rs.rs_antenna;
1895 rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1896 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
1897
1898 if (rxs.rate_idx >= 0 && rs.rs_rate ==
1899 sc->curband->bitrates[rxs.rate_idx].hw_value_short)
1900 rxs.flag |= RX_FLAG_SHORTPRE;
1901
1902 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1903
1904 /* check beacons in IBSS mode */
1905 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1906 ath5k_check_ibss_tsf(sc, skb, &rxs);
1907
1908 memcpy(IEEE80211_SKB_RXCB(skb), &rxs, sizeof(rxs));
1909 ieee80211_rx(sc->hw, skb);
1910
1911 bf->skb = next_skb;
1912 bf->skbaddr = next_skb_addr;
1913 next:
1914 list_move_tail(&bf->list, &sc->rxbuf);
1915 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1916 unlock:
1917 spin_unlock(&sc->rxbuflock);
1918 }
1919
1920
1921
1922
1923 /*************\
1924 * TX Handling *
1925 \*************/
1926
1927 static void
1928 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1929 {
1930 struct ath5k_tx_status ts = {};
1931 struct ath5k_buf *bf, *bf0;
1932 struct ath5k_desc *ds;
1933 struct sk_buff *skb;
1934 struct ieee80211_tx_info *info;
1935 int i, ret;
1936
1937 spin_lock(&txq->lock);
1938 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1939 ds = bf->desc;
1940
1941 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
1942 if (unlikely(ret == -EINPROGRESS))
1943 break;
1944 else if (unlikely(ret)) {
1945 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1946 ret, txq->qnum);
1947 break;
1948 }
1949
1950 skb = bf->skb;
1951 info = IEEE80211_SKB_CB(skb);
1952 bf->skb = NULL;
1953
1954 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1955 PCI_DMA_TODEVICE);
1956
1957 ieee80211_tx_info_clear_status(info);
1958 for (i = 0; i < 4; i++) {
1959 struct ieee80211_tx_rate *r =
1960 &info->status.rates[i];
1961
1962 if (ts.ts_rate[i]) {
1963 r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
1964 r->count = ts.ts_retry[i];
1965 } else {
1966 r->idx = -1;
1967 r->count = 0;
1968 }
1969 }
1970
1971 /* count the successful attempt as well */
1972 info->status.rates[ts.ts_final_idx].count++;
1973
1974 if (unlikely(ts.ts_status)) {
1975 sc->ll_stats.dot11ACKFailureCount++;
1976 if (ts.ts_status & AR5K_TXERR_FILT)
1977 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1978 } else {
1979 info->flags |= IEEE80211_TX_STAT_ACK;
1980 info->status.ack_signal = ts.ts_rssi;
1981 }
1982
1983 ieee80211_tx_status(sc->hw, skb);
1984 sc->tx_stats[txq->qnum].count++;
1985
1986 spin_lock(&sc->txbuflock);
1987 sc->tx_stats[txq->qnum].len--;
1988 list_move_tail(&bf->list, &sc->txbuf);
1989 sc->txbuf_len++;
1990 spin_unlock(&sc->txbuflock);
1991 }
1992 if (likely(list_empty(&txq->q)))
1993 txq->link = NULL;
1994 spin_unlock(&txq->lock);
1995 if (sc->txbuf_len > ATH_TXBUF / 5)
1996 ieee80211_wake_queues(sc->hw);
1997 }
1998
1999 static void
2000 ath5k_tasklet_tx(unsigned long data)
2001 {
2002 struct ath5k_softc *sc = (void *)data;
2003
2004 ath5k_tx_processq(sc, sc->txq);
2005 }
2006
2007
2008 /*****************\
2009 * Beacon handling *
2010 \*****************/
2011
2012 /*
2013 * Setup the beacon frame for transmit.
2014 */
2015 static int
2016 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
2017 {
2018 struct sk_buff *skb = bf->skb;
2019 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2020 struct ath5k_hw *ah = sc->ah;
2021 struct ath5k_desc *ds;
2022 int ret = 0;
2023 u8 antenna;
2024 u32 flags;
2025
2026 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
2027 PCI_DMA_TODEVICE);
2028 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
2029 "skbaddr %llx\n", skb, skb->data, skb->len,
2030 (unsigned long long)bf->skbaddr);
2031 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
2032 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
2033 return -EIO;
2034 }
2035
2036 ds = bf->desc;
2037 antenna = ah->ah_tx_ant;
2038
2039 flags = AR5K_TXDESC_NOACK;
2040 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
2041 ds->ds_link = bf->daddr; /* self-linked */
2042 flags |= AR5K_TXDESC_VEOL;
2043 } else
2044 ds->ds_link = 0;
2045
2046 /*
2047 * If we use multiple antennas on AP and use
2048 * the Sectored AP scenario, switch antenna every
2049 * 4 beacons to make sure everybody hears our AP.
2050 * When a client tries to associate, hw will keep
2051 * track of the tx antenna to be used for this client
2052 * automaticaly, based on ACKed packets.
2053 *
2054 * Note: AP still listens and transmits RTS on the
2055 * default antenna which is supposed to be an omni.
2056 *
2057 * Note2: On sectored scenarios it's possible to have
2058 * multiple antennas (1omni -the default- and 14 sectors)
2059 * so if we choose to actually support this mode we need
2060 * to allow user to set how many antennas we have and tweak
2061 * the code below to send beacons on all of them.
2062 */
2063 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
2064 antenna = sc->bsent & 4 ? 2 : 1;
2065
2066
2067 /* FIXME: If we are in g mode and rate is a CCK rate
2068 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
2069 * from tx power (value is in dB units already) */
2070 ds->ds_data = bf->skbaddr;
2071 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
2072 ieee80211_get_hdrlen_from_skb(skb),
2073 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
2074 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2075 1, AR5K_TXKEYIX_INVALID,
2076 antenna, flags, 0, 0);
2077 if (ret)
2078 goto err_unmap;
2079
2080 return 0;
2081 err_unmap:
2082 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
2083 return ret;
2084 }
2085
2086 static void ath5k_beacon_disable(struct ath5k_softc *sc)
2087 {
2088 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2089 ath5k_hw_set_imr(sc->ah, sc->imask);
2090 ath5k_hw_stop_tx_dma(sc->ah, sc->bhalq);
2091 }
2092
2093 /*
2094 * Transmit a beacon frame at SWBA. Dynamic updates to the
2095 * frame contents are done as needed and the slot time is
2096 * also adjusted based on current state.
2097 *
2098 * This is called from software irq context (beacontq or restq
2099 * tasklets) or user context from ath5k_beacon_config.
2100 */
2101 static void
2102 ath5k_beacon_send(struct ath5k_softc *sc)
2103 {
2104 struct ath5k_buf *bf = sc->bbuf;
2105 struct ath5k_hw *ah = sc->ah;
2106
2107 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
2108
2109 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
2110 sc->opmode == NL80211_IFTYPE_MONITOR)) {
2111 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2112 return;
2113 }
2114 /*
2115 * Check if the previous beacon has gone out. If
2116 * not don't don't try to post another, skip this
2117 * period and wait for the next. Missed beacons
2118 * indicate a problem and should not occur. If we
2119 * miss too many consecutive beacons reset the device.
2120 */
2121 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2122 sc->bmisscount++;
2123 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2124 "missed %u consecutive beacons\n", sc->bmisscount);
2125 if (sc->bmisscount > 10) { /* NB: 10 is a guess */
2126 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2127 "stuck beacon time (%u missed)\n",
2128 sc->bmisscount);
2129 tasklet_schedule(&sc->restq);
2130 }
2131 return;
2132 }
2133 if (unlikely(sc->bmisscount != 0)) {
2134 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2135 "resume beacon xmit after %u misses\n",
2136 sc->bmisscount);
2137 sc->bmisscount = 0;
2138 }
2139
2140 /*
2141 * Stop any current dma and put the new frame on the queue.
2142 * This should never fail since we check above that no frames
2143 * are still pending on the queue.
2144 */
2145 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2146 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
2147 /* NB: hw still stops DMA, so proceed */
2148 }
2149
2150 /* refresh the beacon for AP mode */
2151 if (sc->opmode == NL80211_IFTYPE_AP)
2152 ath5k_beacon_update(sc->hw, sc->vif);
2153
2154 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
2155 ath5k_hw_start_tx_dma(ah, sc->bhalq);
2156 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
2157 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2158
2159 sc->bsent++;
2160 }
2161
2162
2163 /**
2164 * ath5k_beacon_update_timers - update beacon timers
2165 *
2166 * @sc: struct ath5k_softc pointer we are operating on
2167 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2168 * beacon timer update based on the current HW TSF.
2169 *
2170 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2171 * of a received beacon or the current local hardware TSF and write it to the
2172 * beacon timer registers.
2173 *
2174 * This is called in a variety of situations, e.g. when a beacon is received,
2175 * when a TSF update has been detected, but also when an new IBSS is created or
2176 * when we otherwise know we have to update the timers, but we keep it in this
2177 * function to have it all together in one place.
2178 */
2179 static void
2180 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
2181 {
2182 struct ath5k_hw *ah = sc->ah;
2183 u32 nexttbtt, intval, hw_tu, bc_tu;
2184 u64 hw_tsf;
2185
2186 intval = sc->bintval & AR5K_BEACON_PERIOD;
2187 if (WARN_ON(!intval))
2188 return;
2189
2190 /* beacon TSF converted to TU */
2191 bc_tu = TSF_TO_TU(bc_tsf);
2192
2193 /* current TSF converted to TU */
2194 hw_tsf = ath5k_hw_get_tsf64(ah);
2195 hw_tu = TSF_TO_TU(hw_tsf);
2196
2197 #define FUDGE 3
2198 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2199 if (bc_tsf == -1) {
2200 /*
2201 * no beacons received, called internally.
2202 * just need to refresh timers based on HW TSF.
2203 */
2204 nexttbtt = roundup(hw_tu + FUDGE, intval);
2205 } else if (bc_tsf == 0) {
2206 /*
2207 * no beacon received, probably called by ath5k_reset_tsf().
2208 * reset TSF to start with 0.
2209 */
2210 nexttbtt = intval;
2211 intval |= AR5K_BEACON_RESET_TSF;
2212 } else if (bc_tsf > hw_tsf) {
2213 /*
2214 * beacon received, SW merge happend but HW TSF not yet updated.
2215 * not possible to reconfigure timers yet, but next time we
2216 * receive a beacon with the same BSSID, the hardware will
2217 * automatically update the TSF and then we need to reconfigure
2218 * the timers.
2219 */
2220 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2221 "need to wait for HW TSF sync\n");
2222 return;
2223 } else {
2224 /*
2225 * most important case for beacon synchronization between STA.
2226 *
2227 * beacon received and HW TSF has been already updated by HW.
2228 * update next TBTT based on the TSF of the beacon, but make
2229 * sure it is ahead of our local TSF timer.
2230 */
2231 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2232 }
2233 #undef FUDGE
2234
2235 sc->nexttbtt = nexttbtt;
2236
2237 intval |= AR5K_BEACON_ENA;
2238 ath5k_hw_init_beacon(ah, nexttbtt, intval);
2239
2240 /*
2241 * debugging output last in order to preserve the time critical aspect
2242 * of this function
2243 */
2244 if (bc_tsf == -1)
2245 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2246 "reconfigured timers based on HW TSF\n");
2247 else if (bc_tsf == 0)
2248 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2249 "reset HW TSF and timers\n");
2250 else
2251 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2252 "updated timers based on beacon TSF\n");
2253
2254 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2255 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2256 (unsigned long long) bc_tsf,
2257 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2258 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2259 intval & AR5K_BEACON_PERIOD,
2260 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2261 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2262 }
2263
2264
2265 /**
2266 * ath5k_beacon_config - Configure the beacon queues and interrupts
2267 *
2268 * @sc: struct ath5k_softc pointer we are operating on
2269 *
2270 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2271 * interrupts to detect TSF updates only.
2272 */
2273 static void
2274 ath5k_beacon_config(struct ath5k_softc *sc)
2275 {
2276 struct ath5k_hw *ah = sc->ah;
2277 unsigned long flags;
2278
2279 ath5k_hw_set_imr(ah, 0);
2280 sc->bmisscount = 0;
2281 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2282
2283 if (sc->opmode == NL80211_IFTYPE_ADHOC ||
2284 sc->opmode == NL80211_IFTYPE_MESH_POINT ||
2285 sc->opmode == NL80211_IFTYPE_AP) {
2286 /*
2287 * In IBSS mode we use a self-linked tx descriptor and let the
2288 * hardware send the beacons automatically. We have to load it
2289 * only once here.
2290 * We use the SWBA interrupt only to keep track of the beacon
2291 * timers in order to detect automatic TSF updates.
2292 */
2293 ath5k_beaconq_config(sc);
2294
2295 sc->imask |= AR5K_INT_SWBA;
2296
2297 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2298 if (ath5k_hw_hasveol(ah)) {
2299 spin_lock_irqsave(&sc->block, flags);
2300 ath5k_beacon_send(sc);
2301 spin_unlock_irqrestore(&sc->block, flags);
2302 }
2303 } else
2304 ath5k_beacon_update_timers(sc, -1);
2305 }
2306
2307 ath5k_hw_set_imr(ah, sc->imask);
2308 }
2309
2310 static void ath5k_tasklet_beacon(unsigned long data)
2311 {
2312 struct ath5k_softc *sc = (struct ath5k_softc *) data;
2313
2314 /*
2315 * Software beacon alert--time to send a beacon.
2316 *
2317 * In IBSS mode we use this interrupt just to
2318 * keep track of the next TBTT (target beacon
2319 * transmission time) in order to detect wether
2320 * automatic TSF updates happened.
2321 */
2322 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2323 /* XXX: only if VEOL suppported */
2324 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
2325 sc->nexttbtt += sc->bintval;
2326 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2327 "SWBA nexttbtt: %x hw_tu: %x "
2328 "TSF: %llx\n",
2329 sc->nexttbtt,
2330 TSF_TO_TU(tsf),
2331 (unsigned long long) tsf);
2332 } else {
2333 spin_lock(&sc->block);
2334 ath5k_beacon_send(sc);
2335 spin_unlock(&sc->block);
2336 }
2337 }
2338
2339
2340 /********************\
2341 * Interrupt handling *
2342 \********************/
2343
2344 static int
2345 ath5k_init(struct ath5k_softc *sc)
2346 {
2347 struct ath5k_hw *ah = sc->ah;
2348 int ret, i;
2349
2350 mutex_lock(&sc->lock);
2351
2352 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2353
2354 /*
2355 * Stop anything previously setup. This is safe
2356 * no matter this is the first time through or not.
2357 */
2358 ath5k_stop_locked(sc);
2359
2360 /*
2361 * The basic interface to setting the hardware in a good
2362 * state is ``reset''. On return the hardware is known to
2363 * be powered up and with interrupts disabled. This must
2364 * be followed by initialization of the appropriate bits
2365 * and then setup of the interrupt mask.
2366 */
2367 sc->curchan = sc->hw->conf.channel;
2368 sc->curband = &sc->sbands[sc->curchan->band];
2369 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2370 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2371 AR5K_INT_FATAL | AR5K_INT_GLOBAL;
2372 ret = ath5k_reset(sc, NULL);
2373 if (ret)
2374 goto done;
2375
2376 ath5k_rfkill_hw_start(ah);
2377
2378 /*
2379 * Reset the key cache since some parts do not reset the
2380 * contents on initial power up or resume from suspend.
2381 */
2382 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
2383 ath5k_hw_reset_key(ah, i);
2384
2385 /* Set ack to be sent at low bit-rates */
2386 ath5k_hw_set_ack_bitrate_high(ah, false);
2387
2388 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2389 msecs_to_jiffies(ath5k_calinterval * 1000)));
2390
2391 ret = 0;
2392 done:
2393 mmiowb();
2394 mutex_unlock(&sc->lock);
2395 return ret;
2396 }
2397
2398 static int
2399 ath5k_stop_locked(struct ath5k_softc *sc)
2400 {
2401 struct ath5k_hw *ah = sc->ah;
2402
2403 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2404 test_bit(ATH_STAT_INVALID, sc->status));
2405
2406 /*
2407 * Shutdown the hardware and driver:
2408 * stop output from above
2409 * disable interrupts
2410 * turn off timers
2411 * turn off the radio
2412 * clear transmit machinery
2413 * clear receive machinery
2414 * drain and release tx queues
2415 * reclaim beacon resources
2416 * power down hardware
2417 *
2418 * Note that some of this work is not possible if the
2419 * hardware is gone (invalid).
2420 */
2421 ieee80211_stop_queues(sc->hw);
2422
2423 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2424 ath5k_led_off(sc);
2425 ath5k_hw_set_imr(ah, 0);
2426 synchronize_irq(sc->pdev->irq);
2427 }
2428 ath5k_txq_cleanup(sc);
2429 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2430 ath5k_rx_stop(sc);
2431 ath5k_hw_phy_disable(ah);
2432 } else
2433 sc->rxlink = NULL;
2434
2435 return 0;
2436 }
2437
2438 /*
2439 * Stop the device, grabbing the top-level lock to protect
2440 * against concurrent entry through ath5k_init (which can happen
2441 * if another thread does a system call and the thread doing the
2442 * stop is preempted).
2443 */
2444 static int
2445 ath5k_stop_hw(struct ath5k_softc *sc)
2446 {
2447 int ret;
2448
2449 mutex_lock(&sc->lock);
2450 ret = ath5k_stop_locked(sc);
2451 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2452 /*
2453 * Set the chip in full sleep mode. Note that we are
2454 * careful to do this only when bringing the interface
2455 * completely to a stop. When the chip is in this state
2456 * it must be carefully woken up or references to
2457 * registers in the PCI clock domain may freeze the bus
2458 * (and system). This varies by chip and is mostly an
2459 * issue with newer parts that go to sleep more quickly.
2460 */
2461 if (sc->ah->ah_mac_srev >= 0x78) {
2462 /*
2463 * XXX
2464 * don't put newer MAC revisions > 7.8 to sleep because
2465 * of the above mentioned problems
2466 */
2467 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2468 "not putting device to sleep\n");
2469 } else {
2470 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2471 "putting device to full sleep\n");
2472 ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2473 }
2474 }
2475 ath5k_txbuf_free(sc, sc->bbuf);
2476
2477 mmiowb();
2478 mutex_unlock(&sc->lock);
2479
2480 del_timer_sync(&sc->calib_tim);
2481 tasklet_kill(&sc->rxtq);
2482 tasklet_kill(&sc->txtq);
2483 tasklet_kill(&sc->restq);
2484 tasklet_kill(&sc->beacontq);
2485
2486 ath5k_rfkill_hw_stop(sc->ah);
2487
2488 return ret;
2489 }
2490
2491 static irqreturn_t
2492 ath5k_intr(int irq, void *dev_id)
2493 {
2494 struct ath5k_softc *sc = dev_id;
2495 struct ath5k_hw *ah = sc->ah;
2496 enum ath5k_int status;
2497 unsigned int counter = 1000;
2498
2499 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2500 !ath5k_hw_is_intr_pending(ah)))
2501 return IRQ_NONE;
2502
2503 do {
2504 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2505 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2506 status, sc->imask);
2507 if (unlikely(status & AR5K_INT_FATAL)) {
2508 /*
2509 * Fatal errors are unrecoverable.
2510 * Typically these are caused by DMA errors.
2511 */
2512 tasklet_schedule(&sc->restq);
2513 } else if (unlikely(status & AR5K_INT_RXORN)) {
2514 tasklet_schedule(&sc->restq);
2515 } else {
2516 if (status & AR5K_INT_SWBA) {
2517 tasklet_hi_schedule(&sc->beacontq);
2518 }
2519 if (status & AR5K_INT_RXEOL) {
2520 /*
2521 * NB: the hardware should re-read the link when
2522 * RXE bit is written, but it doesn't work at
2523 * least on older hardware revs.
2524 */
2525 sc->rxlink = NULL;
2526 }
2527 if (status & AR5K_INT_TXURN) {
2528 /* bump tx trigger level */
2529 ath5k_hw_update_tx_triglevel(ah, true);
2530 }
2531 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
2532 tasklet_schedule(&sc->rxtq);
2533 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2534 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
2535 tasklet_schedule(&sc->txtq);
2536 if (status & AR5K_INT_BMISS) {
2537 /* TODO */
2538 }
2539 if (status & AR5K_INT_MIB) {
2540 /*
2541 * These stats are also used for ANI i think
2542 * so how about updating them more often ?
2543 */
2544 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
2545 }
2546 if (status & AR5K_INT_GPIO)
2547 tasklet_schedule(&sc->rf_kill.toggleq);
2548
2549 }
2550 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
2551
2552 if (unlikely(!counter))
2553 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2554
2555 return IRQ_HANDLED;
2556 }
2557
2558 static void
2559 ath5k_tasklet_reset(unsigned long data)
2560 {
2561 struct ath5k_softc *sc = (void *)data;
2562
2563 ath5k_reset_wake(sc);
2564 }
2565
2566 /*
2567 * Periodically recalibrate the PHY to account
2568 * for temperature/environment changes.
2569 */
2570 static void
2571 ath5k_calibrate(unsigned long data)
2572 {
2573 struct ath5k_softc *sc = (void *)data;
2574 struct ath5k_hw *ah = sc->ah;
2575
2576 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2577 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2578 sc->curchan->hw_value);
2579
2580 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2581 /*
2582 * Rfgain is out of bounds, reset the chip
2583 * to load new gain values.
2584 */
2585 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2586 ath5k_reset_wake(sc);
2587 }
2588 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2589 ATH5K_ERR(sc, "calibration of channel %u failed\n",
2590 ieee80211_frequency_to_channel(
2591 sc->curchan->center_freq));
2592
2593 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2594 msecs_to_jiffies(ath5k_calinterval * 1000)));
2595 }
2596
2597
2598 /********************\
2599 * Mac80211 functions *
2600 \********************/
2601
2602 static int
2603 ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2604 {
2605 struct ath5k_softc *sc = hw->priv;
2606 struct ath5k_buf *bf;
2607 unsigned long flags;
2608 int hdrlen;
2609 int padsize;
2610
2611 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2612
2613 if (sc->opmode == NL80211_IFTYPE_MONITOR)
2614 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2615
2616 /*
2617 * the hardware expects the header padded to 4 byte boundaries
2618 * if this is not the case we add the padding after the header
2619 */
2620 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2621 padsize = ath5k_pad_size(hdrlen);
2622 if (padsize) {
2623
2624 if (skb_headroom(skb) < padsize) {
2625 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
2626 " headroom to pad %d\n", hdrlen, padsize);
2627 goto drop_packet;
2628 }
2629 skb_push(skb, padsize);
2630 memmove(skb->data, skb->data+padsize, hdrlen);
2631 }
2632
2633 spin_lock_irqsave(&sc->txbuflock, flags);
2634 if (list_empty(&sc->txbuf)) {
2635 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2636 spin_unlock_irqrestore(&sc->txbuflock, flags);
2637 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
2638 goto drop_packet;
2639 }
2640 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2641 list_del(&bf->list);
2642 sc->txbuf_len--;
2643 if (list_empty(&sc->txbuf))
2644 ieee80211_stop_queues(hw);
2645 spin_unlock_irqrestore(&sc->txbuflock, flags);
2646
2647 bf->skb = skb;
2648
2649 if (ath5k_txbuf_setup(sc, bf)) {
2650 bf->skb = NULL;
2651 spin_lock_irqsave(&sc->txbuflock, flags);
2652 list_add_tail(&bf->list, &sc->txbuf);
2653 sc->txbuf_len++;
2654 spin_unlock_irqrestore(&sc->txbuflock, flags);
2655 goto drop_packet;
2656 }
2657 return NETDEV_TX_OK;
2658
2659 drop_packet:
2660 dev_kfree_skb_any(skb);
2661 return NETDEV_TX_OK;
2662 }
2663
2664 /*
2665 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2666 * and change to the given channel.
2667 */
2668 static int
2669 ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan)
2670 {
2671 struct ath5k_hw *ah = sc->ah;
2672 int ret;
2673
2674 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
2675
2676 if (chan) {
2677 ath5k_hw_set_imr(ah, 0);
2678 ath5k_txq_cleanup(sc);
2679 ath5k_rx_stop(sc);
2680
2681 sc->curchan = chan;
2682 sc->curband = &sc->sbands[chan->band];
2683 }
2684 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
2685 if (ret) {
2686 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2687 goto err;
2688 }
2689
2690 ret = ath5k_rx_start(sc);
2691 if (ret) {
2692 ATH5K_ERR(sc, "can't start recv logic\n");
2693 goto err;
2694 }
2695
2696 /*
2697 * Change channels and update the h/w rate map if we're switching;
2698 * e.g. 11a to 11b/g.
2699 *
2700 * We may be doing a reset in response to an ioctl that changes the
2701 * channel so update any state that might change as a result.
2702 *
2703 * XXX needed?
2704 */
2705 /* ath5k_chan_change(sc, c); */
2706
2707 ath5k_beacon_config(sc);
2708 /* intrs are enabled by ath5k_beacon_config */
2709
2710 return 0;
2711 err:
2712 return ret;
2713 }
2714
2715 static int
2716 ath5k_reset_wake(struct ath5k_softc *sc)
2717 {
2718 int ret;
2719
2720 ret = ath5k_reset(sc, sc->curchan);
2721 if (!ret)
2722 ieee80211_wake_queues(sc->hw);
2723
2724 return ret;
2725 }
2726
2727 static int ath5k_start(struct ieee80211_hw *hw)
2728 {
2729 return ath5k_init(hw->priv);
2730 }
2731
2732 static void ath5k_stop(struct ieee80211_hw *hw)
2733 {
2734 ath5k_stop_hw(hw->priv);
2735 }
2736
2737 static int ath5k_add_interface(struct ieee80211_hw *hw,
2738 struct ieee80211_if_init_conf *conf)
2739 {
2740 struct ath5k_softc *sc = hw->priv;
2741 int ret;
2742
2743 mutex_lock(&sc->lock);
2744 if (sc->vif) {
2745 ret = 0;
2746 goto end;
2747 }
2748
2749 sc->vif = conf->vif;
2750
2751 switch (conf->type) {
2752 case NL80211_IFTYPE_AP:
2753 case NL80211_IFTYPE_STATION:
2754 case NL80211_IFTYPE_ADHOC:
2755 case NL80211_IFTYPE_MESH_POINT:
2756 case NL80211_IFTYPE_MONITOR:
2757 sc->opmode = conf->type;
2758 break;
2759 default:
2760 ret = -EOPNOTSUPP;
2761 goto end;
2762 }
2763
2764 ath5k_hw_set_lladdr(sc->ah, conf->mac_addr);
2765
2766 ret = 0;
2767 end:
2768 mutex_unlock(&sc->lock);
2769 return ret;
2770 }
2771
2772 static void
2773 ath5k_remove_interface(struct ieee80211_hw *hw,
2774 struct ieee80211_if_init_conf *conf)
2775 {
2776 struct ath5k_softc *sc = hw->priv;
2777 u8 mac[ETH_ALEN] = {};
2778
2779 mutex_lock(&sc->lock);
2780 if (sc->vif != conf->vif)
2781 goto end;
2782
2783 ath5k_hw_set_lladdr(sc->ah, mac);
2784 ath5k_beacon_disable(sc);
2785 sc->vif = NULL;
2786 end:
2787 mutex_unlock(&sc->lock);
2788 }
2789
2790 /*
2791 * TODO: Phy disable/diversity etc
2792 */
2793 static int
2794 ath5k_config(struct ieee80211_hw *hw, u32 changed)
2795 {
2796 struct ath5k_softc *sc = hw->priv;
2797 struct ath5k_hw *ah = sc->ah;
2798 struct ieee80211_conf *conf = &hw->conf;
2799 int ret = 0;
2800
2801 mutex_lock(&sc->lock);
2802
2803 ret = ath5k_chan_set(sc, conf->channel);
2804 if (ret < 0)
2805 goto unlock;
2806
2807 if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
2808 (sc->power_level != conf->power_level)) {
2809 sc->power_level = conf->power_level;
2810
2811 /* Half dB steps */
2812 ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2));
2813 }
2814
2815 /* TODO:
2816 * 1) Move this on config_interface and handle each case
2817 * separately eg. when we have only one STA vif, use
2818 * AR5K_ANTMODE_SINGLE_AP
2819 *
2820 * 2) Allow the user to change antenna mode eg. when only
2821 * one antenna is present
2822 *
2823 * 3) Allow the user to set default/tx antenna when possible
2824 *
2825 * 4) Default mode should handle 90% of the cases, together
2826 * with fixed a/b and single AP modes we should be able to
2827 * handle 99%. Sectored modes are extreme cases and i still
2828 * haven't found a usage for them. If we decide to support them,
2829 * then we must allow the user to set how many tx antennas we
2830 * have available
2831 */
2832 ath5k_hw_set_antenna_mode(ah, AR5K_ANTMODE_DEFAULT);
2833
2834 unlock:
2835 mutex_unlock(&sc->lock);
2836 return ret;
2837 }
2838
2839 #define SUPPORTED_FIF_FLAGS \
2840 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2841 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2842 FIF_BCN_PRBRESP_PROMISC
2843 /*
2844 * o always accept unicast, broadcast, and multicast traffic
2845 * o multicast traffic for all BSSIDs will be enabled if mac80211
2846 * says it should be
2847 * o maintain current state of phy ofdm or phy cck error reception.
2848 * If the hardware detects any of these type of errors then
2849 * ath5k_hw_get_rx_filter() will pass to us the respective
2850 * hardware filters to be able to receive these type of frames.
2851 * o probe request frames are accepted only when operating in
2852 * hostap, adhoc, or monitor modes
2853 * o enable promiscuous mode according to the interface state
2854 * o accept beacons:
2855 * - when operating in adhoc mode so the 802.11 layer creates
2856 * node table entries for peers,
2857 * - when operating in station mode for collecting rssi data when
2858 * the station is otherwise quiet, or
2859 * - when scanning
2860 */
2861 static void ath5k_configure_filter(struct ieee80211_hw *hw,
2862 unsigned int changed_flags,
2863 unsigned int *new_flags,
2864 int mc_count, struct dev_mc_list *mclist)
2865 {
2866 struct ath5k_softc *sc = hw->priv;
2867 struct ath5k_hw *ah = sc->ah;
2868 u32 mfilt[2], val, rfilt;
2869 u8 pos;
2870 int i;
2871
2872 mfilt[0] = 0;
2873 mfilt[1] = 0;
2874
2875 /* Only deal with supported flags */
2876 changed_flags &= SUPPORTED_FIF_FLAGS;
2877 *new_flags &= SUPPORTED_FIF_FLAGS;
2878
2879 /* If HW detects any phy or radar errors, leave those filters on.
2880 * Also, always enable Unicast, Broadcasts and Multicast
2881 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2882 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2883 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2884 AR5K_RX_FILTER_MCAST);
2885
2886 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2887 if (*new_flags & FIF_PROMISC_IN_BSS) {
2888 rfilt |= AR5K_RX_FILTER_PROM;
2889 __set_bit(ATH_STAT_PROMISC, sc->status);
2890 } else {
2891 __clear_bit(ATH_STAT_PROMISC, sc->status);
2892 }
2893 }
2894
2895 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2896 if (*new_flags & FIF_ALLMULTI) {
2897 mfilt[0] = ~0;
2898 mfilt[1] = ~0;
2899 } else {
2900 for (i = 0; i < mc_count; i++) {
2901 if (!mclist)
2902 break;
2903 /* calculate XOR of eight 6-bit values */
2904 val = get_unaligned_le32(mclist->dmi_addr + 0);
2905 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2906 val = get_unaligned_le32(mclist->dmi_addr + 3);
2907 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2908 pos &= 0x3f;
2909 mfilt[pos / 32] |= (1 << (pos % 32));
2910 /* XXX: we might be able to just do this instead,
2911 * but not sure, needs testing, if we do use this we'd
2912 * neet to inform below to not reset the mcast */
2913 /* ath5k_hw_set_mcast_filterindex(ah,
2914 * mclist->dmi_addr[5]); */
2915 mclist = mclist->next;
2916 }
2917 }
2918
2919 /* This is the best we can do */
2920 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2921 rfilt |= AR5K_RX_FILTER_PHYERR;
2922
2923 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2924 * and probes for any BSSID, this needs testing */
2925 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2926 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2927
2928 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2929 * set we should only pass on control frames for this
2930 * station. This needs testing. I believe right now this
2931 * enables *all* control frames, which is OK.. but
2932 * but we should see if we can improve on granularity */
2933 if (*new_flags & FIF_CONTROL)
2934 rfilt |= AR5K_RX_FILTER_CONTROL;
2935
2936 /* Additional settings per mode -- this is per ath5k */
2937
2938 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2939
2940 if (sc->opmode == NL80211_IFTYPE_MONITOR)
2941 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2942 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
2943 if (sc->opmode != NL80211_IFTYPE_STATION)
2944 rfilt |= AR5K_RX_FILTER_PROBEREQ;
2945 if (sc->opmode != NL80211_IFTYPE_AP &&
2946 sc->opmode != NL80211_IFTYPE_MESH_POINT &&
2947 test_bit(ATH_STAT_PROMISC, sc->status))
2948 rfilt |= AR5K_RX_FILTER_PROM;
2949 if ((sc->opmode == NL80211_IFTYPE_STATION && sc->assoc) ||
2950 sc->opmode == NL80211_IFTYPE_ADHOC ||
2951 sc->opmode == NL80211_IFTYPE_AP)
2952 rfilt |= AR5K_RX_FILTER_BEACON;
2953 if (sc->opmode == NL80211_IFTYPE_MESH_POINT)
2954 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2955 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
2956
2957 /* Set filters */
2958 ath5k_hw_set_rx_filter(ah, rfilt);
2959
2960 /* Set multicast bits */
2961 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
2962 /* Set the cached hw filter flags, this will alter actually
2963 * be set in HW */
2964 sc->filter_flags = rfilt;
2965 }
2966
2967 static int
2968 ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2969 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
2970 struct ieee80211_key_conf *key)
2971 {
2972 struct ath5k_softc *sc = hw->priv;
2973 int ret = 0;
2974
2975 if (modparam_nohwcrypt)
2976 return -EOPNOTSUPP;
2977
2978 switch (key->alg) {
2979 case ALG_WEP:
2980 case ALG_TKIP:
2981 break;
2982 case ALG_CCMP:
2983 return -EOPNOTSUPP;
2984 default:
2985 WARN_ON(1);
2986 return -EINVAL;
2987 }
2988
2989 mutex_lock(&sc->lock);
2990
2991 switch (cmd) {
2992 case SET_KEY:
2993 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key,
2994 sta ? sta->addr : NULL);
2995 if (ret) {
2996 ATH5K_ERR(sc, "can't set the key\n");
2997 goto unlock;
2998 }
2999 __set_bit(key->keyidx, sc->keymap);
3000 key->hw_key_idx = key->keyidx;
3001 key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV |
3002 IEEE80211_KEY_FLAG_GENERATE_MMIC);
3003 break;
3004 case DISABLE_KEY:
3005 ath5k_hw_reset_key(sc->ah, key->keyidx);
3006 __clear_bit(key->keyidx, sc->keymap);
3007 break;
3008 default:
3009 ret = -EINVAL;
3010 goto unlock;
3011 }
3012
3013 unlock:
3014 mmiowb();
3015 mutex_unlock(&sc->lock);
3016 return ret;
3017 }
3018
3019 static int
3020 ath5k_get_stats(struct ieee80211_hw *hw,
3021 struct ieee80211_low_level_stats *stats)
3022 {
3023 struct ath5k_softc *sc = hw->priv;
3024 struct ath5k_hw *ah = sc->ah;
3025
3026 /* Force update */
3027 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
3028
3029 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
3030
3031 return 0;
3032 }
3033
3034 static int
3035 ath5k_get_tx_stats(struct ieee80211_hw *hw,
3036 struct ieee80211_tx_queue_stats *stats)
3037 {
3038 struct ath5k_softc *sc = hw->priv;
3039
3040 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
3041
3042 return 0;
3043 }
3044
3045 static u64
3046 ath5k_get_tsf(struct ieee80211_hw *hw)
3047 {
3048 struct ath5k_softc *sc = hw->priv;
3049
3050 return ath5k_hw_get_tsf64(sc->ah);
3051 }
3052
3053 static void
3054 ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3055 {
3056 struct ath5k_softc *sc = hw->priv;
3057
3058 ath5k_hw_set_tsf64(sc->ah, tsf);
3059 }
3060
3061 static void
3062 ath5k_reset_tsf(struct ieee80211_hw *hw)
3063 {
3064 struct ath5k_softc *sc = hw->priv;
3065
3066 /*
3067 * in IBSS mode we need to update the beacon timers too.
3068 * this will also reset the TSF if we call it with 0
3069 */
3070 if (sc->opmode == NL80211_IFTYPE_ADHOC)
3071 ath5k_beacon_update_timers(sc, 0);
3072 else
3073 ath5k_hw_reset_tsf(sc->ah);
3074 }
3075
3076 /*
3077 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
3078 * this is called only once at config_bss time, for AP we do it every
3079 * SWBA interrupt so that the TIM will reflect buffered frames.
3080 *
3081 * Called with the beacon lock.
3082 */
3083 static int
3084 ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
3085 {
3086 int ret;
3087 struct ath5k_softc *sc = hw->priv;
3088 struct sk_buff *skb;
3089
3090 if (WARN_ON(!vif)) {
3091 ret = -EINVAL;
3092 goto out;
3093 }
3094
3095 skb = ieee80211_beacon_get(hw, vif);
3096
3097 if (!skb) {
3098 ret = -ENOMEM;
3099 goto out;
3100 }
3101
3102 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3103
3104 ath5k_txbuf_free(sc, sc->bbuf);
3105 sc->bbuf->skb = skb;
3106 ret = ath5k_beacon_setup(sc, sc->bbuf);
3107 if (ret)
3108 sc->bbuf->skb = NULL;
3109 out:
3110 return ret;
3111 }
3112
3113 /*
3114 * Update the beacon and reconfigure the beacon queues.
3115 */
3116 static void
3117 ath5k_beacon_reconfig(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
3118 {
3119 int ret;
3120 unsigned long flags;
3121 struct ath5k_softc *sc = hw->priv;
3122
3123 spin_lock_irqsave(&sc->block, flags);
3124 ret = ath5k_beacon_update(hw, vif);
3125 spin_unlock_irqrestore(&sc->block, flags);
3126 if (ret == 0) {
3127 ath5k_beacon_config(sc);
3128 mmiowb();
3129 }
3130 }
3131
3132 static void
3133 set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3134 {
3135 struct ath5k_softc *sc = hw->priv;
3136 struct ath5k_hw *ah = sc->ah;
3137 u32 rfilt;
3138 rfilt = ath5k_hw_get_rx_filter(ah);
3139 if (enable)
3140 rfilt |= AR5K_RX_FILTER_BEACON;
3141 else
3142 rfilt &= ~AR5K_RX_FILTER_BEACON;
3143 ath5k_hw_set_rx_filter(ah, rfilt);
3144 sc->filter_flags = rfilt;
3145 }
3146
3147 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3148 struct ieee80211_vif *vif,
3149 struct ieee80211_bss_conf *bss_conf,
3150 u32 changes)
3151 {
3152 struct ath5k_softc *sc = hw->priv;
3153 struct ath5k_hw *ah = sc->ah;
3154
3155 mutex_lock(&sc->lock);
3156 if (WARN_ON(sc->vif != vif))
3157 goto unlock;
3158
3159 if (changes & BSS_CHANGED_BSSID) {
3160 /* Cache for later use during resets */
3161 memcpy(ah->ah_bssid, bss_conf->bssid, ETH_ALEN);
3162 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
3163 * a clean way of letting us retrieve this yet. */
3164 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
3165 mmiowb();
3166 }
3167
3168 if (changes & BSS_CHANGED_BEACON_INT)
3169 sc->bintval = bss_conf->beacon_int;
3170
3171 if (changes & BSS_CHANGED_ASSOC) {
3172 sc->assoc = bss_conf->assoc;
3173 if (sc->opmode == NL80211_IFTYPE_STATION)
3174 set_beacon_filter(hw, sc->assoc);
3175 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3176 AR5K_LED_ASSOC : AR5K_LED_INIT);
3177 }
3178
3179 if (changes & BSS_CHANGED_BEACON &&
3180 (vif->type == NL80211_IFTYPE_ADHOC ||
3181 vif->type == NL80211_IFTYPE_MESH_POINT ||
3182 vif->type == NL80211_IFTYPE_AP)) {
3183 ath5k_beacon_reconfig(hw, vif);
3184 }
3185
3186 unlock:
3187 mutex_unlock(&sc->lock);
3188 }
3189
3190 static void ath5k_sw_scan_start(struct ieee80211_hw *hw)
3191 {
3192 struct ath5k_softc *sc = hw->priv;
3193 if (!sc->assoc)
3194 ath5k_hw_set_ledstate(sc->ah, AR5K_LED_SCAN);
3195 }
3196
3197 static void ath5k_sw_scan_complete(struct ieee80211_hw *hw)
3198 {
3199 struct ath5k_softc *sc = hw->priv;
3200 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3201 AR5K_LED_ASSOC : AR5K_LED_INIT);
3202 }
Linux kernel - Deliverables
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