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mac80211: clarify interface iteration and make it configurable
[deliverable/linux.git] / drivers / net / wireless / ath / ath5k / base.c
1 /*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
43 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44
45 #include <linux/module.h>
46 #include <linux/delay.h>
47 #include <linux/dma-mapping.h>
48 #include <linux/hardirq.h>
49 #include <linux/if.h>
50 #include <linux/io.h>
51 #include <linux/netdevice.h>
52 #include <linux/cache.h>
53 #include <linux/ethtool.h>
54 #include <linux/uaccess.h>
55 #include <linux/slab.h>
56 #include <linux/etherdevice.h>
57 #include <linux/nl80211.h>
58
59 #include <net/ieee80211_radiotap.h>
60
61 #include <asm/unaligned.h>
62
63 #include "base.h"
64 #include "reg.h"
65 #include "debug.h"
66 #include "ani.h"
67 #include "ath5k.h"
68 #include "../regd.h"
69
70 #define CREATE_TRACE_POINTS
71 #include "trace.h"
72
73 bool ath5k_modparam_nohwcrypt;
74 module_param_named(nohwcrypt, ath5k_modparam_nohwcrypt, bool, S_IRUGO);
75 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
76
77 static bool modparam_fastchanswitch;
78 module_param_named(fastchanswitch, modparam_fastchanswitch, bool, S_IRUGO);
79 MODULE_PARM_DESC(fastchanswitch, "Enable fast channel switching for AR2413/AR5413 radios.");
80
81 static bool ath5k_modparam_no_hw_rfkill_switch;
82 module_param_named(no_hw_rfkill_switch, ath5k_modparam_no_hw_rfkill_switch,
83 bool, S_IRUGO);
84 MODULE_PARM_DESC(no_hw_rfkill_switch, "Ignore the GPIO RFKill switch state");
85
86
87 /* Module info */
88 MODULE_AUTHOR("Jiri Slaby");
89 MODULE_AUTHOR("Nick Kossifidis");
90 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
91 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
92 MODULE_LICENSE("Dual BSD/GPL");
93
94 static int ath5k_init(struct ieee80211_hw *hw);
95 static int ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan,
96 bool skip_pcu);
97
98 /* Known SREVs */
99 static const struct ath5k_srev_name srev_names[] = {
100 #ifdef CONFIG_ATHEROS_AR231X
101 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R2 },
102 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R7 },
103 { "2313", AR5K_VERSION_MAC, AR5K_SREV_AR2313_R8 },
104 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R6 },
105 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R7 },
106 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R1 },
107 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R2 },
108 #else
109 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
110 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
111 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
112 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
113 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
114 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
115 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
116 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
117 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
118 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
119 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
120 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
121 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
122 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
123 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
124 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
125 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
126 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
127 #endif
128 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
129 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
130 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
131 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
132 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
133 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
134 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
135 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
136 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
137 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
138 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
139 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
140 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
141 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
142 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
143 #ifdef CONFIG_ATHEROS_AR231X
144 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
145 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
146 #endif
147 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
148 };
149
150 static const struct ieee80211_rate ath5k_rates[] = {
151 { .bitrate = 10,
152 .hw_value = ATH5K_RATE_CODE_1M, },
153 { .bitrate = 20,
154 .hw_value = ATH5K_RATE_CODE_2M,
155 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
156 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
157 { .bitrate = 55,
158 .hw_value = ATH5K_RATE_CODE_5_5M,
159 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
160 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
161 { .bitrate = 110,
162 .hw_value = ATH5K_RATE_CODE_11M,
163 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
164 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
165 { .bitrate = 60,
166 .hw_value = ATH5K_RATE_CODE_6M,
167 .flags = 0 },
168 { .bitrate = 90,
169 .hw_value = ATH5K_RATE_CODE_9M,
170 .flags = 0 },
171 { .bitrate = 120,
172 .hw_value = ATH5K_RATE_CODE_12M,
173 .flags = 0 },
174 { .bitrate = 180,
175 .hw_value = ATH5K_RATE_CODE_18M,
176 .flags = 0 },
177 { .bitrate = 240,
178 .hw_value = ATH5K_RATE_CODE_24M,
179 .flags = 0 },
180 { .bitrate = 360,
181 .hw_value = ATH5K_RATE_CODE_36M,
182 .flags = 0 },
183 { .bitrate = 480,
184 .hw_value = ATH5K_RATE_CODE_48M,
185 .flags = 0 },
186 { .bitrate = 540,
187 .hw_value = ATH5K_RATE_CODE_54M,
188 .flags = 0 },
189 };
190
191 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
192 {
193 u64 tsf = ath5k_hw_get_tsf64(ah);
194
195 if ((tsf & 0x7fff) < rstamp)
196 tsf -= 0x8000;
197
198 return (tsf & ~0x7fff) | rstamp;
199 }
200
201 const char *
202 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
203 {
204 const char *name = "xxxxx";
205 unsigned int i;
206
207 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
208 if (srev_names[i].sr_type != type)
209 continue;
210
211 if ((val & 0xf0) == srev_names[i].sr_val)
212 name = srev_names[i].sr_name;
213
214 if ((val & 0xff) == srev_names[i].sr_val) {
215 name = srev_names[i].sr_name;
216 break;
217 }
218 }
219
220 return name;
221 }
222 static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
223 {
224 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
225 return ath5k_hw_reg_read(ah, reg_offset);
226 }
227
228 static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
229 {
230 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
231 ath5k_hw_reg_write(ah, val, reg_offset);
232 }
233
234 static const struct ath_ops ath5k_common_ops = {
235 .read = ath5k_ioread32,
236 .write = ath5k_iowrite32,
237 };
238
239 /***********************\
240 * Driver Initialization *
241 \***********************/
242
243 static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
244 {
245 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
246 struct ath5k_hw *ah = hw->priv;
247 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
248
249 return ath_reg_notifier_apply(wiphy, request, regulatory);
250 }
251
252 /********************\
253 * Channel/mode setup *
254 \********************/
255
256 /*
257 * Returns true for the channel numbers used.
258 */
259 #ifdef CONFIG_ATH5K_TEST_CHANNELS
260 static bool ath5k_is_standard_channel(short chan, enum ieee80211_band band)
261 {
262 return true;
263 }
264
265 #else
266 static bool ath5k_is_standard_channel(short chan, enum ieee80211_band band)
267 {
268 if (band == IEEE80211_BAND_2GHZ && chan <= 14)
269 return true;
270
271 return /* UNII 1,2 */
272 (((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
273 /* midband */
274 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
275 /* UNII-3 */
276 ((chan & 3) == 1 && chan >= 149 && chan <= 165) ||
277 /* 802.11j 5.030-5.080 GHz (20MHz) */
278 (chan == 8 || chan == 12 || chan == 16) ||
279 /* 802.11j 4.9GHz (20MHz) */
280 (chan == 184 || chan == 188 || chan == 192 || chan == 196));
281 }
282 #endif
283
284 static unsigned int
285 ath5k_setup_channels(struct ath5k_hw *ah, struct ieee80211_channel *channels,
286 unsigned int mode, unsigned int max)
287 {
288 unsigned int count, size, freq, ch;
289 enum ieee80211_band band;
290
291 switch (mode) {
292 case AR5K_MODE_11A:
293 /* 1..220, but 2GHz frequencies are filtered by check_channel */
294 size = 220;
295 band = IEEE80211_BAND_5GHZ;
296 break;
297 case AR5K_MODE_11B:
298 case AR5K_MODE_11G:
299 size = 26;
300 band = IEEE80211_BAND_2GHZ;
301 break;
302 default:
303 ATH5K_WARN(ah, "bad mode, not copying channels\n");
304 return 0;
305 }
306
307 count = 0;
308 for (ch = 1; ch <= size && count < max; ch++) {
309 freq = ieee80211_channel_to_frequency(ch, band);
310
311 if (freq == 0) /* mapping failed - not a standard channel */
312 continue;
313
314 /* Write channel info, needed for ath5k_channel_ok() */
315 channels[count].center_freq = freq;
316 channels[count].band = band;
317 channels[count].hw_value = mode;
318
319 /* Check if channel is supported by the chipset */
320 if (!ath5k_channel_ok(ah, &channels[count]))
321 continue;
322
323 if (!ath5k_is_standard_channel(ch, band))
324 continue;
325
326 count++;
327 }
328
329 return count;
330 }
331
332 static void
333 ath5k_setup_rate_idx(struct ath5k_hw *ah, struct ieee80211_supported_band *b)
334 {
335 u8 i;
336
337 for (i = 0; i < AR5K_MAX_RATES; i++)
338 ah->rate_idx[b->band][i] = -1;
339
340 for (i = 0; i < b->n_bitrates; i++) {
341 ah->rate_idx[b->band][b->bitrates[i].hw_value] = i;
342 if (b->bitrates[i].hw_value_short)
343 ah->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
344 }
345 }
346
347 static int
348 ath5k_setup_bands(struct ieee80211_hw *hw)
349 {
350 struct ath5k_hw *ah = hw->priv;
351 struct ieee80211_supported_band *sband;
352 int max_c, count_c = 0;
353 int i;
354
355 BUILD_BUG_ON(ARRAY_SIZE(ah->sbands) < IEEE80211_NUM_BANDS);
356 max_c = ARRAY_SIZE(ah->channels);
357
358 /* 2GHz band */
359 sband = &ah->sbands[IEEE80211_BAND_2GHZ];
360 sband->band = IEEE80211_BAND_2GHZ;
361 sband->bitrates = &ah->rates[IEEE80211_BAND_2GHZ][0];
362
363 if (test_bit(AR5K_MODE_11G, ah->ah_capabilities.cap_mode)) {
364 /* G mode */
365 memcpy(sband->bitrates, &ath5k_rates[0],
366 sizeof(struct ieee80211_rate) * 12);
367 sband->n_bitrates = 12;
368
369 sband->channels = ah->channels;
370 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
371 AR5K_MODE_11G, max_c);
372
373 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
374 count_c = sband->n_channels;
375 max_c -= count_c;
376 } else if (test_bit(AR5K_MODE_11B, ah->ah_capabilities.cap_mode)) {
377 /* B mode */
378 memcpy(sband->bitrates, &ath5k_rates[0],
379 sizeof(struct ieee80211_rate) * 4);
380 sband->n_bitrates = 4;
381
382 /* 5211 only supports B rates and uses 4bit rate codes
383 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
384 * fix them up here:
385 */
386 if (ah->ah_version == AR5K_AR5211) {
387 for (i = 0; i < 4; i++) {
388 sband->bitrates[i].hw_value =
389 sband->bitrates[i].hw_value & 0xF;
390 sband->bitrates[i].hw_value_short =
391 sband->bitrates[i].hw_value_short & 0xF;
392 }
393 }
394
395 sband->channels = ah->channels;
396 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
397 AR5K_MODE_11B, max_c);
398
399 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
400 count_c = sband->n_channels;
401 max_c -= count_c;
402 }
403 ath5k_setup_rate_idx(ah, sband);
404
405 /* 5GHz band, A mode */
406 if (test_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode)) {
407 sband = &ah->sbands[IEEE80211_BAND_5GHZ];
408 sband->band = IEEE80211_BAND_5GHZ;
409 sband->bitrates = &ah->rates[IEEE80211_BAND_5GHZ][0];
410
411 memcpy(sband->bitrates, &ath5k_rates[4],
412 sizeof(struct ieee80211_rate) * 8);
413 sband->n_bitrates = 8;
414
415 sband->channels = &ah->channels[count_c];
416 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
417 AR5K_MODE_11A, max_c);
418
419 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
420 }
421 ath5k_setup_rate_idx(ah, sband);
422
423 ath5k_debug_dump_bands(ah);
424
425 return 0;
426 }
427
428 /*
429 * Set/change channels. We always reset the chip.
430 * To accomplish this we must first cleanup any pending DMA,
431 * then restart stuff after a la ath5k_init.
432 *
433 * Called with ah->lock.
434 */
435 int
436 ath5k_chan_set(struct ath5k_hw *ah, struct ieee80211_channel *chan)
437 {
438 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
439 "channel set, resetting (%u -> %u MHz)\n",
440 ah->curchan->center_freq, chan->center_freq);
441
442 /*
443 * To switch channels clear any pending DMA operations;
444 * wait long enough for the RX fifo to drain, reset the
445 * hardware at the new frequency, and then re-enable
446 * the relevant bits of the h/w.
447 */
448 return ath5k_reset(ah, chan, true);
449 }
450
451 void ath5k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
452 {
453 struct ath5k_vif_iter_data *iter_data = data;
454 int i;
455 struct ath5k_vif *avf = (void *)vif->drv_priv;
456
457 if (iter_data->hw_macaddr)
458 for (i = 0; i < ETH_ALEN; i++)
459 iter_data->mask[i] &=
460 ~(iter_data->hw_macaddr[i] ^ mac[i]);
461
462 if (!iter_data->found_active) {
463 iter_data->found_active = true;
464 memcpy(iter_data->active_mac, mac, ETH_ALEN);
465 }
466
467 if (iter_data->need_set_hw_addr && iter_data->hw_macaddr)
468 if (ether_addr_equal(iter_data->hw_macaddr, mac))
469 iter_data->need_set_hw_addr = false;
470
471 if (!iter_data->any_assoc) {
472 if (avf->assoc)
473 iter_data->any_assoc = true;
474 }
475
476 /* Calculate combined mode - when APs are active, operate in AP mode.
477 * Otherwise use the mode of the new interface. This can currently
478 * only deal with combinations of APs and STAs. Only one ad-hoc
479 * interfaces is allowed.
480 */
481 if (avf->opmode == NL80211_IFTYPE_AP)
482 iter_data->opmode = NL80211_IFTYPE_AP;
483 else {
484 if (avf->opmode == NL80211_IFTYPE_STATION)
485 iter_data->n_stas++;
486 if (iter_data->opmode == NL80211_IFTYPE_UNSPECIFIED)
487 iter_data->opmode = avf->opmode;
488 }
489 }
490
491 void
492 ath5k_update_bssid_mask_and_opmode(struct ath5k_hw *ah,
493 struct ieee80211_vif *vif)
494 {
495 struct ath_common *common = ath5k_hw_common(ah);
496 struct ath5k_vif_iter_data iter_data;
497 u32 rfilt;
498
499 /*
500 * Use the hardware MAC address as reference, the hardware uses it
501 * together with the BSSID mask when matching addresses.
502 */
503 iter_data.hw_macaddr = common->macaddr;
504 memset(&iter_data.mask, 0xff, ETH_ALEN);
505 iter_data.found_active = false;
506 iter_data.need_set_hw_addr = true;
507 iter_data.opmode = NL80211_IFTYPE_UNSPECIFIED;
508 iter_data.n_stas = 0;
509
510 if (vif)
511 ath5k_vif_iter(&iter_data, vif->addr, vif);
512
513 /* Get list of all active MAC addresses */
514 ieee80211_iterate_active_interfaces_atomic(
515 ah->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
516 ath5k_vif_iter, &iter_data);
517 memcpy(ah->bssidmask, iter_data.mask, ETH_ALEN);
518
519 ah->opmode = iter_data.opmode;
520 if (ah->opmode == NL80211_IFTYPE_UNSPECIFIED)
521 /* Nothing active, default to station mode */
522 ah->opmode = NL80211_IFTYPE_STATION;
523
524 ath5k_hw_set_opmode(ah, ah->opmode);
525 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n",
526 ah->opmode, ath_opmode_to_string(ah->opmode));
527
528 if (iter_data.need_set_hw_addr && iter_data.found_active)
529 ath5k_hw_set_lladdr(ah, iter_data.active_mac);
530
531 if (ath5k_hw_hasbssidmask(ah))
532 ath5k_hw_set_bssid_mask(ah, ah->bssidmask);
533
534 /* Set up RX Filter */
535 if (iter_data.n_stas > 1) {
536 /* If you have multiple STA interfaces connected to
537 * different APs, ARPs are not received (most of the time?)
538 * Enabling PROMISC appears to fix that problem.
539 */
540 ah->filter_flags |= AR5K_RX_FILTER_PROM;
541 }
542
543 rfilt = ah->filter_flags;
544 ath5k_hw_set_rx_filter(ah, rfilt);
545 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
546 }
547
548 static inline int
549 ath5k_hw_to_driver_rix(struct ath5k_hw *ah, int hw_rix)
550 {
551 int rix;
552
553 /* return base rate on errors */
554 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
555 "hw_rix out of bounds: %x\n", hw_rix))
556 return 0;
557
558 rix = ah->rate_idx[ah->curchan->band][hw_rix];
559 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
560 rix = 0;
561
562 return rix;
563 }
564
565 /***************\
566 * Buffers setup *
567 \***************/
568
569 static
570 struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_hw *ah, dma_addr_t *skb_addr)
571 {
572 struct ath_common *common = ath5k_hw_common(ah);
573 struct sk_buff *skb;
574
575 /*
576 * Allocate buffer with headroom_needed space for the
577 * fake physical layer header at the start.
578 */
579 skb = ath_rxbuf_alloc(common,
580 common->rx_bufsize,
581 GFP_ATOMIC);
582
583 if (!skb) {
584 ATH5K_ERR(ah, "can't alloc skbuff of size %u\n",
585 common->rx_bufsize);
586 return NULL;
587 }
588
589 *skb_addr = dma_map_single(ah->dev,
590 skb->data, common->rx_bufsize,
591 DMA_FROM_DEVICE);
592
593 if (unlikely(dma_mapping_error(ah->dev, *skb_addr))) {
594 ATH5K_ERR(ah, "%s: DMA mapping failed\n", __func__);
595 dev_kfree_skb(skb);
596 return NULL;
597 }
598 return skb;
599 }
600
601 static int
602 ath5k_rxbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf)
603 {
604 struct sk_buff *skb = bf->skb;
605 struct ath5k_desc *ds;
606 int ret;
607
608 if (!skb) {
609 skb = ath5k_rx_skb_alloc(ah, &bf->skbaddr);
610 if (!skb)
611 return -ENOMEM;
612 bf->skb = skb;
613 }
614
615 /*
616 * Setup descriptors. For receive we always terminate
617 * the descriptor list with a self-linked entry so we'll
618 * not get overrun under high load (as can happen with a
619 * 5212 when ANI processing enables PHY error frames).
620 *
621 * To ensure the last descriptor is self-linked we create
622 * each descriptor as self-linked and add it to the end. As
623 * each additional descriptor is added the previous self-linked
624 * entry is "fixed" naturally. This should be safe even
625 * if DMA is happening. When processing RX interrupts we
626 * never remove/process the last, self-linked, entry on the
627 * descriptor list. This ensures the hardware always has
628 * someplace to write a new frame.
629 */
630 ds = bf->desc;
631 ds->ds_link = bf->daddr; /* link to self */
632 ds->ds_data = bf->skbaddr;
633 ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0);
634 if (ret) {
635 ATH5K_ERR(ah, "%s: could not setup RX desc\n", __func__);
636 return ret;
637 }
638
639 if (ah->rxlink != NULL)
640 *ah->rxlink = bf->daddr;
641 ah->rxlink = &ds->ds_link;
642 return 0;
643 }
644
645 static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
646 {
647 struct ieee80211_hdr *hdr;
648 enum ath5k_pkt_type htype;
649 __le16 fc;
650
651 hdr = (struct ieee80211_hdr *)skb->data;
652 fc = hdr->frame_control;
653
654 if (ieee80211_is_beacon(fc))
655 htype = AR5K_PKT_TYPE_BEACON;
656 else if (ieee80211_is_probe_resp(fc))
657 htype = AR5K_PKT_TYPE_PROBE_RESP;
658 else if (ieee80211_is_atim(fc))
659 htype = AR5K_PKT_TYPE_ATIM;
660 else if (ieee80211_is_pspoll(fc))
661 htype = AR5K_PKT_TYPE_PSPOLL;
662 else
663 htype = AR5K_PKT_TYPE_NORMAL;
664
665 return htype;
666 }
667
668 static int
669 ath5k_txbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf,
670 struct ath5k_txq *txq, int padsize)
671 {
672 struct ath5k_desc *ds = bf->desc;
673 struct sk_buff *skb = bf->skb;
674 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
675 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
676 struct ieee80211_rate *rate;
677 unsigned int mrr_rate[3], mrr_tries[3];
678 int i, ret;
679 u16 hw_rate;
680 u16 cts_rate = 0;
681 u16 duration = 0;
682 u8 rc_flags;
683
684 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
685
686 /* XXX endianness */
687 bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len,
688 DMA_TO_DEVICE);
689
690 rate = ieee80211_get_tx_rate(ah->hw, info);
691 if (!rate) {
692 ret = -EINVAL;
693 goto err_unmap;
694 }
695
696 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
697 flags |= AR5K_TXDESC_NOACK;
698
699 rc_flags = info->control.rates[0].flags;
700 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
701 rate->hw_value_short : rate->hw_value;
702
703 pktlen = skb->len;
704
705 /* FIXME: If we are in g mode and rate is a CCK rate
706 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
707 * from tx power (value is in dB units already) */
708 if (info->control.hw_key) {
709 keyidx = info->control.hw_key->hw_key_idx;
710 pktlen += info->control.hw_key->icv_len;
711 }
712 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
713 flags |= AR5K_TXDESC_RTSENA;
714 cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value;
715 duration = le16_to_cpu(ieee80211_rts_duration(ah->hw,
716 info->control.vif, pktlen, info));
717 }
718 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
719 flags |= AR5K_TXDESC_CTSENA;
720 cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value;
721 duration = le16_to_cpu(ieee80211_ctstoself_duration(ah->hw,
722 info->control.vif, pktlen, info));
723 }
724 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
725 ieee80211_get_hdrlen_from_skb(skb), padsize,
726 get_hw_packet_type(skb),
727 (ah->ah_txpower.txp_requested * 2),
728 hw_rate,
729 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
730 cts_rate, duration);
731 if (ret)
732 goto err_unmap;
733
734 /* Set up MRR descriptor */
735 if (ah->ah_capabilities.cap_has_mrr_support) {
736 memset(mrr_rate, 0, sizeof(mrr_rate));
737 memset(mrr_tries, 0, sizeof(mrr_tries));
738 for (i = 0; i < 3; i++) {
739 rate = ieee80211_get_alt_retry_rate(ah->hw, info, i);
740 if (!rate)
741 break;
742
743 mrr_rate[i] = rate->hw_value;
744 mrr_tries[i] = info->control.rates[i + 1].count;
745 }
746
747 ath5k_hw_setup_mrr_tx_desc(ah, ds,
748 mrr_rate[0], mrr_tries[0],
749 mrr_rate[1], mrr_tries[1],
750 mrr_rate[2], mrr_tries[2]);
751 }
752
753 ds->ds_link = 0;
754 ds->ds_data = bf->skbaddr;
755
756 spin_lock_bh(&txq->lock);
757 list_add_tail(&bf->list, &txq->q);
758 txq->txq_len++;
759 if (txq->link == NULL) /* is this first packet? */
760 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
761 else /* no, so only link it */
762 *txq->link = bf->daddr;
763
764 txq->link = &ds->ds_link;
765 ath5k_hw_start_tx_dma(ah, txq->qnum);
766 mmiowb();
767 spin_unlock_bh(&txq->lock);
768
769 return 0;
770 err_unmap:
771 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
772 return ret;
773 }
774
775 /*******************\
776 * Descriptors setup *
777 \*******************/
778
779 static int
780 ath5k_desc_alloc(struct ath5k_hw *ah)
781 {
782 struct ath5k_desc *ds;
783 struct ath5k_buf *bf;
784 dma_addr_t da;
785 unsigned int i;
786 int ret;
787
788 /* allocate descriptors */
789 ah->desc_len = sizeof(struct ath5k_desc) *
790 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
791
792 ah->desc = dma_alloc_coherent(ah->dev, ah->desc_len,
793 &ah->desc_daddr, GFP_KERNEL);
794 if (ah->desc == NULL) {
795 ATH5K_ERR(ah, "can't allocate descriptors\n");
796 ret = -ENOMEM;
797 goto err;
798 }
799 ds = ah->desc;
800 da = ah->desc_daddr;
801 ATH5K_DBG(ah, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
802 ds, ah->desc_len, (unsigned long long)ah->desc_daddr);
803
804 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
805 sizeof(struct ath5k_buf), GFP_KERNEL);
806 if (bf == NULL) {
807 ATH5K_ERR(ah, "can't allocate bufptr\n");
808 ret = -ENOMEM;
809 goto err_free;
810 }
811 ah->bufptr = bf;
812
813 INIT_LIST_HEAD(&ah->rxbuf);
814 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
815 bf->desc = ds;
816 bf->daddr = da;
817 list_add_tail(&bf->list, &ah->rxbuf);
818 }
819
820 INIT_LIST_HEAD(&ah->txbuf);
821 ah->txbuf_len = ATH_TXBUF;
822 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
823 bf->desc = ds;
824 bf->daddr = da;
825 list_add_tail(&bf->list, &ah->txbuf);
826 }
827
828 /* beacon buffers */
829 INIT_LIST_HEAD(&ah->bcbuf);
830 for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) {
831 bf->desc = ds;
832 bf->daddr = da;
833 list_add_tail(&bf->list, &ah->bcbuf);
834 }
835
836 return 0;
837 err_free:
838 dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr);
839 err:
840 ah->desc = NULL;
841 return ret;
842 }
843
844 void
845 ath5k_txbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf)
846 {
847 BUG_ON(!bf);
848 if (!bf->skb)
849 return;
850 dma_unmap_single(ah->dev, bf->skbaddr, bf->skb->len,
851 DMA_TO_DEVICE);
852 dev_kfree_skb_any(bf->skb);
853 bf->skb = NULL;
854 bf->skbaddr = 0;
855 bf->desc->ds_data = 0;
856 }
857
858 void
859 ath5k_rxbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf)
860 {
861 struct ath_common *common = ath5k_hw_common(ah);
862
863 BUG_ON(!bf);
864 if (!bf->skb)
865 return;
866 dma_unmap_single(ah->dev, bf->skbaddr, common->rx_bufsize,
867 DMA_FROM_DEVICE);
868 dev_kfree_skb_any(bf->skb);
869 bf->skb = NULL;
870 bf->skbaddr = 0;
871 bf->desc->ds_data = 0;
872 }
873
874 static void
875 ath5k_desc_free(struct ath5k_hw *ah)
876 {
877 struct ath5k_buf *bf;
878
879 list_for_each_entry(bf, &ah->txbuf, list)
880 ath5k_txbuf_free_skb(ah, bf);
881 list_for_each_entry(bf, &ah->rxbuf, list)
882 ath5k_rxbuf_free_skb(ah, bf);
883 list_for_each_entry(bf, &ah->bcbuf, list)
884 ath5k_txbuf_free_skb(ah, bf);
885
886 /* Free memory associated with all descriptors */
887 dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr);
888 ah->desc = NULL;
889 ah->desc_daddr = 0;
890
891 kfree(ah->bufptr);
892 ah->bufptr = NULL;
893 }
894
895
896 /**************\
897 * Queues setup *
898 \**************/
899
900 static struct ath5k_txq *
901 ath5k_txq_setup(struct ath5k_hw *ah,
902 int qtype, int subtype)
903 {
904 struct ath5k_txq *txq;
905 struct ath5k_txq_info qi = {
906 .tqi_subtype = subtype,
907 /* XXX: default values not correct for B and XR channels,
908 * but who cares? */
909 .tqi_aifs = AR5K_TUNE_AIFS,
910 .tqi_cw_min = AR5K_TUNE_CWMIN,
911 .tqi_cw_max = AR5K_TUNE_CWMAX
912 };
913 int qnum;
914
915 /*
916 * Enable interrupts only for EOL and DESC conditions.
917 * We mark tx descriptors to receive a DESC interrupt
918 * when a tx queue gets deep; otherwise we wait for the
919 * EOL to reap descriptors. Note that this is done to
920 * reduce interrupt load and this only defers reaping
921 * descriptors, never transmitting frames. Aside from
922 * reducing interrupts this also permits more concurrency.
923 * The only potential downside is if the tx queue backs
924 * up in which case the top half of the kernel may backup
925 * due to a lack of tx descriptors.
926 */
927 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
928 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
929 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
930 if (qnum < 0) {
931 /*
932 * NB: don't print a message, this happens
933 * normally on parts with too few tx queues
934 */
935 return ERR_PTR(qnum);
936 }
937 txq = &ah->txqs[qnum];
938 if (!txq->setup) {
939 txq->qnum = qnum;
940 txq->link = NULL;
941 INIT_LIST_HEAD(&txq->q);
942 spin_lock_init(&txq->lock);
943 txq->setup = true;
944 txq->txq_len = 0;
945 txq->txq_max = ATH5K_TXQ_LEN_MAX;
946 txq->txq_poll_mark = false;
947 txq->txq_stuck = 0;
948 }
949 return &ah->txqs[qnum];
950 }
951
952 static int
953 ath5k_beaconq_setup(struct ath5k_hw *ah)
954 {
955 struct ath5k_txq_info qi = {
956 /* XXX: default values not correct for B and XR channels,
957 * but who cares? */
958 .tqi_aifs = AR5K_TUNE_AIFS,
959 .tqi_cw_min = AR5K_TUNE_CWMIN,
960 .tqi_cw_max = AR5K_TUNE_CWMAX,
961 /* NB: for dynamic turbo, don't enable any other interrupts */
962 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
963 };
964
965 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
966 }
967
968 static int
969 ath5k_beaconq_config(struct ath5k_hw *ah)
970 {
971 struct ath5k_txq_info qi;
972 int ret;
973
974 ret = ath5k_hw_get_tx_queueprops(ah, ah->bhalq, &qi);
975 if (ret)
976 goto err;
977
978 if (ah->opmode == NL80211_IFTYPE_AP ||
979 ah->opmode == NL80211_IFTYPE_MESH_POINT) {
980 /*
981 * Always burst out beacon and CAB traffic
982 * (aifs = cwmin = cwmax = 0)
983 */
984 qi.tqi_aifs = 0;
985 qi.tqi_cw_min = 0;
986 qi.tqi_cw_max = 0;
987 } else if (ah->opmode == NL80211_IFTYPE_ADHOC) {
988 /*
989 * Adhoc mode; backoff between 0 and (2 * cw_min).
990 */
991 qi.tqi_aifs = 0;
992 qi.tqi_cw_min = 0;
993 qi.tqi_cw_max = 2 * AR5K_TUNE_CWMIN;
994 }
995
996 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
997 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
998 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
999
1000 ret = ath5k_hw_set_tx_queueprops(ah, ah->bhalq, &qi);
1001 if (ret) {
1002 ATH5K_ERR(ah, "%s: unable to update parameters for beacon "
1003 "hardware queue!\n", __func__);
1004 goto err;
1005 }
1006 ret = ath5k_hw_reset_tx_queue(ah, ah->bhalq); /* push to h/w */
1007 if (ret)
1008 goto err;
1009
1010 /* reconfigure cabq with ready time to 80% of beacon_interval */
1011 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1012 if (ret)
1013 goto err;
1014
1015 qi.tqi_ready_time = (ah->bintval * 80) / 100;
1016 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1017 if (ret)
1018 goto err;
1019
1020 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB);
1021 err:
1022 return ret;
1023 }
1024
1025 /**
1026 * ath5k_drain_tx_buffs - Empty tx buffers
1027 *
1028 * @ah The &struct ath5k_hw
1029 *
1030 * Empty tx buffers from all queues in preparation
1031 * of a reset or during shutdown.
1032 *
1033 * NB: this assumes output has been stopped and
1034 * we do not need to block ath5k_tx_tasklet
1035 */
1036 static void
1037 ath5k_drain_tx_buffs(struct ath5k_hw *ah)
1038 {
1039 struct ath5k_txq *txq;
1040 struct ath5k_buf *bf, *bf0;
1041 int i;
1042
1043 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) {
1044 if (ah->txqs[i].setup) {
1045 txq = &ah->txqs[i];
1046 spin_lock_bh(&txq->lock);
1047 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1048 ath5k_debug_printtxbuf(ah, bf);
1049
1050 ath5k_txbuf_free_skb(ah, bf);
1051
1052 spin_lock(&ah->txbuflock);
1053 list_move_tail(&bf->list, &ah->txbuf);
1054 ah->txbuf_len++;
1055 txq->txq_len--;
1056 spin_unlock(&ah->txbuflock);
1057 }
1058 txq->link = NULL;
1059 txq->txq_poll_mark = false;
1060 spin_unlock_bh(&txq->lock);
1061 }
1062 }
1063 }
1064
1065 static void
1066 ath5k_txq_release(struct ath5k_hw *ah)
1067 {
1068 struct ath5k_txq *txq = ah->txqs;
1069 unsigned int i;
1070
1071 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++, txq++)
1072 if (txq->setup) {
1073 ath5k_hw_release_tx_queue(ah, txq->qnum);
1074 txq->setup = false;
1075 }
1076 }
1077
1078
1079 /*************\
1080 * RX Handling *
1081 \*************/
1082
1083 /*
1084 * Enable the receive h/w following a reset.
1085 */
1086 static int
1087 ath5k_rx_start(struct ath5k_hw *ah)
1088 {
1089 struct ath_common *common = ath5k_hw_common(ah);
1090 struct ath5k_buf *bf;
1091 int ret;
1092
1093 common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz);
1094
1095 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
1096 common->cachelsz, common->rx_bufsize);
1097
1098 spin_lock_bh(&ah->rxbuflock);
1099 ah->rxlink = NULL;
1100 list_for_each_entry(bf, &ah->rxbuf, list) {
1101 ret = ath5k_rxbuf_setup(ah, bf);
1102 if (ret != 0) {
1103 spin_unlock_bh(&ah->rxbuflock);
1104 goto err;
1105 }
1106 }
1107 bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list);
1108 ath5k_hw_set_rxdp(ah, bf->daddr);
1109 spin_unlock_bh(&ah->rxbuflock);
1110
1111 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
1112 ath5k_update_bssid_mask_and_opmode(ah, NULL); /* set filters, etc. */
1113 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1114
1115 return 0;
1116 err:
1117 return ret;
1118 }
1119
1120 /*
1121 * Disable the receive logic on PCU (DRU)
1122 * In preparation for a shutdown.
1123 *
1124 * Note: Doesn't stop rx DMA, ath5k_hw_dma_stop
1125 * does.
1126 */
1127 static void
1128 ath5k_rx_stop(struct ath5k_hw *ah)
1129 {
1130
1131 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1132 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
1133
1134 ath5k_debug_printrxbuffs(ah);
1135 }
1136
1137 static unsigned int
1138 ath5k_rx_decrypted(struct ath5k_hw *ah, struct sk_buff *skb,
1139 struct ath5k_rx_status *rs)
1140 {
1141 struct ath_common *common = ath5k_hw_common(ah);
1142 struct ieee80211_hdr *hdr = (void *)skb->data;
1143 unsigned int keyix, hlen;
1144
1145 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1146 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1147 return RX_FLAG_DECRYPTED;
1148
1149 /* Apparently when a default key is used to decrypt the packet
1150 the hw does not set the index used to decrypt. In such cases
1151 get the index from the packet. */
1152 hlen = ieee80211_hdrlen(hdr->frame_control);
1153 if (ieee80211_has_protected(hdr->frame_control) &&
1154 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1155 skb->len >= hlen + 4) {
1156 keyix = skb->data[hlen + 3] >> 6;
1157
1158 if (test_bit(keyix, common->keymap))
1159 return RX_FLAG_DECRYPTED;
1160 }
1161
1162 return 0;
1163 }
1164
1165
1166 static void
1167 ath5k_check_ibss_tsf(struct ath5k_hw *ah, struct sk_buff *skb,
1168 struct ieee80211_rx_status *rxs)
1169 {
1170 struct ath_common *common = ath5k_hw_common(ah);
1171 u64 tsf, bc_tstamp;
1172 u32 hw_tu;
1173 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1174
1175 if (ieee80211_is_beacon(mgmt->frame_control) &&
1176 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1177 ether_addr_equal(mgmt->bssid, common->curbssid)) {
1178 /*
1179 * Received an IBSS beacon with the same BSSID. Hardware *must*
1180 * have updated the local TSF. We have to work around various
1181 * hardware bugs, though...
1182 */
1183 tsf = ath5k_hw_get_tsf64(ah);
1184 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1185 hw_tu = TSF_TO_TU(tsf);
1186
1187 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
1188 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1189 (unsigned long long)bc_tstamp,
1190 (unsigned long long)rxs->mactime,
1191 (unsigned long long)(rxs->mactime - bc_tstamp),
1192 (unsigned long long)tsf);
1193
1194 /*
1195 * Sometimes the HW will give us a wrong tstamp in the rx
1196 * status, causing the timestamp extension to go wrong.
1197 * (This seems to happen especially with beacon frames bigger
1198 * than 78 byte (incl. FCS))
1199 * But we know that the receive timestamp must be later than the
1200 * timestamp of the beacon since HW must have synced to that.
1201 *
1202 * NOTE: here we assume mactime to be after the frame was
1203 * received, not like mac80211 which defines it at the start.
1204 */
1205 if (bc_tstamp > rxs->mactime) {
1206 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
1207 "fixing mactime from %llx to %llx\n",
1208 (unsigned long long)rxs->mactime,
1209 (unsigned long long)tsf);
1210 rxs->mactime = tsf;
1211 }
1212
1213 /*
1214 * Local TSF might have moved higher than our beacon timers,
1215 * in that case we have to update them to continue sending
1216 * beacons. This also takes care of synchronizing beacon sending
1217 * times with other stations.
1218 */
1219 if (hw_tu >= ah->nexttbtt)
1220 ath5k_beacon_update_timers(ah, bc_tstamp);
1221
1222 /* Check if the beacon timers are still correct, because a TSF
1223 * update might have created a window between them - for a
1224 * longer description see the comment of this function: */
1225 if (!ath5k_hw_check_beacon_timers(ah, ah->bintval)) {
1226 ath5k_beacon_update_timers(ah, bc_tstamp);
1227 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
1228 "fixed beacon timers after beacon receive\n");
1229 }
1230 }
1231 }
1232
1233 static void
1234 ath5k_update_beacon_rssi(struct ath5k_hw *ah, struct sk_buff *skb, int rssi)
1235 {
1236 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1237 struct ath_common *common = ath5k_hw_common(ah);
1238
1239 /* only beacons from our BSSID */
1240 if (!ieee80211_is_beacon(mgmt->frame_control) ||
1241 !ether_addr_equal(mgmt->bssid, common->curbssid))
1242 return;
1243
1244 ewma_add(&ah->ah_beacon_rssi_avg, rssi);
1245
1246 /* in IBSS mode we should keep RSSI statistics per neighbour */
1247 /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */
1248 }
1249
1250 /*
1251 * Compute padding position. skb must contain an IEEE 802.11 frame
1252 */
1253 static int ath5k_common_padpos(struct sk_buff *skb)
1254 {
1255 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1256 __le16 frame_control = hdr->frame_control;
1257 int padpos = 24;
1258
1259 if (ieee80211_has_a4(frame_control))
1260 padpos += ETH_ALEN;
1261
1262 if (ieee80211_is_data_qos(frame_control))
1263 padpos += IEEE80211_QOS_CTL_LEN;
1264
1265 return padpos;
1266 }
1267
1268 /*
1269 * This function expects an 802.11 frame and returns the number of
1270 * bytes added, or -1 if we don't have enough header room.
1271 */
1272 static int ath5k_add_padding(struct sk_buff *skb)
1273 {
1274 int padpos = ath5k_common_padpos(skb);
1275 int padsize = padpos & 3;
1276
1277 if (padsize && skb->len > padpos) {
1278
1279 if (skb_headroom(skb) < padsize)
1280 return -1;
1281
1282 skb_push(skb, padsize);
1283 memmove(skb->data, skb->data + padsize, padpos);
1284 return padsize;
1285 }
1286
1287 return 0;
1288 }
1289
1290 /*
1291 * The MAC header is padded to have 32-bit boundary if the
1292 * packet payload is non-zero. The general calculation for
1293 * padsize would take into account odd header lengths:
1294 * padsize = 4 - (hdrlen & 3); however, since only
1295 * even-length headers are used, padding can only be 0 or 2
1296 * bytes and we can optimize this a bit. We must not try to
1297 * remove padding from short control frames that do not have a
1298 * payload.
1299 *
1300 * This function expects an 802.11 frame and returns the number of
1301 * bytes removed.
1302 */
1303 static int ath5k_remove_padding(struct sk_buff *skb)
1304 {
1305 int padpos = ath5k_common_padpos(skb);
1306 int padsize = padpos & 3;
1307
1308 if (padsize && skb->len >= padpos + padsize) {
1309 memmove(skb->data + padsize, skb->data, padpos);
1310 skb_pull(skb, padsize);
1311 return padsize;
1312 }
1313
1314 return 0;
1315 }
1316
1317 static void
1318 ath5k_receive_frame(struct ath5k_hw *ah, struct sk_buff *skb,
1319 struct ath5k_rx_status *rs)
1320 {
1321 struct ieee80211_rx_status *rxs;
1322
1323 ath5k_remove_padding(skb);
1324
1325 rxs = IEEE80211_SKB_RXCB(skb);
1326
1327 rxs->flag = 0;
1328 if (unlikely(rs->rs_status & AR5K_RXERR_MIC))
1329 rxs->flag |= RX_FLAG_MMIC_ERROR;
1330
1331 /*
1332 * always extend the mac timestamp, since this information is
1333 * also needed for proper IBSS merging.
1334 *
1335 * XXX: it might be too late to do it here, since rs_tstamp is
1336 * 15bit only. that means TSF extension has to be done within
1337 * 32768usec (about 32ms). it might be necessary to move this to
1338 * the interrupt handler, like it is done in madwifi.
1339 *
1340 * Unfortunately we don't know when the hardware takes the rx
1341 * timestamp (beginning of phy frame, data frame, end of rx?).
1342 * The only thing we know is that it is hardware specific...
1343 * On AR5213 it seems the rx timestamp is at the end of the
1344 * frame, but I'm not sure.
1345 *
1346 * NOTE: mac80211 defines mactime at the beginning of the first
1347 * data symbol. Since we don't have any time references it's
1348 * impossible to comply to that. This affects IBSS merge only
1349 * right now, so it's not too bad...
1350 */
1351 rxs->mactime = ath5k_extend_tsf(ah, rs->rs_tstamp);
1352 rxs->flag |= RX_FLAG_MACTIME_MPDU;
1353
1354 rxs->freq = ah->curchan->center_freq;
1355 rxs->band = ah->curchan->band;
1356
1357 rxs->signal = ah->ah_noise_floor + rs->rs_rssi;
1358
1359 rxs->antenna = rs->rs_antenna;
1360
1361 if (rs->rs_antenna > 0 && rs->rs_antenna < 5)
1362 ah->stats.antenna_rx[rs->rs_antenna]++;
1363 else
1364 ah->stats.antenna_rx[0]++; /* invalid */
1365
1366 rxs->rate_idx = ath5k_hw_to_driver_rix(ah, rs->rs_rate);
1367 rxs->flag |= ath5k_rx_decrypted(ah, skb, rs);
1368
1369 if (rxs->rate_idx >= 0 && rs->rs_rate ==
1370 ah->sbands[ah->curchan->band].bitrates[rxs->rate_idx].hw_value_short)
1371 rxs->flag |= RX_FLAG_SHORTPRE;
1372
1373 trace_ath5k_rx(ah, skb);
1374
1375 ath5k_update_beacon_rssi(ah, skb, rs->rs_rssi);
1376
1377 /* check beacons in IBSS mode */
1378 if (ah->opmode == NL80211_IFTYPE_ADHOC)
1379 ath5k_check_ibss_tsf(ah, skb, rxs);
1380
1381 ieee80211_rx(ah->hw, skb);
1382 }
1383
1384 /** ath5k_frame_receive_ok() - Do we want to receive this frame or not?
1385 *
1386 * Check if we want to further process this frame or not. Also update
1387 * statistics. Return true if we want this frame, false if not.
1388 */
1389 static bool
1390 ath5k_receive_frame_ok(struct ath5k_hw *ah, struct ath5k_rx_status *rs)
1391 {
1392 ah->stats.rx_all_count++;
1393 ah->stats.rx_bytes_count += rs->rs_datalen;
1394
1395 if (unlikely(rs->rs_status)) {
1396 if (rs->rs_status & AR5K_RXERR_CRC)
1397 ah->stats.rxerr_crc++;
1398 if (rs->rs_status & AR5K_RXERR_FIFO)
1399 ah->stats.rxerr_fifo++;
1400 if (rs->rs_status & AR5K_RXERR_PHY) {
1401 ah->stats.rxerr_phy++;
1402 if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32)
1403 ah->stats.rxerr_phy_code[rs->rs_phyerr]++;
1404 return false;
1405 }
1406 if (rs->rs_status & AR5K_RXERR_DECRYPT) {
1407 /*
1408 * Decrypt error. If the error occurred
1409 * because there was no hardware key, then
1410 * let the frame through so the upper layers
1411 * can process it. This is necessary for 5210
1412 * parts which have no way to setup a ``clear''
1413 * key cache entry.
1414 *
1415 * XXX do key cache faulting
1416 */
1417 ah->stats.rxerr_decrypt++;
1418 if (rs->rs_keyix == AR5K_RXKEYIX_INVALID &&
1419 !(rs->rs_status & AR5K_RXERR_CRC))
1420 return true;
1421 }
1422 if (rs->rs_status & AR5K_RXERR_MIC) {
1423 ah->stats.rxerr_mic++;
1424 return true;
1425 }
1426
1427 /* reject any frames with non-crypto errors */
1428 if (rs->rs_status & ~(AR5K_RXERR_DECRYPT))
1429 return false;
1430 }
1431
1432 if (unlikely(rs->rs_more)) {
1433 ah->stats.rxerr_jumbo++;
1434 return false;
1435 }
1436 return true;
1437 }
1438
1439 static void
1440 ath5k_set_current_imask(struct ath5k_hw *ah)
1441 {
1442 enum ath5k_int imask;
1443 unsigned long flags;
1444
1445 spin_lock_irqsave(&ah->irqlock, flags);
1446 imask = ah->imask;
1447 if (ah->rx_pending)
1448 imask &= ~AR5K_INT_RX_ALL;
1449 if (ah->tx_pending)
1450 imask &= ~AR5K_INT_TX_ALL;
1451 ath5k_hw_set_imr(ah, imask);
1452 spin_unlock_irqrestore(&ah->irqlock, flags);
1453 }
1454
1455 static void
1456 ath5k_tasklet_rx(unsigned long data)
1457 {
1458 struct ath5k_rx_status rs = {};
1459 struct sk_buff *skb, *next_skb;
1460 dma_addr_t next_skb_addr;
1461 struct ath5k_hw *ah = (void *)data;
1462 struct ath_common *common = ath5k_hw_common(ah);
1463 struct ath5k_buf *bf;
1464 struct ath5k_desc *ds;
1465 int ret;
1466
1467 spin_lock(&ah->rxbuflock);
1468 if (list_empty(&ah->rxbuf)) {
1469 ATH5K_WARN(ah, "empty rx buf pool\n");
1470 goto unlock;
1471 }
1472 do {
1473 bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list);
1474 BUG_ON(bf->skb == NULL);
1475 skb = bf->skb;
1476 ds = bf->desc;
1477
1478 /* bail if HW is still using self-linked descriptor */
1479 if (ath5k_hw_get_rxdp(ah) == bf->daddr)
1480 break;
1481
1482 ret = ah->ah_proc_rx_desc(ah, ds, &rs);
1483 if (unlikely(ret == -EINPROGRESS))
1484 break;
1485 else if (unlikely(ret)) {
1486 ATH5K_ERR(ah, "error in processing rx descriptor\n");
1487 ah->stats.rxerr_proc++;
1488 break;
1489 }
1490
1491 if (ath5k_receive_frame_ok(ah, &rs)) {
1492 next_skb = ath5k_rx_skb_alloc(ah, &next_skb_addr);
1493
1494 /*
1495 * If we can't replace bf->skb with a new skb under
1496 * memory pressure, just skip this packet
1497 */
1498 if (!next_skb)
1499 goto next;
1500
1501 dma_unmap_single(ah->dev, bf->skbaddr,
1502 common->rx_bufsize,
1503 DMA_FROM_DEVICE);
1504
1505 skb_put(skb, rs.rs_datalen);
1506
1507 ath5k_receive_frame(ah, skb, &rs);
1508
1509 bf->skb = next_skb;
1510 bf->skbaddr = next_skb_addr;
1511 }
1512 next:
1513 list_move_tail(&bf->list, &ah->rxbuf);
1514 } while (ath5k_rxbuf_setup(ah, bf) == 0);
1515 unlock:
1516 spin_unlock(&ah->rxbuflock);
1517 ah->rx_pending = false;
1518 ath5k_set_current_imask(ah);
1519 }
1520
1521
1522 /*************\
1523 * TX Handling *
1524 \*************/
1525
1526 void
1527 ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
1528 struct ath5k_txq *txq)
1529 {
1530 struct ath5k_hw *ah = hw->priv;
1531 struct ath5k_buf *bf;
1532 unsigned long flags;
1533 int padsize;
1534
1535 trace_ath5k_tx(ah, skb, txq);
1536
1537 /*
1538 * The hardware expects the header padded to 4 byte boundaries.
1539 * If this is not the case, we add the padding after the header.
1540 */
1541 padsize = ath5k_add_padding(skb);
1542 if (padsize < 0) {
1543 ATH5K_ERR(ah, "tx hdrlen not %%4: not enough"
1544 " headroom to pad");
1545 goto drop_packet;
1546 }
1547
1548 if (txq->txq_len >= txq->txq_max &&
1549 txq->qnum <= AR5K_TX_QUEUE_ID_DATA_MAX)
1550 ieee80211_stop_queue(hw, txq->qnum);
1551
1552 spin_lock_irqsave(&ah->txbuflock, flags);
1553 if (list_empty(&ah->txbuf)) {
1554 ATH5K_ERR(ah, "no further txbuf available, dropping packet\n");
1555 spin_unlock_irqrestore(&ah->txbuflock, flags);
1556 ieee80211_stop_queues(hw);
1557 goto drop_packet;
1558 }
1559 bf = list_first_entry(&ah->txbuf, struct ath5k_buf, list);
1560 list_del(&bf->list);
1561 ah->txbuf_len--;
1562 if (list_empty(&ah->txbuf))
1563 ieee80211_stop_queues(hw);
1564 spin_unlock_irqrestore(&ah->txbuflock, flags);
1565
1566 bf->skb = skb;
1567
1568 if (ath5k_txbuf_setup(ah, bf, txq, padsize)) {
1569 bf->skb = NULL;
1570 spin_lock_irqsave(&ah->txbuflock, flags);
1571 list_add_tail(&bf->list, &ah->txbuf);
1572 ah->txbuf_len++;
1573 spin_unlock_irqrestore(&ah->txbuflock, flags);
1574 goto drop_packet;
1575 }
1576 return;
1577
1578 drop_packet:
1579 dev_kfree_skb_any(skb);
1580 }
1581
1582 static void
1583 ath5k_tx_frame_completed(struct ath5k_hw *ah, struct sk_buff *skb,
1584 struct ath5k_txq *txq, struct ath5k_tx_status *ts)
1585 {
1586 struct ieee80211_tx_info *info;
1587 u8 tries[3];
1588 int i;
1589
1590 ah->stats.tx_all_count++;
1591 ah->stats.tx_bytes_count += skb->len;
1592 info = IEEE80211_SKB_CB(skb);
1593
1594 tries[0] = info->status.rates[0].count;
1595 tries[1] = info->status.rates[1].count;
1596 tries[2] = info->status.rates[2].count;
1597
1598 ieee80211_tx_info_clear_status(info);
1599
1600 for (i = 0; i < ts->ts_final_idx; i++) {
1601 struct ieee80211_tx_rate *r =
1602 &info->status.rates[i];
1603
1604 r->count = tries[i];
1605 }
1606
1607 info->status.rates[ts->ts_final_idx].count = ts->ts_final_retry;
1608 info->status.rates[ts->ts_final_idx + 1].idx = -1;
1609
1610 if (unlikely(ts->ts_status)) {
1611 ah->stats.ack_fail++;
1612 if (ts->ts_status & AR5K_TXERR_FILT) {
1613 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1614 ah->stats.txerr_filt++;
1615 }
1616 if (ts->ts_status & AR5K_TXERR_XRETRY)
1617 ah->stats.txerr_retry++;
1618 if (ts->ts_status & AR5K_TXERR_FIFO)
1619 ah->stats.txerr_fifo++;
1620 } else {
1621 info->flags |= IEEE80211_TX_STAT_ACK;
1622 info->status.ack_signal = ts->ts_rssi;
1623
1624 /* count the successful attempt as well */
1625 info->status.rates[ts->ts_final_idx].count++;
1626 }
1627
1628 /*
1629 * Remove MAC header padding before giving the frame
1630 * back to mac80211.
1631 */
1632 ath5k_remove_padding(skb);
1633
1634 if (ts->ts_antenna > 0 && ts->ts_antenna < 5)
1635 ah->stats.antenna_tx[ts->ts_antenna]++;
1636 else
1637 ah->stats.antenna_tx[0]++; /* invalid */
1638
1639 trace_ath5k_tx_complete(ah, skb, txq, ts);
1640 ieee80211_tx_status(ah->hw, skb);
1641 }
1642
1643 static void
1644 ath5k_tx_processq(struct ath5k_hw *ah, struct ath5k_txq *txq)
1645 {
1646 struct ath5k_tx_status ts = {};
1647 struct ath5k_buf *bf, *bf0;
1648 struct ath5k_desc *ds;
1649 struct sk_buff *skb;
1650 int ret;
1651
1652 spin_lock(&txq->lock);
1653 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1654
1655 txq->txq_poll_mark = false;
1656
1657 /* skb might already have been processed last time. */
1658 if (bf->skb != NULL) {
1659 ds = bf->desc;
1660
1661 ret = ah->ah_proc_tx_desc(ah, ds, &ts);
1662 if (unlikely(ret == -EINPROGRESS))
1663 break;
1664 else if (unlikely(ret)) {
1665 ATH5K_ERR(ah,
1666 "error %d while processing "
1667 "queue %u\n", ret, txq->qnum);
1668 break;
1669 }
1670
1671 skb = bf->skb;
1672 bf->skb = NULL;
1673
1674 dma_unmap_single(ah->dev, bf->skbaddr, skb->len,
1675 DMA_TO_DEVICE);
1676 ath5k_tx_frame_completed(ah, skb, txq, &ts);
1677 }
1678
1679 /*
1680 * It's possible that the hardware can say the buffer is
1681 * completed when it hasn't yet loaded the ds_link from
1682 * host memory and moved on.
1683 * Always keep the last descriptor to avoid HW races...
1684 */
1685 if (ath5k_hw_get_txdp(ah, txq->qnum) != bf->daddr) {
1686 spin_lock(&ah->txbuflock);
1687 list_move_tail(&bf->list, &ah->txbuf);
1688 ah->txbuf_len++;
1689 txq->txq_len--;
1690 spin_unlock(&ah->txbuflock);
1691 }
1692 }
1693 spin_unlock(&txq->lock);
1694 if (txq->txq_len < ATH5K_TXQ_LEN_LOW && txq->qnum < 4)
1695 ieee80211_wake_queue(ah->hw, txq->qnum);
1696 }
1697
1698 static void
1699 ath5k_tasklet_tx(unsigned long data)
1700 {
1701 int i;
1702 struct ath5k_hw *ah = (void *)data;
1703
1704 for (i = 0; i < AR5K_NUM_TX_QUEUES; i++)
1705 if (ah->txqs[i].setup && (ah->ah_txq_isr_txok_all & BIT(i)))
1706 ath5k_tx_processq(ah, &ah->txqs[i]);
1707
1708 ah->tx_pending = false;
1709 ath5k_set_current_imask(ah);
1710 }
1711
1712
1713 /*****************\
1714 * Beacon handling *
1715 \*****************/
1716
1717 /*
1718 * Setup the beacon frame for transmit.
1719 */
1720 static int
1721 ath5k_beacon_setup(struct ath5k_hw *ah, struct ath5k_buf *bf)
1722 {
1723 struct sk_buff *skb = bf->skb;
1724 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1725 struct ath5k_desc *ds;
1726 int ret = 0;
1727 u8 antenna;
1728 u32 flags;
1729 const int padsize = 0;
1730
1731 bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len,
1732 DMA_TO_DEVICE);
1733 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1734 "skbaddr %llx\n", skb, skb->data, skb->len,
1735 (unsigned long long)bf->skbaddr);
1736
1737 if (dma_mapping_error(ah->dev, bf->skbaddr)) {
1738 ATH5K_ERR(ah, "beacon DMA mapping failed\n");
1739 dev_kfree_skb_any(skb);
1740 bf->skb = NULL;
1741 return -EIO;
1742 }
1743
1744 ds = bf->desc;
1745 antenna = ah->ah_tx_ant;
1746
1747 flags = AR5K_TXDESC_NOACK;
1748 if (ah->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
1749 ds->ds_link = bf->daddr; /* self-linked */
1750 flags |= AR5K_TXDESC_VEOL;
1751 } else
1752 ds->ds_link = 0;
1753
1754 /*
1755 * If we use multiple antennas on AP and use
1756 * the Sectored AP scenario, switch antenna every
1757 * 4 beacons to make sure everybody hears our AP.
1758 * When a client tries to associate, hw will keep
1759 * track of the tx antenna to be used for this client
1760 * automatically, based on ACKed packets.
1761 *
1762 * Note: AP still listens and transmits RTS on the
1763 * default antenna which is supposed to be an omni.
1764 *
1765 * Note2: On sectored scenarios it's possible to have
1766 * multiple antennas (1 omni -- the default -- and 14
1767 * sectors), so if we choose to actually support this
1768 * mode, we need to allow the user to set how many antennas
1769 * we have and tweak the code below to send beacons
1770 * on all of them.
1771 */
1772 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
1773 antenna = ah->bsent & 4 ? 2 : 1;
1774
1775
1776 /* FIXME: If we are in g mode and rate is a CCK rate
1777 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1778 * from tx power (value is in dB units already) */
1779 ds->ds_data = bf->skbaddr;
1780 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
1781 ieee80211_get_hdrlen_from_skb(skb), padsize,
1782 AR5K_PKT_TYPE_BEACON,
1783 (ah->ah_txpower.txp_requested * 2),
1784 ieee80211_get_tx_rate(ah->hw, info)->hw_value,
1785 1, AR5K_TXKEYIX_INVALID,
1786 antenna, flags, 0, 0);
1787 if (ret)
1788 goto err_unmap;
1789
1790 return 0;
1791 err_unmap:
1792 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
1793 return ret;
1794 }
1795
1796 /*
1797 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
1798 * this is called only once at config_bss time, for AP we do it every
1799 * SWBA interrupt so that the TIM will reflect buffered frames.
1800 *
1801 * Called with the beacon lock.
1802 */
1803 int
1804 ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1805 {
1806 int ret;
1807 struct ath5k_hw *ah = hw->priv;
1808 struct ath5k_vif *avf;
1809 struct sk_buff *skb;
1810
1811 if (WARN_ON(!vif)) {
1812 ret = -EINVAL;
1813 goto out;
1814 }
1815
1816 skb = ieee80211_beacon_get(hw, vif);
1817
1818 if (!skb) {
1819 ret = -ENOMEM;
1820 goto out;
1821 }
1822
1823 avf = (void *)vif->drv_priv;
1824 ath5k_txbuf_free_skb(ah, avf->bbuf);
1825 avf->bbuf->skb = skb;
1826 ret = ath5k_beacon_setup(ah, avf->bbuf);
1827 out:
1828 return ret;
1829 }
1830
1831 /*
1832 * Transmit a beacon frame at SWBA. Dynamic updates to the
1833 * frame contents are done as needed and the slot time is
1834 * also adjusted based on current state.
1835 *
1836 * This is called from software irq context (beacontq tasklets)
1837 * or user context from ath5k_beacon_config.
1838 */
1839 static void
1840 ath5k_beacon_send(struct ath5k_hw *ah)
1841 {
1842 struct ieee80211_vif *vif;
1843 struct ath5k_vif *avf;
1844 struct ath5k_buf *bf;
1845 struct sk_buff *skb;
1846 int err;
1847
1848 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "in beacon_send\n");
1849
1850 /*
1851 * Check if the previous beacon has gone out. If
1852 * not, don't don't try to post another: skip this
1853 * period and wait for the next. Missed beacons
1854 * indicate a problem and should not occur. If we
1855 * miss too many consecutive beacons reset the device.
1856 */
1857 if (unlikely(ath5k_hw_num_tx_pending(ah, ah->bhalq) != 0)) {
1858 ah->bmisscount++;
1859 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1860 "missed %u consecutive beacons\n", ah->bmisscount);
1861 if (ah->bmisscount > 10) { /* NB: 10 is a guess */
1862 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1863 "stuck beacon time (%u missed)\n",
1864 ah->bmisscount);
1865 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
1866 "stuck beacon, resetting\n");
1867 ieee80211_queue_work(ah->hw, &ah->reset_work);
1868 }
1869 return;
1870 }
1871 if (unlikely(ah->bmisscount != 0)) {
1872 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1873 "resume beacon xmit after %u misses\n",
1874 ah->bmisscount);
1875 ah->bmisscount = 0;
1876 }
1877
1878 if ((ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs +
1879 ah->num_mesh_vifs > 1) ||
1880 ah->opmode == NL80211_IFTYPE_MESH_POINT) {
1881 u64 tsf = ath5k_hw_get_tsf64(ah);
1882 u32 tsftu = TSF_TO_TU(tsf);
1883 int slot = ((tsftu % ah->bintval) * ATH_BCBUF) / ah->bintval;
1884 vif = ah->bslot[(slot + 1) % ATH_BCBUF];
1885 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1886 "tsf %llx tsftu %x intval %u slot %u vif %p\n",
1887 (unsigned long long)tsf, tsftu, ah->bintval, slot, vif);
1888 } else /* only one interface */
1889 vif = ah->bslot[0];
1890
1891 if (!vif)
1892 return;
1893
1894 avf = (void *)vif->drv_priv;
1895 bf = avf->bbuf;
1896
1897 /*
1898 * Stop any current dma and put the new frame on the queue.
1899 * This should never fail since we check above that no frames
1900 * are still pending on the queue.
1901 */
1902 if (unlikely(ath5k_hw_stop_beacon_queue(ah, ah->bhalq))) {
1903 ATH5K_WARN(ah, "beacon queue %u didn't start/stop ?\n", ah->bhalq);
1904 /* NB: hw still stops DMA, so proceed */
1905 }
1906
1907 /* refresh the beacon for AP or MESH mode */
1908 if (ah->opmode == NL80211_IFTYPE_AP ||
1909 ah->opmode == NL80211_IFTYPE_MESH_POINT) {
1910 err = ath5k_beacon_update(ah->hw, vif);
1911 if (err)
1912 return;
1913 }
1914
1915 if (unlikely(bf->skb == NULL || ah->opmode == NL80211_IFTYPE_STATION ||
1916 ah->opmode == NL80211_IFTYPE_MONITOR)) {
1917 ATH5K_WARN(ah, "bf=%p bf_skb=%p\n", bf, bf->skb);
1918 return;
1919 }
1920
1921 trace_ath5k_tx(ah, bf->skb, &ah->txqs[ah->bhalq]);
1922
1923 ath5k_hw_set_txdp(ah, ah->bhalq, bf->daddr);
1924 ath5k_hw_start_tx_dma(ah, ah->bhalq);
1925 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
1926 ah->bhalq, (unsigned long long)bf->daddr, bf->desc);
1927
1928 skb = ieee80211_get_buffered_bc(ah->hw, vif);
1929 while (skb) {
1930 ath5k_tx_queue(ah->hw, skb, ah->cabq);
1931
1932 if (ah->cabq->txq_len >= ah->cabq->txq_max)
1933 break;
1934
1935 skb = ieee80211_get_buffered_bc(ah->hw, vif);
1936 }
1937
1938 ah->bsent++;
1939 }
1940
1941 /**
1942 * ath5k_beacon_update_timers - update beacon timers
1943 *
1944 * @ah: struct ath5k_hw pointer we are operating on
1945 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
1946 * beacon timer update based on the current HW TSF.
1947 *
1948 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
1949 * of a received beacon or the current local hardware TSF and write it to the
1950 * beacon timer registers.
1951 *
1952 * This is called in a variety of situations, e.g. when a beacon is received,
1953 * when a TSF update has been detected, but also when an new IBSS is created or
1954 * when we otherwise know we have to update the timers, but we keep it in this
1955 * function to have it all together in one place.
1956 */
1957 void
1958 ath5k_beacon_update_timers(struct ath5k_hw *ah, u64 bc_tsf)
1959 {
1960 u32 nexttbtt, intval, hw_tu, bc_tu;
1961 u64 hw_tsf;
1962
1963 intval = ah->bintval & AR5K_BEACON_PERIOD;
1964 if (ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs
1965 + ah->num_mesh_vifs > 1) {
1966 intval /= ATH_BCBUF; /* staggered multi-bss beacons */
1967 if (intval < 15)
1968 ATH5K_WARN(ah, "intval %u is too low, min 15\n",
1969 intval);
1970 }
1971 if (WARN_ON(!intval))
1972 return;
1973
1974 /* beacon TSF converted to TU */
1975 bc_tu = TSF_TO_TU(bc_tsf);
1976
1977 /* current TSF converted to TU */
1978 hw_tsf = ath5k_hw_get_tsf64(ah);
1979 hw_tu = TSF_TO_TU(hw_tsf);
1980
1981 #define FUDGE (AR5K_TUNE_SW_BEACON_RESP + 3)
1982 /* We use FUDGE to make sure the next TBTT is ahead of the current TU.
1983 * Since we later subtract AR5K_TUNE_SW_BEACON_RESP (10) in the timer
1984 * configuration we need to make sure it is bigger than that. */
1985
1986 if (bc_tsf == -1) {
1987 /*
1988 * no beacons received, called internally.
1989 * just need to refresh timers based on HW TSF.
1990 */
1991 nexttbtt = roundup(hw_tu + FUDGE, intval);
1992 } else if (bc_tsf == 0) {
1993 /*
1994 * no beacon received, probably called by ath5k_reset_tsf().
1995 * reset TSF to start with 0.
1996 */
1997 nexttbtt = intval;
1998 intval |= AR5K_BEACON_RESET_TSF;
1999 } else if (bc_tsf > hw_tsf) {
2000 /*
2001 * beacon received, SW merge happened but HW TSF not yet updated.
2002 * not possible to reconfigure timers yet, but next time we
2003 * receive a beacon with the same BSSID, the hardware will
2004 * automatically update the TSF and then we need to reconfigure
2005 * the timers.
2006 */
2007 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
2008 "need to wait for HW TSF sync\n");
2009 return;
2010 } else {
2011 /*
2012 * most important case for beacon synchronization between STA.
2013 *
2014 * beacon received and HW TSF has been already updated by HW.
2015 * update next TBTT based on the TSF of the beacon, but make
2016 * sure it is ahead of our local TSF timer.
2017 */
2018 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2019 }
2020 #undef FUDGE
2021
2022 ah->nexttbtt = nexttbtt;
2023
2024 intval |= AR5K_BEACON_ENA;
2025 ath5k_hw_init_beacon_timers(ah, nexttbtt, intval);
2026
2027 /*
2028 * debugging output last in order to preserve the time critical aspect
2029 * of this function
2030 */
2031 if (bc_tsf == -1)
2032 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
2033 "reconfigured timers based on HW TSF\n");
2034 else if (bc_tsf == 0)
2035 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
2036 "reset HW TSF and timers\n");
2037 else
2038 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
2039 "updated timers based on beacon TSF\n");
2040
2041 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
2042 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2043 (unsigned long long) bc_tsf,
2044 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2045 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2046 intval & AR5K_BEACON_PERIOD,
2047 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2048 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2049 }
2050
2051 /**
2052 * ath5k_beacon_config - Configure the beacon queues and interrupts
2053 *
2054 * @ah: struct ath5k_hw pointer we are operating on
2055 *
2056 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2057 * interrupts to detect TSF updates only.
2058 */
2059 void
2060 ath5k_beacon_config(struct ath5k_hw *ah)
2061 {
2062 spin_lock_bh(&ah->block);
2063 ah->bmisscount = 0;
2064 ah->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2065
2066 if (ah->enable_beacon) {
2067 /*
2068 * In IBSS mode we use a self-linked tx descriptor and let the
2069 * hardware send the beacons automatically. We have to load it
2070 * only once here.
2071 * We use the SWBA interrupt only to keep track of the beacon
2072 * timers in order to detect automatic TSF updates.
2073 */
2074 ath5k_beaconq_config(ah);
2075
2076 ah->imask |= AR5K_INT_SWBA;
2077
2078 if (ah->opmode == NL80211_IFTYPE_ADHOC) {
2079 if (ath5k_hw_hasveol(ah))
2080 ath5k_beacon_send(ah);
2081 } else
2082 ath5k_beacon_update_timers(ah, -1);
2083 } else {
2084 ath5k_hw_stop_beacon_queue(ah, ah->bhalq);
2085 }
2086
2087 ath5k_hw_set_imr(ah, ah->imask);
2088 mmiowb();
2089 spin_unlock_bh(&ah->block);
2090 }
2091
2092 static void ath5k_tasklet_beacon(unsigned long data)
2093 {
2094 struct ath5k_hw *ah = (struct ath5k_hw *) data;
2095
2096 /*
2097 * Software beacon alert--time to send a beacon.
2098 *
2099 * In IBSS mode we use this interrupt just to
2100 * keep track of the next TBTT (target beacon
2101 * transmission time) in order to detect whether
2102 * automatic TSF updates happened.
2103 */
2104 if (ah->opmode == NL80211_IFTYPE_ADHOC) {
2105 /* XXX: only if VEOL supported */
2106 u64 tsf = ath5k_hw_get_tsf64(ah);
2107 ah->nexttbtt += ah->bintval;
2108 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
2109 "SWBA nexttbtt: %x hw_tu: %x "
2110 "TSF: %llx\n",
2111 ah->nexttbtt,
2112 TSF_TO_TU(tsf),
2113 (unsigned long long) tsf);
2114 } else {
2115 spin_lock(&ah->block);
2116 ath5k_beacon_send(ah);
2117 spin_unlock(&ah->block);
2118 }
2119 }
2120
2121
2122 /********************\
2123 * Interrupt handling *
2124 \********************/
2125
2126 static void
2127 ath5k_intr_calibration_poll(struct ath5k_hw *ah)
2128 {
2129 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) &&
2130 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL) &&
2131 !(ah->ah_cal_mask & AR5K_CALIBRATION_SHORT)) {
2132
2133 /* Run ANI only when calibration is not active */
2134
2135 ah->ah_cal_next_ani = jiffies +
2136 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
2137 tasklet_schedule(&ah->ani_tasklet);
2138
2139 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_short) &&
2140 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL) &&
2141 !(ah->ah_cal_mask & AR5K_CALIBRATION_SHORT)) {
2142
2143 /* Run calibration only when another calibration
2144 * is not running.
2145 *
2146 * Note: This is for both full/short calibration,
2147 * if it's time for a full one, ath5k_calibrate_work will deal
2148 * with it. */
2149
2150 ah->ah_cal_next_short = jiffies +
2151 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_SHORT);
2152 ieee80211_queue_work(ah->hw, &ah->calib_work);
2153 }
2154 /* we could use SWI to generate enough interrupts to meet our
2155 * calibration interval requirements, if necessary:
2156 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */
2157 }
2158
2159 static void
2160 ath5k_schedule_rx(struct ath5k_hw *ah)
2161 {
2162 ah->rx_pending = true;
2163 tasklet_schedule(&ah->rxtq);
2164 }
2165
2166 static void
2167 ath5k_schedule_tx(struct ath5k_hw *ah)
2168 {
2169 ah->tx_pending = true;
2170 tasklet_schedule(&ah->txtq);
2171 }
2172
2173 static irqreturn_t
2174 ath5k_intr(int irq, void *dev_id)
2175 {
2176 struct ath5k_hw *ah = dev_id;
2177 enum ath5k_int status;
2178 unsigned int counter = 1000;
2179
2180
2181 /*
2182 * If hw is not ready (or detached) and we get an
2183 * interrupt, or if we have no interrupts pending
2184 * (that means it's not for us) skip it.
2185 *
2186 * NOTE: Group 0/1 PCI interface registers are not
2187 * supported on WiSOCs, so we can't check for pending
2188 * interrupts (ISR belongs to another register group
2189 * so we are ok).
2190 */
2191 if (unlikely(test_bit(ATH_STAT_INVALID, ah->status) ||
2192 ((ath5k_get_bus_type(ah) != ATH_AHB) &&
2193 !ath5k_hw_is_intr_pending(ah))))
2194 return IRQ_NONE;
2195
2196 /** Main loop **/
2197 do {
2198 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2199
2200 ATH5K_DBG(ah, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2201 status, ah->imask);
2202
2203 /*
2204 * Fatal hw error -> Log and reset
2205 *
2206 * Fatal errors are unrecoverable so we have to
2207 * reset the card. These errors include bus and
2208 * dma errors.
2209 */
2210 if (unlikely(status & AR5K_INT_FATAL)) {
2211
2212 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2213 "fatal int, resetting\n");
2214 ieee80211_queue_work(ah->hw, &ah->reset_work);
2215
2216 /*
2217 * RX Overrun -> Count and reset if needed
2218 *
2219 * Receive buffers are full. Either the bus is busy or
2220 * the CPU is not fast enough to process all received
2221 * frames.
2222 */
2223 } else if (unlikely(status & AR5K_INT_RXORN)) {
2224
2225 /*
2226 * Older chipsets need a reset to come out of this
2227 * condition, but we treat it as RX for newer chips.
2228 * We don't know exactly which versions need a reset
2229 * this guess is copied from the HAL.
2230 */
2231 ah->stats.rxorn_intr++;
2232
2233 if (ah->ah_mac_srev < AR5K_SREV_AR5212) {
2234 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2235 "rx overrun, resetting\n");
2236 ieee80211_queue_work(ah->hw, &ah->reset_work);
2237 } else
2238 ath5k_schedule_rx(ah);
2239
2240 } else {
2241
2242 /* Software Beacon Alert -> Schedule beacon tasklet */
2243 if (status & AR5K_INT_SWBA)
2244 tasklet_hi_schedule(&ah->beacontq);
2245
2246 /*
2247 * No more RX descriptors -> Just count
2248 *
2249 * NB: the hardware should re-read the link when
2250 * RXE bit is written, but it doesn't work at
2251 * least on older hardware revs.
2252 */
2253 if (status & AR5K_INT_RXEOL)
2254 ah->stats.rxeol_intr++;
2255
2256
2257 /* TX Underrun -> Bump tx trigger level */
2258 if (status & AR5K_INT_TXURN)
2259 ath5k_hw_update_tx_triglevel(ah, true);
2260
2261 /* RX -> Schedule rx tasklet */
2262 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
2263 ath5k_schedule_rx(ah);
2264
2265 /* TX -> Schedule tx tasklet */
2266 if (status & (AR5K_INT_TXOK
2267 | AR5K_INT_TXDESC
2268 | AR5K_INT_TXERR
2269 | AR5K_INT_TXEOL))
2270 ath5k_schedule_tx(ah);
2271
2272 /* Missed beacon -> TODO
2273 if (status & AR5K_INT_BMISS)
2274 */
2275
2276 /* MIB event -> Update counters and notify ANI */
2277 if (status & AR5K_INT_MIB) {
2278 ah->stats.mib_intr++;
2279 ath5k_hw_update_mib_counters(ah);
2280 ath5k_ani_mib_intr(ah);
2281 }
2282
2283 /* GPIO -> Notify RFKill layer */
2284 if (status & AR5K_INT_GPIO)
2285 tasklet_schedule(&ah->rf_kill.toggleq);
2286
2287 }
2288
2289 if (ath5k_get_bus_type(ah) == ATH_AHB)
2290 break;
2291
2292 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
2293
2294 /*
2295 * Until we handle rx/tx interrupts mask them on IMR
2296 *
2297 * NOTE: ah->(rx/tx)_pending are set when scheduling the tasklets
2298 * and unset after we 've handled the interrupts.
2299 */
2300 if (ah->rx_pending || ah->tx_pending)
2301 ath5k_set_current_imask(ah);
2302
2303 if (unlikely(!counter))
2304 ATH5K_WARN(ah, "too many interrupts, giving up for now\n");
2305
2306 /* Fire up calibration poll */
2307 ath5k_intr_calibration_poll(ah);
2308
2309 return IRQ_HANDLED;
2310 }
2311
2312 /*
2313 * Periodically recalibrate the PHY to account
2314 * for temperature/environment changes.
2315 */
2316 static void
2317 ath5k_calibrate_work(struct work_struct *work)
2318 {
2319 struct ath5k_hw *ah = container_of(work, struct ath5k_hw,
2320 calib_work);
2321
2322 /* Should we run a full calibration ? */
2323 if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) {
2324
2325 ah->ah_cal_next_full = jiffies +
2326 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2327 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL;
2328
2329 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE,
2330 "running full calibration\n");
2331
2332 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2333 /*
2334 * Rfgain is out of bounds, reset the chip
2335 * to load new gain values.
2336 */
2337 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2338 "got new rfgain, resetting\n");
2339 ieee80211_queue_work(ah->hw, &ah->reset_work);
2340 }
2341 } else
2342 ah->ah_cal_mask |= AR5K_CALIBRATION_SHORT;
2343
2344
2345 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2346 ieee80211_frequency_to_channel(ah->curchan->center_freq),
2347 ah->curchan->hw_value);
2348
2349 if (ath5k_hw_phy_calibrate(ah, ah->curchan))
2350 ATH5K_ERR(ah, "calibration of channel %u failed\n",
2351 ieee80211_frequency_to_channel(
2352 ah->curchan->center_freq));
2353
2354 /* Clear calibration flags */
2355 if (ah->ah_cal_mask & AR5K_CALIBRATION_FULL)
2356 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL;
2357 else if (ah->ah_cal_mask & AR5K_CALIBRATION_SHORT)
2358 ah->ah_cal_mask &= ~AR5K_CALIBRATION_SHORT;
2359 }
2360
2361
2362 static void
2363 ath5k_tasklet_ani(unsigned long data)
2364 {
2365 struct ath5k_hw *ah = (void *)data;
2366
2367 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI;
2368 ath5k_ani_calibration(ah);
2369 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI;
2370 }
2371
2372
2373 static void
2374 ath5k_tx_complete_poll_work(struct work_struct *work)
2375 {
2376 struct ath5k_hw *ah = container_of(work, struct ath5k_hw,
2377 tx_complete_work.work);
2378 struct ath5k_txq *txq;
2379 int i;
2380 bool needreset = false;
2381
2382 mutex_lock(&ah->lock);
2383
2384 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) {
2385 if (ah->txqs[i].setup) {
2386 txq = &ah->txqs[i];
2387 spin_lock_bh(&txq->lock);
2388 if (txq->txq_len > 1) {
2389 if (txq->txq_poll_mark) {
2390 ATH5K_DBG(ah, ATH5K_DEBUG_XMIT,
2391 "TX queue stuck %d\n",
2392 txq->qnum);
2393 needreset = true;
2394 txq->txq_stuck++;
2395 spin_unlock_bh(&txq->lock);
2396 break;
2397 } else {
2398 txq->txq_poll_mark = true;
2399 }
2400 }
2401 spin_unlock_bh(&txq->lock);
2402 }
2403 }
2404
2405 if (needreset) {
2406 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2407 "TX queues stuck, resetting\n");
2408 ath5k_reset(ah, NULL, true);
2409 }
2410
2411 mutex_unlock(&ah->lock);
2412
2413 ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work,
2414 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2415 }
2416
2417
2418 /*************************\
2419 * Initialization routines *
2420 \*************************/
2421
2422 static const struct ieee80211_iface_limit if_limits[] = {
2423 { .max = 2048, .types = BIT(NL80211_IFTYPE_STATION) },
2424 { .max = 4, .types =
2425 #ifdef CONFIG_MAC80211_MESH
2426 BIT(NL80211_IFTYPE_MESH_POINT) |
2427 #endif
2428 BIT(NL80211_IFTYPE_AP) },
2429 };
2430
2431 static const struct ieee80211_iface_combination if_comb = {
2432 .limits = if_limits,
2433 .n_limits = ARRAY_SIZE(if_limits),
2434 .max_interfaces = 2048,
2435 .num_different_channels = 1,
2436 };
2437
2438 int __devinit
2439 ath5k_init_ah(struct ath5k_hw *ah, const struct ath_bus_ops *bus_ops)
2440 {
2441 struct ieee80211_hw *hw = ah->hw;
2442 struct ath_common *common;
2443 int ret;
2444 int csz;
2445
2446 /* Initialize driver private data */
2447 SET_IEEE80211_DEV(hw, ah->dev);
2448 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
2449 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2450 IEEE80211_HW_SIGNAL_DBM |
2451 IEEE80211_HW_MFP_CAPABLE |
2452 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
2453
2454 hw->wiphy->interface_modes =
2455 BIT(NL80211_IFTYPE_AP) |
2456 BIT(NL80211_IFTYPE_STATION) |
2457 BIT(NL80211_IFTYPE_ADHOC) |
2458 BIT(NL80211_IFTYPE_MESH_POINT);
2459
2460 hw->wiphy->iface_combinations = &if_comb;
2461 hw->wiphy->n_iface_combinations = 1;
2462
2463 /* SW support for IBSS_RSN is provided by mac80211 */
2464 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
2465
2466 /* both antennas can be configured as RX or TX */
2467 hw->wiphy->available_antennas_tx = 0x3;
2468 hw->wiphy->available_antennas_rx = 0x3;
2469
2470 hw->extra_tx_headroom = 2;
2471 hw->channel_change_time = 5000;
2472
2473 /*
2474 * Mark the device as detached to avoid processing
2475 * interrupts until setup is complete.
2476 */
2477 __set_bit(ATH_STAT_INVALID, ah->status);
2478
2479 ah->opmode = NL80211_IFTYPE_STATION;
2480 ah->bintval = 1000;
2481 mutex_init(&ah->lock);
2482 spin_lock_init(&ah->rxbuflock);
2483 spin_lock_init(&ah->txbuflock);
2484 spin_lock_init(&ah->block);
2485 spin_lock_init(&ah->irqlock);
2486
2487 /* Setup interrupt handler */
2488 ret = request_irq(ah->irq, ath5k_intr, IRQF_SHARED, "ath", ah);
2489 if (ret) {
2490 ATH5K_ERR(ah, "request_irq failed\n");
2491 goto err;
2492 }
2493
2494 common = ath5k_hw_common(ah);
2495 common->ops = &ath5k_common_ops;
2496 common->bus_ops = bus_ops;
2497 common->ah = ah;
2498 common->hw = hw;
2499 common->priv = ah;
2500 common->clockrate = 40;
2501
2502 /*
2503 * Cache line size is used to size and align various
2504 * structures used to communicate with the hardware.
2505 */
2506 ath5k_read_cachesize(common, &csz);
2507 common->cachelsz = csz << 2; /* convert to bytes */
2508
2509 spin_lock_init(&common->cc_lock);
2510
2511 /* Initialize device */
2512 ret = ath5k_hw_init(ah);
2513 if (ret)
2514 goto err_irq;
2515
2516 /* Set up multi-rate retry capabilities */
2517 if (ah->ah_capabilities.cap_has_mrr_support) {
2518 hw->max_rates = 4;
2519 hw->max_rate_tries = max(AR5K_INIT_RETRY_SHORT,
2520 AR5K_INIT_RETRY_LONG);
2521 }
2522
2523 hw->vif_data_size = sizeof(struct ath5k_vif);
2524
2525 /* Finish private driver data initialization */
2526 ret = ath5k_init(hw);
2527 if (ret)
2528 goto err_ah;
2529
2530 ATH5K_INFO(ah, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
2531 ath5k_chip_name(AR5K_VERSION_MAC, ah->ah_mac_srev),
2532 ah->ah_mac_srev,
2533 ah->ah_phy_revision);
2534
2535 if (!ah->ah_single_chip) {
2536 /* Single chip radio (!RF5111) */
2537 if (ah->ah_radio_5ghz_revision &&
2538 !ah->ah_radio_2ghz_revision) {
2539 /* No 5GHz support -> report 2GHz radio */
2540 if (!test_bit(AR5K_MODE_11A,
2541 ah->ah_capabilities.cap_mode)) {
2542 ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n",
2543 ath5k_chip_name(AR5K_VERSION_RAD,
2544 ah->ah_radio_5ghz_revision),
2545 ah->ah_radio_5ghz_revision);
2546 /* No 2GHz support (5110 and some
2547 * 5GHz only cards) -> report 5GHz radio */
2548 } else if (!test_bit(AR5K_MODE_11B,
2549 ah->ah_capabilities.cap_mode)) {
2550 ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n",
2551 ath5k_chip_name(AR5K_VERSION_RAD,
2552 ah->ah_radio_5ghz_revision),
2553 ah->ah_radio_5ghz_revision);
2554 /* Multiband radio */
2555 } else {
2556 ATH5K_INFO(ah, "RF%s multiband radio found"
2557 " (0x%x)\n",
2558 ath5k_chip_name(AR5K_VERSION_RAD,
2559 ah->ah_radio_5ghz_revision),
2560 ah->ah_radio_5ghz_revision);
2561 }
2562 }
2563 /* Multi chip radio (RF5111 - RF2111) ->
2564 * report both 2GHz/5GHz radios */
2565 else if (ah->ah_radio_5ghz_revision &&
2566 ah->ah_radio_2ghz_revision) {
2567 ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n",
2568 ath5k_chip_name(AR5K_VERSION_RAD,
2569 ah->ah_radio_5ghz_revision),
2570 ah->ah_radio_5ghz_revision);
2571 ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n",
2572 ath5k_chip_name(AR5K_VERSION_RAD,
2573 ah->ah_radio_2ghz_revision),
2574 ah->ah_radio_2ghz_revision);
2575 }
2576 }
2577
2578 ath5k_debug_init_device(ah);
2579
2580 /* ready to process interrupts */
2581 __clear_bit(ATH_STAT_INVALID, ah->status);
2582
2583 return 0;
2584 err_ah:
2585 ath5k_hw_deinit(ah);
2586 err_irq:
2587 free_irq(ah->irq, ah);
2588 err:
2589 return ret;
2590 }
2591
2592 static int
2593 ath5k_stop_locked(struct ath5k_hw *ah)
2594 {
2595
2596 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "invalid %u\n",
2597 test_bit(ATH_STAT_INVALID, ah->status));
2598
2599 /*
2600 * Shutdown the hardware and driver:
2601 * stop output from above
2602 * disable interrupts
2603 * turn off timers
2604 * turn off the radio
2605 * clear transmit machinery
2606 * clear receive machinery
2607 * drain and release tx queues
2608 * reclaim beacon resources
2609 * power down hardware
2610 *
2611 * Note that some of this work is not possible if the
2612 * hardware is gone (invalid).
2613 */
2614 ieee80211_stop_queues(ah->hw);
2615
2616 if (!test_bit(ATH_STAT_INVALID, ah->status)) {
2617 ath5k_led_off(ah);
2618 ath5k_hw_set_imr(ah, 0);
2619 synchronize_irq(ah->irq);
2620 ath5k_rx_stop(ah);
2621 ath5k_hw_dma_stop(ah);
2622 ath5k_drain_tx_buffs(ah);
2623 ath5k_hw_phy_disable(ah);
2624 }
2625
2626 return 0;
2627 }
2628
2629 int ath5k_start(struct ieee80211_hw *hw)
2630 {
2631 struct ath5k_hw *ah = hw->priv;
2632 struct ath_common *common = ath5k_hw_common(ah);
2633 int ret, i;
2634
2635 mutex_lock(&ah->lock);
2636
2637 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "mode %d\n", ah->opmode);
2638
2639 /*
2640 * Stop anything previously setup. This is safe
2641 * no matter this is the first time through or not.
2642 */
2643 ath5k_stop_locked(ah);
2644
2645 /*
2646 * The basic interface to setting the hardware in a good
2647 * state is ``reset''. On return the hardware is known to
2648 * be powered up and with interrupts disabled. This must
2649 * be followed by initialization of the appropriate bits
2650 * and then setup of the interrupt mask.
2651 */
2652 ah->curchan = ah->hw->conf.channel;
2653 ah->imask = AR5K_INT_RXOK
2654 | AR5K_INT_RXERR
2655 | AR5K_INT_RXEOL
2656 | AR5K_INT_RXORN
2657 | AR5K_INT_TXDESC
2658 | AR5K_INT_TXEOL
2659 | AR5K_INT_FATAL
2660 | AR5K_INT_GLOBAL
2661 | AR5K_INT_MIB;
2662
2663 ret = ath5k_reset(ah, NULL, false);
2664 if (ret)
2665 goto done;
2666
2667 if (!ath5k_modparam_no_hw_rfkill_switch)
2668 ath5k_rfkill_hw_start(ah);
2669
2670 /*
2671 * Reset the key cache since some parts do not reset the
2672 * contents on initial power up or resume from suspend.
2673 */
2674 for (i = 0; i < common->keymax; i++)
2675 ath_hw_keyreset(common, (u16) i);
2676
2677 /* Use higher rates for acks instead of base
2678 * rate */
2679 ah->ah_ack_bitrate_high = true;
2680
2681 for (i = 0; i < ARRAY_SIZE(ah->bslot); i++)
2682 ah->bslot[i] = NULL;
2683
2684 ret = 0;
2685 done:
2686 mmiowb();
2687 mutex_unlock(&ah->lock);
2688
2689 ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work,
2690 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2691
2692 return ret;
2693 }
2694
2695 static void ath5k_stop_tasklets(struct ath5k_hw *ah)
2696 {
2697 ah->rx_pending = false;
2698 ah->tx_pending = false;
2699 tasklet_kill(&ah->rxtq);
2700 tasklet_kill(&ah->txtq);
2701 tasklet_kill(&ah->beacontq);
2702 tasklet_kill(&ah->ani_tasklet);
2703 }
2704
2705 /*
2706 * Stop the device, grabbing the top-level lock to protect
2707 * against concurrent entry through ath5k_init (which can happen
2708 * if another thread does a system call and the thread doing the
2709 * stop is preempted).
2710 */
2711 void ath5k_stop(struct ieee80211_hw *hw)
2712 {
2713 struct ath5k_hw *ah = hw->priv;
2714 int ret;
2715
2716 mutex_lock(&ah->lock);
2717 ret = ath5k_stop_locked(ah);
2718 if (ret == 0 && !test_bit(ATH_STAT_INVALID, ah->status)) {
2719 /*
2720 * Don't set the card in full sleep mode!
2721 *
2722 * a) When the device is in this state it must be carefully
2723 * woken up or references to registers in the PCI clock
2724 * domain may freeze the bus (and system). This varies
2725 * by chip and is mostly an issue with newer parts
2726 * (madwifi sources mentioned srev >= 0x78) that go to
2727 * sleep more quickly.
2728 *
2729 * b) On older chips full sleep results a weird behaviour
2730 * during wakeup. I tested various cards with srev < 0x78
2731 * and they don't wake up after module reload, a second
2732 * module reload is needed to bring the card up again.
2733 *
2734 * Until we figure out what's going on don't enable
2735 * full chip reset on any chip (this is what Legacy HAL
2736 * and Sam's HAL do anyway). Instead Perform a full reset
2737 * on the device (same as initial state after attach) and
2738 * leave it idle (keep MAC/BB on warm reset) */
2739 ret = ath5k_hw_on_hold(ah);
2740
2741 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2742 "putting device to sleep\n");
2743 }
2744
2745 mmiowb();
2746 mutex_unlock(&ah->lock);
2747
2748 ath5k_stop_tasklets(ah);
2749
2750 cancel_delayed_work_sync(&ah->tx_complete_work);
2751
2752 if (!ath5k_modparam_no_hw_rfkill_switch)
2753 ath5k_rfkill_hw_stop(ah);
2754 }
2755
2756 /*
2757 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2758 * and change to the given channel.
2759 *
2760 * This should be called with ah->lock.
2761 */
2762 static int
2763 ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan,
2764 bool skip_pcu)
2765 {
2766 struct ath_common *common = ath5k_hw_common(ah);
2767 int ret, ani_mode;
2768 bool fast;
2769
2770 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "resetting\n");
2771
2772 ath5k_hw_set_imr(ah, 0);
2773 synchronize_irq(ah->irq);
2774 ath5k_stop_tasklets(ah);
2775
2776 /* Save ani mode and disable ANI during
2777 * reset. If we don't we might get false
2778 * PHY error interrupts. */
2779 ani_mode = ah->ani_state.ani_mode;
2780 ath5k_ani_init(ah, ATH5K_ANI_MODE_OFF);
2781
2782 /* We are going to empty hw queues
2783 * so we should also free any remaining
2784 * tx buffers */
2785 ath5k_drain_tx_buffs(ah);
2786 if (chan)
2787 ah->curchan = chan;
2788
2789 fast = ((chan != NULL) && modparam_fastchanswitch) ? 1 : 0;
2790
2791 ret = ath5k_hw_reset(ah, ah->opmode, ah->curchan, fast, skip_pcu);
2792 if (ret) {
2793 ATH5K_ERR(ah, "can't reset hardware (%d)\n", ret);
2794 goto err;
2795 }
2796
2797 ret = ath5k_rx_start(ah);
2798 if (ret) {
2799 ATH5K_ERR(ah, "can't start recv logic\n");
2800 goto err;
2801 }
2802
2803 ath5k_ani_init(ah, ani_mode);
2804
2805 /*
2806 * Set calibration intervals
2807 *
2808 * Note: We don't need to run calibration imediately
2809 * since some initial calibration is done on reset
2810 * even for fast channel switching. Also on scanning
2811 * this will get set again and again and it won't get
2812 * executed unless we connect somewhere and spend some
2813 * time on the channel (that's what calibration needs
2814 * anyway to be accurate).
2815 */
2816 ah->ah_cal_next_full = jiffies +
2817 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2818 ah->ah_cal_next_ani = jiffies +
2819 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
2820 ah->ah_cal_next_short = jiffies +
2821 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_SHORT);
2822
2823 ewma_init(&ah->ah_beacon_rssi_avg, 1024, 8);
2824
2825 /* clear survey data and cycle counters */
2826 memset(&ah->survey, 0, sizeof(ah->survey));
2827 spin_lock_bh(&common->cc_lock);
2828 ath_hw_cycle_counters_update(common);
2829 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
2830 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
2831 spin_unlock_bh(&common->cc_lock);
2832
2833 /*
2834 * Change channels and update the h/w rate map if we're switching;
2835 * e.g. 11a to 11b/g.
2836 *
2837 * We may be doing a reset in response to an ioctl that changes the
2838 * channel so update any state that might change as a result.
2839 *
2840 * XXX needed?
2841 */
2842 /* ath5k_chan_change(ah, c); */
2843
2844 ath5k_beacon_config(ah);
2845 /* intrs are enabled by ath5k_beacon_config */
2846
2847 ieee80211_wake_queues(ah->hw);
2848
2849 return 0;
2850 err:
2851 return ret;
2852 }
2853
2854 static void ath5k_reset_work(struct work_struct *work)
2855 {
2856 struct ath5k_hw *ah = container_of(work, struct ath5k_hw,
2857 reset_work);
2858
2859 mutex_lock(&ah->lock);
2860 ath5k_reset(ah, NULL, true);
2861 mutex_unlock(&ah->lock);
2862 }
2863
2864 static int __devinit
2865 ath5k_init(struct ieee80211_hw *hw)
2866 {
2867
2868 struct ath5k_hw *ah = hw->priv;
2869 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
2870 struct ath5k_txq *txq;
2871 u8 mac[ETH_ALEN] = {};
2872 int ret;
2873
2874
2875 /*
2876 * Collect the channel list. The 802.11 layer
2877 * is responsible for filtering this list based
2878 * on settings like the phy mode and regulatory
2879 * domain restrictions.
2880 */
2881 ret = ath5k_setup_bands(hw);
2882 if (ret) {
2883 ATH5K_ERR(ah, "can't get channels\n");
2884 goto err;
2885 }
2886
2887 /*
2888 * Allocate tx+rx descriptors and populate the lists.
2889 */
2890 ret = ath5k_desc_alloc(ah);
2891 if (ret) {
2892 ATH5K_ERR(ah, "can't allocate descriptors\n");
2893 goto err;
2894 }
2895
2896 /*
2897 * Allocate hardware transmit queues: one queue for
2898 * beacon frames and one data queue for each QoS
2899 * priority. Note that hw functions handle resetting
2900 * these queues at the needed time.
2901 */
2902 ret = ath5k_beaconq_setup(ah);
2903 if (ret < 0) {
2904 ATH5K_ERR(ah, "can't setup a beacon xmit queue\n");
2905 goto err_desc;
2906 }
2907 ah->bhalq = ret;
2908 ah->cabq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_CAB, 0);
2909 if (IS_ERR(ah->cabq)) {
2910 ATH5K_ERR(ah, "can't setup cab queue\n");
2911 ret = PTR_ERR(ah->cabq);
2912 goto err_bhal;
2913 }
2914
2915 /* 5211 and 5212 usually support 10 queues but we better rely on the
2916 * capability information */
2917 if (ah->ah_capabilities.cap_queues.q_tx_num >= 6) {
2918 /* This order matches mac80211's queue priority, so we can
2919 * directly use the mac80211 queue number without any mapping */
2920 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO);
2921 if (IS_ERR(txq)) {
2922 ATH5K_ERR(ah, "can't setup xmit queue\n");
2923 ret = PTR_ERR(txq);
2924 goto err_queues;
2925 }
2926 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI);
2927 if (IS_ERR(txq)) {
2928 ATH5K_ERR(ah, "can't setup xmit queue\n");
2929 ret = PTR_ERR(txq);
2930 goto err_queues;
2931 }
2932 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
2933 if (IS_ERR(txq)) {
2934 ATH5K_ERR(ah, "can't setup xmit queue\n");
2935 ret = PTR_ERR(txq);
2936 goto err_queues;
2937 }
2938 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
2939 if (IS_ERR(txq)) {
2940 ATH5K_ERR(ah, "can't setup xmit queue\n");
2941 ret = PTR_ERR(txq);
2942 goto err_queues;
2943 }
2944 hw->queues = 4;
2945 } else {
2946 /* older hardware (5210) can only support one data queue */
2947 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
2948 if (IS_ERR(txq)) {
2949 ATH5K_ERR(ah, "can't setup xmit queue\n");
2950 ret = PTR_ERR(txq);
2951 goto err_queues;
2952 }
2953 hw->queues = 1;
2954 }
2955
2956 tasklet_init(&ah->rxtq, ath5k_tasklet_rx, (unsigned long)ah);
2957 tasklet_init(&ah->txtq, ath5k_tasklet_tx, (unsigned long)ah);
2958 tasklet_init(&ah->beacontq, ath5k_tasklet_beacon, (unsigned long)ah);
2959 tasklet_init(&ah->ani_tasklet, ath5k_tasklet_ani, (unsigned long)ah);
2960
2961 INIT_WORK(&ah->reset_work, ath5k_reset_work);
2962 INIT_WORK(&ah->calib_work, ath5k_calibrate_work);
2963 INIT_DELAYED_WORK(&ah->tx_complete_work, ath5k_tx_complete_poll_work);
2964
2965 ret = ath5k_hw_common(ah)->bus_ops->eeprom_read_mac(ah, mac);
2966 if (ret) {
2967 ATH5K_ERR(ah, "unable to read address from EEPROM\n");
2968 goto err_queues;
2969 }
2970
2971 SET_IEEE80211_PERM_ADDR(hw, mac);
2972 /* All MAC address bits matter for ACKs */
2973 ath5k_update_bssid_mask_and_opmode(ah, NULL);
2974
2975 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
2976 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
2977 if (ret) {
2978 ATH5K_ERR(ah, "can't initialize regulatory system\n");
2979 goto err_queues;
2980 }
2981
2982 ret = ieee80211_register_hw(hw);
2983 if (ret) {
2984 ATH5K_ERR(ah, "can't register ieee80211 hw\n");
2985 goto err_queues;
2986 }
2987
2988 if (!ath_is_world_regd(regulatory))
2989 regulatory_hint(hw->wiphy, regulatory->alpha2);
2990
2991 ath5k_init_leds(ah);
2992
2993 ath5k_sysfs_register(ah);
2994
2995 return 0;
2996 err_queues:
2997 ath5k_txq_release(ah);
2998 err_bhal:
2999 ath5k_hw_release_tx_queue(ah, ah->bhalq);
3000 err_desc:
3001 ath5k_desc_free(ah);
3002 err:
3003 return ret;
3004 }
3005
3006 void
3007 ath5k_deinit_ah(struct ath5k_hw *ah)
3008 {
3009 struct ieee80211_hw *hw = ah->hw;
3010
3011 /*
3012 * NB: the order of these is important:
3013 * o call the 802.11 layer before detaching ath5k_hw to
3014 * ensure callbacks into the driver to delete global
3015 * key cache entries can be handled
3016 * o reclaim the tx queue data structures after calling
3017 * the 802.11 layer as we'll get called back to reclaim
3018 * node state and potentially want to use them
3019 * o to cleanup the tx queues the hal is called, so detach
3020 * it last
3021 * XXX: ??? detach ath5k_hw ???
3022 * Other than that, it's straightforward...
3023 */
3024 ieee80211_unregister_hw(hw);
3025 ath5k_desc_free(ah);
3026 ath5k_txq_release(ah);
3027 ath5k_hw_release_tx_queue(ah, ah->bhalq);
3028 ath5k_unregister_leds(ah);
3029
3030 ath5k_sysfs_unregister(ah);
3031 /*
3032 * NB: can't reclaim these until after ieee80211_ifdetach
3033 * returns because we'll get called back to reclaim node
3034 * state and potentially want to use them.
3035 */
3036 ath5k_hw_deinit(ah);
3037 free_irq(ah->irq, ah);
3038 }
3039
3040 bool
3041 ath5k_any_vif_assoc(struct ath5k_hw *ah)
3042 {
3043 struct ath5k_vif_iter_data iter_data;
3044 iter_data.hw_macaddr = NULL;
3045 iter_data.any_assoc = false;
3046 iter_data.need_set_hw_addr = false;
3047 iter_data.found_active = true;
3048
3049 ieee80211_iterate_active_interfaces_atomic(
3050 ah->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
3051 ath5k_vif_iter, &iter_data);
3052 return iter_data.any_assoc;
3053 }
3054
3055 void
3056 ath5k_set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3057 {
3058 struct ath5k_hw *ah = hw->priv;
3059 u32 rfilt;
3060 rfilt = ath5k_hw_get_rx_filter(ah);
3061 if (enable)
3062 rfilt |= AR5K_RX_FILTER_BEACON;
3063 else
3064 rfilt &= ~AR5K_RX_FILTER_BEACON;
3065 ath5k_hw_set_rx_filter(ah, rfilt);
3066 ah->filter_flags = rfilt;
3067 }
3068
3069 void _ath5k_printk(const struct ath5k_hw *ah, const char *level,
3070 const char *fmt, ...)
3071 {
3072 struct va_format vaf;
3073 va_list args;
3074
3075 va_start(args, fmt);
3076
3077 vaf.fmt = fmt;
3078 vaf.va = &args;
3079
3080 if (ah && ah->hw)
3081 printk("%s" pr_fmt("%s: %pV"),
3082 level, wiphy_name(ah->hw->wiphy), &vaf);
3083 else
3084 printk("%s" pr_fmt("%pV"), level, &vaf);
3085
3086 va_end(args);
3087 }
Linux kernel - Deliverables
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