2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
43 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
45 #include <linux/module.h>
46 #include <linux/delay.h>
47 #include <linux/dma-mapping.h>
48 #include <linux/hardirq.h>
51 #include <linux/netdevice.h>
52 #include <linux/cache.h>
53 #include <linux/ethtool.h>
54 #include <linux/uaccess.h>
55 #include <linux/slab.h>
56 #include <linux/etherdevice.h>
57 #include <linux/nl80211.h>
59 #include <net/ieee80211_radiotap.h>
61 #include <asm/unaligned.h>
70 #define CREATE_TRACE_POINTS
73 bool ath5k_modparam_nohwcrypt
;
74 module_param_named(nohwcrypt
, ath5k_modparam_nohwcrypt
, bool, S_IRUGO
);
75 MODULE_PARM_DESC(nohwcrypt
, "Disable hardware encryption.");
77 static bool modparam_all_channels
;
78 module_param_named(all_channels
, modparam_all_channels
, bool, S_IRUGO
);
79 MODULE_PARM_DESC(all_channels
, "Expose all channels the device can use.");
81 static bool modparam_fastchanswitch
;
82 module_param_named(fastchanswitch
, modparam_fastchanswitch
, bool, S_IRUGO
);
83 MODULE_PARM_DESC(fastchanswitch
, "Enable fast channel switching for AR2413/AR5413 radios.");
85 static bool ath5k_modparam_no_hw_rfkill_switch
;
86 module_param_named(no_hw_rfkill_switch
, ath5k_modparam_no_hw_rfkill_switch
,
88 MODULE_PARM_DESC(no_hw_rfkill_switch
, "Ignore the GPIO RFKill switch state");
92 MODULE_AUTHOR("Jiri Slaby");
93 MODULE_AUTHOR("Nick Kossifidis");
94 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
95 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
96 MODULE_LICENSE("Dual BSD/GPL");
98 static int ath5k_init(struct ieee80211_hw
*hw
);
99 static int ath5k_reset(struct ath5k_hw
*ah
, struct ieee80211_channel
*chan
,
103 static const struct ath5k_srev_name srev_names
[] = {
104 #ifdef CONFIG_ATHEROS_AR231X
105 { "5312", AR5K_VERSION_MAC
, AR5K_SREV_AR5312_R2
},
106 { "5312", AR5K_VERSION_MAC
, AR5K_SREV_AR5312_R7
},
107 { "2313", AR5K_VERSION_MAC
, AR5K_SREV_AR2313_R8
},
108 { "2315", AR5K_VERSION_MAC
, AR5K_SREV_AR2315_R6
},
109 { "2315", AR5K_VERSION_MAC
, AR5K_SREV_AR2315_R7
},
110 { "2317", AR5K_VERSION_MAC
, AR5K_SREV_AR2317_R1
},
111 { "2317", AR5K_VERSION_MAC
, AR5K_SREV_AR2317_R2
},
113 { "5210", AR5K_VERSION_MAC
, AR5K_SREV_AR5210
},
114 { "5311", AR5K_VERSION_MAC
, AR5K_SREV_AR5311
},
115 { "5311A", AR5K_VERSION_MAC
, AR5K_SREV_AR5311A
},
116 { "5311B", AR5K_VERSION_MAC
, AR5K_SREV_AR5311B
},
117 { "5211", AR5K_VERSION_MAC
, AR5K_SREV_AR5211
},
118 { "5212", AR5K_VERSION_MAC
, AR5K_SREV_AR5212
},
119 { "5213", AR5K_VERSION_MAC
, AR5K_SREV_AR5213
},
120 { "5213A", AR5K_VERSION_MAC
, AR5K_SREV_AR5213A
},
121 { "2413", AR5K_VERSION_MAC
, AR5K_SREV_AR2413
},
122 { "2414", AR5K_VERSION_MAC
, AR5K_SREV_AR2414
},
123 { "5424", AR5K_VERSION_MAC
, AR5K_SREV_AR5424
},
124 { "5413", AR5K_VERSION_MAC
, AR5K_SREV_AR5413
},
125 { "5414", AR5K_VERSION_MAC
, AR5K_SREV_AR5414
},
126 { "2415", AR5K_VERSION_MAC
, AR5K_SREV_AR2415
},
127 { "5416", AR5K_VERSION_MAC
, AR5K_SREV_AR5416
},
128 { "5418", AR5K_VERSION_MAC
, AR5K_SREV_AR5418
},
129 { "2425", AR5K_VERSION_MAC
, AR5K_SREV_AR2425
},
130 { "2417", AR5K_VERSION_MAC
, AR5K_SREV_AR2417
},
132 { "xxxxx", AR5K_VERSION_MAC
, AR5K_SREV_UNKNOWN
},
133 { "5110", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5110
},
134 { "5111", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5111
},
135 { "5111A", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5111A
},
136 { "2111", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2111
},
137 { "5112", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5112
},
138 { "5112A", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5112A
},
139 { "5112B", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5112B
},
140 { "2112", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2112
},
141 { "2112A", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2112A
},
142 { "2112B", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2112B
},
143 { "2413", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2413
},
144 { "5413", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5413
},
145 { "5424", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5424
},
146 { "5133", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5133
},
147 #ifdef CONFIG_ATHEROS_AR231X
148 { "2316", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2316
},
149 { "2317", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2317
},
151 { "xxxxx", AR5K_VERSION_RAD
, AR5K_SREV_UNKNOWN
},
154 static const struct ieee80211_rate ath5k_rates
[] = {
156 .hw_value
= ATH5K_RATE_CODE_1M
, },
158 .hw_value
= ATH5K_RATE_CODE_2M
,
159 .hw_value_short
= ATH5K_RATE_CODE_2M
| AR5K_SET_SHORT_PREAMBLE
,
160 .flags
= IEEE80211_RATE_SHORT_PREAMBLE
},
162 .hw_value
= ATH5K_RATE_CODE_5_5M
,
163 .hw_value_short
= ATH5K_RATE_CODE_5_5M
| AR5K_SET_SHORT_PREAMBLE
,
164 .flags
= IEEE80211_RATE_SHORT_PREAMBLE
},
166 .hw_value
= ATH5K_RATE_CODE_11M
,
167 .hw_value_short
= ATH5K_RATE_CODE_11M
| AR5K_SET_SHORT_PREAMBLE
,
168 .flags
= IEEE80211_RATE_SHORT_PREAMBLE
},
170 .hw_value
= ATH5K_RATE_CODE_6M
,
173 .hw_value
= ATH5K_RATE_CODE_9M
,
176 .hw_value
= ATH5K_RATE_CODE_12M
,
179 .hw_value
= ATH5K_RATE_CODE_18M
,
182 .hw_value
= ATH5K_RATE_CODE_24M
,
185 .hw_value
= ATH5K_RATE_CODE_36M
,
188 .hw_value
= ATH5K_RATE_CODE_48M
,
191 .hw_value
= ATH5K_RATE_CODE_54M
,
195 static inline u64
ath5k_extend_tsf(struct ath5k_hw
*ah
, u32 rstamp
)
197 u64 tsf
= ath5k_hw_get_tsf64(ah
);
199 if ((tsf
& 0x7fff) < rstamp
)
202 return (tsf
& ~0x7fff) | rstamp
;
206 ath5k_chip_name(enum ath5k_srev_type type
, u_int16_t val
)
208 const char *name
= "xxxxx";
211 for (i
= 0; i
< ARRAY_SIZE(srev_names
); i
++) {
212 if (srev_names
[i
].sr_type
!= type
)
215 if ((val
& 0xf0) == srev_names
[i
].sr_val
)
216 name
= srev_names
[i
].sr_name
;
218 if ((val
& 0xff) == srev_names
[i
].sr_val
) {
219 name
= srev_names
[i
].sr_name
;
226 static unsigned int ath5k_ioread32(void *hw_priv
, u32 reg_offset
)
228 struct ath5k_hw
*ah
= (struct ath5k_hw
*) hw_priv
;
229 return ath5k_hw_reg_read(ah
, reg_offset
);
232 static void ath5k_iowrite32(void *hw_priv
, u32 val
, u32 reg_offset
)
234 struct ath5k_hw
*ah
= (struct ath5k_hw
*) hw_priv
;
235 ath5k_hw_reg_write(ah
, val
, reg_offset
);
238 static const struct ath_ops ath5k_common_ops
= {
239 .read
= ath5k_ioread32
,
240 .write
= ath5k_iowrite32
,
243 /***********************\
244 * Driver Initialization *
245 \***********************/
247 static int ath5k_reg_notifier(struct wiphy
*wiphy
, struct regulatory_request
*request
)
249 struct ieee80211_hw
*hw
= wiphy_to_ieee80211_hw(wiphy
);
250 struct ath5k_hw
*ah
= hw
->priv
;
251 struct ath_regulatory
*regulatory
= ath5k_hw_regulatory(ah
);
253 return ath_reg_notifier_apply(wiphy
, request
, regulatory
);
256 /********************\
257 * Channel/mode setup *
258 \********************/
261 * Returns true for the channel numbers used without all_channels modparam.
263 static bool ath5k_is_standard_channel(short chan
, enum ieee80211_band band
)
265 if (band
== IEEE80211_BAND_2GHZ
&& chan
<= 14)
268 return /* UNII 1,2 */
269 (((chan
& 3) == 0 && chan
>= 36 && chan
<= 64) ||
271 ((chan
& 3) == 0 && chan
>= 100 && chan
<= 140) ||
273 ((chan
& 3) == 1 && chan
>= 149 && chan
<= 165) ||
274 /* 802.11j 5.030-5.080 GHz (20MHz) */
275 (chan
== 8 || chan
== 12 || chan
== 16) ||
276 /* 802.11j 4.9GHz (20MHz) */
277 (chan
== 184 || chan
== 188 || chan
== 192 || chan
== 196));
281 ath5k_setup_channels(struct ath5k_hw
*ah
, struct ieee80211_channel
*channels
,
282 unsigned int mode
, unsigned int max
)
284 unsigned int count
, size
, freq
, ch
;
285 enum ieee80211_band band
;
289 /* 1..220, but 2GHz frequencies are filtered by check_channel */
291 band
= IEEE80211_BAND_5GHZ
;
296 band
= IEEE80211_BAND_2GHZ
;
299 ATH5K_WARN(ah
, "bad mode, not copying channels\n");
304 for (ch
= 1; ch
<= size
&& count
< max
; ch
++) {
305 freq
= ieee80211_channel_to_frequency(ch
, band
);
307 if (freq
== 0) /* mapping failed - not a standard channel */
310 /* Write channel info, needed for ath5k_channel_ok() */
311 channels
[count
].center_freq
= freq
;
312 channels
[count
].band
= band
;
313 channels
[count
].hw_value
= mode
;
315 /* Check if channel is supported by the chipset */
316 if (!ath5k_channel_ok(ah
, &channels
[count
]))
319 if (!modparam_all_channels
&&
320 !ath5k_is_standard_channel(ch
, band
))
330 ath5k_setup_rate_idx(struct ath5k_hw
*ah
, struct ieee80211_supported_band
*b
)
334 for (i
= 0; i
< AR5K_MAX_RATES
; i
++)
335 ah
->rate_idx
[b
->band
][i
] = -1;
337 for (i
= 0; i
< b
->n_bitrates
; i
++) {
338 ah
->rate_idx
[b
->band
][b
->bitrates
[i
].hw_value
] = i
;
339 if (b
->bitrates
[i
].hw_value_short
)
340 ah
->rate_idx
[b
->band
][b
->bitrates
[i
].hw_value_short
] = i
;
345 ath5k_setup_bands(struct ieee80211_hw
*hw
)
347 struct ath5k_hw
*ah
= hw
->priv
;
348 struct ieee80211_supported_band
*sband
;
349 int max_c
, count_c
= 0;
352 BUILD_BUG_ON(ARRAY_SIZE(ah
->sbands
) < IEEE80211_NUM_BANDS
);
353 max_c
= ARRAY_SIZE(ah
->channels
);
356 sband
= &ah
->sbands
[IEEE80211_BAND_2GHZ
];
357 sband
->band
= IEEE80211_BAND_2GHZ
;
358 sband
->bitrates
= &ah
->rates
[IEEE80211_BAND_2GHZ
][0];
360 if (test_bit(AR5K_MODE_11G
, ah
->ah_capabilities
.cap_mode
)) {
362 memcpy(sband
->bitrates
, &ath5k_rates
[0],
363 sizeof(struct ieee80211_rate
) * 12);
364 sband
->n_bitrates
= 12;
366 sband
->channels
= ah
->channels
;
367 sband
->n_channels
= ath5k_setup_channels(ah
, sband
->channels
,
368 AR5K_MODE_11G
, max_c
);
370 hw
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] = sband
;
371 count_c
= sband
->n_channels
;
373 } else if (test_bit(AR5K_MODE_11B
, ah
->ah_capabilities
.cap_mode
)) {
375 memcpy(sband
->bitrates
, &ath5k_rates
[0],
376 sizeof(struct ieee80211_rate
) * 4);
377 sband
->n_bitrates
= 4;
379 /* 5211 only supports B rates and uses 4bit rate codes
380 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
383 if (ah
->ah_version
== AR5K_AR5211
) {
384 for (i
= 0; i
< 4; i
++) {
385 sband
->bitrates
[i
].hw_value
=
386 sband
->bitrates
[i
].hw_value
& 0xF;
387 sband
->bitrates
[i
].hw_value_short
=
388 sband
->bitrates
[i
].hw_value_short
& 0xF;
392 sband
->channels
= ah
->channels
;
393 sband
->n_channels
= ath5k_setup_channels(ah
, sband
->channels
,
394 AR5K_MODE_11B
, max_c
);
396 hw
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] = sband
;
397 count_c
= sband
->n_channels
;
400 ath5k_setup_rate_idx(ah
, sband
);
402 /* 5GHz band, A mode */
403 if (test_bit(AR5K_MODE_11A
, ah
->ah_capabilities
.cap_mode
)) {
404 sband
= &ah
->sbands
[IEEE80211_BAND_5GHZ
];
405 sband
->band
= IEEE80211_BAND_5GHZ
;
406 sband
->bitrates
= &ah
->rates
[IEEE80211_BAND_5GHZ
][0];
408 memcpy(sband
->bitrates
, &ath5k_rates
[4],
409 sizeof(struct ieee80211_rate
) * 8);
410 sband
->n_bitrates
= 8;
412 sband
->channels
= &ah
->channels
[count_c
];
413 sband
->n_channels
= ath5k_setup_channels(ah
, sband
->channels
,
414 AR5K_MODE_11A
, max_c
);
416 hw
->wiphy
->bands
[IEEE80211_BAND_5GHZ
] = sband
;
418 ath5k_setup_rate_idx(ah
, sband
);
420 ath5k_debug_dump_bands(ah
);
426 * Set/change channels. We always reset the chip.
427 * To accomplish this we must first cleanup any pending DMA,
428 * then restart stuff after a la ath5k_init.
430 * Called with ah->lock.
433 ath5k_chan_set(struct ath5k_hw
*ah
, struct ieee80211_channel
*chan
)
435 ATH5K_DBG(ah
, ATH5K_DEBUG_RESET
,
436 "channel set, resetting (%u -> %u MHz)\n",
437 ah
->curchan
->center_freq
, chan
->center_freq
);
440 * To switch channels clear any pending DMA operations;
441 * wait long enough for the RX fifo to drain, reset the
442 * hardware at the new frequency, and then re-enable
443 * the relevant bits of the h/w.
445 return ath5k_reset(ah
, chan
, true);
448 void ath5k_vif_iter(void *data
, u8
*mac
, struct ieee80211_vif
*vif
)
450 struct ath5k_vif_iter_data
*iter_data
= data
;
452 struct ath5k_vif
*avf
= (void *)vif
->drv_priv
;
454 if (iter_data
->hw_macaddr
)
455 for (i
= 0; i
< ETH_ALEN
; i
++)
456 iter_data
->mask
[i
] &=
457 ~(iter_data
->hw_macaddr
[i
] ^ mac
[i
]);
459 if (!iter_data
->found_active
) {
460 iter_data
->found_active
= true;
461 memcpy(iter_data
->active_mac
, mac
, ETH_ALEN
);
464 if (iter_data
->need_set_hw_addr
&& iter_data
->hw_macaddr
)
465 if (ether_addr_equal(iter_data
->hw_macaddr
, mac
))
466 iter_data
->need_set_hw_addr
= false;
468 if (!iter_data
->any_assoc
) {
470 iter_data
->any_assoc
= true;
473 /* Calculate combined mode - when APs are active, operate in AP mode.
474 * Otherwise use the mode of the new interface. This can currently
475 * only deal with combinations of APs and STAs. Only one ad-hoc
476 * interfaces is allowed.
478 if (avf
->opmode
== NL80211_IFTYPE_AP
)
479 iter_data
->opmode
= NL80211_IFTYPE_AP
;
481 if (avf
->opmode
== NL80211_IFTYPE_STATION
)
483 if (iter_data
->opmode
== NL80211_IFTYPE_UNSPECIFIED
)
484 iter_data
->opmode
= avf
->opmode
;
489 ath5k_update_bssid_mask_and_opmode(struct ath5k_hw
*ah
,
490 struct ieee80211_vif
*vif
)
492 struct ath_common
*common
= ath5k_hw_common(ah
);
493 struct ath5k_vif_iter_data iter_data
;
497 * Use the hardware MAC address as reference, the hardware uses it
498 * together with the BSSID mask when matching addresses.
500 iter_data
.hw_macaddr
= common
->macaddr
;
501 memset(&iter_data
.mask
, 0xff, ETH_ALEN
);
502 iter_data
.found_active
= false;
503 iter_data
.need_set_hw_addr
= true;
504 iter_data
.opmode
= NL80211_IFTYPE_UNSPECIFIED
;
505 iter_data
.n_stas
= 0;
508 ath5k_vif_iter(&iter_data
, vif
->addr
, vif
);
510 /* Get list of all active MAC addresses */
511 ieee80211_iterate_active_interfaces_atomic(ah
->hw
, ath5k_vif_iter
,
513 memcpy(ah
->bssidmask
, iter_data
.mask
, ETH_ALEN
);
515 ah
->opmode
= iter_data
.opmode
;
516 if (ah
->opmode
== NL80211_IFTYPE_UNSPECIFIED
)
517 /* Nothing active, default to station mode */
518 ah
->opmode
= NL80211_IFTYPE_STATION
;
520 ath5k_hw_set_opmode(ah
, ah
->opmode
);
521 ATH5K_DBG(ah
, ATH5K_DEBUG_MODE
, "mode setup opmode %d (%s)\n",
522 ah
->opmode
, ath_opmode_to_string(ah
->opmode
));
524 if (iter_data
.need_set_hw_addr
&& iter_data
.found_active
)
525 ath5k_hw_set_lladdr(ah
, iter_data
.active_mac
);
527 if (ath5k_hw_hasbssidmask(ah
))
528 ath5k_hw_set_bssid_mask(ah
, ah
->bssidmask
);
530 /* Set up RX Filter */
531 if (iter_data
.n_stas
> 1) {
532 /* If you have multiple STA interfaces connected to
533 * different APs, ARPs are not received (most of the time?)
534 * Enabling PROMISC appears to fix that problem.
536 ah
->filter_flags
|= AR5K_RX_FILTER_PROM
;
539 rfilt
= ah
->filter_flags
;
540 ath5k_hw_set_rx_filter(ah
, rfilt
);
541 ATH5K_DBG(ah
, ATH5K_DEBUG_MODE
, "RX filter 0x%x\n", rfilt
);
545 ath5k_hw_to_driver_rix(struct ath5k_hw
*ah
, int hw_rix
)
549 /* return base rate on errors */
550 if (WARN(hw_rix
< 0 || hw_rix
>= AR5K_MAX_RATES
,
551 "hw_rix out of bounds: %x\n", hw_rix
))
554 rix
= ah
->rate_idx
[ah
->curchan
->band
][hw_rix
];
555 if (WARN(rix
< 0, "invalid hw_rix: %x\n", hw_rix
))
566 struct sk_buff
*ath5k_rx_skb_alloc(struct ath5k_hw
*ah
, dma_addr_t
*skb_addr
)
568 struct ath_common
*common
= ath5k_hw_common(ah
);
572 * Allocate buffer with headroom_needed space for the
573 * fake physical layer header at the start.
575 skb
= ath_rxbuf_alloc(common
,
580 ATH5K_ERR(ah
, "can't alloc skbuff of size %u\n",
585 *skb_addr
= dma_map_single(ah
->dev
,
586 skb
->data
, common
->rx_bufsize
,
589 if (unlikely(dma_mapping_error(ah
->dev
, *skb_addr
))) {
590 ATH5K_ERR(ah
, "%s: DMA mapping failed\n", __func__
);
598 ath5k_rxbuf_setup(struct ath5k_hw
*ah
, struct ath5k_buf
*bf
)
600 struct sk_buff
*skb
= bf
->skb
;
601 struct ath5k_desc
*ds
;
605 skb
= ath5k_rx_skb_alloc(ah
, &bf
->skbaddr
);
612 * Setup descriptors. For receive we always terminate
613 * the descriptor list with a self-linked entry so we'll
614 * not get overrun under high load (as can happen with a
615 * 5212 when ANI processing enables PHY error frames).
617 * To ensure the last descriptor is self-linked we create
618 * each descriptor as self-linked and add it to the end. As
619 * each additional descriptor is added the previous self-linked
620 * entry is "fixed" naturally. This should be safe even
621 * if DMA is happening. When processing RX interrupts we
622 * never remove/process the last, self-linked, entry on the
623 * descriptor list. This ensures the hardware always has
624 * someplace to write a new frame.
627 ds
->ds_link
= bf
->daddr
; /* link to self */
628 ds
->ds_data
= bf
->skbaddr
;
629 ret
= ath5k_hw_setup_rx_desc(ah
, ds
, ah
->common
.rx_bufsize
, 0);
631 ATH5K_ERR(ah
, "%s: could not setup RX desc\n", __func__
);
635 if (ah
->rxlink
!= NULL
)
636 *ah
->rxlink
= bf
->daddr
;
637 ah
->rxlink
= &ds
->ds_link
;
641 static enum ath5k_pkt_type
get_hw_packet_type(struct sk_buff
*skb
)
643 struct ieee80211_hdr
*hdr
;
644 enum ath5k_pkt_type htype
;
647 hdr
= (struct ieee80211_hdr
*)skb
->data
;
648 fc
= hdr
->frame_control
;
650 if (ieee80211_is_beacon(fc
))
651 htype
= AR5K_PKT_TYPE_BEACON
;
652 else if (ieee80211_is_probe_resp(fc
))
653 htype
= AR5K_PKT_TYPE_PROBE_RESP
;
654 else if (ieee80211_is_atim(fc
))
655 htype
= AR5K_PKT_TYPE_ATIM
;
656 else if (ieee80211_is_pspoll(fc
))
657 htype
= AR5K_PKT_TYPE_PSPOLL
;
659 htype
= AR5K_PKT_TYPE_NORMAL
;
665 ath5k_txbuf_setup(struct ath5k_hw
*ah
, struct ath5k_buf
*bf
,
666 struct ath5k_txq
*txq
, int padsize
)
668 struct ath5k_desc
*ds
= bf
->desc
;
669 struct sk_buff
*skb
= bf
->skb
;
670 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
671 unsigned int pktlen
, flags
, keyidx
= AR5K_TXKEYIX_INVALID
;
672 struct ieee80211_rate
*rate
;
673 unsigned int mrr_rate
[3], mrr_tries
[3];
680 flags
= AR5K_TXDESC_INTREQ
| AR5K_TXDESC_CLRDMASK
;
683 bf
->skbaddr
= dma_map_single(ah
->dev
, skb
->data
, skb
->len
,
686 rate
= ieee80211_get_tx_rate(ah
->hw
, info
);
692 if (info
->flags
& IEEE80211_TX_CTL_NO_ACK
)
693 flags
|= AR5K_TXDESC_NOACK
;
695 rc_flags
= info
->control
.rates
[0].flags
;
696 hw_rate
= (rc_flags
& IEEE80211_TX_RC_USE_SHORT_PREAMBLE
) ?
697 rate
->hw_value_short
: rate
->hw_value
;
701 /* FIXME: If we are in g mode and rate is a CCK rate
702 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
703 * from tx power (value is in dB units already) */
704 if (info
->control
.hw_key
) {
705 keyidx
= info
->control
.hw_key
->hw_key_idx
;
706 pktlen
+= info
->control
.hw_key
->icv_len
;
708 if (rc_flags
& IEEE80211_TX_RC_USE_RTS_CTS
) {
709 flags
|= AR5K_TXDESC_RTSENA
;
710 cts_rate
= ieee80211_get_rts_cts_rate(ah
->hw
, info
)->hw_value
;
711 duration
= le16_to_cpu(ieee80211_rts_duration(ah
->hw
,
712 info
->control
.vif
, pktlen
, info
));
714 if (rc_flags
& IEEE80211_TX_RC_USE_CTS_PROTECT
) {
715 flags
|= AR5K_TXDESC_CTSENA
;
716 cts_rate
= ieee80211_get_rts_cts_rate(ah
->hw
, info
)->hw_value
;
717 duration
= le16_to_cpu(ieee80211_ctstoself_duration(ah
->hw
,
718 info
->control
.vif
, pktlen
, info
));
720 ret
= ah
->ah_setup_tx_desc(ah
, ds
, pktlen
,
721 ieee80211_get_hdrlen_from_skb(skb
), padsize
,
722 get_hw_packet_type(skb
),
723 (ah
->power_level
* 2),
725 info
->control
.rates
[0].count
, keyidx
, ah
->ah_tx_ant
, flags
,
730 /* Set up MRR descriptor */
731 if (ah
->ah_capabilities
.cap_has_mrr_support
) {
732 memset(mrr_rate
, 0, sizeof(mrr_rate
));
733 memset(mrr_tries
, 0, sizeof(mrr_tries
));
734 for (i
= 0; i
< 3; i
++) {
735 rate
= ieee80211_get_alt_retry_rate(ah
->hw
, info
, i
);
739 mrr_rate
[i
] = rate
->hw_value
;
740 mrr_tries
[i
] = info
->control
.rates
[i
+ 1].count
;
743 ath5k_hw_setup_mrr_tx_desc(ah
, ds
,
744 mrr_rate
[0], mrr_tries
[0],
745 mrr_rate
[1], mrr_tries
[1],
746 mrr_rate
[2], mrr_tries
[2]);
750 ds
->ds_data
= bf
->skbaddr
;
752 spin_lock_bh(&txq
->lock
);
753 list_add_tail(&bf
->list
, &txq
->q
);
755 if (txq
->link
== NULL
) /* is this first packet? */
756 ath5k_hw_set_txdp(ah
, txq
->qnum
, bf
->daddr
);
757 else /* no, so only link it */
758 *txq
->link
= bf
->daddr
;
760 txq
->link
= &ds
->ds_link
;
761 ath5k_hw_start_tx_dma(ah
, txq
->qnum
);
763 spin_unlock_bh(&txq
->lock
);
767 dma_unmap_single(ah
->dev
, bf
->skbaddr
, skb
->len
, DMA_TO_DEVICE
);
771 /*******************\
772 * Descriptors setup *
773 \*******************/
776 ath5k_desc_alloc(struct ath5k_hw
*ah
)
778 struct ath5k_desc
*ds
;
779 struct ath5k_buf
*bf
;
784 /* allocate descriptors */
785 ah
->desc_len
= sizeof(struct ath5k_desc
) *
786 (ATH_TXBUF
+ ATH_RXBUF
+ ATH_BCBUF
+ 1);
788 ah
->desc
= dma_alloc_coherent(ah
->dev
, ah
->desc_len
,
789 &ah
->desc_daddr
, GFP_KERNEL
);
790 if (ah
->desc
== NULL
) {
791 ATH5K_ERR(ah
, "can't allocate descriptors\n");
797 ATH5K_DBG(ah
, ATH5K_DEBUG_ANY
, "DMA map: %p (%zu) -> %llx\n",
798 ds
, ah
->desc_len
, (unsigned long long)ah
->desc_daddr
);
800 bf
= kcalloc(1 + ATH_TXBUF
+ ATH_RXBUF
+ ATH_BCBUF
,
801 sizeof(struct ath5k_buf
), GFP_KERNEL
);
803 ATH5K_ERR(ah
, "can't allocate bufptr\n");
809 INIT_LIST_HEAD(&ah
->rxbuf
);
810 for (i
= 0; i
< ATH_RXBUF
; i
++, bf
++, ds
++, da
+= sizeof(*ds
)) {
813 list_add_tail(&bf
->list
, &ah
->rxbuf
);
816 INIT_LIST_HEAD(&ah
->txbuf
);
817 ah
->txbuf_len
= ATH_TXBUF
;
818 for (i
= 0; i
< ATH_TXBUF
; i
++, bf
++, ds
++, da
+= sizeof(*ds
)) {
821 list_add_tail(&bf
->list
, &ah
->txbuf
);
825 INIT_LIST_HEAD(&ah
->bcbuf
);
826 for (i
= 0; i
< ATH_BCBUF
; i
++, bf
++, ds
++, da
+= sizeof(*ds
)) {
829 list_add_tail(&bf
->list
, &ah
->bcbuf
);
834 dma_free_coherent(ah
->dev
, ah
->desc_len
, ah
->desc
, ah
->desc_daddr
);
841 ath5k_txbuf_free_skb(struct ath5k_hw
*ah
, struct ath5k_buf
*bf
)
846 dma_unmap_single(ah
->dev
, bf
->skbaddr
, bf
->skb
->len
,
848 dev_kfree_skb_any(bf
->skb
);
851 bf
->desc
->ds_data
= 0;
855 ath5k_rxbuf_free_skb(struct ath5k_hw
*ah
, struct ath5k_buf
*bf
)
857 struct ath_common
*common
= ath5k_hw_common(ah
);
862 dma_unmap_single(ah
->dev
, bf
->skbaddr
, common
->rx_bufsize
,
864 dev_kfree_skb_any(bf
->skb
);
867 bf
->desc
->ds_data
= 0;
871 ath5k_desc_free(struct ath5k_hw
*ah
)
873 struct ath5k_buf
*bf
;
875 list_for_each_entry(bf
, &ah
->txbuf
, list
)
876 ath5k_txbuf_free_skb(ah
, bf
);
877 list_for_each_entry(bf
, &ah
->rxbuf
, list
)
878 ath5k_rxbuf_free_skb(ah
, bf
);
879 list_for_each_entry(bf
, &ah
->bcbuf
, list
)
880 ath5k_txbuf_free_skb(ah
, bf
);
882 /* Free memory associated with all descriptors */
883 dma_free_coherent(ah
->dev
, ah
->desc_len
, ah
->desc
, ah
->desc_daddr
);
896 static struct ath5k_txq
*
897 ath5k_txq_setup(struct ath5k_hw
*ah
,
898 int qtype
, int subtype
)
900 struct ath5k_txq
*txq
;
901 struct ath5k_txq_info qi
= {
902 .tqi_subtype
= subtype
,
903 /* XXX: default values not correct for B and XR channels,
905 .tqi_aifs
= AR5K_TUNE_AIFS
,
906 .tqi_cw_min
= AR5K_TUNE_CWMIN
,
907 .tqi_cw_max
= AR5K_TUNE_CWMAX
912 * Enable interrupts only for EOL and DESC conditions.
913 * We mark tx descriptors to receive a DESC interrupt
914 * when a tx queue gets deep; otherwise we wait for the
915 * EOL to reap descriptors. Note that this is done to
916 * reduce interrupt load and this only defers reaping
917 * descriptors, never transmitting frames. Aside from
918 * reducing interrupts this also permits more concurrency.
919 * The only potential downside is if the tx queue backs
920 * up in which case the top half of the kernel may backup
921 * due to a lack of tx descriptors.
923 qi
.tqi_flags
= AR5K_TXQ_FLAG_TXEOLINT_ENABLE
|
924 AR5K_TXQ_FLAG_TXDESCINT_ENABLE
;
925 qnum
= ath5k_hw_setup_tx_queue(ah
, qtype
, &qi
);
928 * NB: don't print a message, this happens
929 * normally on parts with too few tx queues
931 return ERR_PTR(qnum
);
933 txq
= &ah
->txqs
[qnum
];
937 INIT_LIST_HEAD(&txq
->q
);
938 spin_lock_init(&txq
->lock
);
941 txq
->txq_max
= ATH5K_TXQ_LEN_MAX
;
942 txq
->txq_poll_mark
= false;
945 return &ah
->txqs
[qnum
];
949 ath5k_beaconq_setup(struct ath5k_hw
*ah
)
951 struct ath5k_txq_info qi
= {
952 /* XXX: default values not correct for B and XR channels,
954 .tqi_aifs
= AR5K_TUNE_AIFS
,
955 .tqi_cw_min
= AR5K_TUNE_CWMIN
,
956 .tqi_cw_max
= AR5K_TUNE_CWMAX
,
957 /* NB: for dynamic turbo, don't enable any other interrupts */
958 .tqi_flags
= AR5K_TXQ_FLAG_TXDESCINT_ENABLE
961 return ath5k_hw_setup_tx_queue(ah
, AR5K_TX_QUEUE_BEACON
, &qi
);
965 ath5k_beaconq_config(struct ath5k_hw
*ah
)
967 struct ath5k_txq_info qi
;
970 ret
= ath5k_hw_get_tx_queueprops(ah
, ah
->bhalq
, &qi
);
974 if (ah
->opmode
== NL80211_IFTYPE_AP
||
975 ah
->opmode
== NL80211_IFTYPE_MESH_POINT
) {
977 * Always burst out beacon and CAB traffic
978 * (aifs = cwmin = cwmax = 0)
983 } else if (ah
->opmode
== NL80211_IFTYPE_ADHOC
) {
985 * Adhoc mode; backoff between 0 and (2 * cw_min).
989 qi
.tqi_cw_max
= 2 * AR5K_TUNE_CWMIN
;
992 ATH5K_DBG(ah
, ATH5K_DEBUG_BEACON
,
993 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
994 qi
.tqi_aifs
, qi
.tqi_cw_min
, qi
.tqi_cw_max
);
996 ret
= ath5k_hw_set_tx_queueprops(ah
, ah
->bhalq
, &qi
);
998 ATH5K_ERR(ah
, "%s: unable to update parameters for beacon "
999 "hardware queue!\n", __func__
);
1002 ret
= ath5k_hw_reset_tx_queue(ah
, ah
->bhalq
); /* push to h/w */
1006 /* reconfigure cabq with ready time to 80% of beacon_interval */
1007 ret
= ath5k_hw_get_tx_queueprops(ah
, AR5K_TX_QUEUE_ID_CAB
, &qi
);
1011 qi
.tqi_ready_time
= (ah
->bintval
* 80) / 100;
1012 ret
= ath5k_hw_set_tx_queueprops(ah
, AR5K_TX_QUEUE_ID_CAB
, &qi
);
1016 ret
= ath5k_hw_reset_tx_queue(ah
, AR5K_TX_QUEUE_ID_CAB
);
1022 * ath5k_drain_tx_buffs - Empty tx buffers
1024 * @ah The &struct ath5k_hw
1026 * Empty tx buffers from all queues in preparation
1027 * of a reset or during shutdown.
1029 * NB: this assumes output has been stopped and
1030 * we do not need to block ath5k_tx_tasklet
1033 ath5k_drain_tx_buffs(struct ath5k_hw
*ah
)
1035 struct ath5k_txq
*txq
;
1036 struct ath5k_buf
*bf
, *bf0
;
1039 for (i
= 0; i
< ARRAY_SIZE(ah
->txqs
); i
++) {
1040 if (ah
->txqs
[i
].setup
) {
1042 spin_lock_bh(&txq
->lock
);
1043 list_for_each_entry_safe(bf
, bf0
, &txq
->q
, list
) {
1044 ath5k_debug_printtxbuf(ah
, bf
);
1046 ath5k_txbuf_free_skb(ah
, bf
);
1048 spin_lock_bh(&ah
->txbuflock
);
1049 list_move_tail(&bf
->list
, &ah
->txbuf
);
1052 spin_unlock_bh(&ah
->txbuflock
);
1055 txq
->txq_poll_mark
= false;
1056 spin_unlock_bh(&txq
->lock
);
1062 ath5k_txq_release(struct ath5k_hw
*ah
)
1064 struct ath5k_txq
*txq
= ah
->txqs
;
1067 for (i
= 0; i
< ARRAY_SIZE(ah
->txqs
); i
++, txq
++)
1069 ath5k_hw_release_tx_queue(ah
, txq
->qnum
);
1080 * Enable the receive h/w following a reset.
1083 ath5k_rx_start(struct ath5k_hw
*ah
)
1085 struct ath_common
*common
= ath5k_hw_common(ah
);
1086 struct ath5k_buf
*bf
;
1089 common
->rx_bufsize
= roundup(IEEE80211_MAX_FRAME_LEN
, common
->cachelsz
);
1091 ATH5K_DBG(ah
, ATH5K_DEBUG_RESET
, "cachelsz %u rx_bufsize %u\n",
1092 common
->cachelsz
, common
->rx_bufsize
);
1094 spin_lock_bh(&ah
->rxbuflock
);
1096 list_for_each_entry(bf
, &ah
->rxbuf
, list
) {
1097 ret
= ath5k_rxbuf_setup(ah
, bf
);
1099 spin_unlock_bh(&ah
->rxbuflock
);
1103 bf
= list_first_entry(&ah
->rxbuf
, struct ath5k_buf
, list
);
1104 ath5k_hw_set_rxdp(ah
, bf
->daddr
);
1105 spin_unlock_bh(&ah
->rxbuflock
);
1107 ath5k_hw_start_rx_dma(ah
); /* enable recv descriptors */
1108 ath5k_update_bssid_mask_and_opmode(ah
, NULL
); /* set filters, etc. */
1109 ath5k_hw_start_rx_pcu(ah
); /* re-enable PCU/DMA engine */
1117 * Disable the receive logic on PCU (DRU)
1118 * In preparation for a shutdown.
1120 * Note: Doesn't stop rx DMA, ath5k_hw_dma_stop
1124 ath5k_rx_stop(struct ath5k_hw
*ah
)
1127 ath5k_hw_set_rx_filter(ah
, 0); /* clear recv filter */
1128 ath5k_hw_stop_rx_pcu(ah
); /* disable PCU */
1130 ath5k_debug_printrxbuffs(ah
);
1134 ath5k_rx_decrypted(struct ath5k_hw
*ah
, struct sk_buff
*skb
,
1135 struct ath5k_rx_status
*rs
)
1137 struct ath_common
*common
= ath5k_hw_common(ah
);
1138 struct ieee80211_hdr
*hdr
= (void *)skb
->data
;
1139 unsigned int keyix
, hlen
;
1141 if (!(rs
->rs_status
& AR5K_RXERR_DECRYPT
) &&
1142 rs
->rs_keyix
!= AR5K_RXKEYIX_INVALID
)
1143 return RX_FLAG_DECRYPTED
;
1145 /* Apparently when a default key is used to decrypt the packet
1146 the hw does not set the index used to decrypt. In such cases
1147 get the index from the packet. */
1148 hlen
= ieee80211_hdrlen(hdr
->frame_control
);
1149 if (ieee80211_has_protected(hdr
->frame_control
) &&
1150 !(rs
->rs_status
& AR5K_RXERR_DECRYPT
) &&
1151 skb
->len
>= hlen
+ 4) {
1152 keyix
= skb
->data
[hlen
+ 3] >> 6;
1154 if (test_bit(keyix
, common
->keymap
))
1155 return RX_FLAG_DECRYPTED
;
1163 ath5k_check_ibss_tsf(struct ath5k_hw
*ah
, struct sk_buff
*skb
,
1164 struct ieee80211_rx_status
*rxs
)
1166 struct ath_common
*common
= ath5k_hw_common(ah
);
1169 struct ieee80211_mgmt
*mgmt
= (struct ieee80211_mgmt
*)skb
->data
;
1171 if (ieee80211_is_beacon(mgmt
->frame_control
) &&
1172 le16_to_cpu(mgmt
->u
.beacon
.capab_info
) & WLAN_CAPABILITY_IBSS
&&
1173 ether_addr_equal(mgmt
->bssid
, common
->curbssid
)) {
1175 * Received an IBSS beacon with the same BSSID. Hardware *must*
1176 * have updated the local TSF. We have to work around various
1177 * hardware bugs, though...
1179 tsf
= ath5k_hw_get_tsf64(ah
);
1180 bc_tstamp
= le64_to_cpu(mgmt
->u
.beacon
.timestamp
);
1181 hw_tu
= TSF_TO_TU(tsf
);
1183 ATH5K_DBG_UNLIMIT(ah
, ATH5K_DEBUG_BEACON
,
1184 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1185 (unsigned long long)bc_tstamp
,
1186 (unsigned long long)rxs
->mactime
,
1187 (unsigned long long)(rxs
->mactime
- bc_tstamp
),
1188 (unsigned long long)tsf
);
1191 * Sometimes the HW will give us a wrong tstamp in the rx
1192 * status, causing the timestamp extension to go wrong.
1193 * (This seems to happen especially with beacon frames bigger
1194 * than 78 byte (incl. FCS))
1195 * But we know that the receive timestamp must be later than the
1196 * timestamp of the beacon since HW must have synced to that.
1198 * NOTE: here we assume mactime to be after the frame was
1199 * received, not like mac80211 which defines it at the start.
1201 if (bc_tstamp
> rxs
->mactime
) {
1202 ATH5K_DBG_UNLIMIT(ah
, ATH5K_DEBUG_BEACON
,
1203 "fixing mactime from %llx to %llx\n",
1204 (unsigned long long)rxs
->mactime
,
1205 (unsigned long long)tsf
);
1210 * Local TSF might have moved higher than our beacon timers,
1211 * in that case we have to update them to continue sending
1212 * beacons. This also takes care of synchronizing beacon sending
1213 * times with other stations.
1215 if (hw_tu
>= ah
->nexttbtt
)
1216 ath5k_beacon_update_timers(ah
, bc_tstamp
);
1218 /* Check if the beacon timers are still correct, because a TSF
1219 * update might have created a window between them - for a
1220 * longer description see the comment of this function: */
1221 if (!ath5k_hw_check_beacon_timers(ah
, ah
->bintval
)) {
1222 ath5k_beacon_update_timers(ah
, bc_tstamp
);
1223 ATH5K_DBG_UNLIMIT(ah
, ATH5K_DEBUG_BEACON
,
1224 "fixed beacon timers after beacon receive\n");
1230 ath5k_update_beacon_rssi(struct ath5k_hw
*ah
, struct sk_buff
*skb
, int rssi
)
1232 struct ieee80211_mgmt
*mgmt
= (struct ieee80211_mgmt
*)skb
->data
;
1233 struct ath_common
*common
= ath5k_hw_common(ah
);
1235 /* only beacons from our BSSID */
1236 if (!ieee80211_is_beacon(mgmt
->frame_control
) ||
1237 !ether_addr_equal(mgmt
->bssid
, common
->curbssid
))
1240 ewma_add(&ah
->ah_beacon_rssi_avg
, rssi
);
1242 /* in IBSS mode we should keep RSSI statistics per neighbour */
1243 /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */
1247 * Compute padding position. skb must contain an IEEE 802.11 frame
1249 static int ath5k_common_padpos(struct sk_buff
*skb
)
1251 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
1252 __le16 frame_control
= hdr
->frame_control
;
1255 if (ieee80211_has_a4(frame_control
))
1258 if (ieee80211_is_data_qos(frame_control
))
1259 padpos
+= IEEE80211_QOS_CTL_LEN
;
1265 * This function expects an 802.11 frame and returns the number of
1266 * bytes added, or -1 if we don't have enough header room.
1268 static int ath5k_add_padding(struct sk_buff
*skb
)
1270 int padpos
= ath5k_common_padpos(skb
);
1271 int padsize
= padpos
& 3;
1273 if (padsize
&& skb
->len
> padpos
) {
1275 if (skb_headroom(skb
) < padsize
)
1278 skb_push(skb
, padsize
);
1279 memmove(skb
->data
, skb
->data
+ padsize
, padpos
);
1287 * The MAC header is padded to have 32-bit boundary if the
1288 * packet payload is non-zero. The general calculation for
1289 * padsize would take into account odd header lengths:
1290 * padsize = 4 - (hdrlen & 3); however, since only
1291 * even-length headers are used, padding can only be 0 or 2
1292 * bytes and we can optimize this a bit. We must not try to
1293 * remove padding from short control frames that do not have a
1296 * This function expects an 802.11 frame and returns the number of
1299 static int ath5k_remove_padding(struct sk_buff
*skb
)
1301 int padpos
= ath5k_common_padpos(skb
);
1302 int padsize
= padpos
& 3;
1304 if (padsize
&& skb
->len
>= padpos
+ padsize
) {
1305 memmove(skb
->data
+ padsize
, skb
->data
, padpos
);
1306 skb_pull(skb
, padsize
);
1314 ath5k_receive_frame(struct ath5k_hw
*ah
, struct sk_buff
*skb
,
1315 struct ath5k_rx_status
*rs
)
1317 struct ieee80211_rx_status
*rxs
;
1319 ath5k_remove_padding(skb
);
1321 rxs
= IEEE80211_SKB_RXCB(skb
);
1324 if (unlikely(rs
->rs_status
& AR5K_RXERR_MIC
))
1325 rxs
->flag
|= RX_FLAG_MMIC_ERROR
;
1328 * always extend the mac timestamp, since this information is
1329 * also needed for proper IBSS merging.
1331 * XXX: it might be too late to do it here, since rs_tstamp is
1332 * 15bit only. that means TSF extension has to be done within
1333 * 32768usec (about 32ms). it might be necessary to move this to
1334 * the interrupt handler, like it is done in madwifi.
1336 * Unfortunately we don't know when the hardware takes the rx
1337 * timestamp (beginning of phy frame, data frame, end of rx?).
1338 * The only thing we know is that it is hardware specific...
1339 * On AR5213 it seems the rx timestamp is at the end of the
1340 * frame, but I'm not sure.
1342 * NOTE: mac80211 defines mactime at the beginning of the first
1343 * data symbol. Since we don't have any time references it's
1344 * impossible to comply to that. This affects IBSS merge only
1345 * right now, so it's not too bad...
1347 rxs
->mactime
= ath5k_extend_tsf(ah
, rs
->rs_tstamp
);
1348 rxs
->flag
|= RX_FLAG_MACTIME_MPDU
;
1350 rxs
->freq
= ah
->curchan
->center_freq
;
1351 rxs
->band
= ah
->curchan
->band
;
1353 rxs
->signal
= ah
->ah_noise_floor
+ rs
->rs_rssi
;
1355 rxs
->antenna
= rs
->rs_antenna
;
1357 if (rs
->rs_antenna
> 0 && rs
->rs_antenna
< 5)
1358 ah
->stats
.antenna_rx
[rs
->rs_antenna
]++;
1360 ah
->stats
.antenna_rx
[0]++; /* invalid */
1362 rxs
->rate_idx
= ath5k_hw_to_driver_rix(ah
, rs
->rs_rate
);
1363 rxs
->flag
|= ath5k_rx_decrypted(ah
, skb
, rs
);
1365 if (rxs
->rate_idx
>= 0 && rs
->rs_rate
==
1366 ah
->sbands
[ah
->curchan
->band
].bitrates
[rxs
->rate_idx
].hw_value_short
)
1367 rxs
->flag
|= RX_FLAG_SHORTPRE
;
1369 trace_ath5k_rx(ah
, skb
);
1371 ath5k_update_beacon_rssi(ah
, skb
, rs
->rs_rssi
);
1373 /* check beacons in IBSS mode */
1374 if (ah
->opmode
== NL80211_IFTYPE_ADHOC
)
1375 ath5k_check_ibss_tsf(ah
, skb
, rxs
);
1377 ieee80211_rx(ah
->hw
, skb
);
1380 /** ath5k_frame_receive_ok() - Do we want to receive this frame or not?
1382 * Check if we want to further process this frame or not. Also update
1383 * statistics. Return true if we want this frame, false if not.
1386 ath5k_receive_frame_ok(struct ath5k_hw
*ah
, struct ath5k_rx_status
*rs
)
1388 ah
->stats
.rx_all_count
++;
1389 ah
->stats
.rx_bytes_count
+= rs
->rs_datalen
;
1391 if (unlikely(rs
->rs_status
)) {
1392 if (rs
->rs_status
& AR5K_RXERR_CRC
)
1393 ah
->stats
.rxerr_crc
++;
1394 if (rs
->rs_status
& AR5K_RXERR_FIFO
)
1395 ah
->stats
.rxerr_fifo
++;
1396 if (rs
->rs_status
& AR5K_RXERR_PHY
) {
1397 ah
->stats
.rxerr_phy
++;
1398 if (rs
->rs_phyerr
> 0 && rs
->rs_phyerr
< 32)
1399 ah
->stats
.rxerr_phy_code
[rs
->rs_phyerr
]++;
1402 if (rs
->rs_status
& AR5K_RXERR_DECRYPT
) {
1404 * Decrypt error. If the error occurred
1405 * because there was no hardware key, then
1406 * let the frame through so the upper layers
1407 * can process it. This is necessary for 5210
1408 * parts which have no way to setup a ``clear''
1411 * XXX do key cache faulting
1413 ah
->stats
.rxerr_decrypt
++;
1414 if (rs
->rs_keyix
== AR5K_RXKEYIX_INVALID
&&
1415 !(rs
->rs_status
& AR5K_RXERR_CRC
))
1418 if (rs
->rs_status
& AR5K_RXERR_MIC
) {
1419 ah
->stats
.rxerr_mic
++;
1423 /* reject any frames with non-crypto errors */
1424 if (rs
->rs_status
& ~(AR5K_RXERR_DECRYPT
))
1428 if (unlikely(rs
->rs_more
)) {
1429 ah
->stats
.rxerr_jumbo
++;
1436 ath5k_set_current_imask(struct ath5k_hw
*ah
)
1438 enum ath5k_int imask
;
1439 unsigned long flags
;
1441 spin_lock_irqsave(&ah
->irqlock
, flags
);
1444 imask
&= ~AR5K_INT_RX_ALL
;
1446 imask
&= ~AR5K_INT_TX_ALL
;
1447 ath5k_hw_set_imr(ah
, imask
);
1448 spin_unlock_irqrestore(&ah
->irqlock
, flags
);
1452 ath5k_tasklet_rx(unsigned long data
)
1454 struct ath5k_rx_status rs
= {};
1455 struct sk_buff
*skb
, *next_skb
;
1456 dma_addr_t next_skb_addr
;
1457 struct ath5k_hw
*ah
= (void *)data
;
1458 struct ath_common
*common
= ath5k_hw_common(ah
);
1459 struct ath5k_buf
*bf
;
1460 struct ath5k_desc
*ds
;
1463 spin_lock(&ah
->rxbuflock
);
1464 if (list_empty(&ah
->rxbuf
)) {
1465 ATH5K_WARN(ah
, "empty rx buf pool\n");
1469 bf
= list_first_entry(&ah
->rxbuf
, struct ath5k_buf
, list
);
1470 BUG_ON(bf
->skb
== NULL
);
1474 /* bail if HW is still using self-linked descriptor */
1475 if (ath5k_hw_get_rxdp(ah
) == bf
->daddr
)
1478 ret
= ah
->ah_proc_rx_desc(ah
, ds
, &rs
);
1479 if (unlikely(ret
== -EINPROGRESS
))
1481 else if (unlikely(ret
)) {
1482 ATH5K_ERR(ah
, "error in processing rx descriptor\n");
1483 ah
->stats
.rxerr_proc
++;
1487 if (ath5k_receive_frame_ok(ah
, &rs
)) {
1488 next_skb
= ath5k_rx_skb_alloc(ah
, &next_skb_addr
);
1491 * If we can't replace bf->skb with a new skb under
1492 * memory pressure, just skip this packet
1497 dma_unmap_single(ah
->dev
, bf
->skbaddr
,
1501 skb_put(skb
, rs
.rs_datalen
);
1503 ath5k_receive_frame(ah
, skb
, &rs
);
1506 bf
->skbaddr
= next_skb_addr
;
1509 list_move_tail(&bf
->list
, &ah
->rxbuf
);
1510 } while (ath5k_rxbuf_setup(ah
, bf
) == 0);
1512 spin_unlock(&ah
->rxbuflock
);
1513 ah
->rx_pending
= false;
1514 ath5k_set_current_imask(ah
);
1523 ath5k_tx_queue(struct ieee80211_hw
*hw
, struct sk_buff
*skb
,
1524 struct ath5k_txq
*txq
)
1526 struct ath5k_hw
*ah
= hw
->priv
;
1527 struct ath5k_buf
*bf
;
1528 unsigned long flags
;
1531 trace_ath5k_tx(ah
, skb
, txq
);
1534 * The hardware expects the header padded to 4 byte boundaries.
1535 * If this is not the case, we add the padding after the header.
1537 padsize
= ath5k_add_padding(skb
);
1539 ATH5K_ERR(ah
, "tx hdrlen not %%4: not enough"
1540 " headroom to pad");
1544 if (txq
->txq_len
>= txq
->txq_max
&&
1545 txq
->qnum
<= AR5K_TX_QUEUE_ID_DATA_MAX
)
1546 ieee80211_stop_queue(hw
, txq
->qnum
);
1548 spin_lock_irqsave(&ah
->txbuflock
, flags
);
1549 if (list_empty(&ah
->txbuf
)) {
1550 ATH5K_ERR(ah
, "no further txbuf available, dropping packet\n");
1551 spin_unlock_irqrestore(&ah
->txbuflock
, flags
);
1552 ieee80211_stop_queues(hw
);
1555 bf
= list_first_entry(&ah
->txbuf
, struct ath5k_buf
, list
);
1556 list_del(&bf
->list
);
1558 if (list_empty(&ah
->txbuf
))
1559 ieee80211_stop_queues(hw
);
1560 spin_unlock_irqrestore(&ah
->txbuflock
, flags
);
1564 if (ath5k_txbuf_setup(ah
, bf
, txq
, padsize
)) {
1566 spin_lock_irqsave(&ah
->txbuflock
, flags
);
1567 list_add_tail(&bf
->list
, &ah
->txbuf
);
1569 spin_unlock_irqrestore(&ah
->txbuflock
, flags
);
1575 dev_kfree_skb_any(skb
);
1579 ath5k_tx_frame_completed(struct ath5k_hw
*ah
, struct sk_buff
*skb
,
1580 struct ath5k_txq
*txq
, struct ath5k_tx_status
*ts
)
1582 struct ieee80211_tx_info
*info
;
1586 ah
->stats
.tx_all_count
++;
1587 ah
->stats
.tx_bytes_count
+= skb
->len
;
1588 info
= IEEE80211_SKB_CB(skb
);
1590 tries
[0] = info
->status
.rates
[0].count
;
1591 tries
[1] = info
->status
.rates
[1].count
;
1592 tries
[2] = info
->status
.rates
[2].count
;
1594 ieee80211_tx_info_clear_status(info
);
1596 for (i
= 0; i
< ts
->ts_final_idx
; i
++) {
1597 struct ieee80211_tx_rate
*r
=
1598 &info
->status
.rates
[i
];
1600 r
->count
= tries
[i
];
1603 info
->status
.rates
[ts
->ts_final_idx
].count
= ts
->ts_final_retry
;
1604 info
->status
.rates
[ts
->ts_final_idx
+ 1].idx
= -1;
1606 if (unlikely(ts
->ts_status
)) {
1607 ah
->stats
.ack_fail
++;
1608 if (ts
->ts_status
& AR5K_TXERR_FILT
) {
1609 info
->flags
|= IEEE80211_TX_STAT_TX_FILTERED
;
1610 ah
->stats
.txerr_filt
++;
1612 if (ts
->ts_status
& AR5K_TXERR_XRETRY
)
1613 ah
->stats
.txerr_retry
++;
1614 if (ts
->ts_status
& AR5K_TXERR_FIFO
)
1615 ah
->stats
.txerr_fifo
++;
1617 info
->flags
|= IEEE80211_TX_STAT_ACK
;
1618 info
->status
.ack_signal
= ts
->ts_rssi
;
1620 /* count the successful attempt as well */
1621 info
->status
.rates
[ts
->ts_final_idx
].count
++;
1625 * Remove MAC header padding before giving the frame
1628 ath5k_remove_padding(skb
);
1630 if (ts
->ts_antenna
> 0 && ts
->ts_antenna
< 5)
1631 ah
->stats
.antenna_tx
[ts
->ts_antenna
]++;
1633 ah
->stats
.antenna_tx
[0]++; /* invalid */
1635 trace_ath5k_tx_complete(ah
, skb
, txq
, ts
);
1636 ieee80211_tx_status(ah
->hw
, skb
);
1640 ath5k_tx_processq(struct ath5k_hw
*ah
, struct ath5k_txq
*txq
)
1642 struct ath5k_tx_status ts
= {};
1643 struct ath5k_buf
*bf
, *bf0
;
1644 struct ath5k_desc
*ds
;
1645 struct sk_buff
*skb
;
1648 spin_lock(&txq
->lock
);
1649 list_for_each_entry_safe(bf
, bf0
, &txq
->q
, list
) {
1651 txq
->txq_poll_mark
= false;
1653 /* skb might already have been processed last time. */
1654 if (bf
->skb
!= NULL
) {
1657 ret
= ah
->ah_proc_tx_desc(ah
, ds
, &ts
);
1658 if (unlikely(ret
== -EINPROGRESS
))
1660 else if (unlikely(ret
)) {
1662 "error %d while processing "
1663 "queue %u\n", ret
, txq
->qnum
);
1670 dma_unmap_single(ah
->dev
, bf
->skbaddr
, skb
->len
,
1672 ath5k_tx_frame_completed(ah
, skb
, txq
, &ts
);
1676 * It's possible that the hardware can say the buffer is
1677 * completed when it hasn't yet loaded the ds_link from
1678 * host memory and moved on.
1679 * Always keep the last descriptor to avoid HW races...
1681 if (ath5k_hw_get_txdp(ah
, txq
->qnum
) != bf
->daddr
) {
1682 spin_lock(&ah
->txbuflock
);
1683 list_move_tail(&bf
->list
, &ah
->txbuf
);
1686 spin_unlock(&ah
->txbuflock
);
1689 spin_unlock(&txq
->lock
);
1690 if (txq
->txq_len
< ATH5K_TXQ_LEN_LOW
&& txq
->qnum
< 4)
1691 ieee80211_wake_queue(ah
->hw
, txq
->qnum
);
1695 ath5k_tasklet_tx(unsigned long data
)
1698 struct ath5k_hw
*ah
= (void *)data
;
1700 for (i
= 0; i
< AR5K_NUM_TX_QUEUES
; i
++)
1701 if (ah
->txqs
[i
].setup
&& (ah
->ah_txq_isr_txok_all
& BIT(i
)))
1702 ath5k_tx_processq(ah
, &ah
->txqs
[i
]);
1704 ah
->tx_pending
= false;
1705 ath5k_set_current_imask(ah
);
1714 * Setup the beacon frame for transmit.
1717 ath5k_beacon_setup(struct ath5k_hw
*ah
, struct ath5k_buf
*bf
)
1719 struct sk_buff
*skb
= bf
->skb
;
1720 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
1721 struct ath5k_desc
*ds
;
1725 const int padsize
= 0;
1727 bf
->skbaddr
= dma_map_single(ah
->dev
, skb
->data
, skb
->len
,
1729 ATH5K_DBG(ah
, ATH5K_DEBUG_BEACON
, "skb %p [data %p len %u] "
1730 "skbaddr %llx\n", skb
, skb
->data
, skb
->len
,
1731 (unsigned long long)bf
->skbaddr
);
1733 if (dma_mapping_error(ah
->dev
, bf
->skbaddr
)) {
1734 ATH5K_ERR(ah
, "beacon DMA mapping failed\n");
1735 dev_kfree_skb_any(skb
);
1741 antenna
= ah
->ah_tx_ant
;
1743 flags
= AR5K_TXDESC_NOACK
;
1744 if (ah
->opmode
== NL80211_IFTYPE_ADHOC
&& ath5k_hw_hasveol(ah
)) {
1745 ds
->ds_link
= bf
->daddr
; /* self-linked */
1746 flags
|= AR5K_TXDESC_VEOL
;
1751 * If we use multiple antennas on AP and use
1752 * the Sectored AP scenario, switch antenna every
1753 * 4 beacons to make sure everybody hears our AP.
1754 * When a client tries to associate, hw will keep
1755 * track of the tx antenna to be used for this client
1756 * automatically, based on ACKed packets.
1758 * Note: AP still listens and transmits RTS on the
1759 * default antenna which is supposed to be an omni.
1761 * Note2: On sectored scenarios it's possible to have
1762 * multiple antennas (1 omni -- the default -- and 14
1763 * sectors), so if we choose to actually support this
1764 * mode, we need to allow the user to set how many antennas
1765 * we have and tweak the code below to send beacons
1768 if (ah
->ah_ant_mode
== AR5K_ANTMODE_SECTOR_AP
)
1769 antenna
= ah
->bsent
& 4 ? 2 : 1;
1772 /* FIXME: If we are in g mode and rate is a CCK rate
1773 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1774 * from tx power (value is in dB units already) */
1775 ds
->ds_data
= bf
->skbaddr
;
1776 ret
= ah
->ah_setup_tx_desc(ah
, ds
, skb
->len
,
1777 ieee80211_get_hdrlen_from_skb(skb
), padsize
,
1778 AR5K_PKT_TYPE_BEACON
, (ah
->power_level
* 2),
1779 ieee80211_get_tx_rate(ah
->hw
, info
)->hw_value
,
1780 1, AR5K_TXKEYIX_INVALID
,
1781 antenna
, flags
, 0, 0);
1787 dma_unmap_single(ah
->dev
, bf
->skbaddr
, skb
->len
, DMA_TO_DEVICE
);
1792 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
1793 * this is called only once at config_bss time, for AP we do it every
1794 * SWBA interrupt so that the TIM will reflect buffered frames.
1796 * Called with the beacon lock.
1799 ath5k_beacon_update(struct ieee80211_hw
*hw
, struct ieee80211_vif
*vif
)
1802 struct ath5k_hw
*ah
= hw
->priv
;
1803 struct ath5k_vif
*avf
= (void *)vif
->drv_priv
;
1804 struct sk_buff
*skb
;
1806 if (WARN_ON(!vif
)) {
1811 skb
= ieee80211_beacon_get(hw
, vif
);
1818 ath5k_txbuf_free_skb(ah
, avf
->bbuf
);
1819 avf
->bbuf
->skb
= skb
;
1820 ret
= ath5k_beacon_setup(ah
, avf
->bbuf
);
1826 * Transmit a beacon frame at SWBA. Dynamic updates to the
1827 * frame contents are done as needed and the slot time is
1828 * also adjusted based on current state.
1830 * This is called from software irq context (beacontq tasklets)
1831 * or user context from ath5k_beacon_config.
1834 ath5k_beacon_send(struct ath5k_hw
*ah
)
1836 struct ieee80211_vif
*vif
;
1837 struct ath5k_vif
*avf
;
1838 struct ath5k_buf
*bf
;
1839 struct sk_buff
*skb
;
1842 ATH5K_DBG_UNLIMIT(ah
, ATH5K_DEBUG_BEACON
, "in beacon_send\n");
1845 * Check if the previous beacon has gone out. If
1846 * not, don't don't try to post another: skip this
1847 * period and wait for the next. Missed beacons
1848 * indicate a problem and should not occur. If we
1849 * miss too many consecutive beacons reset the device.
1851 if (unlikely(ath5k_hw_num_tx_pending(ah
, ah
->bhalq
) != 0)) {
1853 ATH5K_DBG(ah
, ATH5K_DEBUG_BEACON
,
1854 "missed %u consecutive beacons\n", ah
->bmisscount
);
1855 if (ah
->bmisscount
> 10) { /* NB: 10 is a guess */
1856 ATH5K_DBG(ah
, ATH5K_DEBUG_BEACON
,
1857 "stuck beacon time (%u missed)\n",
1859 ATH5K_DBG(ah
, ATH5K_DEBUG_RESET
,
1860 "stuck beacon, resetting\n");
1861 ieee80211_queue_work(ah
->hw
, &ah
->reset_work
);
1865 if (unlikely(ah
->bmisscount
!= 0)) {
1866 ATH5K_DBG(ah
, ATH5K_DEBUG_BEACON
,
1867 "resume beacon xmit after %u misses\n",
1872 if ((ah
->opmode
== NL80211_IFTYPE_AP
&& ah
->num_ap_vifs
+
1873 ah
->num_mesh_vifs
> 1) ||
1874 ah
->opmode
== NL80211_IFTYPE_MESH_POINT
) {
1875 u64 tsf
= ath5k_hw_get_tsf64(ah
);
1876 u32 tsftu
= TSF_TO_TU(tsf
);
1877 int slot
= ((tsftu
% ah
->bintval
) * ATH_BCBUF
) / ah
->bintval
;
1878 vif
= ah
->bslot
[(slot
+ 1) % ATH_BCBUF
];
1879 ATH5K_DBG(ah
, ATH5K_DEBUG_BEACON
,
1880 "tsf %llx tsftu %x intval %u slot %u vif %p\n",
1881 (unsigned long long)tsf
, tsftu
, ah
->bintval
, slot
, vif
);
1882 } else /* only one interface */
1888 avf
= (void *)vif
->drv_priv
;
1892 * Stop any current dma and put the new frame on the queue.
1893 * This should never fail since we check above that no frames
1894 * are still pending on the queue.
1896 if (unlikely(ath5k_hw_stop_beacon_queue(ah
, ah
->bhalq
))) {
1897 ATH5K_WARN(ah
, "beacon queue %u didn't start/stop ?\n", ah
->bhalq
);
1898 /* NB: hw still stops DMA, so proceed */
1901 /* refresh the beacon for AP or MESH mode */
1902 if (ah
->opmode
== NL80211_IFTYPE_AP
||
1903 ah
->opmode
== NL80211_IFTYPE_MESH_POINT
) {
1904 err
= ath5k_beacon_update(ah
->hw
, vif
);
1909 if (unlikely(bf
->skb
== NULL
|| ah
->opmode
== NL80211_IFTYPE_STATION
||
1910 ah
->opmode
== NL80211_IFTYPE_MONITOR
)) {
1911 ATH5K_WARN(ah
, "bf=%p bf_skb=%p\n", bf
, bf
->skb
);
1915 trace_ath5k_tx(ah
, bf
->skb
, &ah
->txqs
[ah
->bhalq
]);
1917 ath5k_hw_set_txdp(ah
, ah
->bhalq
, bf
->daddr
);
1918 ath5k_hw_start_tx_dma(ah
, ah
->bhalq
);
1919 ATH5K_DBG(ah
, ATH5K_DEBUG_BEACON
, "TXDP[%u] = %llx (%p)\n",
1920 ah
->bhalq
, (unsigned long long)bf
->daddr
, bf
->desc
);
1922 skb
= ieee80211_get_buffered_bc(ah
->hw
, vif
);
1924 ath5k_tx_queue(ah
->hw
, skb
, ah
->cabq
);
1926 if (ah
->cabq
->txq_len
>= ah
->cabq
->txq_max
)
1929 skb
= ieee80211_get_buffered_bc(ah
->hw
, vif
);
1936 * ath5k_beacon_update_timers - update beacon timers
1938 * @ah: struct ath5k_hw pointer we are operating on
1939 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
1940 * beacon timer update based on the current HW TSF.
1942 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
1943 * of a received beacon or the current local hardware TSF and write it to the
1944 * beacon timer registers.
1946 * This is called in a variety of situations, e.g. when a beacon is received,
1947 * when a TSF update has been detected, but also when an new IBSS is created or
1948 * when we otherwise know we have to update the timers, but we keep it in this
1949 * function to have it all together in one place.
1952 ath5k_beacon_update_timers(struct ath5k_hw
*ah
, u64 bc_tsf
)
1954 u32 nexttbtt
, intval
, hw_tu
, bc_tu
;
1957 intval
= ah
->bintval
& AR5K_BEACON_PERIOD
;
1958 if (ah
->opmode
== NL80211_IFTYPE_AP
&& ah
->num_ap_vifs
1959 + ah
->num_mesh_vifs
> 1) {
1960 intval
/= ATH_BCBUF
; /* staggered multi-bss beacons */
1962 ATH5K_WARN(ah
, "intval %u is too low, min 15\n",
1965 if (WARN_ON(!intval
))
1968 /* beacon TSF converted to TU */
1969 bc_tu
= TSF_TO_TU(bc_tsf
);
1971 /* current TSF converted to TU */
1972 hw_tsf
= ath5k_hw_get_tsf64(ah
);
1973 hw_tu
= TSF_TO_TU(hw_tsf
);
1975 #define FUDGE (AR5K_TUNE_SW_BEACON_RESP + 3)
1976 /* We use FUDGE to make sure the next TBTT is ahead of the current TU.
1977 * Since we later subtract AR5K_TUNE_SW_BEACON_RESP (10) in the timer
1978 * configuration we need to make sure it is bigger than that. */
1982 * no beacons received, called internally.
1983 * just need to refresh timers based on HW TSF.
1985 nexttbtt
= roundup(hw_tu
+ FUDGE
, intval
);
1986 } else if (bc_tsf
== 0) {
1988 * no beacon received, probably called by ath5k_reset_tsf().
1989 * reset TSF to start with 0.
1992 intval
|= AR5K_BEACON_RESET_TSF
;
1993 } else if (bc_tsf
> hw_tsf
) {
1995 * beacon received, SW merge happened but HW TSF not yet updated.
1996 * not possible to reconfigure timers yet, but next time we
1997 * receive a beacon with the same BSSID, the hardware will
1998 * automatically update the TSF and then we need to reconfigure
2001 ATH5K_DBG_UNLIMIT(ah
, ATH5K_DEBUG_BEACON
,
2002 "need to wait for HW TSF sync\n");
2006 * most important case for beacon synchronization between STA.
2008 * beacon received and HW TSF has been already updated by HW.
2009 * update next TBTT based on the TSF of the beacon, but make
2010 * sure it is ahead of our local TSF timer.
2012 nexttbtt
= bc_tu
+ roundup(hw_tu
+ FUDGE
- bc_tu
, intval
);
2016 ah
->nexttbtt
= nexttbtt
;
2018 intval
|= AR5K_BEACON_ENA
;
2019 ath5k_hw_init_beacon_timers(ah
, nexttbtt
, intval
);
2022 * debugging output last in order to preserve the time critical aspect
2026 ATH5K_DBG_UNLIMIT(ah
, ATH5K_DEBUG_BEACON
,
2027 "reconfigured timers based on HW TSF\n");
2028 else if (bc_tsf
== 0)
2029 ATH5K_DBG_UNLIMIT(ah
, ATH5K_DEBUG_BEACON
,
2030 "reset HW TSF and timers\n");
2032 ATH5K_DBG_UNLIMIT(ah
, ATH5K_DEBUG_BEACON
,
2033 "updated timers based on beacon TSF\n");
2035 ATH5K_DBG_UNLIMIT(ah
, ATH5K_DEBUG_BEACON
,
2036 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2037 (unsigned long long) bc_tsf
,
2038 (unsigned long long) hw_tsf
, bc_tu
, hw_tu
, nexttbtt
);
2039 ATH5K_DBG_UNLIMIT(ah
, ATH5K_DEBUG_BEACON
, "intval %u %s %s\n",
2040 intval
& AR5K_BEACON_PERIOD
,
2041 intval
& AR5K_BEACON_ENA
? "AR5K_BEACON_ENA" : "",
2042 intval
& AR5K_BEACON_RESET_TSF
? "AR5K_BEACON_RESET_TSF" : "");
2046 * ath5k_beacon_config - Configure the beacon queues and interrupts
2048 * @ah: struct ath5k_hw pointer we are operating on
2050 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2051 * interrupts to detect TSF updates only.
2054 ath5k_beacon_config(struct ath5k_hw
*ah
)
2056 unsigned long flags
;
2058 spin_lock_irqsave(&ah
->block
, flags
);
2060 ah
->imask
&= ~(AR5K_INT_BMISS
| AR5K_INT_SWBA
);
2062 if (ah
->enable_beacon
) {
2064 * In IBSS mode we use a self-linked tx descriptor and let the
2065 * hardware send the beacons automatically. We have to load it
2067 * We use the SWBA interrupt only to keep track of the beacon
2068 * timers in order to detect automatic TSF updates.
2070 ath5k_beaconq_config(ah
);
2072 ah
->imask
|= AR5K_INT_SWBA
;
2074 if (ah
->opmode
== NL80211_IFTYPE_ADHOC
) {
2075 if (ath5k_hw_hasveol(ah
))
2076 ath5k_beacon_send(ah
);
2078 ath5k_beacon_update_timers(ah
, -1);
2080 ath5k_hw_stop_beacon_queue(ah
, ah
->bhalq
);
2083 ath5k_hw_set_imr(ah
, ah
->imask
);
2085 spin_unlock_irqrestore(&ah
->block
, flags
);
2088 static void ath5k_tasklet_beacon(unsigned long data
)
2090 struct ath5k_hw
*ah
= (struct ath5k_hw
*) data
;
2093 * Software beacon alert--time to send a beacon.
2095 * In IBSS mode we use this interrupt just to
2096 * keep track of the next TBTT (target beacon
2097 * transmission time) in order to detect whether
2098 * automatic TSF updates happened.
2100 if (ah
->opmode
== NL80211_IFTYPE_ADHOC
) {
2101 /* XXX: only if VEOL supported */
2102 u64 tsf
= ath5k_hw_get_tsf64(ah
);
2103 ah
->nexttbtt
+= ah
->bintval
;
2104 ATH5K_DBG(ah
, ATH5K_DEBUG_BEACON
,
2105 "SWBA nexttbtt: %x hw_tu: %x "
2109 (unsigned long long) tsf
);
2111 spin_lock(&ah
->block
);
2112 ath5k_beacon_send(ah
);
2113 spin_unlock(&ah
->block
);
2118 /********************\
2119 * Interrupt handling *
2120 \********************/
2123 ath5k_intr_calibration_poll(struct ath5k_hw
*ah
)
2125 if (time_is_before_eq_jiffies(ah
->ah_cal_next_ani
) &&
2126 !(ah
->ah_cal_mask
& AR5K_CALIBRATION_FULL
) &&
2127 !(ah
->ah_cal_mask
& AR5K_CALIBRATION_SHORT
)) {
2129 /* Run ANI only when calibration is not active */
2131 ah
->ah_cal_next_ani
= jiffies
+
2132 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI
);
2133 tasklet_schedule(&ah
->ani_tasklet
);
2135 } else if (time_is_before_eq_jiffies(ah
->ah_cal_next_short
) &&
2136 !(ah
->ah_cal_mask
& AR5K_CALIBRATION_FULL
) &&
2137 !(ah
->ah_cal_mask
& AR5K_CALIBRATION_SHORT
)) {
2139 /* Run calibration only when another calibration
2142 * Note: This is for both full/short calibration,
2143 * if it's time for a full one, ath5k_calibrate_work will deal
2146 ah
->ah_cal_next_short
= jiffies
+
2147 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_SHORT
);
2148 ieee80211_queue_work(ah
->hw
, &ah
->calib_work
);
2150 /* we could use SWI to generate enough interrupts to meet our
2151 * calibration interval requirements, if necessary:
2152 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */
2156 ath5k_schedule_rx(struct ath5k_hw
*ah
)
2158 ah
->rx_pending
= true;
2159 tasklet_schedule(&ah
->rxtq
);
2163 ath5k_schedule_tx(struct ath5k_hw
*ah
)
2165 ah
->tx_pending
= true;
2166 tasklet_schedule(&ah
->txtq
);
2170 ath5k_intr(int irq
, void *dev_id
)
2172 struct ath5k_hw
*ah
= dev_id
;
2173 enum ath5k_int status
;
2174 unsigned int counter
= 1000;
2178 * If hw is not ready (or detached) and we get an
2179 * interrupt, or if we have no interrupts pending
2180 * (that means it's not for us) skip it.
2182 * NOTE: Group 0/1 PCI interface registers are not
2183 * supported on WiSOCs, so we can't check for pending
2184 * interrupts (ISR belongs to another register group
2187 if (unlikely(test_bit(ATH_STAT_INVALID
, ah
->status
) ||
2188 ((ath5k_get_bus_type(ah
) != ATH_AHB
) &&
2189 !ath5k_hw_is_intr_pending(ah
))))
2194 ath5k_hw_get_isr(ah
, &status
); /* NB: clears IRQ too */
2196 ATH5K_DBG(ah
, ATH5K_DEBUG_INTR
, "status 0x%x/0x%x\n",
2200 * Fatal hw error -> Log and reset
2202 * Fatal errors are unrecoverable so we have to
2203 * reset the card. These errors include bus and
2206 if (unlikely(status
& AR5K_INT_FATAL
)) {
2208 ATH5K_DBG(ah
, ATH5K_DEBUG_RESET
,
2209 "fatal int, resetting\n");
2210 ieee80211_queue_work(ah
->hw
, &ah
->reset_work
);
2213 * RX Overrun -> Count and reset if needed
2215 * Receive buffers are full. Either the bus is busy or
2216 * the CPU is not fast enough to process all received
2219 } else if (unlikely(status
& AR5K_INT_RXORN
)) {
2222 * Older chipsets need a reset to come out of this
2223 * condition, but we treat it as RX for newer chips.
2224 * We don't know exactly which versions need a reset
2225 * this guess is copied from the HAL.
2227 ah
->stats
.rxorn_intr
++;
2229 if (ah
->ah_mac_srev
< AR5K_SREV_AR5212
) {
2230 ATH5K_DBG(ah
, ATH5K_DEBUG_RESET
,
2231 "rx overrun, resetting\n");
2232 ieee80211_queue_work(ah
->hw
, &ah
->reset_work
);
2234 ath5k_schedule_rx(ah
);
2238 /* Software Beacon Alert -> Schedule beacon tasklet */
2239 if (status
& AR5K_INT_SWBA
)
2240 tasklet_hi_schedule(&ah
->beacontq
);
2243 * No more RX descriptors -> Just count
2245 * NB: the hardware should re-read the link when
2246 * RXE bit is written, but it doesn't work at
2247 * least on older hardware revs.
2249 if (status
& AR5K_INT_RXEOL
)
2250 ah
->stats
.rxeol_intr
++;
2253 /* TX Underrun -> Bump tx trigger level */
2254 if (status
& AR5K_INT_TXURN
)
2255 ath5k_hw_update_tx_triglevel(ah
, true);
2257 /* RX -> Schedule rx tasklet */
2258 if (status
& (AR5K_INT_RXOK
| AR5K_INT_RXERR
))
2259 ath5k_schedule_rx(ah
);
2261 /* TX -> Schedule tx tasklet */
2262 if (status
& (AR5K_INT_TXOK
2266 ath5k_schedule_tx(ah
);
2268 /* Missed beacon -> TODO
2269 if (status & AR5K_INT_BMISS)
2272 /* MIB event -> Update counters and notify ANI */
2273 if (status
& AR5K_INT_MIB
) {
2274 ah
->stats
.mib_intr
++;
2275 ath5k_hw_update_mib_counters(ah
);
2276 ath5k_ani_mib_intr(ah
);
2279 /* GPIO -> Notify RFKill layer */
2280 if (status
& AR5K_INT_GPIO
)
2281 tasklet_schedule(&ah
->rf_kill
.toggleq
);
2285 if (ath5k_get_bus_type(ah
) == ATH_AHB
)
2288 } while (ath5k_hw_is_intr_pending(ah
) && --counter
> 0);
2291 * Until we handle rx/tx interrupts mask them on IMR
2293 * NOTE: ah->(rx/tx)_pending are set when scheduling the tasklets
2294 * and unset after we 've handled the interrupts.
2296 if (ah
->rx_pending
|| ah
->tx_pending
)
2297 ath5k_set_current_imask(ah
);
2299 if (unlikely(!counter
))
2300 ATH5K_WARN(ah
, "too many interrupts, giving up for now\n");
2302 /* Fire up calibration poll */
2303 ath5k_intr_calibration_poll(ah
);
2309 * Periodically recalibrate the PHY to account
2310 * for temperature/environment changes.
2313 ath5k_calibrate_work(struct work_struct
*work
)
2315 struct ath5k_hw
*ah
= container_of(work
, struct ath5k_hw
,
2318 /* Should we run a full calibration ? */
2319 if (time_is_before_eq_jiffies(ah
->ah_cal_next_full
)) {
2321 ah
->ah_cal_next_full
= jiffies
+
2322 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL
);
2323 ah
->ah_cal_mask
|= AR5K_CALIBRATION_FULL
;
2325 ATH5K_DBG(ah
, ATH5K_DEBUG_CALIBRATE
,
2326 "running full calibration\n");
2328 if (ath5k_hw_gainf_calibrate(ah
) == AR5K_RFGAIN_NEED_CHANGE
) {
2330 * Rfgain is out of bounds, reset the chip
2331 * to load new gain values.
2333 ATH5K_DBG(ah
, ATH5K_DEBUG_RESET
,
2334 "got new rfgain, resetting\n");
2335 ieee80211_queue_work(ah
->hw
, &ah
->reset_work
);
2338 ah
->ah_cal_mask
|= AR5K_CALIBRATION_SHORT
;
2341 ATH5K_DBG(ah
, ATH5K_DEBUG_CALIBRATE
, "channel %u/%x\n",
2342 ieee80211_frequency_to_channel(ah
->curchan
->center_freq
),
2343 ah
->curchan
->hw_value
);
2345 if (ath5k_hw_phy_calibrate(ah
, ah
->curchan
))
2346 ATH5K_ERR(ah
, "calibration of channel %u failed\n",
2347 ieee80211_frequency_to_channel(
2348 ah
->curchan
->center_freq
));
2350 /* Clear calibration flags */
2351 if (ah
->ah_cal_mask
& AR5K_CALIBRATION_FULL
)
2352 ah
->ah_cal_mask
&= ~AR5K_CALIBRATION_FULL
;
2353 else if (ah
->ah_cal_mask
& AR5K_CALIBRATION_SHORT
)
2354 ah
->ah_cal_mask
&= ~AR5K_CALIBRATION_SHORT
;
2359 ath5k_tasklet_ani(unsigned long data
)
2361 struct ath5k_hw
*ah
= (void *)data
;
2363 ah
->ah_cal_mask
|= AR5K_CALIBRATION_ANI
;
2364 ath5k_ani_calibration(ah
);
2365 ah
->ah_cal_mask
&= ~AR5K_CALIBRATION_ANI
;
2370 ath5k_tx_complete_poll_work(struct work_struct
*work
)
2372 struct ath5k_hw
*ah
= container_of(work
, struct ath5k_hw
,
2373 tx_complete_work
.work
);
2374 struct ath5k_txq
*txq
;
2376 bool needreset
= false;
2378 mutex_lock(&ah
->lock
);
2380 for (i
= 0; i
< ARRAY_SIZE(ah
->txqs
); i
++) {
2381 if (ah
->txqs
[i
].setup
) {
2383 spin_lock_bh(&txq
->lock
);
2384 if (txq
->txq_len
> 1) {
2385 if (txq
->txq_poll_mark
) {
2386 ATH5K_DBG(ah
, ATH5K_DEBUG_XMIT
,
2387 "TX queue stuck %d\n",
2391 spin_unlock_bh(&txq
->lock
);
2394 txq
->txq_poll_mark
= true;
2397 spin_unlock_bh(&txq
->lock
);
2402 ATH5K_DBG(ah
, ATH5K_DEBUG_RESET
,
2403 "TX queues stuck, resetting\n");
2404 ath5k_reset(ah
, NULL
, true);
2407 mutex_unlock(&ah
->lock
);
2409 ieee80211_queue_delayed_work(ah
->hw
, &ah
->tx_complete_work
,
2410 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT
));
2414 /*************************\
2415 * Initialization routines *
2416 \*************************/
2418 static const struct ieee80211_iface_limit if_limits
[] = {
2419 { .max
= 2048, .types
= BIT(NL80211_IFTYPE_STATION
) },
2420 { .max
= 4, .types
=
2421 #ifdef CONFIG_MAC80211_MESH
2422 BIT(NL80211_IFTYPE_MESH_POINT
) |
2424 BIT(NL80211_IFTYPE_AP
) },
2427 static const struct ieee80211_iface_combination if_comb
= {
2428 .limits
= if_limits
,
2429 .n_limits
= ARRAY_SIZE(if_limits
),
2430 .max_interfaces
= 2048,
2431 .num_different_channels
= 1,
2435 ath5k_init_ah(struct ath5k_hw
*ah
, const struct ath_bus_ops
*bus_ops
)
2437 struct ieee80211_hw
*hw
= ah
->hw
;
2438 struct ath_common
*common
;
2442 /* Initialize driver private data */
2443 SET_IEEE80211_DEV(hw
, ah
->dev
);
2444 hw
->flags
= IEEE80211_HW_RX_INCLUDES_FCS
|
2445 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING
|
2446 IEEE80211_HW_SIGNAL_DBM
|
2447 IEEE80211_HW_REPORTS_TX_ACK_STATUS
;
2449 hw
->wiphy
->interface_modes
=
2450 BIT(NL80211_IFTYPE_AP
) |
2451 BIT(NL80211_IFTYPE_STATION
) |
2452 BIT(NL80211_IFTYPE_ADHOC
) |
2453 BIT(NL80211_IFTYPE_MESH_POINT
);
2455 hw
->wiphy
->iface_combinations
= &if_comb
;
2456 hw
->wiphy
->n_iface_combinations
= 1;
2458 /* SW support for IBSS_RSN is provided by mac80211 */
2459 hw
->wiphy
->flags
|= WIPHY_FLAG_IBSS_RSN
;
2461 /* both antennas can be configured as RX or TX */
2462 hw
->wiphy
->available_antennas_tx
= 0x3;
2463 hw
->wiphy
->available_antennas_rx
= 0x3;
2465 hw
->extra_tx_headroom
= 2;
2466 hw
->channel_change_time
= 5000;
2469 * Mark the device as detached to avoid processing
2470 * interrupts until setup is complete.
2472 __set_bit(ATH_STAT_INVALID
, ah
->status
);
2474 ah
->opmode
= NL80211_IFTYPE_STATION
;
2476 mutex_init(&ah
->lock
);
2477 spin_lock_init(&ah
->rxbuflock
);
2478 spin_lock_init(&ah
->txbuflock
);
2479 spin_lock_init(&ah
->block
);
2480 spin_lock_init(&ah
->irqlock
);
2482 /* Setup interrupt handler */
2483 ret
= request_irq(ah
->irq
, ath5k_intr
, IRQF_SHARED
, "ath", ah
);
2485 ATH5K_ERR(ah
, "request_irq failed\n");
2489 common
= ath5k_hw_common(ah
);
2490 common
->ops
= &ath5k_common_ops
;
2491 common
->bus_ops
= bus_ops
;
2495 common
->clockrate
= 40;
2498 * Cache line size is used to size and align various
2499 * structures used to communicate with the hardware.
2501 ath5k_read_cachesize(common
, &csz
);
2502 common
->cachelsz
= csz
<< 2; /* convert to bytes */
2504 spin_lock_init(&common
->cc_lock
);
2506 /* Initialize device */
2507 ret
= ath5k_hw_init(ah
);
2511 /* Set up multi-rate retry capabilities */
2512 if (ah
->ah_capabilities
.cap_has_mrr_support
) {
2514 hw
->max_rate_tries
= max(AR5K_INIT_RETRY_SHORT
,
2515 AR5K_INIT_RETRY_LONG
);
2518 hw
->vif_data_size
= sizeof(struct ath5k_vif
);
2520 /* Finish private driver data initialization */
2521 ret
= ath5k_init(hw
);
2525 ATH5K_INFO(ah
, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
2526 ath5k_chip_name(AR5K_VERSION_MAC
, ah
->ah_mac_srev
),
2528 ah
->ah_phy_revision
);
2530 if (!ah
->ah_single_chip
) {
2531 /* Single chip radio (!RF5111) */
2532 if (ah
->ah_radio_5ghz_revision
&&
2533 !ah
->ah_radio_2ghz_revision
) {
2534 /* No 5GHz support -> report 2GHz radio */
2535 if (!test_bit(AR5K_MODE_11A
,
2536 ah
->ah_capabilities
.cap_mode
)) {
2537 ATH5K_INFO(ah
, "RF%s 2GHz radio found (0x%x)\n",
2538 ath5k_chip_name(AR5K_VERSION_RAD
,
2539 ah
->ah_radio_5ghz_revision
),
2540 ah
->ah_radio_5ghz_revision
);
2541 /* No 2GHz support (5110 and some
2542 * 5GHz only cards) -> report 5GHz radio */
2543 } else if (!test_bit(AR5K_MODE_11B
,
2544 ah
->ah_capabilities
.cap_mode
)) {
2545 ATH5K_INFO(ah
, "RF%s 5GHz radio found (0x%x)\n",
2546 ath5k_chip_name(AR5K_VERSION_RAD
,
2547 ah
->ah_radio_5ghz_revision
),
2548 ah
->ah_radio_5ghz_revision
);
2549 /* Multiband radio */
2551 ATH5K_INFO(ah
, "RF%s multiband radio found"
2553 ath5k_chip_name(AR5K_VERSION_RAD
,
2554 ah
->ah_radio_5ghz_revision
),
2555 ah
->ah_radio_5ghz_revision
);
2558 /* Multi chip radio (RF5111 - RF2111) ->
2559 * report both 2GHz/5GHz radios */
2560 else if (ah
->ah_radio_5ghz_revision
&&
2561 ah
->ah_radio_2ghz_revision
) {
2562 ATH5K_INFO(ah
, "RF%s 5GHz radio found (0x%x)\n",
2563 ath5k_chip_name(AR5K_VERSION_RAD
,
2564 ah
->ah_radio_5ghz_revision
),
2565 ah
->ah_radio_5ghz_revision
);
2566 ATH5K_INFO(ah
, "RF%s 2GHz radio found (0x%x)\n",
2567 ath5k_chip_name(AR5K_VERSION_RAD
,
2568 ah
->ah_radio_2ghz_revision
),
2569 ah
->ah_radio_2ghz_revision
);
2573 ath5k_debug_init_device(ah
);
2575 /* ready to process interrupts */
2576 __clear_bit(ATH_STAT_INVALID
, ah
->status
);
2580 ath5k_hw_deinit(ah
);
2582 free_irq(ah
->irq
, ah
);
2588 ath5k_stop_locked(struct ath5k_hw
*ah
)
2591 ATH5K_DBG(ah
, ATH5K_DEBUG_RESET
, "invalid %u\n",
2592 test_bit(ATH_STAT_INVALID
, ah
->status
));
2595 * Shutdown the hardware and driver:
2596 * stop output from above
2597 * disable interrupts
2599 * turn off the radio
2600 * clear transmit machinery
2601 * clear receive machinery
2602 * drain and release tx queues
2603 * reclaim beacon resources
2604 * power down hardware
2606 * Note that some of this work is not possible if the
2607 * hardware is gone (invalid).
2609 ieee80211_stop_queues(ah
->hw
);
2611 if (!test_bit(ATH_STAT_INVALID
, ah
->status
)) {
2613 ath5k_hw_set_imr(ah
, 0);
2614 synchronize_irq(ah
->irq
);
2616 ath5k_hw_dma_stop(ah
);
2617 ath5k_drain_tx_buffs(ah
);
2618 ath5k_hw_phy_disable(ah
);
2624 int ath5k_start(struct ieee80211_hw
*hw
)
2626 struct ath5k_hw
*ah
= hw
->priv
;
2627 struct ath_common
*common
= ath5k_hw_common(ah
);
2630 mutex_lock(&ah
->lock
);
2632 ATH5K_DBG(ah
, ATH5K_DEBUG_RESET
, "mode %d\n", ah
->opmode
);
2635 * Stop anything previously setup. This is safe
2636 * no matter this is the first time through or not.
2638 ath5k_stop_locked(ah
);
2641 * The basic interface to setting the hardware in a good
2642 * state is ``reset''. On return the hardware is known to
2643 * be powered up and with interrupts disabled. This must
2644 * be followed by initialization of the appropriate bits
2645 * and then setup of the interrupt mask.
2647 ah
->curchan
= ah
->hw
->conf
.channel
;
2648 ah
->imask
= AR5K_INT_RXOK
2658 ret
= ath5k_reset(ah
, NULL
, false);
2662 if (!ath5k_modparam_no_hw_rfkill_switch
)
2663 ath5k_rfkill_hw_start(ah
);
2666 * Reset the key cache since some parts do not reset the
2667 * contents on initial power up or resume from suspend.
2669 for (i
= 0; i
< common
->keymax
; i
++)
2670 ath_hw_keyreset(common
, (u16
) i
);
2672 /* Use higher rates for acks instead of base
2674 ah
->ah_ack_bitrate_high
= true;
2676 for (i
= 0; i
< ARRAY_SIZE(ah
->bslot
); i
++)
2677 ah
->bslot
[i
] = NULL
;
2682 mutex_unlock(&ah
->lock
);
2684 ieee80211_queue_delayed_work(ah
->hw
, &ah
->tx_complete_work
,
2685 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT
));
2690 static void ath5k_stop_tasklets(struct ath5k_hw
*ah
)
2692 ah
->rx_pending
= false;
2693 ah
->tx_pending
= false;
2694 tasklet_kill(&ah
->rxtq
);
2695 tasklet_kill(&ah
->txtq
);
2696 tasklet_kill(&ah
->beacontq
);
2697 tasklet_kill(&ah
->ani_tasklet
);
2701 * Stop the device, grabbing the top-level lock to protect
2702 * against concurrent entry through ath5k_init (which can happen
2703 * if another thread does a system call and the thread doing the
2704 * stop is preempted).
2706 void ath5k_stop(struct ieee80211_hw
*hw
)
2708 struct ath5k_hw
*ah
= hw
->priv
;
2711 mutex_lock(&ah
->lock
);
2712 ret
= ath5k_stop_locked(ah
);
2713 if (ret
== 0 && !test_bit(ATH_STAT_INVALID
, ah
->status
)) {
2715 * Don't set the card in full sleep mode!
2717 * a) When the device is in this state it must be carefully
2718 * woken up or references to registers in the PCI clock
2719 * domain may freeze the bus (and system). This varies
2720 * by chip and is mostly an issue with newer parts
2721 * (madwifi sources mentioned srev >= 0x78) that go to
2722 * sleep more quickly.
2724 * b) On older chips full sleep results a weird behaviour
2725 * during wakeup. I tested various cards with srev < 0x78
2726 * and they don't wake up after module reload, a second
2727 * module reload is needed to bring the card up again.
2729 * Until we figure out what's going on don't enable
2730 * full chip reset on any chip (this is what Legacy HAL
2731 * and Sam's HAL do anyway). Instead Perform a full reset
2732 * on the device (same as initial state after attach) and
2733 * leave it idle (keep MAC/BB on warm reset) */
2734 ret
= ath5k_hw_on_hold(ah
);
2736 ATH5K_DBG(ah
, ATH5K_DEBUG_RESET
,
2737 "putting device to sleep\n");
2741 mutex_unlock(&ah
->lock
);
2743 ath5k_stop_tasklets(ah
);
2745 cancel_delayed_work_sync(&ah
->tx_complete_work
);
2747 if (!ath5k_modparam_no_hw_rfkill_switch
)
2748 ath5k_rfkill_hw_stop(ah
);
2752 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2753 * and change to the given channel.
2755 * This should be called with ah->lock.
2758 ath5k_reset(struct ath5k_hw
*ah
, struct ieee80211_channel
*chan
,
2761 struct ath_common
*common
= ath5k_hw_common(ah
);
2765 ATH5K_DBG(ah
, ATH5K_DEBUG_RESET
, "resetting\n");
2767 ath5k_hw_set_imr(ah
, 0);
2768 synchronize_irq(ah
->irq
);
2769 ath5k_stop_tasklets(ah
);
2771 /* Save ani mode and disable ANI during
2772 * reset. If we don't we might get false
2773 * PHY error interrupts. */
2774 ani_mode
= ah
->ani_state
.ani_mode
;
2775 ath5k_ani_init(ah
, ATH5K_ANI_MODE_OFF
);
2777 /* We are going to empty hw queues
2778 * so we should also free any remaining
2780 ath5k_drain_tx_buffs(ah
);
2784 fast
= ((chan
!= NULL
) && modparam_fastchanswitch
) ? 1 : 0;
2786 ret
= ath5k_hw_reset(ah
, ah
->opmode
, ah
->curchan
, fast
, skip_pcu
);
2788 ATH5K_ERR(ah
, "can't reset hardware (%d)\n", ret
);
2792 ret
= ath5k_rx_start(ah
);
2794 ATH5K_ERR(ah
, "can't start recv logic\n");
2798 ath5k_ani_init(ah
, ani_mode
);
2801 * Set calibration intervals
2803 * Note: We don't need to run calibration imediately
2804 * since some initial calibration is done on reset
2805 * even for fast channel switching. Also on scanning
2806 * this will get set again and again and it won't get
2807 * executed unless we connect somewhere and spend some
2808 * time on the channel (that's what calibration needs
2809 * anyway to be accurate).
2811 ah
->ah_cal_next_full
= jiffies
+
2812 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL
);
2813 ah
->ah_cal_next_ani
= jiffies
+
2814 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI
);
2815 ah
->ah_cal_next_short
= jiffies
+
2816 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_SHORT
);
2818 ewma_init(&ah
->ah_beacon_rssi_avg
, 1024, 8);
2820 /* clear survey data and cycle counters */
2821 memset(&ah
->survey
, 0, sizeof(ah
->survey
));
2822 spin_lock_bh(&common
->cc_lock
);
2823 ath_hw_cycle_counters_update(common
);
2824 memset(&common
->cc_survey
, 0, sizeof(common
->cc_survey
));
2825 memset(&common
->cc_ani
, 0, sizeof(common
->cc_ani
));
2826 spin_unlock_bh(&common
->cc_lock
);
2829 * Change channels and update the h/w rate map if we're switching;
2830 * e.g. 11a to 11b/g.
2832 * We may be doing a reset in response to an ioctl that changes the
2833 * channel so update any state that might change as a result.
2837 /* ath5k_chan_change(ah, c); */
2839 ath5k_beacon_config(ah
);
2840 /* intrs are enabled by ath5k_beacon_config */
2842 ieee80211_wake_queues(ah
->hw
);
2849 static void ath5k_reset_work(struct work_struct
*work
)
2851 struct ath5k_hw
*ah
= container_of(work
, struct ath5k_hw
,
2854 mutex_lock(&ah
->lock
);
2855 ath5k_reset(ah
, NULL
, true);
2856 mutex_unlock(&ah
->lock
);
2859 static int __devinit
2860 ath5k_init(struct ieee80211_hw
*hw
)
2863 struct ath5k_hw
*ah
= hw
->priv
;
2864 struct ath_regulatory
*regulatory
= ath5k_hw_regulatory(ah
);
2865 struct ath5k_txq
*txq
;
2866 u8 mac
[ETH_ALEN
] = {};
2871 * Collect the channel list. The 802.11 layer
2872 * is responsible for filtering this list based
2873 * on settings like the phy mode and regulatory
2874 * domain restrictions.
2876 ret
= ath5k_setup_bands(hw
);
2878 ATH5K_ERR(ah
, "can't get channels\n");
2883 * Allocate tx+rx descriptors and populate the lists.
2885 ret
= ath5k_desc_alloc(ah
);
2887 ATH5K_ERR(ah
, "can't allocate descriptors\n");
2892 * Allocate hardware transmit queues: one queue for
2893 * beacon frames and one data queue for each QoS
2894 * priority. Note that hw functions handle resetting
2895 * these queues at the needed time.
2897 ret
= ath5k_beaconq_setup(ah
);
2899 ATH5K_ERR(ah
, "can't setup a beacon xmit queue\n");
2903 ah
->cabq
= ath5k_txq_setup(ah
, AR5K_TX_QUEUE_CAB
, 0);
2904 if (IS_ERR(ah
->cabq
)) {
2905 ATH5K_ERR(ah
, "can't setup cab queue\n");
2906 ret
= PTR_ERR(ah
->cabq
);
2910 /* 5211 and 5212 usually support 10 queues but we better rely on the
2911 * capability information */
2912 if (ah
->ah_capabilities
.cap_queues
.q_tx_num
>= 6) {
2913 /* This order matches mac80211's queue priority, so we can
2914 * directly use the mac80211 queue number without any mapping */
2915 txq
= ath5k_txq_setup(ah
, AR5K_TX_QUEUE_DATA
, AR5K_WME_AC_VO
);
2917 ATH5K_ERR(ah
, "can't setup xmit queue\n");
2921 txq
= ath5k_txq_setup(ah
, AR5K_TX_QUEUE_DATA
, AR5K_WME_AC_VI
);
2923 ATH5K_ERR(ah
, "can't setup xmit queue\n");
2927 txq
= ath5k_txq_setup(ah
, AR5K_TX_QUEUE_DATA
, AR5K_WME_AC_BE
);
2929 ATH5K_ERR(ah
, "can't setup xmit queue\n");
2933 txq
= ath5k_txq_setup(ah
, AR5K_TX_QUEUE_DATA
, AR5K_WME_AC_BK
);
2935 ATH5K_ERR(ah
, "can't setup xmit queue\n");
2941 /* older hardware (5210) can only support one data queue */
2942 txq
= ath5k_txq_setup(ah
, AR5K_TX_QUEUE_DATA
, AR5K_WME_AC_BE
);
2944 ATH5K_ERR(ah
, "can't setup xmit queue\n");
2951 tasklet_init(&ah
->rxtq
, ath5k_tasklet_rx
, (unsigned long)ah
);
2952 tasklet_init(&ah
->txtq
, ath5k_tasklet_tx
, (unsigned long)ah
);
2953 tasklet_init(&ah
->beacontq
, ath5k_tasklet_beacon
, (unsigned long)ah
);
2954 tasklet_init(&ah
->ani_tasklet
, ath5k_tasklet_ani
, (unsigned long)ah
);
2956 INIT_WORK(&ah
->reset_work
, ath5k_reset_work
);
2957 INIT_WORK(&ah
->calib_work
, ath5k_calibrate_work
);
2958 INIT_DELAYED_WORK(&ah
->tx_complete_work
, ath5k_tx_complete_poll_work
);
2960 ret
= ath5k_hw_common(ah
)->bus_ops
->eeprom_read_mac(ah
, mac
);
2962 ATH5K_ERR(ah
, "unable to read address from EEPROM\n");
2966 SET_IEEE80211_PERM_ADDR(hw
, mac
);
2967 /* All MAC address bits matter for ACKs */
2968 ath5k_update_bssid_mask_and_opmode(ah
, NULL
);
2970 regulatory
->current_rd
= ah
->ah_capabilities
.cap_eeprom
.ee_regdomain
;
2971 ret
= ath_regd_init(regulatory
, hw
->wiphy
, ath5k_reg_notifier
);
2973 ATH5K_ERR(ah
, "can't initialize regulatory system\n");
2977 ret
= ieee80211_register_hw(hw
);
2979 ATH5K_ERR(ah
, "can't register ieee80211 hw\n");
2983 if (!ath_is_world_regd(regulatory
))
2984 regulatory_hint(hw
->wiphy
, regulatory
->alpha2
);
2986 ath5k_init_leds(ah
);
2988 ath5k_sysfs_register(ah
);
2992 ath5k_txq_release(ah
);
2994 ath5k_hw_release_tx_queue(ah
, ah
->bhalq
);
2996 ath5k_desc_free(ah
);
3002 ath5k_deinit_ah(struct ath5k_hw
*ah
)
3004 struct ieee80211_hw
*hw
= ah
->hw
;
3007 * NB: the order of these is important:
3008 * o call the 802.11 layer before detaching ath5k_hw to
3009 * ensure callbacks into the driver to delete global
3010 * key cache entries can be handled
3011 * o reclaim the tx queue data structures after calling
3012 * the 802.11 layer as we'll get called back to reclaim
3013 * node state and potentially want to use them
3014 * o to cleanup the tx queues the hal is called, so detach
3016 * XXX: ??? detach ath5k_hw ???
3017 * Other than that, it's straightforward...
3019 ieee80211_unregister_hw(hw
);
3020 ath5k_desc_free(ah
);
3021 ath5k_txq_release(ah
);
3022 ath5k_hw_release_tx_queue(ah
, ah
->bhalq
);
3023 ath5k_unregister_leds(ah
);
3025 ath5k_sysfs_unregister(ah
);
3027 * NB: can't reclaim these until after ieee80211_ifdetach
3028 * returns because we'll get called back to reclaim node
3029 * state and potentially want to use them.
3031 ath5k_hw_deinit(ah
);
3032 free_irq(ah
->irq
, ah
);
3036 ath5k_any_vif_assoc(struct ath5k_hw
*ah
)
3038 struct ath5k_vif_iter_data iter_data
;
3039 iter_data
.hw_macaddr
= NULL
;
3040 iter_data
.any_assoc
= false;
3041 iter_data
.need_set_hw_addr
= false;
3042 iter_data
.found_active
= true;
3044 ieee80211_iterate_active_interfaces_atomic(ah
->hw
, ath5k_vif_iter
,
3046 return iter_data
.any_assoc
;
3050 ath5k_set_beacon_filter(struct ieee80211_hw
*hw
, bool enable
)
3052 struct ath5k_hw
*ah
= hw
->priv
;
3054 rfilt
= ath5k_hw_get_rx_filter(ah
);
3056 rfilt
|= AR5K_RX_FILTER_BEACON
;
3058 rfilt
&= ~AR5K_RX_FILTER_BEACON
;
3059 ath5k_hw_set_rx_filter(ah
, rfilt
);
3060 ah
->filter_flags
= rfilt
;
3063 void _ath5k_printk(const struct ath5k_hw
*ah
, const char *level
,
3064 const char *fmt
, ...)
3066 struct va_format vaf
;
3069 va_start(args
, fmt
);
3075 printk("%s" pr_fmt("%s: %pV"),
3076 level
, wiphy_name(ah
->hw
->wiphy
), &vaf
);
3078 printk("%s" pr_fmt("%pV"), level
, &vaf
);