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ath5k: fix reference clock frequency for spur mitigation on AR2413
[deliverable/linux.git] / drivers / net / wireless / ath / ath5k / phy.c
1 /*
2 * PHY functions
3 *
4 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
5 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
7 * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org>
8 *
9 * Permission to use, copy, modify, and distribute this software for any
10 * purpose with or without fee is hereby granted, provided that the above
11 * copyright notice and this permission notice appear in all copies.
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 *
21 */
22
23 #include <linux/delay.h>
24 #include <linux/slab.h>
25
26 #include "ath5k.h"
27 #include "reg.h"
28 #include "base.h"
29 #include "rfbuffer.h"
30 #include "rfgain.h"
31
32
33 /******************\
34 * Helper functions *
35 \******************/
36
37 /*
38 * Get the PHY Chip revision
39 */
40 u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan)
41 {
42 unsigned int i;
43 u32 srev;
44 u16 ret;
45
46 /*
47 * Set the radio chip access register
48 */
49 switch (chan) {
50 case CHANNEL_2GHZ:
51 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0));
52 break;
53 case CHANNEL_5GHZ:
54 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
55 break;
56 default:
57 return 0;
58 }
59
60 mdelay(2);
61
62 /* ...wait until PHY is ready and read the selected radio revision */
63 ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34));
64
65 for (i = 0; i < 8; i++)
66 ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20));
67
68 if (ah->ah_version == AR5K_AR5210) {
69 srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf;
70 ret = (u16)ath5k_hw_bitswap(srev, 4) + 1;
71 } else {
72 srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff;
73 ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) |
74 ((srev & 0x0f) << 4), 8);
75 }
76
77 /* Reset to the 5GHz mode */
78 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
79
80 return ret;
81 }
82
83 /*
84 * Check if a channel is supported
85 */
86 bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags)
87 {
88 /* Check if the channel is in our supported range */
89 if (flags & CHANNEL_2GHZ) {
90 if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) &&
91 (freq <= ah->ah_capabilities.cap_range.range_2ghz_max))
92 return true;
93 } else if (flags & CHANNEL_5GHZ)
94 if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) &&
95 (freq <= ah->ah_capabilities.cap_range.range_5ghz_max))
96 return true;
97
98 return false;
99 }
100
101 bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
102 struct ieee80211_channel *channel)
103 {
104 u8 refclk_freq;
105
106 if ((ah->ah_radio == AR5K_RF5112) ||
107 (ah->ah_radio == AR5K_RF5413) ||
108 (ah->ah_radio == AR5K_RF2413) ||
109 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
110 refclk_freq = 40;
111 else
112 refclk_freq = 32;
113
114 if ((channel->center_freq % refclk_freq != 0) &&
115 ((channel->center_freq % refclk_freq < 10) ||
116 (channel->center_freq % refclk_freq > 22)))
117 return true;
118 else
119 return false;
120 }
121
122 /*
123 * Used to modify RF Banks before writing them to AR5K_RF_BUFFER
124 */
125 static unsigned int ath5k_hw_rfb_op(struct ath5k_hw *ah,
126 const struct ath5k_rf_reg *rf_regs,
127 u32 val, u8 reg_id, bool set)
128 {
129 const struct ath5k_rf_reg *rfreg = NULL;
130 u8 offset, bank, num_bits, col, position;
131 u16 entry;
132 u32 mask, data, last_bit, bits_shifted, first_bit;
133 u32 *rfb;
134 s32 bits_left;
135 int i;
136
137 data = 0;
138 rfb = ah->ah_rf_banks;
139
140 for (i = 0; i < ah->ah_rf_regs_count; i++) {
141 if (rf_regs[i].index == reg_id) {
142 rfreg = &rf_regs[i];
143 break;
144 }
145 }
146
147 if (rfb == NULL || rfreg == NULL) {
148 ATH5K_PRINTF("Rf register not found!\n");
149 /* should not happen */
150 return 0;
151 }
152
153 bank = rfreg->bank;
154 num_bits = rfreg->field.len;
155 first_bit = rfreg->field.pos;
156 col = rfreg->field.col;
157
158 /* first_bit is an offset from bank's
159 * start. Since we have all banks on
160 * the same array, we use this offset
161 * to mark each bank's start */
162 offset = ah->ah_offset[bank];
163
164 /* Boundary check */
165 if (!(col <= 3 && num_bits <= 32 && first_bit + num_bits <= 319)) {
166 ATH5K_PRINTF("invalid values at offset %u\n", offset);
167 return 0;
168 }
169
170 entry = ((first_bit - 1) / 8) + offset;
171 position = (first_bit - 1) % 8;
172
173 if (set)
174 data = ath5k_hw_bitswap(val, num_bits);
175
176 for (bits_shifted = 0, bits_left = num_bits; bits_left > 0;
177 position = 0, entry++) {
178
179 last_bit = (position + bits_left > 8) ? 8 :
180 position + bits_left;
181
182 mask = (((1 << last_bit) - 1) ^ ((1 << position) - 1)) <<
183 (col * 8);
184
185 if (set) {
186 rfb[entry] &= ~mask;
187 rfb[entry] |= ((data << position) << (col * 8)) & mask;
188 data >>= (8 - position);
189 } else {
190 data |= (((rfb[entry] & mask) >> (col * 8)) >> position)
191 << bits_shifted;
192 bits_shifted += last_bit - position;
193 }
194
195 bits_left -= 8 - position;
196 }
197
198 data = set ? 1 : ath5k_hw_bitswap(data, num_bits);
199
200 return data;
201 }
202
203 /**
204 * ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212
205 *
206 * @ah: the &struct ath5k_hw
207 * @channel: the currently set channel upon reset
208 *
209 * Write the delta slope coefficient (used on pilot tracking ?) for OFDM
210 * operation on the AR5212 upon reset. This is a helper for ath5k_hw_phy_init.
211 *
212 * Since delta slope is floating point we split it on its exponent and
213 * mantissa and provide these values on hw.
214 *
215 * For more infos i think this patent is related
216 * http://www.freepatentsonline.com/7184495.html
217 */
218 static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah,
219 struct ieee80211_channel *channel)
220 {
221 /* Get exponent and mantissa and set it */
222 u32 coef_scaled, coef_exp, coef_man,
223 ds_coef_exp, ds_coef_man, clock;
224
225 BUG_ON(!(ah->ah_version == AR5K_AR5212) ||
226 !(channel->hw_value & CHANNEL_OFDM));
227
228 /* Get coefficient
229 * ALGO: coef = (5 * clock / carrier_freq) / 2
230 * we scale coef by shifting clock value by 24 for
231 * better precision since we use integers */
232 switch (ah->ah_bwmode) {
233 case AR5K_BWMODE_40MHZ:
234 clock = 40 * 2;
235 break;
236 case AR5K_BWMODE_10MHZ:
237 clock = 40 / 2;
238 break;
239 case AR5K_BWMODE_5MHZ:
240 clock = 40 / 4;
241 break;
242 default:
243 clock = 40;
244 break;
245 }
246 coef_scaled = ((5 * (clock << 24)) / 2) / channel->center_freq;
247
248 /* Get exponent
249 * ALGO: coef_exp = 14 - highest set bit position */
250 coef_exp = ilog2(coef_scaled);
251
252 /* Doesn't make sense if it's zero*/
253 if (!coef_scaled || !coef_exp)
254 return -EINVAL;
255
256 /* Note: we've shifted coef_scaled by 24 */
257 coef_exp = 14 - (coef_exp - 24);
258
259
260 /* Get mantissa (significant digits)
261 * ALGO: coef_mant = floor(coef_scaled* 2^coef_exp+0.5) */
262 coef_man = coef_scaled +
263 (1 << (24 - coef_exp - 1));
264
265 /* Calculate delta slope coefficient exponent
266 * and mantissa (remove scaling) and set them on hw */
267 ds_coef_man = coef_man >> (24 - coef_exp);
268 ds_coef_exp = coef_exp - 16;
269
270 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
271 AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man);
272 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
273 AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp);
274
275 return 0;
276 }
277
278 int ath5k_hw_phy_disable(struct ath5k_hw *ah)
279 {
280 /*Just a try M.F.*/
281 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
282
283 return 0;
284 }
285
286 /*
287 * Wait for synth to settle
288 */
289 static void ath5k_hw_wait_for_synth(struct ath5k_hw *ah,
290 struct ieee80211_channel *channel)
291 {
292 /*
293 * On 5211+ read activation -> rx delay
294 * and use it (100ns steps).
295 */
296 if (ah->ah_version != AR5K_AR5210) {
297 u32 delay;
298 delay = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) &
299 AR5K_PHY_RX_DELAY_M;
300 delay = (channel->hw_value & CHANNEL_CCK) ?
301 ((delay << 2) / 22) : (delay / 10);
302 if (ah->ah_bwmode == AR5K_BWMODE_10MHZ)
303 delay = delay << 1;
304 if (ah->ah_bwmode == AR5K_BWMODE_5MHZ)
305 delay = delay << 2;
306 /* XXX: /2 on turbo ? Let's be safe
307 * for now */
308 udelay(100 + delay);
309 } else {
310 mdelay(1);
311 }
312 }
313
314
315 /**********************\
316 * RF Gain optimization *
317 \**********************/
318
319 /*
320 * This code is used to optimize RF gain on different environments
321 * (temperature mostly) based on feedback from a power detector.
322 *
323 * It's only used on RF5111 and RF5112, later RF chips seem to have
324 * auto adjustment on hw -notice they have a much smaller BANK 7 and
325 * no gain optimization ladder-.
326 *
327 * For more infos check out this patent doc
328 * http://www.freepatentsonline.com/7400691.html
329 *
330 * This paper describes power drops as seen on the receiver due to
331 * probe packets
332 * http://www.cnri.dit.ie/publications/ICT08%20-%20Practical%20Issues
333 * %20of%20Power%20Control.pdf
334 *
335 * And this is the MadWiFi bug entry related to the above
336 * http://madwifi-project.org/ticket/1659
337 * with various measurements and diagrams
338 *
339 * TODO: Deal with power drops due to probes by setting an appropriate
340 * tx power on the probe packets ! Make this part of the calibration process.
341 */
342
343 /* Initialize ah_gain during attach */
344 int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah)
345 {
346 /* Initialize the gain optimization values */
347 switch (ah->ah_radio) {
348 case AR5K_RF5111:
349 ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default;
350 ah->ah_gain.g_low = 20;
351 ah->ah_gain.g_high = 35;
352 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
353 break;
354 case AR5K_RF5112:
355 ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default;
356 ah->ah_gain.g_low = 20;
357 ah->ah_gain.g_high = 85;
358 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
359 break;
360 default:
361 return -EINVAL;
362 }
363
364 return 0;
365 }
366
367 /* Schedule a gain probe check on the next transmitted packet.
368 * That means our next packet is going to be sent with lower
369 * tx power and a Peak to Average Power Detector (PAPD) will try
370 * to measure the gain.
371 *
372 * XXX: How about forcing a tx packet (bypassing PCU arbitrator etc)
373 * just after we enable the probe so that we don't mess with
374 * standard traffic ? Maybe it's time to use sw interrupts and
375 * a probe tasklet !!!
376 */
377 static void ath5k_hw_request_rfgain_probe(struct ath5k_hw *ah)
378 {
379
380 /* Skip if gain calibration is inactive or
381 * we already handle a probe request */
382 if (ah->ah_gain.g_state != AR5K_RFGAIN_ACTIVE)
383 return;
384
385 /* Send the packet with 2dB below max power as
386 * patent doc suggest */
387 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_ofdm - 4,
388 AR5K_PHY_PAPD_PROBE_TXPOWER) |
389 AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE);
390
391 ah->ah_gain.g_state = AR5K_RFGAIN_READ_REQUESTED;
392
393 }
394
395 /* Calculate gain_F measurement correction
396 * based on the current step for RF5112 rev. 2 */
397 static u32 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah)
398 {
399 u32 mix, step;
400 u32 *rf;
401 const struct ath5k_gain_opt *go;
402 const struct ath5k_gain_opt_step *g_step;
403 const struct ath5k_rf_reg *rf_regs;
404
405 /* Only RF5112 Rev. 2 supports it */
406 if ((ah->ah_radio != AR5K_RF5112) ||
407 (ah->ah_radio_5ghz_revision <= AR5K_SREV_RAD_5112A))
408 return 0;
409
410 go = &rfgain_opt_5112;
411 rf_regs = rf_regs_5112a;
412 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a);
413
414 g_step = &go->go_step[ah->ah_gain.g_step_idx];
415
416 if (ah->ah_rf_banks == NULL)
417 return 0;
418
419 rf = ah->ah_rf_banks;
420 ah->ah_gain.g_f_corr = 0;
421
422 /* No VGA (Variable Gain Amplifier) override, skip */
423 if (ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, false) != 1)
424 return 0;
425
426 /* Mix gain stepping */
427 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXGAIN_STEP, false);
428
429 /* Mix gain override */
430 mix = g_step->gos_param[0];
431
432 switch (mix) {
433 case 3:
434 ah->ah_gain.g_f_corr = step * 2;
435 break;
436 case 2:
437 ah->ah_gain.g_f_corr = (step - 5) * 2;
438 break;
439 case 1:
440 ah->ah_gain.g_f_corr = step;
441 break;
442 default:
443 ah->ah_gain.g_f_corr = 0;
444 break;
445 }
446
447 return ah->ah_gain.g_f_corr;
448 }
449
450 /* Check if current gain_F measurement is in the range of our
451 * power detector windows. If we get a measurement outside range
452 * we know it's not accurate (detectors can't measure anything outside
453 * their detection window) so we must ignore it */
454 static bool ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah)
455 {
456 const struct ath5k_rf_reg *rf_regs;
457 u32 step, mix_ovr, level[4];
458 u32 *rf;
459
460 if (ah->ah_rf_banks == NULL)
461 return false;
462
463 rf = ah->ah_rf_banks;
464
465 if (ah->ah_radio == AR5K_RF5111) {
466
467 rf_regs = rf_regs_5111;
468 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111);
469
470 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_RFGAIN_STEP,
471 false);
472
473 level[0] = 0;
474 level[1] = (step == 63) ? 50 : step + 4;
475 level[2] = (step != 63) ? 64 : level[0];
476 level[3] = level[2] + 50;
477
478 ah->ah_gain.g_high = level[3] -
479 (step == 63 ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5);
480 ah->ah_gain.g_low = level[0] +
481 (step == 63 ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0);
482 } else {
483
484 rf_regs = rf_regs_5112;
485 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112);
486
487 mix_ovr = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR,
488 false);
489
490 level[0] = level[2] = 0;
491
492 if (mix_ovr == 1) {
493 level[1] = level[3] = 83;
494 } else {
495 level[1] = level[3] = 107;
496 ah->ah_gain.g_high = 55;
497 }
498 }
499
500 return (ah->ah_gain.g_current >= level[0] &&
501 ah->ah_gain.g_current <= level[1]) ||
502 (ah->ah_gain.g_current >= level[2] &&
503 ah->ah_gain.g_current <= level[3]);
504 }
505
506 /* Perform gain_F adjustment by choosing the right set
507 * of parameters from RF gain optimization ladder */
508 static s8 ath5k_hw_rf_gainf_adjust(struct ath5k_hw *ah)
509 {
510 const struct ath5k_gain_opt *go;
511 const struct ath5k_gain_opt_step *g_step;
512 int ret = 0;
513
514 switch (ah->ah_radio) {
515 case AR5K_RF5111:
516 go = &rfgain_opt_5111;
517 break;
518 case AR5K_RF5112:
519 go = &rfgain_opt_5112;
520 break;
521 default:
522 return 0;
523 }
524
525 g_step = &go->go_step[ah->ah_gain.g_step_idx];
526
527 if (ah->ah_gain.g_current >= ah->ah_gain.g_high) {
528
529 /* Reached maximum */
530 if (ah->ah_gain.g_step_idx == 0)
531 return -1;
532
533 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
534 ah->ah_gain.g_target >= ah->ah_gain.g_high &&
535 ah->ah_gain.g_step_idx > 0;
536 g_step = &go->go_step[ah->ah_gain.g_step_idx])
537 ah->ah_gain.g_target -= 2 *
538 (go->go_step[--(ah->ah_gain.g_step_idx)].gos_gain -
539 g_step->gos_gain);
540
541 ret = 1;
542 goto done;
543 }
544
545 if (ah->ah_gain.g_current <= ah->ah_gain.g_low) {
546
547 /* Reached minimum */
548 if (ah->ah_gain.g_step_idx == (go->go_steps_count - 1))
549 return -2;
550
551 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
552 ah->ah_gain.g_target <= ah->ah_gain.g_low &&
553 ah->ah_gain.g_step_idx < go->go_steps_count - 1;
554 g_step = &go->go_step[ah->ah_gain.g_step_idx])
555 ah->ah_gain.g_target -= 2 *
556 (go->go_step[++ah->ah_gain.g_step_idx].gos_gain -
557 g_step->gos_gain);
558
559 ret = 2;
560 goto done;
561 }
562
563 done:
564 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
565 "ret %d, gain step %u, current gain %u, target gain %u\n",
566 ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current,
567 ah->ah_gain.g_target);
568
569 return ret;
570 }
571
572 /* Main callback for thermal RF gain calibration engine
573 * Check for a new gain reading and schedule an adjustment
574 * if needed.
575 *
576 * TODO: Use sw interrupt to schedule reset if gain_F needs
577 * adjustment */
578 enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah)
579 {
580 u32 data, type;
581 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
582
583 if (ah->ah_rf_banks == NULL ||
584 ah->ah_gain.g_state == AR5K_RFGAIN_INACTIVE)
585 return AR5K_RFGAIN_INACTIVE;
586
587 /* No check requested, either engine is inactive
588 * or an adjustment is already requested */
589 if (ah->ah_gain.g_state != AR5K_RFGAIN_READ_REQUESTED)
590 goto done;
591
592 /* Read the PAPD (Peak to Average Power Detector)
593 * register */
594 data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE);
595
596 /* No probe is scheduled, read gain_F measurement */
597 if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) {
598 ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S;
599 type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE);
600
601 /* If tx packet is CCK correct the gain_F measurement
602 * by cck ofdm gain delta */
603 if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK) {
604 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A)
605 ah->ah_gain.g_current +=
606 ee->ee_cck_ofdm_gain_delta;
607 else
608 ah->ah_gain.g_current +=
609 AR5K_GAIN_CCK_PROBE_CORR;
610 }
611
612 /* Further correct gain_F measurement for
613 * RF5112A radios */
614 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
615 ath5k_hw_rf_gainf_corr(ah);
616 ah->ah_gain.g_current =
617 ah->ah_gain.g_current >= ah->ah_gain.g_f_corr ?
618 (ah->ah_gain.g_current - ah->ah_gain.g_f_corr) :
619 0;
620 }
621
622 /* Check if measurement is ok and if we need
623 * to adjust gain, schedule a gain adjustment,
624 * else switch back to the active state */
625 if (ath5k_hw_rf_check_gainf_readback(ah) &&
626 AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) &&
627 ath5k_hw_rf_gainf_adjust(ah)) {
628 ah->ah_gain.g_state = AR5K_RFGAIN_NEED_CHANGE;
629 } else {
630 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
631 }
632 }
633
634 done:
635 return ah->ah_gain.g_state;
636 }
637
638 /* Write initial RF gain table to set the RF sensitivity
639 * this one works on all RF chips and has nothing to do
640 * with gain_F calibration */
641 static int ath5k_hw_rfgain_init(struct ath5k_hw *ah, enum ieee80211_band band)
642 {
643 const struct ath5k_ini_rfgain *ath5k_rfg;
644 unsigned int i, size, index;
645
646 switch (ah->ah_radio) {
647 case AR5K_RF5111:
648 ath5k_rfg = rfgain_5111;
649 size = ARRAY_SIZE(rfgain_5111);
650 break;
651 case AR5K_RF5112:
652 ath5k_rfg = rfgain_5112;
653 size = ARRAY_SIZE(rfgain_5112);
654 break;
655 case AR5K_RF2413:
656 ath5k_rfg = rfgain_2413;
657 size = ARRAY_SIZE(rfgain_2413);
658 break;
659 case AR5K_RF2316:
660 ath5k_rfg = rfgain_2316;
661 size = ARRAY_SIZE(rfgain_2316);
662 break;
663 case AR5K_RF5413:
664 ath5k_rfg = rfgain_5413;
665 size = ARRAY_SIZE(rfgain_5413);
666 break;
667 case AR5K_RF2317:
668 case AR5K_RF2425:
669 ath5k_rfg = rfgain_2425;
670 size = ARRAY_SIZE(rfgain_2425);
671 break;
672 default:
673 return -EINVAL;
674 }
675
676 index = (band == IEEE80211_BAND_2GHZ) ? 1 : 0;
677
678 for (i = 0; i < size; i++) {
679 AR5K_REG_WAIT(i);
680 ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[index],
681 (u32)ath5k_rfg[i].rfg_register);
682 }
683
684 return 0;
685 }
686
687
688
689 /********************\
690 * RF Registers setup *
691 \********************/
692
693 /*
694 * Setup RF registers by writing RF buffer on hw
695 */
696 static int ath5k_hw_rfregs_init(struct ath5k_hw *ah,
697 struct ieee80211_channel *channel, unsigned int mode)
698 {
699 const struct ath5k_rf_reg *rf_regs;
700 const struct ath5k_ini_rfbuffer *ini_rfb;
701 const struct ath5k_gain_opt *go = NULL;
702 const struct ath5k_gain_opt_step *g_step;
703 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
704 u8 ee_mode = 0;
705 u32 *rfb;
706 int i, obdb = -1, bank = -1;
707
708 switch (ah->ah_radio) {
709 case AR5K_RF5111:
710 rf_regs = rf_regs_5111;
711 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111);
712 ini_rfb = rfb_5111;
713 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5111);
714 go = &rfgain_opt_5111;
715 break;
716 case AR5K_RF5112:
717 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
718 rf_regs = rf_regs_5112a;
719 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a);
720 ini_rfb = rfb_5112a;
721 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112a);
722 } else {
723 rf_regs = rf_regs_5112;
724 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112);
725 ini_rfb = rfb_5112;
726 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112);
727 }
728 go = &rfgain_opt_5112;
729 break;
730 case AR5K_RF2413:
731 rf_regs = rf_regs_2413;
732 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2413);
733 ini_rfb = rfb_2413;
734 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2413);
735 break;
736 case AR5K_RF2316:
737 rf_regs = rf_regs_2316;
738 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2316);
739 ini_rfb = rfb_2316;
740 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2316);
741 break;
742 case AR5K_RF5413:
743 rf_regs = rf_regs_5413;
744 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5413);
745 ini_rfb = rfb_5413;
746 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5413);
747 break;
748 case AR5K_RF2317:
749 rf_regs = rf_regs_2425;
750 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425);
751 ini_rfb = rfb_2317;
752 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2317);
753 break;
754 case AR5K_RF2425:
755 rf_regs = rf_regs_2425;
756 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425);
757 if (ah->ah_mac_srev < AR5K_SREV_AR2417) {
758 ini_rfb = rfb_2425;
759 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2425);
760 } else {
761 ini_rfb = rfb_2417;
762 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2417);
763 }
764 break;
765 default:
766 return -EINVAL;
767 }
768
769 /* If it's the first time we set RF buffer, allocate
770 * ah->ah_rf_banks based on ah->ah_rf_banks_size
771 * we set above */
772 if (ah->ah_rf_banks == NULL) {
773 ah->ah_rf_banks = kmalloc(sizeof(u32) * ah->ah_rf_banks_size,
774 GFP_KERNEL);
775 if (ah->ah_rf_banks == NULL) {
776 ATH5K_ERR(ah->ah_sc, "out of memory\n");
777 return -ENOMEM;
778 }
779 }
780
781 /* Copy values to modify them */
782 rfb = ah->ah_rf_banks;
783
784 for (i = 0; i < ah->ah_rf_banks_size; i++) {
785 if (ini_rfb[i].rfb_bank >= AR5K_MAX_RF_BANKS) {
786 ATH5K_ERR(ah->ah_sc, "invalid bank\n");
787 return -EINVAL;
788 }
789
790 /* Bank changed, write down the offset */
791 if (bank != ini_rfb[i].rfb_bank) {
792 bank = ini_rfb[i].rfb_bank;
793 ah->ah_offset[bank] = i;
794 }
795
796 rfb[i] = ini_rfb[i].rfb_mode_data[mode];
797 }
798
799 /* Set Output and Driver bias current (OB/DB) */
800 if (channel->hw_value & CHANNEL_2GHZ) {
801
802 if (channel->hw_value & CHANNEL_CCK)
803 ee_mode = AR5K_EEPROM_MODE_11B;
804 else
805 ee_mode = AR5K_EEPROM_MODE_11G;
806
807 /* For RF511X/RF211X combination we
808 * use b_OB and b_DB parameters stored
809 * in eeprom on ee->ee_ob[ee_mode][0]
810 *
811 * For all other chips we use OB/DB for 2GHz
812 * stored in the b/g modal section just like
813 * 802.11a on ee->ee_ob[ee_mode][1] */
814 if ((ah->ah_radio == AR5K_RF5111) ||
815 (ah->ah_radio == AR5K_RF5112))
816 obdb = 0;
817 else
818 obdb = 1;
819
820 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb],
821 AR5K_RF_OB_2GHZ, true);
822
823 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb],
824 AR5K_RF_DB_2GHZ, true);
825
826 /* RF5111 always needs OB/DB for 5GHz, even if we use 2GHz */
827 } else if ((channel->hw_value & CHANNEL_5GHZ) ||
828 (ah->ah_radio == AR5K_RF5111)) {
829
830 /* For 11a, Turbo and XR we need to choose
831 * OB/DB based on frequency range */
832 ee_mode = AR5K_EEPROM_MODE_11A;
833 obdb = channel->center_freq >= 5725 ? 3 :
834 (channel->center_freq >= 5500 ? 2 :
835 (channel->center_freq >= 5260 ? 1 :
836 (channel->center_freq > 4000 ? 0 : -1)));
837
838 if (obdb < 0)
839 return -EINVAL;
840
841 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb],
842 AR5K_RF_OB_5GHZ, true);
843
844 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb],
845 AR5K_RF_DB_5GHZ, true);
846 }
847
848 g_step = &go->go_step[ah->ah_gain.g_step_idx];
849
850 /* Set turbo mode (N/A on RF5413) */
851 if ((ah->ah_bwmode == AR5K_BWMODE_40MHZ) &&
852 (ah->ah_radio != AR5K_RF5413))
853 ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_TURBO, false);
854
855 /* Bank Modifications (chip-specific) */
856 if (ah->ah_radio == AR5K_RF5111) {
857
858 /* Set gain_F settings according to current step */
859 if (channel->hw_value & CHANNEL_OFDM) {
860
861 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL,
862 AR5K_PHY_FRAME_CTL_TX_CLIP,
863 g_step->gos_param[0]);
864
865 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1],
866 AR5K_RF_PWD_90, true);
867
868 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2],
869 AR5K_RF_PWD_84, true);
870
871 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3],
872 AR5K_RF_RFGAIN_SEL, true);
873
874 /* We programmed gain_F parameters, switch back
875 * to active state */
876 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
877
878 }
879
880 /* Bank 6/7 setup */
881
882 ath5k_hw_rfb_op(ah, rf_regs, !ee->ee_xpd[ee_mode],
883 AR5K_RF_PWD_XPD, true);
884
885 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_x_gain[ee_mode],
886 AR5K_RF_XPD_GAIN, true);
887
888 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode],
889 AR5K_RF_GAIN_I, true);
890
891 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode],
892 AR5K_RF_PLO_SEL, true);
893
894 /* Tweak power detectors for half/quarter rate support */
895 if (ah->ah_bwmode == AR5K_BWMODE_5MHZ ||
896 ah->ah_bwmode == AR5K_BWMODE_10MHZ) {
897 u8 wait_i;
898
899 ath5k_hw_rfb_op(ah, rf_regs, 0x1f,
900 AR5K_RF_WAIT_S, true);
901
902 wait_i = (ah->ah_bwmode == AR5K_BWMODE_5MHZ) ?
903 0x1f : 0x10;
904
905 ath5k_hw_rfb_op(ah, rf_regs, wait_i,
906 AR5K_RF_WAIT_I, true);
907 ath5k_hw_rfb_op(ah, rf_regs, 3,
908 AR5K_RF_MAX_TIME, true);
909
910 }
911 }
912
913 if (ah->ah_radio == AR5K_RF5112) {
914
915 /* Set gain_F settings according to current step */
916 if (channel->hw_value & CHANNEL_OFDM) {
917
918 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[0],
919 AR5K_RF_MIXGAIN_OVR, true);
920
921 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1],
922 AR5K_RF_PWD_138, true);
923
924 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2],
925 AR5K_RF_PWD_137, true);
926
927 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3],
928 AR5K_RF_PWD_136, true);
929
930 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[4],
931 AR5K_RF_PWD_132, true);
932
933 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[5],
934 AR5K_RF_PWD_131, true);
935
936 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[6],
937 AR5K_RF_PWD_130, true);
938
939 /* We programmed gain_F parameters, switch back
940 * to active state */
941 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
942 }
943
944 /* Bank 6/7 setup */
945
946 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode],
947 AR5K_RF_XPD_SEL, true);
948
949 if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) {
950 /* Rev. 1 supports only one xpd */
951 ath5k_hw_rfb_op(ah, rf_regs,
952 ee->ee_x_gain[ee_mode],
953 AR5K_RF_XPD_GAIN, true);
954
955 } else {
956 u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode];
957 if (ee->ee_pd_gains[ee_mode] > 1) {
958 ath5k_hw_rfb_op(ah, rf_regs,
959 pdg_curve_to_idx[0],
960 AR5K_RF_PD_GAIN_LO, true);
961 ath5k_hw_rfb_op(ah, rf_regs,
962 pdg_curve_to_idx[1],
963 AR5K_RF_PD_GAIN_HI, true);
964 } else {
965 ath5k_hw_rfb_op(ah, rf_regs,
966 pdg_curve_to_idx[0],
967 AR5K_RF_PD_GAIN_LO, true);
968 ath5k_hw_rfb_op(ah, rf_regs,
969 pdg_curve_to_idx[0],
970 AR5K_RF_PD_GAIN_HI, true);
971 }
972
973 /* Lower synth voltage on Rev 2 */
974 if (ah->ah_radio == AR5K_RF5112 &&
975 (ah->ah_radio_5ghz_revision & AR5K_SREV_REV) > 0) {
976 ath5k_hw_rfb_op(ah, rf_regs, 2,
977 AR5K_RF_HIGH_VC_CP, true);
978
979 ath5k_hw_rfb_op(ah, rf_regs, 2,
980 AR5K_RF_MID_VC_CP, true);
981
982 ath5k_hw_rfb_op(ah, rf_regs, 2,
983 AR5K_RF_LOW_VC_CP, true);
984
985 ath5k_hw_rfb_op(ah, rf_regs, 2,
986 AR5K_RF_PUSH_UP, true);
987 }
988
989 /* Decrease power consumption on 5213+ BaseBand */
990 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
991 ath5k_hw_rfb_op(ah, rf_regs, 1,
992 AR5K_RF_PAD2GND, true);
993
994 ath5k_hw_rfb_op(ah, rf_regs, 1,
995 AR5K_RF_XB2_LVL, true);
996
997 ath5k_hw_rfb_op(ah, rf_regs, 1,
998 AR5K_RF_XB5_LVL, true);
999
1000 ath5k_hw_rfb_op(ah, rf_regs, 1,
1001 AR5K_RF_PWD_167, true);
1002
1003 ath5k_hw_rfb_op(ah, rf_regs, 1,
1004 AR5K_RF_PWD_166, true);
1005 }
1006 }
1007
1008 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode],
1009 AR5K_RF_GAIN_I, true);
1010
1011 /* Tweak power detector for half/quarter rates */
1012 if (ah->ah_bwmode == AR5K_BWMODE_5MHZ ||
1013 ah->ah_bwmode == AR5K_BWMODE_10MHZ) {
1014 u8 pd_delay;
1015
1016 pd_delay = (ah->ah_bwmode == AR5K_BWMODE_5MHZ) ?
1017 0xf : 0x8;
1018
1019 ath5k_hw_rfb_op(ah, rf_regs, pd_delay,
1020 AR5K_RF_PD_PERIOD_A, true);
1021 ath5k_hw_rfb_op(ah, rf_regs, 0xf,
1022 AR5K_RF_PD_DELAY_A, true);
1023
1024 }
1025 }
1026
1027 if (ah->ah_radio == AR5K_RF5413 &&
1028 channel->hw_value & CHANNEL_2GHZ) {
1029
1030 ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_DERBY_CHAN_SEL_MODE,
1031 true);
1032
1033 /* Set optimum value for early revisions (on pci-e chips) */
1034 if (ah->ah_mac_srev >= AR5K_SREV_AR5424 &&
1035 ah->ah_mac_srev < AR5K_SREV_AR5413)
1036 ath5k_hw_rfb_op(ah, rf_regs, ath5k_hw_bitswap(6, 3),
1037 AR5K_RF_PWD_ICLOBUF_2G, true);
1038
1039 }
1040
1041 /* Write RF banks on hw */
1042 for (i = 0; i < ah->ah_rf_banks_size; i++) {
1043 AR5K_REG_WAIT(i);
1044 ath5k_hw_reg_write(ah, rfb[i], ini_rfb[i].rfb_ctrl_register);
1045 }
1046
1047 return 0;
1048 }
1049
1050
1051 /**************************\
1052 PHY/RF channel functions
1053 \**************************/
1054
1055 /*
1056 * Conversion needed for RF5110
1057 */
1058 static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel)
1059 {
1060 u32 athchan;
1061
1062 /*
1063 * Convert IEEE channel/MHz to an internal channel value used
1064 * by the AR5210 chipset. This has not been verified with
1065 * newer chipsets like the AR5212A who have a completely
1066 * different RF/PHY part.
1067 */
1068 athchan = (ath5k_hw_bitswap(
1069 (ieee80211_frequency_to_channel(
1070 channel->center_freq) - 24) / 2, 5)
1071 << 1) | (1 << 6) | 0x1;
1072 return athchan;
1073 }
1074
1075 /*
1076 * Set channel on RF5110
1077 */
1078 static int ath5k_hw_rf5110_channel(struct ath5k_hw *ah,
1079 struct ieee80211_channel *channel)
1080 {
1081 u32 data;
1082
1083 /*
1084 * Set the channel and wait
1085 */
1086 data = ath5k_hw_rf5110_chan2athchan(channel);
1087 ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER);
1088 ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0);
1089 mdelay(1);
1090
1091 return 0;
1092 }
1093
1094 /*
1095 * Conversion needed for 5111
1096 */
1097 static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee,
1098 struct ath5k_athchan_2ghz *athchan)
1099 {
1100 int channel;
1101
1102 /* Cast this value to catch negative channel numbers (>= -19) */
1103 channel = (int)ieee;
1104
1105 /*
1106 * Map 2GHz IEEE channel to 5GHz Atheros channel
1107 */
1108 if (channel <= 13) {
1109 athchan->a2_athchan = 115 + channel;
1110 athchan->a2_flags = 0x46;
1111 } else if (channel == 14) {
1112 athchan->a2_athchan = 124;
1113 athchan->a2_flags = 0x44;
1114 } else if (channel >= 15 && channel <= 26) {
1115 athchan->a2_athchan = ((channel - 14) * 4) + 132;
1116 athchan->a2_flags = 0x46;
1117 } else
1118 return -EINVAL;
1119
1120 return 0;
1121 }
1122
1123 /*
1124 * Set channel on 5111
1125 */
1126 static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah,
1127 struct ieee80211_channel *channel)
1128 {
1129 struct ath5k_athchan_2ghz ath5k_channel_2ghz;
1130 unsigned int ath5k_channel =
1131 ieee80211_frequency_to_channel(channel->center_freq);
1132 u32 data0, data1, clock;
1133 int ret;
1134
1135 /*
1136 * Set the channel on the RF5111 radio
1137 */
1138 data0 = data1 = 0;
1139
1140 if (channel->hw_value & CHANNEL_2GHZ) {
1141 /* Map 2GHz channel to 5GHz Atheros channel ID */
1142 ret = ath5k_hw_rf5111_chan2athchan(
1143 ieee80211_frequency_to_channel(channel->center_freq),
1144 &ath5k_channel_2ghz);
1145 if (ret)
1146 return ret;
1147
1148 ath5k_channel = ath5k_channel_2ghz.a2_athchan;
1149 data0 = ((ath5k_hw_bitswap(ath5k_channel_2ghz.a2_flags, 8) & 0xff)
1150 << 5) | (1 << 4);
1151 }
1152
1153 if (ath5k_channel < 145 || !(ath5k_channel & 1)) {
1154 clock = 1;
1155 data1 = ((ath5k_hw_bitswap(ath5k_channel - 24, 8) & 0xff) << 2) |
1156 (clock << 1) | (1 << 10) | 1;
1157 } else {
1158 clock = 0;
1159 data1 = ((ath5k_hw_bitswap((ath5k_channel - 24) / 2, 8) & 0xff)
1160 << 2) | (clock << 1) | (1 << 10) | 1;
1161 }
1162
1163 ath5k_hw_reg_write(ah, (data1 & 0xff) | ((data0 & 0xff) << 8),
1164 AR5K_RF_BUFFER);
1165 ath5k_hw_reg_write(ah, ((data1 >> 8) & 0xff) | (data0 & 0xff00),
1166 AR5K_RF_BUFFER_CONTROL_3);
1167
1168 return 0;
1169 }
1170
1171 /*
1172 * Set channel on 5112 and newer
1173 */
1174 static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah,
1175 struct ieee80211_channel *channel)
1176 {
1177 u32 data, data0, data1, data2;
1178 u16 c;
1179
1180 data = data0 = data1 = data2 = 0;
1181 c = channel->center_freq;
1182
1183 if (c < 4800) {
1184 if (!((c - 2224) % 5)) {
1185 data0 = ((2 * (c - 704)) - 3040) / 10;
1186 data1 = 1;
1187 } else if (!((c - 2192) % 5)) {
1188 data0 = ((2 * (c - 672)) - 3040) / 10;
1189 data1 = 0;
1190 } else
1191 return -EINVAL;
1192
1193 data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8);
1194 } else if ((c % 5) != 2 || c > 5435) {
1195 if (!(c % 20) && c >= 5120) {
1196 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
1197 data2 = ath5k_hw_bitswap(3, 2);
1198 } else if (!(c % 10)) {
1199 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
1200 data2 = ath5k_hw_bitswap(2, 2);
1201 } else if (!(c % 5)) {
1202 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
1203 data2 = ath5k_hw_bitswap(1, 2);
1204 } else
1205 return -EINVAL;
1206 } else {
1207 data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8);
1208 data2 = ath5k_hw_bitswap(0, 2);
1209 }
1210
1211 data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001;
1212
1213 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
1214 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
1215
1216 return 0;
1217 }
1218
1219 /*
1220 * Set the channel on the RF2425
1221 */
1222 static int ath5k_hw_rf2425_channel(struct ath5k_hw *ah,
1223 struct ieee80211_channel *channel)
1224 {
1225 u32 data, data0, data2;
1226 u16 c;
1227
1228 data = data0 = data2 = 0;
1229 c = channel->center_freq;
1230
1231 if (c < 4800) {
1232 data0 = ath5k_hw_bitswap((c - 2272), 8);
1233 data2 = 0;
1234 /* ? 5GHz ? */
1235 } else if ((c % 5) != 2 || c > 5435) {
1236 if (!(c % 20) && c < 5120)
1237 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
1238 else if (!(c % 10))
1239 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
1240 else if (!(c % 5))
1241 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
1242 else
1243 return -EINVAL;
1244 data2 = ath5k_hw_bitswap(1, 2);
1245 } else {
1246 data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8);
1247 data2 = ath5k_hw_bitswap(0, 2);
1248 }
1249
1250 data = (data0 << 4) | data2 << 2 | 0x1001;
1251
1252 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
1253 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
1254
1255 return 0;
1256 }
1257
1258 /*
1259 * Set a channel on the radio chip
1260 */
1261 static int ath5k_hw_channel(struct ath5k_hw *ah,
1262 struct ieee80211_channel *channel)
1263 {
1264 int ret;
1265 /*
1266 * Check bounds supported by the PHY (we don't care about regulatory
1267 * restrictions at this point). Note: hw_value already has the band
1268 * (CHANNEL_2GHZ, or CHANNEL_5GHZ) so we inform ath5k_channel_ok()
1269 * of the band by that */
1270 if (!ath5k_channel_ok(ah, channel->center_freq, channel->hw_value)) {
1271 ATH5K_ERR(ah->ah_sc,
1272 "channel frequency (%u MHz) out of supported "
1273 "band range\n",
1274 channel->center_freq);
1275 return -EINVAL;
1276 }
1277
1278 /*
1279 * Set the channel and wait
1280 */
1281 switch (ah->ah_radio) {
1282 case AR5K_RF5110:
1283 ret = ath5k_hw_rf5110_channel(ah, channel);
1284 break;
1285 case AR5K_RF5111:
1286 ret = ath5k_hw_rf5111_channel(ah, channel);
1287 break;
1288 case AR5K_RF2317:
1289 case AR5K_RF2425:
1290 ret = ath5k_hw_rf2425_channel(ah, channel);
1291 break;
1292 default:
1293 ret = ath5k_hw_rf5112_channel(ah, channel);
1294 break;
1295 }
1296
1297 if (ret)
1298 return ret;
1299
1300 /* Set JAPAN setting for channel 14 */
1301 if (channel->center_freq == 2484) {
1302 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
1303 AR5K_PHY_CCKTXCTL_JAPAN);
1304 } else {
1305 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
1306 AR5K_PHY_CCKTXCTL_WORLD);
1307 }
1308
1309 ah->ah_current_channel = channel;
1310
1311 return 0;
1312 }
1313
1314 /*****************\
1315 PHY calibration
1316 \*****************/
1317
1318 static s32 ath5k_hw_read_measured_noise_floor(struct ath5k_hw *ah)
1319 {
1320 s32 val;
1321
1322 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF);
1323 return sign_extend32(AR5K_REG_MS(val, AR5K_PHY_NF_MINCCA_PWR), 8);
1324 }
1325
1326 void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah)
1327 {
1328 int i;
1329
1330 ah->ah_nfcal_hist.index = 0;
1331 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++)
1332 ah->ah_nfcal_hist.nfval[i] = AR5K_TUNE_CCA_MAX_GOOD_VALUE;
1333 }
1334
1335 static void ath5k_hw_update_nfcal_hist(struct ath5k_hw *ah, s16 noise_floor)
1336 {
1337 struct ath5k_nfcal_hist *hist = &ah->ah_nfcal_hist;
1338 hist->index = (hist->index + 1) & (ATH5K_NF_CAL_HIST_MAX - 1);
1339 hist->nfval[hist->index] = noise_floor;
1340 }
1341
1342 static s16 ath5k_hw_get_median_noise_floor(struct ath5k_hw *ah)
1343 {
1344 s16 sort[ATH5K_NF_CAL_HIST_MAX];
1345 s16 tmp;
1346 int i, j;
1347
1348 memcpy(sort, ah->ah_nfcal_hist.nfval, sizeof(sort));
1349 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX - 1; i++) {
1350 for (j = 1; j < ATH5K_NF_CAL_HIST_MAX - i; j++) {
1351 if (sort[j] > sort[j - 1]) {
1352 tmp = sort[j];
1353 sort[j] = sort[j - 1];
1354 sort[j - 1] = tmp;
1355 }
1356 }
1357 }
1358 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++) {
1359 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1360 "cal %d:%d\n", i, sort[i]);
1361 }
1362 return sort[(ATH5K_NF_CAL_HIST_MAX - 1) / 2];
1363 }
1364
1365 /*
1366 * When we tell the hardware to perform a noise floor calibration
1367 * by setting the AR5K_PHY_AGCCTL_NF bit, it will periodically
1368 * sample-and-hold the minimum noise level seen at the antennas.
1369 * This value is then stored in a ring buffer of recently measured
1370 * noise floor values so we have a moving window of the last few
1371 * samples.
1372 *
1373 * The median of the values in the history is then loaded into the
1374 * hardware for its own use for RSSI and CCA measurements.
1375 */
1376 void ath5k_hw_update_noise_floor(struct ath5k_hw *ah)
1377 {
1378 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1379 u32 val;
1380 s16 nf, threshold;
1381 u8 ee_mode;
1382
1383 /* keep last value if calibration hasn't completed */
1384 if (ath5k_hw_reg_read(ah, AR5K_PHY_AGCCTL) & AR5K_PHY_AGCCTL_NF) {
1385 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1386 "NF did not complete in calibration window\n");
1387
1388 return;
1389 }
1390
1391 ee_mode = ath5k_eeprom_mode_from_channel(ah->ah_current_channel);
1392
1393 /* completed NF calibration, test threshold */
1394 nf = ath5k_hw_read_measured_noise_floor(ah);
1395 threshold = ee->ee_noise_floor_thr[ee_mode];
1396
1397 if (nf > threshold) {
1398 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1399 "noise floor failure detected; "
1400 "read %d, threshold %d\n",
1401 nf, threshold);
1402
1403 nf = AR5K_TUNE_CCA_MAX_GOOD_VALUE;
1404 }
1405
1406 ath5k_hw_update_nfcal_hist(ah, nf);
1407 nf = ath5k_hw_get_median_noise_floor(ah);
1408
1409 /* load noise floor (in .5 dBm) so the hardware will use it */
1410 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF) & ~AR5K_PHY_NF_M;
1411 val |= (nf * 2) & AR5K_PHY_NF_M;
1412 ath5k_hw_reg_write(ah, val, AR5K_PHY_NF);
1413
1414 AR5K_REG_MASKED_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF,
1415 ~(AR5K_PHY_AGCCTL_NF_EN | AR5K_PHY_AGCCTL_NF_NOUPDATE));
1416
1417 ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF,
1418 0, false);
1419
1420 /*
1421 * Load a high max CCA Power value (-50 dBm in .5 dBm units)
1422 * so that we're not capped by the median we just loaded.
1423 * This will be used as the initial value for the next noise
1424 * floor calibration.
1425 */
1426 val = (val & ~AR5K_PHY_NF_M) | ((-50 * 2) & AR5K_PHY_NF_M);
1427 ath5k_hw_reg_write(ah, val, AR5K_PHY_NF);
1428 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1429 AR5K_PHY_AGCCTL_NF_EN |
1430 AR5K_PHY_AGCCTL_NF_NOUPDATE |
1431 AR5K_PHY_AGCCTL_NF);
1432
1433 ah->ah_noise_floor = nf;
1434
1435 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1436 "noise floor calibrated: %d\n", nf);
1437 }
1438
1439 /*
1440 * Perform a PHY calibration on RF5110
1441 * -Fix BPSK/QAM Constellation (I/Q correction)
1442 */
1443 static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah,
1444 struct ieee80211_channel *channel)
1445 {
1446 u32 phy_sig, phy_agc, phy_sat, beacon;
1447 int ret;
1448
1449 /*
1450 * Disable beacons and RX/TX queues, wait
1451 */
1452 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210,
1453 AR5K_DIAG_SW_DIS_TX_5210 | AR5K_DIAG_SW_DIS_RX_5210);
1454 beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210);
1455 ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210);
1456
1457 mdelay(2);
1458
1459 /*
1460 * Set the channel (with AGC turned off)
1461 */
1462 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1463 udelay(10);
1464 ret = ath5k_hw_channel(ah, channel);
1465
1466 /*
1467 * Activate PHY and wait
1468 */
1469 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
1470 mdelay(1);
1471
1472 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1473
1474 if (ret)
1475 return ret;
1476
1477 /*
1478 * Calibrate the radio chip
1479 */
1480
1481 /* Remember normal state */
1482 phy_sig = ath5k_hw_reg_read(ah, AR5K_PHY_SIG);
1483 phy_agc = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCOARSE);
1484 phy_sat = ath5k_hw_reg_read(ah, AR5K_PHY_ADCSAT);
1485
1486 /* Update radio registers */
1487 ath5k_hw_reg_write(ah, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) |
1488 AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG);
1489
1490 ath5k_hw_reg_write(ah, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI |
1491 AR5K_PHY_AGCCOARSE_LO)) |
1492 AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) |
1493 AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE);
1494
1495 ath5k_hw_reg_write(ah, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT |
1496 AR5K_PHY_ADCSAT_THR)) |
1497 AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) |
1498 AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT);
1499
1500 udelay(20);
1501
1502 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1503 udelay(10);
1504 ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG);
1505 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1506
1507 mdelay(1);
1508
1509 /*
1510 * Enable calibration and wait until completion
1511 */
1512 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL);
1513
1514 ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
1515 AR5K_PHY_AGCCTL_CAL, 0, false);
1516
1517 /* Reset to normal state */
1518 ath5k_hw_reg_write(ah, phy_sig, AR5K_PHY_SIG);
1519 ath5k_hw_reg_write(ah, phy_agc, AR5K_PHY_AGCCOARSE);
1520 ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT);
1521
1522 if (ret) {
1523 ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n",
1524 channel->center_freq);
1525 return ret;
1526 }
1527
1528 /*
1529 * Re-enable RX/TX and beacons
1530 */
1531 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210,
1532 AR5K_DIAG_SW_DIS_TX_5210 | AR5K_DIAG_SW_DIS_RX_5210);
1533 ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210);
1534
1535 return 0;
1536 }
1537
1538 /*
1539 * Perform I/Q calibration on RF5111/5112 and newer chips
1540 */
1541 static int
1542 ath5k_hw_rf511x_iq_calibrate(struct ath5k_hw *ah)
1543 {
1544 u32 i_pwr, q_pwr;
1545 s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd;
1546 int i;
1547
1548 if (!ah->ah_calibration ||
1549 ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN)
1550 return 0;
1551
1552 /* Calibration has finished, get the results and re-run */
1553 /* work around empty results which can apparently happen on 5212 */
1554 for (i = 0; i <= 10; i++) {
1555 iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR);
1556 i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I);
1557 q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q);
1558 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1559 "iq_corr:%x i_pwr:%x q_pwr:%x", iq_corr, i_pwr, q_pwr);
1560 if (i_pwr && q_pwr)
1561 break;
1562 }
1563
1564 i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7;
1565
1566 if (ah->ah_version == AR5K_AR5211)
1567 q_coffd = q_pwr >> 6;
1568 else
1569 q_coffd = q_pwr >> 7;
1570
1571 /* protect against divide by 0 and loss of sign bits */
1572 if (i_coffd == 0 || q_coffd < 2)
1573 return 0;
1574
1575 i_coff = (-iq_corr) / i_coffd;
1576 i_coff = clamp(i_coff, -32, 31); /* signed 6 bit */
1577
1578 if (ah->ah_version == AR5K_AR5211)
1579 q_coff = (i_pwr / q_coffd) - 64;
1580 else
1581 q_coff = (i_pwr / q_coffd) - 128;
1582 q_coff = clamp(q_coff, -16, 15); /* signed 5 bit */
1583
1584 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1585 "new I:%d Q:%d (i_coffd:%x q_coffd:%x)",
1586 i_coff, q_coff, i_coffd, q_coffd);
1587
1588 /* Commit new I/Q values (set enable bit last to match HAL sources) */
1589 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF, i_coff);
1590 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF, q_coff);
1591 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE);
1592
1593 /* Re-enable calibration -if we don't we'll commit
1594 * the same values again and again */
1595 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
1596 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
1597 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_RUN);
1598
1599 return 0;
1600 }
1601
1602 /*
1603 * Perform a PHY calibration
1604 */
1605 int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
1606 struct ieee80211_channel *channel)
1607 {
1608 int ret;
1609
1610 if (ah->ah_radio == AR5K_RF5110)
1611 return ath5k_hw_rf5110_calibrate(ah, channel);
1612
1613 ret = ath5k_hw_rf511x_iq_calibrate(ah);
1614
1615 if ((ah->ah_radio == AR5K_RF5111 || ah->ah_radio == AR5K_RF5112) &&
1616 (channel->hw_value & CHANNEL_OFDM))
1617 ath5k_hw_request_rfgain_probe(ah);
1618
1619 return ret;
1620 }
1621
1622
1623 /***************************\
1624 * Spur mitigation functions *
1625 \***************************/
1626
1627 static void
1628 ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah,
1629 struct ieee80211_channel *channel)
1630 {
1631 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1632 u32 mag_mask[4] = {0, 0, 0, 0};
1633 u32 pilot_mask[2] = {0, 0};
1634 /* Note: fbin values are scaled up by 2 */
1635 u16 spur_chan_fbin, chan_fbin, symbol_width, spur_detection_window;
1636 s32 spur_delta_phase, spur_freq_sigma_delta;
1637 s32 spur_offset, num_symbols_x16;
1638 u8 num_symbol_offsets, i, freq_band;
1639
1640 /* Convert current frequency to fbin value (the same way channels
1641 * are stored on EEPROM, check out ath5k_eeprom_bin2freq) and scale
1642 * up by 2 so we can compare it later */
1643 if (channel->hw_value & CHANNEL_2GHZ) {
1644 chan_fbin = (channel->center_freq - 2300) * 10;
1645 freq_band = AR5K_EEPROM_BAND_2GHZ;
1646 } else {
1647 chan_fbin = (channel->center_freq - 4900) * 10;
1648 freq_band = AR5K_EEPROM_BAND_5GHZ;
1649 }
1650
1651 /* Check if any spur_chan_fbin from EEPROM is
1652 * within our current channel's spur detection range */
1653 spur_chan_fbin = AR5K_EEPROM_NO_SPUR;
1654 spur_detection_window = AR5K_SPUR_CHAN_WIDTH;
1655 /* XXX: Half/Quarter channels ?*/
1656 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)
1657 spur_detection_window *= 2;
1658
1659 for (i = 0; i < AR5K_EEPROM_N_SPUR_CHANS; i++) {
1660 spur_chan_fbin = ee->ee_spur_chans[i][freq_band];
1661
1662 /* Note: mask cleans AR5K_EEPROM_NO_SPUR flag
1663 * so it's zero if we got nothing from EEPROM */
1664 if (spur_chan_fbin == AR5K_EEPROM_NO_SPUR) {
1665 spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK;
1666 break;
1667 }
1668
1669 if ((chan_fbin - spur_detection_window <=
1670 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK)) &&
1671 (chan_fbin + spur_detection_window >=
1672 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK))) {
1673 spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK;
1674 break;
1675 }
1676 }
1677
1678 /* We need to enable spur filter for this channel */
1679 if (spur_chan_fbin) {
1680 spur_offset = spur_chan_fbin - chan_fbin;
1681 /*
1682 * Calculate deltas:
1683 * spur_freq_sigma_delta -> spur_offset / sample_freq << 21
1684 * spur_delta_phase -> spur_offset / chip_freq << 11
1685 * Note: Both values have 100Hz resolution
1686 */
1687 switch (ah->ah_bwmode) {
1688 case AR5K_BWMODE_40MHZ:
1689 /* Both sample_freq and chip_freq are 80MHz */
1690 spur_delta_phase = (spur_offset << 16) / 25;
1691 spur_freq_sigma_delta = (spur_delta_phase >> 10);
1692 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz * 2;
1693 break;
1694 case AR5K_BWMODE_10MHZ:
1695 /* Both sample_freq and chip_freq are 20MHz (?) */
1696 spur_delta_phase = (spur_offset << 18) / 25;
1697 spur_freq_sigma_delta = (spur_delta_phase >> 10);
1698 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz / 2;
1699 case AR5K_BWMODE_5MHZ:
1700 /* Both sample_freq and chip_freq are 10MHz (?) */
1701 spur_delta_phase = (spur_offset << 19) / 25;
1702 spur_freq_sigma_delta = (spur_delta_phase >> 10);
1703 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz / 4;
1704 default:
1705 if (channel->hw_value == CHANNEL_A) {
1706 /* Both sample_freq and chip_freq are 40MHz */
1707 spur_delta_phase = (spur_offset << 17) / 25;
1708 spur_freq_sigma_delta =
1709 (spur_delta_phase >> 10);
1710 symbol_width =
1711 AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz;
1712 } else {
1713 /* sample_freq -> 40MHz chip_freq -> 44MHz
1714 * (for b compatibility) */
1715 spur_delta_phase = (spur_offset << 17) / 25;
1716 spur_freq_sigma_delta =
1717 (spur_offset << 8) / 55;
1718 symbol_width =
1719 AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz;
1720 }
1721 break;
1722 }
1723
1724 /* Calculate pilot and magnitude masks */
1725
1726 /* Scale up spur_offset by 1000 to switch to 100HZ resolution
1727 * and divide by symbol_width to find how many symbols we have
1728 * Note: number of symbols is scaled up by 16 */
1729 num_symbols_x16 = ((spur_offset * 1000) << 4) / symbol_width;
1730
1731 /* Spur is on a symbol if num_symbols_x16 % 16 is zero */
1732 if (!(num_symbols_x16 & 0xF))
1733 /* _X_ */
1734 num_symbol_offsets = 3;
1735 else
1736 /* _xx_ */
1737 num_symbol_offsets = 4;
1738
1739 for (i = 0; i < num_symbol_offsets; i++) {
1740
1741 /* Calculate pilot mask */
1742 s32 curr_sym_off =
1743 (num_symbols_x16 / 16) + i + 25;
1744
1745 /* Pilot magnitude mask seems to be a way to
1746 * declare the boundaries for our detection
1747 * window or something, it's 2 for the middle
1748 * value(s) where the symbol is expected to be
1749 * and 1 on the boundary values */
1750 u8 plt_mag_map =
1751 (i == 0 || i == (num_symbol_offsets - 1))
1752 ? 1 : 2;
1753
1754 if (curr_sym_off >= 0 && curr_sym_off <= 32) {
1755 if (curr_sym_off <= 25)
1756 pilot_mask[0] |= 1 << curr_sym_off;
1757 else if (curr_sym_off >= 27)
1758 pilot_mask[0] |= 1 << (curr_sym_off - 1);
1759 } else if (curr_sym_off >= 33 && curr_sym_off <= 52)
1760 pilot_mask[1] |= 1 << (curr_sym_off - 33);
1761
1762 /* Calculate magnitude mask (for viterbi decoder) */
1763 if (curr_sym_off >= -1 && curr_sym_off <= 14)
1764 mag_mask[0] |=
1765 plt_mag_map << (curr_sym_off + 1) * 2;
1766 else if (curr_sym_off >= 15 && curr_sym_off <= 30)
1767 mag_mask[1] |=
1768 plt_mag_map << (curr_sym_off - 15) * 2;
1769 else if (curr_sym_off >= 31 && curr_sym_off <= 46)
1770 mag_mask[2] |=
1771 plt_mag_map << (curr_sym_off - 31) * 2;
1772 else if (curr_sym_off >= 47 && curr_sym_off <= 53)
1773 mag_mask[3] |=
1774 plt_mag_map << (curr_sym_off - 47) * 2;
1775
1776 }
1777
1778 /* Write settings on hw to enable spur filter */
1779 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1780 AR5K_PHY_BIN_MASK_CTL_RATE, 0xff);
1781 /* XXX: Self correlator also ? */
1782 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
1783 AR5K_PHY_IQ_PILOT_MASK_EN |
1784 AR5K_PHY_IQ_CHAN_MASK_EN |
1785 AR5K_PHY_IQ_SPUR_FILT_EN);
1786
1787 /* Set delta phase and freq sigma delta */
1788 ath5k_hw_reg_write(ah,
1789 AR5K_REG_SM(spur_delta_phase,
1790 AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE) |
1791 AR5K_REG_SM(spur_freq_sigma_delta,
1792 AR5K_PHY_TIMING_11_SPUR_FREQ_SD) |
1793 AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC,
1794 AR5K_PHY_TIMING_11);
1795
1796 /* Write pilot masks */
1797 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_7);
1798 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8,
1799 AR5K_PHY_TIMING_8_PILOT_MASK_2,
1800 pilot_mask[1]);
1801
1802 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_9);
1803 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10,
1804 AR5K_PHY_TIMING_10_PILOT_MASK_2,
1805 pilot_mask[1]);
1806
1807 /* Write magnitude masks */
1808 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK_1);
1809 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK_2);
1810 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK_3);
1811 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1812 AR5K_PHY_BIN_MASK_CTL_MASK_4,
1813 mag_mask[3]);
1814
1815 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK2_1);
1816 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK2_2);
1817 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK2_3);
1818 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4,
1819 AR5K_PHY_BIN_MASK2_4_MASK_4,
1820 mag_mask[3]);
1821
1822 } else if (ath5k_hw_reg_read(ah, AR5K_PHY_IQ) &
1823 AR5K_PHY_IQ_SPUR_FILT_EN) {
1824 /* Clean up spur mitigation settings and disable filter */
1825 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1826 AR5K_PHY_BIN_MASK_CTL_RATE, 0);
1827 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_IQ,
1828 AR5K_PHY_IQ_PILOT_MASK_EN |
1829 AR5K_PHY_IQ_CHAN_MASK_EN |
1830 AR5K_PHY_IQ_SPUR_FILT_EN);
1831 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_11);
1832
1833 /* Clear pilot masks */
1834 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_7);
1835 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8,
1836 AR5K_PHY_TIMING_8_PILOT_MASK_2,
1837 0);
1838
1839 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_9);
1840 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10,
1841 AR5K_PHY_TIMING_10_PILOT_MASK_2,
1842 0);
1843
1844 /* Clear magnitude masks */
1845 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_1);
1846 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_2);
1847 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_3);
1848 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1849 AR5K_PHY_BIN_MASK_CTL_MASK_4,
1850 0);
1851
1852 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_1);
1853 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_2);
1854 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_3);
1855 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4,
1856 AR5K_PHY_BIN_MASK2_4_MASK_4,
1857 0);
1858 }
1859 }
1860
1861
1862 /*****************\
1863 * Antenna control *
1864 \*****************/
1865
1866 static void /*TODO:Boundary check*/
1867 ath5k_hw_set_def_antenna(struct ath5k_hw *ah, u8 ant)
1868 {
1869 if (ah->ah_version != AR5K_AR5210)
1870 ath5k_hw_reg_write(ah, ant & 0x7, AR5K_DEFAULT_ANTENNA);
1871 }
1872
1873 /*
1874 * Enable/disable fast rx antenna diversity
1875 */
1876 static void
1877 ath5k_hw_set_fast_div(struct ath5k_hw *ah, u8 ee_mode, bool enable)
1878 {
1879 switch (ee_mode) {
1880 case AR5K_EEPROM_MODE_11G:
1881 /* XXX: This is set to
1882 * disabled on initvals !!! */
1883 case AR5K_EEPROM_MODE_11A:
1884 if (enable)
1885 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGCCTL,
1886 AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
1887 else
1888 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1889 AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
1890 break;
1891 case AR5K_EEPROM_MODE_11B:
1892 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1893 AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
1894 break;
1895 default:
1896 return;
1897 }
1898
1899 if (enable) {
1900 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART,
1901 AR5K_PHY_RESTART_DIV_GC, 4);
1902
1903 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV,
1904 AR5K_PHY_FAST_ANT_DIV_EN);
1905 } else {
1906 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART,
1907 AR5K_PHY_RESTART_DIV_GC, 0);
1908
1909 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV,
1910 AR5K_PHY_FAST_ANT_DIV_EN);
1911 }
1912 }
1913
1914 void
1915 ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode)
1916 {
1917 u8 ant0, ant1;
1918
1919 /*
1920 * In case a fixed antenna was set as default
1921 * use the same switch table twice.
1922 */
1923 if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_A)
1924 ant0 = ant1 = AR5K_ANT_SWTABLE_A;
1925 else if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_B)
1926 ant0 = ant1 = AR5K_ANT_SWTABLE_B;
1927 else {
1928 ant0 = AR5K_ANT_SWTABLE_A;
1929 ant1 = AR5K_ANT_SWTABLE_B;
1930 }
1931
1932 /* Set antenna idle switch table */
1933 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_ANT_CTL,
1934 AR5K_PHY_ANT_CTL_SWTABLE_IDLE,
1935 (ah->ah_ant_ctl[ee_mode][AR5K_ANT_CTL] |
1936 AR5K_PHY_ANT_CTL_TXRX_EN));
1937
1938 /* Set antenna switch tables */
1939 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant0],
1940 AR5K_PHY_ANT_SWITCH_TABLE_0);
1941 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant1],
1942 AR5K_PHY_ANT_SWITCH_TABLE_1);
1943 }
1944
1945 /*
1946 * Set antenna operating mode
1947 */
1948 void
1949 ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode)
1950 {
1951 struct ieee80211_channel *channel = ah->ah_current_channel;
1952 bool use_def_for_tx, update_def_on_tx, use_def_for_rts, fast_div;
1953 bool use_def_for_sg;
1954 int ee_mode;
1955 u8 def_ant, tx_ant;
1956 u32 sta_id1 = 0;
1957
1958 /* if channel is not initialized yet we can't set the antennas
1959 * so just store the mode. it will be set on the next reset */
1960 if (channel == NULL) {
1961 ah->ah_ant_mode = ant_mode;
1962 return;
1963 }
1964
1965 def_ant = ah->ah_def_ant;
1966
1967 ee_mode = ath5k_eeprom_mode_from_channel(channel);
1968 if (ee_mode < 0) {
1969 ATH5K_ERR(ah->ah_sc,
1970 "invalid channel: %d\n", channel->center_freq);
1971 return;
1972 }
1973
1974 switch (ant_mode) {
1975 case AR5K_ANTMODE_DEFAULT:
1976 tx_ant = 0;
1977 use_def_for_tx = false;
1978 update_def_on_tx = false;
1979 use_def_for_rts = false;
1980 use_def_for_sg = false;
1981 fast_div = true;
1982 break;
1983 case AR5K_ANTMODE_FIXED_A:
1984 def_ant = 1;
1985 tx_ant = 1;
1986 use_def_for_tx = true;
1987 update_def_on_tx = false;
1988 use_def_for_rts = true;
1989 use_def_for_sg = true;
1990 fast_div = false;
1991 break;
1992 case AR5K_ANTMODE_FIXED_B:
1993 def_ant = 2;
1994 tx_ant = 2;
1995 use_def_for_tx = true;
1996 update_def_on_tx = false;
1997 use_def_for_rts = true;
1998 use_def_for_sg = true;
1999 fast_div = false;
2000 break;
2001 case AR5K_ANTMODE_SINGLE_AP:
2002 def_ant = 1; /* updated on tx */
2003 tx_ant = 0;
2004 use_def_for_tx = true;
2005 update_def_on_tx = true;
2006 use_def_for_rts = true;
2007 use_def_for_sg = true;
2008 fast_div = true;
2009 break;
2010 case AR5K_ANTMODE_SECTOR_AP:
2011 tx_ant = 1; /* variable */
2012 use_def_for_tx = false;
2013 update_def_on_tx = false;
2014 use_def_for_rts = true;
2015 use_def_for_sg = false;
2016 fast_div = false;
2017 break;
2018 case AR5K_ANTMODE_SECTOR_STA:
2019 tx_ant = 1; /* variable */
2020 use_def_for_tx = true;
2021 update_def_on_tx = false;
2022 use_def_for_rts = true;
2023 use_def_for_sg = false;
2024 fast_div = true;
2025 break;
2026 case AR5K_ANTMODE_DEBUG:
2027 def_ant = 1;
2028 tx_ant = 2;
2029 use_def_for_tx = false;
2030 update_def_on_tx = false;
2031 use_def_for_rts = false;
2032 use_def_for_sg = false;
2033 fast_div = false;
2034 break;
2035 default:
2036 return;
2037 }
2038
2039 ah->ah_tx_ant = tx_ant;
2040 ah->ah_ant_mode = ant_mode;
2041 ah->ah_def_ant = def_ant;
2042
2043 sta_id1 |= use_def_for_tx ? AR5K_STA_ID1_DEFAULT_ANTENNA : 0;
2044 sta_id1 |= update_def_on_tx ? AR5K_STA_ID1_DESC_ANTENNA : 0;
2045 sta_id1 |= use_def_for_rts ? AR5K_STA_ID1_RTS_DEF_ANTENNA : 0;
2046 sta_id1 |= use_def_for_sg ? AR5K_STA_ID1_SELFGEN_DEF_ANT : 0;
2047
2048 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_ANTENNA_SETTINGS);
2049
2050 if (sta_id1)
2051 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, sta_id1);
2052
2053 ath5k_hw_set_antenna_switch(ah, ee_mode);
2054 /* Note: set diversity before default antenna
2055 * because it won't work correctly */
2056 ath5k_hw_set_fast_div(ah, ee_mode, fast_div);
2057 ath5k_hw_set_def_antenna(ah, def_ant);
2058 }
2059
2060
2061 /****************\
2062 * TX power setup *
2063 \****************/
2064
2065 /*
2066 * Helper functions
2067 */
2068
2069 /*
2070 * Do linear interpolation between two given (x, y) points
2071 */
2072 static s16
2073 ath5k_get_interpolated_value(s16 target, s16 x_left, s16 x_right,
2074 s16 y_left, s16 y_right)
2075 {
2076 s16 ratio, result;
2077
2078 /* Avoid divide by zero and skip interpolation
2079 * if we have the same point */
2080 if ((x_left == x_right) || (y_left == y_right))
2081 return y_left;
2082
2083 /*
2084 * Since we use ints and not fps, we need to scale up in
2085 * order to get a sane ratio value (or else we 'll eg. get
2086 * always 1 instead of 1.25, 1.75 etc). We scale up by 100
2087 * to have some accuracy both for 0.5 and 0.25 steps.
2088 */
2089 ratio = ((100 * y_right - 100 * y_left) / (x_right - x_left));
2090
2091 /* Now scale down to be in range */
2092 result = y_left + (ratio * (target - x_left) / 100);
2093
2094 return result;
2095 }
2096
2097 /*
2098 * Find vertical boundary (min pwr) for the linear PCDAC curve.
2099 *
2100 * Since we have the top of the curve and we draw the line below
2101 * until we reach 1 (1 pcdac step) we need to know which point
2102 * (x value) that is so that we don't go below y axis and have negative
2103 * pcdac values when creating the curve, or fill the table with zeroes.
2104 */
2105 static s16
2106 ath5k_get_linear_pcdac_min(const u8 *stepL, const u8 *stepR,
2107 const s16 *pwrL, const s16 *pwrR)
2108 {
2109 s8 tmp;
2110 s16 min_pwrL, min_pwrR;
2111 s16 pwr_i;
2112
2113 /* Some vendors write the same pcdac value twice !!! */
2114 if (stepL[0] == stepL[1] || stepR[0] == stepR[1])
2115 return max(pwrL[0], pwrR[0]);
2116
2117 if (pwrL[0] == pwrL[1])
2118 min_pwrL = pwrL[0];
2119 else {
2120 pwr_i = pwrL[0];
2121 do {
2122 pwr_i--;
2123 tmp = (s8) ath5k_get_interpolated_value(pwr_i,
2124 pwrL[0], pwrL[1],
2125 stepL[0], stepL[1]);
2126 } while (tmp > 1);
2127
2128 min_pwrL = pwr_i;
2129 }
2130
2131 if (pwrR[0] == pwrR[1])
2132 min_pwrR = pwrR[0];
2133 else {
2134 pwr_i = pwrR[0];
2135 do {
2136 pwr_i--;
2137 tmp = (s8) ath5k_get_interpolated_value(pwr_i,
2138 pwrR[0], pwrR[1],
2139 stepR[0], stepR[1]);
2140 } while (tmp > 1);
2141
2142 min_pwrR = pwr_i;
2143 }
2144
2145 /* Keep the right boundary so that it works for both curves */
2146 return max(min_pwrL, min_pwrR);
2147 }
2148
2149 /*
2150 * Interpolate (pwr,vpd) points to create a Power to PDADC or a
2151 * Power to PCDAC curve.
2152 *
2153 * Each curve has power on x axis (in 0.5dB units) and PCDAC/PDADC
2154 * steps (offsets) on y axis. Power can go up to 31.5dB and max
2155 * PCDAC/PDADC step for each curve is 64 but we can write more than
2156 * one curves on hw so we can go up to 128 (which is the max step we
2157 * can write on the final table).
2158 *
2159 * We write y values (PCDAC/PDADC steps) on hw.
2160 */
2161 static void
2162 ath5k_create_power_curve(s16 pmin, s16 pmax,
2163 const s16 *pwr, const u8 *vpd,
2164 u8 num_points,
2165 u8 *vpd_table, u8 type)
2166 {
2167 u8 idx[2] = { 0, 1 };
2168 s16 pwr_i = 2 * pmin;
2169 int i;
2170
2171 if (num_points < 2)
2172 return;
2173
2174 /* We want the whole line, so adjust boundaries
2175 * to cover the entire power range. Note that
2176 * power values are already 0.25dB so no need
2177 * to multiply pwr_i by 2 */
2178 if (type == AR5K_PWRTABLE_LINEAR_PCDAC) {
2179 pwr_i = pmin;
2180 pmin = 0;
2181 pmax = 63;
2182 }
2183
2184 /* Find surrounding turning points (TPs)
2185 * and interpolate between them */
2186 for (i = 0; (i <= (u16) (pmax - pmin)) &&
2187 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) {
2188
2189 /* We passed the right TP, move to the next set of TPs
2190 * if we pass the last TP, extrapolate above using the last
2191 * two TPs for ratio */
2192 if ((pwr_i > pwr[idx[1]]) && (idx[1] < num_points - 1)) {
2193 idx[0]++;
2194 idx[1]++;
2195 }
2196
2197 vpd_table[i] = (u8) ath5k_get_interpolated_value(pwr_i,
2198 pwr[idx[0]], pwr[idx[1]],
2199 vpd[idx[0]], vpd[idx[1]]);
2200
2201 /* Increase by 0.5dB
2202 * (0.25 dB units) */
2203 pwr_i += 2;
2204 }
2205 }
2206
2207 /*
2208 * Get the surrounding per-channel power calibration piers
2209 * for a given frequency so that we can interpolate between
2210 * them and come up with an appropriate dataset for our current
2211 * channel.
2212 */
2213 static void
2214 ath5k_get_chan_pcal_surrounding_piers(struct ath5k_hw *ah,
2215 struct ieee80211_channel *channel,
2216 struct ath5k_chan_pcal_info **pcinfo_l,
2217 struct ath5k_chan_pcal_info **pcinfo_r)
2218 {
2219 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2220 struct ath5k_chan_pcal_info *pcinfo;
2221 u8 idx_l, idx_r;
2222 u8 mode, max, i;
2223 u32 target = channel->center_freq;
2224
2225 idx_l = 0;
2226 idx_r = 0;
2227
2228 if (!(channel->hw_value & CHANNEL_OFDM)) {
2229 pcinfo = ee->ee_pwr_cal_b;
2230 mode = AR5K_EEPROM_MODE_11B;
2231 } else if (channel->hw_value & CHANNEL_2GHZ) {
2232 pcinfo = ee->ee_pwr_cal_g;
2233 mode = AR5K_EEPROM_MODE_11G;
2234 } else {
2235 pcinfo = ee->ee_pwr_cal_a;
2236 mode = AR5K_EEPROM_MODE_11A;
2237 }
2238 max = ee->ee_n_piers[mode] - 1;
2239
2240 /* Frequency is below our calibrated
2241 * range. Use the lowest power curve
2242 * we have */
2243 if (target < pcinfo[0].freq) {
2244 idx_l = idx_r = 0;
2245 goto done;
2246 }
2247
2248 /* Frequency is above our calibrated
2249 * range. Use the highest power curve
2250 * we have */
2251 if (target > pcinfo[max].freq) {
2252 idx_l = idx_r = max;
2253 goto done;
2254 }
2255
2256 /* Frequency is inside our calibrated
2257 * channel range. Pick the surrounding
2258 * calibration piers so that we can
2259 * interpolate */
2260 for (i = 0; i <= max; i++) {
2261
2262 /* Frequency matches one of our calibration
2263 * piers, no need to interpolate, just use
2264 * that calibration pier */
2265 if (pcinfo[i].freq == target) {
2266 idx_l = idx_r = i;
2267 goto done;
2268 }
2269
2270 /* We found a calibration pier that's above
2271 * frequency, use this pier and the previous
2272 * one to interpolate */
2273 if (target < pcinfo[i].freq) {
2274 idx_r = i;
2275 idx_l = idx_r - 1;
2276 goto done;
2277 }
2278 }
2279
2280 done:
2281 *pcinfo_l = &pcinfo[idx_l];
2282 *pcinfo_r = &pcinfo[idx_r];
2283 }
2284
2285 /*
2286 * Get the surrounding per-rate power calibration data
2287 * for a given frequency and interpolate between power
2288 * values to set max target power supported by hw for
2289 * each rate.
2290 */
2291 static void
2292 ath5k_get_rate_pcal_data(struct ath5k_hw *ah,
2293 struct ieee80211_channel *channel,
2294 struct ath5k_rate_pcal_info *rates)
2295 {
2296 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2297 struct ath5k_rate_pcal_info *rpinfo;
2298 u8 idx_l, idx_r;
2299 u8 mode, max, i;
2300 u32 target = channel->center_freq;
2301
2302 idx_l = 0;
2303 idx_r = 0;
2304
2305 if (!(channel->hw_value & CHANNEL_OFDM)) {
2306 rpinfo = ee->ee_rate_tpwr_b;
2307 mode = AR5K_EEPROM_MODE_11B;
2308 } else if (channel->hw_value & CHANNEL_2GHZ) {
2309 rpinfo = ee->ee_rate_tpwr_g;
2310 mode = AR5K_EEPROM_MODE_11G;
2311 } else {
2312 rpinfo = ee->ee_rate_tpwr_a;
2313 mode = AR5K_EEPROM_MODE_11A;
2314 }
2315 max = ee->ee_rate_target_pwr_num[mode] - 1;
2316
2317 /* Get the surrounding calibration
2318 * piers - same as above */
2319 if (target < rpinfo[0].freq) {
2320 idx_l = idx_r = 0;
2321 goto done;
2322 }
2323
2324 if (target > rpinfo[max].freq) {
2325 idx_l = idx_r = max;
2326 goto done;
2327 }
2328
2329 for (i = 0; i <= max; i++) {
2330
2331 if (rpinfo[i].freq == target) {
2332 idx_l = idx_r = i;
2333 goto done;
2334 }
2335
2336 if (target < rpinfo[i].freq) {
2337 idx_r = i;
2338 idx_l = idx_r - 1;
2339 goto done;
2340 }
2341 }
2342
2343 done:
2344 /* Now interpolate power value, based on the frequency */
2345 rates->freq = target;
2346
2347 rates->target_power_6to24 =
2348 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2349 rpinfo[idx_r].freq,
2350 rpinfo[idx_l].target_power_6to24,
2351 rpinfo[idx_r].target_power_6to24);
2352
2353 rates->target_power_36 =
2354 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2355 rpinfo[idx_r].freq,
2356 rpinfo[idx_l].target_power_36,
2357 rpinfo[idx_r].target_power_36);
2358
2359 rates->target_power_48 =
2360 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2361 rpinfo[idx_r].freq,
2362 rpinfo[idx_l].target_power_48,
2363 rpinfo[idx_r].target_power_48);
2364
2365 rates->target_power_54 =
2366 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2367 rpinfo[idx_r].freq,
2368 rpinfo[idx_l].target_power_54,
2369 rpinfo[idx_r].target_power_54);
2370 }
2371
2372 /*
2373 * Get the max edge power for this channel if
2374 * we have such data from EEPROM's Conformance Test
2375 * Limits (CTL), and limit max power if needed.
2376 */
2377 static void
2378 ath5k_get_max_ctl_power(struct ath5k_hw *ah,
2379 struct ieee80211_channel *channel)
2380 {
2381 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
2382 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2383 struct ath5k_edge_power *rep = ee->ee_ctl_pwr;
2384 u8 *ctl_val = ee->ee_ctl;
2385 s16 max_chan_pwr = ah->ah_txpower.txp_max_pwr / 4;
2386 s16 edge_pwr = 0;
2387 u8 rep_idx;
2388 u8 i, ctl_mode;
2389 u8 ctl_idx = 0xFF;
2390 u32 target = channel->center_freq;
2391
2392 ctl_mode = ath_regd_get_band_ctl(regulatory, channel->band);
2393
2394 switch (channel->hw_value & CHANNEL_MODES) {
2395 case CHANNEL_A:
2396 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)
2397 ctl_mode |= AR5K_CTL_TURBO;
2398 else
2399 ctl_mode |= AR5K_CTL_11A;
2400 break;
2401 case CHANNEL_G:
2402 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)
2403 ctl_mode |= AR5K_CTL_TURBOG;
2404 else
2405 ctl_mode |= AR5K_CTL_11G;
2406 break;
2407 case CHANNEL_B:
2408 ctl_mode |= AR5K_CTL_11B;
2409 break;
2410 case CHANNEL_XR:
2411 /* Fall through */
2412 default:
2413 return;
2414 }
2415
2416 for (i = 0; i < ee->ee_ctls; i++) {
2417 if (ctl_val[i] == ctl_mode) {
2418 ctl_idx = i;
2419 break;
2420 }
2421 }
2422
2423 /* If we have a CTL dataset available grab it and find the
2424 * edge power for our frequency */
2425 if (ctl_idx == 0xFF)
2426 return;
2427
2428 /* Edge powers are sorted by frequency from lower
2429 * to higher. Each CTL corresponds to 8 edge power
2430 * measurements. */
2431 rep_idx = ctl_idx * AR5K_EEPROM_N_EDGES;
2432
2433 /* Don't do boundaries check because we
2434 * might have more that one bands defined
2435 * for this mode */
2436
2437 /* Get the edge power that's closer to our
2438 * frequency */
2439 for (i = 0; i < AR5K_EEPROM_N_EDGES; i++) {
2440 rep_idx += i;
2441 if (target <= rep[rep_idx].freq)
2442 edge_pwr = (s16) rep[rep_idx].edge;
2443 }
2444
2445 if (edge_pwr)
2446 ah->ah_txpower.txp_max_pwr = 4 * min(edge_pwr, max_chan_pwr);
2447 }
2448
2449
2450 /*
2451 * Power to PCDAC table functions
2452 */
2453
2454 /*
2455 * Fill Power to PCDAC table on RF5111
2456 *
2457 * No further processing is needed for RF5111, the only thing we have to
2458 * do is fill the values below and above calibration range since eeprom data
2459 * may not cover the entire PCDAC table.
2460 */
2461 static void
2462 ath5k_fill_pwr_to_pcdac_table(struct ath5k_hw *ah, s16* table_min,
2463 s16 *table_max)
2464 {
2465 u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
2466 u8 *pcdac_tmp = ah->ah_txpower.tmpL[0];
2467 u8 pcdac_0, pcdac_n, pcdac_i, pwr_idx, i;
2468 s16 min_pwr, max_pwr;
2469
2470 /* Get table boundaries */
2471 min_pwr = table_min[0];
2472 pcdac_0 = pcdac_tmp[0];
2473
2474 max_pwr = table_max[0];
2475 pcdac_n = pcdac_tmp[table_max[0] - table_min[0]];
2476
2477 /* Extrapolate below minimum using pcdac_0 */
2478 pcdac_i = 0;
2479 for (i = 0; i < min_pwr; i++)
2480 pcdac_out[pcdac_i++] = pcdac_0;
2481
2482 /* Copy values from pcdac_tmp */
2483 pwr_idx = min_pwr;
2484 for (i = 0; pwr_idx <= max_pwr &&
2485 pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE; i++) {
2486 pcdac_out[pcdac_i++] = pcdac_tmp[i];
2487 pwr_idx++;
2488 }
2489
2490 /* Extrapolate above maximum */
2491 while (pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE)
2492 pcdac_out[pcdac_i++] = pcdac_n;
2493
2494 }
2495
2496 /*
2497 * Combine available XPD Curves and fill Linear Power to PCDAC table
2498 * on RF5112
2499 *
2500 * RFX112 can have up to 2 curves (one for low txpower range and one for
2501 * higher txpower range). We need to put them both on pcdac_out and place
2502 * them in the correct location. In case we only have one curve available
2503 * just fit it on pcdac_out (it's supposed to cover the entire range of
2504 * available pwr levels since it's always the higher power curve). Extrapolate
2505 * below and above final table if needed.
2506 */
2507 static void
2508 ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min,
2509 s16 *table_max, u8 pdcurves)
2510 {
2511 u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
2512 u8 *pcdac_low_pwr;
2513 u8 *pcdac_high_pwr;
2514 u8 *pcdac_tmp;
2515 u8 pwr;
2516 s16 max_pwr_idx;
2517 s16 min_pwr_idx;
2518 s16 mid_pwr_idx = 0;
2519 /* Edge flag turns on the 7nth bit on the PCDAC
2520 * to declare the higher power curve (force values
2521 * to be greater than 64). If we only have one curve
2522 * we don't need to set this, if we have 2 curves and
2523 * fill the table backwards this can also be used to
2524 * switch from higher power curve to lower power curve */
2525 u8 edge_flag;
2526 int i;
2527
2528 /* When we have only one curve available
2529 * that's the higher power curve. If we have
2530 * two curves the first is the high power curve
2531 * and the next is the low power curve. */
2532 if (pdcurves > 1) {
2533 pcdac_low_pwr = ah->ah_txpower.tmpL[1];
2534 pcdac_high_pwr = ah->ah_txpower.tmpL[0];
2535 mid_pwr_idx = table_max[1] - table_min[1] - 1;
2536 max_pwr_idx = (table_max[0] - table_min[0]) / 2;
2537
2538 /* If table size goes beyond 31.5dB, keep the
2539 * upper 31.5dB range when setting tx power.
2540 * Note: 126 = 31.5 dB in quarter dB steps */
2541 if (table_max[0] - table_min[1] > 126)
2542 min_pwr_idx = table_max[0] - 126;
2543 else
2544 min_pwr_idx = table_min[1];
2545
2546 /* Since we fill table backwards
2547 * start from high power curve */
2548 pcdac_tmp = pcdac_high_pwr;
2549
2550 edge_flag = 0x40;
2551 } else {
2552 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; /* Zeroed */
2553 pcdac_high_pwr = ah->ah_txpower.tmpL[0];
2554 min_pwr_idx = table_min[0];
2555 max_pwr_idx = (table_max[0] - table_min[0]) / 2;
2556 pcdac_tmp = pcdac_high_pwr;
2557 edge_flag = 0;
2558 }
2559
2560 /* This is used when setting tx power*/
2561 ah->ah_txpower.txp_min_idx = min_pwr_idx / 2;
2562
2563 /* Fill Power to PCDAC table backwards */
2564 pwr = max_pwr_idx;
2565 for (i = 63; i >= 0; i--) {
2566 /* Entering lower power range, reset
2567 * edge flag and set pcdac_tmp to lower
2568 * power curve.*/
2569 if (edge_flag == 0x40 &&
2570 (2 * pwr <= (table_max[1] - table_min[0]) || pwr == 0)) {
2571 edge_flag = 0x00;
2572 pcdac_tmp = pcdac_low_pwr;
2573 pwr = mid_pwr_idx / 2;
2574 }
2575
2576 /* Don't go below 1, extrapolate below if we have
2577 * already switched to the lower power curve -or
2578 * we only have one curve and edge_flag is zero
2579 * anyway */
2580 if (pcdac_tmp[pwr] < 1 && (edge_flag == 0x00)) {
2581 while (i >= 0) {
2582 pcdac_out[i] = pcdac_out[i + 1];
2583 i--;
2584 }
2585 break;
2586 }
2587
2588 pcdac_out[i] = pcdac_tmp[pwr] | edge_flag;
2589
2590 /* Extrapolate above if pcdac is greater than
2591 * 126 -this can happen because we OR pcdac_out
2592 * value with edge_flag on high power curve */
2593 if (pcdac_out[i] > 126)
2594 pcdac_out[i] = 126;
2595
2596 /* Decrease by a 0.5dB step */
2597 pwr--;
2598 }
2599 }
2600
2601 /* Write PCDAC values on hw */
2602 static void
2603 ath5k_write_pcdac_table(struct ath5k_hw *ah)
2604 {
2605 u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
2606 int i;
2607
2608 /*
2609 * Write TX power values
2610 */
2611 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
2612 ath5k_hw_reg_write(ah,
2613 (((pcdac_out[2 * i + 0] << 8 | 0xff) & 0xffff) << 0) |
2614 (((pcdac_out[2 * i + 1] << 8 | 0xff) & 0xffff) << 16),
2615 AR5K_PHY_PCDAC_TXPOWER(i));
2616 }
2617 }
2618
2619
2620 /*
2621 * Power to PDADC table functions
2622 */
2623
2624 /*
2625 * Set the gain boundaries and create final Power to PDADC table
2626 *
2627 * We can have up to 4 pd curves, we need to do a similar process
2628 * as we do for RF5112. This time we don't have an edge_flag but we
2629 * set the gain boundaries on a separate register.
2630 */
2631 static void
2632 ath5k_combine_pwr_to_pdadc_curves(struct ath5k_hw *ah,
2633 s16 *pwr_min, s16 *pwr_max, u8 pdcurves)
2634 {
2635 u8 gain_boundaries[AR5K_EEPROM_N_PD_GAINS];
2636 u8 *pdadc_out = ah->ah_txpower.txp_pd_table;
2637 u8 *pdadc_tmp;
2638 s16 pdadc_0;
2639 u8 pdadc_i, pdadc_n, pwr_step, pdg, max_idx, table_size;
2640 u8 pd_gain_overlap;
2641
2642 /* Note: Register value is initialized on initvals
2643 * there is no feedback from hw.
2644 * XXX: What about pd_gain_overlap from EEPROM ? */
2645 pd_gain_overlap = (u8) ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG5) &
2646 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP;
2647
2648 /* Create final PDADC table */
2649 for (pdg = 0, pdadc_i = 0; pdg < pdcurves; pdg++) {
2650 pdadc_tmp = ah->ah_txpower.tmpL[pdg];
2651
2652 if (pdg == pdcurves - 1)
2653 /* 2 dB boundary stretch for last
2654 * (higher power) curve */
2655 gain_boundaries[pdg] = pwr_max[pdg] + 4;
2656 else
2657 /* Set gain boundary in the middle
2658 * between this curve and the next one */
2659 gain_boundaries[pdg] =
2660 (pwr_max[pdg] + pwr_min[pdg + 1]) / 2;
2661
2662 /* Sanity check in case our 2 db stretch got out of
2663 * range. */
2664 if (gain_boundaries[pdg] > AR5K_TUNE_MAX_TXPOWER)
2665 gain_boundaries[pdg] = AR5K_TUNE_MAX_TXPOWER;
2666
2667 /* For the first curve (lower power)
2668 * start from 0 dB */
2669 if (pdg == 0)
2670 pdadc_0 = 0;
2671 else
2672 /* For the other curves use the gain overlap */
2673 pdadc_0 = (gain_boundaries[pdg - 1] - pwr_min[pdg]) -
2674 pd_gain_overlap;
2675
2676 /* Force each power step to be at least 0.5 dB */
2677 if ((pdadc_tmp[1] - pdadc_tmp[0]) > 1)
2678 pwr_step = pdadc_tmp[1] - pdadc_tmp[0];
2679 else
2680 pwr_step = 1;
2681
2682 /* If pdadc_0 is negative, we need to extrapolate
2683 * below this pdgain by a number of pwr_steps */
2684 while ((pdadc_0 < 0) && (pdadc_i < 128)) {
2685 s16 tmp = pdadc_tmp[0] + pdadc_0 * pwr_step;
2686 pdadc_out[pdadc_i++] = (tmp < 0) ? 0 : (u8) tmp;
2687 pdadc_0++;
2688 }
2689
2690 /* Set last pwr level, using gain boundaries */
2691 pdadc_n = gain_boundaries[pdg] + pd_gain_overlap - pwr_min[pdg];
2692 /* Limit it to be inside pwr range */
2693 table_size = pwr_max[pdg] - pwr_min[pdg];
2694 max_idx = (pdadc_n < table_size) ? pdadc_n : table_size;
2695
2696 /* Fill pdadc_out table */
2697 while (pdadc_0 < max_idx && pdadc_i < 128)
2698 pdadc_out[pdadc_i++] = pdadc_tmp[pdadc_0++];
2699
2700 /* Need to extrapolate above this pdgain? */
2701 if (pdadc_n <= max_idx)
2702 continue;
2703
2704 /* Force each power step to be at least 0.5 dB */
2705 if ((pdadc_tmp[table_size - 1] - pdadc_tmp[table_size - 2]) > 1)
2706 pwr_step = pdadc_tmp[table_size - 1] -
2707 pdadc_tmp[table_size - 2];
2708 else
2709 pwr_step = 1;
2710
2711 /* Extrapolate above */
2712 while ((pdadc_0 < (s16) pdadc_n) &&
2713 (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2)) {
2714 s16 tmp = pdadc_tmp[table_size - 1] +
2715 (pdadc_0 - max_idx) * pwr_step;
2716 pdadc_out[pdadc_i++] = (tmp > 127) ? 127 : (u8) tmp;
2717 pdadc_0++;
2718 }
2719 }
2720
2721 while (pdg < AR5K_EEPROM_N_PD_GAINS) {
2722 gain_boundaries[pdg] = gain_boundaries[pdg - 1];
2723 pdg++;
2724 }
2725
2726 while (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2) {
2727 pdadc_out[pdadc_i] = pdadc_out[pdadc_i - 1];
2728 pdadc_i++;
2729 }
2730
2731 /* Set gain boundaries */
2732 ath5k_hw_reg_write(ah,
2733 AR5K_REG_SM(pd_gain_overlap,
2734 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP) |
2735 AR5K_REG_SM(gain_boundaries[0],
2736 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1) |
2737 AR5K_REG_SM(gain_boundaries[1],
2738 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2) |
2739 AR5K_REG_SM(gain_boundaries[2],
2740 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3) |
2741 AR5K_REG_SM(gain_boundaries[3],
2742 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4),
2743 AR5K_PHY_TPC_RG5);
2744
2745 /* Used for setting rate power table */
2746 ah->ah_txpower.txp_min_idx = pwr_min[0];
2747
2748 }
2749
2750 /* Write PDADC values on hw */
2751 static void
2752 ath5k_write_pwr_to_pdadc_table(struct ath5k_hw *ah, u8 ee_mode)
2753 {
2754 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2755 u8 *pdadc_out = ah->ah_txpower.txp_pd_table;
2756 u8 *pdg_to_idx = ee->ee_pdc_to_idx[ee_mode];
2757 u8 pdcurves = ee->ee_pd_gains[ee_mode];
2758 u32 reg;
2759 u8 i;
2760
2761 /* Select the right pdgain curves */
2762
2763 /* Clear current settings */
2764 reg = ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG1);
2765 reg &= ~(AR5K_PHY_TPC_RG1_PDGAIN_1 |
2766 AR5K_PHY_TPC_RG1_PDGAIN_2 |
2767 AR5K_PHY_TPC_RG1_PDGAIN_3 |
2768 AR5K_PHY_TPC_RG1_NUM_PD_GAIN);
2769
2770 /*
2771 * Use pd_gains curve from eeprom
2772 *
2773 * This overrides the default setting from initvals
2774 * in case some vendors (e.g. Zcomax) don't use the default
2775 * curves. If we don't honor their settings we 'll get a
2776 * 5dB (1 * gain overlap ?) drop.
2777 */
2778 reg |= AR5K_REG_SM(pdcurves, AR5K_PHY_TPC_RG1_NUM_PD_GAIN);
2779
2780 switch (pdcurves) {
2781 case 3:
2782 reg |= AR5K_REG_SM(pdg_to_idx[2], AR5K_PHY_TPC_RG1_PDGAIN_3);
2783 /* Fall through */
2784 case 2:
2785 reg |= AR5K_REG_SM(pdg_to_idx[1], AR5K_PHY_TPC_RG1_PDGAIN_2);
2786 /* Fall through */
2787 case 1:
2788 reg |= AR5K_REG_SM(pdg_to_idx[0], AR5K_PHY_TPC_RG1_PDGAIN_1);
2789 break;
2790 }
2791 ath5k_hw_reg_write(ah, reg, AR5K_PHY_TPC_RG1);
2792
2793 /*
2794 * Write TX power values
2795 */
2796 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
2797 ath5k_hw_reg_write(ah,
2798 ((pdadc_out[4 * i + 0] & 0xff) << 0) |
2799 ((pdadc_out[4 * i + 1] & 0xff) << 8) |
2800 ((pdadc_out[4 * i + 2] & 0xff) << 16) |
2801 ((pdadc_out[4 * i + 3] & 0xff) << 24),
2802 AR5K_PHY_PDADC_TXPOWER(i));
2803 }
2804 }
2805
2806
2807 /*
2808 * Common code for PCDAC/PDADC tables
2809 */
2810
2811 /*
2812 * This is the main function that uses all of the above
2813 * to set PCDAC/PDADC table on hw for the current channel.
2814 * This table is used for tx power calibration on the baseband,
2815 * without it we get weird tx power levels and in some cases
2816 * distorted spectral mask
2817 */
2818 static int
2819 ath5k_setup_channel_powertable(struct ath5k_hw *ah,
2820 struct ieee80211_channel *channel,
2821 u8 ee_mode, u8 type)
2822 {
2823 struct ath5k_pdgain_info *pdg_L, *pdg_R;
2824 struct ath5k_chan_pcal_info *pcinfo_L;
2825 struct ath5k_chan_pcal_info *pcinfo_R;
2826 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2827 u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode];
2828 s16 table_min[AR5K_EEPROM_N_PD_GAINS];
2829 s16 table_max[AR5K_EEPROM_N_PD_GAINS];
2830 u8 *tmpL;
2831 u8 *tmpR;
2832 u32 target = channel->center_freq;
2833 int pdg, i;
2834
2835 /* Get surrounding freq piers for this channel */
2836 ath5k_get_chan_pcal_surrounding_piers(ah, channel,
2837 &pcinfo_L,
2838 &pcinfo_R);
2839
2840 /* Loop over pd gain curves on
2841 * surrounding freq piers by index */
2842 for (pdg = 0; pdg < ee->ee_pd_gains[ee_mode]; pdg++) {
2843
2844 /* Fill curves in reverse order
2845 * from lower power (max gain)
2846 * to higher power. Use curve -> idx
2847 * backmapping we did on eeprom init */
2848 u8 idx = pdg_curve_to_idx[pdg];
2849
2850 /* Grab the needed curves by index */
2851 pdg_L = &pcinfo_L->pd_curves[idx];
2852 pdg_R = &pcinfo_R->pd_curves[idx];
2853
2854 /* Initialize the temp tables */
2855 tmpL = ah->ah_txpower.tmpL[pdg];
2856 tmpR = ah->ah_txpower.tmpR[pdg];
2857
2858 /* Set curve's x boundaries and create
2859 * curves so that they cover the same
2860 * range (if we don't do that one table
2861 * will have values on some range and the
2862 * other one won't have any so interpolation
2863 * will fail) */
2864 table_min[pdg] = min(pdg_L->pd_pwr[0],
2865 pdg_R->pd_pwr[0]) / 2;
2866
2867 table_max[pdg] = max(pdg_L->pd_pwr[pdg_L->pd_points - 1],
2868 pdg_R->pd_pwr[pdg_R->pd_points - 1]) / 2;
2869
2870 /* Now create the curves on surrounding channels
2871 * and interpolate if needed to get the final
2872 * curve for this gain on this channel */
2873 switch (type) {
2874 case AR5K_PWRTABLE_LINEAR_PCDAC:
2875 /* Override min/max so that we don't loose
2876 * accuracy (don't divide by 2) */
2877 table_min[pdg] = min(pdg_L->pd_pwr[0],
2878 pdg_R->pd_pwr[0]);
2879
2880 table_max[pdg] =
2881 max(pdg_L->pd_pwr[pdg_L->pd_points - 1],
2882 pdg_R->pd_pwr[pdg_R->pd_points - 1]);
2883
2884 /* Override minimum so that we don't get
2885 * out of bounds while extrapolating
2886 * below. Don't do this when we have 2
2887 * curves and we are on the high power curve
2888 * because table_min is ok in this case */
2889 if (!(ee->ee_pd_gains[ee_mode] > 1 && pdg == 0)) {
2890
2891 table_min[pdg] =
2892 ath5k_get_linear_pcdac_min(pdg_L->pd_step,
2893 pdg_R->pd_step,
2894 pdg_L->pd_pwr,
2895 pdg_R->pd_pwr);
2896
2897 /* Don't go too low because we will
2898 * miss the upper part of the curve.
2899 * Note: 126 = 31.5dB (max power supported)
2900 * in 0.25dB units */
2901 if (table_max[pdg] - table_min[pdg] > 126)
2902 table_min[pdg] = table_max[pdg] - 126;
2903 }
2904
2905 /* Fall through */
2906 case AR5K_PWRTABLE_PWR_TO_PCDAC:
2907 case AR5K_PWRTABLE_PWR_TO_PDADC:
2908
2909 ath5k_create_power_curve(table_min[pdg],
2910 table_max[pdg],
2911 pdg_L->pd_pwr,
2912 pdg_L->pd_step,
2913 pdg_L->pd_points, tmpL, type);
2914
2915 /* We are in a calibration
2916 * pier, no need to interpolate
2917 * between freq piers */
2918 if (pcinfo_L == pcinfo_R)
2919 continue;
2920
2921 ath5k_create_power_curve(table_min[pdg],
2922 table_max[pdg],
2923 pdg_R->pd_pwr,
2924 pdg_R->pd_step,
2925 pdg_R->pd_points, tmpR, type);
2926 break;
2927 default:
2928 return -EINVAL;
2929 }
2930
2931 /* Interpolate between curves
2932 * of surrounding freq piers to
2933 * get the final curve for this
2934 * pd gain. Re-use tmpL for interpolation
2935 * output */
2936 for (i = 0; (i < (u16) (table_max[pdg] - table_min[pdg])) &&
2937 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) {
2938 tmpL[i] = (u8) ath5k_get_interpolated_value(target,
2939 (s16) pcinfo_L->freq,
2940 (s16) pcinfo_R->freq,
2941 (s16) tmpL[i],
2942 (s16) tmpR[i]);
2943 }
2944 }
2945
2946 /* Now we have a set of curves for this
2947 * channel on tmpL (x range is table_max - table_min
2948 * and y values are tmpL[pdg][]) sorted in the same
2949 * order as EEPROM (because we've used the backmapping).
2950 * So for RF5112 it's from higher power to lower power
2951 * and for RF2413 it's from lower power to higher power.
2952 * For RF5111 we only have one curve. */
2953
2954 /* Fill min and max power levels for this
2955 * channel by interpolating the values on
2956 * surrounding channels to complete the dataset */
2957 ah->ah_txpower.txp_min_pwr = ath5k_get_interpolated_value(target,
2958 (s16) pcinfo_L->freq,
2959 (s16) pcinfo_R->freq,
2960 pcinfo_L->min_pwr, pcinfo_R->min_pwr);
2961
2962 ah->ah_txpower.txp_max_pwr = ath5k_get_interpolated_value(target,
2963 (s16) pcinfo_L->freq,
2964 (s16) pcinfo_R->freq,
2965 pcinfo_L->max_pwr, pcinfo_R->max_pwr);
2966
2967 /* Fill PCDAC/PDADC table */
2968 switch (type) {
2969 case AR5K_PWRTABLE_LINEAR_PCDAC:
2970 /* For RF5112 we can have one or two curves
2971 * and each curve covers a certain power lvl
2972 * range so we need to do some more processing */
2973 ath5k_combine_linear_pcdac_curves(ah, table_min, table_max,
2974 ee->ee_pd_gains[ee_mode]);
2975
2976 /* Set txp.offset so that we can
2977 * match max power value with max
2978 * table index */
2979 ah->ah_txpower.txp_offset = 64 - (table_max[0] / 2);
2980 break;
2981 case AR5K_PWRTABLE_PWR_TO_PCDAC:
2982 /* We are done for RF5111 since it has only
2983 * one curve, just fit the curve on the table */
2984 ath5k_fill_pwr_to_pcdac_table(ah, table_min, table_max);
2985
2986 /* No rate powertable adjustment for RF5111 */
2987 ah->ah_txpower.txp_min_idx = 0;
2988 ah->ah_txpower.txp_offset = 0;
2989 break;
2990 case AR5K_PWRTABLE_PWR_TO_PDADC:
2991 /* Set PDADC boundaries and fill
2992 * final PDADC table */
2993 ath5k_combine_pwr_to_pdadc_curves(ah, table_min, table_max,
2994 ee->ee_pd_gains[ee_mode]);
2995
2996 /* Set txp.offset, note that table_min
2997 * can be negative */
2998 ah->ah_txpower.txp_offset = table_min[0];
2999 break;
3000 default:
3001 return -EINVAL;
3002 }
3003
3004 ah->ah_txpower.txp_setup = true;
3005
3006 return 0;
3007 }
3008
3009 /* Write power table for current channel to hw */
3010 static void
3011 ath5k_write_channel_powertable(struct ath5k_hw *ah, u8 ee_mode, u8 type)
3012 {
3013 if (type == AR5K_PWRTABLE_PWR_TO_PDADC)
3014 ath5k_write_pwr_to_pdadc_table(ah, ee_mode);
3015 else
3016 ath5k_write_pcdac_table(ah);
3017 }
3018
3019 /*
3020 * Per-rate tx power setting
3021 *
3022 * This is the code that sets the desired tx power (below
3023 * maximum) on hw for each rate (we also have TPC that sets
3024 * power per packet). We do that by providing an index on the
3025 * PCDAC/PDADC table we set up.
3026 */
3027
3028 /*
3029 * Set rate power table
3030 *
3031 * For now we only limit txpower based on maximum tx power
3032 * supported by hw (what's inside rate_info). We need to limit
3033 * this even more, based on regulatory domain etc.
3034 *
3035 * Rate power table contains indices to PCDAC/PDADC table (0.5dB steps)
3036 * and is indexed as follows:
3037 * rates[0] - rates[7] -> OFDM rates
3038 * rates[8] - rates[14] -> CCK rates
3039 * rates[15] -> XR rates (they all have the same power)
3040 */
3041 static void
3042 ath5k_setup_rate_powertable(struct ath5k_hw *ah, u16 max_pwr,
3043 struct ath5k_rate_pcal_info *rate_info,
3044 u8 ee_mode)
3045 {
3046 unsigned int i;
3047 u16 *rates;
3048
3049 /* max_pwr is power level we got from driver/user in 0.5dB
3050 * units, switch to 0.25dB units so we can compare */
3051 max_pwr *= 2;
3052 max_pwr = min(max_pwr, (u16) ah->ah_txpower.txp_max_pwr) / 2;
3053
3054 /* apply rate limits */
3055 rates = ah->ah_txpower.txp_rates_power_table;
3056
3057 /* OFDM rates 6 to 24Mb/s */
3058 for (i = 0; i < 5; i++)
3059 rates[i] = min(max_pwr, rate_info->target_power_6to24);
3060
3061 /* Rest OFDM rates */
3062 rates[5] = min(rates[0], rate_info->target_power_36);
3063 rates[6] = min(rates[0], rate_info->target_power_48);
3064 rates[7] = min(rates[0], rate_info->target_power_54);
3065
3066 /* CCK rates */
3067 /* 1L */
3068 rates[8] = min(rates[0], rate_info->target_power_6to24);
3069 /* 2L */
3070 rates[9] = min(rates[0], rate_info->target_power_36);
3071 /* 2S */
3072 rates[10] = min(rates[0], rate_info->target_power_36);
3073 /* 5L */
3074 rates[11] = min(rates[0], rate_info->target_power_48);
3075 /* 5S */
3076 rates[12] = min(rates[0], rate_info->target_power_48);
3077 /* 11L */
3078 rates[13] = min(rates[0], rate_info->target_power_54);
3079 /* 11S */
3080 rates[14] = min(rates[0], rate_info->target_power_54);
3081
3082 /* XR rates */
3083 rates[15] = min(rates[0], rate_info->target_power_6to24);
3084
3085 /* CCK rates have different peak to average ratio
3086 * so we have to tweak their power so that gainf
3087 * correction works ok. For this we use OFDM to
3088 * CCK delta from eeprom */
3089 if ((ee_mode == AR5K_EEPROM_MODE_11G) &&
3090 (ah->ah_phy_revision < AR5K_SREV_PHY_5212A))
3091 for (i = 8; i <= 15; i++)
3092 rates[i] -= ah->ah_txpower.txp_cck_ofdm_gainf_delta;
3093
3094 /* Now that we have all rates setup use table offset to
3095 * match the power range set by user with the power indices
3096 * on PCDAC/PDADC table */
3097 for (i = 0; i < 16; i++) {
3098 rates[i] += ah->ah_txpower.txp_offset;
3099 /* Don't get out of bounds */
3100 if (rates[i] > 63)
3101 rates[i] = 63;
3102 }
3103
3104 /* Min/max in 0.25dB units */
3105 ah->ah_txpower.txp_min_pwr = 2 * rates[7];
3106 ah->ah_txpower.txp_cur_pwr = 2 * rates[0];
3107 ah->ah_txpower.txp_ofdm = rates[7];
3108 }
3109
3110
3111 /*
3112 * Set transmission power
3113 */
3114 static int
3115 ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
3116 u8 txpower)
3117 {
3118 struct ath5k_rate_pcal_info rate_info;
3119 struct ieee80211_channel *curr_channel = ah->ah_current_channel;
3120 int ee_mode;
3121 u8 type;
3122 int ret;
3123
3124 if (txpower > AR5K_TUNE_MAX_TXPOWER) {
3125 ATH5K_ERR(ah->ah_sc, "invalid tx power: %u\n", txpower);
3126 return -EINVAL;
3127 }
3128
3129 ee_mode = ath5k_eeprom_mode_from_channel(channel);
3130 if (ee_mode < 0) {
3131 ATH5K_ERR(ah->ah_sc,
3132 "invalid channel: %d\n", channel->center_freq);
3133 return -EINVAL;
3134 }
3135
3136 /* Initialize TX power table */
3137 switch (ah->ah_radio) {
3138 case AR5K_RF5110:
3139 /* TODO */
3140 return 0;
3141 case AR5K_RF5111:
3142 type = AR5K_PWRTABLE_PWR_TO_PCDAC;
3143 break;
3144 case AR5K_RF5112:
3145 type = AR5K_PWRTABLE_LINEAR_PCDAC;
3146 break;
3147 case AR5K_RF2413:
3148 case AR5K_RF5413:
3149 case AR5K_RF2316:
3150 case AR5K_RF2317:
3151 case AR5K_RF2425:
3152 type = AR5K_PWRTABLE_PWR_TO_PDADC;
3153 break;
3154 default:
3155 return -EINVAL;
3156 }
3157
3158 /*
3159 * If we don't change channel/mode skip tx powertable calculation
3160 * and use the cached one.
3161 */
3162 if (!ah->ah_txpower.txp_setup ||
3163 (channel->hw_value != curr_channel->hw_value) ||
3164 (channel->center_freq != curr_channel->center_freq)) {
3165 /* Reset TX power values */
3166 memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower));
3167 ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
3168
3169 /* Calculate the powertable */
3170 ret = ath5k_setup_channel_powertable(ah, channel,
3171 ee_mode, type);
3172 if (ret)
3173 return ret;
3174 }
3175
3176 /* Write table on hw */
3177 ath5k_write_channel_powertable(ah, ee_mode, type);
3178
3179 /* Limit max power if we have a CTL available */
3180 ath5k_get_max_ctl_power(ah, channel);
3181
3182 /* FIXME: Antenna reduction stuff */
3183
3184 /* FIXME: Limit power on turbo modes */
3185
3186 /* FIXME: TPC scale reduction */
3187
3188 /* Get surrounding channels for per-rate power table
3189 * calibration */
3190 ath5k_get_rate_pcal_data(ah, channel, &rate_info);
3191
3192 /* Setup rate power table */
3193 ath5k_setup_rate_powertable(ah, txpower, &rate_info, ee_mode);
3194
3195 /* Write rate power table on hw */
3196 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(3, 24) |
3197 AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) |
3198 AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1);
3199
3200 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(7, 24) |
3201 AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) |
3202 AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2);
3203
3204 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(10, 24) |
3205 AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) |
3206 AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3);
3207
3208 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(14, 24) |
3209 AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) |
3210 AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4);
3211
3212 /* FIXME: TPC support */
3213 if (ah->ah_txpower.txp_tpc) {
3214 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE |
3215 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
3216
3217 ath5k_hw_reg_write(ah,
3218 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_ACK) |
3219 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CTS) |
3220 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CHIRP),
3221 AR5K_TPC);
3222 } else {
3223 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX |
3224 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
3225 }
3226
3227 return 0;
3228 }
3229
3230 int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower)
3231 {
3232 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_TXPOWER,
3233 "changing txpower to %d\n", txpower);
3234
3235 return ath5k_hw_txpower(ah, ah->ah_current_channel, txpower);
3236 }
3237
3238 /*************\
3239 Init function
3240 \*************/
3241
3242 int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
3243 u8 mode, bool fast)
3244 {
3245 struct ieee80211_channel *curr_channel;
3246 int ret, i;
3247 u32 phy_tst1;
3248 ret = 0;
3249
3250 /*
3251 * Sanity check for fast flag
3252 * Don't try fast channel change when changing modulation
3253 * mode/band. We check for chip compatibility on
3254 * ath5k_hw_reset.
3255 */
3256 curr_channel = ah->ah_current_channel;
3257 if (fast && (channel->hw_value != curr_channel->hw_value))
3258 return -EINVAL;
3259
3260 /*
3261 * On fast channel change we only set the synth parameters
3262 * while PHY is running, enable calibration and skip the rest.
3263 */
3264 if (fast) {
3265 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_RFBUS_REQ,
3266 AR5K_PHY_RFBUS_REQ_REQUEST);
3267 for (i = 0; i < 100; i++) {
3268 if (ath5k_hw_reg_read(ah, AR5K_PHY_RFBUS_GRANT))
3269 break;
3270 udelay(5);
3271 }
3272 /* Failed */
3273 if (i >= 100)
3274 return -EIO;
3275
3276 /* Set channel and wait for synth */
3277 ret = ath5k_hw_channel(ah, channel);
3278 if (ret)
3279 return ret;
3280
3281 ath5k_hw_wait_for_synth(ah, channel);
3282 }
3283
3284 /*
3285 * Set TX power
3286 *
3287 * Note: We need to do that before we set
3288 * RF buffer settings on 5211/5212+ so that we
3289 * properly set curve indices.
3290 */
3291 ret = ath5k_hw_txpower(ah, channel, ah->ah_txpower.txp_cur_pwr ?
3292 ah->ah_txpower.txp_cur_pwr / 2 : AR5K_TUNE_MAX_TXPOWER);
3293 if (ret)
3294 return ret;
3295
3296 /* Write OFDM timings on 5212*/
3297 if (ah->ah_version == AR5K_AR5212 &&
3298 channel->hw_value & CHANNEL_OFDM) {
3299
3300 ret = ath5k_hw_write_ofdm_timings(ah, channel);
3301 if (ret)
3302 return ret;
3303
3304 /* Spur info is available only from EEPROM versions
3305 * greater than 5.3, but the EEPROM routines will use
3306 * static values for older versions */
3307 if (ah->ah_mac_srev >= AR5K_SREV_AR5424)
3308 ath5k_hw_set_spur_mitigation_filter(ah,
3309 channel);
3310 }
3311
3312 /* If we used fast channel switching
3313 * we are done, release RF bus and
3314 * fire up NF calibration.
3315 *
3316 * Note: Only NF calibration due to
3317 * channel change, not AGC calibration
3318 * since AGC is still running !
3319 */
3320 if (fast) {
3321 /*
3322 * Release RF Bus grant
3323 */
3324 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_RFBUS_REQ,
3325 AR5K_PHY_RFBUS_REQ_REQUEST);
3326
3327 /*
3328 * Start NF calibration
3329 */
3330 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
3331 AR5K_PHY_AGCCTL_NF);
3332
3333 return ret;
3334 }
3335
3336 /*
3337 * For 5210 we do all initialization using
3338 * initvals, so we don't have to modify
3339 * any settings (5210 also only supports
3340 * a/aturbo modes)
3341 */
3342 if (ah->ah_version != AR5K_AR5210) {
3343
3344 /*
3345 * Write initial RF gain settings
3346 * This should work for both 5111/5112
3347 */
3348 ret = ath5k_hw_rfgain_init(ah, channel->band);
3349 if (ret)
3350 return ret;
3351
3352 mdelay(1);
3353
3354 /*
3355 * Write RF buffer
3356 */
3357 ret = ath5k_hw_rfregs_init(ah, channel, mode);
3358 if (ret)
3359 return ret;
3360
3361 /*Enable/disable 802.11b mode on 5111
3362 (enable 2111 frequency converter + CCK)*/
3363 if (ah->ah_radio == AR5K_RF5111) {
3364 if (mode == AR5K_MODE_11B)
3365 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG,
3366 AR5K_TXCFG_B_MODE);
3367 else
3368 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
3369 AR5K_TXCFG_B_MODE);
3370 }
3371
3372 } else if (ah->ah_version == AR5K_AR5210) {
3373 mdelay(1);
3374 /* Disable phy and wait */
3375 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
3376 mdelay(1);
3377 }
3378
3379 /* Set channel on PHY */
3380 ret = ath5k_hw_channel(ah, channel);
3381 if (ret)
3382 return ret;
3383
3384 /*
3385 * Enable the PHY and wait until completion
3386 * This includes BaseBand and Synthesizer
3387 * activation.
3388 */
3389 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
3390
3391 ath5k_hw_wait_for_synth(ah, channel);
3392
3393 /*
3394 * Perform ADC test to see if baseband is ready
3395 * Set tx hold and check adc test register
3396 */
3397 phy_tst1 = ath5k_hw_reg_read(ah, AR5K_PHY_TST1);
3398 ath5k_hw_reg_write(ah, AR5K_PHY_TST1_TXHOLD, AR5K_PHY_TST1);
3399 for (i = 0; i <= 20; i++) {
3400 if (!(ath5k_hw_reg_read(ah, AR5K_PHY_ADC_TEST) & 0x10))
3401 break;
3402 udelay(200);
3403 }
3404 ath5k_hw_reg_write(ah, phy_tst1, AR5K_PHY_TST1);
3405
3406 /*
3407 * Start automatic gain control calibration
3408 *
3409 * During AGC calibration RX path is re-routed to
3410 * a power detector so we don't receive anything.
3411 *
3412 * This method is used to calibrate some static offsets
3413 * used together with on-the fly I/Q calibration (the
3414 * one performed via ath5k_hw_phy_calibrate), which doesn't
3415 * interrupt rx path.
3416 *
3417 * While rx path is re-routed to the power detector we also
3418 * start a noise floor calibration to measure the
3419 * card's noise floor (the noise we measure when we are not
3420 * transmitting or receiving anything).
3421 *
3422 * If we are in a noisy environment, AGC calibration may time
3423 * out and/or noise floor calibration might timeout.
3424 */
3425 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
3426 AR5K_PHY_AGCCTL_CAL | AR5K_PHY_AGCCTL_NF);
3427
3428 /* At the same time start I/Q calibration for QAM constellation
3429 * -no need for CCK- */
3430 ah->ah_calibration = false;
3431 if (!(mode == AR5K_MODE_11B)) {
3432 ah->ah_calibration = true;
3433 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
3434 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
3435 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
3436 AR5K_PHY_IQ_RUN);
3437 }
3438
3439 /* Wait for gain calibration to finish (we check for I/Q calibration
3440 * during ath5k_phy_calibrate) */
3441 if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
3442 AR5K_PHY_AGCCTL_CAL, 0, false)) {
3443 ATH5K_ERR(ah->ah_sc, "gain calibration timeout (%uMHz)\n",
3444 channel->center_freq);
3445 }
3446
3447 /* Restore antenna mode */
3448 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode);
3449
3450 return ret;
3451 }
Linux kernel - Deliverables
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