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Merge branch 'hwmon-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jdelv...
[deliverable/linux.git] / drivers / net / wireless / ath / ath5k / reset.c
1 /*
2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu>
5 * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
7 *
8 * Permission to use, copy, modify, and distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 *
20 */
21
22 #define _ATH5K_RESET
23
24 /*****************************\
25 Reset functions and helpers
26 \*****************************/
27
28 #include <linux/pci.h> /* To determine if a card is pci-e */
29 #include <linux/log2.h>
30 #include "ath5k.h"
31 #include "reg.h"
32 #include "base.h"
33 #include "debug.h"
34
35 /**
36 * ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212
37 *
38 * @ah: the &struct ath5k_hw
39 * @channel: the currently set channel upon reset
40 *
41 * Write the delta slope coefficient (used on pilot tracking ?) for OFDM
42 * operation on the AR5212 upon reset. This is a helper for ath5k_hw_reset().
43 *
44 * Since delta slope is floating point we split it on its exponent and
45 * mantissa and provide these values on hw.
46 *
47 * For more infos i think this patent is related
48 * http://www.freepatentsonline.com/7184495.html
49 */
50 static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah,
51 struct ieee80211_channel *channel)
52 {
53 /* Get exponent and mantissa and set it */
54 u32 coef_scaled, coef_exp, coef_man,
55 ds_coef_exp, ds_coef_man, clock;
56
57 BUG_ON(!(ah->ah_version == AR5K_AR5212) ||
58 !(channel->hw_value & CHANNEL_OFDM));
59
60 /* Get coefficient
61 * ALGO: coef = (5 * clock * carrier_freq) / 2)
62 * we scale coef by shifting clock value by 24 for
63 * better precision since we use integers */
64 /* TODO: Half/quarter rate */
65 clock = ath5k_hw_htoclock(1, channel->hw_value & CHANNEL_TURBO);
66
67 coef_scaled = ((5 * (clock << 24)) / 2) / channel->center_freq;
68
69 /* Get exponent
70 * ALGO: coef_exp = 14 - highest set bit position */
71 coef_exp = ilog2(coef_scaled);
72
73 /* Doesn't make sense if it's zero*/
74 if (!coef_scaled || !coef_exp)
75 return -EINVAL;
76
77 /* Note: we've shifted coef_scaled by 24 */
78 coef_exp = 14 - (coef_exp - 24);
79
80
81 /* Get mantissa (significant digits)
82 * ALGO: coef_mant = floor(coef_scaled* 2^coef_exp+0.5) */
83 coef_man = coef_scaled +
84 (1 << (24 - coef_exp - 1));
85
86 /* Calculate delta slope coefficient exponent
87 * and mantissa (remove scaling) and set them on hw */
88 ds_coef_man = coef_man >> (24 - coef_exp);
89 ds_coef_exp = coef_exp - 16;
90
91 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
92 AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man);
93 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
94 AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp);
95
96 return 0;
97 }
98
99
100 /*
101 * index into rates for control rates, we can set it up like this because
102 * this is only used for AR5212 and we know it supports G mode
103 */
104 static const unsigned int control_rates[] =
105 { 0, 1, 1, 1, 4, 4, 6, 6, 8, 8, 8, 8 };
106
107 /**
108 * ath5k_hw_write_rate_duration - fill rate code to duration table
109 *
110 * @ah: the &struct ath5k_hw
111 * @mode: one of enum ath5k_driver_mode
112 *
113 * Write the rate code to duration table upon hw reset. This is a helper for
114 * ath5k_hw_reset(). It seems all this is doing is setting an ACK timeout on
115 * the hardware, based on current mode, for each rate. The rates which are
116 * capable of short preamble (802.11b rates 2Mbps, 5.5Mbps, and 11Mbps) have
117 * different rate code so we write their value twice (one for long preample
118 * and one for short).
119 *
120 * Note: Band doesn't matter here, if we set the values for OFDM it works
121 * on both a and g modes. So all we have to do is set values for all g rates
122 * that include all OFDM and CCK rates. If we operate in turbo or xr/half/
123 * quarter rate mode, we need to use another set of bitrates (that's why we
124 * need the mode parameter) but we don't handle these proprietary modes yet.
125 */
126 static inline void ath5k_hw_write_rate_duration(struct ath5k_hw *ah,
127 unsigned int mode)
128 {
129 struct ath5k_softc *sc = ah->ah_sc;
130 struct ieee80211_rate *rate;
131 unsigned int i;
132
133 /* Write rate duration table */
134 for (i = 0; i < sc->sbands[IEEE80211_BAND_2GHZ].n_bitrates; i++) {
135 u32 reg;
136 u16 tx_time;
137
138 rate = &sc->sbands[IEEE80211_BAND_2GHZ].bitrates[control_rates[i]];
139
140 /* Set ACK timeout */
141 reg = AR5K_RATE_DUR(rate->hw_value);
142
143 /* An ACK frame consists of 10 bytes. If you add the FCS,
144 * which ieee80211_generic_frame_duration() adds,
145 * its 14 bytes. Note we use the control rate and not the
146 * actual rate for this rate. See mac80211 tx.c
147 * ieee80211_duration() for a brief description of
148 * what rate we should choose to TX ACKs. */
149 tx_time = le16_to_cpu(ieee80211_generic_frame_duration(sc->hw,
150 sc->vif, 10, rate));
151
152 ath5k_hw_reg_write(ah, tx_time, reg);
153
154 if (!(rate->flags & IEEE80211_RATE_SHORT_PREAMBLE))
155 continue;
156
157 /*
158 * We're not distinguishing short preamble here,
159 * This is true, all we'll get is a longer value here
160 * which is not necessarilly bad. We could use
161 * export ieee80211_frame_duration() but that needs to be
162 * fixed first to be properly used by mac802111 drivers:
163 *
164 * - remove erp stuff and let the routine figure ofdm
165 * erp rates
166 * - remove passing argument ieee80211_local as
167 * drivers don't have access to it
168 * - move drivers using ieee80211_generic_frame_duration()
169 * to this
170 */
171 ath5k_hw_reg_write(ah, tx_time,
172 reg + (AR5K_SET_SHORT_PREAMBLE << 2));
173 }
174 }
175
176 /*
177 * Reset chipset
178 */
179 static int ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val)
180 {
181 int ret;
182 u32 mask = val ? val : ~0U;
183
184 ATH5K_TRACE(ah->ah_sc);
185
186 /* Read-and-clear RX Descriptor Pointer*/
187 ath5k_hw_reg_read(ah, AR5K_RXDP);
188
189 /*
190 * Reset the device and wait until success
191 */
192 ath5k_hw_reg_write(ah, val, AR5K_RESET_CTL);
193
194 /* Wait at least 128 PCI clocks */
195 udelay(15);
196
197 if (ah->ah_version == AR5K_AR5210) {
198 val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA
199 | AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY;
200 mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA
201 | AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY;
202 } else {
203 val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
204 mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
205 }
206
207 ret = ath5k_hw_register_timeout(ah, AR5K_RESET_CTL, mask, val, false);
208
209 /*
210 * Reset configuration register (for hw byte-swap). Note that this
211 * is only set for big endian. We do the necessary magic in
212 * AR5K_INIT_CFG.
213 */
214 if ((val & AR5K_RESET_CTL_PCU) == 0)
215 ath5k_hw_reg_write(ah, AR5K_INIT_CFG, AR5K_CFG);
216
217 return ret;
218 }
219
220 /*
221 * Sleep control
222 */
223 int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode,
224 bool set_chip, u16 sleep_duration)
225 {
226 unsigned int i;
227 u32 staid, data;
228
229 ATH5K_TRACE(ah->ah_sc);
230 staid = ath5k_hw_reg_read(ah, AR5K_STA_ID1);
231
232 switch (mode) {
233 case AR5K_PM_AUTO:
234 staid &= ~AR5K_STA_ID1_DEFAULT_ANTENNA;
235 /* fallthrough */
236 case AR5K_PM_NETWORK_SLEEP:
237 if (set_chip)
238 ath5k_hw_reg_write(ah,
239 AR5K_SLEEP_CTL_SLE_ALLOW |
240 sleep_duration,
241 AR5K_SLEEP_CTL);
242
243 staid |= AR5K_STA_ID1_PWR_SV;
244 break;
245
246 case AR5K_PM_FULL_SLEEP:
247 if (set_chip)
248 ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_SLP,
249 AR5K_SLEEP_CTL);
250
251 staid |= AR5K_STA_ID1_PWR_SV;
252 break;
253
254 case AR5K_PM_AWAKE:
255
256 staid &= ~AR5K_STA_ID1_PWR_SV;
257
258 if (!set_chip)
259 goto commit;
260
261 /* Preserve sleep duration */
262 data = ath5k_hw_reg_read(ah, AR5K_SLEEP_CTL);
263 if (data & 0xffc00000)
264 data = 0;
265 else
266 data = data & 0xfffcffff;
267
268 ath5k_hw_reg_write(ah, data, AR5K_SLEEP_CTL);
269 udelay(15);
270
271 for (i = 50; i > 0; i--) {
272 /* Check if the chip did wake up */
273 if ((ath5k_hw_reg_read(ah, AR5K_PCICFG) &
274 AR5K_PCICFG_SPWR_DN) == 0)
275 break;
276
277 /* Wait a bit and retry */
278 udelay(200);
279 ath5k_hw_reg_write(ah, data, AR5K_SLEEP_CTL);
280 }
281
282 /* Fail if the chip didn't wake up */
283 if (i <= 0)
284 return -EIO;
285
286 break;
287
288 default:
289 return -EINVAL;
290 }
291
292 commit:
293 ah->ah_power_mode = mode;
294 ath5k_hw_reg_write(ah, staid, AR5K_STA_ID1);
295
296 return 0;
297 }
298
299 /*
300 * Bring up MAC + PHY Chips and program PLL
301 * TODO: Half/Quarter rate support
302 */
303 int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
304 {
305 struct pci_dev *pdev = ah->ah_sc->pdev;
306 u32 turbo, mode, clock, bus_flags;
307 int ret;
308
309 turbo = 0;
310 mode = 0;
311 clock = 0;
312
313 ATH5K_TRACE(ah->ah_sc);
314
315 /* Wakeup the device */
316 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
317 if (ret) {
318 ATH5K_ERR(ah->ah_sc, "failed to wakeup the MAC Chip\n");
319 return ret;
320 }
321
322 if (ah->ah_version != AR5K_AR5210) {
323 /*
324 * Get channel mode flags
325 */
326
327 if (ah->ah_radio >= AR5K_RF5112) {
328 mode = AR5K_PHY_MODE_RAD_RF5112;
329 clock = AR5K_PHY_PLL_RF5112;
330 } else {
331 mode = AR5K_PHY_MODE_RAD_RF5111; /*Zero*/
332 clock = AR5K_PHY_PLL_RF5111; /*Zero*/
333 }
334
335 if (flags & CHANNEL_2GHZ) {
336 mode |= AR5K_PHY_MODE_FREQ_2GHZ;
337 clock |= AR5K_PHY_PLL_44MHZ;
338
339 if (flags & CHANNEL_CCK) {
340 mode |= AR5K_PHY_MODE_MOD_CCK;
341 } else if (flags & CHANNEL_OFDM) {
342 /* XXX Dynamic OFDM/CCK is not supported by the
343 * AR5211 so we set MOD_OFDM for plain g (no
344 * CCK headers) operation. We need to test
345 * this, 5211 might support ofdm-only g after
346 * all, there are also initial register values
347 * in the code for g mode (see initvals.c). */
348 if (ah->ah_version == AR5K_AR5211)
349 mode |= AR5K_PHY_MODE_MOD_OFDM;
350 else
351 mode |= AR5K_PHY_MODE_MOD_DYN;
352 } else {
353 ATH5K_ERR(ah->ah_sc,
354 "invalid radio modulation mode\n");
355 return -EINVAL;
356 }
357 } else if (flags & CHANNEL_5GHZ) {
358 mode |= AR5K_PHY_MODE_FREQ_5GHZ;
359
360 if (ah->ah_radio == AR5K_RF5413)
361 clock = AR5K_PHY_PLL_40MHZ_5413;
362 else
363 clock |= AR5K_PHY_PLL_40MHZ;
364
365 if (flags & CHANNEL_OFDM)
366 mode |= AR5K_PHY_MODE_MOD_OFDM;
367 else {
368 ATH5K_ERR(ah->ah_sc,
369 "invalid radio modulation mode\n");
370 return -EINVAL;
371 }
372 } else {
373 ATH5K_ERR(ah->ah_sc, "invalid radio frequency mode\n");
374 return -EINVAL;
375 }
376
377 if (flags & CHANNEL_TURBO)
378 turbo = AR5K_PHY_TURBO_MODE | AR5K_PHY_TURBO_SHORT;
379 } else { /* Reset the device */
380
381 /* ...enable Atheros turbo mode if requested */
382 if (flags & CHANNEL_TURBO)
383 ath5k_hw_reg_write(ah, AR5K_PHY_TURBO_MODE,
384 AR5K_PHY_TURBO);
385 }
386
387 /* reseting PCI on PCI-E cards results card to hang
388 * and always return 0xffff... so we ingore that flag
389 * for PCI-E cards */
390 bus_flags = (pdev->is_pcie) ? 0 : AR5K_RESET_CTL_PCI;
391
392 /* Reset chipset */
393 if (ah->ah_version == AR5K_AR5210) {
394 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
395 AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA |
396 AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI);
397 mdelay(2);
398 } else {
399 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
400 AR5K_RESET_CTL_BASEBAND | bus_flags);
401 }
402 if (ret) {
403 ATH5K_ERR(ah->ah_sc, "failed to reset the MAC Chip\n");
404 return -EIO;
405 }
406
407 /* ...wakeup again!*/
408 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
409 if (ret) {
410 ATH5K_ERR(ah->ah_sc, "failed to resume the MAC Chip\n");
411 return ret;
412 }
413
414 /* ...final warm reset */
415 if (ath5k_hw_nic_reset(ah, 0)) {
416 ATH5K_ERR(ah->ah_sc, "failed to warm reset the MAC Chip\n");
417 return -EIO;
418 }
419
420 if (ah->ah_version != AR5K_AR5210) {
421
422 /* ...update PLL if needed */
423 if (ath5k_hw_reg_read(ah, AR5K_PHY_PLL) != clock) {
424 ath5k_hw_reg_write(ah, clock, AR5K_PHY_PLL);
425 udelay(300);
426 }
427
428 /* ...set the PHY operating mode */
429 ath5k_hw_reg_write(ah, mode, AR5K_PHY_MODE);
430 ath5k_hw_reg_write(ah, turbo, AR5K_PHY_TURBO);
431 }
432
433 return 0;
434 }
435
436 /*
437 * If there is an external 32KHz crystal available, use it
438 * as ref. clock instead of 32/40MHz clock and baseband clocks
439 * to save power during sleep or restore normal 32/40MHz
440 * operation.
441 *
442 * XXX: When operating on 32KHz certain PHY registers (27 - 31,
443 * 123 - 127) require delay on access.
444 */
445 static void ath5k_hw_set_sleep_clock(struct ath5k_hw *ah, bool enable)
446 {
447 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
448 u32 scal, spending, usec32;
449
450 /* Only set 32KHz settings if we have an external
451 * 32KHz crystal present */
452 if ((AR5K_EEPROM_HAS32KHZCRYSTAL(ee->ee_misc1) ||
453 AR5K_EEPROM_HAS32KHZCRYSTAL_OLD(ee->ee_misc1)) &&
454 enable) {
455
456 /* 1 usec/cycle */
457 AR5K_REG_WRITE_BITS(ah, AR5K_USEC_5211, AR5K_USEC_32, 1);
458 /* Set up tsf increment on each cycle */
459 AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 61);
460
461 /* Set baseband sleep control registers
462 * and sleep control rate */
463 ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR);
464
465 if ((ah->ah_radio == AR5K_RF5112) ||
466 (ah->ah_radio == AR5K_RF5413) ||
467 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
468 spending = 0x14;
469 else
470 spending = 0x18;
471 ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING);
472
473 if ((ah->ah_radio == AR5K_RF5112) ||
474 (ah->ah_radio == AR5K_RF5413) ||
475 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) {
476 ath5k_hw_reg_write(ah, 0x26, AR5K_PHY_SLMT);
477 ath5k_hw_reg_write(ah, 0x0d, AR5K_PHY_SCAL);
478 ath5k_hw_reg_write(ah, 0x07, AR5K_PHY_SCLOCK);
479 ath5k_hw_reg_write(ah, 0x3f, AR5K_PHY_SDELAY);
480 AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
481 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0x02);
482 } else {
483 ath5k_hw_reg_write(ah, 0x0a, AR5K_PHY_SLMT);
484 ath5k_hw_reg_write(ah, 0x0c, AR5K_PHY_SCAL);
485 ath5k_hw_reg_write(ah, 0x03, AR5K_PHY_SCLOCK);
486 ath5k_hw_reg_write(ah, 0x20, AR5K_PHY_SDELAY);
487 AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
488 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0x03);
489 }
490
491 /* Enable sleep clock operation */
492 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG,
493 AR5K_PCICFG_SLEEP_CLOCK_EN);
494
495 } else {
496
497 /* Disable sleep clock operation and
498 * restore default parameters */
499 AR5K_REG_DISABLE_BITS(ah, AR5K_PCICFG,
500 AR5K_PCICFG_SLEEP_CLOCK_EN);
501
502 AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
503 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0);
504
505 ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR);
506 ath5k_hw_reg_write(ah, AR5K_PHY_SLMT_32MHZ, AR5K_PHY_SLMT);
507
508 if (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))
509 scal = AR5K_PHY_SCAL_32MHZ_2417;
510 else if (ee->ee_is_hb63)
511 scal = AR5K_PHY_SCAL_32MHZ_HB63;
512 else
513 scal = AR5K_PHY_SCAL_32MHZ;
514 ath5k_hw_reg_write(ah, scal, AR5K_PHY_SCAL);
515
516 ath5k_hw_reg_write(ah, AR5K_PHY_SCLOCK_32MHZ, AR5K_PHY_SCLOCK);
517 ath5k_hw_reg_write(ah, AR5K_PHY_SDELAY_32MHZ, AR5K_PHY_SDELAY);
518
519 if ((ah->ah_radio == AR5K_RF5112) ||
520 (ah->ah_radio == AR5K_RF5413) ||
521 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
522 spending = 0x14;
523 else
524 spending = 0x18;
525 ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING);
526
527 if ((ah->ah_radio == AR5K_RF5112) ||
528 (ah->ah_radio == AR5K_RF5413))
529 usec32 = 39;
530 else
531 usec32 = 31;
532 AR5K_REG_WRITE_BITS(ah, AR5K_USEC_5211, AR5K_USEC_32, usec32);
533
534 AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 1);
535 }
536 return;
537 }
538
539 /* TODO: Half/Quarter rate */
540 static void ath5k_hw_tweak_initval_settings(struct ath5k_hw *ah,
541 struct ieee80211_channel *channel)
542 {
543 if (ah->ah_version == AR5K_AR5212 &&
544 ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
545
546 /* Setup ADC control */
547 ath5k_hw_reg_write(ah,
548 (AR5K_REG_SM(2,
549 AR5K_PHY_ADC_CTL_INBUFGAIN_OFF) |
550 AR5K_REG_SM(2,
551 AR5K_PHY_ADC_CTL_INBUFGAIN_ON) |
552 AR5K_PHY_ADC_CTL_PWD_DAC_OFF |
553 AR5K_PHY_ADC_CTL_PWD_ADC_OFF),
554 AR5K_PHY_ADC_CTL);
555
556
557
558 /* Disable barker RSSI threshold */
559 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_DAG_CCK_CTL,
560 AR5K_PHY_DAG_CCK_CTL_EN_RSSI_THR);
561
562 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DAG_CCK_CTL,
563 AR5K_PHY_DAG_CCK_CTL_RSSI_THR, 2);
564
565 /* Set the mute mask */
566 ath5k_hw_reg_write(ah, 0x0000000f, AR5K_SEQ_MASK);
567 }
568
569 /* Clear PHY_BLUETOOTH to allow RX_CLEAR line debug */
570 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212B)
571 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BLUETOOTH);
572
573 /* Enable DCU double buffering */
574 if (ah->ah_phy_revision > AR5K_SREV_PHY_5212B)
575 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
576 AR5K_TXCFG_DCU_DBL_BUF_DIS);
577
578 /* Set DAC/ADC delays */
579 if (ah->ah_version == AR5K_AR5212) {
580 u32 scal;
581 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
582 if (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))
583 scal = AR5K_PHY_SCAL_32MHZ_2417;
584 else if (ee->ee_is_hb63)
585 scal = AR5K_PHY_SCAL_32MHZ_HB63;
586 else
587 scal = AR5K_PHY_SCAL_32MHZ;
588 ath5k_hw_reg_write(ah, scal, AR5K_PHY_SCAL);
589 }
590
591 /* Set fast ADC */
592 if ((ah->ah_radio == AR5K_RF5413) ||
593 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) {
594 u32 fast_adc = true;
595
596 if (channel->center_freq == 2462 ||
597 channel->center_freq == 2467)
598 fast_adc = 0;
599
600 /* Only update if needed */
601 if (ath5k_hw_reg_read(ah, AR5K_PHY_FAST_ADC) != fast_adc)
602 ath5k_hw_reg_write(ah, fast_adc,
603 AR5K_PHY_FAST_ADC);
604 }
605
606 /* Fix for first revision of the RF5112 RF chipset */
607 if (ah->ah_radio == AR5K_RF5112 &&
608 ah->ah_radio_5ghz_revision <
609 AR5K_SREV_RAD_5112A) {
610 u32 data;
611 ath5k_hw_reg_write(ah, AR5K_PHY_CCKTXCTL_WORLD,
612 AR5K_PHY_CCKTXCTL);
613 if (channel->hw_value & CHANNEL_5GHZ)
614 data = 0xffb81020;
615 else
616 data = 0xffb80d20;
617 ath5k_hw_reg_write(ah, data, AR5K_PHY_FRAME_CTL);
618 }
619
620 if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
621 u32 usec_reg;
622 /* 5311 has different tx/rx latency masks
623 * from 5211, since we deal 5311 the same
624 * as 5211 when setting initvals, shift
625 * values here to their proper locations */
626 usec_reg = ath5k_hw_reg_read(ah, AR5K_USEC_5211);
627 ath5k_hw_reg_write(ah, usec_reg & (AR5K_USEC_1 |
628 AR5K_USEC_32 |
629 AR5K_USEC_TX_LATENCY_5211 |
630 AR5K_REG_SM(29,
631 AR5K_USEC_RX_LATENCY_5210)),
632 AR5K_USEC_5211);
633 /* Clear QCU/DCU clock gating register */
634 ath5k_hw_reg_write(ah, 0, AR5K_QCUDCU_CLKGT);
635 /* Set DAC/ADC delays */
636 ath5k_hw_reg_write(ah, 0x08, AR5K_PHY_SCAL);
637 /* Enable PCU FIFO corruption ECO */
638 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5211,
639 AR5K_DIAG_SW_ECO_ENABLE);
640 }
641 }
642
643 static void ath5k_hw_commit_eeprom_settings(struct ath5k_hw *ah,
644 struct ieee80211_channel *channel, u8 *ant, u8 ee_mode)
645 {
646 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
647 s16 cck_ofdm_pwr_delta;
648
649 /* Adjust power delta for channel 14 */
650 if (channel->center_freq == 2484)
651 cck_ofdm_pwr_delta =
652 ((ee->ee_cck_ofdm_power_delta -
653 ee->ee_scaled_cck_delta) * 2) / 10;
654 else
655 cck_ofdm_pwr_delta =
656 (ee->ee_cck_ofdm_power_delta * 2) / 10;
657
658 /* Set CCK to OFDM power delta on tx power
659 * adjustment register */
660 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
661 if (channel->hw_value == CHANNEL_G)
662 ath5k_hw_reg_write(ah,
663 AR5K_REG_SM((ee->ee_cck_ofdm_gain_delta * -1),
664 AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA) |
665 AR5K_REG_SM((cck_ofdm_pwr_delta * -1),
666 AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX),
667 AR5K_PHY_TX_PWR_ADJ);
668 else
669 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TX_PWR_ADJ);
670 } else {
671 /* For older revs we scale power on sw during tx power
672 * setup */
673 ah->ah_txpower.txp_cck_ofdm_pwr_delta = cck_ofdm_pwr_delta;
674 ah->ah_txpower.txp_cck_ofdm_gainf_delta =
675 ee->ee_cck_ofdm_gain_delta;
676 }
677
678 /* Set antenna idle switch table */
679 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_ANT_CTL,
680 AR5K_PHY_ANT_CTL_SWTABLE_IDLE,
681 (ah->ah_ant_ctl[ee_mode][0] |
682 AR5K_PHY_ANT_CTL_TXRX_EN));
683
684 /* Set antenna switch tables */
685 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant[0]],
686 AR5K_PHY_ANT_SWITCH_TABLE_0);
687 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant[1]],
688 AR5K_PHY_ANT_SWITCH_TABLE_1);
689
690 /* Noise floor threshold */
691 ath5k_hw_reg_write(ah,
692 AR5K_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode]),
693 AR5K_PHY_NFTHRES);
694
695 if ((channel->hw_value & CHANNEL_TURBO) &&
696 (ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_0)) {
697 /* Switch settling time (Turbo) */
698 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
699 AR5K_PHY_SETTLING_SWITCH,
700 ee->ee_switch_settling_turbo[ee_mode]);
701
702 /* Tx/Rx attenuation (Turbo) */
703 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN,
704 AR5K_PHY_GAIN_TXRX_ATTEN,
705 ee->ee_atn_tx_rx_turbo[ee_mode]);
706
707 /* ADC/PGA desired size (Turbo) */
708 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
709 AR5K_PHY_DESIRED_SIZE_ADC,
710 ee->ee_adc_desired_size_turbo[ee_mode]);
711
712 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
713 AR5K_PHY_DESIRED_SIZE_PGA,
714 ee->ee_pga_desired_size_turbo[ee_mode]);
715
716 /* Tx/Rx margin (Turbo) */
717 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ,
718 AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX,
719 ee->ee_margin_tx_rx_turbo[ee_mode]);
720
721 } else {
722 /* Switch settling time */
723 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
724 AR5K_PHY_SETTLING_SWITCH,
725 ee->ee_switch_settling[ee_mode]);
726
727 /* Tx/Rx attenuation */
728 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN,
729 AR5K_PHY_GAIN_TXRX_ATTEN,
730 ee->ee_atn_tx_rx[ee_mode]);
731
732 /* ADC/PGA desired size */
733 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
734 AR5K_PHY_DESIRED_SIZE_ADC,
735 ee->ee_adc_desired_size[ee_mode]);
736
737 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
738 AR5K_PHY_DESIRED_SIZE_PGA,
739 ee->ee_pga_desired_size[ee_mode]);
740
741 /* Tx/Rx margin */
742 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
743 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ,
744 AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX,
745 ee->ee_margin_tx_rx[ee_mode]);
746 }
747
748 /* XPA delays */
749 ath5k_hw_reg_write(ah,
750 (ee->ee_tx_end2xpa_disable[ee_mode] << 24) |
751 (ee->ee_tx_end2xpa_disable[ee_mode] << 16) |
752 (ee->ee_tx_frm2xpa_enable[ee_mode] << 8) |
753 (ee->ee_tx_frm2xpa_enable[ee_mode]), AR5K_PHY_RF_CTL4);
754
755 /* XLNA delay */
756 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RF_CTL3,
757 AR5K_PHY_RF_CTL3_TXE2XLNA_ON,
758 ee->ee_tx_end2xlna_enable[ee_mode]);
759
760 /* Thresh64 (ANI) */
761 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_NF,
762 AR5K_PHY_NF_THRESH62,
763 ee->ee_thr_62[ee_mode]);
764
765
766 /* False detect backoff for channels
767 * that have spur noise. Write the new
768 * cyclic power RSSI threshold. */
769 if (ath5k_hw_chan_has_spur_noise(ah, channel))
770 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR,
771 AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1,
772 AR5K_INIT_CYCRSSI_THR1 +
773 ee->ee_false_detect[ee_mode]);
774 else
775 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR,
776 AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1,
777 AR5K_INIT_CYCRSSI_THR1);
778
779 /* I/Q correction
780 * TODO: Per channel i/q infos ? */
781 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
782 AR5K_PHY_IQ_CORR_ENABLE |
783 (ee->ee_i_cal[ee_mode] << AR5K_PHY_IQ_CORR_Q_I_COFF_S) |
784 ee->ee_q_cal[ee_mode]);
785
786 /* Heavy clipping -disable for now */
787 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_1)
788 ath5k_hw_reg_write(ah, 0, AR5K_PHY_HEAVY_CLIP_ENABLE);
789
790 return;
791 }
792
793 /*
794 * Main reset function
795 */
796 int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
797 struct ieee80211_channel *channel, bool change_channel)
798 {
799 u32 s_seq[10], s_ant, s_led[3], staid1_flags, tsf_up, tsf_lo;
800 u32 phy_tst1;
801 u8 mode, freq, ee_mode, ant[2];
802 int i, ret;
803
804 ATH5K_TRACE(ah->ah_sc);
805
806 s_ant = 0;
807 ee_mode = 0;
808 staid1_flags = 0;
809 tsf_up = 0;
810 tsf_lo = 0;
811 freq = 0;
812 mode = 0;
813
814 /*
815 * Save some registers before a reset
816 */
817 /*DCU/Antenna selection not available on 5210*/
818 if (ah->ah_version != AR5K_AR5210) {
819
820 switch (channel->hw_value & CHANNEL_MODES) {
821 case CHANNEL_A:
822 mode = AR5K_MODE_11A;
823 freq = AR5K_INI_RFGAIN_5GHZ;
824 ee_mode = AR5K_EEPROM_MODE_11A;
825 break;
826 case CHANNEL_G:
827 mode = AR5K_MODE_11G;
828 freq = AR5K_INI_RFGAIN_2GHZ;
829 ee_mode = AR5K_EEPROM_MODE_11G;
830 break;
831 case CHANNEL_B:
832 mode = AR5K_MODE_11B;
833 freq = AR5K_INI_RFGAIN_2GHZ;
834 ee_mode = AR5K_EEPROM_MODE_11B;
835 break;
836 case CHANNEL_T:
837 mode = AR5K_MODE_11A_TURBO;
838 freq = AR5K_INI_RFGAIN_5GHZ;
839 ee_mode = AR5K_EEPROM_MODE_11A;
840 break;
841 case CHANNEL_TG:
842 if (ah->ah_version == AR5K_AR5211) {
843 ATH5K_ERR(ah->ah_sc,
844 "TurboG mode not available on 5211");
845 return -EINVAL;
846 }
847 mode = AR5K_MODE_11G_TURBO;
848 freq = AR5K_INI_RFGAIN_2GHZ;
849 ee_mode = AR5K_EEPROM_MODE_11G;
850 break;
851 case CHANNEL_XR:
852 if (ah->ah_version == AR5K_AR5211) {
853 ATH5K_ERR(ah->ah_sc,
854 "XR mode not available on 5211");
855 return -EINVAL;
856 }
857 mode = AR5K_MODE_XR;
858 freq = AR5K_INI_RFGAIN_5GHZ;
859 ee_mode = AR5K_EEPROM_MODE_11A;
860 break;
861 default:
862 ATH5K_ERR(ah->ah_sc,
863 "invalid channel: %d\n", channel->center_freq);
864 return -EINVAL;
865 }
866
867 if (change_channel) {
868 /*
869 * Save frame sequence count
870 * For revs. after Oahu, only save
871 * seq num for DCU 0 (Global seq num)
872 */
873 if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
874
875 for (i = 0; i < 10; i++)
876 s_seq[i] = ath5k_hw_reg_read(ah,
877 AR5K_QUEUE_DCU_SEQNUM(i));
878
879 } else {
880 s_seq[0] = ath5k_hw_reg_read(ah,
881 AR5K_QUEUE_DCU_SEQNUM(0));
882 }
883
884 /* TSF accelerates on AR5211 durring reset
885 * As a workaround save it here and restore
886 * it later so that it's back in time after
887 * reset. This way it'll get re-synced on the
888 * next beacon without breaking ad-hoc.
889 *
890 * On AR5212 TSF is almost preserved across a
891 * reset so it stays back in time anyway and
892 * we don't have to save/restore it.
893 *
894 * XXX: Since this breaks power saving we have
895 * to disable power saving until we receive the
896 * next beacon, so we can resync beacon timers */
897 if (ah->ah_version == AR5K_AR5211) {
898 tsf_up = ath5k_hw_reg_read(ah, AR5K_TSF_U32);
899 tsf_lo = ath5k_hw_reg_read(ah, AR5K_TSF_L32);
900 }
901 }
902
903 /* Save default antenna */
904 s_ant = ath5k_hw_reg_read(ah, AR5K_DEFAULT_ANTENNA);
905
906 if (ah->ah_version == AR5K_AR5212) {
907 /* Restore normal 32/40MHz clock operation
908 * to avoid register access delay on certain
909 * PHY registers */
910 ath5k_hw_set_sleep_clock(ah, false);
911
912 /* Since we are going to write rf buffer
913 * check if we have any pending gain_F
914 * optimization settings */
915 if (change_channel && ah->ah_rf_banks != NULL)
916 ath5k_hw_gainf_calibrate(ah);
917 }
918 }
919
920 /*GPIOs*/
921 s_led[0] = ath5k_hw_reg_read(ah, AR5K_PCICFG) &
922 AR5K_PCICFG_LEDSTATE;
923 s_led[1] = ath5k_hw_reg_read(ah, AR5K_GPIOCR);
924 s_led[2] = ath5k_hw_reg_read(ah, AR5K_GPIODO);
925
926 /* AR5K_STA_ID1 flags, only preserve antenna
927 * settings and ack/cts rate mode */
928 staid1_flags = ath5k_hw_reg_read(ah, AR5K_STA_ID1) &
929 (AR5K_STA_ID1_DEFAULT_ANTENNA |
930 AR5K_STA_ID1_DESC_ANTENNA |
931 AR5K_STA_ID1_RTS_DEF_ANTENNA |
932 AR5K_STA_ID1_ACKCTS_6MB |
933 AR5K_STA_ID1_BASE_RATE_11B |
934 AR5K_STA_ID1_SELFGEN_DEF_ANT);
935
936 /* Wakeup the device */
937 ret = ath5k_hw_nic_wakeup(ah, channel->hw_value, false);
938 if (ret)
939 return ret;
940
941 /*
942 * Initialize operating mode
943 */
944 ah->ah_op_mode = op_mode;
945
946 /* PHY access enable */
947 if (ah->ah_mac_srev >= AR5K_SREV_AR5211)
948 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
949 else
950 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ | 0x40,
951 AR5K_PHY(0));
952
953 /* Write initial settings */
954 ret = ath5k_hw_write_initvals(ah, mode, change_channel);
955 if (ret)
956 return ret;
957
958 /*
959 * 5211/5212 Specific
960 */
961 if (ah->ah_version != AR5K_AR5210) {
962
963 /*
964 * Write initial RF gain settings
965 * This should work for both 5111/5112
966 */
967 ret = ath5k_hw_rfgain_init(ah, freq);
968 if (ret)
969 return ret;
970
971 mdelay(1);
972
973 /*
974 * Tweak initval settings for revised
975 * chipsets and add some more config
976 * bits
977 */
978 ath5k_hw_tweak_initval_settings(ah, channel);
979
980 /*
981 * Set TX power
982 */
983 ret = ath5k_hw_txpower(ah, channel, ee_mode,
984 ah->ah_txpower.txp_max_pwr / 2);
985 if (ret)
986 return ret;
987
988 /* Write rate duration table only on AR5212 and if
989 * virtual interface has already been brought up
990 * XXX: rethink this after new mode changes to
991 * mac80211 are integrated */
992 if (ah->ah_version == AR5K_AR5212 &&
993 ah->ah_sc->vif != NULL)
994 ath5k_hw_write_rate_duration(ah, mode);
995
996 /*
997 * Write RF buffer
998 */
999 ret = ath5k_hw_rfregs_init(ah, channel, mode);
1000 if (ret)
1001 return ret;
1002
1003
1004 /* Write OFDM timings on 5212*/
1005 if (ah->ah_version == AR5K_AR5212 &&
1006 channel->hw_value & CHANNEL_OFDM) {
1007 struct ath5k_eeprom_info *ee =
1008 &ah->ah_capabilities.cap_eeprom;
1009
1010 ret = ath5k_hw_write_ofdm_timings(ah, channel);
1011 if (ret)
1012 return ret;
1013
1014 /* Note: According to docs we can have a newer
1015 * EEPROM on old hardware, so we need to verify
1016 * that our hardware is new enough to have spur
1017 * mitigation registers (delta phase etc) */
1018 if (ah->ah_mac_srev >= AR5K_SREV_AR5424 ||
1019 (ah->ah_mac_srev >= AR5K_SREV_AR5424 &&
1020 ee->ee_version >= AR5K_EEPROM_VERSION_5_3))
1021 ath5k_hw_set_spur_mitigation_filter(ah,
1022 channel);
1023 }
1024
1025 /*Enable/disable 802.11b mode on 5111
1026 (enable 2111 frequency converter + CCK)*/
1027 if (ah->ah_radio == AR5K_RF5111) {
1028 if (mode == AR5K_MODE_11B)
1029 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG,
1030 AR5K_TXCFG_B_MODE);
1031 else
1032 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
1033 AR5K_TXCFG_B_MODE);
1034 }
1035
1036 /*
1037 * In case a fixed antenna was set as default
1038 * use the same switch table twice.
1039 */
1040 if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_A)
1041 ant[0] = ant[1] = AR5K_ANT_SWTABLE_A;
1042 else if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_B)
1043 ant[0] = ant[1] = AR5K_ANT_SWTABLE_B;
1044 else {
1045 ant[0] = AR5K_ANT_SWTABLE_A;
1046 ant[1] = AR5K_ANT_SWTABLE_B;
1047 }
1048
1049 /* Commit values from EEPROM */
1050 ath5k_hw_commit_eeprom_settings(ah, channel, ant, ee_mode);
1051
1052 } else {
1053 /*
1054 * For 5210 we do all initialization using
1055 * initvals, so we don't have to modify
1056 * any settings (5210 also only supports
1057 * a/aturbo modes)
1058 */
1059 mdelay(1);
1060 /* Disable phy and wait */
1061 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
1062 mdelay(1);
1063 }
1064
1065 /*
1066 * Restore saved values
1067 */
1068
1069 /*DCU/Antenna selection not available on 5210*/
1070 if (ah->ah_version != AR5K_AR5210) {
1071
1072 if (change_channel) {
1073 if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
1074 for (i = 0; i < 10; i++)
1075 ath5k_hw_reg_write(ah, s_seq[i],
1076 AR5K_QUEUE_DCU_SEQNUM(i));
1077 } else {
1078 ath5k_hw_reg_write(ah, s_seq[0],
1079 AR5K_QUEUE_DCU_SEQNUM(0));
1080 }
1081
1082
1083 if (ah->ah_version == AR5K_AR5211) {
1084 ath5k_hw_reg_write(ah, tsf_up, AR5K_TSF_U32);
1085 ath5k_hw_reg_write(ah, tsf_lo, AR5K_TSF_L32);
1086 }
1087 }
1088
1089 ath5k_hw_reg_write(ah, s_ant, AR5K_DEFAULT_ANTENNA);
1090 }
1091
1092 /* Ledstate */
1093 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, s_led[0]);
1094
1095 /* Gpio settings */
1096 ath5k_hw_reg_write(ah, s_led[1], AR5K_GPIOCR);
1097 ath5k_hw_reg_write(ah, s_led[2], AR5K_GPIODO);
1098
1099 /* Restore sta_id flags and preserve our mac address*/
1100 ath5k_hw_reg_write(ah, AR5K_LOW_ID(ah->ah_sta_id),
1101 AR5K_STA_ID0);
1102 ath5k_hw_reg_write(ah, staid1_flags | AR5K_HIGH_ID(ah->ah_sta_id),
1103 AR5K_STA_ID1);
1104
1105
1106 /*
1107 * Configure PCU
1108 */
1109
1110 /* Restore bssid and bssid mask */
1111 /* XXX: add ah->aid once mac80211 gives this to us */
1112 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
1113
1114 /* Set PCU config */
1115 ath5k_hw_set_opmode(ah);
1116
1117 /* Clear any pending interrupts
1118 * PISR/SISR Not available on 5210 */
1119 if (ah->ah_version != AR5K_AR5210)
1120 ath5k_hw_reg_write(ah, 0xffffffff, AR5K_PISR);
1121
1122 /* Set RSSI/BRSSI thresholds
1123 *
1124 * Note: If we decide to set this value
1125 * dynamicaly, have in mind that when AR5K_RSSI_THR
1126 * register is read it might return 0x40 if we haven't
1127 * wrote anything to it plus BMISS RSSI threshold is zeroed.
1128 * So doing a save/restore procedure here isn't the right
1129 * choice. Instead store it on ath5k_hw */
1130 ath5k_hw_reg_write(ah, (AR5K_TUNE_RSSI_THRES |
1131 AR5K_TUNE_BMISS_THRES <<
1132 AR5K_RSSI_THR_BMISS_S),
1133 AR5K_RSSI_THR);
1134
1135 /* MIC QoS support */
1136 if (ah->ah_mac_srev >= AR5K_SREV_AR2413) {
1137 ath5k_hw_reg_write(ah, 0x000100aa, AR5K_MIC_QOS_CTL);
1138 ath5k_hw_reg_write(ah, 0x00003210, AR5K_MIC_QOS_SEL);
1139 }
1140
1141 /* QoS NOACK Policy */
1142 if (ah->ah_version == AR5K_AR5212) {
1143 ath5k_hw_reg_write(ah,
1144 AR5K_REG_SM(2, AR5K_QOS_NOACK_2BIT_VALUES) |
1145 AR5K_REG_SM(5, AR5K_QOS_NOACK_BIT_OFFSET) |
1146 AR5K_REG_SM(0, AR5K_QOS_NOACK_BYTE_OFFSET),
1147 AR5K_QOS_NOACK);
1148 }
1149
1150
1151 /*
1152 * Configure PHY
1153 */
1154
1155 /* Set channel on PHY */
1156 ret = ath5k_hw_channel(ah, channel);
1157 if (ret)
1158 return ret;
1159
1160 /*
1161 * Enable the PHY and wait until completion
1162 * This includes BaseBand and Synthesizer
1163 * activation.
1164 */
1165 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
1166
1167 /*
1168 * On 5211+ read activation -> rx delay
1169 * and use it.
1170 *
1171 * TODO: Half/quarter rate support
1172 */
1173 if (ah->ah_version != AR5K_AR5210) {
1174 u32 delay;
1175 delay = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) &
1176 AR5K_PHY_RX_DELAY_M;
1177 delay = (channel->hw_value & CHANNEL_CCK) ?
1178 ((delay << 2) / 22) : (delay / 10);
1179
1180 udelay(100 + (2 * delay));
1181 } else {
1182 mdelay(1);
1183 }
1184
1185 /*
1186 * Perform ADC test to see if baseband is ready
1187 * Set tx hold and check adc test register
1188 */
1189 phy_tst1 = ath5k_hw_reg_read(ah, AR5K_PHY_TST1);
1190 ath5k_hw_reg_write(ah, AR5K_PHY_TST1_TXHOLD, AR5K_PHY_TST1);
1191 for (i = 0; i <= 20; i++) {
1192 if (!(ath5k_hw_reg_read(ah, AR5K_PHY_ADC_TEST) & 0x10))
1193 break;
1194 udelay(200);
1195 }
1196 ath5k_hw_reg_write(ah, phy_tst1, AR5K_PHY_TST1);
1197
1198 /*
1199 * Start automatic gain control calibration
1200 *
1201 * During AGC calibration RX path is re-routed to
1202 * a power detector so we don't receive anything.
1203 *
1204 * This method is used to calibrate some static offsets
1205 * used together with on-the fly I/Q calibration (the
1206 * one performed via ath5k_hw_phy_calibrate), that doesn't
1207 * interrupt rx path.
1208 *
1209 * While rx path is re-routed to the power detector we also
1210 * start a noise floor calibration, to measure the
1211 * card's noise floor (the noise we measure when we are not
1212 * transmiting or receiving anything).
1213 *
1214 * If we are in a noisy environment AGC calibration may time
1215 * out and/or noise floor calibration might timeout.
1216 */
1217 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1218 AR5K_PHY_AGCCTL_CAL);
1219
1220 /* At the same time start I/Q calibration for QAM constellation
1221 * -no need for CCK- */
1222 ah->ah_calibration = false;
1223 if (!(mode == AR5K_MODE_11B)) {
1224 ah->ah_calibration = true;
1225 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
1226 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
1227 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
1228 AR5K_PHY_IQ_RUN);
1229 }
1230
1231 /* Wait for gain calibration to finish (we check for I/Q calibration
1232 * during ath5k_phy_calibrate) */
1233 if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
1234 AR5K_PHY_AGCCTL_CAL, 0, false)) {
1235 ATH5K_ERR(ah->ah_sc, "gain calibration timeout (%uMHz)\n",
1236 channel->center_freq);
1237 }
1238
1239 /*
1240 * If we run NF calibration before AGC, it always times out.
1241 * Binary HAL starts NF and AGC calibration at the same time
1242 * and only waits for AGC to finish. Also if AGC or NF cal.
1243 * times out, reset doesn't fail on binary HAL. I believe
1244 * that's wrong because since rx path is routed to a detector,
1245 * if cal. doesn't finish we won't have RX. Sam's HAL for AR5210/5211
1246 * enables noise floor calibration after offset calibration and if noise
1247 * floor calibration fails, reset fails. I believe that's
1248 * a better approach, we just need to find a polling interval
1249 * that suits best, even if reset continues we need to make
1250 * sure that rx path is ready.
1251 */
1252 ath5k_hw_noise_floor_calibration(ah, channel->center_freq);
1253
1254 /* Restore antenna mode */
1255 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode);
1256
1257 /*
1258 * Configure QCUs/DCUs
1259 */
1260
1261 /* TODO: HW Compression support for data queues */
1262 /* TODO: Burst prefetch for data queues */
1263
1264 /*
1265 * Reset queues and start beacon timers at the end of the reset routine
1266 * This also sets QCU mask on each DCU for 1:1 qcu to dcu mapping
1267 * Note: If we want we can assign multiple qcus on one dcu.
1268 */
1269 for (i = 0; i < ah->ah_capabilities.cap_queues.q_tx_num; i++) {
1270 ret = ath5k_hw_reset_tx_queue(ah, i);
1271 if (ret) {
1272 ATH5K_ERR(ah->ah_sc,
1273 "failed to reset TX queue #%d\n", i);
1274 return ret;
1275 }
1276 }
1277
1278
1279 /*
1280 * Configure DMA/Interrupts
1281 */
1282
1283 /*
1284 * Set Rx/Tx DMA Configuration
1285 *
1286 * Set standard DMA size (128). Note that
1287 * a DMA size of 512 causes rx overruns and tx errors
1288 * on pci-e cards (tested on 5424 but since rx overruns
1289 * also occur on 5416/5418 with madwifi we set 128
1290 * for all PCI-E cards to be safe).
1291 *
1292 * XXX: need to check 5210 for this
1293 * TODO: Check out tx triger level, it's always 64 on dumps but I
1294 * guess we can tweak it and see how it goes ;-)
1295 */
1296 if (ah->ah_version != AR5K_AR5210) {
1297 AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG,
1298 AR5K_TXCFG_SDMAMR, AR5K_DMASIZE_128B);
1299 AR5K_REG_WRITE_BITS(ah, AR5K_RXCFG,
1300 AR5K_RXCFG_SDMAMW, AR5K_DMASIZE_128B);
1301 }
1302
1303 /* Pre-enable interrupts on 5211/5212*/
1304 if (ah->ah_version != AR5K_AR5210)
1305 ath5k_hw_set_imr(ah, ah->ah_imr);
1306
1307 /* Enable 32KHz clock function for AR5212+ chips
1308 * Set clocks to 32KHz operation and use an
1309 * external 32KHz crystal when sleeping if one
1310 * exists */
1311 if (ah->ah_version == AR5K_AR5212)
1312 ath5k_hw_set_sleep_clock(ah, true);
1313
1314 /*
1315 * Disable beacons and reset the register
1316 */
1317 AR5K_REG_DISABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_ENABLE |
1318 AR5K_BEACON_RESET_TSF);
1319
1320 return 0;
1321 }
1322
1323 #undef _ATH5K_RESET
Linux kernel - Deliverables
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