drivers/net/wireless/ath/ath6kl/hif.c

   1 /*
   2  * Copyright (c) 2007-2011 Atheros Communications Inc.
   3  * Copyright (c) 2011-2012 Qualcomm Atheros, Inc.
   4  *
   5  * Permission to use, copy, modify, and/or distribute this software for any
   6  * purpose with or without fee is hereby granted, provided that the above
   7  * copyright notice and this permission notice appear in all copies.
   8  *
   9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16  */
  17 #include "hif.h"
  18
  19 #include <linux/export.h>
  20
  21 #include "core.h"
  22 #include "target.h"
  23 #include "hif-ops.h"
  24 #include "debug.h"
  25
  26 #define MAILBOX_FOR_BLOCK_SIZE          1
  27
  28 #define ATH6KL_TIME_QUANTUM     10  /* in ms */
  29
  30 static int ath6kl_hif_cp_scat_dma_buf(struct hif_scatter_req *req,
  31                                       bool from_dma)
  32 {
  33         u8 *buf;
  34         int i;
  35
  36         buf = req->virt_dma_buf;
  37
  38         for (i = 0; i < req->scat_entries; i++) {
  39
  40                 if (from_dma)
  41                         memcpy(req->scat_list[i].buf, buf,
  42                                req->scat_list[i].len);
  43                 else
  44                         memcpy(buf, req->scat_list[i].buf,
  45                                req->scat_list[i].len);
  46
  47                 buf += req->scat_list[i].len;
  48         }
  49
  50         return 0;
  51 }
  52
  53 int ath6kl_hif_rw_comp_handler(void *context, int status)
  54 {
  55         struct htc_packet *packet = context;
  56
  57         ath6kl_dbg(ATH6KL_DBG_HIF, "hif rw completion pkt 0x%p status %d\n",
  58                    packet, status);
  59
  60         packet->status = status;
  61         packet->completion(packet->context, packet);
  62
  63         return 0;
  64 }
  65 EXPORT_SYMBOL(ath6kl_hif_rw_comp_handler);
  66
  67 #define REG_DUMP_COUNT_AR6003   60
  68 #define REGISTER_DUMP_LEN_MAX   60
  69
  70 static void ath6kl_hif_dump_fw_crash(struct ath6kl *ar)
  71 {
  72         __le32 regdump_val[REGISTER_DUMP_LEN_MAX];
  73         u32 i, address, regdump_addr = 0;
  74         int ret;
  75
  76         if (ar->target_type != TARGET_TYPE_AR6003)
  77                 return;
  78
  79         /* the reg dump pointer is copied to the host interest area */
  80         address = ath6kl_get_hi_item_addr(ar, HI_ITEM(hi_failure_state));
  81         address = TARG_VTOP(ar->target_type, address);
  82
  83         /* read RAM location through diagnostic window */
  84         ret = ath6kl_diag_read32(ar, address, &regdump_addr);
  85
  86         if (ret || !regdump_addr) {
  87                 ath6kl_warn("failed to get ptr to register dump area: %d\n",
  88                             ret);
  89                 return;
  90         }
  91
  92         ath6kl_dbg(ATH6KL_DBG_IRQ, "register dump data address 0x%x\n",
  93                 regdump_addr);
  94         regdump_addr = TARG_VTOP(ar->target_type, regdump_addr);
  95
  96         /* fetch register dump data */
  97         ret = ath6kl_diag_read(ar, regdump_addr, (u8 *)&regdump_val[0],
  98                                   REG_DUMP_COUNT_AR6003 * (sizeof(u32)));
  99         if (ret) {
 100                 ath6kl_warn("failed to get register dump: %d\n", ret);
 101                 return;
 102         }
 103
 104         ath6kl_info("crash dump:\n");
 105         ath6kl_info("hw 0x%x fw %s\n", ar->wiphy->hw_version,
 106                     ar->wiphy->fw_version);
 107
 108         BUILD_BUG_ON(REG_DUMP_COUNT_AR6003 % 4);
 109
 110         for (i = 0; i < REG_DUMP_COUNT_AR6003 / 4; i++) {
 111                 ath6kl_info("%d: 0x%8.8x 0x%8.8x 0x%8.8x 0x%8.8x\n",
 112                             4 * i,
 113                             le32_to_cpu(regdump_val[i]),
 114                             le32_to_cpu(regdump_val[i + 1]),
 115                             le32_to_cpu(regdump_val[i + 2]),
 116                             le32_to_cpu(regdump_val[i + 3]));
 117         }
 118
 119 }
 120
 121 static int ath6kl_hif_proc_dbg_intr(struct ath6kl_device *dev)
 122 {
 123         u32 dummy;
 124         int ret;
 125
 126         ath6kl_warn("firmware crashed\n");
 127
 128         /*
 129          * read counter to clear the interrupt, the debug error interrupt is
 130          * counter 0.
 131          */
 132         ret = hif_read_write_sync(dev->ar, COUNT_DEC_ADDRESS,
 133                                      (u8 *)&dummy, 4, HIF_RD_SYNC_BYTE_INC);
 134         if (ret)
 135                 ath6kl_warn("Failed to clear debug interrupt: %d\n", ret);
 136
 137         ath6kl_hif_dump_fw_crash(dev->ar);
 138
 139         return ret;
 140 }
 141
 142 /* mailbox recv message polling */
 143 int ath6kl_hif_poll_mboxmsg_rx(struct ath6kl_device *dev, u32 *lk_ahd,
 144                               int timeout)
 145 {
 146         struct ath6kl_irq_proc_registers *rg;
 147         int status = 0, i;
 148         u8 htc_mbox = 1 << HTC_MAILBOX;
 149
 150         for (i = timeout / ATH6KL_TIME_QUANTUM; i > 0; i--) {
 151                 /* this is the standard HIF way, load the reg table */
 152                 status = hif_read_write_sync(dev->ar, HOST_INT_STATUS_ADDRESS,
 153                                              (u8 *) &dev->irq_proc_reg,
 154                                              sizeof(dev->irq_proc_reg),
 155                                              HIF_RD_SYNC_BYTE_INC);
 156
 157                 if (status) {
 158                         ath6kl_err("failed to read reg table\n");
 159                         return status;
 160                 }
 161
 162                 /* check for MBOX data and valid lookahead */
 163                 if (dev->irq_proc_reg.host_int_status & htc_mbox) {
 164                         if (dev->irq_proc_reg.rx_lkahd_valid &
 165                             htc_mbox) {
 166                                 /*
 167                                  * Mailbox has a message and the look ahead
 168                                  * is valid.
 169                                  */
 170                                 rg = &dev->irq_proc_reg;
 171                                 *lk_ahd =
 172                                         le32_to_cpu(rg->rx_lkahd[HTC_MAILBOX]);
 173                                 break;
 174                         }
 175                 }
 176
 177                 /* delay a little  */
 178                 mdelay(ATH6KL_TIME_QUANTUM);
 179                 ath6kl_dbg(ATH6KL_DBG_HIF, "hif retry mbox poll try %d\n", i);
 180         }
 181
 182         if (i == 0) {
 183                 ath6kl_err("timeout waiting for recv message\n");
 184                 status = -ETIME;
 185                 /* check if the target asserted */
 186                 if (dev->irq_proc_reg.counter_int_status &
 187                     ATH6KL_TARGET_DEBUG_INTR_MASK)
 188                         /*
 189                          * Target failure handler will be called in case of
 190                          * an assert.
 191                          */
 192                         ath6kl_hif_proc_dbg_intr(dev);
 193         }
 194
 195         return status;
 196 }
 197
 198 /*
 199  * Disable packet reception (used in case the host runs out of buffers)
 200  * using the interrupt enable registers through the host I/F
 201  */
 202 int ath6kl_hif_rx_control(struct ath6kl_device *dev, bool enable_rx)
 203 {
 204         struct ath6kl_irq_enable_reg regs;
 205         int status = 0;
 206
 207         ath6kl_dbg(ATH6KL_DBG_HIF, "hif rx %s\n",
 208                    enable_rx ? "enable" : "disable");
 209
 210         /* take the lock to protect interrupt enable shadows */
 211         spin_lock_bh(&dev->lock);
 212
 213         if (enable_rx)
 214                 dev->irq_en_reg.int_status_en |=
 215                         SM(INT_STATUS_ENABLE_MBOX_DATA, 0x01);
 216         else
 217                 dev->irq_en_reg.int_status_en &=
 218                     ~SM(INT_STATUS_ENABLE_MBOX_DATA, 0x01);
 219
 220         memcpy(&regs, &dev->irq_en_reg, sizeof(regs));
 221
 222         spin_unlock_bh(&dev->lock);
 223
 224         status = hif_read_write_sync(dev->ar, INT_STATUS_ENABLE_ADDRESS,
 225                                      &regs.int_status_en,
 226                                      sizeof(struct ath6kl_irq_enable_reg),
 227                                      HIF_WR_SYNC_BYTE_INC);
 228
 229         return status;
 230 }
 231
 232 int ath6kl_hif_submit_scat_req(struct ath6kl_device *dev,
 233                               struct hif_scatter_req *scat_req, bool read)
 234 {
 235         int status = 0;
 236
 237         if (read) {
 238                 scat_req->req = HIF_RD_SYNC_BLOCK_FIX;
 239                 scat_req->addr = dev->ar->mbox_info.htc_addr;
 240         } else {
 241                 scat_req->req = HIF_WR_ASYNC_BLOCK_INC;
 242
 243                 scat_req->addr =
 244                         (scat_req->len > HIF_MBOX_WIDTH) ?
 245                         dev->ar->mbox_info.htc_ext_addr :
 246                         dev->ar->mbox_info.htc_addr;
 247         }
 248
 249         ath6kl_dbg(ATH6KL_DBG_HIF,
 250                    "hif submit scatter request entries %d len %d mbox 0x%x %s %s\n",
 251                    scat_req->scat_entries, scat_req->len,
 252                    scat_req->addr, !read ? "async" : "sync",
 253                    (read) ? "rd" : "wr");
 254
 255         if (!read && scat_req->virt_scat) {
 256                 status = ath6kl_hif_cp_scat_dma_buf(scat_req, false);
 257                 if (status) {
 258                         scat_req->status = status;
 259                         scat_req->complete(dev->ar->htc_target, scat_req);
 260                         return 0;
 261                 }
 262         }
 263
 264         status = ath6kl_hif_scat_req_rw(dev->ar, scat_req);
 265
 266         if (read) {
 267                 /* in sync mode, we can touch the scatter request */
 268                 scat_req->status = status;
 269                 if (!status && scat_req->virt_scat)
 270                         scat_req->status =
 271                                 ath6kl_hif_cp_scat_dma_buf(scat_req, true);
 272         }
 273
 274         return status;
 275 }
 276
 277 static int ath6kl_hif_proc_counter_intr(struct ath6kl_device *dev)
 278 {
 279         u8 counter_int_status;
 280
 281         ath6kl_dbg(ATH6KL_DBG_IRQ, "counter interrupt\n");
 282
 283         counter_int_status = dev->irq_proc_reg.counter_int_status &
 284                              dev->irq_en_reg.cntr_int_status_en;
 285
 286         ath6kl_dbg(ATH6KL_DBG_IRQ,
 287                 "valid interrupt source(s) in COUNTER_INT_STATUS: 0x%x\n",
 288                 counter_int_status);
 289
 290         /*
 291          * NOTE: other modules like GMBOX may use the counter interrupt for
 292          * credit flow control on other counters, we only need to check for
 293          * the debug assertion counter interrupt.
 294          */
 295         if (counter_int_status & ATH6KL_TARGET_DEBUG_INTR_MASK)
 296                 return ath6kl_hif_proc_dbg_intr(dev);
 297
 298         return 0;
 299 }
 300
 301 static int ath6kl_hif_proc_err_intr(struct ath6kl_device *dev)
 302 {
 303         int status;
 304         u8 error_int_status;
 305         u8 reg_buf[4];
 306
 307         ath6kl_dbg(ATH6KL_DBG_IRQ, "error interrupt\n");
 308
 309         error_int_status = dev->irq_proc_reg.error_int_status & 0x0F;
 310         if (!error_int_status) {
 311                 WARN_ON(1);
 312                 return -EIO;
 313         }
 314
 315         ath6kl_dbg(ATH6KL_DBG_IRQ,
 316                    "valid interrupt source(s) in ERROR_INT_STATUS: 0x%x\n",
 317                    error_int_status);
 318
 319         if (MS(ERROR_INT_STATUS_WAKEUP, error_int_status))
 320                 ath6kl_dbg(ATH6KL_DBG_IRQ, "error : wakeup\n");
 321
 322         if (MS(ERROR_INT_STATUS_RX_UNDERFLOW, error_int_status))
 323                 ath6kl_err("rx underflow\n");
 324
 325         if (MS(ERROR_INT_STATUS_TX_OVERFLOW, error_int_status))
 326                 ath6kl_err("tx overflow\n");
 327
 328         /* Clear the interrupt */
 329         dev->irq_proc_reg.error_int_status &= ~error_int_status;
 330
 331         /* set W1C value to clear the interrupt, this hits the register first */
 332         reg_buf[0] = error_int_status;
 333         reg_buf[1] = 0;
 334         reg_buf[2] = 0;
 335         reg_buf[3] = 0;
 336
 337         status = hif_read_write_sync(dev->ar, ERROR_INT_STATUS_ADDRESS,
 338                                      reg_buf, 4, HIF_WR_SYNC_BYTE_FIX);
 339
 340         if (status)
 341                 WARN_ON(1);
 342
 343         return status;
 344 }
 345
 346 static int ath6kl_hif_proc_cpu_intr(struct ath6kl_device *dev)
 347 {
 348         int status;
 349         u8 cpu_int_status;
 350         u8 reg_buf[4];
 351
 352         ath6kl_dbg(ATH6KL_DBG_IRQ, "cpu interrupt\n");
 353
 354         cpu_int_status = dev->irq_proc_reg.cpu_int_status &
 355                          dev->irq_en_reg.cpu_int_status_en;
 356         if (!cpu_int_status) {
 357                 WARN_ON(1);
 358                 return -EIO;
 359         }
 360
 361         ath6kl_dbg(ATH6KL_DBG_IRQ,
 362                 "valid interrupt source(s) in CPU_INT_STATUS: 0x%x\n",
 363                 cpu_int_status);
 364
 365         /* Clear the interrupt */
 366         dev->irq_proc_reg.cpu_int_status &= ~cpu_int_status;
 367
 368         /*
 369          * Set up the register transfer buffer to hit the register 4 times ,
 370          * this is done to make the access 4-byte aligned to mitigate issues
 371          * with host bus interconnects that restrict bus transfer lengths to
 372          * be a multiple of 4-bytes.
 373          */
 374
 375         /* set W1C value to clear the interrupt, this hits the register first */
 376         reg_buf[0] = cpu_int_status;
 377         /* the remaining are set to zero which have no-effect  */
 378         reg_buf[1] = 0;
 379         reg_buf[2] = 0;
 380         reg_buf[3] = 0;
 381
 382         status = hif_read_write_sync(dev->ar, CPU_INT_STATUS_ADDRESS,
 383                                      reg_buf, 4, HIF_WR_SYNC_BYTE_FIX);
 384
 385         if (status)
 386                 WARN_ON(1);
 387
 388         return status;
 389 }
 390
 391 /* process pending interrupts synchronously */
 392 static int proc_pending_irqs(struct ath6kl_device *dev, bool *done)
 393 {
 394         struct ath6kl_irq_proc_registers *rg;
 395         int status = 0;
 396         u8 host_int_status = 0;
 397         u32 lk_ahd = 0;
 398         u8 htc_mbox = 1 << HTC_MAILBOX;
 399
 400         ath6kl_dbg(ATH6KL_DBG_IRQ, "proc_pending_irqs: (dev: 0x%p)\n", dev);
 401
 402         /*
 403          * NOTE: HIF implementation guarantees that the context of this
 404          * call allows us to perform SYNCHRONOUS I/O, that is we can block,
 405          * sleep or call any API that can block or switch thread/task
 406          * contexts. This is a fully schedulable context.
 407          */
 408
 409         /*
 410          * Process pending intr only when int_status_en is clear, it may
 411          * result in unnecessary bus transaction otherwise. Target may be
 412          * unresponsive at the time.
 413          */
 414         if (dev->irq_en_reg.int_status_en) {
 415                 /*
 416                  * Read the first 28 bytes of the HTC register table. This
 417                  * will yield us the value of different int status
 418                  * registers and the lookahead registers.
 419                  *
 420                  *    length = sizeof(int_status) + sizeof(cpu_int_status)
 421                  *             + sizeof(error_int_status) +
 422                  *             sizeof(counter_int_status) +
 423                  *             sizeof(mbox_frame) + sizeof(rx_lkahd_valid)
 424                  *             + sizeof(hole) + sizeof(rx_lkahd) +
 425                  *             sizeof(int_status_en) +
 426                  *             sizeof(cpu_int_status_en) +
 427                  *             sizeof(err_int_status_en) +
 428                  *             sizeof(cntr_int_status_en);
 429                  */
 430                 status = hif_read_write_sync(dev->ar, HOST_INT_STATUS_ADDRESS,
 431                                              (u8 *) &dev->irq_proc_reg,
 432                                              sizeof(dev->irq_proc_reg),
 433                                              HIF_RD_SYNC_BYTE_INC);
 434                 if (status)
 435                         goto out;
 436
 437                 ath6kl_dump_registers(dev, &dev->irq_proc_reg,
 438                                       &dev->irq_en_reg);
 439
 440                 /* Update only those registers that are enabled */
 441                 host_int_status = dev->irq_proc_reg.host_int_status &
 442                                   dev->irq_en_reg.int_status_en;
 443
 444                 /* Look at mbox status */
 445                 if (host_int_status & htc_mbox) {
 446                         /*
 447                          * Mask out pending mbox value, we use "lookAhead as
 448                          * the real flag for mbox processing.
 449                          */
 450                         host_int_status &= ~htc_mbox;
 451                         if (dev->irq_proc_reg.rx_lkahd_valid &
 452                             htc_mbox) {
 453                                 rg = &dev->irq_proc_reg;
 454                                 lk_ahd = le32_to_cpu(rg->rx_lkahd[HTC_MAILBOX]);
 455                                 if (!lk_ahd)
 456                                         ath6kl_err("lookAhead is zero!\n");
 457                         }
 458                 }
 459         }
 460
 461         if (!host_int_status && !lk_ahd) {
 462                 *done = true;
 463                 goto out;
 464         }
 465
 466         if (lk_ahd) {
 467                 int fetched = 0;
 468
 469                 ath6kl_dbg(ATH6KL_DBG_IRQ,
 470                            "pending mailbox msg, lk_ahd: 0x%X\n", lk_ahd);
 471                 /*
 472                  * Mailbox Interrupt, the HTC layer may issue async
 473                  * requests to empty the mailbox. When emptying the recv
 474                  * mailbox we use the async handler above called from the
 475                  * completion routine of the callers read request. This can
 476                  * improve performance by reducing context switching when
 477                  * we rapidly pull packets.
 478                  */
 479                 status = ath6kl_htc_rxmsg_pending_handler(dev->htc_cnxt,
 480                                                           lk_ahd, &fetched);
 481                 if (status)
 482                         goto out;
 483
 484                 if (!fetched)
 485                         /*
 486                          * HTC could not pull any messages out due to lack
 487                          * of resources.
 488                          */
 489                         dev->htc_cnxt->chk_irq_status_cnt = 0;
 490         }
 491
 492         /* now handle the rest of them */
 493         ath6kl_dbg(ATH6KL_DBG_IRQ,
 494                    "valid interrupt source(s) for other interrupts: 0x%x\n",
 495                    host_int_status);
 496
 497         if (MS(HOST_INT_STATUS_CPU, host_int_status)) {
 498                 /* CPU Interrupt */
 499                 status = ath6kl_hif_proc_cpu_intr(dev);
 500                 if (status)
 501                         goto out;
 502         }
 503
 504         if (MS(HOST_INT_STATUS_ERROR, host_int_status)) {
 505                 /* Error Interrupt */
 506                 status = ath6kl_hif_proc_err_intr(dev);
 507                 if (status)
 508                         goto out;
 509         }
 510
 511         if (MS(HOST_INT_STATUS_COUNTER, host_int_status))
 512                 /* Counter Interrupt */
 513                 status = ath6kl_hif_proc_counter_intr(dev);
 514
 515 out:
 516         /*
 517          * An optimization to bypass reading the IRQ status registers
 518          * unecessarily which can re-wake the target, if upper layers
 519          * determine that we are in a low-throughput mode, we can rely on
 520          * taking another interrupt rather than re-checking the status
 521          * registers which can re-wake the target.
 522          *
 523          * NOTE : for host interfaces that makes use of detecting pending
 524          * mbox messages at hif can not use this optimization due to
 525          * possible side effects, SPI requires the host to drain all
 526          * messages from the mailbox before exiting the ISR routine.
 527          */
 528
 529         ath6kl_dbg(ATH6KL_DBG_IRQ,
 530                    "bypassing irq status re-check, forcing done\n");
 531
 532         if (!dev->htc_cnxt->chk_irq_status_cnt)
 533                 *done = true;
 534
 535         ath6kl_dbg(ATH6KL_DBG_IRQ,
 536                    "proc_pending_irqs: (done:%d, status=%d\n", *done, status);
 537
 538         return status;
 539 }
 540
 541 /* interrupt handler, kicks off all interrupt processing */
 542 int ath6kl_hif_intr_bh_handler(struct ath6kl *ar)
 543 {
 544         struct ath6kl_device *dev = ar->htc_target->dev;
 545         unsigned long timeout;
 546         int status = 0;
 547         bool done = false;
 548
 549         /*
 550          * Reset counter used to flag a re-scan of IRQ status registers on
 551          * the target.
 552          */
 553         dev->htc_cnxt->chk_irq_status_cnt = 0;
 554
 555         /*
 556          * IRQ processing is synchronous, interrupt status registers can be
 557          * re-read.
 558          */
 559         timeout = jiffies + msecs_to_jiffies(ATH6KL_HIF_COMMUNICATION_TIMEOUT);
 560         while (time_before(jiffies, timeout) && !done) {
 561                 status = proc_pending_irqs(dev, &done);
 562                 if (status)
 563                         break;
 564         }
 565
 566         return status;
 567 }
 568 EXPORT_SYMBOL(ath6kl_hif_intr_bh_handler);
 569
 570 static int ath6kl_hif_enable_intrs(struct ath6kl_device *dev)
 571 {
 572         struct ath6kl_irq_enable_reg regs;
 573         int status;
 574
 575         spin_lock_bh(&dev->lock);
 576
 577         /* Enable all but ATH6KL CPU interrupts */
 578         dev->irq_en_reg.int_status_en =
 579                         SM(INT_STATUS_ENABLE_ERROR, 0x01) |
 580                         SM(INT_STATUS_ENABLE_CPU, 0x01) |
 581                         SM(INT_STATUS_ENABLE_COUNTER, 0x01);
 582
 583         /*
 584          * NOTE: There are some cases where HIF can do detection of
 585          * pending mbox messages which is disabled now.
 586          */
 587         dev->irq_en_reg.int_status_en |= SM(INT_STATUS_ENABLE_MBOX_DATA, 0x01);
 588
 589         /* Set up the CPU Interrupt status Register */
 590         dev->irq_en_reg.cpu_int_status_en = 0;
 591
 592         /* Set up the Error Interrupt status Register */
 593         dev->irq_en_reg.err_int_status_en =
 594                 SM(ERROR_STATUS_ENABLE_RX_UNDERFLOW, 0x01) |
 595                 SM(ERROR_STATUS_ENABLE_TX_OVERFLOW, 0x1);
 596
 597         /*
 598          * Enable Counter interrupt status register to get fatal errors for
 599          * debugging.
 600          */
 601         dev->irq_en_reg.cntr_int_status_en = SM(COUNTER_INT_STATUS_ENABLE_BIT,
 602                                                 ATH6KL_TARGET_DEBUG_INTR_MASK);
 603         memcpy(&regs, &dev->irq_en_reg, sizeof(regs));
 604
 605         spin_unlock_bh(&dev->lock);
 606
 607         status = hif_read_write_sync(dev->ar, INT_STATUS_ENABLE_ADDRESS,
 608                                      &regs.int_status_en, sizeof(regs),
 609                                      HIF_WR_SYNC_BYTE_INC);
 610
 611         if (status)
 612                 ath6kl_err("failed to update interrupt ctl reg err: %d\n",
 613                            status);
 614
 615         return status;
 616 }
 617
 618 int ath6kl_hif_disable_intrs(struct ath6kl_device *dev)
 619 {
 620         struct ath6kl_irq_enable_reg regs;
 621
 622         spin_lock_bh(&dev->lock);
 623         /* Disable all interrupts */
 624         dev->irq_en_reg.int_status_en = 0;
 625         dev->irq_en_reg.cpu_int_status_en = 0;
 626         dev->irq_en_reg.err_int_status_en = 0;
 627         dev->irq_en_reg.cntr_int_status_en = 0;
 628         memcpy(&regs, &dev->irq_en_reg, sizeof(regs));
 629         spin_unlock_bh(&dev->lock);
 630
 631         return hif_read_write_sync(dev->ar, INT_STATUS_ENABLE_ADDRESS,
 632                                    &regs.int_status_en, sizeof(regs),
 633                                    HIF_WR_SYNC_BYTE_INC);
 634 }
 635
 636 /* enable device interrupts */
 637 int ath6kl_hif_unmask_intrs(struct ath6kl_device *dev)
 638 {
 639         int status = 0;
 640
 641         /*
 642          * Make sure interrupt are disabled before unmasking at the HIF
 643          * layer. The rationale here is that between device insertion
 644          * (where we clear the interrupts the first time) and when HTC
 645          * is finally ready to handle interrupts, other software can perform
 646          * target "soft" resets. The ATH6KL interrupt enables reset back to an
 647          * "enabled" state when this happens.
 648          */
 649         ath6kl_hif_disable_intrs(dev);
 650
 651         /* unmask the host controller interrupts */
 652         ath6kl_hif_irq_enable(dev->ar);
 653         status = ath6kl_hif_enable_intrs(dev);
 654
 655         return status;
 656 }
 657
 658 /* disable all device interrupts */
 659 int ath6kl_hif_mask_intrs(struct ath6kl_device *dev)
 660 {
 661         /*
 662          * Mask the interrupt at the HIF layer to avoid any stray interrupt
 663          * taken while we zero out our shadow registers in
 664          * ath6kl_hif_disable_intrs().
 665          */
 666         ath6kl_hif_irq_disable(dev->ar);
 667
 668         return ath6kl_hif_disable_intrs(dev);
 669 }
 670
 671 int ath6kl_hif_setup(struct ath6kl_device *dev)
 672 {
 673         int status = 0;
 674
 675         spin_lock_init(&dev->lock);
 676
 677         /*
 678          * NOTE: we actually get the block size of a mailbox other than 0,
 679          * for SDIO the block size on mailbox 0 is artificially set to 1.
 680          * So we use the block size that is set for the other 3 mailboxes.
 681          */
 682         dev->htc_cnxt->block_sz = dev->ar->mbox_info.block_size;
 683
 684         /* must be a power of 2 */
 685         if ((dev->htc_cnxt->block_sz & (dev->htc_cnxt->block_sz - 1)) != 0) {
 686                 WARN_ON(1);
 687                 status = -EINVAL;
 688                 goto fail_setup;
 689         }
 690
 691         /* assemble mask, used for padding to a block */
 692         dev->htc_cnxt->block_mask = dev->htc_cnxt->block_sz - 1;
 693
 694         ath6kl_dbg(ATH6KL_DBG_HIF, "hif block size %d mbox addr 0x%x\n",
 695                    dev->htc_cnxt->block_sz, dev->ar->mbox_info.htc_addr);
 696
 697         /* usb doesn't support enabling interrupts */
 698         /* FIXME: remove check once USB support is implemented */
 699         if (dev->ar->hif_type == ATH6KL_HIF_TYPE_USB)
 700                 return 0;
 701
 702         status = ath6kl_hif_disable_intrs(dev);
 703
 704 fail_setup:
 705         return status;
 706
 707 }