drivers/net/wireless/ath/ath6kl/hif.h

   1 /*
   2  * Copyright (c) 2004-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef HIF_H
  18 #define HIF_H
  19
  20 #include "common.h"
  21 #include "core.h"
  22
  23 #include <linux/scatterlist.h>
  24
  25 #define BUS_REQUEST_MAX_NUM                64
  26 #define HIF_MBOX_BLOCK_SIZE                128
  27 #define HIF_MBOX0_BLOCK_SIZE               1
  28
  29 #define HIF_DMA_BUFFER_SIZE (32 * 1024)
  30 #define CMD53_FIXED_ADDRESS 1
  31 #define CMD53_INCR_ADDRESS  2
  32
  33 #define MAX_SCATTER_REQUESTS             4
  34 #define MAX_SCATTER_ENTRIES_PER_REQ      16
  35 #define MAX_SCATTER_REQ_TRANSFER_SIZE    (32 * 1024)
  36
  37 #define MANUFACTURER_ID_AR6003_BASE        0x300
  38     /* SDIO manufacturer ID and Codes */
  39 #define MANUFACTURER_ID_ATH6KL_BASE_MASK     0xFF00
  40 #define MANUFACTURER_CODE                  0x271        /* Atheros */
  41
  42 /* Mailbox address in SDIO address space */
  43 #define HIF_MBOX_BASE_ADDR                 0x800
  44 #define HIF_MBOX_WIDTH                     0x800
  45
  46 #define HIF_MBOX_END_ADDR  (HTC_MAILBOX_NUM_MAX * HIF_MBOX_WIDTH - 1)
  47
  48 /* version 1 of the chip has only a 12K extended mbox range */
  49 #define HIF_MBOX0_EXT_BASE_ADDR  0x4000
  50 #define HIF_MBOX0_EXT_WIDTH      (12*1024)
  51
  52 /* GMBOX addresses */
  53 #define HIF_GMBOX_BASE_ADDR                0x7000
  54 #define HIF_GMBOX_WIDTH                    0x4000
  55
  56 /* interrupt mode register */
  57 #define CCCR_SDIO_IRQ_MODE_REG         0xF0
  58
  59 /* mode to enable special 4-bit interrupt assertion without clock */
  60 #define SDIO_IRQ_MODE_ASYNC_4BIT_IRQ   (1 << 0)
  61
  62 struct bus_request {
  63         struct list_head list;
  64
  65         /* request data */
  66         u32 address;
  67
  68         u8 *buffer;
  69         u32 length;
  70         u32 request;
  71         struct htc_packet *packet;
  72         int status;
  73
  74         /* this is a scatter request */
  75         struct hif_scatter_req *scat_req;
  76 };
  77
  78 /* direction of transfer (read/write) */
  79 #define HIF_READ                    0x00000001
  80 #define HIF_WRITE                   0x00000002
  81 #define HIF_DIR_MASK                (HIF_READ | HIF_WRITE)
  82
  83 /*
  84  *     emode - This indicates the whether the command is to be executed in a
  85  *             blocking or non-blocking fashion (HIF_SYNCHRONOUS/
  86  *             HIF_ASYNCHRONOUS). The read/write data paths in HTC have been
  87  *             implemented using the asynchronous mode allowing the the bus
  88  *             driver to indicate the completion of operation through the
  89  *             registered callback routine. The requirement primarily comes
  90  *             from the contexts these operations get called from (a driver's
  91  *             transmit context or the ISR context in case of receive).
  92  *             Support for both of these modes is essential.
  93  */
  94 #define HIF_SYNCHRONOUS             0x00000010
  95 #define HIF_ASYNCHRONOUS            0x00000020
  96 #define HIF_EMODE_MASK              (HIF_SYNCHRONOUS | HIF_ASYNCHRONOUS)
  97
  98 /*
  99  *     dmode - An interface may support different kinds of commands based on
 100  *             the tradeoff between the amount of data it can carry and the
 101  *             setup time. Byte and Block modes are supported (HIF_BYTE_BASIS/
 102  *             HIF_BLOCK_BASIS). In case of latter, the data is rounded off
 103  *             to the nearest block size by padding. The size of the block is
 104  *             configurable at compile time using the HIF_BLOCK_SIZE and is
 105  *             negotiated with the target during initialization after the
 106  *             ATH6KL interrupts are enabled.
 107  */
 108 #define HIF_BYTE_BASIS              0x00000040
 109 #define HIF_BLOCK_BASIS             0x00000080
 110 #define HIF_DMODE_MASK              (HIF_BYTE_BASIS | HIF_BLOCK_BASIS)
 111
 112 /*
 113  *     amode - This indicates if the address has to be incremented on ATH6KL
 114  *             after every read/write operation (HIF?FIXED_ADDRESS/
 115  *             HIF_INCREMENTAL_ADDRESS).
 116  */
 117 #define HIF_FIXED_ADDRESS           0x00000100
 118 #define HIF_INCREMENTAL_ADDRESS     0x00000200
 119 #define HIF_AMODE_MASK            (HIF_FIXED_ADDRESS | HIF_INCREMENTAL_ADDRESS)
 120
 121 #define HIF_WR_ASYNC_BYTE_INC                                   \
 122         (HIF_WRITE | HIF_ASYNCHRONOUS |                         \
 123          HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)
 124
 125 #define HIF_WR_ASYNC_BLOCK_INC                                  \
 126         (HIF_WRITE | HIF_ASYNCHRONOUS |                         \
 127          HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS)
 128
 129 #define HIF_WR_SYNC_BYTE_FIX                                    \
 130         (HIF_WRITE | HIF_SYNCHRONOUS |                          \
 131          HIF_BYTE_BASIS | HIF_FIXED_ADDRESS)
 132
 133 #define HIF_WR_SYNC_BYTE_INC                                    \
 134         (HIF_WRITE | HIF_SYNCHRONOUS |                          \
 135          HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)
 136
 137 #define HIF_WR_SYNC_BLOCK_INC                                   \
 138         (HIF_WRITE | HIF_SYNCHRONOUS |                          \
 139          HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS)
 140
 141 #define HIF_RD_SYNC_BYTE_INC                                            \
 142         (HIF_READ | HIF_SYNCHRONOUS |                                   \
 143          HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)
 144
 145 #define HIF_RD_SYNC_BYTE_FIX                                            \
 146         (HIF_READ | HIF_SYNCHRONOUS |                                   \
 147          HIF_BYTE_BASIS | HIF_FIXED_ADDRESS)
 148
 149 #define HIF_RD_ASYNC_BLOCK_FIX                                          \
 150         (HIF_READ | HIF_ASYNCHRONOUS |                                  \
 151          HIF_BLOCK_BASIS | HIF_FIXED_ADDRESS)
 152
 153 #define HIF_RD_SYNC_BLOCK_FIX                                           \
 154         (HIF_READ | HIF_SYNCHRONOUS |                                   \
 155          HIF_BLOCK_BASIS | HIF_FIXED_ADDRESS)
 156
 157 struct hif_scatter_item {
 158         u8 *buf;
 159         int len;
 160         struct htc_packet *packet;
 161 };
 162
 163 struct hif_scatter_req {
 164         struct list_head list;
 165         /* address for the read/write operation */
 166         u32 addr;
 167
 168         /* request flags */
 169         u32 req;
 170
 171         /* total length of entire transfer */
 172         u32 len;
 173
 174         bool virt_scat;
 175
 176         void (*complete) (struct htc_target *, struct hif_scatter_req *);
 177         int status;
 178         int scat_entries;
 179
 180         struct bus_request *busrequest;
 181         struct scatterlist *sgentries;
 182
 183         /* bounce buffer for upper layers to copy to/from */
 184         u8 *virt_dma_buf;
 185
 186         struct hif_scatter_item scat_list[1];
 187 };
 188
 189 struct ath6kl_hif_ops {
 190         int (*read_write_sync)(struct ath6kl *ar, u32 addr, u8 *buf,
 191                                u32 len, u32 request);
 192         int (*write_async)(struct ath6kl *ar, u32 address, u8 *buffer,
 193                            u32 length, u32 request, struct htc_packet *packet);
 194
 195         void (*irq_enable)(struct ath6kl *ar);
 196         void (*irq_disable)(struct ath6kl *ar);
 197
 198         struct hif_scatter_req *(*scatter_req_get)(struct ath6kl *ar);
 199         void (*scatter_req_add)(struct ath6kl *ar,
 200                                 struct hif_scatter_req *s_req);
 201         int (*enable_scatter)(struct ath6kl *ar);
 202         int (*scat_req_rw) (struct ath6kl *ar,
 203                             struct hif_scatter_req *scat_req);
 204         void (*cleanup_scatter)(struct ath6kl *ar);
 205         int (*suspend)(struct ath6kl *ar);
 206 };
 207
 208 #endif