2 * Copyright (c) 2004-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
23 #include <linux/scatterlist.h>
25 #define BUS_REQUEST_MAX_NUM 64
26 #define HIF_MBOX_BLOCK_SIZE 128
27 #define HIF_MBOX0_BLOCK_SIZE 1
29 #define HIF_DMA_BUFFER_SIZE (32 * 1024)
30 #define CMD53_FIXED_ADDRESS 1
31 #define CMD53_INCR_ADDRESS 2
33 #define MAX_SCATTER_REQUESTS 4
34 #define MAX_SCATTER_ENTRIES_PER_REQ 16
35 #define MAX_SCATTER_REQ_TRANSFER_SIZE (32 * 1024)
37 #define MANUFACTURER_ID_AR6003_BASE 0x300
38 /* SDIO manufacturer ID and Codes */
39 #define MANUFACTURER_ID_ATH6KL_BASE_MASK 0xFF00
40 #define MANUFACTURER_CODE 0x271 /* Atheros */
42 /* Mailbox address in SDIO address space */
43 #define HIF_MBOX_BASE_ADDR 0x800
44 #define HIF_MBOX_WIDTH 0x800
46 #define HIF_MBOX_END_ADDR (HTC_MAILBOX_NUM_MAX * HIF_MBOX_WIDTH - 1)
48 /* version 1 of the chip has only a 12K extended mbox range */
49 #define HIF_MBOX0_EXT_BASE_ADDR 0x4000
50 #define HIF_MBOX0_EXT_WIDTH (12*1024)
53 #define HIF_GMBOX_BASE_ADDR 0x7000
54 #define HIF_GMBOX_WIDTH 0x4000
56 /* interrupt mode register */
57 #define CCCR_SDIO_IRQ_MODE_REG 0xF0
59 /* mode to enable special 4-bit interrupt assertion without clock */
60 #define SDIO_IRQ_MODE_ASYNC_4BIT_IRQ (1 << 0)
63 struct list_head list
;
71 struct htc_packet
*packet
;
74 /* this is a scatter request */
75 struct hif_scatter_req
*scat_req
;
78 /* direction of transfer (read/write) */
79 #define HIF_READ 0x00000001
80 #define HIF_WRITE 0x00000002
81 #define HIF_DIR_MASK (HIF_READ | HIF_WRITE)
84 * emode - This indicates the whether the command is to be executed in a
85 * blocking or non-blocking fashion (HIF_SYNCHRONOUS/
86 * HIF_ASYNCHRONOUS). The read/write data paths in HTC have been
87 * implemented using the asynchronous mode allowing the the bus
88 * driver to indicate the completion of operation through the
89 * registered callback routine. The requirement primarily comes
90 * from the contexts these operations get called from (a driver's
91 * transmit context or the ISR context in case of receive).
92 * Support for both of these modes is essential.
94 #define HIF_SYNCHRONOUS 0x00000010
95 #define HIF_ASYNCHRONOUS 0x00000020
96 #define HIF_EMODE_MASK (HIF_SYNCHRONOUS | HIF_ASYNCHRONOUS)
99 * dmode - An interface may support different kinds of commands based on
100 * the tradeoff between the amount of data it can carry and the
101 * setup time. Byte and Block modes are supported (HIF_BYTE_BASIS/
102 * HIF_BLOCK_BASIS). In case of latter, the data is rounded off
103 * to the nearest block size by padding. The size of the block is
104 * configurable at compile time using the HIF_BLOCK_SIZE and is
105 * negotiated with the target during initialization after the
106 * ATH6KL interrupts are enabled.
108 #define HIF_BYTE_BASIS 0x00000040
109 #define HIF_BLOCK_BASIS 0x00000080
110 #define HIF_DMODE_MASK (HIF_BYTE_BASIS | HIF_BLOCK_BASIS)
113 * amode - This indicates if the address has to be incremented on ATH6KL
114 * after every read/write operation (HIF?FIXED_ADDRESS/
115 * HIF_INCREMENTAL_ADDRESS).
117 #define HIF_FIXED_ADDRESS 0x00000100
118 #define HIF_INCREMENTAL_ADDRESS 0x00000200
119 #define HIF_AMODE_MASK (HIF_FIXED_ADDRESS | HIF_INCREMENTAL_ADDRESS)
121 #define HIF_WR_ASYNC_BYTE_INC \
122 (HIF_WRITE | HIF_ASYNCHRONOUS | \
123 HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)
125 #define HIF_WR_ASYNC_BLOCK_INC \
126 (HIF_WRITE | HIF_ASYNCHRONOUS | \
127 HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS)
129 #define HIF_WR_SYNC_BYTE_FIX \
130 (HIF_WRITE | HIF_SYNCHRONOUS | \
131 HIF_BYTE_BASIS | HIF_FIXED_ADDRESS)
133 #define HIF_WR_SYNC_BYTE_INC \
134 (HIF_WRITE | HIF_SYNCHRONOUS | \
135 HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)
137 #define HIF_WR_SYNC_BLOCK_INC \
138 (HIF_WRITE | HIF_SYNCHRONOUS | \
139 HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS)
141 #define HIF_RD_SYNC_BYTE_INC \
142 (HIF_READ | HIF_SYNCHRONOUS | \
143 HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)
145 #define HIF_RD_SYNC_BYTE_FIX \
146 (HIF_READ | HIF_SYNCHRONOUS | \
147 HIF_BYTE_BASIS | HIF_FIXED_ADDRESS)
149 #define HIF_RD_ASYNC_BLOCK_FIX \
150 (HIF_READ | HIF_ASYNCHRONOUS | \
151 HIF_BLOCK_BASIS | HIF_FIXED_ADDRESS)
153 #define HIF_RD_SYNC_BLOCK_FIX \
154 (HIF_READ | HIF_SYNCHRONOUS | \
155 HIF_BLOCK_BASIS | HIF_FIXED_ADDRESS)
157 struct hif_scatter_item
{
160 struct htc_packet
*packet
;
163 struct hif_scatter_req
{
164 struct list_head list
;
165 /* address for the read/write operation */
171 /* total length of entire transfer */
176 void (*complete
) (struct htc_target
*, struct hif_scatter_req
*);
180 struct bus_request
*busrequest
;
181 struct scatterlist
*sgentries
;
183 /* bounce buffer for upper layers to copy to/from */
186 struct hif_scatter_item scat_list
[1];
189 struct hif_dev_scat_sup_info
{
190 int max_scat_entries
;
191 int max_xfer_szper_scatreq
;
194 struct ath6kl_hif_ops
{
195 int (*read_write_sync
)(struct ath6kl
*ar
, u32 addr
, u8
*buf
,
196 u32 len
, u32 request
);
197 int (*write_async
)(struct ath6kl
*ar
, u32 address
, u8
*buffer
,
198 u32 length
, u32 request
, struct htc_packet
*packet
);
200 void (*irq_enable
)(struct ath6kl
*ar
);
201 void (*irq_disable
)(struct ath6kl
*ar
);
203 struct hif_scatter_req
*(*scatter_req_get
)(struct ath6kl
*ar
);
204 void (*scatter_req_add
)(struct ath6kl
*ar
,
205 struct hif_scatter_req
*s_req
);
206 int (*enable_scatter
)(struct ath6kl
*ar
,
207 struct hif_dev_scat_sup_info
*info
);
208 int (*scat_req_rw
) (struct ath6kl
*ar
,
209 struct hif_scatter_req
*scat_req
);
210 void (*cleanup_scatter
)(struct ath6kl
*ar
);