2 * Copyright (c) 2004-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/module.h>
18 #include <linux/mmc/card.h>
19 #include <linux/mmc/mmc.h>
20 #include <linux/mmc/host.h>
21 #include <linux/mmc/sdio_func.h>
22 #include <linux/mmc/sdio_ids.h>
23 #include <linux/mmc/sdio.h>
24 #include <linux/mmc/sd.h>
32 struct sdio_func
*func
;
37 struct list_head bus_req_freeq
;
39 /* available bus requests */
40 struct bus_request bus_req
[BUS_REQUEST_MAX_NUM
];
46 /* protects access to dma_buffer */
47 struct mutex dma_buffer_mutex
;
49 /* scatter request list head */
50 struct list_head scat_req
;
52 /* Avoids disabling irq while the interrupts being handled */
59 const struct sdio_device_id
*id
;
60 struct work_struct wr_async_work
;
61 struct list_head wr_asyncq
;
62 spinlock_t wr_async_lock
;
65 #define CMD53_ARG_READ 0
66 #define CMD53_ARG_WRITE 1
67 #define CMD53_ARG_BLOCK_BASIS 1
68 #define CMD53_ARG_FIXED_ADDRESS 0
69 #define CMD53_ARG_INCR_ADDRESS 1
71 static inline struct ath6kl_sdio
*ath6kl_sdio_priv(struct ath6kl
*ar
)
77 * Macro to check if DMA buffer is WORD-aligned and DMA-able.
78 * Most host controllers assume the buffer is DMA'able and will
79 * bug-check otherwise (i.e. buffers on the stack). virt_addr_valid
80 * check fails on stack memory.
82 static inline bool buf_needs_bounce(u8
*buf
)
84 return ((unsigned long) buf
& 0x3) || !virt_addr_valid(buf
);
87 static void ath6kl_sdio_set_mbox_info(struct ath6kl
*ar
)
89 struct ath6kl_mbox_info
*mbox_info
= &ar
->mbox_info
;
91 /* EP1 has an extended range */
92 mbox_info
->htc_addr
= HIF_MBOX_BASE_ADDR
;
93 mbox_info
->htc_ext_addr
= HIF_MBOX0_EXT_BASE_ADDR
;
94 mbox_info
->htc_ext_sz
= HIF_MBOX0_EXT_WIDTH
;
95 mbox_info
->block_size
= HIF_MBOX_BLOCK_SIZE
;
96 mbox_info
->gmbox_addr
= HIF_GMBOX_BASE_ADDR
;
97 mbox_info
->gmbox_sz
= HIF_GMBOX_WIDTH
;
100 static inline void ath6kl_sdio_set_cmd53_arg(u32
*arg
, u8 rw
, u8 func
,
101 u8 mode
, u8 opcode
, u32 addr
,
104 *arg
= (((rw
& 1) << 31) |
105 ((func
& 0x7) << 28) |
107 ((opcode
& 1) << 26) |
108 ((addr
& 0x1FFFF) << 9) |
112 static inline void ath6kl_sdio_set_cmd52_arg(u32
*arg
, u8 write
, u8 raw
,
113 unsigned int address
,
118 *arg
= ((write
& 1) << 31) |
119 ((func
& 0x7) << 28) |
122 ((address
& 0x1FFFF) << 9) |
127 static int ath6kl_sdio_func0_cmd52_wr_byte(struct mmc_card
*card
,
128 unsigned int address
,
131 struct mmc_command io_cmd
;
133 memset(&io_cmd
, 0, sizeof(io_cmd
));
134 ath6kl_sdio_set_cmd52_arg(&io_cmd
.arg
, 1, 0, address
, byte
);
135 io_cmd
.opcode
= SD_IO_RW_DIRECT
;
136 io_cmd
.flags
= MMC_RSP_R5
| MMC_CMD_AC
;
138 return mmc_wait_for_cmd(card
->host
, &io_cmd
, 0);
141 static int ath6kl_sdio_io(struct sdio_func
*func
, u32 request
, u32 addr
,
146 sdio_claim_host(func
);
148 if (request
& HIF_WRITE
) {
149 /* FIXME: looks like ugly workaround for something */
150 if (addr
>= HIF_MBOX_BASE_ADDR
&&
151 addr
<= HIF_MBOX_END_ADDR
)
152 addr
+= (HIF_MBOX_WIDTH
- len
);
154 /* FIXME: this also looks like ugly workaround */
155 if (addr
== HIF_MBOX0_EXT_BASE_ADDR
)
156 addr
+= HIF_MBOX0_EXT_WIDTH
- len
;
158 if (request
& HIF_FIXED_ADDRESS
)
159 ret
= sdio_writesb(func
, addr
, buf
, len
);
161 ret
= sdio_memcpy_toio(func
, addr
, buf
, len
);
163 if (request
& HIF_FIXED_ADDRESS
)
164 ret
= sdio_readsb(func
, buf
, addr
, len
);
166 ret
= sdio_memcpy_fromio(func
, buf
, addr
, len
);
169 sdio_release_host(func
);
171 ath6kl_dbg(ATH6KL_DBG_SDIO
, "%s addr 0x%x%s buf 0x%p len %d\n",
172 request
& HIF_WRITE
? "wr" : "rd", addr
,
173 request
& HIF_FIXED_ADDRESS
? " (fixed)" : "", buf
, len
);
174 ath6kl_dbg_dump(ATH6KL_DBG_SDIO_DUMP
, NULL
, "sdio ", buf
, len
);
179 static struct bus_request
*ath6kl_sdio_alloc_busreq(struct ath6kl_sdio
*ar_sdio
)
181 struct bus_request
*bus_req
;
183 spin_lock_bh(&ar_sdio
->lock
);
185 if (list_empty(&ar_sdio
->bus_req_freeq
)) {
186 spin_unlock_bh(&ar_sdio
->lock
);
190 bus_req
= list_first_entry(&ar_sdio
->bus_req_freeq
,
191 struct bus_request
, list
);
192 list_del(&bus_req
->list
);
194 spin_unlock_bh(&ar_sdio
->lock
);
195 ath6kl_dbg(ATH6KL_DBG_SCATTER
, "%s: bus request 0x%p\n",
201 static void ath6kl_sdio_free_bus_req(struct ath6kl_sdio
*ar_sdio
,
202 struct bus_request
*bus_req
)
204 ath6kl_dbg(ATH6KL_DBG_SCATTER
, "%s: bus request 0x%p\n",
207 spin_lock_bh(&ar_sdio
->lock
);
208 list_add_tail(&bus_req
->list
, &ar_sdio
->bus_req_freeq
);
209 spin_unlock_bh(&ar_sdio
->lock
);
212 static void ath6kl_sdio_setup_scat_data(struct hif_scatter_req
*scat_req
,
213 struct mmc_data
*data
)
215 struct scatterlist
*sg
;
218 data
->blksz
= HIF_MBOX_BLOCK_SIZE
;
219 data
->blocks
= scat_req
->len
/ HIF_MBOX_BLOCK_SIZE
;
221 ath6kl_dbg(ATH6KL_DBG_SCATTER
,
222 "hif-scatter: (%s) addr: 0x%X, (block len: %d, block count: %d) , (tot:%d,sg:%d)\n",
223 (scat_req
->req
& HIF_WRITE
) ? "WR" : "RD", scat_req
->addr
,
224 data
->blksz
, data
->blocks
, scat_req
->len
,
225 scat_req
->scat_entries
);
227 data
->flags
= (scat_req
->req
& HIF_WRITE
) ? MMC_DATA_WRITE
:
230 /* fill SG entries */
231 sg
= scat_req
->sgentries
;
232 sg_init_table(sg
, scat_req
->scat_entries
);
234 /* assemble SG list */
235 for (i
= 0; i
< scat_req
->scat_entries
; i
++, sg
++) {
236 ath6kl_dbg(ATH6KL_DBG_SCATTER
, "%d: addr:0x%p, len:%d\n",
237 i
, scat_req
->scat_list
[i
].buf
,
238 scat_req
->scat_list
[i
].len
);
240 sg_set_buf(sg
, scat_req
->scat_list
[i
].buf
,
241 scat_req
->scat_list
[i
].len
);
244 /* set scatter-gather table for request */
245 data
->sg
= scat_req
->sgentries
;
246 data
->sg_len
= scat_req
->scat_entries
;
249 static int ath6kl_sdio_scat_rw(struct ath6kl_sdio
*ar_sdio
,
250 struct bus_request
*req
)
252 struct mmc_request mmc_req
;
253 struct mmc_command cmd
;
254 struct mmc_data data
;
255 struct hif_scatter_req
*scat_req
;
259 scat_req
= req
->scat_req
;
261 if (scat_req
->virt_scat
) {
263 if (scat_req
->req
& HIF_BLOCK_BASIS
)
264 len
= round_down(len
, HIF_MBOX_BLOCK_SIZE
);
266 status
= ath6kl_sdio_io(ar_sdio
->func
, scat_req
->req
,
267 scat_req
->addr
, scat_req
->virt_dma_buf
,
272 memset(&mmc_req
, 0, sizeof(struct mmc_request
));
273 memset(&cmd
, 0, sizeof(struct mmc_command
));
274 memset(&data
, 0, sizeof(struct mmc_data
));
276 ath6kl_sdio_setup_scat_data(scat_req
, &data
);
278 opcode
= (scat_req
->req
& HIF_FIXED_ADDRESS
) ?
279 CMD53_ARG_FIXED_ADDRESS
: CMD53_ARG_INCR_ADDRESS
;
281 rw
= (scat_req
->req
& HIF_WRITE
) ? CMD53_ARG_WRITE
: CMD53_ARG_READ
;
283 /* Fixup the address so that the last byte will fall on MBOX EOM */
284 if (scat_req
->req
& HIF_WRITE
) {
285 if (scat_req
->addr
== HIF_MBOX_BASE_ADDR
)
286 scat_req
->addr
+= HIF_MBOX_WIDTH
- scat_req
->len
;
288 /* Uses extended address range */
289 scat_req
->addr
+= HIF_MBOX0_EXT_WIDTH
- scat_req
->len
;
292 /* set command argument */
293 ath6kl_sdio_set_cmd53_arg(&cmd
.arg
, rw
, ar_sdio
->func
->num
,
294 CMD53_ARG_BLOCK_BASIS
, opcode
, scat_req
->addr
,
297 cmd
.opcode
= SD_IO_RW_EXTENDED
;
298 cmd
.flags
= MMC_RSP_SPI_R5
| MMC_RSP_R5
| MMC_CMD_ADTC
;
301 mmc_req
.data
= &data
;
303 sdio_claim_host(ar_sdio
->func
);
305 mmc_set_data_timeout(&data
, ar_sdio
->func
->card
);
306 /* synchronous call to process request */
307 mmc_wait_for_req(ar_sdio
->func
->card
->host
, &mmc_req
);
309 sdio_release_host(ar_sdio
->func
);
311 status
= cmd
.error
? cmd
.error
: data
.error
;
314 scat_req
->status
= status
;
316 if (scat_req
->status
)
317 ath6kl_err("Scatter write request failed:%d\n",
320 if (scat_req
->req
& HIF_ASYNCHRONOUS
)
321 scat_req
->complete(ar_sdio
->ar
->htc_target
, scat_req
);
326 static int ath6kl_sdio_alloc_prep_scat_req(struct ath6kl_sdio
*ar_sdio
,
327 int n_scat_entry
, int n_scat_req
,
330 struct hif_scatter_req
*s_req
;
331 struct bus_request
*bus_req
;
332 int i
, scat_req_sz
, scat_list_sz
, sg_sz
, buf_sz
;
335 scat_list_sz
= (n_scat_entry
- 1) * sizeof(struct hif_scatter_item
);
336 scat_req_sz
= sizeof(*s_req
) + scat_list_sz
;
339 sg_sz
= sizeof(struct scatterlist
) * n_scat_entry
;
341 buf_sz
= 2 * L1_CACHE_BYTES
+
342 ATH6KL_MAX_TRANSFER_SIZE_PER_SCATTER
;
344 for (i
= 0; i
< n_scat_req
; i
++) {
345 /* allocate the scatter request */
346 s_req
= kzalloc(scat_req_sz
, GFP_KERNEL
);
351 virt_buf
= kzalloc(buf_sz
, GFP_KERNEL
);
357 s_req
->virt_dma_buf
=
358 (u8
*)L1_CACHE_ALIGN((unsigned long)virt_buf
);
360 /* allocate sglist */
361 s_req
->sgentries
= kzalloc(sg_sz
, GFP_KERNEL
);
363 if (!s_req
->sgentries
) {
369 /* allocate a bus request for this scatter request */
370 bus_req
= ath6kl_sdio_alloc_busreq(ar_sdio
);
372 kfree(s_req
->sgentries
);
373 kfree(s_req
->virt_dma_buf
);
378 /* assign the scatter request to this bus request */
379 bus_req
->scat_req
= s_req
;
380 s_req
->busrequest
= bus_req
;
382 s_req
->virt_scat
= virt_scat
;
384 /* add it to the scatter pool */
385 hif_scatter_req_add(ar_sdio
->ar
, s_req
);
391 static int ath6kl_sdio_read_write_sync(struct ath6kl
*ar
, u32 addr
, u8
*buf
,
392 u32 len
, u32 request
)
394 struct ath6kl_sdio
*ar_sdio
= ath6kl_sdio_priv(ar
);
397 bool bounced
= false;
399 if (request
& HIF_BLOCK_BASIS
)
400 len
= round_down(len
, HIF_MBOX_BLOCK_SIZE
);
402 if (buf_needs_bounce(buf
)) {
403 if (!ar_sdio
->dma_buffer
)
405 mutex_lock(&ar_sdio
->dma_buffer_mutex
);
406 tbuf
= ar_sdio
->dma_buffer
;
407 memcpy(tbuf
, buf
, len
);
412 ret
= ath6kl_sdio_io(ar_sdio
->func
, request
, addr
, tbuf
, len
);
413 if ((request
& HIF_READ
) && bounced
)
414 memcpy(buf
, tbuf
, len
);
417 mutex_unlock(&ar_sdio
->dma_buffer_mutex
);
422 static void __ath6kl_sdio_write_async(struct ath6kl_sdio
*ar_sdio
,
423 struct bus_request
*req
)
426 ath6kl_sdio_scat_rw(ar_sdio
, req
);
431 status
= ath6kl_sdio_read_write_sync(ar_sdio
->ar
, req
->address
,
432 req
->buffer
, req
->length
,
434 context
= req
->packet
;
435 ath6kl_sdio_free_bus_req(ar_sdio
, req
);
436 ath6kl_hif_rw_comp_handler(context
, status
);
440 static void ath6kl_sdio_write_async_work(struct work_struct
*work
)
442 struct ath6kl_sdio
*ar_sdio
;
443 struct bus_request
*req
, *tmp_req
;
445 ar_sdio
= container_of(work
, struct ath6kl_sdio
, wr_async_work
);
447 spin_lock_bh(&ar_sdio
->wr_async_lock
);
448 list_for_each_entry_safe(req
, tmp_req
, &ar_sdio
->wr_asyncq
, list
) {
449 list_del(&req
->list
);
450 spin_unlock_bh(&ar_sdio
->wr_async_lock
);
451 __ath6kl_sdio_write_async(ar_sdio
, req
);
452 spin_lock_bh(&ar_sdio
->wr_async_lock
);
454 spin_unlock_bh(&ar_sdio
->wr_async_lock
);
457 static void ath6kl_sdio_irq_handler(struct sdio_func
*func
)
460 struct ath6kl_sdio
*ar_sdio
;
462 ath6kl_dbg(ATH6KL_DBG_SDIO
, "irq\n");
464 ar_sdio
= sdio_get_drvdata(func
);
465 mutex_lock(&ar_sdio
->mtx_irq
);
467 * Release the host during interrups so we can pick it back up when
468 * we process commands.
470 sdio_release_host(ar_sdio
->func
);
472 status
= ath6kl_hif_intr_bh_handler(ar_sdio
->ar
);
473 sdio_claim_host(ar_sdio
->func
);
474 mutex_unlock(&ar_sdio
->mtx_irq
);
475 WARN_ON(status
&& status
!= -ECANCELED
);
478 static int ath6kl_sdio_power_on(struct ath6kl
*ar
)
480 struct ath6kl_sdio
*ar_sdio
= ath6kl_sdio_priv(ar
);
481 struct sdio_func
*func
= ar_sdio
->func
;
484 if (!ar_sdio
->is_disabled
)
487 ath6kl_dbg(ATH6KL_DBG_BOOT
, "sdio power on\n");
489 sdio_claim_host(func
);
491 ret
= sdio_enable_func(func
);
493 ath6kl_err("Unable to enable sdio func: %d)\n", ret
);
494 sdio_release_host(func
);
498 sdio_release_host(func
);
501 * Wait for hardware to initialise. It should take a lot less than
502 * 10 ms but let's be conservative here.
506 ar_sdio
->is_disabled
= false;
511 static int ath6kl_sdio_power_off(struct ath6kl
*ar
)
513 struct ath6kl_sdio
*ar_sdio
= ath6kl_sdio_priv(ar
);
516 if (ar_sdio
->is_disabled
)
519 ath6kl_dbg(ATH6KL_DBG_BOOT
, "sdio power off\n");
521 /* Disable the card */
522 sdio_claim_host(ar_sdio
->func
);
523 ret
= sdio_disable_func(ar_sdio
->func
);
524 sdio_release_host(ar_sdio
->func
);
529 ar_sdio
->is_disabled
= true;
534 static int ath6kl_sdio_write_async(struct ath6kl
*ar
, u32 address
, u8
*buffer
,
535 u32 length
, u32 request
,
536 struct htc_packet
*packet
)
538 struct ath6kl_sdio
*ar_sdio
= ath6kl_sdio_priv(ar
);
539 struct bus_request
*bus_req
;
541 bus_req
= ath6kl_sdio_alloc_busreq(ar_sdio
);
546 bus_req
->address
= address
;
547 bus_req
->buffer
= buffer
;
548 bus_req
->length
= length
;
549 bus_req
->request
= request
;
550 bus_req
->packet
= packet
;
552 spin_lock_bh(&ar_sdio
->wr_async_lock
);
553 list_add_tail(&bus_req
->list
, &ar_sdio
->wr_asyncq
);
554 spin_unlock_bh(&ar_sdio
->wr_async_lock
);
555 queue_work(ar
->ath6kl_wq
, &ar_sdio
->wr_async_work
);
560 static void ath6kl_sdio_irq_enable(struct ath6kl
*ar
)
562 struct ath6kl_sdio
*ar_sdio
= ath6kl_sdio_priv(ar
);
565 sdio_claim_host(ar_sdio
->func
);
567 /* Register the isr */
568 ret
= sdio_claim_irq(ar_sdio
->func
, ath6kl_sdio_irq_handler
);
570 ath6kl_err("Failed to claim sdio irq: %d\n", ret
);
572 sdio_release_host(ar_sdio
->func
);
575 static void ath6kl_sdio_irq_disable(struct ath6kl
*ar
)
577 struct ath6kl_sdio
*ar_sdio
= ath6kl_sdio_priv(ar
);
580 sdio_claim_host(ar_sdio
->func
);
582 mutex_lock(&ar_sdio
->mtx_irq
);
584 ret
= sdio_release_irq(ar_sdio
->func
);
586 ath6kl_err("Failed to release sdio irq: %d\n", ret
);
588 mutex_unlock(&ar_sdio
->mtx_irq
);
590 sdio_release_host(ar_sdio
->func
);
593 static struct hif_scatter_req
*ath6kl_sdio_scatter_req_get(struct ath6kl
*ar
)
595 struct ath6kl_sdio
*ar_sdio
= ath6kl_sdio_priv(ar
);
596 struct hif_scatter_req
*node
= NULL
;
598 spin_lock_bh(&ar_sdio
->scat_lock
);
600 if (!list_empty(&ar_sdio
->scat_req
)) {
601 node
= list_first_entry(&ar_sdio
->scat_req
,
602 struct hif_scatter_req
, list
);
603 list_del(&node
->list
);
606 spin_unlock_bh(&ar_sdio
->scat_lock
);
611 static void ath6kl_sdio_scatter_req_add(struct ath6kl
*ar
,
612 struct hif_scatter_req
*s_req
)
614 struct ath6kl_sdio
*ar_sdio
= ath6kl_sdio_priv(ar
);
616 spin_lock_bh(&ar_sdio
->scat_lock
);
618 list_add_tail(&s_req
->list
, &ar_sdio
->scat_req
);
620 spin_unlock_bh(&ar_sdio
->scat_lock
);
624 /* scatter gather read write request */
625 static int ath6kl_sdio_async_rw_scatter(struct ath6kl
*ar
,
626 struct hif_scatter_req
*scat_req
)
628 struct ath6kl_sdio
*ar_sdio
= ath6kl_sdio_priv(ar
);
629 u32 request
= scat_req
->req
;
635 ath6kl_dbg(ATH6KL_DBG_SCATTER
,
636 "hif-scatter: total len: %d scatter entries: %d\n",
637 scat_req
->len
, scat_req
->scat_entries
);
639 if (request
& HIF_SYNCHRONOUS
)
640 status
= ath6kl_sdio_scat_rw(ar_sdio
, scat_req
->busrequest
);
642 spin_lock_bh(&ar_sdio
->wr_async_lock
);
643 list_add_tail(&scat_req
->busrequest
->list
, &ar_sdio
->wr_asyncq
);
644 spin_unlock_bh(&ar_sdio
->wr_async_lock
);
645 queue_work(ar
->ath6kl_wq
, &ar_sdio
->wr_async_work
);
651 /* clean up scatter support */
652 static void ath6kl_sdio_cleanup_scatter(struct ath6kl
*ar
)
654 struct ath6kl_sdio
*ar_sdio
= ath6kl_sdio_priv(ar
);
655 struct hif_scatter_req
*s_req
, *tmp_req
;
657 /* empty the free list */
658 spin_lock_bh(&ar_sdio
->scat_lock
);
659 list_for_each_entry_safe(s_req
, tmp_req
, &ar_sdio
->scat_req
, list
) {
660 list_del(&s_req
->list
);
661 spin_unlock_bh(&ar_sdio
->scat_lock
);
664 * FIXME: should we also call completion handler with
665 * ath6kl_hif_rw_comp_handler() with status -ECANCELED so
666 * that the packet is properly freed?
668 if (s_req
->busrequest
)
669 ath6kl_sdio_free_bus_req(ar_sdio
, s_req
->busrequest
);
670 kfree(s_req
->virt_dma_buf
);
671 kfree(s_req
->sgentries
);
674 spin_lock_bh(&ar_sdio
->scat_lock
);
676 spin_unlock_bh(&ar_sdio
->scat_lock
);
679 /* setup of HIF scatter resources */
680 static int ath6kl_sdio_enable_scatter(struct ath6kl
*ar
)
682 struct ath6kl_sdio
*ar_sdio
= ath6kl_sdio_priv(ar
);
683 struct htc_target
*target
= ar
->htc_target
;
685 bool virt_scat
= false;
687 if (ar_sdio
->scatter_enabled
)
690 ar_sdio
->scatter_enabled
= true;
692 /* check if host supports scatter and it meets our requirements */
693 if (ar_sdio
->func
->card
->host
->max_segs
< MAX_SCATTER_ENTRIES_PER_REQ
) {
694 ath6kl_err("host only supports scatter of :%d entries, need: %d\n",
695 ar_sdio
->func
->card
->host
->max_segs
,
696 MAX_SCATTER_ENTRIES_PER_REQ
);
701 ret
= ath6kl_sdio_alloc_prep_scat_req(ar_sdio
,
702 MAX_SCATTER_ENTRIES_PER_REQ
,
703 MAX_SCATTER_REQUESTS
, virt_scat
);
706 ath6kl_dbg(ATH6KL_DBG_BOOT
,
707 "hif-scatter enabled requests %d entries %d\n",
708 MAX_SCATTER_REQUESTS
,
709 MAX_SCATTER_ENTRIES_PER_REQ
);
711 target
->max_scat_entries
= MAX_SCATTER_ENTRIES_PER_REQ
;
712 target
->max_xfer_szper_scatreq
=
713 MAX_SCATTER_REQ_TRANSFER_SIZE
;
715 ath6kl_sdio_cleanup_scatter(ar
);
716 ath6kl_warn("hif scatter resource setup failed, trying virtual scatter method\n");
720 if (virt_scat
|| ret
) {
721 ret
= ath6kl_sdio_alloc_prep_scat_req(ar_sdio
,
722 ATH6KL_SCATTER_ENTRIES_PER_REQ
,
723 ATH6KL_SCATTER_REQS
, virt_scat
);
726 ath6kl_err("failed to alloc virtual scatter resources !\n");
727 ath6kl_sdio_cleanup_scatter(ar
);
731 ath6kl_dbg(ATH6KL_DBG_BOOT
,
732 "virtual scatter enabled requests %d entries %d\n",
733 ATH6KL_SCATTER_REQS
, ATH6KL_SCATTER_ENTRIES_PER_REQ
);
735 target
->max_scat_entries
= ATH6KL_SCATTER_ENTRIES_PER_REQ
;
736 target
->max_xfer_szper_scatreq
=
737 ATH6KL_MAX_TRANSFER_SIZE_PER_SCATTER
;
743 static int ath6kl_sdio_config(struct ath6kl
*ar
)
745 struct ath6kl_sdio
*ar_sdio
= ath6kl_sdio_priv(ar
);
746 struct sdio_func
*func
= ar_sdio
->func
;
749 sdio_claim_host(func
);
751 if ((ar_sdio
->id
->device
& MANUFACTURER_ID_ATH6KL_BASE_MASK
) >=
752 MANUFACTURER_ID_AR6003_BASE
) {
753 /* enable 4-bit ASYNC interrupt on AR6003 or later */
754 ret
= ath6kl_sdio_func0_cmd52_wr_byte(func
->card
,
755 CCCR_SDIO_IRQ_MODE_REG
,
756 SDIO_IRQ_MODE_ASYNC_4BIT_IRQ
);
758 ath6kl_err("Failed to enable 4-bit async irq mode %d\n",
763 ath6kl_dbg(ATH6KL_DBG_BOOT
, "4-bit async irq mode enabled\n");
766 /* give us some time to enable, in ms */
767 func
->enable_timeout
= 100;
769 ret
= sdio_set_block_size(func
, HIF_MBOX_BLOCK_SIZE
);
771 ath6kl_err("Set sdio block size %d failed: %d)\n",
772 HIF_MBOX_BLOCK_SIZE
, ret
);
777 sdio_release_host(func
);
782 static int ath6kl_set_sdio_pm_caps(struct ath6kl
*ar
)
784 struct ath6kl_sdio
*ar_sdio
= ath6kl_sdio_priv(ar
);
785 struct sdio_func
*func
= ar_sdio
->func
;
789 flags
= sdio_get_host_pm_caps(func
);
791 ath6kl_dbg(ATH6KL_DBG_SUSPEND
, "sdio suspend pm_caps 0x%x\n", flags
);
793 if (!(flags
& MMC_PM_WAKE_SDIO_IRQ
) ||
794 !(flags
& MMC_PM_KEEP_POWER
))
797 ret
= sdio_set_host_pm_flags(func
, MMC_PM_KEEP_POWER
);
799 ath6kl_err("set sdio keep pwr flag failed: %d\n", ret
);
803 /* sdio irq wakes up host */
804 ret
= sdio_set_host_pm_flags(func
, MMC_PM_WAKE_SDIO_IRQ
);
806 ath6kl_err("set sdio wake irq flag failed: %d\n", ret
);
811 static int ath6kl_sdio_suspend(struct ath6kl
*ar
, struct cfg80211_wowlan
*wow
)
813 struct ath6kl_sdio
*ar_sdio
= ath6kl_sdio_priv(ar
);
814 struct sdio_func
*func
= ar_sdio
->func
;
818 if (ar
->state
== ATH6KL_STATE_SCHED_SCAN
) {
819 ath6kl_dbg(ATH6KL_DBG_SUSPEND
, "sched scan is in progress\n");
821 ret
= ath6kl_set_sdio_pm_caps(ar
);
825 ret
= ath6kl_cfg80211_suspend(ar
,
826 ATH6KL_CFG_SUSPEND_SCHED_SCAN
,
834 if (ar
->suspend_mode
== WLAN_POWER_STATE_WOW
||
835 (!ar
->suspend_mode
&& wow
)) {
837 ret
= ath6kl_set_sdio_pm_caps(ar
);
841 ret
= ath6kl_cfg80211_suspend(ar
, ATH6KL_CFG_SUSPEND_WOW
, wow
);
848 if (ar
->suspend_mode
== WLAN_POWER_STATE_DEEP_SLEEP
||
851 flags
= sdio_get_host_pm_caps(func
);
852 if (!(flags
& MMC_PM_KEEP_POWER
))
855 ret
= sdio_set_host_pm_flags(func
, MMC_PM_KEEP_POWER
);
860 * Workaround to support Deep Sleep with MSM, set the host pm
861 * flag as MMC_PM_WAKE_SDIO_IRQ to allow SDCC deiver to disable
862 * the sdc2_clock and internally allows MSM to enter
863 * TCXO shutdown properly.
865 if ((flags
& MMC_PM_WAKE_SDIO_IRQ
)) {
866 ret
= sdio_set_host_pm_flags(func
,
867 MMC_PM_WAKE_SDIO_IRQ
);
872 ret
= ath6kl_cfg80211_suspend(ar
, ATH6KL_CFG_SUSPEND_DEEPSLEEP
,
881 return ath6kl_cfg80211_suspend(ar
, ATH6KL_CFG_SUSPEND_CUTPOWER
, NULL
);
884 static int ath6kl_sdio_resume(struct ath6kl
*ar
)
887 case ATH6KL_STATE_OFF
:
888 case ATH6KL_STATE_CUTPOWER
:
889 ath6kl_dbg(ATH6KL_DBG_SUSPEND
,
890 "sdio resume configuring sdio\n");
892 /* need to set sdio settings after power is cut from sdio */
893 ath6kl_sdio_config(ar
);
896 case ATH6KL_STATE_ON
:
899 case ATH6KL_STATE_DEEPSLEEP
:
902 case ATH6KL_STATE_WOW
:
904 case ATH6KL_STATE_SCHED_SCAN
:
908 ath6kl_cfg80211_resume(ar
);
913 /* set the window address register (using 4-byte register access ). */
914 static int ath6kl_set_addrwin_reg(struct ath6kl
*ar
, u32 reg_addr
, u32 addr
)
921 * Write bytes 1,2,3 of the register to set the upper address bytes,
922 * the LSB is written last to initiate the access cycle
925 for (i
= 1; i
<= 3; i
++) {
927 * Fill the buffer with the address byte value we want to
930 memset(addr_val
, ((u8
*)&addr
)[i
], 4);
933 * Hit each byte of the register address with a 4-byte
934 * write operation to the same address, this is a harmless
937 status
= ath6kl_sdio_read_write_sync(ar
, reg_addr
+ i
, addr_val
,
938 4, HIF_WR_SYNC_BYTE_FIX
);
944 ath6kl_err("%s: failed to write initial bytes of 0x%x "
945 "to window reg: 0x%X\n", __func__
,
951 * Write the address register again, this time write the whole
952 * 4-byte value. The effect here is that the LSB write causes the
953 * cycle to start, the extra 3 byte write to bytes 1,2,3 has no
954 * effect since we are writing the same values again
956 status
= ath6kl_sdio_read_write_sync(ar
, reg_addr
, (u8
*)(&addr
),
957 4, HIF_WR_SYNC_BYTE_INC
);
960 ath6kl_err("%s: failed to write 0x%x to window reg: 0x%X\n",
961 __func__
, addr
, reg_addr
);
968 static int ath6kl_sdio_diag_read32(struct ath6kl
*ar
, u32 address
, u32
*data
)
972 /* set window register to start read cycle */
973 status
= ath6kl_set_addrwin_reg(ar
, WINDOW_READ_ADDR_ADDRESS
,
980 status
= ath6kl_sdio_read_write_sync(ar
, WINDOW_DATA_ADDRESS
,
981 (u8
*)data
, sizeof(u32
), HIF_RD_SYNC_BYTE_INC
);
983 ath6kl_err("%s: failed to read from window data addr\n",
991 static int ath6kl_sdio_diag_write32(struct ath6kl
*ar
, u32 address
,
995 u32 val
= (__force u32
) data
;
998 status
= ath6kl_sdio_read_write_sync(ar
, WINDOW_DATA_ADDRESS
,
999 (u8
*) &val
, sizeof(u32
), HIF_WR_SYNC_BYTE_INC
);
1001 ath6kl_err("%s: failed to write 0x%x to window data addr\n",
1006 /* set window register, which starts the write cycle */
1007 return ath6kl_set_addrwin_reg(ar
, WINDOW_WRITE_ADDR_ADDRESS
,
1011 static int ath6kl_sdio_bmi_credits(struct ath6kl
*ar
)
1014 unsigned long timeout
;
1017 ar
->bmi
.cmd_credits
= 0;
1019 /* Read the counter register to get the command credits */
1020 addr
= COUNT_DEC_ADDRESS
+ (HTC_MAILBOX_NUM_MAX
+ ENDPOINT1
) * 4;
1022 timeout
= jiffies
+ msecs_to_jiffies(BMI_COMMUNICATION_TIMEOUT
);
1023 while (time_before(jiffies
, timeout
) && !ar
->bmi
.cmd_credits
) {
1026 * Hit the credit counter with a 4-byte access, the first byte
1027 * read will hit the counter and cause a decrement, while the
1028 * remaining 3 bytes has no effect. The rationale behind this
1029 * is to make all HIF accesses 4-byte aligned.
1031 ret
= ath6kl_sdio_read_write_sync(ar
, addr
,
1032 (u8
*)&ar
->bmi
.cmd_credits
, 4,
1033 HIF_RD_SYNC_BYTE_INC
);
1035 ath6kl_err("Unable to decrement the command credit "
1036 "count register: %d\n", ret
);
1040 /* The counter is only 8 bits.
1041 * Ignore anything in the upper 3 bytes
1043 ar
->bmi
.cmd_credits
&= 0xFF;
1046 if (!ar
->bmi
.cmd_credits
) {
1047 ath6kl_err("bmi communication timeout\n");
1054 static int ath6kl_bmi_get_rx_lkahd(struct ath6kl
*ar
)
1056 unsigned long timeout
;
1060 timeout
= jiffies
+ msecs_to_jiffies(BMI_COMMUNICATION_TIMEOUT
);
1061 while ((time_before(jiffies
, timeout
)) && !rx_word
) {
1062 ret
= ath6kl_sdio_read_write_sync(ar
,
1063 RX_LOOKAHEAD_VALID_ADDRESS
,
1064 (u8
*)&rx_word
, sizeof(rx_word
),
1065 HIF_RD_SYNC_BYTE_INC
);
1067 ath6kl_err("unable to read RX_LOOKAHEAD_VALID\n");
1071 /* all we really want is one bit */
1072 rx_word
&= (1 << ENDPOINT1
);
1076 ath6kl_err("bmi_recv_buf FIFO empty\n");
1083 static int ath6kl_sdio_bmi_write(struct ath6kl
*ar
, u8
*buf
, u32 len
)
1088 ret
= ath6kl_sdio_bmi_credits(ar
);
1092 addr
= ar
->mbox_info
.htc_addr
;
1094 ret
= ath6kl_sdio_read_write_sync(ar
, addr
, buf
, len
,
1095 HIF_WR_SYNC_BYTE_INC
);
1097 ath6kl_err("unable to send the bmi data to the device\n");
1102 static int ath6kl_sdio_bmi_read(struct ath6kl
*ar
, u8
*buf
, u32 len
)
1108 * During normal bootup, small reads may be required.
1109 * Rather than issue an HIF Read and then wait as the Target
1110 * adds successive bytes to the FIFO, we wait here until
1111 * we know that response data is available.
1113 * This allows us to cleanly timeout on an unexpected
1114 * Target failure rather than risk problems at the HIF level.
1115 * In particular, this avoids SDIO timeouts and possibly garbage
1116 * data on some host controllers. And on an interconnect
1117 * such as Compact Flash (as well as some SDIO masters) which
1118 * does not provide any indication on data timeout, it avoids
1119 * a potential hang or garbage response.
1121 * Synchronization is more difficult for reads larger than the
1122 * size of the MBOX FIFO (128B), because the Target is unable
1123 * to push the 129th byte of data until AFTER the Host posts an
1124 * HIF Read and removes some FIFO data. So for large reads the
1125 * Host proceeds to post an HIF Read BEFORE all the data is
1126 * actually available to read. Fortunately, large BMI reads do
1127 * not occur in practice -- they're supported for debug/development.
1129 * So Host/Target BMI synchronization is divided into these cases:
1130 * CASE 1: length < 4
1133 * CASE 2: 4 <= length <= 128
1134 * Wait for first 4 bytes to be in FIFO
1135 * If CONSERVATIVE_BMI_READ is enabled, also wait for
1136 * a BMI command credit, which indicates that the ENTIRE
1137 * response is available in the the FIFO
1139 * CASE 3: length > 128
1140 * Wait for the first 4 bytes to be in FIFO
1142 * For most uses, a small timeout should be sufficient and we will
1143 * usually see a response quickly; but there may be some unusual
1144 * (debug) cases of BMI_EXECUTE where we want an larger timeout.
1145 * For now, we use an unbounded busy loop while waiting for
1148 * If BMI_EXECUTE ever needs to support longer-latency execution,
1149 * especially in production, this code needs to be enhanced to sleep
1150 * and yield. Also note that BMI_COMMUNICATION_TIMEOUT is currently
1151 * a function of Host processor speed.
1153 if (len
>= 4) { /* NB: Currently, always true */
1154 ret
= ath6kl_bmi_get_rx_lkahd(ar
);
1159 addr
= ar
->mbox_info
.htc_addr
;
1160 ret
= ath6kl_sdio_read_write_sync(ar
, addr
, buf
, len
,
1161 HIF_RD_SYNC_BYTE_INC
);
1163 ath6kl_err("Unable to read the bmi data from the device: %d\n",
1171 static void ath6kl_sdio_stop(struct ath6kl
*ar
)
1173 struct ath6kl_sdio
*ar_sdio
= ath6kl_sdio_priv(ar
);
1174 struct bus_request
*req
, *tmp_req
;
1177 /* FIXME: make sure that wq is not queued again */
1179 cancel_work_sync(&ar_sdio
->wr_async_work
);
1181 spin_lock_bh(&ar_sdio
->wr_async_lock
);
1183 list_for_each_entry_safe(req
, tmp_req
, &ar_sdio
->wr_asyncq
, list
) {
1184 list_del(&req
->list
);
1186 if (req
->scat_req
) {
1187 /* this is a scatter gather request */
1188 req
->scat_req
->status
= -ECANCELED
;
1189 req
->scat_req
->complete(ar_sdio
->ar
->htc_target
,
1192 context
= req
->packet
;
1193 ath6kl_sdio_free_bus_req(ar_sdio
, req
);
1194 ath6kl_hif_rw_comp_handler(context
, -ECANCELED
);
1198 spin_unlock_bh(&ar_sdio
->wr_async_lock
);
1200 WARN_ON(get_queue_depth(&ar_sdio
->scat_req
) != 4);
1203 static const struct ath6kl_hif_ops ath6kl_sdio_ops
= {
1204 .read_write_sync
= ath6kl_sdio_read_write_sync
,
1205 .write_async
= ath6kl_sdio_write_async
,
1206 .irq_enable
= ath6kl_sdio_irq_enable
,
1207 .irq_disable
= ath6kl_sdio_irq_disable
,
1208 .scatter_req_get
= ath6kl_sdio_scatter_req_get
,
1209 .scatter_req_add
= ath6kl_sdio_scatter_req_add
,
1210 .enable_scatter
= ath6kl_sdio_enable_scatter
,
1211 .scat_req_rw
= ath6kl_sdio_async_rw_scatter
,
1212 .cleanup_scatter
= ath6kl_sdio_cleanup_scatter
,
1213 .suspend
= ath6kl_sdio_suspend
,
1214 .resume
= ath6kl_sdio_resume
,
1215 .diag_read32
= ath6kl_sdio_diag_read32
,
1216 .diag_write32
= ath6kl_sdio_diag_write32
,
1217 .bmi_read
= ath6kl_sdio_bmi_read
,
1218 .bmi_write
= ath6kl_sdio_bmi_write
,
1219 .power_on
= ath6kl_sdio_power_on
,
1220 .power_off
= ath6kl_sdio_power_off
,
1221 .stop
= ath6kl_sdio_stop
,
1224 #ifdef CONFIG_PM_SLEEP
1227 * Empty handlers so that mmc subsystem doesn't remove us entirely during
1228 * suspend. We instead follow cfg80211 suspend/resume handlers.
1230 static int ath6kl_sdio_pm_suspend(struct device
*device
)
1232 ath6kl_dbg(ATH6KL_DBG_SUSPEND
, "sdio pm suspend\n");
1237 static int ath6kl_sdio_pm_resume(struct device
*device
)
1239 ath6kl_dbg(ATH6KL_DBG_SUSPEND
, "sdio pm resume\n");
1244 static SIMPLE_DEV_PM_OPS(ath6kl_sdio_pm_ops
, ath6kl_sdio_pm_suspend
,
1245 ath6kl_sdio_pm_resume
);
1247 #define ATH6KL_SDIO_PM_OPS (&ath6kl_sdio_pm_ops)
1251 #define ATH6KL_SDIO_PM_OPS NULL
1253 #endif /* CONFIG_PM_SLEEP */
1255 static int ath6kl_sdio_probe(struct sdio_func
*func
,
1256 const struct sdio_device_id
*id
)
1259 struct ath6kl_sdio
*ar_sdio
;
1263 ath6kl_dbg(ATH6KL_DBG_BOOT
,
1264 "sdio new func %d vendor 0x%x device 0x%x block 0x%x/0x%x\n",
1265 func
->num
, func
->vendor
, func
->device
,
1266 func
->max_blksize
, func
->cur_blksize
);
1268 ar_sdio
= kzalloc(sizeof(struct ath6kl_sdio
), GFP_KERNEL
);
1272 ar_sdio
->dma_buffer
= kzalloc(HIF_DMA_BUFFER_SIZE
, GFP_KERNEL
);
1273 if (!ar_sdio
->dma_buffer
) {
1278 ar_sdio
->func
= func
;
1279 sdio_set_drvdata(func
, ar_sdio
);
1282 ar_sdio
->is_disabled
= true;
1284 spin_lock_init(&ar_sdio
->lock
);
1285 spin_lock_init(&ar_sdio
->scat_lock
);
1286 spin_lock_init(&ar_sdio
->wr_async_lock
);
1287 mutex_init(&ar_sdio
->dma_buffer_mutex
);
1288 mutex_init(&ar_sdio
->mtx_irq
);
1290 INIT_LIST_HEAD(&ar_sdio
->scat_req
);
1291 INIT_LIST_HEAD(&ar_sdio
->bus_req_freeq
);
1292 INIT_LIST_HEAD(&ar_sdio
->wr_asyncq
);
1294 INIT_WORK(&ar_sdio
->wr_async_work
, ath6kl_sdio_write_async_work
);
1296 for (count
= 0; count
< BUS_REQUEST_MAX_NUM
; count
++)
1297 ath6kl_sdio_free_bus_req(ar_sdio
, &ar_sdio
->bus_req
[count
]);
1299 ar
= ath6kl_core_create(&ar_sdio
->func
->dev
);
1301 ath6kl_err("Failed to alloc ath6kl core\n");
1307 ar
->hif_type
= ATH6KL_HIF_TYPE_SDIO
;
1308 ar
->hif_priv
= ar_sdio
;
1309 ar
->hif_ops
= &ath6kl_sdio_ops
;
1310 ar
->bmi
.max_data_size
= 256;
1312 ath6kl_sdio_set_mbox_info(ar
);
1314 ret
= ath6kl_sdio_config(ar
);
1316 ath6kl_err("Failed to config sdio: %d\n", ret
);
1317 goto err_core_alloc
;
1320 ret
= ath6kl_core_init(ar
);
1322 ath6kl_err("Failed to init ath6kl core\n");
1323 goto err_core_alloc
;
1329 ath6kl_core_destroy(ar_sdio
->ar
);
1331 kfree(ar_sdio
->dma_buffer
);
1338 static void ath6kl_sdio_remove(struct sdio_func
*func
)
1340 struct ath6kl_sdio
*ar_sdio
;
1342 ath6kl_dbg(ATH6KL_DBG_BOOT
,
1343 "sdio removed func %d vendor 0x%x device 0x%x\n",
1344 func
->num
, func
->vendor
, func
->device
);
1346 ar_sdio
= sdio_get_drvdata(func
);
1348 ath6kl_stop_txrx(ar_sdio
->ar
);
1349 cancel_work_sync(&ar_sdio
->wr_async_work
);
1351 ath6kl_core_cleanup(ar_sdio
->ar
);
1352 ath6kl_core_destroy(ar_sdio
->ar
);
1354 kfree(ar_sdio
->dma_buffer
);
1358 static const struct sdio_device_id ath6kl_sdio_devices
[] = {
1359 {SDIO_DEVICE(MANUFACTURER_CODE
, (MANUFACTURER_ID_AR6003_BASE
| 0x0))},
1360 {SDIO_DEVICE(MANUFACTURER_CODE
, (MANUFACTURER_ID_AR6003_BASE
| 0x1))},
1361 {SDIO_DEVICE(MANUFACTURER_CODE
, (MANUFACTURER_ID_AR6004_BASE
| 0x0))},
1362 {SDIO_DEVICE(MANUFACTURER_CODE
, (MANUFACTURER_ID_AR6004_BASE
| 0x1))},
1366 MODULE_DEVICE_TABLE(sdio
, ath6kl_sdio_devices
);
1368 static struct sdio_driver ath6kl_sdio_driver
= {
1369 .name
= "ath6kl_sdio",
1370 .id_table
= ath6kl_sdio_devices
,
1371 .probe
= ath6kl_sdio_probe
,
1372 .remove
= ath6kl_sdio_remove
,
1373 .drv
.pm
= ATH6KL_SDIO_PM_OPS
,
1376 static int __init
ath6kl_sdio_init(void)
1380 ret
= sdio_register_driver(&ath6kl_sdio_driver
);
1382 ath6kl_err("sdio driver registration failed: %d\n", ret
);
1387 static void __exit
ath6kl_sdio_exit(void)
1389 sdio_unregister_driver(&ath6kl_sdio_driver
);
1392 module_init(ath6kl_sdio_init
);
1393 module_exit(ath6kl_sdio_exit
);
1395 MODULE_AUTHOR("Atheros Communications, Inc.");
1396 MODULE_DESCRIPTION("Driver support for Atheros AR600x SDIO devices");
1397 MODULE_LICENSE("Dual BSD/GPL");
1399 MODULE_FIRMWARE(AR6003_HW_2_0_FW_DIR
"/" AR6003_HW_2_0_OTP_FILE
);
1400 MODULE_FIRMWARE(AR6003_HW_2_0_FW_DIR
"/" AR6003_HW_2_0_FIRMWARE_FILE
);
1401 MODULE_FIRMWARE(AR6003_HW_2_0_FW_DIR
"/" AR6003_HW_2_0_PATCH_FILE
);
1402 MODULE_FIRMWARE(AR6003_HW_2_0_BOARD_DATA_FILE
);
1403 MODULE_FIRMWARE(AR6003_HW_2_0_DEFAULT_BOARD_DATA_FILE
);
1404 MODULE_FIRMWARE(AR6003_HW_2_1_1_FW_DIR
"/" AR6003_HW_2_1_1_OTP_FILE
);
1405 MODULE_FIRMWARE(AR6003_HW_2_1_1_FW_DIR
"/" AR6003_HW_2_1_1_FIRMWARE_FILE
);
1406 MODULE_FIRMWARE(AR6003_HW_2_1_1_FW_DIR
"/" AR6003_HW_2_1_1_PATCH_FILE
);
1407 MODULE_FIRMWARE(AR6003_HW_2_1_1_BOARD_DATA_FILE
);
1408 MODULE_FIRMWARE(AR6003_HW_2_1_1_DEFAULT_BOARD_DATA_FILE
);
1409 MODULE_FIRMWARE(AR6004_HW_1_0_FW_DIR
"/" AR6004_HW_1_0_FIRMWARE_FILE
);
1410 MODULE_FIRMWARE(AR6004_HW_1_0_BOARD_DATA_FILE
);
1411 MODULE_FIRMWARE(AR6004_HW_1_0_DEFAULT_BOARD_DATA_FILE
);
1412 MODULE_FIRMWARE(AR6004_HW_1_1_FW_DIR
"/" AR6004_HW_1_1_FIRMWARE_FILE
);
1413 MODULE_FIRMWARE(AR6004_HW_1_1_BOARD_DATA_FILE
);
1414 MODULE_FIRMWARE(AR6004_HW_1_1_DEFAULT_BOARD_DATA_FILE
);