drivers/net/wireless/ath/ath9k/ani.c

   1 /*
   2  * Copyright (c) 2008-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/kernel.h>
  18 #include <linux/export.h>
  19 #include "hw.h"
  20 #include "hw-ops.h"
  21
  22 struct ani_ofdm_level_entry {
  23         int spur_immunity_level;
  24         int fir_step_level;
  25         int ofdm_weak_signal_on;
  26 };
  27
  28 /* values here are relative to the INI */
  29
  30 /*
  31  * Legend:
  32  *
  33  * SI: Spur immunity
  34  * FS: FIR Step
  35  * WS: OFDM / CCK Weak Signal detection
  36  * MRC-CCK: Maximal Ratio Combining for CCK
  37  */
  38
  39 static const struct ani_ofdm_level_entry ofdm_level_table[] = {
  40         /* SI  FS  WS */
  41         {  0,  0,  1  }, /* lvl 0 */
  42         {  1,  1,  1  }, /* lvl 1 */
  43         {  2,  2,  1  }, /* lvl 2 */
  44         {  3,  2,  1  }, /* lvl 3  (default) */
  45         {  4,  3,  1  }, /* lvl 4 */
  46         {  5,  4,  1  }, /* lvl 5 */
  47         {  6,  5,  1  }, /* lvl 6 */
  48         {  7,  6,  1  }, /* lvl 7 */
  49         {  7,  6,  0  }, /* lvl 8 */
  50         {  7,  7,  0  }  /* lvl 9 */
  51 };
  52 #define ATH9K_ANI_OFDM_NUM_LEVEL \
  53         ARRAY_SIZE(ofdm_level_table)
  54 #define ATH9K_ANI_OFDM_MAX_LEVEL \
  55         (ATH9K_ANI_OFDM_NUM_LEVEL-1)
  56 #define ATH9K_ANI_OFDM_DEF_LEVEL \
  57         3 /* default level - matches the INI settings */
  58
  59 /*
  60  * MRC (Maximal Ratio Combining) has always been used with multi-antenna ofdm.
  61  * With OFDM for single stream you just add up all antenna inputs, you're
  62  * only interested in what you get after FFT. Signal aligment is also not
  63  * required for OFDM because any phase difference adds up in the frequency
  64  * domain.
  65  *
  66  * MRC requires extra work for use with CCK. You need to align the antenna
  67  * signals from the different antenna before you can add the signals together.
  68  * You need aligment of signals as CCK is in time domain, so addition can cancel
  69  * your signal completely if phase is 180 degrees (think of adding sine waves).
  70  * You also need to remove noise before the addition and this is where ANI
  71  * MRC CCK comes into play. One of the antenna inputs may be stronger but
  72  * lower SNR, so just adding after alignment can be dangerous.
  73  *
  74  * Regardless of alignment in time, the antenna signals add constructively after
  75  * FFT and improve your reception. For more information:
  76  *
  77  * http://en.wikipedia.org/wiki/Maximal-ratio_combining
  78  */
  79
  80 struct ani_cck_level_entry {
  81         int fir_step_level;
  82         int mrc_cck_on;
  83 };
  84
  85 static const struct ani_cck_level_entry cck_level_table[] = {
  86         /* FS  MRC-CCK  */
  87         {  0,  1  }, /* lvl 0 */
  88         {  1,  1  }, /* lvl 1 */
  89         {  2,  1  }, /* lvl 2  (default) */
  90         {  3,  1  }, /* lvl 3 */
  91         {  4,  0  }, /* lvl 4 */
  92         {  5,  0  }, /* lvl 5 */
  93         {  6,  0  }, /* lvl 6 */
  94         {  6,  0  }, /* lvl 7 (only for high rssi) */
  95         {  7,  0  }  /* lvl 8 (only for high rssi) */
  96 };
  97
  98 #define ATH9K_ANI_CCK_NUM_LEVEL \
  99         ARRAY_SIZE(cck_level_table)
 100 #define ATH9K_ANI_CCK_MAX_LEVEL \
 101         (ATH9K_ANI_CCK_NUM_LEVEL-1)
 102 #define ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI \
 103         (ATH9K_ANI_CCK_NUM_LEVEL-3)
 104 #define ATH9K_ANI_CCK_DEF_LEVEL \
 105         2 /* default level - matches the INI settings */
 106
 107 static bool use_new_ani(struct ath_hw *ah)
 108 {
 109         return AR_SREV_9300_20_OR_LATER(ah) || modparam_force_new_ani;
 110 }
 111
 112 static void ath9k_hw_update_mibstats(struct ath_hw *ah,
 113                                      struct ath9k_mib_stats *stats)
 114 {
 115         stats->ackrcv_bad += REG_READ(ah, AR_ACK_FAIL);
 116         stats->rts_bad += REG_READ(ah, AR_RTS_FAIL);
 117         stats->fcs_bad += REG_READ(ah, AR_FCS_FAIL);
 118         stats->rts_good += REG_READ(ah, AR_RTS_OK);
 119         stats->beacons += REG_READ(ah, AR_BEACON_CNT);
 120 }
 121
 122 static void ath9k_ani_restart(struct ath_hw *ah)
 123 {
 124         struct ar5416AniState *aniState;
 125         struct ath_common *common = ath9k_hw_common(ah);
 126         u32 ofdm_base = 0, cck_base = 0;
 127
 128         if (!DO_ANI(ah))
 129                 return;
 130
 131         aniState = &ah->curchan->ani;
 132         aniState->listenTime = 0;
 133
 134         if (!use_new_ani(ah)) {
 135                 ofdm_base = AR_PHY_COUNTMAX - ah->config.ofdm_trig_high;
 136                 cck_base = AR_PHY_COUNTMAX - ah->config.cck_trig_high;
 137         }
 138
 139         ath_dbg(common, ANI, "Writing ofdmbase=%u   cckbase=%u\n",
 140                 ofdm_base, cck_base);
 141
 142         ENABLE_REGWRITE_BUFFER(ah);
 143
 144         REG_WRITE(ah, AR_PHY_ERR_1, ofdm_base);
 145         REG_WRITE(ah, AR_PHY_ERR_2, cck_base);
 146         REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
 147         REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
 148
 149         REGWRITE_BUFFER_FLUSH(ah);
 150
 151         ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
 152
 153         aniState->ofdmPhyErrCount = 0;
 154         aniState->cckPhyErrCount = 0;
 155 }
 156
 157 static void ath9k_hw_ani_ofdm_err_trigger_old(struct ath_hw *ah)
 158 {
 159         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
 160         struct ar5416AniState *aniState;
 161         int32_t rssi;
 162
 163         aniState = &ah->curchan->ani;
 164
 165         if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
 166                 if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
 167                                          aniState->noiseImmunityLevel + 1)) {
 168                         return;
 169                 }
 170         }
 171
 172         if (aniState->spurImmunityLevel < HAL_SPUR_IMMUNE_MAX) {
 173                 if (ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
 174                                          aniState->spurImmunityLevel + 1)) {
 175                         return;
 176                 }
 177         }
 178
 179         if (ah->opmode == NL80211_IFTYPE_AP) {
 180                 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
 181                         ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
 182                                              aniState->firstepLevel + 1);
 183                 }
 184                 return;
 185         }
 186         rssi = BEACON_RSSI(ah);
 187         if (rssi > aniState->rssiThrHigh) {
 188                 if (!aniState->ofdmWeakSigDetectOff) {
 189                         if (ath9k_hw_ani_control(ah,
 190                                          ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
 191                                          false)) {
 192                                 ath9k_hw_ani_control(ah,
 193                                         ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 0);
 194                                 return;
 195                         }
 196                 }
 197                 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
 198                         ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
 199                                              aniState->firstepLevel + 1);
 200                         return;
 201                 }
 202         } else if (rssi > aniState->rssiThrLow) {
 203                 if (aniState->ofdmWeakSigDetectOff)
 204                         ath9k_hw_ani_control(ah,
 205                                      ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
 206                                      true);
 207                 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX)
 208                         ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
 209                                              aniState->firstepLevel + 1);
 210                 return;
 211         } else {
 212                 if ((conf->channel->band == IEEE80211_BAND_2GHZ) &&
 213                     !conf_is_ht(conf)) {
 214                         if (!aniState->ofdmWeakSigDetectOff)
 215                                 ath9k_hw_ani_control(ah,
 216                                      ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
 217                                      false);
 218                         if (aniState->firstepLevel > 0)
 219                                 ath9k_hw_ani_control(ah,
 220                                              ATH9K_ANI_FIRSTEP_LEVEL, 0);
 221                         return;
 222                 }
 223         }
 224 }
 225
 226 static void ath9k_hw_ani_cck_err_trigger_old(struct ath_hw *ah)
 227 {
 228         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
 229         struct ar5416AniState *aniState;
 230         int32_t rssi;
 231
 232         aniState = &ah->curchan->ani;
 233         if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
 234                 if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
 235                                          aniState->noiseImmunityLevel + 1)) {
 236                         return;
 237                 }
 238         }
 239         if (ah->opmode == NL80211_IFTYPE_AP) {
 240                 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
 241                         ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
 242                                              aniState->firstepLevel + 1);
 243                 }
 244                 return;
 245         }
 246         rssi = BEACON_RSSI(ah);
 247         if (rssi > aniState->rssiThrLow) {
 248                 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX)
 249                         ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
 250                                              aniState->firstepLevel + 1);
 251         } else {
 252                 if ((conf->channel->band == IEEE80211_BAND_2GHZ) &&
 253                     !conf_is_ht(conf)) {
 254                         if (aniState->firstepLevel > 0)
 255                                 ath9k_hw_ani_control(ah,
 256                                              ATH9K_ANI_FIRSTEP_LEVEL, 0);
 257                 }
 258         }
 259 }
 260
 261 /* Adjust the OFDM Noise Immunity Level */
 262 static void ath9k_hw_set_ofdm_nil(struct ath_hw *ah, u8 immunityLevel)
 263 {
 264         struct ar5416AniState *aniState = &ah->curchan->ani;
 265         struct ath_common *common = ath9k_hw_common(ah);
 266         const struct ani_ofdm_level_entry *entry_ofdm;
 267         const struct ani_cck_level_entry *entry_cck;
 268
 269         aniState->noiseFloor = BEACON_RSSI(ah);
 270
 271         ath_dbg(common, ANI, "**** ofdmlevel %d=>%d, rssi=%d[lo=%d hi=%d]\n",
 272                 aniState->ofdmNoiseImmunityLevel,
 273                 immunityLevel, aniState->noiseFloor,
 274                 aniState->rssiThrLow, aniState->rssiThrHigh);
 275
 276         if (aniState->update_ani)
 277                 aniState->ofdmNoiseImmunityLevel =
 278                         (immunityLevel > ATH9K_ANI_OFDM_DEF_LEVEL) ?
 279                         immunityLevel : ATH9K_ANI_OFDM_DEF_LEVEL;
 280
 281         entry_ofdm = &ofdm_level_table[aniState->ofdmNoiseImmunityLevel];
 282         entry_cck = &cck_level_table[aniState->cckNoiseImmunityLevel];
 283
 284         if (aniState->spurImmunityLevel != entry_ofdm->spur_immunity_level)
 285                 ath9k_hw_ani_control(ah,
 286                                      ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
 287                                      entry_ofdm->spur_immunity_level);
 288
 289         if (aniState->firstepLevel != entry_ofdm->fir_step_level &&
 290             entry_ofdm->fir_step_level >= entry_cck->fir_step_level)
 291                 ath9k_hw_ani_control(ah,
 292                                      ATH9K_ANI_FIRSTEP_LEVEL,
 293                                      entry_ofdm->fir_step_level);
 294
 295         if ((aniState->noiseFloor >= aniState->rssiThrHigh) &&
 296             (!aniState->ofdmWeakSigDetectOff !=
 297              entry_ofdm->ofdm_weak_signal_on)) {
 298                         ath9k_hw_ani_control(ah,
 299                                 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
 300                                 entry_ofdm->ofdm_weak_signal_on);
 301         }
 302 }
 303
 304 static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hw *ah)
 305 {
 306         struct ar5416AniState *aniState;
 307
 308         if (!DO_ANI(ah))
 309                 return;
 310
 311         if (!use_new_ani(ah)) {
 312                 ath9k_hw_ani_ofdm_err_trigger_old(ah);
 313                 return;
 314         }
 315
 316         aniState = &ah->curchan->ani;
 317
 318         if (aniState->ofdmNoiseImmunityLevel < ATH9K_ANI_OFDM_MAX_LEVEL)
 319                 ath9k_hw_set_ofdm_nil(ah, aniState->ofdmNoiseImmunityLevel + 1);
 320 }
 321
 322 /*
 323  * Set the ANI settings to match an CCK level.
 324  */
 325 static void ath9k_hw_set_cck_nil(struct ath_hw *ah, u_int8_t immunityLevel)
 326 {
 327         struct ar5416AniState *aniState = &ah->curchan->ani;
 328         struct ath_common *common = ath9k_hw_common(ah);
 329         const struct ani_ofdm_level_entry *entry_ofdm;
 330         const struct ani_cck_level_entry *entry_cck;
 331
 332         aniState->noiseFloor = BEACON_RSSI(ah);
 333         ath_dbg(common, ANI, "**** ccklevel %d=>%d, rssi=%d[lo=%d hi=%d]\n",
 334                 aniState->cckNoiseImmunityLevel, immunityLevel,
 335                 aniState->noiseFloor, aniState->rssiThrLow,
 336                 aniState->rssiThrHigh);
 337
 338         if ((ah->opmode == NL80211_IFTYPE_STATION ||
 339              ah->opmode == NL80211_IFTYPE_ADHOC) &&
 340             aniState->noiseFloor <= aniState->rssiThrLow &&
 341             immunityLevel > ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI)
 342                 immunityLevel = ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI;
 343
 344         if (aniState->update_ani)
 345                 aniState->cckNoiseImmunityLevel =
 346                         (immunityLevel > ATH9K_ANI_CCK_DEF_LEVEL) ?
 347                         immunityLevel : ATH9K_ANI_CCK_DEF_LEVEL;
 348
 349         entry_ofdm = &ofdm_level_table[aniState->ofdmNoiseImmunityLevel];
 350         entry_cck = &cck_level_table[aniState->cckNoiseImmunityLevel];
 351
 352         if (aniState->firstepLevel != entry_cck->fir_step_level &&
 353             entry_cck->fir_step_level >= entry_ofdm->fir_step_level)
 354                 ath9k_hw_ani_control(ah,
 355                                      ATH9K_ANI_FIRSTEP_LEVEL,
 356                                      entry_cck->fir_step_level);
 357
 358         /* Skip MRC CCK for pre AR9003 families */
 359         if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9485(ah))
 360                 return;
 361
 362         if (aniState->mrcCCKOff == entry_cck->mrc_cck_on)
 363                 ath9k_hw_ani_control(ah,
 364                                      ATH9K_ANI_MRC_CCK,
 365                                      entry_cck->mrc_cck_on);
 366 }
 367
 368 static void ath9k_hw_ani_cck_err_trigger(struct ath_hw *ah)
 369 {
 370         struct ar5416AniState *aniState;
 371
 372         if (!DO_ANI(ah))
 373                 return;
 374
 375         if (!use_new_ani(ah)) {
 376                 ath9k_hw_ani_cck_err_trigger_old(ah);
 377                 return;
 378         }
 379
 380         aniState = &ah->curchan->ani;
 381
 382         if (aniState->cckNoiseImmunityLevel < ATH9K_ANI_CCK_MAX_LEVEL)
 383                 ath9k_hw_set_cck_nil(ah, aniState->cckNoiseImmunityLevel + 1);
 384 }
 385
 386 static void ath9k_hw_ani_lower_immunity_old(struct ath_hw *ah)
 387 {
 388         struct ar5416AniState *aniState;
 389         int32_t rssi;
 390
 391         aniState = &ah->curchan->ani;
 392
 393         if (ah->opmode == NL80211_IFTYPE_AP) {
 394                 if (aniState->firstepLevel > 0) {
 395                         if (ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
 396                                                  aniState->firstepLevel - 1))
 397                                 return;
 398                 }
 399         } else {
 400                 rssi = BEACON_RSSI(ah);
 401                 if (rssi > aniState->rssiThrHigh) {
 402                         /* XXX: Handle me */
 403                 } else if (rssi > aniState->rssiThrLow) {
 404                         if (aniState->ofdmWeakSigDetectOff) {
 405                                 if (ath9k_hw_ani_control(ah,
 406                                          ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
 407                                          true))
 408                                         return;
 409                         }
 410                         if (aniState->firstepLevel > 0) {
 411                                 if (ath9k_hw_ani_control(ah,
 412                                          ATH9K_ANI_FIRSTEP_LEVEL,
 413                                          aniState->firstepLevel - 1))
 414                                         return;
 415                         }
 416                 } else {
 417                         if (aniState->firstepLevel > 0) {
 418                                 if (ath9k_hw_ani_control(ah,
 419                                          ATH9K_ANI_FIRSTEP_LEVEL,
 420                                          aniState->firstepLevel - 1))
 421                                         return;
 422                         }
 423                 }
 424         }
 425
 426         if (aniState->spurImmunityLevel > 0) {
 427                 if (ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
 428                                          aniState->spurImmunityLevel - 1))
 429                         return;
 430         }
 431
 432         if (aniState->noiseImmunityLevel > 0) {
 433                 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
 434                                      aniState->noiseImmunityLevel - 1);
 435                 return;
 436         }
 437 }
 438
 439 /*
 440  * only lower either OFDM or CCK errors per turn
 441  * we lower the other one next time
 442  */
 443 static void ath9k_hw_ani_lower_immunity(struct ath_hw *ah)
 444 {
 445         struct ar5416AniState *aniState;
 446
 447         aniState = &ah->curchan->ani;
 448
 449         if (!use_new_ani(ah)) {
 450                 ath9k_hw_ani_lower_immunity_old(ah);
 451                 return;
 452         }
 453
 454         /* lower OFDM noise immunity */
 455         if (aniState->ofdmNoiseImmunityLevel > 0 &&
 456             (aniState->ofdmsTurn || aniState->cckNoiseImmunityLevel == 0)) {
 457                 ath9k_hw_set_ofdm_nil(ah, aniState->ofdmNoiseImmunityLevel - 1);
 458                 return;
 459         }
 460
 461         /* lower CCK noise immunity */
 462         if (aniState->cckNoiseImmunityLevel > 0)
 463                 ath9k_hw_set_cck_nil(ah, aniState->cckNoiseImmunityLevel - 1);
 464 }
 465
 466 static void ath9k_ani_reset_old(struct ath_hw *ah, bool is_scanning)
 467 {
 468         struct ar5416AniState *aniState;
 469         struct ath9k_channel *chan = ah->curchan;
 470         struct ath_common *common = ath9k_hw_common(ah);
 471
 472         if (!DO_ANI(ah))
 473                 return;
 474
 475         aniState = &ah->curchan->ani;
 476
 477         if (ah->opmode != NL80211_IFTYPE_STATION
 478             && ah->opmode != NL80211_IFTYPE_ADHOC) {
 479                 ath_dbg(common, ANI, "Reset ANI state opmode %u\n", ah->opmode);
 480                 ah->stats.ast_ani_reset++;
 481
 482                 if (ah->opmode == NL80211_IFTYPE_AP) {
 483                         /*
 484                          * ath9k_hw_ani_control() will only process items set on
 485                          * ah->ani_function
 486                          */
 487                         if (IS_CHAN_2GHZ(chan))
 488                                 ah->ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
 489                                                     ATH9K_ANI_FIRSTEP_LEVEL);
 490                         else
 491                                 ah->ani_function = 0;
 492                 }
 493
 494                 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 0);
 495                 ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 0);
 496                 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, 0);
 497                 ath9k_hw_ani_control(ah, ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
 498                                      !ATH9K_ANI_USE_OFDM_WEAK_SIG);
 499                 ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR,
 500                                      ATH9K_ANI_CCK_WEAK_SIG_THR);
 501
 502                 ath9k_ani_restart(ah);
 503                 return;
 504         }
 505
 506         if (aniState->noiseImmunityLevel != 0)
 507                 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
 508                                      aniState->noiseImmunityLevel);
 509         if (aniState->spurImmunityLevel != 0)
 510                 ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
 511                                      aniState->spurImmunityLevel);
 512         if (aniState->ofdmWeakSigDetectOff)
 513                 ath9k_hw_ani_control(ah, ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
 514                                      !aniState->ofdmWeakSigDetectOff);
 515         if (aniState->cckWeakSigThreshold)
 516                 ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR,
 517                                      aniState->cckWeakSigThreshold);
 518         if (aniState->firstepLevel != 0)
 519                 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
 520                                      aniState->firstepLevel);
 521
 522         ath9k_ani_restart(ah);
 523
 524         ENABLE_REGWRITE_BUFFER(ah);
 525
 526         REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
 527         REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
 528
 529         REGWRITE_BUFFER_FLUSH(ah);
 530 }
 531
 532 /*
 533  * Restore the ANI parameters in the HAL and reset the statistics.
 534  * This routine should be called for every hardware reset and for
 535  * every channel change.
 536  */
 537 void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning)
 538 {
 539         struct ar5416AniState *aniState = &ah->curchan->ani;
 540         struct ath9k_channel *chan = ah->curchan;
 541         struct ath_common *common = ath9k_hw_common(ah);
 542
 543         if (!DO_ANI(ah))
 544                 return;
 545
 546         if (!use_new_ani(ah))
 547                 return ath9k_ani_reset_old(ah, is_scanning);
 548
 549         BUG_ON(aniState == NULL);
 550         ah->stats.ast_ani_reset++;
 551
 552         /* only allow a subset of functions in AP mode */
 553         if (ah->opmode == NL80211_IFTYPE_AP) {
 554                 if (IS_CHAN_2GHZ(chan)) {
 555                         ah->ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
 556                                             ATH9K_ANI_FIRSTEP_LEVEL);
 557                         if (AR_SREV_9300_20_OR_LATER(ah))
 558                                 ah->ani_function |= ATH9K_ANI_MRC_CCK;
 559                 } else
 560                         ah->ani_function = 0;
 561         }
 562
 563         /* always allow mode (on/off) to be controlled */
 564         ah->ani_function |= ATH9K_ANI_MODE;
 565
 566         if (is_scanning ||
 567             (ah->opmode != NL80211_IFTYPE_STATION &&
 568              ah->opmode != NL80211_IFTYPE_ADHOC)) {
 569                 /*
 570                  * If we're scanning or in AP mode, the defaults (ini)
 571                  * should be in place. For an AP we assume the historical
 572                  * levels for this channel are probably outdated so start
 573                  * from defaults instead.
 574                  */
 575                 if (aniState->ofdmNoiseImmunityLevel !=
 576                     ATH9K_ANI_OFDM_DEF_LEVEL ||
 577                     aniState->cckNoiseImmunityLevel !=
 578                     ATH9K_ANI_CCK_DEF_LEVEL) {
 579                         ath_dbg(common, ANI,
 580                                 "Restore defaults: opmode %u chan %d Mhz/0x%x is_scanning=%d ofdm:%d cck:%d\n",
 581                                 ah->opmode,
 582                                 chan->channel,
 583                                 chan->channelFlags,
 584                                 is_scanning,
 585                                 aniState->ofdmNoiseImmunityLevel,
 586                                 aniState->cckNoiseImmunityLevel);
 587
 588                         aniState->update_ani = false;
 589                         ath9k_hw_set_ofdm_nil(ah, ATH9K_ANI_OFDM_DEF_LEVEL);
 590                         ath9k_hw_set_cck_nil(ah, ATH9K_ANI_CCK_DEF_LEVEL);
 591                 }
 592         } else {
 593                 /*
 594                  * restore historical levels for this channel
 595                  */
 596                 ath_dbg(common, ANI,
 597                         "Restore history: opmode %u chan %d Mhz/0x%x is_scanning=%d ofdm:%d cck:%d\n",
 598                         ah->opmode,
 599                         chan->channel,
 600                         chan->channelFlags,
 601                         is_scanning,
 602                         aniState->ofdmNoiseImmunityLevel,
 603                         aniState->cckNoiseImmunityLevel);
 604
 605                         aniState->update_ani = true;
 606                         ath9k_hw_set_ofdm_nil(ah,
 607                                               aniState->ofdmNoiseImmunityLevel);
 608                         ath9k_hw_set_cck_nil(ah,
 609                                              aniState->cckNoiseImmunityLevel);
 610         }
 611
 612         /*
 613          * enable phy counters if hw supports or if not, enable phy
 614          * interrupts (so we can count each one)
 615          */
 616         ath9k_ani_restart(ah);
 617
 618         ENABLE_REGWRITE_BUFFER(ah);
 619
 620         REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
 621         REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
 622
 623         REGWRITE_BUFFER_FLUSH(ah);
 624 }
 625
 626 static bool ath9k_hw_ani_read_counters(struct ath_hw *ah)
 627 {
 628         struct ath_common *common = ath9k_hw_common(ah);
 629         struct ar5416AniState *aniState = &ah->curchan->ani;
 630         u32 ofdm_base = 0;
 631         u32 cck_base = 0;
 632         u32 ofdmPhyErrCnt, cckPhyErrCnt;
 633         u32 phyCnt1, phyCnt2;
 634         int32_t listenTime;
 635
 636         ath_hw_cycle_counters_update(common);
 637         listenTime = ath_hw_get_listen_time(common);
 638
 639         if (listenTime <= 0) {
 640                 ah->stats.ast_ani_lneg_or_lzero++;
 641                 ath9k_ani_restart(ah);
 642                 return false;
 643         }
 644
 645         if (!use_new_ani(ah)) {
 646                 ofdm_base = AR_PHY_COUNTMAX - ah->config.ofdm_trig_high;
 647                 cck_base = AR_PHY_COUNTMAX - ah->config.cck_trig_high;
 648         }
 649
 650         aniState->listenTime += listenTime;
 651
 652         ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
 653
 654         phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
 655         phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
 656
 657         if (!use_new_ani(ah) && (phyCnt1 < ofdm_base || phyCnt2 < cck_base)) {
 658                 if (phyCnt1 < ofdm_base) {
 659                         ath_dbg(common, ANI,
 660                                 "phyCnt1 0x%x, resetting counter value to 0x%x\n",
 661                                 phyCnt1, ofdm_base);
 662                         REG_WRITE(ah, AR_PHY_ERR_1, ofdm_base);
 663                         REG_WRITE(ah, AR_PHY_ERR_MASK_1,
 664                                   AR_PHY_ERR_OFDM_TIMING);
 665                 }
 666                 if (phyCnt2 < cck_base) {
 667                         ath_dbg(common, ANI,
 668                                 "phyCnt2 0x%x, resetting counter value to 0x%x\n",
 669                                 phyCnt2, cck_base);
 670                         REG_WRITE(ah, AR_PHY_ERR_2, cck_base);
 671                         REG_WRITE(ah, AR_PHY_ERR_MASK_2,
 672                                   AR_PHY_ERR_CCK_TIMING);
 673                 }
 674                 return false;
 675         }
 676
 677         ofdmPhyErrCnt = phyCnt1 - ofdm_base;
 678         ah->stats.ast_ani_ofdmerrs +=
 679                 ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
 680         aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
 681
 682         cckPhyErrCnt = phyCnt2 - cck_base;
 683         ah->stats.ast_ani_cckerrs +=
 684                 cckPhyErrCnt - aniState->cckPhyErrCount;
 685         aniState->cckPhyErrCount = cckPhyErrCnt;
 686         return true;
 687 }
 688
 689 void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan)
 690 {
 691         struct ar5416AniState *aniState;
 692         struct ath_common *common = ath9k_hw_common(ah);
 693         u32 ofdmPhyErrRate, cckPhyErrRate;
 694
 695         if (!DO_ANI(ah))
 696                 return;
 697
 698         aniState = &ah->curchan->ani;
 699         if (WARN_ON(!aniState))
 700                 return;
 701
 702         if (!ath9k_hw_ani_read_counters(ah))
 703                 return;
 704
 705         ofdmPhyErrRate = aniState->ofdmPhyErrCount * 1000 /
 706                          aniState->listenTime;
 707         cckPhyErrRate =  aniState->cckPhyErrCount * 1000 /
 708                          aniState->listenTime;
 709
 710         ath_dbg(common, ANI,
 711                 "listenTime=%d OFDM:%d errs=%d/s CCK:%d errs=%d/s ofdm_turn=%d\n",
 712                 aniState->listenTime,
 713                 aniState->ofdmNoiseImmunityLevel,
 714                 ofdmPhyErrRate, aniState->cckNoiseImmunityLevel,
 715                 cckPhyErrRate, aniState->ofdmsTurn);
 716
 717         if (aniState->listenTime > ah->aniperiod) {
 718                 if (cckPhyErrRate < ah->config.cck_trig_low &&
 719                     ((ofdmPhyErrRate < ah->config.ofdm_trig_low &&
 720                       aniState->ofdmNoiseImmunityLevel <
 721                       ATH9K_ANI_OFDM_DEF_LEVEL) ||
 722                      (ofdmPhyErrRate < ATH9K_ANI_OFDM_TRIG_LOW_ABOVE_INI &&
 723                       aniState->ofdmNoiseImmunityLevel >=
 724                       ATH9K_ANI_OFDM_DEF_LEVEL))) {
 725                         ath9k_hw_ani_lower_immunity(ah);
 726                         aniState->ofdmsTurn = !aniState->ofdmsTurn;
 727                 } else if ((ofdmPhyErrRate > ah->config.ofdm_trig_high &&
 728                             aniState->ofdmNoiseImmunityLevel >=
 729                             ATH9K_ANI_OFDM_DEF_LEVEL) ||
 730                            (ofdmPhyErrRate >
 731                             ATH9K_ANI_OFDM_TRIG_HIGH_BELOW_INI &&
 732                             aniState->ofdmNoiseImmunityLevel <
 733                             ATH9K_ANI_OFDM_DEF_LEVEL)) {
 734                         ath9k_hw_ani_ofdm_err_trigger(ah);
 735                         aniState->ofdmsTurn = false;
 736                 } else if (cckPhyErrRate > ah->config.cck_trig_high) {
 737                         ath9k_hw_ani_cck_err_trigger(ah);
 738                         aniState->ofdmsTurn = true;
 739                 }
 740                 ath9k_ani_restart(ah);
 741         }
 742 }
 743 EXPORT_SYMBOL(ath9k_hw_ani_monitor);
 744
 745 void ath9k_enable_mib_counters(struct ath_hw *ah)
 746 {
 747         struct ath_common *common = ath9k_hw_common(ah);
 748
 749         ath_dbg(common, ANI, "Enable MIB counters\n");
 750
 751         ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
 752
 753         ENABLE_REGWRITE_BUFFER(ah);
 754
 755         REG_WRITE(ah, AR_FILT_OFDM, 0);
 756         REG_WRITE(ah, AR_FILT_CCK, 0);
 757         REG_WRITE(ah, AR_MIBC,
 758                   ~(AR_MIBC_COW | AR_MIBC_FMC | AR_MIBC_CMC | AR_MIBC_MCS)
 759                   & 0x0f);
 760         REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
 761         REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
 762
 763         REGWRITE_BUFFER_FLUSH(ah);
 764 }
 765
 766 /* Freeze the MIB counters, get the stats and then clear them */
 767 void ath9k_hw_disable_mib_counters(struct ath_hw *ah)
 768 {
 769         struct ath_common *common = ath9k_hw_common(ah);
 770
 771         ath_dbg(common, ANI, "Disable MIB counters\n");
 772
 773         REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC);
 774         ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
 775         REG_WRITE(ah, AR_MIBC, AR_MIBC_CMC);
 776         REG_WRITE(ah, AR_FILT_OFDM, 0);
 777         REG_WRITE(ah, AR_FILT_CCK, 0);
 778 }
 779 EXPORT_SYMBOL(ath9k_hw_disable_mib_counters);
 780
 781 /*
 782  * Process a MIB interrupt.  We may potentially be invoked because
 783  * any of the MIB counters overflow/trigger so don't assume we're
 784  * here because a PHY error counter triggered.
 785  */
 786 void ath9k_hw_proc_mib_event(struct ath_hw *ah)
 787 {
 788         u32 phyCnt1, phyCnt2;
 789
 790         /* Reset these counters regardless */
 791         REG_WRITE(ah, AR_FILT_OFDM, 0);
 792         REG_WRITE(ah, AR_FILT_CCK, 0);
 793         if (!(REG_READ(ah, AR_SLP_MIB_CTRL) & AR_SLP_MIB_PENDING))
 794                 REG_WRITE(ah, AR_SLP_MIB_CTRL, AR_SLP_MIB_CLEAR);
 795
 796         /* Clear the mib counters and save them in the stats */
 797         ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
 798
 799         if (!DO_ANI(ah)) {
 800                 /*
 801                  * We must always clear the interrupt cause by
 802                  * resetting the phy error regs.
 803                  */
 804                 REG_WRITE(ah, AR_PHY_ERR_1, 0);
 805                 REG_WRITE(ah, AR_PHY_ERR_2, 0);
 806                 return;
 807         }
 808
 809         /* NB: these are not reset-on-read */
 810         phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
 811         phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
 812         if (((phyCnt1 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK) ||
 813             ((phyCnt2 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK)) {
 814
 815                 if (!use_new_ani(ah))
 816                         ath9k_hw_ani_read_counters(ah);
 817
 818                 /* NB: always restart to insure the h/w counters are reset */
 819                 ath9k_ani_restart(ah);
 820         }
 821 }
 822 EXPORT_SYMBOL(ath9k_hw_proc_mib_event);
 823
 824 void ath9k_hw_ani_setup(struct ath_hw *ah)
 825 {
 826         int i;
 827
 828         static const int totalSizeDesired[] = { -55, -55, -55, -55, -62 };
 829         static const int coarseHigh[] = { -14, -14, -14, -14, -12 };
 830         static const int coarseLow[] = { -64, -64, -64, -64, -70 };
 831         static const int firpwr[] = { -78, -78, -78, -78, -80 };
 832
 833         for (i = 0; i < 5; i++) {
 834                 ah->totalSizeDesired[i] = totalSizeDesired[i];
 835                 ah->coarse_high[i] = coarseHigh[i];
 836                 ah->coarse_low[i] = coarseLow[i];
 837                 ah->firpwr[i] = firpwr[i];
 838         }
 839 }
 840
 841 void ath9k_hw_ani_init(struct ath_hw *ah)
 842 {
 843         struct ath_common *common = ath9k_hw_common(ah);
 844         int i;
 845
 846         ath_dbg(common, ANI, "Initialize ANI\n");
 847
 848         if (use_new_ani(ah)) {
 849                 ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH_NEW;
 850                 ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW_NEW;
 851
 852                 ah->config.cck_trig_high = ATH9K_ANI_CCK_TRIG_HIGH_NEW;
 853                 ah->config.cck_trig_low = ATH9K_ANI_CCK_TRIG_LOW_NEW;
 854         } else {
 855                 ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH_OLD;
 856                 ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW_OLD;
 857
 858                 ah->config.cck_trig_high = ATH9K_ANI_CCK_TRIG_HIGH_OLD;
 859                 ah->config.cck_trig_low = ATH9K_ANI_CCK_TRIG_LOW_OLD;
 860         }
 861
 862         for (i = 0; i < ARRAY_SIZE(ah->channels); i++) {
 863                 struct ath9k_channel *chan = &ah->channels[i];
 864                 struct ar5416AniState *ani = &chan->ani;
 865
 866                 if (use_new_ani(ah)) {
 867                         ani->spurImmunityLevel =
 868                                 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW;
 869
 870                         ani->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW;
 871
 872                         if (AR_SREV_9300_20_OR_LATER(ah))
 873                                 ani->mrcCCKOff =
 874                                         !ATH9K_ANI_ENABLE_MRC_CCK;
 875                         else
 876                                 ani->mrcCCKOff = true;
 877
 878                         ani->ofdmsTurn = true;
 879                 } else {
 880                         ani->spurImmunityLevel =
 881                                 ATH9K_ANI_SPUR_IMMUNE_LVL_OLD;
 882                         ani->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_OLD;
 883
 884                         ani->cckWeakSigThreshold =
 885                                 ATH9K_ANI_CCK_WEAK_SIG_THR;
 886                 }
 887
 888                 ani->rssiThrHigh = ATH9K_ANI_RSSI_THR_HIGH;
 889                 ani->rssiThrLow = ATH9K_ANI_RSSI_THR_LOW;
 890                 ani->ofdmWeakSigDetectOff =
 891                         !ATH9K_ANI_USE_OFDM_WEAK_SIG;
 892                 ani->cckNoiseImmunityLevel = ATH9K_ANI_CCK_DEF_LEVEL;
 893                 ani->ofdmNoiseImmunityLevel = ATH9K_ANI_OFDM_DEF_LEVEL;
 894                 ani->update_ani = false;
 895         }
 896
 897         /*
 898          * since we expect some ongoing maintenance on the tables, let's sanity
 899          * check here default level should not modify INI setting.
 900          */
 901         if (use_new_ani(ah)) {
 902                 ah->aniperiod = ATH9K_ANI_PERIOD_NEW;
 903                 ah->config.ani_poll_interval = ATH9K_ANI_POLLINTERVAL_NEW;
 904         } else {
 905                 ah->aniperiod = ATH9K_ANI_PERIOD_OLD;
 906                 ah->config.ani_poll_interval = ATH9K_ANI_POLLINTERVAL_OLD;
 907         }
 908
 909         if (ah->config.enable_ani)
 910                 ah->proc_phyerr |= HAL_PROCESS_ANI;
 911
 912         ath9k_ani_restart(ah);
 913         ath9k_enable_mib_counters(ah);
 914 }