2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "ar9002_phy.h"
22 /* All code below is for AR5008, AR9001, AR9002 */
24 static const int firstep_table
[] =
25 /* level: 0 1 2 3 4 5 6 7 8 */
26 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */
28 static const int cycpwrThr1_table
[] =
29 /* level: 0 1 2 3 4 5 6 7 8 */
30 { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */
33 * register values to turn OFDM weak signal detection OFF
35 static const int m1ThreshLow_off
= 127;
36 static const int m2ThreshLow_off
= 127;
37 static const int m1Thresh_off
= 127;
38 static const int m2Thresh_off
= 127;
39 static const int m2CountThr_off
= 31;
40 static const int m2CountThrLow_off
= 63;
41 static const int m1ThreshLowExt_off
= 127;
42 static const int m2ThreshLowExt_off
= 127;
43 static const int m1ThreshExt_off
= 127;
44 static const int m2ThreshExt_off
= 127;
47 static void ar5008_rf_bank_setup(u32
*bank
, struct ar5416IniArray
*array
,
52 for (i
= 0; i
< array
->ia_rows
; i
++)
53 bank
[i
] = INI_RA(array
, i
, col
);
57 #define REG_WRITE_RF_ARRAY(iniarray, regData, regWr) \
58 ar5008_write_rf_array(ah, iniarray, regData, &(regWr))
60 static void ar5008_write_rf_array(struct ath_hw
*ah
, struct ar5416IniArray
*array
,
61 u32
*data
, unsigned int *writecnt
)
65 ENABLE_REGWRITE_BUFFER(ah
);
67 for (r
= 0; r
< array
->ia_rows
; r
++) {
68 REG_WRITE(ah
, INI_RA(array
, r
, 0), data
[r
]);
72 REGWRITE_BUFFER_FLUSH(ah
);
76 * ar5008_hw_phy_modify_rx_buffer() - perform analog swizzling of parameters
83 * Performs analog "swizzling" of parameters into their location.
84 * Used on external AR2133/AR5133 radios.
86 static void ar5008_hw_phy_modify_rx_buffer(u32
*rfBuf
, u32 reg32
,
87 u32 numBits
, u32 firstBit
,
90 u32 tmp32
, mask
, arrayEntry
, lastBit
;
91 int32_t bitPosition
, bitsLeft
;
93 tmp32
= ath9k_hw_reverse_bits(reg32
, numBits
);
94 arrayEntry
= (firstBit
- 1) / 8;
95 bitPosition
= (firstBit
- 1) % 8;
97 while (bitsLeft
> 0) {
98 lastBit
= (bitPosition
+ bitsLeft
> 8) ?
99 8 : bitPosition
+ bitsLeft
;
100 mask
= (((1 << lastBit
) - 1) ^ ((1 << bitPosition
) - 1)) <<
102 rfBuf
[arrayEntry
] &= ~mask
;
103 rfBuf
[arrayEntry
] |= ((tmp32
<< bitPosition
) <<
104 (column
* 8)) & mask
;
105 bitsLeft
-= 8 - bitPosition
;
106 tmp32
= tmp32
>> (8 - bitPosition
);
113 * Fix on 2.4 GHz band for orientation sensitivity issue by increasing
119 * if synth_freq < 2412
121 * else if 2412 <= synth_freq <= 2422
123 * else // synth_freq > 2422
125 * else if forceBias > 0
126 * bias = forceBias & 7
128 * no change, use value from ini file
130 * no change, invalid band
133 * 2422 also uses value of 2
137 * Less than 2412 uses value of 0, 2412 and above uses value of 2
139 static void ar5008_hw_force_bias(struct ath_hw
*ah
, u16 synth_freq
)
141 struct ath_common
*common
= ath9k_hw_common(ah
);
146 if (!AR_SREV_5416(ah
) || synth_freq
>= 3000)
149 BUG_ON(AR_SREV_9280_20_OR_LATER(ah
));
151 if (synth_freq
< 2412)
153 else if (synth_freq
< 2422)
158 /* pre-reverse this field */
159 tmp_reg
= ath9k_hw_reverse_bits(new_bias
, 3);
161 ath_dbg(common
, CONFIG
, "Force rf_pwd_icsyndiv to %1d on %4d\n",
162 new_bias
, synth_freq
);
164 /* swizzle rf_pwd_icsyndiv */
165 ar5008_hw_phy_modify_rx_buffer(ah
->analogBank6Data
, tmp_reg
, 3, 181, 3);
167 /* write Bank 6 with new params */
168 REG_WRITE_RF_ARRAY(&ah
->iniBank6
, ah
->analogBank6Data
, reg_writes
);
172 * ar5008_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios
173 * @ah: atheros hardware structure
176 * For the external AR2133/AR5133 radios, takes the MHz channel value and set
177 * the channel value. Assumes writes enabled to analog bus and bank6 register
178 * cache in ah->analogBank6Data.
180 static int ar5008_hw_set_channel(struct ath_hw
*ah
, struct ath9k_channel
*chan
)
182 struct ath_common
*common
= ath9k_hw_common(ah
);
188 struct chan_centers centers
;
190 ath9k_hw_get_channel_centers(ah
, chan
, ¢ers
);
191 freq
= centers
.synth_center
;
196 if (((freq
- 2192) % 5) == 0) {
197 channelSel
= ((freq
- 672) * 2 - 3040) / 10;
199 } else if (((freq
- 2224) % 5) == 0) {
200 channelSel
= ((freq
- 704) * 2 - 3040) / 10;
203 ath_err(common
, "Invalid channel %u MHz\n", freq
);
207 channelSel
= (channelSel
<< 2) & 0xff;
208 channelSel
= ath9k_hw_reverse_bits(channelSel
, 8);
210 txctl
= REG_READ(ah
, AR_PHY_CCK_TX_CTRL
);
213 REG_WRITE(ah
, AR_PHY_CCK_TX_CTRL
,
214 txctl
| AR_PHY_CCK_TX_CTRL_JAPAN
);
216 REG_WRITE(ah
, AR_PHY_CCK_TX_CTRL
,
217 txctl
& ~AR_PHY_CCK_TX_CTRL_JAPAN
);
220 } else if ((freq
% 20) == 0 && freq
>= 5120) {
222 ath9k_hw_reverse_bits(((freq
- 4800) / 20 << 2), 8);
223 aModeRefSel
= ath9k_hw_reverse_bits(1, 2);
224 } else if ((freq
% 10) == 0) {
226 ath9k_hw_reverse_bits(((freq
- 4800) / 10 << 1), 8);
227 if (AR_SREV_9100(ah
) || AR_SREV_9160_10_OR_LATER(ah
))
228 aModeRefSel
= ath9k_hw_reverse_bits(2, 2);
230 aModeRefSel
= ath9k_hw_reverse_bits(1, 2);
231 } else if ((freq
% 5) == 0) {
232 channelSel
= ath9k_hw_reverse_bits((freq
- 4800) / 5, 8);
233 aModeRefSel
= ath9k_hw_reverse_bits(1, 2);
235 ath_err(common
, "Invalid channel %u MHz\n", freq
);
239 ar5008_hw_force_bias(ah
, freq
);
242 (channelSel
<< 8) | (aModeRefSel
<< 2) | (bModeSynth
<< 1) |
245 REG_WRITE(ah
, AR_PHY(0x37), reg32
);
253 * ar5008_hw_spur_mitigate - convert baseband spur frequency for external radios
254 * @ah: atheros hardware structure
257 * For non single-chip solutions. Converts to baseband spur frequency given the
258 * input channel frequency and compute register settings below.
260 static void ar5008_hw_spur_mitigate(struct ath_hw
*ah
,
261 struct ath9k_channel
*chan
)
263 int bb_spur
= AR_NO_SPUR
;
266 int spur_delta_phase
;
268 int upper
, lower
, cur_vit_mask
;
271 static int pilot_mask_reg
[4] = {
272 AR_PHY_TIMING7
, AR_PHY_TIMING8
,
273 AR_PHY_PILOT_MASK_01_30
, AR_PHY_PILOT_MASK_31_60
275 static int chan_mask_reg
[4] = {
276 AR_PHY_TIMING9
, AR_PHY_TIMING10
,
277 AR_PHY_CHANNEL_MASK_01_30
, AR_PHY_CHANNEL_MASK_31_60
279 static int inc
[4] = { 0, 100, 0, 0 };
286 bool is2GHz
= IS_CHAN_2GHZ(chan
);
288 memset(&mask_m
, 0, sizeof(int8_t) * 123);
289 memset(&mask_p
, 0, sizeof(int8_t) * 123);
291 for (i
= 0; i
< AR_EEPROM_MODAL_SPURS
; i
++) {
292 cur_bb_spur
= ah
->eep_ops
->get_spur_channel(ah
, i
, is2GHz
);
293 if (AR_NO_SPUR
== cur_bb_spur
)
295 cur_bb_spur
= cur_bb_spur
- (chan
->channel
* 10);
296 if ((cur_bb_spur
> -95) && (cur_bb_spur
< 95)) {
297 bb_spur
= cur_bb_spur
;
302 if (AR_NO_SPUR
== bb_spur
)
307 tmp
= REG_READ(ah
, AR_PHY_TIMING_CTRL4(0));
308 new = tmp
| (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI
|
309 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER
|
310 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK
|
311 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK
);
313 REG_WRITE(ah
, AR_PHY_TIMING_CTRL4(0), new);
315 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL
|
316 AR_PHY_SPUR_REG_ENABLE_MASK_PPM
|
317 AR_PHY_SPUR_REG_MASK_RATE_SELECT
|
318 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI
|
319 SM(SPUR_RSSI_THRESH
, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH
));
320 REG_WRITE(ah
, AR_PHY_SPUR_REG
, new);
322 spur_delta_phase
= ((bb_spur
* 524288) / 100) &
323 AR_PHY_TIMING11_SPUR_DELTA_PHASE
;
325 denominator
= IS_CHAN_2GHZ(chan
) ? 440 : 400;
326 spur_freq_sd
= ((bb_spur
* 2048) / denominator
) & 0x3ff;
328 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC
|
329 SM(spur_freq_sd
, AR_PHY_TIMING11_SPUR_FREQ_SD
) |
330 SM(spur_delta_phase
, AR_PHY_TIMING11_SPUR_DELTA_PHASE
));
331 REG_WRITE(ah
, AR_PHY_TIMING11
, new);
337 for (i
= 0; i
< 4; i
++) {
341 for (bp
= 0; bp
< 30; bp
++) {
342 if ((cur_bin
> lower
) && (cur_bin
< upper
)) {
343 pilot_mask
= pilot_mask
| 0x1 << bp
;
344 chan_mask
= chan_mask
| 0x1 << bp
;
349 REG_WRITE(ah
, pilot_mask_reg
[i
], pilot_mask
);
350 REG_WRITE(ah
, chan_mask_reg
[i
], chan_mask
);
357 for (i
= 0; i
< 123; i
++) {
358 if ((cur_vit_mask
> lower
) && (cur_vit_mask
< upper
)) {
360 /* workaround for gcc bug #37014 */
361 volatile int tmp_v
= abs(cur_vit_mask
- bin
);
367 if (cur_vit_mask
< 0)
368 mask_m
[abs(cur_vit_mask
/ 100)] = mask_amt
;
370 mask_p
[cur_vit_mask
/ 100] = mask_amt
;
375 tmp_mask
= (mask_m
[46] << 30) | (mask_m
[47] << 28)
376 | (mask_m
[48] << 26) | (mask_m
[49] << 24)
377 | (mask_m
[50] << 22) | (mask_m
[51] << 20)
378 | (mask_m
[52] << 18) | (mask_m
[53] << 16)
379 | (mask_m
[54] << 14) | (mask_m
[55] << 12)
380 | (mask_m
[56] << 10) | (mask_m
[57] << 8)
381 | (mask_m
[58] << 6) | (mask_m
[59] << 4)
382 | (mask_m
[60] << 2) | (mask_m
[61] << 0);
383 REG_WRITE(ah
, AR_PHY_BIN_MASK_1
, tmp_mask
);
384 REG_WRITE(ah
, AR_PHY_VIT_MASK2_M_46_61
, tmp_mask
);
386 tmp_mask
= (mask_m
[31] << 28)
387 | (mask_m
[32] << 26) | (mask_m
[33] << 24)
388 | (mask_m
[34] << 22) | (mask_m
[35] << 20)
389 | (mask_m
[36] << 18) | (mask_m
[37] << 16)
390 | (mask_m
[48] << 14) | (mask_m
[39] << 12)
391 | (mask_m
[40] << 10) | (mask_m
[41] << 8)
392 | (mask_m
[42] << 6) | (mask_m
[43] << 4)
393 | (mask_m
[44] << 2) | (mask_m
[45] << 0);
394 REG_WRITE(ah
, AR_PHY_BIN_MASK_2
, tmp_mask
);
395 REG_WRITE(ah
, AR_PHY_MASK2_M_31_45
, tmp_mask
);
397 tmp_mask
= (mask_m
[16] << 30) | (mask_m
[16] << 28)
398 | (mask_m
[18] << 26) | (mask_m
[18] << 24)
399 | (mask_m
[20] << 22) | (mask_m
[20] << 20)
400 | (mask_m
[22] << 18) | (mask_m
[22] << 16)
401 | (mask_m
[24] << 14) | (mask_m
[24] << 12)
402 | (mask_m
[25] << 10) | (mask_m
[26] << 8)
403 | (mask_m
[27] << 6) | (mask_m
[28] << 4)
404 | (mask_m
[29] << 2) | (mask_m
[30] << 0);
405 REG_WRITE(ah
, AR_PHY_BIN_MASK_3
, tmp_mask
);
406 REG_WRITE(ah
, AR_PHY_MASK2_M_16_30
, tmp_mask
);
408 tmp_mask
= (mask_m
[0] << 30) | (mask_m
[1] << 28)
409 | (mask_m
[2] << 26) | (mask_m
[3] << 24)
410 | (mask_m
[4] << 22) | (mask_m
[5] << 20)
411 | (mask_m
[6] << 18) | (mask_m
[7] << 16)
412 | (mask_m
[8] << 14) | (mask_m
[9] << 12)
413 | (mask_m
[10] << 10) | (mask_m
[11] << 8)
414 | (mask_m
[12] << 6) | (mask_m
[13] << 4)
415 | (mask_m
[14] << 2) | (mask_m
[15] << 0);
416 REG_WRITE(ah
, AR_PHY_MASK_CTL
, tmp_mask
);
417 REG_WRITE(ah
, AR_PHY_MASK2_M_00_15
, tmp_mask
);
419 tmp_mask
= (mask_p
[15] << 28)
420 | (mask_p
[14] << 26) | (mask_p
[13] << 24)
421 | (mask_p
[12] << 22) | (mask_p
[11] << 20)
422 | (mask_p
[10] << 18) | (mask_p
[9] << 16)
423 | (mask_p
[8] << 14) | (mask_p
[7] << 12)
424 | (mask_p
[6] << 10) | (mask_p
[5] << 8)
425 | (mask_p
[4] << 6) | (mask_p
[3] << 4)
426 | (mask_p
[2] << 2) | (mask_p
[1] << 0);
427 REG_WRITE(ah
, AR_PHY_BIN_MASK2_1
, tmp_mask
);
428 REG_WRITE(ah
, AR_PHY_MASK2_P_15_01
, tmp_mask
);
430 tmp_mask
= (mask_p
[30] << 28)
431 | (mask_p
[29] << 26) | (mask_p
[28] << 24)
432 | (mask_p
[27] << 22) | (mask_p
[26] << 20)
433 | (mask_p
[25] << 18) | (mask_p
[24] << 16)
434 | (mask_p
[23] << 14) | (mask_p
[22] << 12)
435 | (mask_p
[21] << 10) | (mask_p
[20] << 8)
436 | (mask_p
[19] << 6) | (mask_p
[18] << 4)
437 | (mask_p
[17] << 2) | (mask_p
[16] << 0);
438 REG_WRITE(ah
, AR_PHY_BIN_MASK2_2
, tmp_mask
);
439 REG_WRITE(ah
, AR_PHY_MASK2_P_30_16
, tmp_mask
);
441 tmp_mask
= (mask_p
[45] << 28)
442 | (mask_p
[44] << 26) | (mask_p
[43] << 24)
443 | (mask_p
[42] << 22) | (mask_p
[41] << 20)
444 | (mask_p
[40] << 18) | (mask_p
[39] << 16)
445 | (mask_p
[38] << 14) | (mask_p
[37] << 12)
446 | (mask_p
[36] << 10) | (mask_p
[35] << 8)
447 | (mask_p
[34] << 6) | (mask_p
[33] << 4)
448 | (mask_p
[32] << 2) | (mask_p
[31] << 0);
449 REG_WRITE(ah
, AR_PHY_BIN_MASK2_3
, tmp_mask
);
450 REG_WRITE(ah
, AR_PHY_MASK2_P_45_31
, tmp_mask
);
452 tmp_mask
= (mask_p
[61] << 30) | (mask_p
[60] << 28)
453 | (mask_p
[59] << 26) | (mask_p
[58] << 24)
454 | (mask_p
[57] << 22) | (mask_p
[56] << 20)
455 | (mask_p
[55] << 18) | (mask_p
[54] << 16)
456 | (mask_p
[53] << 14) | (mask_p
[52] << 12)
457 | (mask_p
[51] << 10) | (mask_p
[50] << 8)
458 | (mask_p
[49] << 6) | (mask_p
[48] << 4)
459 | (mask_p
[47] << 2) | (mask_p
[46] << 0);
460 REG_WRITE(ah
, AR_PHY_BIN_MASK2_4
, tmp_mask
);
461 REG_WRITE(ah
, AR_PHY_MASK2_P_61_45
, tmp_mask
);
465 * ar5008_hw_rf_alloc_ext_banks - allocates banks for external radio programming
466 * @ah: atheros hardware structure
468 * Only required for older devices with external AR2133/AR5133 radios.
470 static int ar5008_hw_rf_alloc_ext_banks(struct ath_hw
*ah
)
472 #define ATH_ALLOC_BANK(bank, size) do { \
473 bank = kzalloc((sizeof(u32) * size), GFP_KERNEL); \
475 ath_err(common, "Cannot allocate RF banks\n"); \
480 struct ath_common
*common
= ath9k_hw_common(ah
);
482 BUG_ON(AR_SREV_9280_20_OR_LATER(ah
));
484 ATH_ALLOC_BANK(ah
->analogBank0Data
, ah
->iniBank0
.ia_rows
);
485 ATH_ALLOC_BANK(ah
->analogBank1Data
, ah
->iniBank1
.ia_rows
);
486 ATH_ALLOC_BANK(ah
->analogBank2Data
, ah
->iniBank2
.ia_rows
);
487 ATH_ALLOC_BANK(ah
->analogBank3Data
, ah
->iniBank3
.ia_rows
);
488 ATH_ALLOC_BANK(ah
->analogBank6Data
, ah
->iniBank6
.ia_rows
);
489 ATH_ALLOC_BANK(ah
->analogBank6TPCData
, ah
->iniBank6TPC
.ia_rows
);
490 ATH_ALLOC_BANK(ah
->analogBank7Data
, ah
->iniBank7
.ia_rows
);
491 ATH_ALLOC_BANK(ah
->bank6Temp
, ah
->iniBank6
.ia_rows
);
494 #undef ATH_ALLOC_BANK
499 * ar5008_hw_rf_free_ext_banks - Free memory for analog bank scratch buffers
500 * @ah: atheros hardware struture
501 * For the external AR2133/AR5133 radios banks.
503 static void ar5008_hw_rf_free_ext_banks(struct ath_hw
*ah
)
505 #define ATH_FREE_BANK(bank) do { \
510 BUG_ON(AR_SREV_9280_20_OR_LATER(ah
));
512 ATH_FREE_BANK(ah
->analogBank0Data
);
513 ATH_FREE_BANK(ah
->analogBank1Data
);
514 ATH_FREE_BANK(ah
->analogBank2Data
);
515 ATH_FREE_BANK(ah
->analogBank3Data
);
516 ATH_FREE_BANK(ah
->analogBank6Data
);
517 ATH_FREE_BANK(ah
->analogBank6TPCData
);
518 ATH_FREE_BANK(ah
->analogBank7Data
);
519 ATH_FREE_BANK(ah
->bank6Temp
);
525 * ar5008_hw_set_rf_regs - programs rf registers based on EEPROM
526 * @ah: atheros hardware structure
530 * Used for the external AR2133/AR5133 radios.
532 * Reads the EEPROM header info from the device structure and programs
533 * all rf registers. This routine requires access to the analog
534 * rf device. This is not required for single-chip devices.
536 static bool ar5008_hw_set_rf_regs(struct ath_hw
*ah
,
537 struct ath9k_channel
*chan
,
541 u32 ob5GHz
= 0, db5GHz
= 0;
542 u32 ob2GHz
= 0, db2GHz
= 0;
546 * Software does not need to program bank data
547 * for single chip devices, that is AR9280 or anything
550 if (AR_SREV_9280_20_OR_LATER(ah
))
553 /* Setup rf parameters */
554 eepMinorRev
= ah
->eep_ops
->get_eeprom(ah
, EEP_MINOR_REV
);
556 /* Setup Bank 0 Write */
557 ar5008_rf_bank_setup(ah
->analogBank0Data
, &ah
->iniBank0
, 1);
559 /* Setup Bank 1 Write */
560 ar5008_rf_bank_setup(ah
->analogBank1Data
, &ah
->iniBank1
, 1);
562 /* Setup Bank 2 Write */
563 ar5008_rf_bank_setup(ah
->analogBank2Data
, &ah
->iniBank2
, 1);
565 /* Setup Bank 6 Write */
566 ar5008_rf_bank_setup(ah
->analogBank3Data
, &ah
->iniBank3
,
570 for (i
= 0; i
< ah
->iniBank6TPC
.ia_rows
; i
++) {
571 ah
->analogBank6Data
[i
] =
572 INI_RA(&ah
->iniBank6TPC
, i
, modesIndex
);
576 /* Only the 5 or 2 GHz OB/DB need to be set for a mode */
577 if (eepMinorRev
>= 2) {
578 if (IS_CHAN_2GHZ(chan
)) {
579 ob2GHz
= ah
->eep_ops
->get_eeprom(ah
, EEP_OB_2
);
580 db2GHz
= ah
->eep_ops
->get_eeprom(ah
, EEP_DB_2
);
581 ar5008_hw_phy_modify_rx_buffer(ah
->analogBank6Data
,
583 ar5008_hw_phy_modify_rx_buffer(ah
->analogBank6Data
,
586 ob5GHz
= ah
->eep_ops
->get_eeprom(ah
, EEP_OB_5
);
587 db5GHz
= ah
->eep_ops
->get_eeprom(ah
, EEP_DB_5
);
588 ar5008_hw_phy_modify_rx_buffer(ah
->analogBank6Data
,
590 ar5008_hw_phy_modify_rx_buffer(ah
->analogBank6Data
,
595 /* Setup Bank 7 Setup */
596 ar5008_rf_bank_setup(ah
->analogBank7Data
, &ah
->iniBank7
, 1);
598 /* Write Analog registers */
599 REG_WRITE_RF_ARRAY(&ah
->iniBank0
, ah
->analogBank0Data
,
601 REG_WRITE_RF_ARRAY(&ah
->iniBank1
, ah
->analogBank1Data
,
603 REG_WRITE_RF_ARRAY(&ah
->iniBank2
, ah
->analogBank2Data
,
605 REG_WRITE_RF_ARRAY(&ah
->iniBank3
, ah
->analogBank3Data
,
607 REG_WRITE_RF_ARRAY(&ah
->iniBank6TPC
, ah
->analogBank6Data
,
609 REG_WRITE_RF_ARRAY(&ah
->iniBank7
, ah
->analogBank7Data
,
615 static void ar5008_hw_init_bb(struct ath_hw
*ah
,
616 struct ath9k_channel
*chan
)
620 synthDelay
= REG_READ(ah
, AR_PHY_RX_DELAY
) & AR_PHY_RX_DELAY_DELAY
;
622 REG_WRITE(ah
, AR_PHY_ACTIVE
, AR_PHY_ACTIVE_EN
);
624 ath9k_hw_synth_delay(ah
, chan
, synthDelay
);
627 static void ar5008_hw_init_chain_masks(struct ath_hw
*ah
)
629 int rx_chainmask
, tx_chainmask
;
631 rx_chainmask
= ah
->rxchainmask
;
632 tx_chainmask
= ah
->txchainmask
;
635 switch (rx_chainmask
) {
637 REG_SET_BIT(ah
, AR_PHY_ANALOG_SWAP
,
638 AR_PHY_SWAP_ALT_CHAIN
);
640 if (ah
->hw_version
.macVersion
== AR_SREV_REVISION_5416_10
) {
641 REG_WRITE(ah
, AR_PHY_RX_CHAINMASK
, 0x7);
642 REG_WRITE(ah
, AR_PHY_CAL_CHAINMASK
, 0x7);
648 ENABLE_REGWRITE_BUFFER(ah
);
649 REG_WRITE(ah
, AR_PHY_RX_CHAINMASK
, rx_chainmask
);
650 REG_WRITE(ah
, AR_PHY_CAL_CHAINMASK
, rx_chainmask
);
653 ENABLE_REGWRITE_BUFFER(ah
);
657 REG_WRITE(ah
, AR_SELFGEN_MASK
, tx_chainmask
);
659 REGWRITE_BUFFER_FLUSH(ah
);
661 if (tx_chainmask
== 0x5) {
662 REG_SET_BIT(ah
, AR_PHY_ANALOG_SWAP
,
663 AR_PHY_SWAP_ALT_CHAIN
);
665 if (AR_SREV_9100(ah
))
666 REG_WRITE(ah
, AR_PHY_ANALOG_SWAP
,
667 REG_READ(ah
, AR_PHY_ANALOG_SWAP
) | 0x00000001);
670 static void ar5008_hw_override_ini(struct ath_hw
*ah
,
671 struct ath9k_channel
*chan
)
676 * Set the RX_ABORT and RX_DIS and clear if off only after
677 * RXE is set for MAC. This prevents frames with corrupted
680 REG_SET_BIT(ah
, AR_DIAG_SW
, (AR_DIAG_RX_DIS
| AR_DIAG_RX_ABORT
));
682 if (AR_SREV_9280_20_OR_LATER(ah
)) {
683 val
= REG_READ(ah
, AR_PCU_MISC_MODE2
);
685 if (!AR_SREV_9271(ah
))
686 val
&= ~AR_PCU_MISC_MODE2_HWWAR1
;
688 if (AR_SREV_9287_11_OR_LATER(ah
))
689 val
= val
& (~AR_PCU_MISC_MODE2_HWWAR2
);
691 REG_WRITE(ah
, AR_PCU_MISC_MODE2
, val
);
694 REG_SET_BIT(ah
, AR_PHY_CCK_DETECT
,
695 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV
);
697 if (AR_SREV_9280_20_OR_LATER(ah
))
700 * Disable BB clock gating
701 * Necessary to avoid issues on AR5416 2.0
703 REG_WRITE(ah
, 0x9800 + (651 << 2), 0x11);
706 * Disable RIFS search on some chips to avoid baseband
709 if (AR_SREV_9100(ah
) || AR_SREV_9160(ah
)) {
710 val
= REG_READ(ah
, AR_PHY_HEAVY_CLIP_FACTOR_RIFS
);
711 val
&= ~AR_PHY_RIFS_INIT_DELAY
;
712 REG_WRITE(ah
, AR_PHY_HEAVY_CLIP_FACTOR_RIFS
, val
);
716 static void ar5008_hw_set_channel_regs(struct ath_hw
*ah
,
717 struct ath9k_channel
*chan
)
720 u32 enableDacFifo
= 0;
722 if (AR_SREV_9285_12_OR_LATER(ah
))
723 enableDacFifo
= (REG_READ(ah
, AR_PHY_TURBO
) &
724 AR_PHY_FC_ENABLE_DAC_FIFO
);
726 phymode
= AR_PHY_FC_HT_EN
| AR_PHY_FC_SHORT_GI_40
727 | AR_PHY_FC_SINGLE_HT_LTF1
| AR_PHY_FC_WALSH
| enableDacFifo
;
729 if (IS_CHAN_HT40(chan
)) {
730 phymode
|= AR_PHY_FC_DYN2040_EN
;
732 if ((chan
->chanmode
== CHANNEL_A_HT40PLUS
) ||
733 (chan
->chanmode
== CHANNEL_G_HT40PLUS
))
734 phymode
|= AR_PHY_FC_DYN2040_PRI_CH
;
737 REG_WRITE(ah
, AR_PHY_TURBO
, phymode
);
739 ath9k_hw_set11nmac2040(ah
);
741 ENABLE_REGWRITE_BUFFER(ah
);
743 REG_WRITE(ah
, AR_GTXTO
, 25 << AR_GTXTO_TIMEOUT_LIMIT_S
);
744 REG_WRITE(ah
, AR_CST
, 0xF << AR_CST_TIMEOUT_LIMIT_S
);
746 REGWRITE_BUFFER_FLUSH(ah
);
750 static int ar5008_hw_process_ini(struct ath_hw
*ah
,
751 struct ath9k_channel
*chan
)
753 struct ath_common
*common
= ath9k_hw_common(ah
);
754 int i
, regWrites
= 0;
755 u32 modesIndex
, freqIndex
;
757 switch (chan
->chanmode
) {
763 case CHANNEL_A_HT40PLUS
:
764 case CHANNEL_A_HT40MINUS
:
774 case CHANNEL_G_HT40PLUS
:
775 case CHANNEL_G_HT40MINUS
:
785 * Set correct baseband to analog shift setting to
786 * access analog chips.
788 REG_WRITE(ah
, AR_PHY(0), 0x00000007);
790 /* Write ADDAC shifts */
791 REG_WRITE(ah
, AR_PHY_ADC_SERIAL_CTL
, AR_PHY_SEL_EXTERNAL_RADIO
);
792 if (ah
->eep_ops
->set_addac
)
793 ah
->eep_ops
->set_addac(ah
, chan
);
795 REG_WRITE_ARRAY(&ah
->iniAddac
, 1, regWrites
);
796 REG_WRITE(ah
, AR_PHY_ADC_SERIAL_CTL
, AR_PHY_SEL_INTERNAL_ADDAC
);
798 ENABLE_REGWRITE_BUFFER(ah
);
800 for (i
= 0; i
< ah
->iniModes
.ia_rows
; i
++) {
801 u32 reg
= INI_RA(&ah
->iniModes
, i
, 0);
802 u32 val
= INI_RA(&ah
->iniModes
, i
, modesIndex
);
804 if (reg
== AR_AN_TOP2
&& ah
->need_an_top2_fixup
)
805 val
&= ~AR_AN_TOP2_PWDCLKIND
;
807 REG_WRITE(ah
, reg
, val
);
809 if (reg
>= 0x7800 && reg
< 0x78a0
810 && ah
->config
.analog_shiftreg
811 && (common
->bus_ops
->ath_bus_type
!= ATH_USB
)) {
818 REGWRITE_BUFFER_FLUSH(ah
);
820 if (AR_SREV_9280(ah
) || AR_SREV_9287_11_OR_LATER(ah
))
821 REG_WRITE_ARRAY(&ah
->iniModesRxGain
, modesIndex
, regWrites
);
823 if (AR_SREV_9280(ah
) || AR_SREV_9285_12_OR_LATER(ah
) ||
824 AR_SREV_9287_11_OR_LATER(ah
))
825 REG_WRITE_ARRAY(&ah
->iniModesTxGain
, modesIndex
, regWrites
);
827 if (AR_SREV_9271_10(ah
)) {
828 REG_SET_BIT(ah
, AR_PHY_SPECTRAL_SCAN
, AR_PHY_SPECTRAL_SCAN_ENA
);
829 REG_RMW_FIELD(ah
, AR_PHY_RF_CTL3
, AR_PHY_TX_END_TO_ADC_ON
, 0xa);
832 ENABLE_REGWRITE_BUFFER(ah
);
834 /* Write common array parameters */
835 for (i
= 0; i
< ah
->iniCommon
.ia_rows
; i
++) {
836 u32 reg
= INI_RA(&ah
->iniCommon
, i
, 0);
837 u32 val
= INI_RA(&ah
->iniCommon
, i
, 1);
839 REG_WRITE(ah
, reg
, val
);
841 if (reg
>= 0x7800 && reg
< 0x78a0
842 && ah
->config
.analog_shiftreg
843 && (common
->bus_ops
->ath_bus_type
!= ATH_USB
)) {
850 REGWRITE_BUFFER_FLUSH(ah
);
852 REG_WRITE_ARRAY(&ah
->iniBB_RfGain
, freqIndex
, regWrites
);
854 if (IS_CHAN_A_FAST_CLOCK(ah
, chan
))
855 REG_WRITE_ARRAY(&ah
->iniModesFastClock
, modesIndex
,
858 ar5008_hw_override_ini(ah
, chan
);
859 ar5008_hw_set_channel_regs(ah
, chan
);
860 ar5008_hw_init_chain_masks(ah
);
862 ath9k_hw_apply_txpower(ah
, chan
);
864 /* Write analog registers */
865 if (!ath9k_hw_set_rf_regs(ah
, chan
, freqIndex
)) {
866 ath_err(ath9k_hw_common(ah
), "ar5416SetRfRegs failed\n");
873 static void ar5008_hw_set_rfmode(struct ath_hw
*ah
, struct ath9k_channel
*chan
)
880 rfMode
|= (IS_CHAN_B(chan
) || IS_CHAN_G(chan
))
881 ? AR_PHY_MODE_DYNAMIC
: AR_PHY_MODE_OFDM
;
883 if (!AR_SREV_9280_20_OR_LATER(ah
))
884 rfMode
|= (IS_CHAN_5GHZ(chan
)) ?
885 AR_PHY_MODE_RF5GHZ
: AR_PHY_MODE_RF2GHZ
;
887 if (IS_CHAN_A_FAST_CLOCK(ah
, chan
))
888 rfMode
|= (AR_PHY_MODE_DYNAMIC
| AR_PHY_MODE_DYN_CCK_DISABLE
);
890 REG_WRITE(ah
, AR_PHY_MODE
, rfMode
);
893 static void ar5008_hw_mark_phy_inactive(struct ath_hw
*ah
)
895 REG_WRITE(ah
, AR_PHY_ACTIVE
, AR_PHY_ACTIVE_DIS
);
898 static void ar5008_hw_set_delta_slope(struct ath_hw
*ah
,
899 struct ath9k_channel
*chan
)
901 u32 coef_scaled
, ds_coef_exp
, ds_coef_man
;
902 u32 clockMhzScaled
= 0x64000000;
903 struct chan_centers centers
;
905 if (IS_CHAN_HALF_RATE(chan
))
906 clockMhzScaled
= clockMhzScaled
>> 1;
907 else if (IS_CHAN_QUARTER_RATE(chan
))
908 clockMhzScaled
= clockMhzScaled
>> 2;
910 ath9k_hw_get_channel_centers(ah
, chan
, ¢ers
);
911 coef_scaled
= clockMhzScaled
/ centers
.synth_center
;
913 ath9k_hw_get_delta_slope_vals(ah
, coef_scaled
, &ds_coef_man
,
916 REG_RMW_FIELD(ah
, AR_PHY_TIMING3
,
917 AR_PHY_TIMING3_DSC_MAN
, ds_coef_man
);
918 REG_RMW_FIELD(ah
, AR_PHY_TIMING3
,
919 AR_PHY_TIMING3_DSC_EXP
, ds_coef_exp
);
921 coef_scaled
= (9 * coef_scaled
) / 10;
923 ath9k_hw_get_delta_slope_vals(ah
, coef_scaled
, &ds_coef_man
,
926 REG_RMW_FIELD(ah
, AR_PHY_HALFGI
,
927 AR_PHY_HALFGI_DSC_MAN
, ds_coef_man
);
928 REG_RMW_FIELD(ah
, AR_PHY_HALFGI
,
929 AR_PHY_HALFGI_DSC_EXP
, ds_coef_exp
);
932 static bool ar5008_hw_rfbus_req(struct ath_hw
*ah
)
934 REG_WRITE(ah
, AR_PHY_RFBUS_REQ
, AR_PHY_RFBUS_REQ_EN
);
935 return ath9k_hw_wait(ah
, AR_PHY_RFBUS_GRANT
, AR_PHY_RFBUS_GRANT_EN
,
936 AR_PHY_RFBUS_GRANT_EN
, AH_WAIT_TIMEOUT
);
939 static void ar5008_hw_rfbus_done(struct ath_hw
*ah
)
941 u32 synthDelay
= REG_READ(ah
, AR_PHY_RX_DELAY
) & AR_PHY_RX_DELAY_DELAY
;
943 ath9k_hw_synth_delay(ah
, ah
->curchan
, synthDelay
);
945 REG_WRITE(ah
, AR_PHY_RFBUS_REQ
, 0);
948 static void ar5008_restore_chainmask(struct ath_hw
*ah
)
950 int rx_chainmask
= ah
->rxchainmask
;
952 if ((rx_chainmask
== 0x5) || (rx_chainmask
== 0x3)) {
953 REG_WRITE(ah
, AR_PHY_RX_CHAINMASK
, rx_chainmask
);
954 REG_WRITE(ah
, AR_PHY_CAL_CHAINMASK
, rx_chainmask
);
958 static u32
ar9160_hw_compute_pll_control(struct ath_hw
*ah
,
959 struct ath9k_channel
*chan
)
963 pll
= SM(0x5, AR_RTC_9160_PLL_REFDIV
);
965 if (chan
&& IS_CHAN_HALF_RATE(chan
))
966 pll
|= SM(0x1, AR_RTC_9160_PLL_CLKSEL
);
967 else if (chan
&& IS_CHAN_QUARTER_RATE(chan
))
968 pll
|= SM(0x2, AR_RTC_9160_PLL_CLKSEL
);
970 if (chan
&& IS_CHAN_5GHZ(chan
))
971 pll
|= SM(0x50, AR_RTC_9160_PLL_DIV
);
973 pll
|= SM(0x58, AR_RTC_9160_PLL_DIV
);
978 static u32
ar5008_hw_compute_pll_control(struct ath_hw
*ah
,
979 struct ath9k_channel
*chan
)
983 pll
= AR_RTC_PLL_REFDIV_5
| AR_RTC_PLL_DIV2
;
985 if (chan
&& IS_CHAN_HALF_RATE(chan
))
986 pll
|= SM(0x1, AR_RTC_PLL_CLKSEL
);
987 else if (chan
&& IS_CHAN_QUARTER_RATE(chan
))
988 pll
|= SM(0x2, AR_RTC_PLL_CLKSEL
);
990 if (chan
&& IS_CHAN_5GHZ(chan
))
991 pll
|= SM(0xa, AR_RTC_PLL_DIV
);
993 pll
|= SM(0xb, AR_RTC_PLL_DIV
);
998 static bool ar5008_hw_ani_control_old(struct ath_hw
*ah
,
999 enum ath9k_ani_cmd cmd
,
1002 struct ar5416AniState
*aniState
= &ah
->curchan
->ani
;
1003 struct ath_common
*common
= ath9k_hw_common(ah
);
1005 switch (cmd
& ah
->ani_function
) {
1006 case ATH9K_ANI_NOISE_IMMUNITY_LEVEL
:{
1009 if (level
>= ARRAY_SIZE(ah
->totalSizeDesired
)) {
1010 ath_dbg(common
, ANI
, "level out of range (%u > %zu)\n",
1011 level
, ARRAY_SIZE(ah
->totalSizeDesired
));
1015 REG_RMW_FIELD(ah
, AR_PHY_DESIRED_SZ
,
1016 AR_PHY_DESIRED_SZ_TOT_DES
,
1017 ah
->totalSizeDesired
[level
]);
1018 REG_RMW_FIELD(ah
, AR_PHY_AGC_CTL1
,
1019 AR_PHY_AGC_CTL1_COARSE_LOW
,
1020 ah
->coarse_low
[level
]);
1021 REG_RMW_FIELD(ah
, AR_PHY_AGC_CTL1
,
1022 AR_PHY_AGC_CTL1_COARSE_HIGH
,
1023 ah
->coarse_high
[level
]);
1024 REG_RMW_FIELD(ah
, AR_PHY_FIND_SIG
,
1025 AR_PHY_FIND_SIG_FIRPWR
,
1028 if (level
> aniState
->noiseImmunityLevel
)
1029 ah
->stats
.ast_ani_niup
++;
1030 else if (level
< aniState
->noiseImmunityLevel
)
1031 ah
->stats
.ast_ani_nidown
++;
1032 aniState
->noiseImmunityLevel
= level
;
1035 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION
:{
1036 u32 on
= param
? 1 : 0;
1039 REG_SET_BIT(ah
, AR_PHY_SFCORR_LOW
,
1040 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW
);
1042 REG_CLR_BIT(ah
, AR_PHY_SFCORR_LOW
,
1043 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW
);
1045 if (!on
!= aniState
->ofdmWeakSigDetectOff
) {
1047 ah
->stats
.ast_ani_ofdmon
++;
1049 ah
->stats
.ast_ani_ofdmoff
++;
1050 aniState
->ofdmWeakSigDetectOff
= !on
;
1054 case ATH9K_ANI_CCK_WEAK_SIGNAL_THR
:{
1055 static const int weakSigThrCck
[] = { 8, 6 };
1056 u32 high
= param
? 1 : 0;
1058 REG_RMW_FIELD(ah
, AR_PHY_CCK_DETECT
,
1059 AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK
,
1060 weakSigThrCck
[high
]);
1061 if (high
!= aniState
->cckWeakSigThreshold
) {
1063 ah
->stats
.ast_ani_cckhigh
++;
1065 ah
->stats
.ast_ani_ccklow
++;
1066 aniState
->cckWeakSigThreshold
= high
;
1070 case ATH9K_ANI_FIRSTEP_LEVEL
:{
1071 static const int firstep
[] = { 0, 4, 8 };
1074 if (level
>= ARRAY_SIZE(firstep
)) {
1075 ath_dbg(common
, ANI
, "level out of range (%u > %zu)\n",
1076 level
, ARRAY_SIZE(firstep
));
1079 REG_RMW_FIELD(ah
, AR_PHY_FIND_SIG
,
1080 AR_PHY_FIND_SIG_FIRSTEP
,
1082 if (level
> aniState
->firstepLevel
)
1083 ah
->stats
.ast_ani_stepup
++;
1084 else if (level
< aniState
->firstepLevel
)
1085 ah
->stats
.ast_ani_stepdown
++;
1086 aniState
->firstepLevel
= level
;
1089 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL
:{
1090 static const int cycpwrThr1
[] = { 2, 4, 6, 8, 10, 12, 14, 16 };
1093 if (level
>= ARRAY_SIZE(cycpwrThr1
)) {
1094 ath_dbg(common
, ANI
, "level out of range (%u > %zu)\n",
1095 level
, ARRAY_SIZE(cycpwrThr1
));
1098 REG_RMW_FIELD(ah
, AR_PHY_TIMING5
,
1099 AR_PHY_TIMING5_CYCPWR_THR1
,
1101 if (level
> aniState
->spurImmunityLevel
)
1102 ah
->stats
.ast_ani_spurup
++;
1103 else if (level
< aniState
->spurImmunityLevel
)
1104 ah
->stats
.ast_ani_spurdown
++;
1105 aniState
->spurImmunityLevel
= level
;
1108 case ATH9K_ANI_PRESENT
:
1111 ath_dbg(common
, ANI
, "invalid cmd %u\n", cmd
);
1115 ath_dbg(common
, ANI
, "ANI parameters:\n");
1116 ath_dbg(common
, ANI
,
1117 "noiseImmunityLevel=%d, spurImmunityLevel=%d, ofdmWeakSigDetectOff=%d\n",
1118 aniState
->noiseImmunityLevel
,
1119 aniState
->spurImmunityLevel
,
1120 !aniState
->ofdmWeakSigDetectOff
);
1121 ath_dbg(common
, ANI
,
1122 "cckWeakSigThreshold=%d, firstepLevel=%d, listenTime=%d\n",
1123 aniState
->cckWeakSigThreshold
,
1124 aniState
->firstepLevel
,
1125 aniState
->listenTime
);
1126 ath_dbg(common
, ANI
, "ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
1127 aniState
->ofdmPhyErrCount
,
1128 aniState
->cckPhyErrCount
);
1133 static bool ar5008_hw_ani_control_new(struct ath_hw
*ah
,
1134 enum ath9k_ani_cmd cmd
,
1137 struct ath_common
*common
= ath9k_hw_common(ah
);
1138 struct ath9k_channel
*chan
= ah
->curchan
;
1139 struct ar5416AniState
*aniState
= &chan
->ani
;
1142 switch (cmd
& ah
->ani_function
) {
1143 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION
:{
1145 * on == 1 means ofdm weak signal detection is ON
1146 * on == 1 is the default, for less noise immunity
1148 * on == 0 means ofdm weak signal detection is OFF
1149 * on == 0 means more noise imm
1151 u32 on
= param
? 1 : 0;
1153 * make register setting for default
1154 * (weak sig detect ON) come from INI file
1156 int m1ThreshLow
= on
?
1157 aniState
->iniDef
.m1ThreshLow
: m1ThreshLow_off
;
1158 int m2ThreshLow
= on
?
1159 aniState
->iniDef
.m2ThreshLow
: m2ThreshLow_off
;
1161 aniState
->iniDef
.m1Thresh
: m1Thresh_off
;
1163 aniState
->iniDef
.m2Thresh
: m2Thresh_off
;
1164 int m2CountThr
= on
?
1165 aniState
->iniDef
.m2CountThr
: m2CountThr_off
;
1166 int m2CountThrLow
= on
?
1167 aniState
->iniDef
.m2CountThrLow
: m2CountThrLow_off
;
1168 int m1ThreshLowExt
= on
?
1169 aniState
->iniDef
.m1ThreshLowExt
: m1ThreshLowExt_off
;
1170 int m2ThreshLowExt
= on
?
1171 aniState
->iniDef
.m2ThreshLowExt
: m2ThreshLowExt_off
;
1172 int m1ThreshExt
= on
?
1173 aniState
->iniDef
.m1ThreshExt
: m1ThreshExt_off
;
1174 int m2ThreshExt
= on
?
1175 aniState
->iniDef
.m2ThreshExt
: m2ThreshExt_off
;
1177 REG_RMW_FIELD(ah
, AR_PHY_SFCORR_LOW
,
1178 AR_PHY_SFCORR_LOW_M1_THRESH_LOW
,
1180 REG_RMW_FIELD(ah
, AR_PHY_SFCORR_LOW
,
1181 AR_PHY_SFCORR_LOW_M2_THRESH_LOW
,
1183 REG_RMW_FIELD(ah
, AR_PHY_SFCORR
,
1184 AR_PHY_SFCORR_M1_THRESH
, m1Thresh
);
1185 REG_RMW_FIELD(ah
, AR_PHY_SFCORR
,
1186 AR_PHY_SFCORR_M2_THRESH
, m2Thresh
);
1187 REG_RMW_FIELD(ah
, AR_PHY_SFCORR
,
1188 AR_PHY_SFCORR_M2COUNT_THR
, m2CountThr
);
1189 REG_RMW_FIELD(ah
, AR_PHY_SFCORR_LOW
,
1190 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW
,
1193 REG_RMW_FIELD(ah
, AR_PHY_SFCORR_EXT
,
1194 AR_PHY_SFCORR_EXT_M1_THRESH_LOW
, m1ThreshLowExt
);
1195 REG_RMW_FIELD(ah
, AR_PHY_SFCORR_EXT
,
1196 AR_PHY_SFCORR_EXT_M2_THRESH_LOW
, m2ThreshLowExt
);
1197 REG_RMW_FIELD(ah
, AR_PHY_SFCORR_EXT
,
1198 AR_PHY_SFCORR_EXT_M1_THRESH
, m1ThreshExt
);
1199 REG_RMW_FIELD(ah
, AR_PHY_SFCORR_EXT
,
1200 AR_PHY_SFCORR_EXT_M2_THRESH
, m2ThreshExt
);
1203 REG_SET_BIT(ah
, AR_PHY_SFCORR_LOW
,
1204 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW
);
1206 REG_CLR_BIT(ah
, AR_PHY_SFCORR_LOW
,
1207 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW
);
1209 if (!on
!= aniState
->ofdmWeakSigDetectOff
) {
1210 ath_dbg(common
, ANI
,
1211 "** ch %d: ofdm weak signal: %s=>%s\n",
1213 !aniState
->ofdmWeakSigDetectOff
?
1217 ah
->stats
.ast_ani_ofdmon
++;
1219 ah
->stats
.ast_ani_ofdmoff
++;
1220 aniState
->ofdmWeakSigDetectOff
= !on
;
1224 case ATH9K_ANI_FIRSTEP_LEVEL
:{
1227 if (level
>= ARRAY_SIZE(firstep_table
)) {
1228 ath_dbg(common
, ANI
,
1229 "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n",
1230 level
, ARRAY_SIZE(firstep_table
));
1235 * make register setting relative to default
1236 * from INI file & cap value
1238 value
= firstep_table
[level
] -
1239 firstep_table
[ATH9K_ANI_FIRSTEP_LVL_NEW
] +
1240 aniState
->iniDef
.firstep
;
1241 if (value
< ATH9K_SIG_FIRSTEP_SETTING_MIN
)
1242 value
= ATH9K_SIG_FIRSTEP_SETTING_MIN
;
1243 if (value
> ATH9K_SIG_FIRSTEP_SETTING_MAX
)
1244 value
= ATH9K_SIG_FIRSTEP_SETTING_MAX
;
1245 REG_RMW_FIELD(ah
, AR_PHY_FIND_SIG
,
1246 AR_PHY_FIND_SIG_FIRSTEP
,
1249 * we need to set first step low register too
1250 * make register setting relative to default
1251 * from INI file & cap value
1253 value2
= firstep_table
[level
] -
1254 firstep_table
[ATH9K_ANI_FIRSTEP_LVL_NEW
] +
1255 aniState
->iniDef
.firstepLow
;
1256 if (value2
< ATH9K_SIG_FIRSTEP_SETTING_MIN
)
1257 value2
= ATH9K_SIG_FIRSTEP_SETTING_MIN
;
1258 if (value2
> ATH9K_SIG_FIRSTEP_SETTING_MAX
)
1259 value2
= ATH9K_SIG_FIRSTEP_SETTING_MAX
;
1261 REG_RMW_FIELD(ah
, AR_PHY_FIND_SIG_LOW
,
1262 AR_PHY_FIND_SIG_FIRSTEP_LOW
, value2
);
1264 if (level
!= aniState
->firstepLevel
) {
1265 ath_dbg(common
, ANI
,
1266 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
1268 aniState
->firstepLevel
,
1270 ATH9K_ANI_FIRSTEP_LVL_NEW
,
1272 aniState
->iniDef
.firstep
);
1273 ath_dbg(common
, ANI
,
1274 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
1276 aniState
->firstepLevel
,
1278 ATH9K_ANI_FIRSTEP_LVL_NEW
,
1280 aniState
->iniDef
.firstepLow
);
1281 if (level
> aniState
->firstepLevel
)
1282 ah
->stats
.ast_ani_stepup
++;
1283 else if (level
< aniState
->firstepLevel
)
1284 ah
->stats
.ast_ani_stepdown
++;
1285 aniState
->firstepLevel
= level
;
1289 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL
:{
1292 if (level
>= ARRAY_SIZE(cycpwrThr1_table
)) {
1293 ath_dbg(common
, ANI
,
1294 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n",
1295 level
, ARRAY_SIZE(cycpwrThr1_table
));
1299 * make register setting relative to default
1300 * from INI file & cap value
1302 value
= cycpwrThr1_table
[level
] -
1303 cycpwrThr1_table
[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW
] +
1304 aniState
->iniDef
.cycpwrThr1
;
1305 if (value
< ATH9K_SIG_SPUR_IMM_SETTING_MIN
)
1306 value
= ATH9K_SIG_SPUR_IMM_SETTING_MIN
;
1307 if (value
> ATH9K_SIG_SPUR_IMM_SETTING_MAX
)
1308 value
= ATH9K_SIG_SPUR_IMM_SETTING_MAX
;
1309 REG_RMW_FIELD(ah
, AR_PHY_TIMING5
,
1310 AR_PHY_TIMING5_CYCPWR_THR1
,
1314 * set AR_PHY_EXT_CCA for extension channel
1315 * make register setting relative to default
1316 * from INI file & cap value
1318 value2
= cycpwrThr1_table
[level
] -
1319 cycpwrThr1_table
[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW
] +
1320 aniState
->iniDef
.cycpwrThr1Ext
;
1321 if (value2
< ATH9K_SIG_SPUR_IMM_SETTING_MIN
)
1322 value2
= ATH9K_SIG_SPUR_IMM_SETTING_MIN
;
1323 if (value2
> ATH9K_SIG_SPUR_IMM_SETTING_MAX
)
1324 value2
= ATH9K_SIG_SPUR_IMM_SETTING_MAX
;
1325 REG_RMW_FIELD(ah
, AR_PHY_EXT_CCA
,
1326 AR_PHY_EXT_TIMING5_CYCPWR_THR1
, value2
);
1328 if (level
!= aniState
->spurImmunityLevel
) {
1329 ath_dbg(common
, ANI
,
1330 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
1332 aniState
->spurImmunityLevel
,
1334 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW
,
1336 aniState
->iniDef
.cycpwrThr1
);
1337 ath_dbg(common
, ANI
,
1338 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
1340 aniState
->spurImmunityLevel
,
1342 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW
,
1344 aniState
->iniDef
.cycpwrThr1Ext
);
1345 if (level
> aniState
->spurImmunityLevel
)
1346 ah
->stats
.ast_ani_spurup
++;
1347 else if (level
< aniState
->spurImmunityLevel
)
1348 ah
->stats
.ast_ani_spurdown
++;
1349 aniState
->spurImmunityLevel
= level
;
1353 case ATH9K_ANI_MRC_CCK
:
1355 * You should not see this as AR5008, AR9001, AR9002
1356 * does not have hardware support for MRC CCK.
1360 case ATH9K_ANI_PRESENT
:
1363 ath_dbg(common
, ANI
, "invalid cmd %u\n", cmd
);
1367 ath_dbg(common
, ANI
,
1368 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1369 aniState
->spurImmunityLevel
,
1370 !aniState
->ofdmWeakSigDetectOff
? "on" : "off",
1371 aniState
->firstepLevel
,
1372 !aniState
->mrcCCKOff
? "on" : "off",
1373 aniState
->listenTime
,
1374 aniState
->ofdmPhyErrCount
,
1375 aniState
->cckPhyErrCount
);
1379 static void ar5008_hw_do_getnf(struct ath_hw
*ah
,
1380 int16_t nfarray
[NUM_NF_READINGS
])
1384 nf
= MS(REG_READ(ah
, AR_PHY_CCA
), AR_PHY_MINCCA_PWR
);
1385 nfarray
[0] = sign_extend32(nf
, 8);
1387 nf
= MS(REG_READ(ah
, AR_PHY_CH1_CCA
), AR_PHY_CH1_MINCCA_PWR
);
1388 nfarray
[1] = sign_extend32(nf
, 8);
1390 nf
= MS(REG_READ(ah
, AR_PHY_CH2_CCA
), AR_PHY_CH2_MINCCA_PWR
);
1391 nfarray
[2] = sign_extend32(nf
, 8);
1393 if (!IS_CHAN_HT40(ah
->curchan
))
1396 nf
= MS(REG_READ(ah
, AR_PHY_EXT_CCA
), AR_PHY_EXT_MINCCA_PWR
);
1397 nfarray
[3] = sign_extend32(nf
, 8);
1399 nf
= MS(REG_READ(ah
, AR_PHY_CH1_EXT_CCA
), AR_PHY_CH1_EXT_MINCCA_PWR
);
1400 nfarray
[4] = sign_extend32(nf
, 8);
1402 nf
= MS(REG_READ(ah
, AR_PHY_CH2_EXT_CCA
), AR_PHY_CH2_EXT_MINCCA_PWR
);
1403 nfarray
[5] = sign_extend32(nf
, 8);
1407 * Initialize the ANI register values with default (ini) values.
1408 * This routine is called during a (full) hardware reset after
1409 * all the registers are initialised from the INI.
1411 static void ar5008_hw_ani_cache_ini_regs(struct ath_hw
*ah
)
1413 struct ath_common
*common
= ath9k_hw_common(ah
);
1414 struct ath9k_channel
*chan
= ah
->curchan
;
1415 struct ar5416AniState
*aniState
= &chan
->ani
;
1416 struct ath9k_ani_default
*iniDef
;
1419 iniDef
= &aniState
->iniDef
;
1421 ath_dbg(common
, ANI
, "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
1422 ah
->hw_version
.macVersion
,
1423 ah
->hw_version
.macRev
,
1426 chan
->channelFlags
);
1428 val
= REG_READ(ah
, AR_PHY_SFCORR
);
1429 iniDef
->m1Thresh
= MS(val
, AR_PHY_SFCORR_M1_THRESH
);
1430 iniDef
->m2Thresh
= MS(val
, AR_PHY_SFCORR_M2_THRESH
);
1431 iniDef
->m2CountThr
= MS(val
, AR_PHY_SFCORR_M2COUNT_THR
);
1433 val
= REG_READ(ah
, AR_PHY_SFCORR_LOW
);
1434 iniDef
->m1ThreshLow
= MS(val
, AR_PHY_SFCORR_LOW_M1_THRESH_LOW
);
1435 iniDef
->m2ThreshLow
= MS(val
, AR_PHY_SFCORR_LOW_M2_THRESH_LOW
);
1436 iniDef
->m2CountThrLow
= MS(val
, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW
);
1438 val
= REG_READ(ah
, AR_PHY_SFCORR_EXT
);
1439 iniDef
->m1ThreshExt
= MS(val
, AR_PHY_SFCORR_EXT_M1_THRESH
);
1440 iniDef
->m2ThreshExt
= MS(val
, AR_PHY_SFCORR_EXT_M2_THRESH
);
1441 iniDef
->m1ThreshLowExt
= MS(val
, AR_PHY_SFCORR_EXT_M1_THRESH_LOW
);
1442 iniDef
->m2ThreshLowExt
= MS(val
, AR_PHY_SFCORR_EXT_M2_THRESH_LOW
);
1443 iniDef
->firstep
= REG_READ_FIELD(ah
,
1445 AR_PHY_FIND_SIG_FIRSTEP
);
1446 iniDef
->firstepLow
= REG_READ_FIELD(ah
,
1447 AR_PHY_FIND_SIG_LOW
,
1448 AR_PHY_FIND_SIG_FIRSTEP_LOW
);
1449 iniDef
->cycpwrThr1
= REG_READ_FIELD(ah
,
1451 AR_PHY_TIMING5_CYCPWR_THR1
);
1452 iniDef
->cycpwrThr1Ext
= REG_READ_FIELD(ah
,
1454 AR_PHY_EXT_TIMING5_CYCPWR_THR1
);
1456 /* these levels just got reset to defaults by the INI */
1457 aniState
->spurImmunityLevel
= ATH9K_ANI_SPUR_IMMUNE_LVL_NEW
;
1458 aniState
->firstepLevel
= ATH9K_ANI_FIRSTEP_LVL_NEW
;
1459 aniState
->ofdmWeakSigDetectOff
= !ATH9K_ANI_USE_OFDM_WEAK_SIG
;
1460 aniState
->mrcCCKOff
= true; /* not available on pre AR9003 */
1463 static void ar5008_hw_set_nf_limits(struct ath_hw
*ah
)
1465 ah
->nf_2g
.max
= AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ
;
1466 ah
->nf_2g
.min
= AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ
;
1467 ah
->nf_2g
.nominal
= AR_PHY_CCA_NOM_VAL_5416_2GHZ
;
1468 ah
->nf_5g
.max
= AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ
;
1469 ah
->nf_5g
.min
= AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ
;
1470 ah
->nf_5g
.nominal
= AR_PHY_CCA_NOM_VAL_5416_5GHZ
;
1473 static void ar5008_hw_set_radar_params(struct ath_hw
*ah
,
1474 struct ath_hw_radar_conf
*conf
)
1476 u32 radar_0
= 0, radar_1
= 0;
1479 REG_CLR_BIT(ah
, AR_PHY_RADAR_0
, AR_PHY_RADAR_0_ENA
);
1483 radar_0
|= AR_PHY_RADAR_0_ENA
| AR_PHY_RADAR_0_FFT_ENA
;
1484 radar_0
|= SM(conf
->fir_power
, AR_PHY_RADAR_0_FIRPWR
);
1485 radar_0
|= SM(conf
->radar_rssi
, AR_PHY_RADAR_0_RRSSI
);
1486 radar_0
|= SM(conf
->pulse_height
, AR_PHY_RADAR_0_HEIGHT
);
1487 radar_0
|= SM(conf
->pulse_rssi
, AR_PHY_RADAR_0_PRSSI
);
1488 radar_0
|= SM(conf
->pulse_inband
, AR_PHY_RADAR_0_INBAND
);
1490 radar_1
|= AR_PHY_RADAR_1_MAX_RRSSI
;
1491 radar_1
|= AR_PHY_RADAR_1_BLOCK_CHECK
;
1492 radar_1
|= SM(conf
->pulse_maxlen
, AR_PHY_RADAR_1_MAXLEN
);
1493 radar_1
|= SM(conf
->pulse_inband_step
, AR_PHY_RADAR_1_RELSTEP_THRESH
);
1494 radar_1
|= SM(conf
->radar_inband
, AR_PHY_RADAR_1_RELPWR_THRESH
);
1496 REG_WRITE(ah
, AR_PHY_RADAR_0
, radar_0
);
1497 REG_WRITE(ah
, AR_PHY_RADAR_1
, radar_1
);
1498 if (conf
->ext_channel
)
1499 REG_SET_BIT(ah
, AR_PHY_RADAR_EXT
, AR_PHY_RADAR_EXT_ENA
);
1501 REG_CLR_BIT(ah
, AR_PHY_RADAR_EXT
, AR_PHY_RADAR_EXT_ENA
);
1504 static void ar5008_hw_set_radar_conf(struct ath_hw
*ah
)
1506 struct ath_hw_radar_conf
*conf
= &ah
->radar_conf
;
1508 conf
->fir_power
= -33;
1509 conf
->radar_rssi
= 20;
1510 conf
->pulse_height
= 10;
1511 conf
->pulse_rssi
= 24;
1512 conf
->pulse_inband
= 15;
1513 conf
->pulse_maxlen
= 255;
1514 conf
->pulse_inband_step
= 12;
1515 conf
->radar_inband
= 8;
1518 void ar5008_hw_attach_phy_ops(struct ath_hw
*ah
)
1520 struct ath_hw_private_ops
*priv_ops
= ath9k_hw_private_ops(ah
);
1521 static const u32 ar5416_cca_regs
[6] = {
1530 priv_ops
->rf_set_freq
= ar5008_hw_set_channel
;
1531 priv_ops
->spur_mitigate_freq
= ar5008_hw_spur_mitigate
;
1533 priv_ops
->rf_alloc_ext_banks
= ar5008_hw_rf_alloc_ext_banks
;
1534 priv_ops
->rf_free_ext_banks
= ar5008_hw_rf_free_ext_banks
;
1535 priv_ops
->set_rf_regs
= ar5008_hw_set_rf_regs
;
1536 priv_ops
->set_channel_regs
= ar5008_hw_set_channel_regs
;
1537 priv_ops
->init_bb
= ar5008_hw_init_bb
;
1538 priv_ops
->process_ini
= ar5008_hw_process_ini
;
1539 priv_ops
->set_rfmode
= ar5008_hw_set_rfmode
;
1540 priv_ops
->mark_phy_inactive
= ar5008_hw_mark_phy_inactive
;
1541 priv_ops
->set_delta_slope
= ar5008_hw_set_delta_slope
;
1542 priv_ops
->rfbus_req
= ar5008_hw_rfbus_req
;
1543 priv_ops
->rfbus_done
= ar5008_hw_rfbus_done
;
1544 priv_ops
->restore_chainmask
= ar5008_restore_chainmask
;
1545 priv_ops
->do_getnf
= ar5008_hw_do_getnf
;
1546 priv_ops
->set_radar_params
= ar5008_hw_set_radar_params
;
1548 if (modparam_force_new_ani
) {
1549 priv_ops
->ani_control
= ar5008_hw_ani_control_new
;
1550 priv_ops
->ani_cache_ini_regs
= ar5008_hw_ani_cache_ini_regs
;
1552 priv_ops
->ani_control
= ar5008_hw_ani_control_old
;
1554 if (AR_SREV_9100(ah
) || AR_SREV_9160_10_OR_LATER(ah
))
1555 priv_ops
->compute_pll_control
= ar9160_hw_compute_pll_control
;
1557 priv_ops
->compute_pll_control
= ar5008_hw_compute_pll_control
;
1559 ar5008_hw_set_nf_limits(ah
);
1560 ar5008_hw_set_radar_conf(ah
);
1561 memcpy(ah
->nf_regs
, ar5416_cca_regs
, sizeof(ah
->nf_regs
));