2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 * DOC: Programming Atheros 802.11n analog front end radios
20 * AR5416 MAC based PCI devices and AR518 MAC based PCI-Express
21 * devices have either an external AR2133 analog front end radio for single
22 * band 2.4 GHz communication or an AR5133 analog front end radio for dual
23 * band 2.4 GHz / 5 GHz communication.
25 * All devices after the AR5416 and AR5418 family starting with the AR9280
26 * have their analog front radios, MAC/BB and host PCIe/USB interface embedded
27 * into a single-chip and require less programming.
29 * The following single-chips exist with a respective embedded radio:
31 * AR9280 - 11n dual-band 2x2 MIMO for PCIe
32 * AR9281 - 11n single-band 1x2 MIMO for PCIe
33 * AR9285 - 11n single-band 1x1 for PCIe
34 * AR9287 - 11n single-band 2x2 MIMO for PCIe
36 * AR9220 - 11n dual-band 2x2 MIMO for PCI
37 * AR9223 - 11n single-band 2x2 MIMO for PCI
39 * AR9287 - 11n single-band 1x1 MIMO for USB
43 #include "ar9002_phy.h"
46 * ar9002_hw_set_channel - set channel on single-chip device
47 * @ah: atheros hardware structure
50 * This is the function to change channel on single-chip devices, that is
51 * all devices after ar9280.
53 * This function takes the channel value in MHz and sets
54 * hardware channel value. Assumes writes have been enabled to analog bus.
59 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
63 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
64 * (freq_ref = 40MHz/(24>>amodeRefSel))
66 static int ar9002_hw_set_channel(struct ath_hw
*ah
, struct ath9k_channel
*chan
)
68 u16 bMode
, fracMode
, aModeRefSel
= 0;
69 u32 freq
, ndiv
, channelSel
= 0, channelFrac
= 0, reg32
= 0;
70 struct chan_centers centers
;
73 ath9k_hw_get_channel_centers(ah
, chan
, ¢ers
);
74 freq
= centers
.synth_center
;
76 reg32
= REG_READ(ah
, AR_PHY_SYNTH_CONTROL
);
79 if (freq
< 4800) { /* 2 GHz, fractional mode */
86 channelSel
= CHANSEL_2G(freq
);
88 if (AR_SREV_9287_11_OR_LATER(ah
)) {
90 /* Enable channel spreading for channel 14 */
91 REG_WRITE_ARRAY(&ah
->iniCckfirJapan2484
,
94 REG_WRITE_ARRAY(&ah
->iniCckfirNormal
,
98 txctl
= REG_READ(ah
, AR_PHY_CCK_TX_CTRL
);
100 /* Enable channel spreading for channel 14 */
101 REG_WRITE(ah
, AR_PHY_CCK_TX_CTRL
,
102 txctl
| AR_PHY_CCK_TX_CTRL_JAPAN
);
104 REG_WRITE(ah
, AR_PHY_CCK_TX_CTRL
,
105 txctl
& ~AR_PHY_CCK_TX_CTRL_JAPAN
);
112 switch (ah
->eep_ops
->get_eeprom(ah
, EEP_FRAC_N_5G
)) {
114 if (IS_CHAN_HALF_RATE(chan
) || IS_CHAN_QUARTER_RATE(chan
))
116 else if ((freq
% 20) == 0)
118 else if ((freq
% 10) == 0)
126 * Enable 2G (fractional) mode for channels
127 * which are 5MHz spaced.
131 channelSel
= CHANSEL_5G(freq
);
133 /* RefDivA setting */
134 ath9k_hw_analog_shift_rmw(ah
, AR_AN_SYNTH9
,
135 AR_AN_SYNTH9_REFDIVA
,
136 AR_AN_SYNTH9_REFDIVA_S
, refDivA
);
141 ndiv
= (freq
* (refDivA
>> aModeRefSel
)) / 60;
142 channelSel
= ndiv
& 0x1ff;
143 channelFrac
= (ndiv
& 0xfffffe00) * 2;
144 channelSel
= (channelSel
<< 17) | channelFrac
;
150 (fracMode
<< 28) | (aModeRefSel
<< 26) | (channelSel
);
152 REG_WRITE(ah
, AR_PHY_SYNTH_CONTROL
, reg32
);
160 * ar9002_hw_spur_mitigate - convert baseband spur frequency
161 * @ah: atheros hardware structure
164 * For single-chip solutions. Converts to baseband spur frequency given the
165 * input channel frequency and compute register settings below.
167 static void ar9002_hw_spur_mitigate(struct ath_hw
*ah
,
168 struct ath9k_channel
*chan
)
170 int bb_spur
= AR_NO_SPUR
;
173 int bb_spur_off
, spur_subchannel_sd
;
175 int spur_delta_phase
;
179 struct chan_centers centers
;
184 bool is2GHz
= IS_CHAN_2GHZ(chan
);
186 memset(&mask_m
, 0, sizeof(int8_t) * 123);
187 memset(&mask_p
, 0, sizeof(int8_t) * 123);
189 ath9k_hw_get_channel_centers(ah
, chan
, ¢ers
);
190 freq
= centers
.synth_center
;
192 for (i
= 0; i
< AR_EEPROM_MODAL_SPURS
; i
++) {
193 cur_bb_spur
= ah
->eep_ops
->get_spur_channel(ah
, i
, is2GHz
);
195 if (AR_NO_SPUR
== cur_bb_spur
)
199 cur_bb_spur
= (cur_bb_spur
/ 10) + AR_BASE_FREQ_2GHZ
;
201 cur_bb_spur
= (cur_bb_spur
/ 10) + AR_BASE_FREQ_5GHZ
;
203 cur_bb_spur
= cur_bb_spur
- freq
;
205 if (IS_CHAN_HT40(chan
)) {
206 if ((cur_bb_spur
> -AR_SPUR_FEEQ_BOUND_HT40
) &&
207 (cur_bb_spur
< AR_SPUR_FEEQ_BOUND_HT40
)) {
208 bb_spur
= cur_bb_spur
;
211 } else if ((cur_bb_spur
> -AR_SPUR_FEEQ_BOUND_HT20
) &&
212 (cur_bb_spur
< AR_SPUR_FEEQ_BOUND_HT20
)) {
213 bb_spur
= cur_bb_spur
;
218 if (AR_NO_SPUR
== bb_spur
) {
219 REG_CLR_BIT(ah
, AR_PHY_FORCE_CLKEN_CCK
,
220 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX
);
223 REG_CLR_BIT(ah
, AR_PHY_FORCE_CLKEN_CCK
,
224 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX
);
229 tmp
= REG_READ(ah
, AR_PHY_TIMING_CTRL4(0));
231 ENABLE_REGWRITE_BUFFER(ah
);
233 newVal
= tmp
| (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI
|
234 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER
|
235 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK
|
236 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK
);
237 REG_WRITE(ah
, AR_PHY_TIMING_CTRL4(0), newVal
);
239 newVal
= (AR_PHY_SPUR_REG_MASK_RATE_CNTL
|
240 AR_PHY_SPUR_REG_ENABLE_MASK_PPM
|
241 AR_PHY_SPUR_REG_MASK_RATE_SELECT
|
242 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI
|
243 SM(SPUR_RSSI_THRESH
, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH
));
244 REG_WRITE(ah
, AR_PHY_SPUR_REG
, newVal
);
246 if (IS_CHAN_HT40(chan
)) {
248 spur_subchannel_sd
= 1;
249 bb_spur_off
= bb_spur
+ 10;
251 spur_subchannel_sd
= 0;
252 bb_spur_off
= bb_spur
- 10;
255 spur_subchannel_sd
= 0;
256 bb_spur_off
= bb_spur
;
259 if (IS_CHAN_HT40(chan
))
261 ((bb_spur
* 262144) /
262 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE
;
265 ((bb_spur
* 524288) /
266 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE
;
268 denominator
= IS_CHAN_2GHZ(chan
) ? 44 : 40;
269 spur_freq_sd
= ((bb_spur_off
* 2048) / denominator
) & 0x3ff;
271 newVal
= (AR_PHY_TIMING11_USE_SPUR_IN_AGC
|
272 SM(spur_freq_sd
, AR_PHY_TIMING11_SPUR_FREQ_SD
) |
273 SM(spur_delta_phase
, AR_PHY_TIMING11_SPUR_DELTA_PHASE
));
274 REG_WRITE(ah
, AR_PHY_TIMING11
, newVal
);
276 newVal
= spur_subchannel_sd
<< AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S
;
277 REG_WRITE(ah
, AR_PHY_SFCORR_EXT
, newVal
);
279 ar5008_hw_cmn_spur_mitigate(ah
, chan
, bin
);
281 REGWRITE_BUFFER_FLUSH(ah
);
284 static void ar9002_olc_init(struct ath_hw
*ah
)
288 if (!OLC_FOR_AR9280_20_LATER
)
291 if (OLC_FOR_AR9287_10_LATER
) {
292 REG_SET_BIT(ah
, AR_PHY_TX_PWRCTRL9
,
293 AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL
);
294 ath9k_hw_analog_shift_rmw(ah
, AR9287_AN_TXPC0
,
295 AR9287_AN_TXPC0_TXPCMODE
,
296 AR9287_AN_TXPC0_TXPCMODE_S
,
297 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE
);
300 for (i
= 0; i
< AR9280_TX_GAIN_TABLE_SIZE
; i
++)
301 ah
->originalGain
[i
] =
302 MS(REG_READ(ah
, AR_PHY_TX_GAIN_TBL1
+ i
* 4),
308 static u32
ar9002_hw_compute_pll_control(struct ath_hw
*ah
,
309 struct ath9k_channel
*chan
)
315 if (chan
&& IS_CHAN_5GHZ(chan
) && !IS_CHAN_A_FAST_CLOCK(ah
, chan
)) {
316 if (AR_SREV_9280_20(ah
)) {
324 pll
= SM(ref_div
, AR_RTC_9160_PLL_REFDIV
);
325 pll
|= SM(pll_div
, AR_RTC_9160_PLL_DIV
);
327 if (chan
&& IS_CHAN_HALF_RATE(chan
))
328 pll
|= SM(0x1, AR_RTC_9160_PLL_CLKSEL
);
329 else if (chan
&& IS_CHAN_QUARTER_RATE(chan
))
330 pll
|= SM(0x2, AR_RTC_9160_PLL_CLKSEL
);
335 static void ar9002_hw_do_getnf(struct ath_hw
*ah
,
336 int16_t nfarray
[NUM_NF_READINGS
])
340 nf
= MS(REG_READ(ah
, AR_PHY_CCA
), AR9280_PHY_MINCCA_PWR
);
341 nfarray
[0] = sign_extend32(nf
, 8);
343 nf
= MS(REG_READ(ah
, AR_PHY_EXT_CCA
), AR9280_PHY_EXT_MINCCA_PWR
);
344 if (IS_CHAN_HT40(ah
->curchan
))
345 nfarray
[3] = sign_extend32(nf
, 8);
347 if (!(ah
->rxchainmask
& BIT(1)))
350 nf
= MS(REG_READ(ah
, AR_PHY_CH1_CCA
), AR9280_PHY_CH1_MINCCA_PWR
);
351 nfarray
[1] = sign_extend32(nf
, 8);
353 nf
= MS(REG_READ(ah
, AR_PHY_CH1_EXT_CCA
), AR9280_PHY_CH1_EXT_MINCCA_PWR
);
354 if (IS_CHAN_HT40(ah
->curchan
))
355 nfarray
[4] = sign_extend32(nf
, 8);
358 static void ar9002_hw_set_nf_limits(struct ath_hw
*ah
)
360 if (AR_SREV_9285(ah
)) {
361 ah
->nf_2g
.max
= AR_PHY_CCA_MAX_GOOD_VAL_9285_2GHZ
;
362 ah
->nf_2g
.min
= AR_PHY_CCA_MIN_GOOD_VAL_9285_2GHZ
;
363 ah
->nf_2g
.nominal
= AR_PHY_CCA_NOM_VAL_9285_2GHZ
;
364 } else if (AR_SREV_9287(ah
)) {
365 ah
->nf_2g
.max
= AR_PHY_CCA_MAX_GOOD_VAL_9287_2GHZ
;
366 ah
->nf_2g
.min
= AR_PHY_CCA_MIN_GOOD_VAL_9287_2GHZ
;
367 ah
->nf_2g
.nominal
= AR_PHY_CCA_NOM_VAL_9287_2GHZ
;
368 } else if (AR_SREV_9271(ah
)) {
369 ah
->nf_2g
.max
= AR_PHY_CCA_MAX_GOOD_VAL_9271_2GHZ
;
370 ah
->nf_2g
.min
= AR_PHY_CCA_MIN_GOOD_VAL_9271_2GHZ
;
371 ah
->nf_2g
.nominal
= AR_PHY_CCA_NOM_VAL_9271_2GHZ
;
373 ah
->nf_2g
.max
= AR_PHY_CCA_MAX_GOOD_VAL_9280_2GHZ
;
374 ah
->nf_2g
.min
= AR_PHY_CCA_MIN_GOOD_VAL_9280_2GHZ
;
375 ah
->nf_2g
.nominal
= AR_PHY_CCA_NOM_VAL_9280_2GHZ
;
376 ah
->nf_5g
.max
= AR_PHY_CCA_MAX_GOOD_VAL_9280_5GHZ
;
377 ah
->nf_5g
.min
= AR_PHY_CCA_MIN_GOOD_VAL_9280_5GHZ
;
378 ah
->nf_5g
.nominal
= AR_PHY_CCA_NOM_VAL_9280_5GHZ
;
382 static void ar9002_hw_antdiv_comb_conf_get(struct ath_hw
*ah
,
383 struct ath_hw_antcomb_conf
*antconf
)
387 regval
= REG_READ(ah
, AR_PHY_MULTICHAIN_GAIN_CTL
);
388 antconf
->main_lna_conf
= (regval
& AR_PHY_9285_ANT_DIV_MAIN_LNACONF
) >>
389 AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S
;
390 antconf
->alt_lna_conf
= (regval
& AR_PHY_9285_ANT_DIV_ALT_LNACONF
) >>
391 AR_PHY_9285_ANT_DIV_ALT_LNACONF_S
;
392 antconf
->fast_div_bias
= (regval
& AR_PHY_9285_FAST_DIV_BIAS
) >>
393 AR_PHY_9285_FAST_DIV_BIAS_S
;
394 antconf
->lna1_lna2_switch_delta
= -1;
395 antconf
->lna1_lna2_delta
= -3;
396 antconf
->div_group
= 0;
399 static void ar9002_hw_antdiv_comb_conf_set(struct ath_hw
*ah
,
400 struct ath_hw_antcomb_conf
*antconf
)
404 regval
= REG_READ(ah
, AR_PHY_MULTICHAIN_GAIN_CTL
);
405 regval
&= ~(AR_PHY_9285_ANT_DIV_MAIN_LNACONF
|
406 AR_PHY_9285_ANT_DIV_ALT_LNACONF
|
407 AR_PHY_9285_FAST_DIV_BIAS
);
408 regval
|= ((antconf
->main_lna_conf
<< AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S
)
409 & AR_PHY_9285_ANT_DIV_MAIN_LNACONF
);
410 regval
|= ((antconf
->alt_lna_conf
<< AR_PHY_9285_ANT_DIV_ALT_LNACONF_S
)
411 & AR_PHY_9285_ANT_DIV_ALT_LNACONF
);
412 regval
|= ((antconf
->fast_div_bias
<< AR_PHY_9285_FAST_DIV_BIAS_S
)
413 & AR_PHY_9285_FAST_DIV_BIAS
);
415 REG_WRITE(ah
, AR_PHY_MULTICHAIN_GAIN_CTL
, regval
);
418 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
420 static void ar9002_hw_set_bt_ant_diversity(struct ath_hw
*ah
, bool enable
)
422 struct ath_btcoex_hw
*btcoex
= &ah
->btcoex_hw
;
423 u8 antdiv_ctrl1
, antdiv_ctrl2
;
427 antdiv_ctrl1
= ATH_BT_COEX_ANTDIV_CONTROL1_ENABLE
;
428 antdiv_ctrl2
= ATH_BT_COEX_ANTDIV_CONTROL2_ENABLE
;
431 * Don't disable BT ant to allow BB to control SWCOM.
433 btcoex
->bt_coex_mode2
&= (~(AR_BT_DISABLE_BT_ANT
));
434 REG_WRITE(ah
, AR_BT_COEX_MODE2
, btcoex
->bt_coex_mode2
);
436 REG_WRITE(ah
, AR_PHY_SWITCH_COM
, ATH_BT_COEX_ANT_DIV_SWITCH_COM
);
437 REG_RMW(ah
, AR_PHY_SWITCH_CHAIN_0
, 0, 0xf0000000);
440 * Disable antenna diversity, use LNA1 only.
442 antdiv_ctrl1
= ATH_BT_COEX_ANTDIV_CONTROL1_FIXED_A
;
443 antdiv_ctrl2
= ATH_BT_COEX_ANTDIV_CONTROL2_FIXED_A
;
446 * Disable BT Ant. to allow concurrent BT and WLAN receive.
448 btcoex
->bt_coex_mode2
|= AR_BT_DISABLE_BT_ANT
;
449 REG_WRITE(ah
, AR_BT_COEX_MODE2
, btcoex
->bt_coex_mode2
);
452 * Program SWCOM table to make sure RF switch always parks
455 REG_WRITE(ah
, AR_PHY_SWITCH_COM
, 0);
456 REG_RMW(ah
, AR_PHY_SWITCH_CHAIN_0
, 0, 0xf0000000);
459 regval
= REG_READ(ah
, AR_PHY_MULTICHAIN_GAIN_CTL
);
460 regval
&= (~(AR_PHY_9285_ANT_DIV_CTL_ALL
));
462 * Clear ant_fast_div_bias [14:9] since for WB195,
463 * the main LNA is always LNA1.
465 regval
&= (~(AR_PHY_9285_FAST_DIV_BIAS
));
466 regval
|= SM(antdiv_ctrl1
, AR_PHY_9285_ANT_DIV_CTL
);
467 regval
|= SM(antdiv_ctrl2
, AR_PHY_9285_ANT_DIV_ALT_LNACONF
);
468 regval
|= SM((antdiv_ctrl2
>> 2), AR_PHY_9285_ANT_DIV_MAIN_LNACONF
);
469 regval
|= SM((antdiv_ctrl1
>> 1), AR_PHY_9285_ANT_DIV_ALT_GAINTB
);
470 regval
|= SM((antdiv_ctrl1
>> 2), AR_PHY_9285_ANT_DIV_MAIN_GAINTB
);
471 REG_WRITE(ah
, AR_PHY_MULTICHAIN_GAIN_CTL
, regval
);
473 regval
= REG_READ(ah
, AR_PHY_CCK_DETECT
);
474 regval
&= (~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV
);
475 regval
|= SM((antdiv_ctrl1
>> 3), AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV
);
476 REG_WRITE(ah
, AR_PHY_CCK_DETECT
, regval
);
481 static void ar9002_hw_spectral_scan_config(struct ath_hw
*ah
,
482 struct ath_spec_scan
*param
)
486 if (!param
->enabled
) {
487 REG_CLR_BIT(ah
, AR_PHY_SPECTRAL_SCAN
,
488 AR_PHY_SPECTRAL_SCAN_ENABLE
);
491 REG_SET_BIT(ah
, AR_PHY_RADAR_0
, AR_PHY_RADAR_0_FFT_ENA
);
492 REG_SET_BIT(ah
, AR_PHY_SPECTRAL_SCAN
, AR_PHY_SPECTRAL_SCAN_ENABLE
);
494 if (param
->short_repeat
)
495 REG_SET_BIT(ah
, AR_PHY_SPECTRAL_SCAN
,
496 AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT
);
498 REG_CLR_BIT(ah
, AR_PHY_SPECTRAL_SCAN
,
499 AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT
);
501 /* on AR92xx, the highest bit of count will make the the chip send
502 * spectral samples endlessly. Check if this really was intended,
505 count
= param
->count
;
506 if (param
->endless
) {
507 if (AR_SREV_9271(ah
))
511 } else if (count
& 0x80)
514 REG_RMW_FIELD(ah
, AR_PHY_SPECTRAL_SCAN
,
515 AR_PHY_SPECTRAL_SCAN_COUNT
, count
);
516 REG_RMW_FIELD(ah
, AR_PHY_SPECTRAL_SCAN
,
517 AR_PHY_SPECTRAL_SCAN_PERIOD
, param
->period
);
518 REG_RMW_FIELD(ah
, AR_PHY_SPECTRAL_SCAN
,
519 AR_PHY_SPECTRAL_SCAN_FFT_PERIOD
, param
->fft_period
);
524 static void ar9002_hw_spectral_scan_trigger(struct ath_hw
*ah
)
526 REG_SET_BIT(ah
, AR_PHY_SPECTRAL_SCAN
, AR_PHY_SPECTRAL_SCAN_ENABLE
);
527 /* Activate spectral scan */
528 REG_SET_BIT(ah
, AR_PHY_SPECTRAL_SCAN
,
529 AR_PHY_SPECTRAL_SCAN_ACTIVE
);
532 static void ar9002_hw_spectral_scan_wait(struct ath_hw
*ah
)
534 struct ath_common
*common
= ath9k_hw_common(ah
);
536 /* Poll for spectral scan complete */
537 if (!ath9k_hw_wait(ah
, AR_PHY_SPECTRAL_SCAN
,
538 AR_PHY_SPECTRAL_SCAN_ACTIVE
,
539 0, AH_WAIT_TIMEOUT
)) {
540 ath_err(common
, "spectral scan wait failed\n");
545 static void ar9002_hw_tx99_start(struct ath_hw
*ah
, u32 qnum
)
547 REG_SET_BIT(ah
, 0x9864, 0x7f000);
548 REG_SET_BIT(ah
, 0x9924, 0x7f00fe);
549 REG_CLR_BIT(ah
, AR_DIAG_SW
, AR_DIAG_RX_DIS
);
550 REG_WRITE(ah
, AR_CR
, AR_CR_RXD
);
551 REG_WRITE(ah
, AR_DLCL_IFS(qnum
), 0);
552 REG_WRITE(ah
, AR_D_GBL_IFS_SIFS
, 20);
553 REG_WRITE(ah
, AR_D_GBL_IFS_EIFS
, 20);
554 REG_WRITE(ah
, AR_D_FPCTL
, 0x10|qnum
);
555 REG_WRITE(ah
, AR_TIME_OUT
, 0x00000400);
556 REG_WRITE(ah
, AR_DRETRY_LIMIT(qnum
), 0xffffffff);
557 REG_SET_BIT(ah
, AR_QMISC(qnum
), AR_Q_MISC_DCU_EARLY_TERM_REQ
);
560 static void ar9002_hw_tx99_stop(struct ath_hw
*ah
)
562 REG_SET_BIT(ah
, AR_DIAG_SW
, AR_DIAG_RX_DIS
);
565 void ar9002_hw_attach_phy_ops(struct ath_hw
*ah
)
567 struct ath_hw_private_ops
*priv_ops
= ath9k_hw_private_ops(ah
);
568 struct ath_hw_ops
*ops
= ath9k_hw_ops(ah
);
570 priv_ops
->set_rf_regs
= NULL
;
571 priv_ops
->rf_set_freq
= ar9002_hw_set_channel
;
572 priv_ops
->spur_mitigate_freq
= ar9002_hw_spur_mitigate
;
573 priv_ops
->olc_init
= ar9002_olc_init
;
574 priv_ops
->compute_pll_control
= ar9002_hw_compute_pll_control
;
575 priv_ops
->do_getnf
= ar9002_hw_do_getnf
;
577 ops
->antdiv_comb_conf_get
= ar9002_hw_antdiv_comb_conf_get
;
578 ops
->antdiv_comb_conf_set
= ar9002_hw_antdiv_comb_conf_set
;
579 ops
->spectral_scan_config
= ar9002_hw_spectral_scan_config
;
580 ops
->spectral_scan_trigger
= ar9002_hw_spectral_scan_trigger
;
581 ops
->spectral_scan_wait
= ar9002_hw_spectral_scan_wait
;
583 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
584 ops
->set_bt_ant_diversity
= ar9002_hw_set_bt_ant_diversity
;
586 ops
->tx99_start
= ar9002_hw_tx99_start
;
587 ops
->tx99_stop
= ar9002_hw_tx99_stop
;
589 ar9002_hw_set_nf_limits(ah
);