drivers/net/wireless/ath/ath9k/ar9003_hw.c

   1 /*
   2  * Copyright (c) 2008-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include "hw.h"
  18 #include "ar9003_mac.h"
  19 #include "ar9003_2p2_initvals.h"
  20 #include "ar9485_initvals.h"
  21 #include "ar9340_initvals.h"
  22 #include "ar9330_1p1_initvals.h"
  23 #include "ar9330_1p2_initvals.h"
  24 #include "ar9580_1p0_initvals.h"
  25 #include "ar9462_2p0_initvals.h"
  26
  27 /* General hardware code for the AR9003 hadware family */
  28
  29 /*
  30  * The AR9003 family uses a new INI format (pre, core, post
  31  * arrays per subsystem). This provides support for the
  32  * AR9003 2.2 chipsets.
  33  */
  34 static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
  35 {
  36 #define PCIE_PLL_ON_CREQ_DIS_L1_2P0 \
  37                 ar9462_pciephy_pll_on_clkreq_disable_L1_2p0
  38
  39 #define AR9462_BB_CTX_COEFJ(x)  \
  40                 ar9462_##x##_baseband_core_txfir_coeff_japan_2484
  41
  42 #define AR9462_BBC_TXIFR_COEFFJ \
  43                 ar9462_2p0_baseband_core_txfir_coeff_japan_2484
  44         if (AR_SREV_9330_11(ah)) {
  45                 /* mac */
  46                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
  47                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
  48                                 ar9331_1p1_mac_core,
  49                                 ARRAY_SIZE(ar9331_1p1_mac_core), 2);
  50                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
  51                                 ar9331_1p1_mac_postamble,
  52                                 ARRAY_SIZE(ar9331_1p1_mac_postamble), 5);
  53
  54                 /* bb */
  55                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
  56                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
  57                                 ar9331_1p1_baseband_core,
  58                                 ARRAY_SIZE(ar9331_1p1_baseband_core), 2);
  59                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
  60                                 ar9331_1p1_baseband_postamble,
  61                                 ARRAY_SIZE(ar9331_1p1_baseband_postamble), 5);
  62
  63                 /* radio */
  64                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
  65                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
  66                                 ar9331_1p1_radio_core,
  67                                 ARRAY_SIZE(ar9331_1p1_radio_core), 2);
  68                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], NULL, 0, 0);
  69
  70                 /* soc */
  71                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
  72                                 ar9331_1p1_soc_preamble,
  73                                 ARRAY_SIZE(ar9331_1p1_soc_preamble), 2);
  74                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
  75                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
  76                                 ar9331_1p1_soc_postamble,
  77                                 ARRAY_SIZE(ar9331_1p1_soc_postamble), 2);
  78
  79                 /* rx/tx gain */
  80                 INIT_INI_ARRAY(&ah->iniModesRxGain,
  81                                 ar9331_common_rx_gain_1p1,
  82                                 ARRAY_SIZE(ar9331_common_rx_gain_1p1), 2);
  83                 INIT_INI_ARRAY(&ah->iniModesTxGain,
  84                         ar9331_modes_lowest_ob_db_tx_gain_1p1,
  85                         ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p1),
  86                         5);
  87
  88                 /* additional clock settings */
  89                 if (ah->is_clk_25mhz)
  90                         INIT_INI_ARRAY(&ah->iniAdditional,
  91                                         ar9331_1p1_xtal_25M,
  92                                         ARRAY_SIZE(ar9331_1p1_xtal_25M), 2);
  93                 else
  94                         INIT_INI_ARRAY(&ah->iniAdditional,
  95                                         ar9331_1p1_xtal_40M,
  96                                         ARRAY_SIZE(ar9331_1p1_xtal_40M), 2);
  97         } else if (AR_SREV_9330_12(ah)) {
  98                 /* mac */
  99                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
 100                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 101                                 ar9331_1p2_mac_core,
 102                                 ARRAY_SIZE(ar9331_1p2_mac_core), 2);
 103                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 104                                 ar9331_1p2_mac_postamble,
 105                                 ARRAY_SIZE(ar9331_1p2_mac_postamble), 5);
 106
 107                 /* bb */
 108                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
 109                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 110                                 ar9331_1p2_baseband_core,
 111                                 ARRAY_SIZE(ar9331_1p2_baseband_core), 2);
 112                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 113                                 ar9331_1p2_baseband_postamble,
 114                                 ARRAY_SIZE(ar9331_1p2_baseband_postamble), 5);
 115
 116                 /* radio */
 117                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
 118                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 119                                 ar9331_1p2_radio_core,
 120                                 ARRAY_SIZE(ar9331_1p2_radio_core), 2);
 121                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], NULL, 0, 0);
 122
 123                 /* soc */
 124                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 125                                 ar9331_1p2_soc_preamble,
 126                                 ARRAY_SIZE(ar9331_1p2_soc_preamble), 2);
 127                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
 128                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 129                                 ar9331_1p2_soc_postamble,
 130                                 ARRAY_SIZE(ar9331_1p2_soc_postamble), 2);
 131
 132                 /* rx/tx gain */
 133                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 134                                 ar9331_common_rx_gain_1p2,
 135                                 ARRAY_SIZE(ar9331_common_rx_gain_1p2), 2);
 136                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 137                         ar9331_modes_lowest_ob_db_tx_gain_1p2,
 138                         ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p2),
 139                         5);
 140
 141                 /* additional clock settings */
 142                 if (ah->is_clk_25mhz)
 143                         INIT_INI_ARRAY(&ah->iniAdditional,
 144                                         ar9331_1p2_xtal_25M,
 145                                         ARRAY_SIZE(ar9331_1p2_xtal_25M), 2);
 146                 else
 147                         INIT_INI_ARRAY(&ah->iniAdditional,
 148                                         ar9331_1p2_xtal_40M,
 149                                         ARRAY_SIZE(ar9331_1p2_xtal_40M), 2);
 150         } else if (AR_SREV_9340(ah)) {
 151                 /* mac */
 152                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
 153                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 154                                 ar9340_1p0_mac_core,
 155                                 ARRAY_SIZE(ar9340_1p0_mac_core), 2);
 156                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 157                                 ar9340_1p0_mac_postamble,
 158                                 ARRAY_SIZE(ar9340_1p0_mac_postamble), 5);
 159
 160                 /* bb */
 161                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
 162                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 163                                 ar9340_1p0_baseband_core,
 164                                 ARRAY_SIZE(ar9340_1p0_baseband_core), 2);
 165                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 166                                 ar9340_1p0_baseband_postamble,
 167                                 ARRAY_SIZE(ar9340_1p0_baseband_postamble), 5);
 168
 169                 /* radio */
 170                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
 171                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 172                                 ar9340_1p0_radio_core,
 173                                 ARRAY_SIZE(ar9340_1p0_radio_core), 2);
 174                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 175                                 ar9340_1p0_radio_postamble,
 176                                 ARRAY_SIZE(ar9340_1p0_radio_postamble), 5);
 177
 178                 /* soc */
 179                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 180                                 ar9340_1p0_soc_preamble,
 181                                 ARRAY_SIZE(ar9340_1p0_soc_preamble), 2);
 182                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
 183                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 184                                 ar9340_1p0_soc_postamble,
 185                                 ARRAY_SIZE(ar9340_1p0_soc_postamble), 5);
 186
 187                 /* rx/tx gain */
 188                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 189                                 ar9340Common_wo_xlna_rx_gain_table_1p0,
 190                                 ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0),
 191                                 5);
 192                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 193                                 ar9340Modes_high_ob_db_tx_gain_table_1p0,
 194                                 ARRAY_SIZE(ar9340Modes_high_ob_db_tx_gain_table_1p0),
 195                                 5);
 196
 197                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 198                                 ar9340Modes_fast_clock_1p0,
 199                                 ARRAY_SIZE(ar9340Modes_fast_clock_1p0),
 200                                 3);
 201
 202                 if (!ah->is_clk_25mhz)
 203                         INIT_INI_ARRAY(&ah->iniAdditional,
 204                                        ar9340_1p0_radio_core_40M,
 205                                        ARRAY_SIZE(ar9340_1p0_radio_core_40M),
 206                                        2);
 207         } else if (AR_SREV_9485_11(ah)) {
 208                 /* mac */
 209                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
 210                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 211                                 ar9485_1_1_mac_core,
 212                                 ARRAY_SIZE(ar9485_1_1_mac_core), 2);
 213                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 214                                 ar9485_1_1_mac_postamble,
 215                                 ARRAY_SIZE(ar9485_1_1_mac_postamble), 5);
 216
 217                 /* bb */
 218                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_1,
 219                                 ARRAY_SIZE(ar9485_1_1), 2);
 220                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 221                                 ar9485_1_1_baseband_core,
 222                                 ARRAY_SIZE(ar9485_1_1_baseband_core), 2);
 223                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 224                                 ar9485_1_1_baseband_postamble,
 225                                 ARRAY_SIZE(ar9485_1_1_baseband_postamble), 5);
 226
 227                 /* radio */
 228                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
 229                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 230                                 ar9485_1_1_radio_core,
 231                                 ARRAY_SIZE(ar9485_1_1_radio_core), 2);
 232                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 233                                 ar9485_1_1_radio_postamble,
 234                                 ARRAY_SIZE(ar9485_1_1_radio_postamble), 2);
 235
 236                 /* soc */
 237                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 238                                 ar9485_1_1_soc_preamble,
 239                                 ARRAY_SIZE(ar9485_1_1_soc_preamble), 2);
 240                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
 241                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], NULL, 0, 0);
 242
 243                 /* rx/tx gain */
 244                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 245                                 ar9485Common_wo_xlna_rx_gain_1_1,
 246                                 ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1), 2);
 247                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 248                                 ar9485_modes_lowest_ob_db_tx_gain_1_1,
 249                                 ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
 250                                 5);
 251
 252                 /* Load PCIE SERDES settings from INI */
 253
 254                 /* Awake Setting */
 255
 256                 INIT_INI_ARRAY(&ah->iniPcieSerdes,
 257                                 ar9485_1_1_pcie_phy_clkreq_disable_L1,
 258                                 ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
 259                                 2);
 260
 261                 /* Sleep Setting */
 262
 263                 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 264                                 ar9485_1_1_pcie_phy_clkreq_disable_L1,
 265                                 ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
 266                                 2);
 267         } else if (AR_SREV_9462_20(ah)) {
 268
 269                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
 270                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core,
 271                                 ARRAY_SIZE(ar9462_2p0_mac_core), 2);
 272                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 273                                 ar9462_2p0_mac_postamble,
 274                                 ARRAY_SIZE(ar9462_2p0_mac_postamble), 5);
 275
 276                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
 277                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 278                                 ar9462_2p0_baseband_core,
 279                                 ARRAY_SIZE(ar9462_2p0_baseband_core), 2);
 280                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 281                                 ar9462_2p0_baseband_postamble,
 282                                 ARRAY_SIZE(ar9462_2p0_baseband_postamble), 5);
 283
 284                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
 285                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 286                                 ar9462_2p0_radio_core,
 287                                 ARRAY_SIZE(ar9462_2p0_radio_core), 2);
 288                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 289                                 ar9462_2p0_radio_postamble,
 290                                 ARRAY_SIZE(ar9462_2p0_radio_postamble), 5);
 291                 INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant,
 292                                 ar9462_2p0_radio_postamble_sys2ant,
 293                                 ARRAY_SIZE(ar9462_2p0_radio_postamble_sys2ant),
 294                                 5);
 295
 296                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 297                                 ar9462_2p0_soc_preamble,
 298                                 ARRAY_SIZE(ar9462_2p0_soc_preamble), 2);
 299                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
 300                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 301                                 ar9462_2p0_soc_postamble,
 302                                 ARRAY_SIZE(ar9462_2p0_soc_postamble), 5);
 303
 304                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 305                                 ar9462_common_rx_gain_table_2p0,
 306                                 ARRAY_SIZE(ar9462_common_rx_gain_table_2p0), 2);
 307
 308                 INIT_INI_ARRAY(&ah->ini_BTCOEX_MAX_TXPWR,
 309                                 ar9462_2p0_BTCOEX_MAX_TXPWR_table,
 310                                 ARRAY_SIZE(ar9462_2p0_BTCOEX_MAX_TXPWR_table),
 311                                 2);
 312
 313                 /* Awake -> Sleep Setting */
 314                 INIT_INI_ARRAY(&ah->iniPcieSerdes,
 315                                 PCIE_PLL_ON_CREQ_DIS_L1_2P0,
 316                                 ARRAY_SIZE(PCIE_PLL_ON_CREQ_DIS_L1_2P0),
 317                                 2);
 318                 /* Sleep -> Awake Setting */
 319                 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 320                                 PCIE_PLL_ON_CREQ_DIS_L1_2P0,
 321                                 ARRAY_SIZE(PCIE_PLL_ON_CREQ_DIS_L1_2P0),
 322                                 2);
 323
 324                 /* Fast clock modal settings */
 325                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 326                                 ar9462_modes_fast_clock_2p0,
 327                                 ARRAY_SIZE(ar9462_modes_fast_clock_2p0), 3);
 328
 329                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 330                                 AR9462_BB_CTX_COEFJ(2p0),
 331                                 ARRAY_SIZE(AR9462_BB_CTX_COEFJ(2p0)), 2);
 332
 333                 INIT_INI_ARRAY(&ah->ini_japan2484, AR9462_BBC_TXIFR_COEFFJ,
 334                                 ARRAY_SIZE(AR9462_BBC_TXIFR_COEFFJ), 2);
 335
 336         } else if (AR_SREV_9580(ah)) {
 337                 /* mac */
 338                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
 339                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 340                                 ar9580_1p0_mac_core,
 341                                 ARRAY_SIZE(ar9580_1p0_mac_core), 2);
 342                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 343                                 ar9580_1p0_mac_postamble,
 344                                 ARRAY_SIZE(ar9580_1p0_mac_postamble), 5);
 345
 346                 /* bb */
 347                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
 348                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 349                                 ar9580_1p0_baseband_core,
 350                                 ARRAY_SIZE(ar9580_1p0_baseband_core), 2);
 351                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 352                                 ar9580_1p0_baseband_postamble,
 353                                 ARRAY_SIZE(ar9580_1p0_baseband_postamble), 5);
 354
 355                 /* radio */
 356                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
 357                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 358                                 ar9580_1p0_radio_core,
 359                                 ARRAY_SIZE(ar9580_1p0_radio_core), 2);
 360                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 361                                 ar9580_1p0_radio_postamble,
 362                                 ARRAY_SIZE(ar9580_1p0_radio_postamble), 5);
 363
 364                 /* soc */
 365                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 366                                 ar9580_1p0_soc_preamble,
 367                                 ARRAY_SIZE(ar9580_1p0_soc_preamble), 2);
 368                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
 369                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 370                                 ar9580_1p0_soc_postamble,
 371                                 ARRAY_SIZE(ar9580_1p0_soc_postamble), 5);
 372
 373                 /* rx/tx gain */
 374                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 375                                 ar9580_1p0_rx_gain_table,
 376                                 ARRAY_SIZE(ar9580_1p0_rx_gain_table), 2);
 377                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 378                                 ar9580_1p0_low_ob_db_tx_gain_table,
 379                                 ARRAY_SIZE(ar9580_1p0_low_ob_db_tx_gain_table),
 380                                 5);
 381
 382                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 383                                 ar9580_1p0_modes_fast_clock,
 384                                 ARRAY_SIZE(ar9580_1p0_modes_fast_clock),
 385                                 3);
 386         } else {
 387                 /* mac */
 388                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
 389                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 390                                 ar9300_2p2_mac_core,
 391                                 ARRAY_SIZE(ar9300_2p2_mac_core), 2);
 392                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 393                                 ar9300_2p2_mac_postamble,
 394                                 ARRAY_SIZE(ar9300_2p2_mac_postamble), 5);
 395
 396                 /* bb */
 397                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
 398                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 399                                 ar9300_2p2_baseband_core,
 400                                 ARRAY_SIZE(ar9300_2p2_baseband_core), 2);
 401                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 402                                 ar9300_2p2_baseband_postamble,
 403                                 ARRAY_SIZE(ar9300_2p2_baseband_postamble), 5);
 404
 405                 /* radio */
 406                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
 407                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 408                                 ar9300_2p2_radio_core,
 409                                 ARRAY_SIZE(ar9300_2p2_radio_core), 2);
 410                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 411                                 ar9300_2p2_radio_postamble,
 412                                 ARRAY_SIZE(ar9300_2p2_radio_postamble), 5);
 413
 414                 /* soc */
 415                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 416                                 ar9300_2p2_soc_preamble,
 417                                 ARRAY_SIZE(ar9300_2p2_soc_preamble), 2);
 418                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
 419                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 420                                 ar9300_2p2_soc_postamble,
 421                                 ARRAY_SIZE(ar9300_2p2_soc_postamble), 5);
 422
 423                 /* rx/tx gain */
 424                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 425                                 ar9300Common_rx_gain_table_2p2,
 426                                 ARRAY_SIZE(ar9300Common_rx_gain_table_2p2), 2);
 427                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 428                                 ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
 429                                 ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
 430                                 5);
 431
 432                 /* Load PCIE SERDES settings from INI */
 433
 434                 /* Awake Setting */
 435
 436                 INIT_INI_ARRAY(&ah->iniPcieSerdes,
 437                                 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
 438                                 ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
 439                                 2);
 440
 441                 /* Sleep Setting */
 442
 443                 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 444                                 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
 445                                 ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
 446                                 2);
 447
 448                 /* Fast clock modal settings */
 449                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 450                                 ar9300Modes_fast_clock_2p2,
 451                                 ARRAY_SIZE(ar9300Modes_fast_clock_2p2),
 452                                 3);
 453         }
 454 }
 455
 456 static void ar9003_tx_gain_table_mode0(struct ath_hw *ah)
 457 {
 458         if (AR_SREV_9330_12(ah))
 459                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 460                         ar9331_modes_lowest_ob_db_tx_gain_1p2,
 461                         ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p2),
 462                         5);
 463         else if (AR_SREV_9330_11(ah))
 464                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 465                         ar9331_modes_lowest_ob_db_tx_gain_1p1,
 466                         ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p1),
 467                         5);
 468         else if (AR_SREV_9340(ah))
 469                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 470                         ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
 471                         ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
 472                         5);
 473         else if (AR_SREV_9485_11(ah))
 474                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 475                         ar9485_modes_lowest_ob_db_tx_gain_1_1,
 476                         ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
 477                         5);
 478         else if (AR_SREV_9580(ah))
 479                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 480                         ar9580_1p0_lowest_ob_db_tx_gain_table,
 481                         ARRAY_SIZE(ar9580_1p0_lowest_ob_db_tx_gain_table),
 482                         5);
 483         else if (AR_SREV_9462_20(ah))
 484                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 485                         ar9462_modes_low_ob_db_tx_gain_table_2p0,
 486                         ARRAY_SIZE(ar9462_modes_low_ob_db_tx_gain_table_2p0),
 487                         5);
 488         else
 489                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 490                         ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
 491                         ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
 492                         5);
 493 }
 494
 495 static void ar9003_tx_gain_table_mode1(struct ath_hw *ah)
 496 {
 497         if (AR_SREV_9330_12(ah))
 498                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 499                         ar9331_modes_high_ob_db_tx_gain_1p2,
 500                         ARRAY_SIZE(ar9331_modes_high_ob_db_tx_gain_1p2),
 501                         5);
 502         else if (AR_SREV_9330_11(ah))
 503                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 504                         ar9331_modes_high_ob_db_tx_gain_1p1,
 505                         ARRAY_SIZE(ar9331_modes_high_ob_db_tx_gain_1p1),
 506                         5);
 507         else if (AR_SREV_9340(ah))
 508                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 509                         ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
 510                         ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
 511                         5);
 512         else if (AR_SREV_9485_11(ah))
 513                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 514                         ar9485Modes_high_ob_db_tx_gain_1_1,
 515                         ARRAY_SIZE(ar9485Modes_high_ob_db_tx_gain_1_1),
 516                         5);
 517         else if (AR_SREV_9580(ah))
 518                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 519                         ar9580_1p0_high_ob_db_tx_gain_table,
 520                         ARRAY_SIZE(ar9580_1p0_high_ob_db_tx_gain_table),
 521                         5);
 522         else if (AR_SREV_9462_20(ah))
 523                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 524                         ar9462_modes_high_ob_db_tx_gain_table_2p0,
 525                         ARRAY_SIZE(ar9462_modes_high_ob_db_tx_gain_table_2p0),
 526                         5);
 527         else
 528                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 529                         ar9300Modes_high_ob_db_tx_gain_table_2p2,
 530                         ARRAY_SIZE(ar9300Modes_high_ob_db_tx_gain_table_2p2),
 531                         5);
 532 }
 533
 534 static void ar9003_tx_gain_table_mode2(struct ath_hw *ah)
 535 {
 536         if (AR_SREV_9330_12(ah))
 537                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 538                         ar9331_modes_low_ob_db_tx_gain_1p2,
 539                         ARRAY_SIZE(ar9331_modes_low_ob_db_tx_gain_1p2),
 540                         5);
 541         else if (AR_SREV_9330_11(ah))
 542                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 543                         ar9331_modes_low_ob_db_tx_gain_1p1,
 544                         ARRAY_SIZE(ar9331_modes_low_ob_db_tx_gain_1p1),
 545                         5);
 546         else if (AR_SREV_9340(ah))
 547                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 548                         ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
 549                         ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
 550                         5);
 551         else if (AR_SREV_9485_11(ah))
 552                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 553                         ar9485Modes_low_ob_db_tx_gain_1_1,
 554                         ARRAY_SIZE(ar9485Modes_low_ob_db_tx_gain_1_1),
 555                         5);
 556         else if (AR_SREV_9580(ah))
 557                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 558                         ar9580_1p0_low_ob_db_tx_gain_table,
 559                         ARRAY_SIZE(ar9580_1p0_low_ob_db_tx_gain_table),
 560                         5);
 561         else
 562                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 563                         ar9300Modes_low_ob_db_tx_gain_table_2p2,
 564                         ARRAY_SIZE(ar9300Modes_low_ob_db_tx_gain_table_2p2),
 565                         5);
 566 }
 567
 568 static void ar9003_tx_gain_table_mode3(struct ath_hw *ah)
 569 {
 570         if (AR_SREV_9330_12(ah))
 571                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 572                         ar9331_modes_high_power_tx_gain_1p2,
 573                         ARRAY_SIZE(ar9331_modes_high_power_tx_gain_1p2),
 574                         5);
 575         else if (AR_SREV_9330_11(ah))
 576                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 577                         ar9331_modes_high_power_tx_gain_1p1,
 578                         ARRAY_SIZE(ar9331_modes_high_power_tx_gain_1p1),
 579                         5);
 580         else if (AR_SREV_9340(ah))
 581                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 582                         ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
 583                         ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
 584                         5);
 585         else if (AR_SREV_9485_11(ah))
 586                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 587                         ar9485Modes_high_power_tx_gain_1_1,
 588                         ARRAY_SIZE(ar9485Modes_high_power_tx_gain_1_1),
 589                         5);
 590         else if (AR_SREV_9580(ah))
 591                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 592                         ar9580_1p0_high_power_tx_gain_table,
 593                         ARRAY_SIZE(ar9580_1p0_high_power_tx_gain_table),
 594                         5);
 595         else
 596                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 597                         ar9300Modes_high_power_tx_gain_table_2p2,
 598                         ARRAY_SIZE(ar9300Modes_high_power_tx_gain_table_2p2),
 599                         5);
 600 }
 601
 602 static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
 603 {
 604         switch (ar9003_hw_get_tx_gain_idx(ah)) {
 605         case 0:
 606         default:
 607                 ar9003_tx_gain_table_mode0(ah);
 608                 break;
 609         case 1:
 610                 ar9003_tx_gain_table_mode1(ah);
 611                 break;
 612         case 2:
 613                 ar9003_tx_gain_table_mode2(ah);
 614                 break;
 615         case 3:
 616                 ar9003_tx_gain_table_mode3(ah);
 617                 break;
 618         }
 619 }
 620
 621 static void ar9003_rx_gain_table_mode0(struct ath_hw *ah)
 622 {
 623         if (AR_SREV_9330_12(ah))
 624                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 625                                 ar9331_common_rx_gain_1p2,
 626                                 ARRAY_SIZE(ar9331_common_rx_gain_1p2),
 627                                 2);
 628         else if (AR_SREV_9330_11(ah))
 629                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 630                                 ar9331_common_rx_gain_1p1,
 631                                 ARRAY_SIZE(ar9331_common_rx_gain_1p1),
 632                                 2);
 633         else if (AR_SREV_9340(ah))
 634                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 635                                 ar9340Common_rx_gain_table_1p0,
 636                                 ARRAY_SIZE(ar9340Common_rx_gain_table_1p0),
 637                                 2);
 638         else if (AR_SREV_9485_11(ah))
 639                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 640                                 ar9485Common_wo_xlna_rx_gain_1_1,
 641                                 ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
 642                                 2);
 643         else if (AR_SREV_9580(ah))
 644                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 645                                 ar9580_1p0_rx_gain_table,
 646                                 ARRAY_SIZE(ar9580_1p0_rx_gain_table),
 647                                 2);
 648         else if (AR_SREV_9462_20(ah))
 649                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 650                                 ar9462_common_rx_gain_table_2p0,
 651                                 ARRAY_SIZE(ar9462_common_rx_gain_table_2p0),
 652                                 2);
 653         else
 654                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 655                                 ar9300Common_rx_gain_table_2p2,
 656                                 ARRAY_SIZE(ar9300Common_rx_gain_table_2p2),
 657                                 2);
 658 }
 659
 660 static void ar9003_rx_gain_table_mode1(struct ath_hw *ah)
 661 {
 662         if (AR_SREV_9330_12(ah))
 663                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 664                         ar9331_common_wo_xlna_rx_gain_1p2,
 665                         ARRAY_SIZE(ar9331_common_wo_xlna_rx_gain_1p2),
 666                         2);
 667         else if (AR_SREV_9330_11(ah))
 668                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 669                         ar9331_common_wo_xlna_rx_gain_1p1,
 670                         ARRAY_SIZE(ar9331_common_wo_xlna_rx_gain_1p1),
 671                         2);
 672         else if (AR_SREV_9340(ah))
 673                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 674                         ar9340Common_wo_xlna_rx_gain_table_1p0,
 675                         ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0),
 676                         2);
 677         else if (AR_SREV_9485_11(ah))
 678                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 679                         ar9485Common_wo_xlna_rx_gain_1_1,
 680                         ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
 681                         2);
 682         else if (AR_SREV_9462_20(ah))
 683                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 684                         ar9462_common_wo_xlna_rx_gain_table_2p0,
 685                         ARRAY_SIZE(ar9462_common_wo_xlna_rx_gain_table_2p0),
 686                         2);
 687         else if (AR_SREV_9580(ah))
 688                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 689                         ar9580_1p0_wo_xlna_rx_gain_table,
 690                         ARRAY_SIZE(ar9580_1p0_wo_xlna_rx_gain_table),
 691                         2);
 692         else
 693                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 694                         ar9300Common_wo_xlna_rx_gain_table_2p2,
 695                         ARRAY_SIZE(ar9300Common_wo_xlna_rx_gain_table_2p2),
 696                         2);
 697 }
 698
 699 static void ar9003_rx_gain_table_mode2(struct ath_hw *ah)
 700 {
 701         if (AR_SREV_9462_20(ah))
 702                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 703                                ar9462_common_mixed_rx_gain_table_2p0,
 704                                ARRAY_SIZE(ar9462_common_mixed_rx_gain_table_2p0), 2);
 705 }
 706
 707 static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
 708 {
 709         switch (ar9003_hw_get_rx_gain_idx(ah)) {
 710         case 0:
 711         default:
 712                 ar9003_rx_gain_table_mode0(ah);
 713                 break;
 714         case 1:
 715                 ar9003_rx_gain_table_mode1(ah);
 716                 break;
 717         case 2:
 718                 ar9003_rx_gain_table_mode2(ah);
 719                 break;
 720         }
 721 }
 722
 723 /* set gain table pointers according to values read from the eeprom */
 724 static void ar9003_hw_init_mode_gain_regs(struct ath_hw *ah)
 725 {
 726         ar9003_tx_gain_table_apply(ah);
 727         ar9003_rx_gain_table_apply(ah);
 728 }
 729
 730 /*
 731  * Helper for ASPM support.
 732  *
 733  * Disable PLL when in L0s as well as receiver clock when in L1.
 734  * This power saving option must be enabled through the SerDes.
 735  *
 736  * Programming the SerDes must go through the same 288 bit serial shift
 737  * register as the other analog registers.  Hence the 9 writes.
 738  */
 739 static void ar9003_hw_configpcipowersave(struct ath_hw *ah,
 740                                          bool power_off)
 741 {
 742         /* Nothing to do on restore for 11N */
 743         if (!power_off /* !restore */) {
 744                 /* set bit 19 to allow forcing of pcie core into L1 state */
 745                 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
 746
 747                 /* Several PCIe massages to ensure proper behaviour */
 748                 if (ah->config.pcie_waen)
 749                         REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
 750                 else
 751                         REG_WRITE(ah, AR_WA, ah->WARegVal);
 752         }
 753
 754         /*
 755          * Configire PCIE after Ini init. SERDES values now come from ini file
 756          * This enables PCIe low power mode.
 757          */
 758         if (ah->config.pcieSerDesWrite) {
 759                 unsigned int i;
 760                 struct ar5416IniArray *array;
 761
 762                 array = power_off ? &ah->iniPcieSerdes :
 763                                     &ah->iniPcieSerdesLowPower;
 764
 765                 for (i = 0; i < array->ia_rows; i++) {
 766                         REG_WRITE(ah,
 767                                   INI_RA(array, i, 0),
 768                                   INI_RA(array, i, 1));
 769                 }
 770         }
 771 }
 772
 773 /* Sets up the AR9003 hardware familiy callbacks */
 774 void ar9003_hw_attach_ops(struct ath_hw *ah)
 775 {
 776         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
 777         struct ath_hw_ops *ops = ath9k_hw_ops(ah);
 778
 779         priv_ops->init_mode_regs = ar9003_hw_init_mode_regs;
 780         priv_ops->init_mode_gain_regs = ar9003_hw_init_mode_gain_regs;
 781
 782         ops->config_pci_powersave = ar9003_hw_configpcipowersave;
 783
 784         ar9003_hw_attach_phy_ops(ah);
 785         ar9003_hw_attach_calib_ops(ah);
 786         ar9003_hw_attach_mac_ops(ah);
 787 }