drivers/net/wireless/ath/ath9k/ar9003_hw.c

   1 /*
   2  * Copyright (c) 2008-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include "hw.h"
  18 #include "ar9003_mac.h"
  19 #include "ar9003_2p2_initvals.h"
  20 #include "ar9003_buffalo_initvals.h"
  21 #include "ar9485_initvals.h"
  22 #include "ar9340_initvals.h"
  23 #include "ar9330_1p1_initvals.h"
  24 #include "ar9330_1p2_initvals.h"
  25 #include "ar955x_1p0_initvals.h"
  26 #include "ar9580_1p0_initvals.h"
  27 #include "ar9462_2p0_initvals.h"
  28 #include "ar9462_2p1_initvals.h"
  29 #include "ar9565_1p0_initvals.h"
  30 #include "ar9565_1p1_initvals.h"
  31 #include "ar953x_initvals.h"
  32
  33 /* General hardware code for the AR9003 hadware family */
  34
  35 /*
  36  * The AR9003 family uses a new INI format (pre, core, post
  37  * arrays per subsystem). This provides support for the
  38  * AR9003 2.2 chipsets.
  39  */
  40 static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
  41 {
  42         if (AR_SREV_9330_11(ah)) {
  43                 /* mac */
  44                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
  45                                 ar9331_1p1_mac_core);
  46                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
  47                                 ar9331_1p1_mac_postamble);
  48
  49                 /* bb */
  50                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
  51                                 ar9331_1p1_baseband_core);
  52                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
  53                                 ar9331_1p1_baseband_postamble);
  54
  55                 /* radio */
  56                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
  57                                 ar9331_1p1_radio_core);
  58
  59                 /* soc */
  60                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
  61                                 ar9331_1p1_soc_preamble);
  62                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
  63                                 ar9331_1p1_soc_postamble);
  64
  65                 /* rx/tx gain */
  66                 INIT_INI_ARRAY(&ah->iniModesRxGain,
  67                                 ar9331_common_rx_gain_1p1);
  68                 INIT_INI_ARRAY(&ah->iniModesTxGain,
  69                                 ar9331_modes_lowest_ob_db_tx_gain_1p1);
  70
  71                 /* Japan 2484 Mhz CCK */
  72                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
  73                                ar9331_1p1_baseband_core_txfir_coeff_japan_2484);
  74
  75                 /* additional clock settings */
  76                 if (ah->is_clk_25mhz)
  77                         INIT_INI_ARRAY(&ah->iniAdditional,
  78                                         ar9331_1p1_xtal_25M);
  79                 else
  80                         INIT_INI_ARRAY(&ah->iniAdditional,
  81                                         ar9331_1p1_xtal_40M);
  82         } else if (AR_SREV_9330_12(ah)) {
  83                 /* mac */
  84                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
  85                                 ar9331_1p2_mac_core);
  86                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
  87                                 ar9331_1p2_mac_postamble);
  88
  89                 /* bb */
  90                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
  91                                 ar9331_1p2_baseband_core);
  92                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
  93                                 ar9331_1p2_baseband_postamble);
  94
  95                 /* radio */
  96                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
  97                                 ar9331_1p2_radio_core);
  98
  99                 /* soc */
 100                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 101                                 ar9331_1p2_soc_preamble);
 102                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 103                                 ar9331_1p2_soc_postamble);
 104
 105                 /* rx/tx gain */
 106                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 107                                 ar9331_common_rx_gain_1p2);
 108                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 109                                 ar9331_modes_lowest_ob_db_tx_gain_1p2);
 110
 111                 /* Japan 2484 Mhz CCK */
 112                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 113                                ar9331_1p2_baseband_core_txfir_coeff_japan_2484);
 114
 115                 /* additional clock settings */
 116                 if (ah->is_clk_25mhz)
 117                         INIT_INI_ARRAY(&ah->iniAdditional,
 118                                         ar9331_1p2_xtal_25M);
 119                 else
 120                         INIT_INI_ARRAY(&ah->iniAdditional,
 121                                         ar9331_1p2_xtal_40M);
 122         } else if (AR_SREV_9340(ah)) {
 123                 /* mac */
 124                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 125                                 ar9340_1p0_mac_core);
 126                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 127                                 ar9340_1p0_mac_postamble);
 128
 129                 /* bb */
 130                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 131                                 ar9340_1p0_baseband_core);
 132                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 133                                 ar9340_1p0_baseband_postamble);
 134
 135                 /* radio */
 136                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 137                                 ar9340_1p0_radio_core);
 138                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 139                                 ar9340_1p0_radio_postamble);
 140
 141                 /* soc */
 142                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 143                                 ar9340_1p0_soc_preamble);
 144                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 145                                 ar9340_1p0_soc_postamble);
 146
 147                 /* rx/tx gain */
 148                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 149                                 ar9340Common_wo_xlna_rx_gain_table_1p0);
 150                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 151                                 ar9340Modes_high_ob_db_tx_gain_table_1p0);
 152
 153                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 154                                ar9340Modes_fast_clock_1p0);
 155                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 156                                ar9340_1p0_baseband_core_txfir_coeff_japan_2484);
 157                 INIT_INI_ARRAY(&ah->ini_dfs,
 158                                ar9340_1p0_baseband_postamble_dfs_channel);
 159
 160                 if (!ah->is_clk_25mhz)
 161                         INIT_INI_ARRAY(&ah->iniAdditional,
 162                                        ar9340_1p0_radio_core_40M);
 163         } else if (AR_SREV_9485_11_OR_LATER(ah)) {
 164                 /* mac */
 165                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 166                                 ar9485_1_1_mac_core);
 167                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 168                                 ar9485_1_1_mac_postamble);
 169
 170                 /* bb */
 171                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_1);
 172                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 173                                 ar9485_1_1_baseband_core);
 174                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 175                                 ar9485_1_1_baseband_postamble);
 176
 177                 /* radio */
 178                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 179                                 ar9485_1_1_radio_core);
 180                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 181                                 ar9485_1_1_radio_postamble);
 182
 183                 /* soc */
 184                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 185                                 ar9485_1_1_soc_preamble);
 186
 187                 /* rx/tx gain */
 188                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 189                                 ar9485Common_wo_xlna_rx_gain_1_1);
 190                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 191                                 ar9485_modes_lowest_ob_db_tx_gain_1_1);
 192
 193                 /* Japan 2484 Mhz CCK */
 194                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 195                                ar9485_1_1_baseband_core_txfir_coeff_japan_2484);
 196
 197                 if (ah->config.no_pll_pwrsave) {
 198                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 199                                        ar9485_1_1_pcie_phy_clkreq_disable_L1);
 200                         INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 201                                        ar9485_1_1_pcie_phy_clkreq_disable_L1);
 202                 } else {
 203                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 204                                        ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);
 205                         INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 206                                        ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);
 207                 }
 208         } else if (AR_SREV_9462_21(ah)) {
 209                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 210                                ar9462_2p1_mac_core);
 211                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 212                                ar9462_2p1_mac_postamble);
 213                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 214                                ar9462_2p1_baseband_core);
 215                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 216                                ar9462_2p1_baseband_postamble);
 217                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 218                                ar9462_2p1_radio_core);
 219                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 220                                ar9462_2p1_radio_postamble);
 221                 INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant,
 222                                ar9462_2p1_radio_postamble_sys2ant);
 223                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 224                                ar9462_2p1_soc_preamble);
 225                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 226                                ar9462_2p1_soc_postamble);
 227                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 228                                ar9462_2p1_common_rx_gain);
 229                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 230                                ar9462_2p1_modes_fast_clock);
 231                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 232                                ar9462_2p1_baseband_core_txfir_coeff_japan_2484);
 233                 INIT_INI_ARRAY(&ah->iniPcieSerdes,
 234                                ar9462_2p1_pciephy_clkreq_disable_L1);
 235                 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 236                                ar9462_2p1_pciephy_clkreq_disable_L1);
 237         } else if (AR_SREV_9462_20(ah)) {
 238
 239                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core);
 240                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 241                                 ar9462_2p0_mac_postamble);
 242
 243                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 244                                 ar9462_2p0_baseband_core);
 245                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 246                                 ar9462_2p0_baseband_postamble);
 247
 248                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 249                                 ar9462_2p0_radio_core);
 250                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 251                                 ar9462_2p0_radio_postamble);
 252                 INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant,
 253                                 ar9462_2p0_radio_postamble_sys2ant);
 254
 255                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 256                                 ar9462_2p0_soc_preamble);
 257                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 258                                 ar9462_2p0_soc_postamble);
 259
 260                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 261                                 ar9462_2p0_common_rx_gain);
 262
 263                 /* Awake -> Sleep Setting */
 264                 INIT_INI_ARRAY(&ah->iniPcieSerdes,
 265                                ar9462_2p0_pciephy_clkreq_disable_L1);
 266                 /* Sleep -> Awake Setting */
 267                 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 268                                ar9462_2p0_pciephy_clkreq_disable_L1);
 269
 270                 /* Fast clock modal settings */
 271                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 272                                 ar9462_2p0_modes_fast_clock);
 273
 274                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 275                                ar9462_2p0_baseband_core_txfir_coeff_japan_2484);
 276         } else if (AR_SREV_9550(ah)) {
 277                 /* mac */
 278                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 279                                 ar955x_1p0_mac_core);
 280                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 281                                 ar955x_1p0_mac_postamble);
 282
 283                 /* bb */
 284                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 285                                 ar955x_1p0_baseband_core);
 286                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 287                                 ar955x_1p0_baseband_postamble);
 288
 289                 /* radio */
 290                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 291                                 ar955x_1p0_radio_core);
 292                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 293                                 ar955x_1p0_radio_postamble);
 294
 295                 /* soc */
 296                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 297                                 ar955x_1p0_soc_preamble);
 298                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 299                                 ar955x_1p0_soc_postamble);
 300
 301                 /* rx/tx gain */
 302                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 303                         ar955x_1p0_common_wo_xlna_rx_gain_table);
 304                 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
 305                         ar955x_1p0_common_wo_xlna_rx_gain_bounds);
 306                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 307                                 ar955x_1p0_modes_xpa_tx_gain_table);
 308
 309                 /* Fast clock modal settings */
 310                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 311                                 ar955x_1p0_modes_fast_clock);
 312         } else if (AR_SREV_9531(ah)) {
 313                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 314                                qca953x_1p0_mac_core);
 315                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 316                                qca953x_1p0_mac_postamble);
 317                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 318                                qca953x_1p0_baseband_core);
 319                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 320                                qca953x_1p0_baseband_postamble);
 321                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 322                                qca953x_1p0_radio_core);
 323                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 324                                qca953x_1p0_radio_postamble);
 325                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 326                                qca953x_1p0_soc_preamble);
 327                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 328                                qca953x_1p0_soc_postamble);
 329                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 330                                qca953x_1p0_common_wo_xlna_rx_gain_table);
 331                 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
 332                                qca953x_1p0_common_wo_xlna_rx_gain_bounds);
 333                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 334                                qca953x_1p0_modes_no_xpa_tx_gain_table);
 335                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 336                                qca953x_1p0_modes_fast_clock);
 337         } else if (AR_SREV_9580(ah)) {
 338                 /* mac */
 339                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 340                                 ar9580_1p0_mac_core);
 341                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 342                                 ar9580_1p0_mac_postamble);
 343
 344                 /* bb */
 345                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 346                                 ar9580_1p0_baseband_core);
 347                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 348                                 ar9580_1p0_baseband_postamble);
 349
 350                 /* radio */
 351                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 352                                 ar9580_1p0_radio_core);
 353                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 354                                 ar9580_1p0_radio_postamble);
 355
 356                 /* soc */
 357                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 358                                 ar9580_1p0_soc_preamble);
 359                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 360                                 ar9580_1p0_soc_postamble);
 361
 362                 /* rx/tx gain */
 363                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 364                                 ar9580_1p0_rx_gain_table);
 365                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 366                                 ar9580_1p0_low_ob_db_tx_gain_table);
 367
 368                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 369                                ar9580_1p0_modes_fast_clock);
 370                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 371                                ar9580_1p0_baseband_core_txfir_coeff_japan_2484);
 372                 INIT_INI_ARRAY(&ah->ini_dfs,
 373                                ar9580_1p0_baseband_postamble_dfs_channel);
 374         } else if (AR_SREV_9565_11_OR_LATER(ah)) {
 375                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 376                                ar9565_1p1_mac_core);
 377                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 378                                ar9565_1p1_mac_postamble);
 379
 380                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 381                                ar9565_1p1_baseband_core);
 382                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 383                                ar9565_1p1_baseband_postamble);
 384
 385                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 386                                ar9565_1p1_radio_core);
 387                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 388                                ar9565_1p1_radio_postamble);
 389
 390                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 391                                ar9565_1p1_soc_preamble);
 392                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 393                                ar9565_1p1_soc_postamble);
 394
 395                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 396                                ar9565_1p1_Common_rx_gain_table);
 397                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 398                                ar9565_1p1_Modes_lowest_ob_db_tx_gain_table);
 399
 400                 INIT_INI_ARRAY(&ah->iniPcieSerdes,
 401                                ar9565_1p1_pciephy_clkreq_disable_L1);
 402                 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 403                                ar9565_1p1_pciephy_clkreq_disable_L1);
 404
 405                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 406                                 ar9565_1p1_modes_fast_clock);
 407                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 408                                ar9565_1p1_baseband_core_txfir_coeff_japan_2484);
 409         } else if (AR_SREV_9565(ah)) {
 410                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 411                                ar9565_1p0_mac_core);
 412                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 413                                ar9565_1p0_mac_postamble);
 414
 415                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 416                                ar9565_1p0_baseband_core);
 417                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 418                                ar9565_1p0_baseband_postamble);
 419
 420                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 421                                ar9565_1p0_radio_core);
 422                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 423                                ar9565_1p0_radio_postamble);
 424
 425                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 426                                ar9565_1p0_soc_preamble);
 427                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 428                                ar9565_1p0_soc_postamble);
 429
 430                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 431                                ar9565_1p0_Common_rx_gain_table);
 432                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 433                                ar9565_1p0_Modes_lowest_ob_db_tx_gain_table);
 434
 435                 INIT_INI_ARRAY(&ah->iniPcieSerdes,
 436                                ar9565_1p0_pciephy_clkreq_disable_L1);
 437                 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 438                                ar9565_1p0_pciephy_clkreq_disable_L1);
 439
 440                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 441                                 ar9565_1p0_modes_fast_clock);
 442                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 443                                ar9565_1p0_baseband_core_txfir_coeff_japan_2484);
 444         } else {
 445                 /* mac */
 446                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 447                                 ar9300_2p2_mac_core);
 448                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 449                                 ar9300_2p2_mac_postamble);
 450
 451                 /* bb */
 452                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 453                                 ar9300_2p2_baseband_core);
 454                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 455                                 ar9300_2p2_baseband_postamble);
 456
 457                 /* radio */
 458                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 459                                 ar9300_2p2_radio_core);
 460                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 461                                 ar9300_2p2_radio_postamble);
 462
 463                 /* soc */
 464                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 465                                 ar9300_2p2_soc_preamble);
 466                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 467                                 ar9300_2p2_soc_postamble);
 468
 469                 /* rx/tx gain */
 470                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 471                                 ar9300Common_rx_gain_table_2p2);
 472                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 473                                 ar9300Modes_lowest_ob_db_tx_gain_table_2p2);
 474
 475                 /* Load PCIE SERDES settings from INI */
 476
 477                 /* Awake Setting */
 478
 479                 INIT_INI_ARRAY(&ah->iniPcieSerdes,
 480                                 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2);
 481
 482                 /* Sleep Setting */
 483
 484                 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 485                                 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2);
 486
 487                 /* Fast clock modal settings */
 488                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 489                                ar9300Modes_fast_clock_2p2);
 490                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 491                                ar9300_2p2_baseband_core_txfir_coeff_japan_2484);
 492                 INIT_INI_ARRAY(&ah->ini_dfs,
 493                                ar9300_2p2_baseband_postamble_dfs_channel);
 494         }
 495 }
 496
 497 static void ar9003_tx_gain_table_mode0(struct ath_hw *ah)
 498 {
 499         if (AR_SREV_9330_12(ah))
 500                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 501                         ar9331_modes_lowest_ob_db_tx_gain_1p2);
 502         else if (AR_SREV_9330_11(ah))
 503                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 504                         ar9331_modes_lowest_ob_db_tx_gain_1p1);
 505         else if (AR_SREV_9340(ah))
 506                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 507                         ar9340Modes_lowest_ob_db_tx_gain_table_1p0);
 508         else if (AR_SREV_9485_11_OR_LATER(ah))
 509                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 510                         ar9485_modes_lowest_ob_db_tx_gain_1_1);
 511         else if (AR_SREV_9550(ah))
 512                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 513                         ar955x_1p0_modes_xpa_tx_gain_table);
 514         else if (AR_SREV_9531(ah))
 515                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 516                         qca953x_1p0_modes_xpa_tx_gain_table);
 517         else if (AR_SREV_9580(ah))
 518                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 519                         ar9580_1p0_lowest_ob_db_tx_gain_table);
 520         else if (AR_SREV_9462_21(ah))
 521                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 522                         ar9462_2p1_modes_low_ob_db_tx_gain);
 523         else if (AR_SREV_9462_20(ah))
 524                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 525                         ar9462_2p0_modes_low_ob_db_tx_gain);
 526         else if (AR_SREV_9565_11(ah))
 527                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 528                                ar9565_1p1_modes_low_ob_db_tx_gain_table);
 529         else if (AR_SREV_9565(ah))
 530                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 531                                ar9565_1p0_modes_low_ob_db_tx_gain_table);
 532         else
 533                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 534                         ar9300Modes_lowest_ob_db_tx_gain_table_2p2);
 535 }
 536
 537 static void ar9003_tx_gain_table_mode1(struct ath_hw *ah)
 538 {
 539         if (AR_SREV_9330_12(ah))
 540                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 541                         ar9331_modes_high_ob_db_tx_gain_1p2);
 542         else if (AR_SREV_9330_11(ah))
 543                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 544                         ar9331_modes_high_ob_db_tx_gain_1p1);
 545         else if (AR_SREV_9340(ah))
 546                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 547                         ar9340Modes_high_ob_db_tx_gain_table_1p0);
 548         else if (AR_SREV_9485_11_OR_LATER(ah))
 549                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 550                         ar9485Modes_high_ob_db_tx_gain_1_1);
 551         else if (AR_SREV_9580(ah))
 552                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 553                         ar9580_1p0_high_ob_db_tx_gain_table);
 554         else if (AR_SREV_9550(ah))
 555                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 556                         ar955x_1p0_modes_no_xpa_tx_gain_table);
 557         else if (AR_SREV_9531(ah)) {
 558                 if (AR_SREV_9531_11(ah))
 559                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 560                                        qca953x_1p1_modes_no_xpa_tx_gain_table);
 561                 else
 562                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 563                                        qca953x_1p0_modes_no_xpa_tx_gain_table);
 564         } else if (AR_SREV_9462_21(ah))
 565                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 566                         ar9462_2p1_modes_high_ob_db_tx_gain);
 567         else if (AR_SREV_9462_20(ah))
 568                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 569                         ar9462_2p0_modes_high_ob_db_tx_gain);
 570         else if (AR_SREV_9565_11(ah))
 571                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 572                                ar9565_1p1_modes_high_ob_db_tx_gain_table);
 573         else if (AR_SREV_9565(ah))
 574                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 575                                ar9565_1p0_modes_high_ob_db_tx_gain_table);
 576         else
 577                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 578                         ar9300Modes_high_ob_db_tx_gain_table_2p2);
 579 }
 580
 581 static void ar9003_tx_gain_table_mode2(struct ath_hw *ah)
 582 {
 583         if (AR_SREV_9330_12(ah))
 584                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 585                         ar9331_modes_low_ob_db_tx_gain_1p2);
 586         else if (AR_SREV_9330_11(ah))
 587                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 588                         ar9331_modes_low_ob_db_tx_gain_1p1);
 589         else if (AR_SREV_9340(ah))
 590                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 591                         ar9340Modes_low_ob_db_tx_gain_table_1p0);
 592         else if (AR_SREV_9485_11_OR_LATER(ah))
 593                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 594                         ar9485Modes_low_ob_db_tx_gain_1_1);
 595         else if (AR_SREV_9580(ah))
 596                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 597                         ar9580_1p0_low_ob_db_tx_gain_table);
 598         else if (AR_SREV_9565_11(ah))
 599                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 600                                ar9565_1p1_modes_low_ob_db_tx_gain_table);
 601         else if (AR_SREV_9565(ah))
 602                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 603                                ar9565_1p0_modes_low_ob_db_tx_gain_table);
 604         else
 605                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 606                         ar9300Modes_low_ob_db_tx_gain_table_2p2);
 607 }
 608
 609 static void ar9003_tx_gain_table_mode3(struct ath_hw *ah)
 610 {
 611         if (AR_SREV_9330_12(ah))
 612                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 613                         ar9331_modes_high_power_tx_gain_1p2);
 614         else if (AR_SREV_9330_11(ah))
 615                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 616                         ar9331_modes_high_power_tx_gain_1p1);
 617         else if (AR_SREV_9340(ah))
 618                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 619                         ar9340Modes_high_power_tx_gain_table_1p0);
 620         else if (AR_SREV_9485_11_OR_LATER(ah))
 621                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 622                         ar9485Modes_high_power_tx_gain_1_1);
 623         else if (AR_SREV_9580(ah))
 624                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 625                         ar9580_1p0_high_power_tx_gain_table);
 626         else if (AR_SREV_9565_11(ah))
 627                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 628                                ar9565_1p1_modes_high_power_tx_gain_table);
 629         else if (AR_SREV_9565(ah))
 630                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 631                                ar9565_1p0_modes_high_power_tx_gain_table);
 632         else {
 633                 if (ah->config.tx_gain_buffalo)
 634                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 635                                        ar9300Modes_high_power_tx_gain_table_buffalo);
 636                 else
 637                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 638                                        ar9300Modes_high_power_tx_gain_table_2p2);
 639         }
 640 }
 641
 642 static void ar9003_tx_gain_table_mode4(struct ath_hw *ah)
 643 {
 644         if (AR_SREV_9340(ah))
 645                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 646                         ar9340Modes_mixed_ob_db_tx_gain_table_1p0);
 647         else if (AR_SREV_9580(ah))
 648                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 649                         ar9580_1p0_mixed_ob_db_tx_gain_table);
 650         else if (AR_SREV_9462_21(ah))
 651                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 652                        ar9462_2p1_modes_mix_ob_db_tx_gain);
 653         else if (AR_SREV_9462_20(ah))
 654                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 655                        ar9462_2p0_modes_mix_ob_db_tx_gain);
 656         else
 657                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 658                         ar9300Modes_mixed_ob_db_tx_gain_table_2p2);
 659 }
 660
 661 static void ar9003_tx_gain_table_mode5(struct ath_hw *ah)
 662 {
 663         if (AR_SREV_9485_11_OR_LATER(ah))
 664                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 665                         ar9485Modes_green_ob_db_tx_gain_1_1);
 666         else if (AR_SREV_9340(ah))
 667                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 668                         ar9340Modes_ub124_tx_gain_table_1p0);
 669         else if (AR_SREV_9580(ah))
 670                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 671                         ar9580_1p0_type5_tx_gain_table);
 672         else if (AR_SREV_9300_22(ah))
 673                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 674                         ar9300Modes_type5_tx_gain_table_2p2);
 675 }
 676
 677 static void ar9003_tx_gain_table_mode6(struct ath_hw *ah)
 678 {
 679         if (AR_SREV_9340(ah))
 680                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 681                         ar9340Modes_low_ob_db_and_spur_tx_gain_table_1p0);
 682         else if (AR_SREV_9485_11_OR_LATER(ah))
 683                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 684                         ar9485Modes_green_spur_ob_db_tx_gain_1_1);
 685         else if (AR_SREV_9580(ah))
 686                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 687                         ar9580_1p0_type6_tx_gain_table);
 688 }
 689
 690 static void ar9003_tx_gain_table_mode7(struct ath_hw *ah)
 691 {
 692         if (AR_SREV_9340(ah))
 693                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 694                                ar9340_cus227_tx_gain_table_1p0);
 695 }
 696
 697 typedef void (*ath_txgain_tab)(struct ath_hw *ah);
 698
 699 static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
 700 {
 701         static const ath_txgain_tab modes[] = {
 702                 ar9003_tx_gain_table_mode0,
 703                 ar9003_tx_gain_table_mode1,
 704                 ar9003_tx_gain_table_mode2,
 705                 ar9003_tx_gain_table_mode3,
 706                 ar9003_tx_gain_table_mode4,
 707                 ar9003_tx_gain_table_mode5,
 708                 ar9003_tx_gain_table_mode6,
 709                 ar9003_tx_gain_table_mode7,
 710         };
 711         int idx = ar9003_hw_get_tx_gain_idx(ah);
 712
 713         if (idx >= ARRAY_SIZE(modes))
 714                 idx = 0;
 715
 716         modes[idx](ah);
 717 }
 718
 719 static void ar9003_rx_gain_table_mode0(struct ath_hw *ah)
 720 {
 721         if (AR_SREV_9330_12(ah))
 722                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 723                                 ar9331_common_rx_gain_1p2);
 724         else if (AR_SREV_9330_11(ah))
 725                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 726                                 ar9331_common_rx_gain_1p1);
 727         else if (AR_SREV_9340(ah))
 728                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 729                                 ar9340Common_rx_gain_table_1p0);
 730         else if (AR_SREV_9485_11_OR_LATER(ah))
 731                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 732                                ar9485_common_rx_gain_1_1);
 733         else if (AR_SREV_9550(ah)) {
 734                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 735                                 ar955x_1p0_common_rx_gain_table);
 736                 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
 737                                 ar955x_1p0_common_rx_gain_bounds);
 738         } else if (AR_SREV_9531(ah)) {
 739                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 740                                qca953x_1p0_common_rx_gain_table);
 741                 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
 742                                qca953x_1p0_common_rx_gain_bounds);
 743         } else if (AR_SREV_9580(ah))
 744                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 745                                 ar9580_1p0_rx_gain_table);
 746         else if (AR_SREV_9462_21(ah))
 747                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 748                                 ar9462_2p1_common_rx_gain);
 749         else if (AR_SREV_9462_20(ah))
 750                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 751                                 ar9462_2p0_common_rx_gain);
 752         else if (AR_SREV_9565_11(ah))
 753                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 754                                ar9565_1p1_Common_rx_gain_table);
 755         else if (AR_SREV_9565(ah))
 756                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 757                                ar9565_1p0_Common_rx_gain_table);
 758         else
 759                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 760                                 ar9300Common_rx_gain_table_2p2);
 761 }
 762
 763 static void ar9003_rx_gain_table_mode1(struct ath_hw *ah)
 764 {
 765         if (AR_SREV_9330_12(ah))
 766                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 767                         ar9331_common_wo_xlna_rx_gain_1p2);
 768         else if (AR_SREV_9330_11(ah))
 769                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 770                         ar9331_common_wo_xlna_rx_gain_1p1);
 771         else if (AR_SREV_9340(ah))
 772                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 773                         ar9340Common_wo_xlna_rx_gain_table_1p0);
 774         else if (AR_SREV_9485_11_OR_LATER(ah))
 775                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 776                         ar9485Common_wo_xlna_rx_gain_1_1);
 777         else if (AR_SREV_9462_21(ah))
 778                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 779                         ar9462_2p1_common_wo_xlna_rx_gain);
 780         else if (AR_SREV_9462_20(ah))
 781                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 782                         ar9462_2p0_common_wo_xlna_rx_gain);
 783         else if (AR_SREV_9550(ah)) {
 784                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 785                         ar955x_1p0_common_wo_xlna_rx_gain_table);
 786                 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
 787                         ar955x_1p0_common_wo_xlna_rx_gain_bounds);
 788         } else if (AR_SREV_9531(ah)) {
 789                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 790                                qca953x_1p0_common_wo_xlna_rx_gain_table);
 791                 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
 792                                qca953x_1p0_common_wo_xlna_rx_gain_bounds);
 793         } else if (AR_SREV_9580(ah))
 794                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 795                         ar9580_1p0_wo_xlna_rx_gain_table);
 796         else if (AR_SREV_9565_11(ah))
 797                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 798                                ar9565_1p1_common_wo_xlna_rx_gain_table);
 799         else if (AR_SREV_9565(ah))
 800                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 801                                ar9565_1p0_common_wo_xlna_rx_gain_table);
 802         else
 803                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 804                         ar9300Common_wo_xlna_rx_gain_table_2p2);
 805 }
 806
 807 static void ar9003_rx_gain_table_mode2(struct ath_hw *ah)
 808 {
 809         if (AR_SREV_9462_21(ah)) {
 810                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 811                                ar9462_2p1_common_mixed_rx_gain);
 812                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_core,
 813                                ar9462_2p1_baseband_core_mix_rxgain);
 814                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
 815                                ar9462_2p1_baseband_postamble_mix_rxgain);
 816                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna,
 817                                ar9462_2p1_baseband_postamble_5g_xlna);
 818         } else if (AR_SREV_9462_20(ah)) {
 819                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 820                                ar9462_2p0_common_mixed_rx_gain);
 821                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_core,
 822                                ar9462_2p0_baseband_core_mix_rxgain);
 823                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
 824                                ar9462_2p0_baseband_postamble_mix_rxgain);
 825                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna,
 826                                ar9462_2p0_baseband_postamble_5g_xlna);
 827         }
 828 }
 829
 830 static void ar9003_rx_gain_table_mode3(struct ath_hw *ah)
 831 {
 832         if (AR_SREV_9462_21(ah)) {
 833                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 834                                ar9462_2p1_common_5g_xlna_only_rxgain);
 835                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna,
 836                                ar9462_2p1_baseband_postamble_5g_xlna);
 837         } else if (AR_SREV_9462_20(ah)) {
 838                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 839                                ar9462_2p0_common_5g_xlna_only_rxgain);
 840                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna,
 841                                ar9462_2p0_baseband_postamble_5g_xlna);
 842         }
 843 }
 844
 845 static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
 846 {
 847         switch (ar9003_hw_get_rx_gain_idx(ah)) {
 848         case 0:
 849         default:
 850                 ar9003_rx_gain_table_mode0(ah);
 851                 break;
 852         case 1:
 853                 ar9003_rx_gain_table_mode1(ah);
 854                 break;
 855         case 2:
 856                 ar9003_rx_gain_table_mode2(ah);
 857                 break;
 858         case 3:
 859                 ar9003_rx_gain_table_mode3(ah);
 860                 break;
 861         }
 862 }
 863
 864 /* set gain table pointers according to values read from the eeprom */
 865 static void ar9003_hw_init_mode_gain_regs(struct ath_hw *ah)
 866 {
 867         ar9003_tx_gain_table_apply(ah);
 868         ar9003_rx_gain_table_apply(ah);
 869 }
 870
 871 /*
 872  * Helper for ASPM support.
 873  *
 874  * Disable PLL when in L0s as well as receiver clock when in L1.
 875  * This power saving option must be enabled through the SerDes.
 876  *
 877  * Programming the SerDes must go through the same 288 bit serial shift
 878  * register as the other analog registers.  Hence the 9 writes.
 879  */
 880 static void ar9003_hw_configpcipowersave(struct ath_hw *ah,
 881                                          bool power_off)
 882 {
 883         unsigned int i;
 884         struct ar5416IniArray *array;
 885
 886         /*
 887          * Increase L1 Entry Latency. Some WB222 boards don't have
 888          * this change in eeprom/OTP.
 889          *
 890          */
 891         if (AR_SREV_9462(ah)) {
 892                 u32 val = ah->config.aspm_l1_fix;
 893                 if ((val & 0xff000000) == 0x17000000) {
 894                         val &= 0x00ffffff;
 895                         val |= 0x27000000;
 896                         REG_WRITE(ah, 0x570c, val);
 897                 }
 898         }
 899
 900         /* Nothing to do on restore for 11N */
 901         if (!power_off /* !restore */) {
 902                 /* set bit 19 to allow forcing of pcie core into L1 state */
 903                 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
 904                 REG_WRITE(ah, AR_WA, ah->WARegVal);
 905         }
 906
 907         /*
 908          * Configire PCIE after Ini init. SERDES values now come from ini file
 909          * This enables PCIe low power mode.
 910          */
 911         array = power_off ? &ah->iniPcieSerdes :
 912                 &ah->iniPcieSerdesLowPower;
 913
 914         for (i = 0; i < array->ia_rows; i++) {
 915                 REG_WRITE(ah,
 916                           INI_RA(array, i, 0),
 917                           INI_RA(array, i, 1));
 918         }
 919 }
 920
 921 static void ar9003_hw_init_hang_checks(struct ath_hw *ah)
 922 {
 923         /*
 924          * All chips support detection of BB/MAC hangs.
 925          */
 926         ah->config.hw_hang_checks |= HW_BB_WATCHDOG;
 927         ah->config.hw_hang_checks |= HW_MAC_HANG;
 928
 929         /*
 930          * This is not required for AR9580 1.0
 931          */
 932         if (AR_SREV_9300_22(ah))
 933                 ah->config.hw_hang_checks |= HW_PHYRESTART_CLC_WAR;
 934
 935         if (AR_SREV_9330(ah))
 936                 ah->bb_watchdog_timeout_ms = 85;
 937         else
 938                 ah->bb_watchdog_timeout_ms = 25;
 939 }
 940
 941 /*
 942  * MAC HW hang check
 943  * =================
 944  *
 945  * Signature: dcu_chain_state is 0x6 and dcu_complete_state is 0x1.
 946  *
 947  * The state of each DCU chain (mapped to TX queues) is available from these
 948  * DMA debug registers:
 949  *
 950  * Chain 0 state : Bits 4:0   of AR_DMADBG_4
 951  * Chain 1 state : Bits 9:5   of AR_DMADBG_4
 952  * Chain 2 state : Bits 14:10 of AR_DMADBG_4
 953  * Chain 3 state : Bits 19:15 of AR_DMADBG_4
 954  * Chain 4 state : Bits 24:20 of AR_DMADBG_4
 955  * Chain 5 state : Bits 29:25 of AR_DMADBG_4
 956  * Chain 6 state : Bits 4:0   of AR_DMADBG_5
 957  * Chain 7 state : Bits 9:5   of AR_DMADBG_5
 958  * Chain 8 state : Bits 14:10 of AR_DMADBG_5
 959  * Chain 9 state : Bits 19:15 of AR_DMADBG_5
 960  *
 961  * The DCU chain state "0x6" means "WAIT_FRDONE" - wait for TX frame to be done.
 962  */
 963
 964 #define NUM_STATUS_READS 50
 965
 966 static bool ath9k_hw_verify_hang(struct ath_hw *ah, unsigned int queue)
 967 {
 968         u32 dma_dbg_chain, dma_dbg_complete;
 969         u8 dcu_chain_state, dcu_complete_state;
 970         int i;
 971
 972         for (i = 0; i < NUM_STATUS_READS; i++) {
 973                 if (queue < 6)
 974                         dma_dbg_chain = REG_READ(ah, AR_DMADBG_4);
 975                 else
 976                         dma_dbg_chain = REG_READ(ah, AR_DMADBG_5);
 977
 978                 dma_dbg_complete = REG_READ(ah, AR_DMADBG_6);
 979
 980                 dcu_chain_state = (dma_dbg_chain >> (5 * queue)) & 0x1f;
 981                 dcu_complete_state = dma_dbg_complete & 0x3;
 982
 983                 if ((dcu_chain_state != 0x6) || (dcu_complete_state != 0x1))
 984                         return false;
 985         }
 986
 987         ath_dbg(ath9k_hw_common(ah), RESET,
 988                 "MAC Hang signature found for queue: %d\n", queue);
 989
 990         return true;
 991 }
 992
 993 static bool ar9003_hw_detect_mac_hang(struct ath_hw *ah)
 994 {
 995         u32 dma_dbg_4, dma_dbg_5, dma_dbg_6, chk_dbg;
 996         u8 dcu_chain_state, dcu_complete_state;
 997         bool dcu_wait_frdone = false;
 998         unsigned long chk_dcu = 0;
 999         unsigned int i = 0;
1000
1001         dma_dbg_4 = REG_READ(ah, AR_DMADBG_4);
1002         dma_dbg_5 = REG_READ(ah, AR_DMADBG_5);
1003         dma_dbg_6 = REG_READ(ah, AR_DMADBG_6);
1004
1005         dcu_complete_state = dma_dbg_6 & 0x3;
1006         if (dcu_complete_state != 0x1)
1007                 goto exit;
1008
1009         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1010                 if (i < 6)
1011                         chk_dbg = dma_dbg_4;
1012                 else
1013                         chk_dbg = dma_dbg_5;
1014
1015                 dcu_chain_state = (chk_dbg >> (5 * i)) & 0x1f;
1016                 if (dcu_chain_state == 0x6) {
1017                         dcu_wait_frdone = true;
1018                         chk_dcu |= BIT(i);
1019                 }
1020         }
1021
1022         if ((dcu_complete_state == 0x1) && dcu_wait_frdone) {
1023                 for_each_set_bit(i, &chk_dcu, ATH9K_NUM_TX_QUEUES) {
1024                         if (ath9k_hw_verify_hang(ah, i))
1025                                 return true;
1026                 }
1027         }
1028 exit:
1029         return false;
1030 }
1031
1032 /* Sets up the AR9003 hardware familiy callbacks */
1033 void ar9003_hw_attach_ops(struct ath_hw *ah)
1034 {
1035         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1036         struct ath_hw_ops *ops = ath9k_hw_ops(ah);
1037
1038         ar9003_hw_init_mode_regs(ah);
1039         priv_ops->init_mode_gain_regs = ar9003_hw_init_mode_gain_regs;
1040         priv_ops->init_hang_checks = ar9003_hw_init_hang_checks;
1041         priv_ops->detect_mac_hang = ar9003_hw_detect_mac_hang;
1042
1043         ops->config_pci_powersave = ar9003_hw_configpcipowersave;
1044
1045         ar9003_hw_attach_phy_ops(ah);
1046         ar9003_hw_attach_calib_ops(ah);
1047         ar9003_hw_attach_mac_ops(ah);
1048 }