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[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / ar9003_phy.c
1 /*
2 * Copyright (c) 2010-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/export.h>
18 #include "hw.h"
19 #include "ar9003_phy.h"
20
21 static const int firstep_table[] =
22 /* level: 0 1 2 3 4 5 6 7 8 */
23 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */
24
25 static const int cycpwrThr1_table[] =
26 /* level: 0 1 2 3 4 5 6 7 8 */
27 { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */
28
29 /*
30 * register values to turn OFDM weak signal detection OFF
31 */
32 static const int m1ThreshLow_off = 127;
33 static const int m2ThreshLow_off = 127;
34 static const int m1Thresh_off = 127;
35 static const int m2Thresh_off = 127;
36 static const int m2CountThr_off = 31;
37 static const int m2CountThrLow_off = 63;
38 static const int m1ThreshLowExt_off = 127;
39 static const int m2ThreshLowExt_off = 127;
40 static const int m1ThreshExt_off = 127;
41 static const int m2ThreshExt_off = 127;
42
43 /**
44 * ar9003_hw_set_channel - set channel on single-chip device
45 * @ah: atheros hardware structure
46 * @chan:
47 *
48 * This is the function to change channel on single-chip devices, that is
49 * for AR9300 family of chipsets.
50 *
51 * This function takes the channel value in MHz and sets
52 * hardware channel value. Assumes writes have been enabled to analog bus.
53 *
54 * Actual Expression,
55 *
56 * For 2GHz channel,
57 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
58 * (freq_ref = 40MHz)
59 *
60 * For 5GHz channel,
61 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
62 * (freq_ref = 40MHz/(24>>amodeRefSel))
63 *
64 * For 5GHz channels which are 5MHz spaced,
65 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
66 * (freq_ref = 40MHz)
67 */
68 static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
69 {
70 u16 bMode, fracMode = 0, aModeRefSel = 0;
71 u32 freq, chan_frac, div, channelSel = 0, reg32 = 0;
72 struct chan_centers centers;
73 int loadSynthChannel;
74
75 ath9k_hw_get_channel_centers(ah, chan, &centers);
76 freq = centers.synth_center;
77
78 if (freq < 4800) { /* 2 GHz, fractional mode */
79 if (AR_SREV_9330(ah)) {
80 if (ah->is_clk_25mhz)
81 div = 75;
82 else
83 div = 120;
84
85 channelSel = (freq * 4) / div;
86 chan_frac = (((freq * 4) % div) * 0x20000) / div;
87 channelSel = (channelSel << 17) | chan_frac;
88 } else if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
89 /*
90 * freq_ref = 40 / (refdiva >> amoderefsel);
91 * where refdiva=1 and amoderefsel=0
92 * ndiv = ((chan_mhz * 4) / 3) / freq_ref;
93 * chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000
94 */
95 channelSel = (freq * 4) / 120;
96 chan_frac = (((freq * 4) % 120) * 0x20000) / 120;
97 channelSel = (channelSel << 17) | chan_frac;
98 } else if (AR_SREV_9340(ah)) {
99 if (ah->is_clk_25mhz) {
100 channelSel = (freq * 2) / 75;
101 chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
102 channelSel = (channelSel << 17) | chan_frac;
103 } else {
104 channelSel = CHANSEL_2G(freq) >> 1;
105 }
106 } else if (AR_SREV_9550(ah) || AR_SREV_9531(ah)) {
107 if (ah->is_clk_25mhz)
108 div = 75;
109 else
110 div = 120;
111
112 channelSel = (freq * 4) / div;
113 chan_frac = (((freq * 4) % div) * 0x20000) / div;
114 channelSel = (channelSel << 17) | chan_frac;
115 } else {
116 channelSel = CHANSEL_2G(freq);
117 }
118 /* Set to 2G mode */
119 bMode = 1;
120 } else {
121 if ((AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah)) &&
122 ah->is_clk_25mhz) {
123 channelSel = freq / 75;
124 chan_frac = ((freq % 75) * 0x20000) / 75;
125 channelSel = (channelSel << 17) | chan_frac;
126 } else {
127 channelSel = CHANSEL_5G(freq);
128 /* Doubler is ON, so, divide channelSel by 2. */
129 channelSel >>= 1;
130 }
131 /* Set to 5G mode */
132 bMode = 0;
133 }
134
135 /* Enable fractional mode for all channels */
136 fracMode = 1;
137 aModeRefSel = 0;
138 loadSynthChannel = 0;
139
140 reg32 = (bMode << 29);
141 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
142
143 /* Enable Long shift Select for Synthesizer */
144 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4,
145 AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1);
146
147 /* Program Synth. setting */
148 reg32 = (channelSel << 2) | (fracMode << 30) |
149 (aModeRefSel << 28) | (loadSynthChannel << 31);
150 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
151
152 /* Toggle Load Synth channel bit */
153 loadSynthChannel = 1;
154 reg32 = (channelSel << 2) | (fracMode << 30) |
155 (aModeRefSel << 28) | (loadSynthChannel << 31);
156 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
157
158 ah->curchan = chan;
159
160 return 0;
161 }
162
163 /**
164 * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency
165 * @ah: atheros hardware structure
166 * @chan:
167 *
168 * For single-chip solutions. Converts to baseband spur frequency given the
169 * input channel frequency and compute register settings below.
170 *
171 * Spur mitigation for MRC CCK
172 */
173 static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
174 struct ath9k_channel *chan)
175 {
176 static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
177 int cur_bb_spur, negative = 0, cck_spur_freq;
178 int i;
179 int range, max_spur_cnts, synth_freq;
180 u8 *spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah, IS_CHAN_2GHZ(chan));
181
182 /*
183 * Need to verify range +/- 10 MHz in control channel, otherwise spur
184 * is out-of-band and can be ignored.
185 */
186
187 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
188 AR_SREV_9550(ah)) {
189 if (spur_fbin_ptr[0] == 0) /* No spur */
190 return;
191 max_spur_cnts = 5;
192 if (IS_CHAN_HT40(chan)) {
193 range = 19;
194 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
195 AR_PHY_GC_DYN2040_PRI_CH) == 0)
196 synth_freq = chan->channel + 10;
197 else
198 synth_freq = chan->channel - 10;
199 } else {
200 range = 10;
201 synth_freq = chan->channel;
202 }
203 } else {
204 range = AR_SREV_9462(ah) ? 5 : 10;
205 max_spur_cnts = 4;
206 synth_freq = chan->channel;
207 }
208
209 for (i = 0; i < max_spur_cnts; i++) {
210 if (AR_SREV_9462(ah) && (i == 0 || i == 3))
211 continue;
212
213 negative = 0;
214 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
215 AR_SREV_9550(ah))
216 cur_bb_spur = ath9k_hw_fbin2freq(spur_fbin_ptr[i],
217 IS_CHAN_2GHZ(chan));
218 else
219 cur_bb_spur = spur_freq[i];
220
221 cur_bb_spur -= synth_freq;
222 if (cur_bb_spur < 0) {
223 negative = 1;
224 cur_bb_spur = -cur_bb_spur;
225 }
226 if (cur_bb_spur < range) {
227 cck_spur_freq = (int)((cur_bb_spur << 19) / 11);
228
229 if (negative == 1)
230 cck_spur_freq = -cck_spur_freq;
231
232 cck_spur_freq = cck_spur_freq & 0xfffff;
233
234 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
235 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);
236 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
237 AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);
238 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
239 AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE,
240 0x2);
241 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
242 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT,
243 0x1);
244 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
245 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ,
246 cck_spur_freq);
247
248 return;
249 }
250 }
251
252 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
253 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);
254 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
255 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0);
256 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
257 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0);
258 }
259
260 /* Clean all spur register fields */
261 static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah)
262 {
263 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
264 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0);
265 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
266 AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
267 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
268 AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
269 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
270 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0);
271 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
272 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0);
273 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
274 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0);
275 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
276 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0);
277 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
278 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0);
279 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
280 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0);
281
282 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
283 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0);
284 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
285 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0);
286 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
287 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0);
288 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
289 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0);
290 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
291 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0);
292 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
293 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0);
294 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
295 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0);
296 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
297 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0);
298 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
299 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0);
300 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
301 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
302 }
303
304 static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
305 int freq_offset,
306 int spur_freq_sd,
307 int spur_delta_phase,
308 int spur_subchannel_sd,
309 int range,
310 int synth_freq)
311 {
312 int mask_index = 0;
313
314 /* OFDM Spur mitigation */
315 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
316 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1);
317 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
318 AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
319 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
320 AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
321 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
322 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd);
323 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
324 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1);
325
326 if (!(AR_SREV_9565(ah) && range == 10 && synth_freq == 2437))
327 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
328 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1);
329
330 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
331 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1);
332 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
333 AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
334 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
335 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1);
336
337 if (!AR_SREV_9340(ah) &&
338 REG_READ_FIELD(ah, AR_PHY_MODE,
339 AR_PHY_MODE_DYNAMIC) == 0x1)
340 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
341 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1);
342
343 mask_index = (freq_offset << 4) / 5;
344 if (mask_index < 0)
345 mask_index = mask_index - 1;
346
347 mask_index = mask_index & 0x7f;
348
349 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
350 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1);
351 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
352 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1);
353 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
354 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1);
355 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
356 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index);
357 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
358 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index);
359 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
360 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index);
361 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
362 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc);
363 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
364 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc);
365 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
366 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
367 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
368 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
369 }
370
371 static void ar9003_hw_spur_ofdm_9565(struct ath_hw *ah,
372 int freq_offset)
373 {
374 int mask_index = 0;
375
376 mask_index = (freq_offset << 4) / 5;
377 if (mask_index < 0)
378 mask_index = mask_index - 1;
379
380 mask_index = mask_index & 0x7f;
381
382 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
383 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B,
384 mask_index);
385
386 /* A == B */
387 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B,
388 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A,
389 mask_index);
390
391 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
392 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B,
393 mask_index);
394 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
395 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_B, 0xe);
396 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
397 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_B, 0xe);
398
399 /* A == B */
400 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B,
401 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
402 }
403
404 static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah,
405 struct ath9k_channel *chan,
406 int freq_offset,
407 int range,
408 int synth_freq)
409 {
410 int spur_freq_sd = 0;
411 int spur_subchannel_sd = 0;
412 int spur_delta_phase = 0;
413
414 if (IS_CHAN_HT40(chan)) {
415 if (freq_offset < 0) {
416 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
417 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
418 spur_subchannel_sd = 1;
419 else
420 spur_subchannel_sd = 0;
421
422 spur_freq_sd = ((freq_offset + 10) << 9) / 11;
423
424 } else {
425 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
426 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
427 spur_subchannel_sd = 0;
428 else
429 spur_subchannel_sd = 1;
430
431 spur_freq_sd = ((freq_offset - 10) << 9) / 11;
432
433 }
434
435 spur_delta_phase = (freq_offset << 17) / 5;
436
437 } else {
438 spur_subchannel_sd = 0;
439 spur_freq_sd = (freq_offset << 9) /11;
440 spur_delta_phase = (freq_offset << 18) / 5;
441 }
442
443 spur_freq_sd = spur_freq_sd & 0x3ff;
444 spur_delta_phase = spur_delta_phase & 0xfffff;
445
446 ar9003_hw_spur_ofdm(ah,
447 freq_offset,
448 spur_freq_sd,
449 spur_delta_phase,
450 spur_subchannel_sd,
451 range, synth_freq);
452 }
453
454 /* Spur mitigation for OFDM */
455 static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah,
456 struct ath9k_channel *chan)
457 {
458 int synth_freq;
459 int range = 10;
460 int freq_offset = 0;
461 int mode;
462 u8* spurChansPtr;
463 unsigned int i;
464 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
465
466 if (IS_CHAN_5GHZ(chan)) {
467 spurChansPtr = &(eep->modalHeader5G.spurChans[0]);
468 mode = 0;
469 }
470 else {
471 spurChansPtr = &(eep->modalHeader2G.spurChans[0]);
472 mode = 1;
473 }
474
475 if (spurChansPtr[0] == 0)
476 return; /* No spur in the mode */
477
478 if (IS_CHAN_HT40(chan)) {
479 range = 19;
480 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
481 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
482 synth_freq = chan->channel - 10;
483 else
484 synth_freq = chan->channel + 10;
485 } else {
486 range = 10;
487 synth_freq = chan->channel;
488 }
489
490 ar9003_hw_spur_ofdm_clear(ah);
491
492 for (i = 0; i < AR_EEPROM_MODAL_SPURS && spurChansPtr[i]; i++) {
493 freq_offset = ath9k_hw_fbin2freq(spurChansPtr[i], mode);
494 freq_offset -= synth_freq;
495 if (abs(freq_offset) < range) {
496 ar9003_hw_spur_ofdm_work(ah, chan, freq_offset,
497 range, synth_freq);
498
499 if (AR_SREV_9565(ah) && (i < 4)) {
500 freq_offset = ath9k_hw_fbin2freq(spurChansPtr[i + 1],
501 mode);
502 freq_offset -= synth_freq;
503 if (abs(freq_offset) < range)
504 ar9003_hw_spur_ofdm_9565(ah, freq_offset);
505 }
506
507 break;
508 }
509 }
510 }
511
512 static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
513 struct ath9k_channel *chan)
514 {
515 if (!AR_SREV_9565(ah))
516 ar9003_hw_spur_mitigate_mrc_cck(ah, chan);
517 ar9003_hw_spur_mitigate_ofdm(ah, chan);
518 }
519
520 static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
521 struct ath9k_channel *chan)
522 {
523 u32 pll;
524
525 pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
526
527 if (chan && IS_CHAN_HALF_RATE(chan))
528 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
529 else if (chan && IS_CHAN_QUARTER_RATE(chan))
530 pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
531
532 pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
533
534 return pll;
535 }
536
537 static void ar9003_hw_set_channel_regs(struct ath_hw *ah,
538 struct ath9k_channel *chan)
539 {
540 u32 phymode;
541 u32 enableDacFifo = 0;
542
543 enableDacFifo =
544 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO);
545
546 /* Enable 11n HT, 20 MHz */
547 phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SINGLE_HT_LTF1 |
548 AR_PHY_GC_SHORT_GI_40 | enableDacFifo;
549
550 /* Configure baseband for dynamic 20/40 operation */
551 if (IS_CHAN_HT40(chan)) {
552 phymode |= AR_PHY_GC_DYN2040_EN;
553 /* Configure control (primary) channel at +-10MHz */
554 if (IS_CHAN_HT40PLUS(chan))
555 phymode |= AR_PHY_GC_DYN2040_PRI_CH;
556
557 }
558
559 /* make sure we preserve INI settings */
560 phymode |= REG_READ(ah, AR_PHY_GEN_CTRL);
561 /* turn off Green Field detection for STA for now */
562 phymode &= ~AR_PHY_GC_GF_DETECT_EN;
563
564 REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);
565
566 /* Configure MAC for 20/40 operation */
567 ath9k_hw_set11nmac2040(ah, chan);
568
569 /* global transmit timeout (25 TUs default)*/
570 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
571 /* carrier sense timeout */
572 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
573 }
574
575 static void ar9003_hw_init_bb(struct ath_hw *ah,
576 struct ath9k_channel *chan)
577 {
578 u32 synthDelay;
579
580 /*
581 * Wait for the frequency synth to settle (synth goes on
582 * via AR_PHY_ACTIVE_EN). Read the phy active delay register.
583 * Value is in 100ns increments.
584 */
585 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
586
587 /* Activate the PHY (includes baseband activate + synthesizer on) */
588 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
589 ath9k_hw_synth_delay(ah, chan, synthDelay);
590 }
591
592 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
593 {
594 if (ah->caps.tx_chainmask == 5 || ah->caps.rx_chainmask == 5)
595 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
596 AR_PHY_SWAP_ALT_CHAIN);
597
598 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);
599 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);
600
601 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7))
602 tx = 3;
603
604 REG_WRITE(ah, AR_SELFGEN_MASK, tx);
605 }
606
607 /*
608 * Override INI values with chip specific configuration.
609 */
610 static void ar9003_hw_override_ini(struct ath_hw *ah)
611 {
612 u32 val;
613
614 /*
615 * Set the RX_ABORT and RX_DIS and clear it only after
616 * RXE is set for MAC. This prevents frames with
617 * corrupted descriptor status.
618 */
619 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
620
621 /*
622 * For AR9280 and above, there is a new feature that allows
623 * Multicast search based on both MAC Address and Key ID. By default,
624 * this feature is enabled. But since the driver is not using this
625 * feature, we switch it off; otherwise multicast search based on
626 * MAC addr only will fail.
627 */
628 val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE);
629 val |= AR_AGG_WEP_ENABLE_FIX |
630 AR_AGG_WEP_ENABLE |
631 AR_PCU_MISC_MODE2_CFP_IGNORE;
632 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
633
634 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
635 REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE,
636 AR_GLB_SWREG_DISCONT_EN_BT_WLAN);
637
638 if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0,
639 AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL))
640 ah->enabled_cals |= TX_IQ_CAL;
641 else
642 ah->enabled_cals &= ~TX_IQ_CAL;
643
644 }
645
646 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE)
647 ah->enabled_cals |= TX_CL_CAL;
648 else
649 ah->enabled_cals &= ~TX_CL_CAL;
650 }
651
652 static void ar9003_hw_prog_ini(struct ath_hw *ah,
653 struct ar5416IniArray *iniArr,
654 int column)
655 {
656 unsigned int i, regWrites = 0;
657
658 /* New INI format: Array may be undefined (pre, core, post arrays) */
659 if (!iniArr->ia_array)
660 return;
661
662 /*
663 * New INI format: Pre, core, and post arrays for a given subsystem
664 * may be modal (> 2 columns) or non-modal (2 columns). Determine if
665 * the array is non-modal and force the column to 1.
666 */
667 if (column >= iniArr->ia_columns)
668 column = 1;
669
670 for (i = 0; i < iniArr->ia_rows; i++) {
671 u32 reg = INI_RA(iniArr, i, 0);
672 u32 val = INI_RA(iniArr, i, column);
673
674 REG_WRITE(ah, reg, val);
675
676 DO_DELAY(regWrites);
677 }
678 }
679
680 static int ar9550_hw_get_modes_txgain_index(struct ath_hw *ah,
681 struct ath9k_channel *chan)
682 {
683 int ret;
684
685 if (IS_CHAN_2GHZ(chan)) {
686 if (IS_CHAN_HT40(chan))
687 return 7;
688 else
689 return 8;
690 }
691
692 if (chan->channel <= 5350)
693 ret = 1;
694 else if ((chan->channel > 5350) && (chan->channel <= 5600))
695 ret = 3;
696 else
697 ret = 5;
698
699 if (IS_CHAN_HT40(chan))
700 ret++;
701
702 return ret;
703 }
704
705 static void ar9003_doubler_fix(struct ath_hw *ah)
706 {
707 if (AR_SREV_9300(ah) || AR_SREV_9580(ah) || AR_SREV_9550(ah)) {
708 REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2,
709 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
710 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0);
711 REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2,
712 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
713 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0);
714 REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2,
715 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
716 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0);
717
718 udelay(200);
719
720 REG_CLR_BIT(ah, AR_PHY_65NM_CH0_RXTX2,
721 AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK);
722 REG_CLR_BIT(ah, AR_PHY_65NM_CH1_RXTX2,
723 AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK);
724 REG_CLR_BIT(ah, AR_PHY_65NM_CH2_RXTX2,
725 AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK);
726
727 udelay(1);
728
729 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX2,
730 AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1);
731 REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX2,
732 AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1);
733 REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX2,
734 AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1);
735
736 udelay(200);
737
738 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH12,
739 AR_PHY_65NM_CH0_SYNTH12_VREFMUL3, 0xf);
740
741 REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2, 0,
742 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
743 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S);
744 REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2, 0,
745 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
746 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S);
747 REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2, 0,
748 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
749 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S);
750 }
751 }
752
753 static int ar9003_hw_process_ini(struct ath_hw *ah,
754 struct ath9k_channel *chan)
755 {
756 unsigned int regWrites = 0, i;
757 u32 modesIndex;
758
759 if (IS_CHAN_5GHZ(chan))
760 modesIndex = IS_CHAN_HT40(chan) ? 2 : 1;
761 else
762 modesIndex = IS_CHAN_HT40(chan) ? 3 : 4;
763
764 /*
765 * SOC, MAC, BB, RADIO initvals.
766 */
767 for (i = 0; i < ATH_INI_NUM_SPLIT; i++) {
768 ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex);
769 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
770 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
771 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
772 if (i == ATH_INI_POST && AR_SREV_9462_20_OR_LATER(ah))
773 ar9003_hw_prog_ini(ah,
774 &ah->ini_radio_post_sys2ant,
775 modesIndex);
776 }
777
778 ar9003_doubler_fix(ah);
779
780 /*
781 * RXGAIN initvals.
782 */
783 REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
784
785 if (AR_SREV_9462_20_OR_LATER(ah)) {
786 /*
787 * CUS217 mix LNA mode.
788 */
789 if (ar9003_hw_get_rx_gain_idx(ah) == 2) {
790 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_core,
791 1, regWrites);
792 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
793 modesIndex, regWrites);
794 }
795
796 /*
797 * 5G-XLNA
798 */
799 if ((ar9003_hw_get_rx_gain_idx(ah) == 2) ||
800 (ar9003_hw_get_rx_gain_idx(ah) == 3)) {
801 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_5g_xlna,
802 modesIndex, regWrites);
803 }
804 }
805
806 if (AR_SREV_9550(ah))
807 REG_WRITE_ARRAY(&ah->ini_modes_rx_gain_bounds, modesIndex,
808 regWrites);
809
810 /*
811 * TXGAIN initvals.
812 */
813 if (AR_SREV_9550(ah) || AR_SREV_9531(ah)) {
814 int modes_txgain_index = 1;
815
816 if (AR_SREV_9550(ah))
817 modes_txgain_index = ar9550_hw_get_modes_txgain_index(ah, chan);
818
819 if (modes_txgain_index < 0)
820 return -EINVAL;
821
822 REG_WRITE_ARRAY(&ah->iniModesTxGain, modes_txgain_index,
823 regWrites);
824 } else {
825 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
826 }
827
828 /*
829 * For 5GHz channels requiring Fast Clock, apply
830 * different modal values.
831 */
832 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
833 REG_WRITE_ARRAY(&ah->iniModesFastClock,
834 modesIndex, regWrites);
835
836 /*
837 * Clock frequency initvals.
838 */
839 REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites);
840
841 /*
842 * JAPAN regulatory.
843 */
844 if (chan->channel == 2484)
845 ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1);
846
847 ah->modes_index = modesIndex;
848 ar9003_hw_override_ini(ah);
849 ar9003_hw_set_channel_regs(ah, chan);
850 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
851 ath9k_hw_apply_txpower(ah, chan, false);
852
853 return 0;
854 }
855
856 static void ar9003_hw_set_rfmode(struct ath_hw *ah,
857 struct ath9k_channel *chan)
858 {
859 u32 rfMode = 0;
860
861 if (chan == NULL)
862 return;
863
864 if (IS_CHAN_2GHZ(chan))
865 rfMode |= AR_PHY_MODE_DYNAMIC;
866 else
867 rfMode |= AR_PHY_MODE_OFDM;
868
869 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
870 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
871
872 if (rfMode & (AR_PHY_MODE_QUARTER | AR_PHY_MODE_HALF))
873 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,
874 AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW, 3);
875
876 REG_WRITE(ah, AR_PHY_MODE, rfMode);
877 }
878
879 static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah)
880 {
881 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
882 }
883
884 static void ar9003_hw_set_delta_slope(struct ath_hw *ah,
885 struct ath9k_channel *chan)
886 {
887 u32 coef_scaled, ds_coef_exp, ds_coef_man;
888 u32 clockMhzScaled = 0x64000000;
889 struct chan_centers centers;
890
891 /*
892 * half and quarter rate can divide the scaled clock by 2 or 4
893 * scale for selected channel bandwidth
894 */
895 if (IS_CHAN_HALF_RATE(chan))
896 clockMhzScaled = clockMhzScaled >> 1;
897 else if (IS_CHAN_QUARTER_RATE(chan))
898 clockMhzScaled = clockMhzScaled >> 2;
899
900 /*
901 * ALGO -> coef = 1e8/fcarrier*fclock/40;
902 * scaled coef to provide precision for this floating calculation
903 */
904 ath9k_hw_get_channel_centers(ah, chan, &centers);
905 coef_scaled = clockMhzScaled / centers.synth_center;
906
907 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
908 &ds_coef_exp);
909
910 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
911 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
912 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
913 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
914
915 /*
916 * For Short GI,
917 * scaled coeff is 9/10 that of normal coeff
918 */
919 coef_scaled = (9 * coef_scaled) / 10;
920
921 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
922 &ds_coef_exp);
923
924 /* for short gi */
925 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
926 AR_PHY_SGI_DSC_MAN, ds_coef_man);
927 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
928 AR_PHY_SGI_DSC_EXP, ds_coef_exp);
929 }
930
931 static bool ar9003_hw_rfbus_req(struct ath_hw *ah)
932 {
933 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
934 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
935 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
936 }
937
938 /*
939 * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN).
940 * Read the phy active delay register. Value is in 100ns increments.
941 */
942 static void ar9003_hw_rfbus_done(struct ath_hw *ah)
943 {
944 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
945
946 ath9k_hw_synth_delay(ah, ah->curchan, synthDelay);
947
948 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
949 }
950
951 static bool ar9003_hw_ani_control(struct ath_hw *ah,
952 enum ath9k_ani_cmd cmd, int param)
953 {
954 struct ath_common *common = ath9k_hw_common(ah);
955 struct ath9k_channel *chan = ah->curchan;
956 struct ar5416AniState *aniState = &ah->ani;
957 int m1ThreshLow, m2ThreshLow;
958 int m1Thresh, m2Thresh;
959 int m2CountThr, m2CountThrLow;
960 int m1ThreshLowExt, m2ThreshLowExt;
961 int m1ThreshExt, m2ThreshExt;
962 s32 value, value2;
963
964 switch (cmd & ah->ani_function) {
965 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
966 /*
967 * on == 1 means ofdm weak signal detection is ON
968 * on == 1 is the default, for less noise immunity
969 *
970 * on == 0 means ofdm weak signal detection is OFF
971 * on == 0 means more noise imm
972 */
973 u32 on = param ? 1 : 0;
974
975 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
976 goto skip_ws_det;
977
978 m1ThreshLow = on ?
979 aniState->iniDef.m1ThreshLow : m1ThreshLow_off;
980 m2ThreshLow = on ?
981 aniState->iniDef.m2ThreshLow : m2ThreshLow_off;
982 m1Thresh = on ?
983 aniState->iniDef.m1Thresh : m1Thresh_off;
984 m2Thresh = on ?
985 aniState->iniDef.m2Thresh : m2Thresh_off;
986 m2CountThr = on ?
987 aniState->iniDef.m2CountThr : m2CountThr_off;
988 m2CountThrLow = on ?
989 aniState->iniDef.m2CountThrLow : m2CountThrLow_off;
990 m1ThreshLowExt = on ?
991 aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;
992 m2ThreshLowExt = on ?
993 aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;
994 m1ThreshExt = on ?
995 aniState->iniDef.m1ThreshExt : m1ThreshExt_off;
996 m2ThreshExt = on ?
997 aniState->iniDef.m2ThreshExt : m2ThreshExt_off;
998
999 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1000 AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
1001 m1ThreshLow);
1002 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1003 AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
1004 m2ThreshLow);
1005 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1006 AR_PHY_SFCORR_M1_THRESH,
1007 m1Thresh);
1008 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1009 AR_PHY_SFCORR_M2_THRESH,
1010 m2Thresh);
1011 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1012 AR_PHY_SFCORR_M2COUNT_THR,
1013 m2CountThr);
1014 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1015 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
1016 m2CountThrLow);
1017 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1018 AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
1019 m1ThreshLowExt);
1020 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1021 AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
1022 m2ThreshLowExt);
1023 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1024 AR_PHY_SFCORR_EXT_M1_THRESH,
1025 m1ThreshExt);
1026 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1027 AR_PHY_SFCORR_EXT_M2_THRESH,
1028 m2ThreshExt);
1029 skip_ws_det:
1030 if (on)
1031 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
1032 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1033 else
1034 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
1035 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1036
1037 if (on != aniState->ofdmWeakSigDetect) {
1038 ath_dbg(common, ANI,
1039 "** ch %d: ofdm weak signal: %s=>%s\n",
1040 chan->channel,
1041 aniState->ofdmWeakSigDetect ?
1042 "on" : "off",
1043 on ? "on" : "off");
1044 if (on)
1045 ah->stats.ast_ani_ofdmon++;
1046 else
1047 ah->stats.ast_ani_ofdmoff++;
1048 aniState->ofdmWeakSigDetect = on;
1049 }
1050 break;
1051 }
1052 case ATH9K_ANI_FIRSTEP_LEVEL:{
1053 u32 level = param;
1054
1055 if (level >= ARRAY_SIZE(firstep_table)) {
1056 ath_dbg(common, ANI,
1057 "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n",
1058 level, ARRAY_SIZE(firstep_table));
1059 return false;
1060 }
1061
1062 /*
1063 * make register setting relative to default
1064 * from INI file & cap value
1065 */
1066 value = firstep_table[level] -
1067 firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
1068 aniState->iniDef.firstep;
1069 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1070 value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1071 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1072 value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
1073 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1074 AR_PHY_FIND_SIG_FIRSTEP,
1075 value);
1076 /*
1077 * we need to set first step low register too
1078 * make register setting relative to default
1079 * from INI file & cap value
1080 */
1081 value2 = firstep_table[level] -
1082 firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
1083 aniState->iniDef.firstepLow;
1084 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1085 value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1086 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1087 value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
1088
1089 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
1090 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2);
1091
1092 if (level != aniState->firstepLevel) {
1093 ath_dbg(common, ANI,
1094 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
1095 chan->channel,
1096 aniState->firstepLevel,
1097 level,
1098 ATH9K_ANI_FIRSTEP_LVL,
1099 value,
1100 aniState->iniDef.firstep);
1101 ath_dbg(common, ANI,
1102 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
1103 chan->channel,
1104 aniState->firstepLevel,
1105 level,
1106 ATH9K_ANI_FIRSTEP_LVL,
1107 value2,
1108 aniState->iniDef.firstepLow);
1109 if (level > aniState->firstepLevel)
1110 ah->stats.ast_ani_stepup++;
1111 else if (level < aniState->firstepLevel)
1112 ah->stats.ast_ani_stepdown++;
1113 aniState->firstepLevel = level;
1114 }
1115 break;
1116 }
1117 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
1118 u32 level = param;
1119
1120 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
1121 ath_dbg(common, ANI,
1122 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n",
1123 level, ARRAY_SIZE(cycpwrThr1_table));
1124 return false;
1125 }
1126 /*
1127 * make register setting relative to default
1128 * from INI file & cap value
1129 */
1130 value = cycpwrThr1_table[level] -
1131 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
1132 aniState->iniDef.cycpwrThr1;
1133 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1134 value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1135 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1136 value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1137 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
1138 AR_PHY_TIMING5_CYCPWR_THR1,
1139 value);
1140
1141 /*
1142 * set AR_PHY_EXT_CCA for extension channel
1143 * make register setting relative to default
1144 * from INI file & cap value
1145 */
1146 value2 = cycpwrThr1_table[level] -
1147 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
1148 aniState->iniDef.cycpwrThr1Ext;
1149 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1150 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1151 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1152 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1153 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
1154 AR_PHY_EXT_CYCPWR_THR1, value2);
1155
1156 if (level != aniState->spurImmunityLevel) {
1157 ath_dbg(common, ANI,
1158 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
1159 chan->channel,
1160 aniState->spurImmunityLevel,
1161 level,
1162 ATH9K_ANI_SPUR_IMMUNE_LVL,
1163 value,
1164 aniState->iniDef.cycpwrThr1);
1165 ath_dbg(common, ANI,
1166 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
1167 chan->channel,
1168 aniState->spurImmunityLevel,
1169 level,
1170 ATH9K_ANI_SPUR_IMMUNE_LVL,
1171 value2,
1172 aniState->iniDef.cycpwrThr1Ext);
1173 if (level > aniState->spurImmunityLevel)
1174 ah->stats.ast_ani_spurup++;
1175 else if (level < aniState->spurImmunityLevel)
1176 ah->stats.ast_ani_spurdown++;
1177 aniState->spurImmunityLevel = level;
1178 }
1179 break;
1180 }
1181 case ATH9K_ANI_MRC_CCK:{
1182 /*
1183 * is_on == 1 means MRC CCK ON (default, less noise imm)
1184 * is_on == 0 means MRC CCK is OFF (more noise imm)
1185 */
1186 bool is_on = param ? 1 : 0;
1187
1188 if (ah->caps.rx_chainmask == 1)
1189 break;
1190
1191 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1192 AR_PHY_MRC_CCK_ENABLE, is_on);
1193 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1194 AR_PHY_MRC_CCK_MUX_REG, is_on);
1195 if (is_on != aniState->mrcCCK) {
1196 ath_dbg(common, ANI, "** ch %d: MRC CCK: %s=>%s\n",
1197 chan->channel,
1198 aniState->mrcCCK ? "on" : "off",
1199 is_on ? "on" : "off");
1200 if (is_on)
1201 ah->stats.ast_ani_ccklow++;
1202 else
1203 ah->stats.ast_ani_cckhigh++;
1204 aniState->mrcCCK = is_on;
1205 }
1206 break;
1207 }
1208 default:
1209 ath_dbg(common, ANI, "invalid cmd %u\n", cmd);
1210 return false;
1211 }
1212
1213 ath_dbg(common, ANI,
1214 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1215 aniState->spurImmunityLevel,
1216 aniState->ofdmWeakSigDetect ? "on" : "off",
1217 aniState->firstepLevel,
1218 aniState->mrcCCK ? "on" : "off",
1219 aniState->listenTime,
1220 aniState->ofdmPhyErrCount,
1221 aniState->cckPhyErrCount);
1222 return true;
1223 }
1224
1225 static void ar9003_hw_do_getnf(struct ath_hw *ah,
1226 int16_t nfarray[NUM_NF_READINGS])
1227 {
1228 #define AR_PHY_CH_MINCCA_PWR 0x1FF00000
1229 #define AR_PHY_CH_MINCCA_PWR_S 20
1230 #define AR_PHY_CH_EXT_MINCCA_PWR 0x01FF0000
1231 #define AR_PHY_CH_EXT_MINCCA_PWR_S 16
1232
1233 int16_t nf;
1234 int i;
1235
1236 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1237 if (ah->rxchainmask & BIT(i)) {
1238 nf = MS(REG_READ(ah, ah->nf_regs[i]),
1239 AR_PHY_CH_MINCCA_PWR);
1240 nfarray[i] = sign_extend32(nf, 8);
1241
1242 if (IS_CHAN_HT40(ah->curchan)) {
1243 u8 ext_idx = AR9300_MAX_CHAINS + i;
1244
1245 nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]),
1246 AR_PHY_CH_EXT_MINCCA_PWR);
1247 nfarray[ext_idx] = sign_extend32(nf, 8);
1248 }
1249 }
1250 }
1251 }
1252
1253 static void ar9003_hw_set_nf_limits(struct ath_hw *ah)
1254 {
1255 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ;
1256 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ;
1257 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ;
1258 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ;
1259 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ;
1260 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ;
1261
1262 if (AR_SREV_9330(ah))
1263 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ;
1264
1265 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
1266 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ;
1267 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9462_2GHZ;
1268 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ;
1269 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9462_5GHZ;
1270 }
1271 }
1272
1273 /*
1274 * Initialize the ANI register values with default (ini) values.
1275 * This routine is called during a (full) hardware reset after
1276 * all the registers are initialised from the INI.
1277 */
1278 static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
1279 {
1280 struct ar5416AniState *aniState;
1281 struct ath_common *common = ath9k_hw_common(ah);
1282 struct ath9k_channel *chan = ah->curchan;
1283 struct ath9k_ani_default *iniDef;
1284 u32 val;
1285
1286 aniState = &ah->ani;
1287 iniDef = &aniState->iniDef;
1288
1289 ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz\n",
1290 ah->hw_version.macVersion,
1291 ah->hw_version.macRev,
1292 ah->opmode,
1293 chan->channel);
1294
1295 val = REG_READ(ah, AR_PHY_SFCORR);
1296 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1297 iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1298 iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
1299
1300 val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1301 iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
1302 iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
1303 iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
1304
1305 val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1306 iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
1307 iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
1308 iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
1309 iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
1310 iniDef->firstep = REG_READ_FIELD(ah,
1311 AR_PHY_FIND_SIG,
1312 AR_PHY_FIND_SIG_FIRSTEP);
1313 iniDef->firstepLow = REG_READ_FIELD(ah,
1314 AR_PHY_FIND_SIG_LOW,
1315 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW);
1316 iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1317 AR_PHY_TIMING5,
1318 AR_PHY_TIMING5_CYCPWR_THR1);
1319 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1320 AR_PHY_EXT_CCA,
1321 AR_PHY_EXT_CYCPWR_THR1);
1322
1323 /* these levels just got reset to defaults by the INI */
1324 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
1325 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
1326 aniState->ofdmWeakSigDetect = true;
1327 aniState->mrcCCK = true;
1328 }
1329
1330 static void ar9003_hw_set_radar_params(struct ath_hw *ah,
1331 struct ath_hw_radar_conf *conf)
1332 {
1333 unsigned int regWrites = 0;
1334 u32 radar_0 = 0, radar_1 = 0;
1335
1336 if (!conf) {
1337 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
1338 return;
1339 }
1340
1341 radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
1342 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
1343 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
1344 radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
1345 radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
1346 radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
1347
1348 radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
1349 radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
1350 radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
1351 radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
1352 radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
1353
1354 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
1355 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
1356 if (conf->ext_channel)
1357 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1358 else
1359 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1360
1361 if (AR_SREV_9300(ah) || AR_SREV_9340(ah) || AR_SREV_9580(ah)) {
1362 REG_WRITE_ARRAY(&ah->ini_dfs,
1363 IS_CHAN_HT40(ah->curchan) ? 2 : 1, regWrites);
1364 }
1365 }
1366
1367 static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
1368 {
1369 struct ath_hw_radar_conf *conf = &ah->radar_conf;
1370
1371 conf->fir_power = -28;
1372 conf->radar_rssi = 0;
1373 conf->pulse_height = 10;
1374 conf->pulse_rssi = 24;
1375 conf->pulse_inband = 8;
1376 conf->pulse_maxlen = 255;
1377 conf->pulse_inband_step = 12;
1378 conf->radar_inband = 8;
1379 }
1380
1381 static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah,
1382 struct ath_hw_antcomb_conf *antconf)
1383 {
1384 u32 regval;
1385
1386 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1387 antconf->main_lna_conf = (regval & AR_PHY_ANT_DIV_MAIN_LNACONF) >>
1388 AR_PHY_ANT_DIV_MAIN_LNACONF_S;
1389 antconf->alt_lna_conf = (regval & AR_PHY_ANT_DIV_ALT_LNACONF) >>
1390 AR_PHY_ANT_DIV_ALT_LNACONF_S;
1391 antconf->fast_div_bias = (regval & AR_PHY_ANT_FAST_DIV_BIAS) >>
1392 AR_PHY_ANT_FAST_DIV_BIAS_S;
1393
1394 if (AR_SREV_9330_11(ah)) {
1395 antconf->lna1_lna2_switch_delta = -1;
1396 antconf->lna1_lna2_delta = -9;
1397 antconf->div_group = 1;
1398 } else if (AR_SREV_9485(ah)) {
1399 antconf->lna1_lna2_switch_delta = -1;
1400 antconf->lna1_lna2_delta = -9;
1401 antconf->div_group = 2;
1402 } else if (AR_SREV_9565(ah)) {
1403 antconf->lna1_lna2_switch_delta = 3;
1404 antconf->lna1_lna2_delta = -9;
1405 antconf->div_group = 3;
1406 } else {
1407 antconf->lna1_lna2_switch_delta = -1;
1408 antconf->lna1_lna2_delta = -3;
1409 antconf->div_group = 0;
1410 }
1411 }
1412
1413 static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah,
1414 struct ath_hw_antcomb_conf *antconf)
1415 {
1416 u32 regval;
1417
1418 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1419 regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1420 AR_PHY_ANT_DIV_ALT_LNACONF |
1421 AR_PHY_ANT_FAST_DIV_BIAS |
1422 AR_PHY_ANT_DIV_MAIN_GAINTB |
1423 AR_PHY_ANT_DIV_ALT_GAINTB);
1424 regval |= ((antconf->main_lna_conf << AR_PHY_ANT_DIV_MAIN_LNACONF_S)
1425 & AR_PHY_ANT_DIV_MAIN_LNACONF);
1426 regval |= ((antconf->alt_lna_conf << AR_PHY_ANT_DIV_ALT_LNACONF_S)
1427 & AR_PHY_ANT_DIV_ALT_LNACONF);
1428 regval |= ((antconf->fast_div_bias << AR_PHY_ANT_FAST_DIV_BIAS_S)
1429 & AR_PHY_ANT_FAST_DIV_BIAS);
1430 regval |= ((antconf->main_gaintb << AR_PHY_ANT_DIV_MAIN_GAINTB_S)
1431 & AR_PHY_ANT_DIV_MAIN_GAINTB);
1432 regval |= ((antconf->alt_gaintb << AR_PHY_ANT_DIV_ALT_GAINTB_S)
1433 & AR_PHY_ANT_DIV_ALT_GAINTB);
1434
1435 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1436 }
1437
1438 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
1439
1440 static void ar9003_hw_set_bt_ant_diversity(struct ath_hw *ah, bool enable)
1441 {
1442 struct ath9k_hw_capabilities *pCap = &ah->caps;
1443 u8 ant_div_ctl1;
1444 u32 regval;
1445
1446 if (!AR_SREV_9485(ah) && !AR_SREV_9565(ah))
1447 return;
1448
1449 if (AR_SREV_9485(ah)) {
1450 regval = ar9003_hw_ant_ctrl_common_2_get(ah,
1451 IS_CHAN_2GHZ(ah->curchan));
1452 if (enable) {
1453 regval &= ~AR_SWITCH_TABLE_COM2_ALL;
1454 regval |= ah->config.ant_ctrl_comm2g_switch_enable;
1455 }
1456 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2,
1457 AR_SWITCH_TABLE_COM2_ALL, regval);
1458 }
1459
1460 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
1461
1462 /*
1463 * Set MAIN/ALT LNA conf.
1464 * Set MAIN/ALT gain_tb.
1465 */
1466 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1467 regval &= (~AR_ANT_DIV_CTRL_ALL);
1468 regval |= (ant_div_ctl1 & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;
1469 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1470
1471 if (AR_SREV_9485_11_OR_LATER(ah)) {
1472 /*
1473 * Enable LNA diversity.
1474 */
1475 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1476 regval &= ~AR_PHY_ANT_DIV_LNADIV;
1477 regval |= ((ant_div_ctl1 >> 6) & 0x1) << AR_PHY_ANT_DIV_LNADIV_S;
1478 if (enable)
1479 regval |= AR_ANT_DIV_ENABLE;
1480
1481 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1482
1483 /*
1484 * Enable fast antenna diversity.
1485 */
1486 regval = REG_READ(ah, AR_PHY_CCK_DETECT);
1487 regval &= ~AR_FAST_DIV_ENABLE;
1488 regval |= ((ant_div_ctl1 >> 7) & 0x1) << AR_FAST_DIV_ENABLE_S;
1489 if (enable)
1490 regval |= AR_FAST_DIV_ENABLE;
1491
1492 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
1493
1494 if (pCap->hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) {
1495 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1496 regval &= (~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1497 AR_PHY_ANT_DIV_ALT_LNACONF |
1498 AR_PHY_ANT_DIV_ALT_GAINTB |
1499 AR_PHY_ANT_DIV_MAIN_GAINTB));
1500 /*
1501 * Set MAIN to LNA1 and ALT to LNA2 at the
1502 * beginning.
1503 */
1504 regval |= (ATH_ANT_DIV_COMB_LNA1 <<
1505 AR_PHY_ANT_DIV_MAIN_LNACONF_S);
1506 regval |= (ATH_ANT_DIV_COMB_LNA2 <<
1507 AR_PHY_ANT_DIV_ALT_LNACONF_S);
1508 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1509 }
1510 } else if (AR_SREV_9565(ah)) {
1511 if (enable) {
1512 REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1513 AR_ANT_DIV_ENABLE);
1514 REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1515 (1 << AR_PHY_ANT_SW_RX_PROT_S));
1516 REG_SET_BIT(ah, AR_PHY_CCK_DETECT,
1517 AR_FAST_DIV_ENABLE);
1518 REG_SET_BIT(ah, AR_PHY_RESTART,
1519 AR_PHY_RESTART_ENABLE_DIV_M2FLAG);
1520 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV,
1521 AR_BTCOEX_WL_LNADIV_FORCE_ON);
1522 } else {
1523 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1524 AR_ANT_DIV_ENABLE);
1525 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1526 (1 << AR_PHY_ANT_SW_RX_PROT_S));
1527 REG_CLR_BIT(ah, AR_PHY_CCK_DETECT,
1528 AR_FAST_DIV_ENABLE);
1529 REG_CLR_BIT(ah, AR_PHY_RESTART,
1530 AR_PHY_RESTART_ENABLE_DIV_M2FLAG);
1531 REG_CLR_BIT(ah, AR_BTCOEX_WL_LNADIV,
1532 AR_BTCOEX_WL_LNADIV_FORCE_ON);
1533
1534 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1535 regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1536 AR_PHY_ANT_DIV_ALT_LNACONF |
1537 AR_PHY_ANT_DIV_MAIN_GAINTB |
1538 AR_PHY_ANT_DIV_ALT_GAINTB);
1539 regval |= (ATH_ANT_DIV_COMB_LNA1 <<
1540 AR_PHY_ANT_DIV_MAIN_LNACONF_S);
1541 regval |= (ATH_ANT_DIV_COMB_LNA2 <<
1542 AR_PHY_ANT_DIV_ALT_LNACONF_S);
1543 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1544 }
1545 }
1546 }
1547
1548 #endif
1549
1550 static int ar9003_hw_fast_chan_change(struct ath_hw *ah,
1551 struct ath9k_channel *chan,
1552 u8 *ini_reloaded)
1553 {
1554 unsigned int regWrites = 0;
1555 u32 modesIndex;
1556
1557 if (IS_CHAN_5GHZ(chan))
1558 modesIndex = IS_CHAN_HT40(chan) ? 2 : 1;
1559 else
1560 modesIndex = IS_CHAN_HT40(chan) ? 3 : 4;
1561
1562 if (modesIndex == ah->modes_index) {
1563 *ini_reloaded = false;
1564 goto set_rfmode;
1565 }
1566
1567 ar9003_hw_prog_ini(ah, &ah->iniSOC[ATH_INI_POST], modesIndex);
1568 ar9003_hw_prog_ini(ah, &ah->iniMac[ATH_INI_POST], modesIndex);
1569 ar9003_hw_prog_ini(ah, &ah->iniBB[ATH_INI_POST], modesIndex);
1570 ar9003_hw_prog_ini(ah, &ah->iniRadio[ATH_INI_POST], modesIndex);
1571
1572 if (AR_SREV_9462_20_OR_LATER(ah))
1573 ar9003_hw_prog_ini(ah, &ah->ini_radio_post_sys2ant,
1574 modesIndex);
1575
1576 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1577
1578 if (AR_SREV_9462_20_OR_LATER(ah)) {
1579 /*
1580 * CUS217 mix LNA mode.
1581 */
1582 if (ar9003_hw_get_rx_gain_idx(ah) == 2) {
1583 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_core,
1584 1, regWrites);
1585 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
1586 modesIndex, regWrites);
1587 }
1588 }
1589
1590 /*
1591 * For 5GHz channels requiring Fast Clock, apply
1592 * different modal values.
1593 */
1594 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1595 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, regWrites);
1596
1597 if (AR_SREV_9565(ah))
1598 REG_WRITE_ARRAY(&ah->iniModesFastClock, 1, regWrites);
1599
1600 /*
1601 * JAPAN regulatory.
1602 */
1603 if (chan->channel == 2484)
1604 ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1);
1605
1606 ah->modes_index = modesIndex;
1607 *ini_reloaded = true;
1608
1609 set_rfmode:
1610 ar9003_hw_set_rfmode(ah, chan);
1611 return 0;
1612 }
1613
1614 static void ar9003_hw_spectral_scan_config(struct ath_hw *ah,
1615 struct ath_spec_scan *param)
1616 {
1617 u8 count;
1618
1619 if (!param->enabled) {
1620 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1621 AR_PHY_SPECTRAL_SCAN_ENABLE);
1622 return;
1623 }
1624
1625 REG_SET_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_FFT_ENA);
1626 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENABLE);
1627
1628 /* on AR93xx and newer, count = 0 will make the the chip send
1629 * spectral samples endlessly. Check if this really was intended,
1630 * and fix otherwise.
1631 */
1632 count = param->count;
1633 if (param->endless)
1634 count = 0;
1635 else if (param->count == 0)
1636 count = 1;
1637
1638 if (param->short_repeat)
1639 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1640 AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT);
1641 else
1642 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1643 AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT);
1644
1645 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1646 AR_PHY_SPECTRAL_SCAN_COUNT, count);
1647 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1648 AR_PHY_SPECTRAL_SCAN_PERIOD, param->period);
1649 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1650 AR_PHY_SPECTRAL_SCAN_FFT_PERIOD, param->fft_period);
1651
1652 return;
1653 }
1654
1655 static void ar9003_hw_spectral_scan_trigger(struct ath_hw *ah)
1656 {
1657 /* Activate spectral scan */
1658 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1659 AR_PHY_SPECTRAL_SCAN_ACTIVE);
1660 }
1661
1662 static void ar9003_hw_spectral_scan_wait(struct ath_hw *ah)
1663 {
1664 struct ath_common *common = ath9k_hw_common(ah);
1665
1666 /* Poll for spectral scan complete */
1667 if (!ath9k_hw_wait(ah, AR_PHY_SPECTRAL_SCAN,
1668 AR_PHY_SPECTRAL_SCAN_ACTIVE,
1669 0, AH_WAIT_TIMEOUT)) {
1670 ath_err(common, "spectral scan wait failed\n");
1671 return;
1672 }
1673 }
1674
1675 static void ar9003_hw_tx99_start(struct ath_hw *ah, u32 qnum)
1676 {
1677 REG_SET_BIT(ah, AR_PHY_TEST, PHY_AGC_CLR);
1678 REG_SET_BIT(ah, 0x9864, 0x7f000);
1679 REG_SET_BIT(ah, 0x9924, 0x7f00fe);
1680 REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
1681 REG_WRITE(ah, AR_CR, AR_CR_RXD);
1682 REG_WRITE(ah, AR_DLCL_IFS(qnum), 0);
1683 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20); /* 50 OK */
1684 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20);
1685 REG_WRITE(ah, AR_TIME_OUT, 0x00000400);
1686 REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff);
1687 REG_SET_BIT(ah, AR_QMISC(qnum), AR_Q_MISC_DCU_EARLY_TERM_REQ);
1688 }
1689
1690 static void ar9003_hw_tx99_stop(struct ath_hw *ah)
1691 {
1692 REG_CLR_BIT(ah, AR_PHY_TEST, PHY_AGC_CLR);
1693 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
1694 }
1695
1696 static void ar9003_hw_tx99_set_txpower(struct ath_hw *ah, u8 txpower)
1697 {
1698 static s16 p_pwr_array[ar9300RateSize] = { 0 };
1699 unsigned int i;
1700
1701 if (txpower <= MAX_RATE_POWER) {
1702 for (i = 0; i < ar9300RateSize; i++)
1703 p_pwr_array[i] = txpower;
1704 } else {
1705 for (i = 0; i < ar9300RateSize; i++)
1706 p_pwr_array[i] = MAX_RATE_POWER;
1707 }
1708
1709 REG_WRITE(ah, 0xa458, 0);
1710
1711 REG_WRITE(ah, 0xa3c0,
1712 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 24) |
1713 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 16) |
1714 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 8) |
1715 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 0));
1716 REG_WRITE(ah, 0xa3c4,
1717 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_54], 24) |
1718 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_48], 16) |
1719 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_36], 8) |
1720 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 0));
1721 REG_WRITE(ah, 0xa3c8,
1722 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 24) |
1723 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 16) |
1724 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 0));
1725 REG_WRITE(ah, 0xa3cc,
1726 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_11S], 24) |
1727 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_11L], 16) |
1728 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_5S], 8) |
1729 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 0));
1730 REG_WRITE(ah, 0xa3d0,
1731 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_5], 24) |
1732 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_4], 16) |
1733 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_1_3_9_11_17_19], 8)|
1734 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_0_8_16], 0));
1735 REG_WRITE(ah, 0xa3d4,
1736 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_13], 24) |
1737 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_12], 16) |
1738 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_7], 8) |
1739 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_6], 0));
1740 REG_WRITE(ah, 0xa3e4,
1741 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_21], 24) |
1742 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_20], 16) |
1743 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_15], 8) |
1744 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_14], 0));
1745 REG_WRITE(ah, 0xa3e8,
1746 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_23], 24) |
1747 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_22], 16) |
1748 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_23], 8) |
1749 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_22], 0));
1750 REG_WRITE(ah, 0xa3d8,
1751 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_5], 24) |
1752 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_4], 16) |
1753 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_1_3_9_11_17_19], 8) |
1754 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_0_8_16], 0));
1755 REG_WRITE(ah, 0xa3dc,
1756 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_13], 24) |
1757 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_12], 16) |
1758 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_7], 8) |
1759 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_6], 0));
1760 REG_WRITE(ah, 0xa3ec,
1761 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_21], 24) |
1762 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_20], 16) |
1763 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_15], 8) |
1764 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_14], 0));
1765 }
1766
1767 void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
1768 {
1769 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1770 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
1771 static const u32 ar9300_cca_regs[6] = {
1772 AR_PHY_CCA_0,
1773 AR_PHY_CCA_1,
1774 AR_PHY_CCA_2,
1775 AR_PHY_EXT_CCA,
1776 AR_PHY_EXT_CCA_1,
1777 AR_PHY_EXT_CCA_2,
1778 };
1779
1780 priv_ops->rf_set_freq = ar9003_hw_set_channel;
1781 priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
1782 priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
1783 priv_ops->set_channel_regs = ar9003_hw_set_channel_regs;
1784 priv_ops->init_bb = ar9003_hw_init_bb;
1785 priv_ops->process_ini = ar9003_hw_process_ini;
1786 priv_ops->set_rfmode = ar9003_hw_set_rfmode;
1787 priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive;
1788 priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
1789 priv_ops->rfbus_req = ar9003_hw_rfbus_req;
1790 priv_ops->rfbus_done = ar9003_hw_rfbus_done;
1791 priv_ops->ani_control = ar9003_hw_ani_control;
1792 priv_ops->do_getnf = ar9003_hw_do_getnf;
1793 priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
1794 priv_ops->set_radar_params = ar9003_hw_set_radar_params;
1795 priv_ops->fast_chan_change = ar9003_hw_fast_chan_change;
1796
1797 ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get;
1798 ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set;
1799 ops->spectral_scan_config = ar9003_hw_spectral_scan_config;
1800 ops->spectral_scan_trigger = ar9003_hw_spectral_scan_trigger;
1801 ops->spectral_scan_wait = ar9003_hw_spectral_scan_wait;
1802
1803 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
1804 ops->set_bt_ant_diversity = ar9003_hw_set_bt_ant_diversity;
1805 #endif
1806 ops->tx99_start = ar9003_hw_tx99_start;
1807 ops->tx99_stop = ar9003_hw_tx99_stop;
1808 ops->tx99_set_txpower = ar9003_hw_tx99_set_txpower;
1809
1810 ar9003_hw_set_nf_limits(ah);
1811 ar9003_hw_set_radar_conf(ah);
1812 memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs));
1813 }
1814
1815 /*
1816 * Baseband Watchdog signatures:
1817 *
1818 * 0x04000539: BB hang when operating in HT40 DFS Channel.
1819 * Full chip reset is not required, but a recovery
1820 * mechanism is needed.
1821 *
1822 * 0x1300000a: Related to CAC deafness.
1823 * Chip reset is not required.
1824 *
1825 * 0x0400000a: Related to CAC deafness.
1826 * Full chip reset is required.
1827 *
1828 * 0x04000b09: RX state machine gets into an illegal state
1829 * when a packet with unsupported rate is received.
1830 * Full chip reset is required and PHY_RESTART has
1831 * to be disabled.
1832 *
1833 * 0x04000409: Packet stuck on receive.
1834 * Full chip reset is required for all chips except AR9340.
1835 */
1836
1837 /*
1838 * ar9003_hw_bb_watchdog_check(): Returns true if a chip reset is required.
1839 */
1840 bool ar9003_hw_bb_watchdog_check(struct ath_hw *ah)
1841 {
1842 u32 val;
1843
1844 switch(ah->bb_watchdog_last_status) {
1845 case 0x04000539:
1846 val = REG_READ(ah, AR_PHY_RADAR_0);
1847 val &= (~AR_PHY_RADAR_0_FIRPWR);
1848 val |= SM(0x7f, AR_PHY_RADAR_0_FIRPWR);
1849 REG_WRITE(ah, AR_PHY_RADAR_0, val);
1850 udelay(1);
1851 val = REG_READ(ah, AR_PHY_RADAR_0);
1852 val &= ~AR_PHY_RADAR_0_FIRPWR;
1853 val |= SM(AR9300_DFS_FIRPWR, AR_PHY_RADAR_0_FIRPWR);
1854 REG_WRITE(ah, AR_PHY_RADAR_0, val);
1855
1856 return false;
1857 case 0x1300000a:
1858 return false;
1859 case 0x0400000a:
1860 case 0x04000b09:
1861 return true;
1862 case 0x04000409:
1863 if (AR_SREV_9340(ah) || AR_SREV_9531(ah))
1864 return false;
1865 else
1866 return true;
1867 default:
1868 /*
1869 * For any other unknown signatures, do a
1870 * full chip reset.
1871 */
1872 return true;
1873 }
1874 }
1875 EXPORT_SYMBOL(ar9003_hw_bb_watchdog_check);
1876
1877 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah)
1878 {
1879 struct ath_common *common = ath9k_hw_common(ah);
1880 u32 idle_tmo_ms = ah->bb_watchdog_timeout_ms;
1881 u32 val, idle_count;
1882
1883 if (!idle_tmo_ms) {
1884 /* disable IRQ, disable chip-reset for BB panic */
1885 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1886 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) &
1887 ~(AR_PHY_WATCHDOG_RST_ENABLE |
1888 AR_PHY_WATCHDOG_IRQ_ENABLE));
1889
1890 /* disable watchdog in non-IDLE mode, disable in IDLE mode */
1891 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1892 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1) &
1893 ~(AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1894 AR_PHY_WATCHDOG_IDLE_ENABLE));
1895
1896 ath_dbg(common, RESET, "Disabled BB Watchdog\n");
1897 return;
1898 }
1899
1900 /* enable IRQ, disable chip-reset for BB watchdog */
1901 val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK;
1902 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1903 (val | AR_PHY_WATCHDOG_IRQ_ENABLE) &
1904 ~AR_PHY_WATCHDOG_RST_ENABLE);
1905
1906 /* bound limit to 10 secs */
1907 if (idle_tmo_ms > 10000)
1908 idle_tmo_ms = 10000;
1909
1910 /*
1911 * The time unit for watchdog event is 2^15 44/88MHz cycles.
1912 *
1913 * For HT20 we have a time unit of 2^15/44 MHz = .74 ms per tick
1914 * For HT40 we have a time unit of 2^15/88 MHz = .37 ms per tick
1915 *
1916 * Given we use fast clock now in 5 GHz, these time units should
1917 * be common for both 2 GHz and 5 GHz.
1918 */
1919 idle_count = (100 * idle_tmo_ms) / 74;
1920 if (ah->curchan && IS_CHAN_HT40(ah->curchan))
1921 idle_count = (100 * idle_tmo_ms) / 37;
1922
1923 /*
1924 * enable watchdog in non-IDLE mode, disable in IDLE mode,
1925 * set idle time-out.
1926 */
1927 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1928 AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1929 AR_PHY_WATCHDOG_IDLE_MASK |
1930 (AR_PHY_WATCHDOG_NON_IDLE_MASK & (idle_count << 2)));
1931
1932 ath_dbg(common, RESET, "Enabled BB Watchdog timeout (%u ms)\n",
1933 idle_tmo_ms);
1934 }
1935
1936 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah)
1937 {
1938 /*
1939 * we want to avoid printing in ISR context so we save the
1940 * watchdog status to be printed later in bottom half context.
1941 */
1942 ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS);
1943
1944 /*
1945 * the watchdog timer should reset on status read but to be sure
1946 * sure we write 0 to the watchdog status bit.
1947 */
1948 REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS,
1949 ah->bb_watchdog_last_status & ~AR_PHY_WATCHDOG_STATUS_CLR);
1950 }
1951
1952 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah)
1953 {
1954 struct ath_common *common = ath9k_hw_common(ah);
1955 u32 status;
1956
1957 if (likely(!(common->debug_mask & ATH_DBG_RESET)))
1958 return;
1959
1960 status = ah->bb_watchdog_last_status;
1961 ath_dbg(common, RESET,
1962 "\n==== BB update: BB status=0x%08x ====\n", status);
1963 ath_dbg(common, RESET,
1964 "** BB state: wd=%u det=%u rdar=%u rOFDM=%d rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n",
1965 MS(status, AR_PHY_WATCHDOG_INFO),
1966 MS(status, AR_PHY_WATCHDOG_DET_HANG),
1967 MS(status, AR_PHY_WATCHDOG_RADAR_SM),
1968 MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM),
1969 MS(status, AR_PHY_WATCHDOG_RX_CCK_SM),
1970 MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM),
1971 MS(status, AR_PHY_WATCHDOG_TX_CCK_SM),
1972 MS(status, AR_PHY_WATCHDOG_AGC_SM),
1973 MS(status, AR_PHY_WATCHDOG_SRCH_SM));
1974
1975 ath_dbg(common, RESET, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",
1976 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1),
1977 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2));
1978 ath_dbg(common, RESET, "** BB mode: BB_gen_controls=0x%08x **\n",
1979 REG_READ(ah, AR_PHY_GEN_CTRL));
1980
1981 #define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles)
1982 if (common->cc_survey.cycles)
1983 ath_dbg(common, RESET,
1984 "** BB busy times: rx_clear=%d%%, rx_frame=%d%%, tx_frame=%d%% **\n",
1985 PCT(rx_busy), PCT(rx_frame), PCT(tx_frame));
1986
1987 ath_dbg(common, RESET, "==== BB update: done ====\n\n");
1988 }
1989 EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info);
1990
1991 void ar9003_hw_disable_phy_restart(struct ath_hw *ah)
1992 {
1993 u8 result;
1994 u32 val;
1995
1996 /* While receiving unsupported rate frame rx state machine
1997 * gets into a state 0xb and if phy_restart happens in that
1998 * state, BB would go hang. If RXSM is in 0xb state after
1999 * first bb panic, ensure to disable the phy_restart.
2000 */
2001 result = MS(ah->bb_watchdog_last_status, AR_PHY_WATCHDOG_RX_OFDM_SM);
2002
2003 if ((result == 0xb) || ah->bb_hang_rx_ofdm) {
2004 ah->bb_hang_rx_ofdm = true;
2005 val = REG_READ(ah, AR_PHY_RESTART);
2006 val &= ~AR_PHY_RESTART_ENA;
2007 REG_WRITE(ah, AR_PHY_RESTART, val);
2008 }
2009 }
2010 EXPORT_SYMBOL(ar9003_hw_disable_phy_restart);
Linux kernel - Deliverables
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