drivers/net/wireless/ath/ath9k/ar9003_rtt.c

   1 /*
   2  * Copyright (c) 2010-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include "hw.h"
  18 #include "ar9003_phy.h"
  19
  20 #define RTT_RESTORE_TIMEOUT          1000
  21 #define RTT_ACCESS_TIMEOUT           100
  22 #define RTT_BAD_VALUE                0x0bad0bad
  23
  24 /*
  25  * RTT (Radio Retention Table) hardware implementation information
  26  *
  27  * There is an internal table (i.e. the rtt) for each chain (or bank).
  28  * Each table contains 6 entries and each entry is corresponding to
  29  * a specific calibration parameter as depicted below.
  30  *  0~2 - DC offset DAC calibration: loop, low, high (offsetI/Q_...)
  31  *  3   - Filter cal (filterfc)
  32  *  4   - RX gain settings
  33  *  5   - Peak detector offset calibration (agc_caldac)
  34  */
  35
  36 void ar9003_hw_rtt_enable(struct ath_hw *ah)
  37 {
  38         REG_WRITE(ah, AR_PHY_RTT_CTRL, 1);
  39 }
  40
  41 void ar9003_hw_rtt_disable(struct ath_hw *ah)
  42 {
  43         REG_WRITE(ah, AR_PHY_RTT_CTRL, 0);
  44 }
  45
  46 void ar9003_hw_rtt_set_mask(struct ath_hw *ah, u32 rtt_mask)
  47 {
  48         REG_RMW_FIELD(ah, AR_PHY_RTT_CTRL,
  49                       AR_PHY_RTT_CTRL_RESTORE_MASK, rtt_mask);
  50 }
  51
  52 bool ar9003_hw_rtt_force_restore(struct ath_hw *ah)
  53 {
  54         if (!ath9k_hw_wait(ah, AR_PHY_RTT_CTRL,
  55                            AR_PHY_RTT_CTRL_FORCE_RADIO_RESTORE,
  56                            0, RTT_RESTORE_TIMEOUT))
  57                 return false;
  58
  59         REG_RMW_FIELD(ah, AR_PHY_RTT_CTRL,
  60                       AR_PHY_RTT_CTRL_FORCE_RADIO_RESTORE, 1);
  61
  62         if (!ath9k_hw_wait(ah, AR_PHY_RTT_CTRL,
  63                            AR_PHY_RTT_CTRL_FORCE_RADIO_RESTORE,
  64                            0, RTT_RESTORE_TIMEOUT))
  65                 return false;
  66
  67         return true;
  68 }
  69
  70 static void ar9003_hw_rtt_load_hist_entry(struct ath_hw *ah, u8 chain,
  71                 u32 index, u32 data28)
  72 {
  73         u32 val;
  74
  75         val = SM(data28, AR_PHY_RTT_SW_RTT_TABLE_DATA);
  76         REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_1_B(chain), val);
  77
  78         val = SM(0, AR_PHY_RTT_SW_RTT_TABLE_ACCESS) |
  79               SM(1, AR_PHY_RTT_SW_RTT_TABLE_WRITE) |
  80               SM(index, AR_PHY_RTT_SW_RTT_TABLE_ADDR);
  81         REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val);
  82         udelay(1);
  83
  84         val |= SM(1, AR_PHY_RTT_SW_RTT_TABLE_ACCESS);
  85         REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val);
  86         udelay(1);
  87
  88         if (!ath9k_hw_wait(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain),
  89                            AR_PHY_RTT_SW_RTT_TABLE_ACCESS, 0,
  90                            RTT_ACCESS_TIMEOUT))
  91                 return;
  92
  93         val &= ~SM(1, AR_PHY_RTT_SW_RTT_TABLE_WRITE);
  94         REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val);
  95         udelay(1);
  96
  97         ath9k_hw_wait(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain),
  98                       AR_PHY_RTT_SW_RTT_TABLE_ACCESS, 0,
  99                       RTT_ACCESS_TIMEOUT);
 100 }
 101
 102 void ar9003_hw_rtt_load_hist(struct ath_hw *ah, u8 chain, u32 *table)
 103 {
 104         int i;
 105
 106         for (i = 0; i < MAX_RTT_TABLE_ENTRY; i++)
 107                 ar9003_hw_rtt_load_hist_entry(ah, chain, i, table[i]);
 108 }
 109
 110 static int ar9003_hw_rtt_fill_hist_entry(struct ath_hw *ah, u8 chain, u32 index)
 111 {
 112         u32 val;
 113
 114         val = SM(0, AR_PHY_RTT_SW_RTT_TABLE_ACCESS) |
 115               SM(0, AR_PHY_RTT_SW_RTT_TABLE_WRITE) |
 116               SM(index, AR_PHY_RTT_SW_RTT_TABLE_ADDR);
 117
 118         REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val);
 119         udelay(1);
 120
 121         val |= SM(1, AR_PHY_RTT_SW_RTT_TABLE_ACCESS);
 122         REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val);
 123         udelay(1);
 124
 125         if (!ath9k_hw_wait(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain),
 126                            AR_PHY_RTT_SW_RTT_TABLE_ACCESS, 0,
 127                            RTT_ACCESS_TIMEOUT))
 128                 return RTT_BAD_VALUE;
 129
 130         val = REG_READ(ah, AR_PHY_RTT_TABLE_SW_INTF_1_B(chain));
 131
 132         return val;
 133 }
 134
 135 void ar9003_hw_rtt_fill_hist(struct ath_hw *ah, u8 chain, u32 *table)
 136 {
 137         int i;
 138
 139         for (i = 0; i < MAX_RTT_TABLE_ENTRY; i++)
 140                 table[i] = ar9003_hw_rtt_fill_hist_entry(ah, chain, i);
 141 }
 142
 143 void ar9003_hw_rtt_clear_hist(struct ath_hw *ah)
 144 {
 145         int i, j;
 146
 147         for (i = 0; i < AR9300_MAX_CHAINS; i++) {
 148                 if (!(ah->rxchainmask & (1 << i)))
 149                         continue;
 150                 for (j = 0; j < MAX_RTT_TABLE_ENTRY; j++)
 151                         ar9003_hw_rtt_load_hist_entry(ah, i, j, 0);
 152         }
 153 }