2 * Copyright (c) 2012 Qualcomm Atheros, Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/export.h>
23 static void ath9k_hw_set_powermode_wow_sleep(struct ath_hw
*ah
)
25 struct ath_common
*common
= ath9k_hw_common(ah
);
27 REG_SET_BIT(ah
, AR_STA_ID1
, AR_STA_ID1_PWR_SAV
);
29 /* set rx disable bit */
30 REG_WRITE(ah
, AR_CR
, AR_CR_RXD
);
32 if (!ath9k_hw_wait(ah
, AR_CR
, AR_CR_RXE
, 0, AH_WAIT_TIMEOUT
)) {
33 ath_err(common
, "Failed to stop Rx DMA in 10ms AR_CR=0x%08x AR_DIAG_SW=0x%08x\n",
34 REG_READ(ah
, AR_CR
), REG_READ(ah
, AR_DIAG_SW
));
38 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
, AR_RTC_FORCE_WAKE_ON_INT
);
41 static void ath9k_wow_create_keep_alive_pattern(struct ath_hw
*ah
)
43 struct ath_common
*common
= ath9k_hw_common(ah
);
44 u8 sta_mac_addr
[ETH_ALEN
], ap_mac_addr
[ETH_ALEN
];
46 u32 data_word
[KAL_NUM_DATA_WORDS
];
48 u32 wow_ka_data_word0
;
50 memcpy(sta_mac_addr
, common
->macaddr
, ETH_ALEN
);
51 memcpy(ap_mac_addr
, common
->curbssid
, ETH_ALEN
);
53 /* set the transmit buffer */
54 ctl
[0] = (KAL_FRAME_LEN
| (MAX_RATE_POWER
<< 16));
56 ctl
[3] = 0xb; /* OFDM_6M hardware value for this rate */
58 ctl
[7] = (ah
->txchainmask
) << 2;
59 ctl
[2] = 0xf << 16; /* tx_tries 0 */
61 for (i
= 0; i
< KAL_NUM_DESC_WORDS
; i
++)
62 REG_WRITE(ah
, (AR_WOW_KA_DESC_WORD2
+ i
* 4), ctl
[i
]);
64 REG_WRITE(ah
, (AR_WOW_KA_DESC_WORD2
+ i
* 4), ctl
[i
]);
66 data_word
[0] = (KAL_FRAME_TYPE
<< 2) | (KAL_FRAME_SUB_TYPE
<< 4) |
67 (KAL_TO_DS
<< 8) | (KAL_DURATION_ID
<< 16);
68 data_word
[1] = (ap_mac_addr
[3] << 24) | (ap_mac_addr
[2] << 16) |
69 (ap_mac_addr
[1] << 8) | (ap_mac_addr
[0]);
70 data_word
[2] = (sta_mac_addr
[1] << 24) | (sta_mac_addr
[0] << 16) |
71 (ap_mac_addr
[5] << 8) | (ap_mac_addr
[4]);
72 data_word
[3] = (sta_mac_addr
[5] << 24) | (sta_mac_addr
[4] << 16) |
73 (sta_mac_addr
[3] << 8) | (sta_mac_addr
[2]);
74 data_word
[4] = (ap_mac_addr
[3] << 24) | (ap_mac_addr
[2] << 16) |
75 (ap_mac_addr
[1] << 8) | (ap_mac_addr
[0]);
76 data_word
[5] = (ap_mac_addr
[5] << 8) | (ap_mac_addr
[4]);
78 if (AR_SREV_9462_20(ah
)) {
79 /* AR9462 2.0 has an extra descriptor word (time based
80 * discard) compared to other chips */
81 REG_WRITE(ah
, (AR_WOW_KA_DESC_WORD2
+ (12 * 4)), 0);
82 wow_ka_data_word0
= AR_WOW_TXBUF(13);
84 wow_ka_data_word0
= AR_WOW_TXBUF(12);
87 for (i
= 0; i
< KAL_NUM_DATA_WORDS
; i
++)
88 REG_WRITE(ah
, (wow_ka_data_word0
+ i
*4), data_word
[i
]);
92 int ath9k_hw_wow_apply_pattern(struct ath_hw
*ah
, u8
*user_pattern
,
93 u8
*user_mask
, int pattern_count
,
97 u32 pattern_val
, mask_val
;
100 if (pattern_count
>= ah
->wow
.max_patterns
)
103 if (pattern_count
< MAX_NUM_PATTERN_LEGACY
)
104 REG_SET_BIT(ah
, AR_WOW_PATTERN
, BIT(pattern_count
));
106 REG_SET_BIT(ah
, AR_MAC_PCU_WOW4
, BIT(pattern_count
- 8));
108 for (i
= 0; i
< MAX_PATTERN_SIZE
; i
+= 4) {
109 memcpy(&pattern_val
, user_pattern
, 4);
110 REG_WRITE(ah
, (AR_WOW_TB_PATTERN(pattern_count
) + i
),
115 for (i
= 0; i
< MAX_PATTERN_MASK_SIZE
; i
+= 4) {
116 memcpy(&mask_val
, user_mask
, 4);
117 REG_WRITE(ah
, (AR_WOW_TB_MASK(pattern_count
) + i
), mask_val
);
121 if (pattern_count
< MAX_NUM_PATTERN_LEGACY
)
122 ah
->wow
.wow_event_mask
|=
123 BIT(pattern_count
+ AR_WOW_PAT_FOUND_SHIFT
);
125 ah
->wow
.wow_event_mask2
|=
126 BIT((pattern_count
- 8) + AR_WOW_PAT_FOUND_SHIFT
);
128 if (pattern_count
< 4) {
129 set
= (pattern_len
& AR_WOW_LENGTH_MAX
) <<
130 AR_WOW_LEN1_SHIFT(pattern_count
);
131 clr
= AR_WOW_LENGTH1_MASK(pattern_count
);
132 REG_RMW(ah
, AR_WOW_LENGTH1
, set
, clr
);
133 } else if (pattern_count
< 8) {
134 set
= (pattern_len
& AR_WOW_LENGTH_MAX
) <<
135 AR_WOW_LEN2_SHIFT(pattern_count
);
136 clr
= AR_WOW_LENGTH2_MASK(pattern_count
);
137 REG_RMW(ah
, AR_WOW_LENGTH2
, set
, clr
);
138 } else if (pattern_count
< 12) {
139 set
= (pattern_len
& AR_WOW_LENGTH_MAX
) <<
140 AR_WOW_LEN3_SHIFT(pattern_count
);
141 clr
= AR_WOW_LENGTH3_MASK(pattern_count
);
142 REG_RMW(ah
, AR_WOW_LENGTH3
, set
, clr
);
143 } else if (pattern_count
< MAX_NUM_PATTERN
) {
144 set
= (pattern_len
& AR_WOW_LENGTH_MAX
) <<
145 AR_WOW_LEN4_SHIFT(pattern_count
);
146 clr
= AR_WOW_LENGTH4_MASK(pattern_count
);
147 REG_RMW(ah
, AR_WOW_LENGTH4
, set
, clr
);
152 EXPORT_SYMBOL(ath9k_hw_wow_apply_pattern
);
154 u32
ath9k_hw_wow_wakeup(struct ath_hw
*ah
)
160 * read the WoW status register to know
163 rval
= REG_READ(ah
, AR_WOW_PATTERN
);
164 val
= AR_WOW_STATUS(rval
);
167 * mask only the WoW events that we have enabled. Sometimes
168 * we have spurious WoW events from the AR_WOW_PATTERN
169 * register. This mask will clean it up.
172 val
&= ah
->wow
.wow_event_mask
;
175 if (val
& AR_WOW_MAGIC_PAT_FOUND
)
176 wow_status
|= AH_WOW_MAGIC_PATTERN_EN
;
177 if (AR_WOW_PATTERN_FOUND(val
))
178 wow_status
|= AH_WOW_USER_PATTERN_EN
;
179 if (val
& AR_WOW_KEEP_ALIVE_FAIL
)
180 wow_status
|= AH_WOW_LINK_CHANGE
;
181 if (val
& AR_WOW_BEACON_FAIL
)
182 wow_status
|= AH_WOW_BEACON_MISS
;
186 * set and clear WOW_PME_CLEAR registers for the chip to
187 * generate next wow signal.
188 * disable D3 before accessing other registers ?
191 /* do we need to check the bit value 0x01000000 (7-10) ?? */
192 REG_RMW(ah
, AR_PCIE_PM_CTRL
, AR_PMCTRL_WOW_PME_CLR
,
193 AR_PMCTRL_PWR_STATE_D1D3
);
198 REG_WRITE(ah
, AR_WOW_PATTERN
,
199 AR_WOW_CLEAR_EVENTS(REG_READ(ah
, AR_WOW_PATTERN
)));
202 * restore the beacon threshold to init value
204 REG_WRITE(ah
, AR_RSSI_THR
, INIT_RSSI_THR
);
207 * Restore the way the PCI-E reset, Power-On-Reset, external
208 * PCIE_POR_SHORT pins are tied to its original value.
209 * Previously just before WoW sleep, we untie the PCI-E
210 * reset to our Chip's Power On Reset so that any PCI-E
211 * reset from the bus will not reset our chip
213 if (ah
->is_pciexpress
)
214 ath9k_hw_configpcipowersave(ah
, false);
216 ah
->wow
.wow_event_mask
= 0;
220 EXPORT_SYMBOL(ath9k_hw_wow_wakeup
);
222 static void ath9k_hw_wow_set_arwr_reg(struct ath_hw
*ah
)
226 if (!ah
->is_pciexpress
)
230 * We need to untie the internal POR (power-on-reset)
231 * to the external PCI-E reset. We also need to tie
232 * the PCI-E Phy reset to the PCI-E reset.
234 wa_reg
= REG_READ(ah
, AR_WA
);
235 wa_reg
&= ~AR_WA_UNTIE_RESET_EN
;
236 wa_reg
|= AR_WA_RESET_EN
;
237 wa_reg
|= AR_WA_POR_SHORT
;
239 REG_WRITE(ah
, AR_WA
, wa_reg
);
242 void ath9k_hw_wow_enable(struct ath_hw
*ah
, u32 pattern_enable
)
245 u32 keep_alive
, magic_pattern
, host_pm_ctrl
;
247 wow_event_mask
= ah
->wow
.wow_event_mask
;
250 * AR_PMCTRL_HOST_PME_EN - Override PME enable in configuration
251 * space and allow MAC to generate WoW anyway.
253 * AR_PMCTRL_PWR_PM_CTRL_ENA - ???
255 * AR_PMCTRL_AUX_PWR_DET - PCI core SYS_AUX_PWR_DET signal,
256 * needs to be set for WoW in PCI mode.
258 * AR_PMCTRL_WOW_PME_CLR - WoW Clear Signal going to the MAC.
260 * Set the power states appropriately and enable PME.
262 * Set and clear WOW_PME_CLEAR for the chip
263 * to generate next wow signal.
265 REG_SET_BIT(ah
, AR_PCIE_PM_CTRL
, AR_PMCTRL_HOST_PME_EN
|
266 AR_PMCTRL_PWR_PM_CTRL_ENA
|
267 AR_PMCTRL_AUX_PWR_DET
|
268 AR_PMCTRL_WOW_PME_CLR
);
269 REG_CLR_BIT(ah
, AR_PCIE_PM_CTRL
, AR_PMCTRL_WOW_PME_CLR
);
274 * 31:28 in AR_WOW_PATTERN : Indicates the number of bits used in the
275 * contention window. For value N,
276 * the random backoff will be selected between
279 REG_SET_BIT(ah
, AR_WOW_PATTERN
,
280 AR_WOW_BACK_OFF_SHIFT(AR_WOW_PAT_BACKOFF
));
283 * AIFS time, Slot time, Keep Alive count.
285 REG_SET_BIT(ah
, AR_WOW_COUNT
, AR_WOW_AIFS_CNT(AR_WOW_CNT_AIFS_CNT
) |
286 AR_WOW_SLOT_CNT(AR_WOW_CNT_SLOT_CNT
) |
287 AR_WOW_KEEP_ALIVE_CNT(AR_WOW_CNT_KA_CNT
));
291 if (pattern_enable
& AH_WOW_BEACON_MISS
)
292 REG_WRITE(ah
, AR_WOW_BCN_TIMO
, AR_WOW_BEACON_TIMO
);
294 REG_WRITE(ah
, AR_WOW_BCN_TIMO
, AR_WOW_BEACON_TIMO_MAX
);
297 * Keep alive timeout in ms.
300 REG_WRITE(ah
, AR_WOW_KEEP_ALIVE_TIMO
, AR_WOW_KEEP_ALIVE_NEVER
);
302 REG_WRITE(ah
, AR_WOW_KEEP_ALIVE_TIMO
, KAL_TIMEOUT
* 32);
305 * Keep alive delay in us.
307 REG_WRITE(ah
, AR_WOW_KEEP_ALIVE_DELAY
, KAL_DELAY
* 1000);
310 * Create keep alive pattern to respond to beacons.
312 ath9k_wow_create_keep_alive_pattern(ah
);
315 * Configure keep alive register.
317 keep_alive
= REG_READ(ah
, AR_WOW_KEEP_ALIVE
);
319 /* Send keep alive timeouts anyway */
320 keep_alive
&= ~AR_WOW_KEEP_ALIVE_AUTO_DIS
;
322 if (pattern_enable
& AH_WOW_LINK_CHANGE
) {
323 keep_alive
&= ~AR_WOW_KEEP_ALIVE_FAIL_DIS
;
324 wow_event_mask
|= AR_WOW_KEEP_ALIVE_FAIL
;
326 keep_alive
|= AR_WOW_KEEP_ALIVE_FAIL_DIS
;
329 REG_WRITE(ah
, AR_WOW_KEEP_ALIVE
, keep_alive
);
332 * We are relying on a bmiss failure, ensure we have
333 * enough threshold to prevent false positives.
335 REG_RMW_FIELD(ah
, AR_RSSI_THR
, AR_RSSI_THR_BM_THR
,
336 AR_WOW_BMISSTHRESHOLD
);
338 if (pattern_enable
& AH_WOW_BEACON_MISS
) {
339 wow_event_mask
|= AR_WOW_BEACON_FAIL
;
340 REG_SET_BIT(ah
, AR_WOW_BCN_EN
, AR_WOW_BEACON_FAIL_EN
);
342 REG_CLR_BIT(ah
, AR_WOW_BCN_EN
, AR_WOW_BEACON_FAIL_EN
);
346 * Enable the magic packet registers.
348 magic_pattern
= REG_READ(ah
, AR_WOW_PATTERN
);
349 magic_pattern
|= AR_WOW_MAC_INTR_EN
;
351 if (pattern_enable
& AH_WOW_MAGIC_PATTERN_EN
) {
352 magic_pattern
|= AR_WOW_MAGIC_EN
;
353 wow_event_mask
|= AR_WOW_MAGIC_PAT_FOUND
;
355 magic_pattern
&= ~AR_WOW_MAGIC_EN
;
358 REG_WRITE(ah
, AR_WOW_PATTERN
, magic_pattern
);
361 * Enable pattern matching for packets which are less
364 REG_WRITE(ah
, AR_WOW_PATTERN_MATCH_LT_256B
,
365 AR_WOW_PATTERN_SUPPORTED
);
368 * Set the power states appropriately and enable PME.
370 host_pm_ctrl
= REG_READ(ah
, AR_PCIE_PM_CTRL
);
371 host_pm_ctrl
|= AR_PMCTRL_PWR_STATE_D1D3
|
372 AR_PMCTRL_HOST_PME_EN
|
373 AR_PMCTRL_PWR_PM_CTRL_ENA
;
374 host_pm_ctrl
&= ~AR_PCIE_PM_CTRL_ENA
;
376 if (AR_SREV_9462(ah
)) {
378 * This is needed to prevent the chip waking up
379 * the host within 3-4 seconds with certain
382 host_pm_ctrl
&= ~AR_PMCTRL_PWR_STATE_D1D3
;
383 host_pm_ctrl
|= AR_PMCTRL_PWR_STATE_D1D3_REAL
;
386 REG_WRITE(ah
, AR_PCIE_PM_CTRL
, host_pm_ctrl
);
389 * Enable sequence number generation when asleep.
391 REG_CLR_BIT(ah
, AR_STA_ID1
, AR_STA_ID1_PRESERVE_SEQNUM
);
393 /* To bring down WOW power low margin */
394 REG_SET_BIT(ah
, AR_PCIE_PHY_REG3
, BIT(13));
396 ath9k_hw_wow_set_arwr_reg(ah
);
399 REG_CLR_BIT(ah
, AR_PCU_MISC_MODE3
, BIT(5));
401 ath9k_hw_set_powermode_wow_sleep(ah
);
402 ah
->wow
.wow_event_mask
= wow_event_mask
;
404 EXPORT_SYMBOL(ath9k_hw_wow_enable
);